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Zorro-LAN-IDE/Logic/LAN_IDE/_xmsgs/taengine.xmsgs
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<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin &apos;LAN_INT_ENABLE.CLKF&apos; has multiple original clock nets &apos;C1&apos; &apos;C3&apos;
</msg>
<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin &apos;AUTO_CONFIG_DONE&lt;1&gt;.CLKF&apos; has multiple original clock nets &apos;C1&apos; &apos;C3&apos;
</msg>
<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin &apos;AUTO_CONFIG_DONE&lt;0&gt;.CLKF&apos; has multiple original clock nets &apos;C1&apos; &apos;C3&apos;
</msg>
<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin &apos;AUTO_CONFIG_DONE_CYCLE&lt;0&gt;.CLKF&apos; has multiple original clock nets &apos;C1&apos; &apos;C3&apos;
</msg>
<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin &apos;AUTO_CONFIG_DONE_CYCLE&lt;1&gt;.CLKF&apos; has multiple original clock nets &apos;C1&apos; &apos;C3&apos;
</msg>
<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin &apos;SHUT_UP&lt;0&gt;.CLKF&apos; has multiple original clock nets &apos;C1&apos; &apos;C3&apos;
</msg>
<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin &apos;SHUT_UP&lt;1&gt;.CLKF&apos; has multiple original clock nets &apos;C1&apos; &apos;C3&apos;
</msg>
<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin &apos;SHUT_UP&lt;2&gt;.CLKF&apos; has multiple original clock nets &apos;C1&apos; &apos;C3&apos;
</msg>
<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin &apos;IDE_ENABLE.CLKF&apos; has multiple original clock nets &apos;C1&apos; &apos;C3&apos;
</msg>
<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin &apos;CP_BASEADR&lt;0&gt;.CLKF&apos; has multiple original clock nets &apos;C1&apos; &apos;C3&apos;
</msg>
<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin &apos;CP_BASEADR&lt;1&gt;.CLKF&apos; has multiple original clock nets &apos;C1&apos; &apos;C3&apos;
</msg>
<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin &apos;CP_BASEADR&lt;2&gt;.CLKF&apos; has multiple original clock nets &apos;C1&apos; &apos;C3&apos;
</msg>
<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin &apos;CP_BASEADR&lt;3&gt;.CLKF&apos; has multiple original clock nets &apos;C1&apos; &apos;C3&apos;
</msg>
<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin &apos;CP_BASEADR&lt;4&gt;.CLKF&apos; has multiple original clock nets &apos;C1&apos; &apos;C3&apos;
</msg>
<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin &apos;CP_BASEADR&lt;5&gt;.CLKF&apos; has multiple original clock nets &apos;C1&apos; &apos;C3&apos;
</msg>
<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin &apos;CP_BASEADR&lt;6&gt;.CLKF&apos; has multiple original clock nets &apos;C1&apos; &apos;C3&apos;
</msg>
<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin &apos;CP_BASEADR&lt;7&gt;.CLKF&apos; has multiple original clock nets &apos;C1&apos; &apos;C3&apos;
</msg>
<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin &apos;Dout1&lt;0&gt;.CLKF&apos; has multiple original clock nets &apos;C1&apos; &apos;C3&apos;
</msg>
<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin &apos;Dout1&lt;1&gt;.CLKF&apos; has multiple original clock nets &apos;C1&apos; &apos;C3&apos;
</msg>
<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin &apos;Dout1&lt;2&gt;.CLKF&apos; has multiple original clock nets &apos;C1&apos; &apos;C3&apos;
</msg>
<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin &apos;Dout1&lt;3&gt;.CLKF&apos; has multiple original clock nets &apos;C1&apos; &apos;C3&apos;
</msg>
<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin &apos;IDE_BASEADR&lt;0&gt;.CLKF&apos; has multiple original clock nets &apos;C1&apos; &apos;C3&apos;
</msg>
<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin &apos;IDE_BASEADR&lt;1&gt;.CLKF&apos; has multiple original clock nets &apos;C1&apos; &apos;C3&apos;
</msg>
<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin &apos;IDE_BASEADR&lt;2&gt;.CLKF&apos; has multiple original clock nets &apos;C1&apos; &apos;C3&apos;
</msg>
<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin &apos;IDE_BASEADR&lt;3&gt;.CLKF&apos; has multiple original clock nets &apos;C1&apos; &apos;C3&apos;
</msg>
<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin &apos;IDE_BASEADR&lt;4&gt;.CLKF&apos; has multiple original clock nets &apos;C1&apos; &apos;C3&apos;
</msg>
<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin &apos;IDE_BASEADR&lt;5&gt;.CLKF&apos; has multiple original clock nets &apos;C1&apos; &apos;C3&apos;
</msg>
<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin &apos;IDE_BASEADR&lt;6&gt;.CLKF&apos; has multiple original clock nets &apos;C1&apos; &apos;C3&apos;
</msg>
<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin &apos;IDE_BASEADR&lt;7&gt;.CLKF&apos; has multiple original clock nets &apos;C1&apos; &apos;C3&apos;
</msg>
<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin &apos;LAN_BASEADR&lt;0&gt;.CLKF&apos; has multiple original clock nets &apos;C1&apos; &apos;C3&apos;
</msg>
<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin &apos;LAN_BASEADR&lt;1&gt;.CLKF&apos; has multiple original clock nets &apos;C1&apos; &apos;C3&apos;
</msg>
<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin &apos;LAN_BASEADR&lt;2&gt;.CLKF&apos; has multiple original clock nets &apos;C1&apos; &apos;C3&apos;
</msg>
<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin &apos;LAN_BASEADR&lt;3&gt;.CLKF&apos; has multiple original clock nets &apos;C1&apos; &apos;C3&apos;
</msg>
<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin &apos;LAN_BASEADR&lt;4&gt;.CLKF&apos; has multiple original clock nets &apos;C1&apos; &apos;C3&apos;
</msg>
<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin &apos;LAN_BASEADR&lt;5&gt;.CLKF&apos; has multiple original clock nets &apos;C1&apos; &apos;C3&apos;
</msg>
<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin &apos;LAN_BASEADR&lt;6&gt;.CLKF&apos; has multiple original clock nets &apos;C1&apos; &apos;C3&apos;
</msg>
<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin &apos;LAN_BASEADR&lt;7&gt;.CLKF&apos; has multiple original clock nets &apos;C1&apos; &apos;C3&apos;
</msg>
<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin &apos;DS_D.CLKF&apos; has multiple original clock nets &apos;C1&apos; &apos;C3&apos;
</msg>
<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin &apos;CP_RD_S.CLKF&apos; has multiple original clock nets &apos;C1&apos; &apos;C3&apos;
</msg>
<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin &apos;CP_WE_S.CLKF&apos; has multiple original clock nets &apos;C1&apos; &apos;C3&apos;
</msg>
<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin &apos;IDE_R_S.CLKF&apos; has multiple original clock nets &apos;C1&apos; &apos;C3&apos;
</msg>
<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin &apos;IDE_W_S.CLKF&apos; has multiple original clock nets &apos;C1&apos; &apos;C3&apos;
</msg>
<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin &apos;LAN_RD_S.CLKF&apos; has multiple original clock nets &apos;C1&apos; &apos;C3&apos;
</msg>
<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin &apos;LAN_WRH_S.CLKF&apos; has multiple original clock nets &apos;C1&apos; &apos;C3&apos;
</msg>
<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin &apos;LAN_WRL_S.CLKF&apos; has multiple original clock nets &apos;C1&apos; &apos;C3&apos;
</msg>
<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin &apos;ROM_OE_S.CLKF&apos; has multiple original clock nets &apos;C1&apos; &apos;C3&apos;
</msg>
</messages>