Possible asynchronous logic: Clock pin 'LAN_INT_ENABLE.CLKF' has multiple original clock nets 'C1' 'C3' Possible asynchronous logic: Clock pin 'AUTO_CONFIG_DONE<1>.CLKF' has multiple original clock nets 'C1' 'C3' Possible asynchronous logic: Clock pin 'AUTO_CONFIG_DONE<0>.CLKF' has multiple original clock nets 'C1' 'C3' Possible asynchronous logic: Clock pin 'AUTO_CONFIG_DONE_CYCLE<0>.CLKF' has multiple original clock nets 'C1' 'C3' Possible asynchronous logic: Clock pin 'AUTO_CONFIG_DONE_CYCLE<1>.CLKF' has multiple original clock nets 'C1' 'C3' Possible asynchronous logic: Clock pin 'SHUT_UP<0>.CLKF' has multiple original clock nets 'C1' 'C3' Possible asynchronous logic: Clock pin 'SHUT_UP<1>.CLKF' has multiple original clock nets 'C1' 'C3' Possible asynchronous logic: Clock pin 'SHUT_UP<2>.CLKF' has multiple original clock nets 'C1' 'C3' Possible asynchronous logic: Clock pin 'IDE_ENABLE.CLKF' has multiple original clock nets 'C1' 'C3' Possible asynchronous logic: Clock pin 'CP_BASEADR<0>.CLKF' has multiple original clock nets 'C1' 'C3' Possible asynchronous logic: Clock pin 'CP_BASEADR<1>.CLKF' has multiple original clock nets 'C1' 'C3' Possible asynchronous logic: Clock pin 'CP_BASEADR<2>.CLKF' has multiple original clock nets 'C1' 'C3' Possible asynchronous logic: Clock pin 'CP_BASEADR<3>.CLKF' has multiple original clock nets 'C1' 'C3' Possible asynchronous logic: Clock pin 'CP_BASEADR<4>.CLKF' has multiple original clock nets 'C1' 'C3' Possible asynchronous logic: Clock pin 'CP_BASEADR<5>.CLKF' has multiple original clock nets 'C1' 'C3' Possible asynchronous logic: Clock pin 'CP_BASEADR<6>.CLKF' has multiple original clock nets 'C1' 'C3' Possible asynchronous logic: Clock pin 'CP_BASEADR<7>.CLKF' has multiple original clock nets 'C1' 'C3' Possible asynchronous logic: Clock pin 'Dout1<0>.CLKF' has multiple original clock nets 'C1' 'C3' Possible asynchronous logic: Clock pin 'Dout1<1>.CLKF' has multiple original clock nets 'C1' 'C3' Possible asynchronous logic: Clock pin 'Dout1<2>.CLKF' has multiple original clock nets 'C1' 'C3' Possible asynchronous logic: Clock pin 'Dout1<3>.CLKF' has multiple original clock nets 'C1' 'C3' Possible asynchronous logic: Clock pin 'IDE_BASEADR<0>.CLKF' has multiple original clock nets 'C1' 'C3' Possible asynchronous logic: Clock pin 'IDE_BASEADR<1>.CLKF' has multiple original clock nets 'C1' 'C3' Possible asynchronous logic: Clock pin 'IDE_BASEADR<2>.CLKF' has multiple original clock nets 'C1' 'C3' Possible asynchronous logic: Clock pin 'IDE_BASEADR<3>.CLKF' has multiple original clock nets 'C1' 'C3' Possible asynchronous logic: Clock pin 'IDE_BASEADR<4>.CLKF' has multiple original clock nets 'C1' 'C3' Possible asynchronous logic: Clock pin 'IDE_BASEADR<5>.CLKF' has multiple original clock nets 'C1' 'C3' Possible asynchronous logic: Clock pin 'IDE_BASEADR<6>.CLKF' has multiple original clock nets 'C1' 'C3' Possible asynchronous logic: Clock pin 'IDE_BASEADR<7>.CLKF' has multiple original clock nets 'C1' 'C3' Possible asynchronous logic: Clock pin 'LAN_BASEADR<0>.CLKF' has multiple original clock nets 'C1' 'C3' Possible asynchronous logic: Clock pin 'LAN_BASEADR<1>.CLKF' has multiple original clock nets 'C1' 'C3' Possible asynchronous logic: Clock pin 'LAN_BASEADR<2>.CLKF' has multiple original clock nets 'C1' 'C3' Possible asynchronous logic: Clock pin 'LAN_BASEADR<3>.CLKF' has multiple original clock nets 'C1' 'C3' Possible asynchronous logic: Clock pin 'LAN_BASEADR<4>.CLKF' has multiple original clock nets 'C1' 'C3' Possible asynchronous logic: Clock pin 'LAN_BASEADR<5>.CLKF' has multiple original clock nets 'C1' 'C3' Possible asynchronous logic: Clock pin 'LAN_BASEADR<6>.CLKF' has multiple original clock nets 'C1' 'C3' Possible asynchronous logic: Clock pin 'LAN_BASEADR<7>.CLKF' has multiple original clock nets 'C1' 'C3' Possible asynchronous logic: Clock pin 'DS_D.CLKF' has multiple original clock nets 'C1' 'C3' Possible asynchronous logic: Clock pin 'CP_RD_S.CLKF' has multiple original clock nets 'C1' 'C3' Possible asynchronous logic: Clock pin 'CP_WE_S.CLKF' has multiple original clock nets 'C1' 'C3' Possible asynchronous logic: Clock pin 'IDE_R_S.CLKF' has multiple original clock nets 'C1' 'C3' Possible asynchronous logic: Clock pin 'IDE_W_S.CLKF' has multiple original clock nets 'C1' 'C3' Possible asynchronous logic: Clock pin 'LAN_RD_S.CLKF' has multiple original clock nets 'C1' 'C3' Possible asynchronous logic: Clock pin 'LAN_WRH_S.CLKF' has multiple original clock nets 'C1' 'C3' Possible asynchronous logic: Clock pin 'LAN_WRL_S.CLKF' has multiple original clock nets 'C1' 'C3' Possible asynchronous logic: Clock pin 'ROM_OE_S.CLKF' has multiple original clock nets 'C1' 'C3'