148 lines
9.3 KiB
XML
148 lines
9.3 KiB
XML
<?xml version="1.0" encoding="UTF-8"?>
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<!-- IMPORTANT: This is an internal file that has been generated
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by the Xilinx ISE software. Any direct editing or
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changes made to this file may result in unpredictable
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behavior or data corruption. It is strongly advised that
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users do not edit the contents of this file. -->
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<messages>
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<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin 'LAN_INT_ENABLE.CLKF' has multiple original clock nets 'C1' 'C3'
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</msg>
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<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin 'AUTO_CONFIG_DONE<1>.CLKF' has multiple original clock nets 'C1' 'C3'
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</msg>
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<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin 'AUTO_CONFIG_DONE<0>.CLKF' has multiple original clock nets 'C1' 'C3'
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</msg>
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<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin 'AUTO_CONFIG_DONE_CYCLE<0>.CLKF' has multiple original clock nets 'C1' 'C3'
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</msg>
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<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin 'AUTO_CONFIG_DONE_CYCLE<1>.CLKF' has multiple original clock nets 'C1' 'C3'
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</msg>
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<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin 'SHUT_UP<0>.CLKF' has multiple original clock nets 'C1' 'C3'
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</msg>
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<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin 'SHUT_UP<1>.CLKF' has multiple original clock nets 'C1' 'C3'
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</msg>
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<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin 'SHUT_UP<2>.CLKF' has multiple original clock nets 'C1' 'C3'
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</msg>
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<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin 'IDE_ENABLE.CLKF' has multiple original clock nets 'C1' 'C3'
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</msg>
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<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin 'CP_BASEADR<0>.CLKF' has multiple original clock nets 'C1' 'C3'
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</msg>
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<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin 'CP_BASEADR<1>.CLKF' has multiple original clock nets 'C1' 'C3'
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</msg>
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<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin 'CP_BASEADR<2>.CLKF' has multiple original clock nets 'C1' 'C3'
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</msg>
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<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin 'CP_BASEADR<3>.CLKF' has multiple original clock nets 'C1' 'C3'
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</msg>
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<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin 'CP_BASEADR<4>.CLKF' has multiple original clock nets 'C1' 'C3'
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</msg>
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<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin 'CP_BASEADR<5>.CLKF' has multiple original clock nets 'C1' 'C3'
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</msg>
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<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin 'CP_BASEADR<6>.CLKF' has multiple original clock nets 'C1' 'C3'
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</msg>
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<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin 'CP_BASEADR<7>.CLKF' has multiple original clock nets 'C1' 'C3'
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</msg>
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<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin 'Dout1<0>.CLKF' has multiple original clock nets 'C1' 'C3'
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</msg>
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<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin 'Dout1<1>.CLKF' has multiple original clock nets 'C1' 'C3'
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</msg>
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<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin 'Dout1<2>.CLKF' has multiple original clock nets 'C1' 'C3'
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</msg>
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<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin 'Dout1<3>.CLKF' has multiple original clock nets 'C1' 'C3'
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</msg>
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<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin 'IDE_BASEADR<0>.CLKF' has multiple original clock nets 'C1' 'C3'
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</msg>
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<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin 'IDE_BASEADR<1>.CLKF' has multiple original clock nets 'C1' 'C3'
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</msg>
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<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin 'IDE_BASEADR<2>.CLKF' has multiple original clock nets 'C1' 'C3'
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</msg>
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<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin 'IDE_BASEADR<3>.CLKF' has multiple original clock nets 'C1' 'C3'
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</msg>
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<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin 'IDE_BASEADR<4>.CLKF' has multiple original clock nets 'C1' 'C3'
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</msg>
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<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin 'IDE_BASEADR<5>.CLKF' has multiple original clock nets 'C1' 'C3'
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</msg>
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<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin 'IDE_BASEADR<6>.CLKF' has multiple original clock nets 'C1' 'C3'
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</msg>
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<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin 'IDE_BASEADR<7>.CLKF' has multiple original clock nets 'C1' 'C3'
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</msg>
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<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin 'LAN_BASEADR<0>.CLKF' has multiple original clock nets 'C1' 'C3'
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</msg>
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<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin 'LAN_BASEADR<1>.CLKF' has multiple original clock nets 'C1' 'C3'
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</msg>
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<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin 'LAN_BASEADR<2>.CLKF' has multiple original clock nets 'C1' 'C3'
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</msg>
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<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin 'LAN_BASEADR<3>.CLKF' has multiple original clock nets 'C1' 'C3'
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</msg>
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<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin 'LAN_BASEADR<4>.CLKF' has multiple original clock nets 'C1' 'C3'
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</msg>
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<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin 'LAN_BASEADR<5>.CLKF' has multiple original clock nets 'C1' 'C3'
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</msg>
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<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin 'LAN_BASEADR<6>.CLKF' has multiple original clock nets 'C1' 'C3'
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</msg>
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<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin 'LAN_BASEADR<7>.CLKF' has multiple original clock nets 'C1' 'C3'
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</msg>
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<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin 'DS_D.CLKF' has multiple original clock nets 'C1' 'C3'
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</msg>
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<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin 'CP_RD_S.CLKF' has multiple original clock nets 'C1' 'C3'
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</msg>
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<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin 'CP_WE_S.CLKF' has multiple original clock nets 'C1' 'C3'
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</msg>
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<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin 'IDE_R_S.CLKF' has multiple original clock nets 'C1' 'C3'
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</msg>
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<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin 'IDE_W_S.CLKF' has multiple original clock nets 'C1' 'C3'
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</msg>
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<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin 'LAN_RD_S.CLKF' has multiple original clock nets 'C1' 'C3'
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</msg>
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<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin 'LAN_WRH_S.CLKF' has multiple original clock nets 'C1' 'C3'
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</msg>
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<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin 'LAN_WRL_S.CLKF' has multiple original clock nets 'C1' 'C3'
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</msg>
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<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin 'ROM_OE_S.CLKF' has multiple original clock nets 'C1' 'C3'
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</msg>
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</messages>
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