1168 lines
62 KiB
Plaintext
1168 lines
62 KiB
Plaintext
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cpldfit: version P.68d Xilinx Inc.
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Fitter Report
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Design Name: LAN_IDE_CP Date: 12-15-2016, 7:48PM
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Device Used: XC95144XL-10-TQ144
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Fitting Status: Successful
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************************* Mapped Resource Summary **************************
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Macrocells Product Terms Function Block Registers Pins
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Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot
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51 /144 ( 35%) 179 /720 ( 25%) 134/432 ( 31%) 26 /144 ( 18%) 54 /117 ( 46%)
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** Function Block Resources **
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Function Mcells FB Inps Pterms IO
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Block Used/Tot Used/Tot Used/Tot Used/Tot
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FB1 16/18 24/54 40/90 13/15
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FB2 11/18 24/54 56/90 4/15
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FB3 12/18 24/54 25/90 11/15
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FB4 3/18 24/54 25/90 0/15
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FB5 7/18 23/54 19/90 10/14
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FB6 1/18 15/54 14/90 0/13
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FB7 1/18 0/54 0/90 8/15
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FB8 0/18 0/54 0/90 8/15
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----- ----- ----- -----
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51/144 134/432 179/720 54/117
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* - Resource is exhausted
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** Global Control Resources **
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Global clock net(s) unused.
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Global output enable net(s) unused.
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Signal 'RESET' mapped onto global set/reset net GSR.
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** Pin Resources **
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Signal Type Required Mapped | Pin Type Used Total
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------------------------------------|------------------------------------
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Input : 26 26 | I/O : 52 109
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Output : 19 19 | GCK/IO : 0 3
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Bidirectional : 8 8 | GTS/IO : 1 4
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GCK : 0 0 | GSR/IO : 1 1
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GTS : 0 0 |
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GSR : 1 1 |
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---- ----
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Total 54 54
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** Power Data **
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There are 51 macrocells in high performance mode (MCHP).
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There are 0 macrocells in low power mode (MCLP).
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End of Mapped Resource Summary
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************************** Errors and Warnings ***************************
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WARNING:Cpld - Unable to retrieve the path to the iSE Project Repository. Will
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use the default filename of 'LAN_IDE_CP.ise'.
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INFO:Cpld - Inferring BUFG constraint for signal 'CLK_EXT' based upon the LOC
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constraint 'P30'. It is recommended that you declare this BUFG explicitedly
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in your design. Note that for certain device families the output of a BUFG
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constraint can not drive a gated clock, and the BUFG constraint will be
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ignored.
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WARNING:Cpld:936 - The output buffer 'SLAVE_OBUF' is missing an input and will
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be deleted.
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WARNING:Cpld:936 - The output buffer 'OWN_OBUF' is missing an input and will be
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deleted.
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WARNING:Cpld:936 - The output buffer 'OVR_OBUF' is missing an input and will be
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deleted.
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WARNING:Cpld:936 - The output buffer 'MTACK_OBUF' is missing an input and will
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be deleted.
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WARNING:Cpld:936 - The output buffer 'LAN_WRH_OBUF' is missing an input and will
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be deleted.
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WARNING:Cpld:936 - The output buffer 'LAN_RD_OBUF' is missing an input and will
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be deleted.
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WARNING:Cpld:936 - The output buffer 'LAN_EN_OBUF' is missing an input and will
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be deleted.
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WARNING:Cpld:936 - The output buffer 'LAN_CS_OBUF' is missing an input and will
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be deleted.
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WARNING:Cpld:936 - The output buffer 'LAN_CFG<4>_OBUF' is missing an input and
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will be deleted.
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WARNING:Cpld:936 - The output buffer 'LAN_CFG<3>_OBUF' is missing an input and
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will be deleted.
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WARNING:Cpld:936 - The output buffer 'LAN_CFG<2>_OBUF' is missing an input and
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will be deleted.
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WARNING:Cpld:936 - The output buffer 'LAN_CFG<1>_OBUF' is missing an input and
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will be deleted.
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WARNING:Cpld:936 - The output buffer 'INT_OUT_OBUF' is missing an input and will
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be deleted.
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WARNING:Cpld:936 - The output buffer 'CP_WE_OBUF' is missing an input and will
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be deleted.
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WARNING:Cpld:936 - The output buffer 'CP_RD_OBUF' is missing an input and will
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be deleted.
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WARNING:Cpld:936 - The output buffer 'CP_CS_OBUF' is missing an input and will
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be deleted.
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WARNING:Cpld:936 - The output buffer 'CFOUT_OBUF' is missing an input and will
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be deleted.
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WARNING:Cpld:936 - The output buffer 'A_LAN<9>_OBUF' is missing an input and
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will be deleted.
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WARNING:Cpld:936 - The output buffer 'A_LAN<8>_OBUF' is missing an input and
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will be deleted.
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WARNING:Cpld:936 - The output buffer 'A_LAN<7>_OBUF' is missing an input and
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will be deleted.
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WARNING:Cpld:936 - The output buffer 'A_LAN<6>_OBUF' is missing an input and
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will be deleted.
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WARNING:Cpld:936 - The output buffer 'A_LAN<5>_OBUF' is missing an input and
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will be deleted.
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WARNING:Cpld:936 - The output buffer 'A_LAN<4>_OBUF' is missing an input and
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will be deleted.
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WARNING:Cpld:936 - The output buffer 'A_LAN<3>_OBUF' is missing an input and
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will be deleted.
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WARNING:Cpld:936 - The output buffer 'A_LAN<2>_OBUF' is missing an input and
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will be deleted.
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WARNING:Cpld:936 - The output buffer 'A_LAN<1>_OBUF' is missing an input and
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will be deleted.
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WARNING:Cpld:936 - The output buffer 'A_LAN<13>_OBUF' is missing an input and
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will be deleted.
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WARNING:Cpld:936 - The output buffer 'A_LAN<12>_OBUF' is missing an input and
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will be deleted.
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WARNING:Cpld:936 - The output buffer 'A_LAN<11>_OBUF' is missing an input and
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will be deleted.
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WARNING:Cpld:936 - The output buffer 'A_LAN<10>_OBUF' is missing an input and
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will be deleted.
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WARNING:Cpld:936 - The output buffer 'A_LAN<0>_OBUF' is missing an input and
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will be deleted.
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WARNING:Cpld:1007 - Removing unused input(s) 'A<14>'. The input(s) are unused
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after optimization. Please verify functionality via simulation.
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WARNING:Cpld:1007 - Removing unused input(s) 'A<15>'. The input(s) are unused
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after optimization. Please verify functionality via simulation.
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WARNING:Cpld:1007 - Removing unused input(s) 'A<7>'. The input(s) are unused
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after optimization. Please verify functionality via simulation.
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WARNING:Cpld:1007 - Removing unused input(s) 'A<8>'. The input(s) are unused
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after optimization. Please verify functionality via simulation.
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WARNING:Cpld:1007 - Removing unused input(s) 'CFIN'. The input(s) are unused
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after optimization. Please verify functionality via simulation.
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WARNING:Cpld:1007 - Removing unused input(s) 'CLK_EXT'. The input(s) are unused
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after optimization. Please verify functionality via simulation.
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WARNING:Cpld:1007 - Removing unused input(s) 'CP_IRQ'. The input(s) are unused
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after optimization. Please verify functionality via simulation.
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WARNING:Cpld:1007 - Removing unused input(s) 'DQ<0>'. The input(s) are unused
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after optimization. Please verify functionality via simulation.
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WARNING:Cpld:1007 - Removing unused input(s) 'DQ<10>'. The input(s) are unused
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after optimization. Please verify functionality via simulation.
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WARNING:Cpld:1007 - Removing unused input(s) 'DQ<11>'. The input(s) are unused
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after optimization. Please verify functionality via simulation.
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WARNING:Cpld:1007 - Removing unused input(s) 'DQ<12>'. The input(s) are unused
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after optimization. Please verify functionality via simulation.
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WARNING:Cpld:1007 - Removing unused input(s) 'DQ<13>'. The input(s) are unused
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after optimization. Please verify functionality via simulation.
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WARNING:Cpld:1007 - Removing unused input(s) 'DQ<14>'. The input(s) are unused
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after optimization. Please verify functionality via simulation.
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WARNING:Cpld:1007 - Removing unused input(s) 'DQ<15>'. The input(s) are unused
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after optimization. Please verify functionality via simulation.
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WARNING:Cpld:1007 - Removing unused input(s) 'DQ<1>'. The input(s) are unused
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after optimization. Please verify functionality via simulation.
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WARNING:Cpld:1007 - Removing unused input(s) 'DQ<2>'. The input(s) are unused
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after optimization. Please verify functionality via simulation.
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WARNING:Cpld:1007 - Removing unused input(s) 'DQ<3>'. The input(s) are unused
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after optimization. Please verify functionality via simulation.
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WARNING:Cpld:1007 - Removing unused input(s) 'DQ<4>'. The input(s) are unused
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after optimization. Please verify functionality via simulation.
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WARNING:Cpld:1007 - Removing unused input(s) 'DQ<5>'. The input(s) are unused
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after optimization. Please verify functionality via simulation.
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WARNING:Cpld:1007 - Removing unused input(s) 'DQ<6>'. The input(s) are unused
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after optimization. Please verify functionality via simulation.
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WARNING:Cpld:1007 - Removing unused input(s) 'DQ<7>'. The input(s) are unused
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after optimization. Please verify functionality via simulation.
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WARNING:Cpld:1007 - Removing unused input(s) 'DQ<8>'. The input(s) are unused
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after optimization. Please verify functionality via simulation.
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WARNING:Cpld:1007 - Removing unused input(s) 'DQ<9>'. The input(s) are unused
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after optimization. Please verify functionality via simulation.
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WARNING:Cpld:1007 - Removing unused input(s) 'DS0'. The input(s) are unused
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after optimization. Please verify functionality via simulation.
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WARNING:Cpld:1007 - Removing unused input(s) 'DS1'. The input(s) are unused
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after optimization. Please verify functionality via simulation.
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WARNING:Cpld:1007 - Removing unused input(s) 'FCS'. The input(s) are unused
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after optimization. Please verify functionality via simulation.
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WARNING:Cpld:1007 - Removing unused input(s) 'IDE_WAIT'. The input(s) are
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unused after optimization. Please verify functionality via simulation.
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WARNING:Cpld:1007 - Removing unused input(s) 'LAN_INT'. The input(s) are unused
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after optimization. Please verify functionality via simulation.
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WARNING:Cpld:1007 - Removing unused input(s) 'LDS'. The input(s) are unused
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after optimization. Please verify functionality via simulation.
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WARNING:Cpld:1007 - Removing unused input(s) 'MTCR'. The input(s) are unused
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after optimization. Please verify functionality via simulation.
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WARNING:Cpld:1007 - Removing unused input(s) 'Z3'. The input(s) are unused
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after optimization. Please verify functionality via simulation.
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WARNING:Cpld:896 - Unable to map all desired signals into function block, FB3,
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because too many function block product terms are required. Buffering output
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signal D<12> to allow all signals assigned to this function block to be
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placed.
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WARNING:Cpld:896 - Unable to map all desired signals into function block, FB3,
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because too many function block product terms are required. Buffering output
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signal D<14> to allow all signals assigned to this function block to be
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placed.
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WARNING:Cpld:896 - Unable to map all desired signals into function block, FB3,
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because too many function block product terms are required. Buffering output
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signal D<13> to allow all signals assigned to this function block to be
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placed.
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WARNING:Cpld:896 - Unable to map all desired signals into function block, FB3,
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because too many function block product terms are required. Buffering output
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signal D<15> to allow all signals assigned to this function block to be
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placed.
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************************* Summary of Mapped Logic ************************
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** 27 Outputs **
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Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init
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Name Pts Inps No. Type Use Mode Rate State
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IDE_CS<1> 1 1 FB1_1 23 I/O O STD FAST
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D<7> 1 2 FB1_2 16 I/O O STD FAST
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D<1> 1 2 FB1_3 17 I/O O STD FAST
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IDE_A<2> 1 1 FB1_4 25 I/O O STD FAST
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D<8> 1 2 FB1_5 19 I/O I/O STD FAST
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D<5> 1 2 FB1_6 20 I/O O STD FAST
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D<4> 1 2 FB1_8 21 I/O O STD FAST
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IDE_CS<0> 1 1 FB1_9 22 I/O O STD FAST
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IDE_A<0> 1 1 FB1_11 24 I/O O STD FAST
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IDE_A<1> 1 1 FB1_12 26 I/O O STD FAST
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IDE_R 2 6 FB1_14 27 I/O O STD FAST SET
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IDE_W 2 5 FB1_15 28 I/O O STD FAST SET
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ROM_OE 2 6 FB1_16 35 I/O O STD FAST SET
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D<0> 1 2 FB2_5 2 GTS/I/O O STD FAST
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D<6> 1 2 FB2_16 14 I/O O STD FAST
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D<3> 1 2 FB2_17 15 I/O O STD FAST
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D<2> 1 2 FB3_1 39 I/O O STD FAST
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D<10> 1 2 FB3_3 41 I/O I/O STD FAST
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D<12> 2 3 FB3_4 44 I/O I/O STD FAST
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D<14> 2 3 FB3_7 46 I/O I/O STD FAST
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D<9> 1 2 FB3_9 40 I/O I/O STD FAST
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D<15> 2 3 FB3_10 48 I/O I/O STD FAST
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D<11> 1 2 FB3_11 43 I/O I/O STD FAST
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D<13> 2 3 FB3_12 45 I/O I/O STD FAST
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ROM_B<0> 0 0 FB5_10 68 I/O O STD FAST
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ROM_B<1> 0 0 FB5_17 69 I/O O STD FAST
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DTACK 0 0 FB7_12 85 I/O O STD FAST
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** 24 Buried Nodes **
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Signal Total Total Loc Pwr Reg Init
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Name Pts Inps Mode State
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AUTOCONFIG_IN_PROGRESS 2 3 FB1_7 STD RESET
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IDE_ENABLE 3 6 FB1_10 STD RESET
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D<12>_BUFR 19 16 FB1_18 STD RESET
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D<14>_BUFR 18 15 FB2_1 STD RESET
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AUTO_CONFIG_DONE<2> 2 2 FB2_8 STD RESET
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AUTO_CONFIG_DONE<0> 2 2 FB2_9 STD RESET
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AUTO_CONFIG_DONE_CYCLE<2> 3 15 FB2_10 STD RESET
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AUTO_CONFIG_DONE_CYCLE<0> 3 13 FB2_11 STD RESET
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IDE_BASEADR<7> 4 16 FB2_12 STD RESET
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IDE_BASEADR<6> 4 16 FB2_13 STD RESET
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D<13>_BUFR 17 15 FB2_15 STD RESET
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AUTO_CONFIG_DONE<1> 2 2 FB3_15 STD RESET
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AUTO_CONFIG_DONE_CYCLE<1> 3 14 FB3_16 STD RESET
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IDE_BASEADR<3> 4 16 FB3_17 STD RESET
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IDE_BASEADR<2> 4 16 FB3_18 STD RESET
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ide 19 19 FB4_1 STD RESET
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ide/ide_CLKF 2 2 FB4_16 STD
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autoconfig 4 13 FB4_17 STD RESET
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SHUT_UP<1> 3 15 FB5_13 STD RESET
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IDE_BASEADR<5> 4 16 FB5_14 STD RESET
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IDE_BASEADR<4> 4 16 FB5_15 STD RESET
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IDE_BASEADR<1> 4 16 FB5_16 STD RESET
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IDE_BASEADR<0> 4 16 FB5_18 STD RESET
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D<15>_BUFR 14 15 FB6_17 STD RESET
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** 27 Inputs **
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Signal Loc Pin Pin Pin
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Name No. Type Use
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RESET FB2_2 143 GSR/I/O GSR/I
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A<5> FB3_14 49 I/O I
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A<4> FB3_15 50 I/O I
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A<6> FB3_17 51 I/O I
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A<3> FB5_2 52 I/O I
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A<10> FB5_3 59 I/O I
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A<2> FB5_6 54 I/O I
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A<1> FB5_9 57 I/O I
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A<9> FB5_11 58 I/O I
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A<11> FB5_12 60 I/O I
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A<12> FB5_14 61 I/O I
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A<13> FB5_15 64 I/O I
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AUTOBOOT_OFF FB7_3 75 I/O I
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AS FB7_9 80 I/O I
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UDS FB7_13 81 I/O I
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A<23> FB7_14 86 I/O I
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A<22> FB7_15 87 I/O I
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RW FB7_16 83 I/O I
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A<21> FB7_17 88 I/O I
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A<20> FB8_2 91 I/O I
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A<17> FB8_3 95 I/O I
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A<16> FB8_4 97 I/O I
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A<19> FB8_5 92 I/O I
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A<18> FB8_8 94 I/O I
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BERR FB8_11 98 I/O I
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C1 FB8_13 103 I/O I
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C3 FB8_14 102 I/O I
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Legend:
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Pin No. - ~ - User Assigned
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************************** Function Block Details ************************
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Legend:
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Total Pt - Total product terms used by the macrocell signal
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Imp Pt - Product terms imported from other macrocells
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Exp Pt - Product terms exported to other macrocells
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in direction shown
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Unused Pt - Unused local product terms remaining in macrocell
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Loc - Location where logic was mapped in device
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Pin Type/Use - I - Input GCK - Global Clock
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O - Output GTS - Global Output Enable
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(b) - Buried macrocell GSR - Global Set/Reset
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X - Signal used as input to the macrocell logic.
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Pin No. - ~ - User Assigned
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*********************************** FB1 ***********************************
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Number of function block inputs used/remaining: 24/30
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Number of signals used by logic mapping into function block: 24
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Signal Total Imp Exp Unused Loc Pin Pin Pin
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Name Pt Pt Pt Pt # Type Use
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IDE_CS<1> 1 1<- /\5 0 FB1_1 23 I/O O
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D<7> 1 0 /\1 3 FB1_2 16 I/O O
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D<1> 1 0 0 4 FB1_3 17 I/O O
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IDE_A<2> 1 0 0 4 FB1_4 25 I/O O
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D<8> 1 0 0 4 FB1_5 19 I/O I/O
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D<5> 1 0 0 4 FB1_6 20 I/O O
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AUTOCONFIG_IN_PROGRESS
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2 0 0 3 FB1_7 (b) (b)
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D<4> 1 0 0 4 FB1_8 21 I/O O
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IDE_CS<0> 1 0 0 4 FB1_9 22 I/O O
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IDE_ENABLE 3 0 0 2 FB1_10 31 I/O (b)
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IDE_A<0> 1 0 0 4 FB1_11 24 I/O O
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IDE_A<1> 1 0 0 4 FB1_12 26 I/O O
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(unused) 0 0 0 5 FB1_13 (b)
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IDE_R 2 0 0 3 FB1_14 27 I/O O
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IDE_W 2 0 \/1 2 FB1_15 28 I/O O
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ROM_OE 2 1<- \/4 0 FB1_16 35 I/O O
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(unused) 0 0 \/5 0 FB1_17 30 GCK/I/O (b)
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D<12>_BUFR 19 14<- 0 0 FB1_18 (b) (b)
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Signals Used by Logic in Function Block
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1: AS 9: A<1> 17: A<10>
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2: AUTOBOOT_OFF 10: A<2> 18: A<11>
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3: AUTOCONFIG_IN_PROGRESS 11: A<3> 19: IDE_ENABLE
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4: AUTO_CONFIG_DONE<0> 12: A<4> 20: RESET
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5: AUTO_CONFIG_DONE<1> 13: A<5> 21: RW
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6: AUTO_CONFIG_DONE<2> 14: A<6> 22: autoconfig
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7: A<12> 15: D<12> 23: ide
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8: A<13> 16: A<9> 24: ide/ide_CLKF
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Signal 1 2 3 4 FB
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Name 0----+----0----+----0----+----0----+----0 Inputs
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IDE_CS<1> .......X................................ 1
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D<7> ..X.................X................... 2
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D<1> ..X.................X................... 2
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IDE_A<2> .................X...................... 1
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D<8> ..X.................X................... 2
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D<5> ..X.................X................... 2
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AUTOCONFIG_IN_PROGRESS
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X....................X.X................ 3
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D<4> ..X.................X................... 2
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IDE_CS<0> ......X................................. 1
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IDE_ENABLE X.................XXX.XX................ 6
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IDE_A<0> ...............X........................ 1
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IDE_A<1> ................X....................... 1
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IDE_R X.................XXX.XX................ 6
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IDE_W X..................XX.XX................ 5
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ROM_OE X.................XXX.XX................ 6
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D<12>_BUFR XX.XXX..XXXXXXX....XXX.X................ 16
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0----+----1----+----2----+----3----+----4
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0 0 0 0
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*********************************** FB2 ***********************************
|
|
Number of function block inputs used/remaining: 24/30
|
|
Number of signals used by logic mapping into function block: 24
|
|
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
|
Name Pt Pt Pt Pt # Type Use
|
|
D<14>_BUFR 18 13<- 0 0 FB2_1 142 I/O (b)
|
|
(unused) 0 0 /\5 0 FB2_2 143 GSR/I/O GSR/I
|
|
(unused) 0 0 /\3 2 FB2_3 (b) (b)
|
|
(unused) 0 0 0 5 FB2_4 4 I/O
|
|
D<0> 1 0 0 4 FB2_5 2 GTS/I/O O
|
|
(unused) 0 0 0 5 FB2_6 3 GTS/I/O
|
|
(unused) 0 0 0 5 FB2_7 (b)
|
|
AUTO_CONFIG_DONE<2> 2 0 0 3 FB2_8 5 GTS/I/O (b)
|
|
AUTO_CONFIG_DONE<0> 2 0 0 3 FB2_9 6 GTS/I/O (b)
|
|
AUTO_CONFIG_DONE_CYCLE<2>
|
|
3 0 0 2 FB2_10 7 I/O (b)
|
|
AUTO_CONFIG_DONE_CYCLE<0>
|
|
3 0 \/1 1 FB2_11 9 I/O (b)
|
|
IDE_BASEADR<7> 4 1<- \/2 0 FB2_12 10 I/O (b)
|
|
IDE_BASEADR<6> 4 2<- \/3 0 FB2_13 12 I/O (b)
|
|
(unused) 0 0 \/5 0 FB2_14 11 I/O (b)
|
|
D<13>_BUFR 17 12<- 0 0 FB2_15 13 I/O (b)
|
|
D<6> 1 0 /\4 0 FB2_16 14 I/O O
|
|
D<3> 1 0 0 4 FB2_17 15 I/O O
|
|
(unused) 0 0 \/5 0 FB2_18 (b) (b)
|
|
|
|
Signals Used by Logic in Function Block
|
|
1: AS 9: A<2> 17: IDE_BASEADR<7>
|
|
2: AUTOCONFIG_IN_PROGRESS 10: A<3> 18: D<14>.PIN
|
|
3: AUTO_CONFIG_DONE<0> 11: A<4> 19: D<15>.PIN
|
|
4: AUTO_CONFIG_DONE<1> 12: A<5> 20: RESET
|
|
5: AUTO_CONFIG_DONE<2> 13: A<6> 21: RW
|
|
6: AUTO_CONFIG_DONE_CYCLE<0> 14: D<13> 22: UDS
|
|
7: AUTO_CONFIG_DONE_CYCLE<2> 15: D<14> 23: autoconfig
|
|
8: A<1> 16: IDE_BASEADR<6> 24: ide/ide_CLKF
|
|
|
|
Signal 1 2 3 4 FB
|
|
Name 0----+----0----+----0----+----0----+----0 Inputs
|
|
D<14>_BUFR X.XXX..XXXXXX.X....XX.XX................ 15
|
|
D<0> .X..................X................... 2
|
|
AUTO_CONFIG_DONE<2> X.....X................................. 2
|
|
AUTO_CONFIG_DONE<0> X....X.................................. 2
|
|
AUTO_CONFIG_DONE_CYCLE<2>
|
|
X.XXX.XX.XXXX......XXXXX................ 15
|
|
AUTO_CONFIG_DONE_CYCLE<0>
|
|
X.X..X.X.XXXX......XXXXX................ 13
|
|
IDE_BASEADR<7> X.XX...XXXXXX...X.XXXXXX................ 16
|
|
IDE_BASEADR<6> X.XX...XXXXXX..X.X.XXXXX................ 16
|
|
D<13>_BUFR X.XXX..XXXXXXX.....XX.XX................ 15
|
|
D<6> .X..................X................... 2
|
|
D<3> .X..................X................... 2
|
|
0----+----1----+----2----+----3----+----4
|
|
0 0 0 0
|
|
*********************************** FB3 ***********************************
|
|
Number of function block inputs used/remaining: 24/30
|
|
Number of signals used by logic mapping into function block: 24
|
|
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
|
Name Pt Pt Pt Pt # Type Use
|
|
D<2> 1 0 0 4 FB3_1 39 I/O O
|
|
(unused) 0 0 0 5 FB3_2 32 GCK/I/O
|
|
D<10> 1 0 0 4 FB3_3 41 I/O I/O
|
|
D<12> 2 0 0 3 FB3_4 44 I/O I/O
|
|
(unused) 0 0 0 5 FB3_5 33 I/O
|
|
(unused) 0 0 0 5 FB3_6 34 I/O
|
|
D<14> 2 0 0 3 FB3_7 46 I/O I/O
|
|
(unused) 0 0 0 5 FB3_8 38 GCK/I/O
|
|
D<9> 1 0 0 4 FB3_9 40 I/O I/O
|
|
D<15> 2 0 0 3 FB3_10 48 I/O I/O
|
|
D<11> 1 0 0 4 FB3_11 43 I/O I/O
|
|
D<13> 2 0 0 3 FB3_12 45 I/O I/O
|
|
(unused) 0 0 0 5 FB3_13 (b)
|
|
(unused) 0 0 0 5 FB3_14 49 I/O I
|
|
AUTO_CONFIG_DONE<1> 2 0 0 3 FB3_15 50 I/O I
|
|
AUTO_CONFIG_DONE_CYCLE<1>
|
|
3 0 0 2 FB3_16 (b) (b)
|
|
IDE_BASEADR<3> 4 0 0 1 FB3_17 51 I/O I
|
|
IDE_BASEADR<2> 4 0 0 1 FB3_18 (b) (b)
|
|
|
|
Signals Used by Logic in Function Block
|
|
1: AS 9: A<4> 17: IDE_BASEADR<3>
|
|
2: AUTOCONFIG_IN_PROGRESS 10: A<5> 18: D<11>.PIN
|
|
3: AUTO_CONFIG_DONE<0> 11: A<6> 19: D<10>.PIN
|
|
4: AUTO_CONFIG_DONE<1> 12: D<12>_BUFR 20: RESET
|
|
5: AUTO_CONFIG_DONE_CYCLE<1> 13: D<13>_BUFR 21: RW
|
|
6: A<1> 14: D<14>_BUFR 22: UDS
|
|
7: A<2> 15: D<15>_BUFR 23: autoconfig
|
|
8: A<3> 16: IDE_BASEADR<2> 24: ide/ide_CLKF
|
|
|
|
Signal 1 2 3 4 FB
|
|
Name 0----+----0----+----0----+----0----+----0 Inputs
|
|
D<2> .X..................X................... 2
|
|
D<10> .X..................X................... 2
|
|
D<12> .X.........X........X................... 3
|
|
D<14> .X...........X......X................... 3
|
|
D<9> .X..................X................... 2
|
|
D<15> .X............X.....X................... 3
|
|
D<11> .X..................X................... 2
|
|
D<13> .X..........X.......X................... 3
|
|
AUTO_CONFIG_DONE<1> X...X................................... 2
|
|
AUTO_CONFIG_DONE_CYCLE<1>
|
|
X.XXXX.XXXX........XXXXX................ 14
|
|
IDE_BASEADR<3> X.XX.XXXXXX.....XX.XXXXX................ 16
|
|
IDE_BASEADR<2> X.XX.XXXXXX....X..XXXXXX................ 16
|
|
0----+----1----+----2----+----3----+----4
|
|
0 0 0 0
|
|
*********************************** FB4 ***********************************
|
|
Number of function block inputs used/remaining: 24/30
|
|
Number of signals used by logic mapping into function block: 24
|
|
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
|
Name Pt Pt Pt Pt # Type Use
|
|
ide 19 14<- 0 0 FB4_1 118 I/O (b)
|
|
(unused) 0 0 /\5 0 FB4_2 126 I/O (b)
|
|
(unused) 0 0 /\3 2 FB4_3 133 I/O (b)
|
|
(unused) 0 0 0 5 FB4_4 (b)
|
|
(unused) 0 0 0 5 FB4_5 128 I/O
|
|
(unused) 0 0 0 5 FB4_6 129 I/O
|
|
(unused) 0 0 0 5 FB4_7 (b)
|
|
(unused) 0 0 0 5 FB4_8 130 I/O
|
|
(unused) 0 0 0 5 FB4_9 131 I/O
|
|
(unused) 0 0 0 5 FB4_10 135 I/O
|
|
(unused) 0 0 0 5 FB4_11 132 I/O
|
|
(unused) 0 0 0 5 FB4_12 134 I/O
|
|
(unused) 0 0 0 5 FB4_13 137 I/O
|
|
(unused) 0 0 0 5 FB4_14 136 I/O
|
|
(unused) 0 0 0 5 FB4_15 138 I/O
|
|
ide/ide_CLKF 2 0 0 3 FB4_16 139 I/O (b)
|
|
autoconfig 4 0 \/1 0 FB4_17 140 I/O (b)
|
|
(unused) 0 0 \/5 0 FB4_18 (b) (b)
|
|
|
|
Signals Used by Logic in Function Block
|
|
1: AUTO_CONFIG_DONE<0> 9: A<21> 17: IDE_BASEADR<2>
|
|
2: AUTO_CONFIG_DONE<1> 10: A<22> 18: IDE_BASEADR<3>
|
|
3: AUTO_CONFIG_DONE<2> 11: A<23> 19: IDE_BASEADR<4>
|
|
4: A<16> 12: BERR 20: IDE_BASEADR<5>
|
|
5: A<17> 13: C1 21: IDE_BASEADR<6>
|
|
6: A<18> 14: C3 22: IDE_BASEADR<7>
|
|
7: A<19> 15: IDE_BASEADR<0> 23: SHUT_UP<1>
|
|
8: A<20> 16: IDE_BASEADR<1> 24: ide/ide_CLKF
|
|
|
|
Signal 1 2 3 4 FB
|
|
Name 0----+----0----+----0----+----0----+----0 Inputs
|
|
ide ...XXXXXXXXX..XXXXXXXXXX................ 19
|
|
ide/ide_CLKF ............XX.......................... 2
|
|
autoconfig XXXXXXXXXXXX...........X................ 13
|
|
0----+----1----+----2----+----3----+----4
|
|
0 0 0 0
|
|
*********************************** FB5 ***********************************
|
|
Number of function block inputs used/remaining: 23/31
|
|
Number of signals used by logic mapping into function block: 23
|
|
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
|
Name Pt Pt Pt Pt # Type Use
|
|
(unused) 0 0 0 5 FB5_1 (b)
|
|
(unused) 0 0 0 5 FB5_2 52 I/O I
|
|
(unused) 0 0 0 5 FB5_3 59 I/O I
|
|
(unused) 0 0 0 5 FB5_4 (b)
|
|
(unused) 0 0 0 5 FB5_5 53 I/O
|
|
(unused) 0 0 0 5 FB5_6 54 I/O I
|
|
(unused) 0 0 0 5 FB5_7 66 I/O
|
|
(unused) 0 0 0 5 FB5_8 56 I/O
|
|
(unused) 0 0 0 5 FB5_9 57 I/O I
|
|
ROM_B<0> 0 0 0 5 FB5_10 68 I/O O
|
|
(unused) 0 0 0 5 FB5_11 58 I/O I
|
|
(unused) 0 0 0 5 FB5_12 60 I/O I
|
|
SHUT_UP<1> 3 0 0 2 FB5_13 70 I/O (b)
|
|
IDE_BASEADR<5> 4 0 0 1 FB5_14 61 I/O I
|
|
IDE_BASEADR<4> 4 0 0 1 FB5_15 64 I/O I
|
|
IDE_BASEADR<1> 4 0 0 1 FB5_16 (b) (b)
|
|
ROM_B<1> 0 0 0 5 FB5_17 69 I/O O
|
|
IDE_BASEADR<0> 4 0 0 1 FB5_18 (b) (b)
|
|
|
|
Signals Used by Logic in Function Block
|
|
1: AS 9: A<6> 17: D<9>.PIN
|
|
2: AUTO_CONFIG_DONE<0> 10: IDE_BASEADR<0> 18: RESET
|
|
3: AUTO_CONFIG_DONE<1> 11: IDE_BASEADR<1> 19: RW
|
|
4: A<1> 12: IDE_BASEADR<4> 20: SHUT_UP<1>
|
|
5: A<2> 13: IDE_BASEADR<5> 21: UDS
|
|
6: A<3> 14: D<12>.PIN 22: autoconfig
|
|
7: A<4> 15: D<13>.PIN 23: ide/ide_CLKF
|
|
8: A<5> 16: D<8>.PIN
|
|
|
|
Signal 1 2 3 4 FB
|
|
Name 0----+----0----+----0----+----0----+----0 Inputs
|
|
ROM_B<0> ........................................ 0
|
|
SHUT_UP<1> XXXXXXXXX........XXXXXX................. 15
|
|
IDE_BASEADR<5> XXXXXXXXX...X.X..XX.XXX................. 16
|
|
IDE_BASEADR<4> XXXXXXXXX..X.X...XX.XXX................. 16
|
|
IDE_BASEADR<1> XXXXXXXXX.X.....XXX.XXX................. 16
|
|
ROM_B<1> ........................................ 0
|
|
IDE_BASEADR<0> XXXXXXXXXX.....X.XX.XXX................. 16
|
|
0----+----1----+----2----+----3----+----4
|
|
0 0 0 0
|
|
*********************************** FB6 ***********************************
|
|
Number of function block inputs used/remaining: 15/39
|
|
Number of signals used by logic mapping into function block: 15
|
|
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
|
Name Pt Pt Pt Pt # Type Use
|
|
(unused) 0 0 0 5 FB6_1 (b)
|
|
(unused) 0 0 0 5 FB6_2 106 I/O
|
|
(unused) 0 0 0 5 FB6_3 (b)
|
|
(unused) 0 0 0 5 FB6_4 111 I/O
|
|
(unused) 0 0 0 5 FB6_5 110 I/O
|
|
(unused) 0 0 0 5 FB6_6 112 I/O
|
|
(unused) 0 0 0 5 FB6_7 (b)
|
|
(unused) 0 0 0 5 FB6_8 113 I/O
|
|
(unused) 0 0 0 5 FB6_9 116 I/O
|
|
(unused) 0 0 0 5 FB6_10 115 I/O
|
|
(unused) 0 0 0 5 FB6_11 119 I/O
|
|
(unused) 0 0 0 5 FB6_12 120 I/O
|
|
(unused) 0 0 0 5 FB6_13 (b)
|
|
(unused) 0 0 0 5 FB6_14 121 I/O
|
|
(unused) 0 0 0 5 FB6_15 124 I/O
|
|
(unused) 0 0 \/4 1 FB6_16 117 I/O (b)
|
|
D<15>_BUFR 14 9<- 0 0 FB6_17 125 I/O (b)
|
|
(unused) 0 0 /\5 0 FB6_18 (b) (b)
|
|
|
|
Signals Used by Logic in Function Block
|
|
1: AS 6: A<2> 11: D<15>
|
|
2: AUTO_CONFIG_DONE<0> 7: A<3> 12: RESET
|
|
3: AUTO_CONFIG_DONE<1> 8: A<4> 13: RW
|
|
4: AUTO_CONFIG_DONE<2> 9: A<5> 14: autoconfig
|
|
5: A<1> 10: A<6> 15: ide/ide_CLKF
|
|
|
|
Signal 1 2 3 4 FB
|
|
Name 0----+----0----+----0----+----0----+----0 Inputs
|
|
D<15>_BUFR XXXXXXXXXXXXXXX......................... 15
|
|
0----+----1----+----2----+----3----+----4
|
|
0 0 0 0
|
|
*********************************** FB7 ***********************************
|
|
Number of function block inputs used/remaining: 0/54
|
|
Number of signals used by logic mapping into function block: 0
|
|
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
|
Name Pt Pt Pt Pt # Type Use
|
|
(unused) 0 0 0 5 FB7_1 (b)
|
|
(unused) 0 0 0 5 FB7_2 71 I/O
|
|
(unused) 0 0 0 5 FB7_3 75 I/O I
|
|
(unused) 0 0 0 5 FB7_4 (b)
|
|
(unused) 0 0 0 5 FB7_5 74 I/O
|
|
(unused) 0 0 0 5 FB7_6 76 I/O
|
|
(unused) 0 0 0 5 FB7_7 77 I/O
|
|
(unused) 0 0 0 5 FB7_8 78 I/O
|
|
(unused) 0 0 0 5 FB7_9 80 I/O I
|
|
(unused) 0 0 0 5 FB7_10 79 I/O
|
|
(unused) 0 0 0 5 FB7_11 82 I/O
|
|
DTACK 0 0 0 5 FB7_12 85 I/O O
|
|
(unused) 0 0 0 5 FB7_13 81 I/O I
|
|
(unused) 0 0 0 5 FB7_14 86 I/O I
|
|
(unused) 0 0 0 5 FB7_15 87 I/O I
|
|
(unused) 0 0 0 5 FB7_16 83 I/O I
|
|
(unused) 0 0 0 5 FB7_17 88 I/O I
|
|
(unused) 0 0 0 5 FB7_18 (b)
|
|
|
|
Signals Used by Logic in Function Block
|
|
|
|
Signal 1 2 3 4 FB
|
|
Name 0----+----0----+----0----+----0----+----0 Inputs
|
|
DTACK ........................................ 0
|
|
0----+----1----+----2----+----3----+----4
|
|
0 0 0 0
|
|
*********************************** FB8 ***********************************
|
|
Number of function block inputs used/remaining: 0/54
|
|
Number of signals used by logic mapping into function block: 0
|
|
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
|
Name Pt Pt Pt Pt # Type Use
|
|
(unused) 0 0 0 5 FB8_1 (b)
|
|
(unused) 0 0 0 5 FB8_2 91 I/O I
|
|
(unused) 0 0 0 5 FB8_3 95 I/O I
|
|
(unused) 0 0 0 5 FB8_4 97 I/O I
|
|
(unused) 0 0 0 5 FB8_5 92 I/O I
|
|
(unused) 0 0 0 5 FB8_6 93 I/O
|
|
(unused) 0 0 0 5 FB8_7 (b)
|
|
(unused) 0 0 0 5 FB8_8 94 I/O I
|
|
(unused) 0 0 0 5 FB8_9 96 I/O
|
|
(unused) 0 0 0 5 FB8_10 101 I/O
|
|
(unused) 0 0 0 5 FB8_11 98 I/O I
|
|
(unused) 0 0 0 5 FB8_12 100 I/O
|
|
(unused) 0 0 0 5 FB8_13 103 I/O I
|
|
(unused) 0 0 0 5 FB8_14 102 I/O I
|
|
(unused) 0 0 0 5 FB8_15 104 I/O
|
|
(unused) 0 0 0 5 FB8_16 107 I/O
|
|
(unused) 0 0 0 5 FB8_17 105 I/O
|
|
(unused) 0 0 0 5 FB8_18 (b)
|
|
******************************* Equations ********************************
|
|
|
|
********** Mapped Logic **********
|
|
|
|
FDCPE_AUTOCONFIG_IN_PROGRESS: FDCPE port map (AUTOCONFIG_IN_PROGRESS,AUTOCONFIG_IN_PROGRESS_D,ide/ide_CLKF,'0','0');
|
|
AUTOCONFIG_IN_PROGRESS_D <= (NOT AS AND autoconfig);
|
|
|
|
FDCPE_AUTO_CONFIG_DONE0: FDCPE port map (AUTO_CONFIG_DONE(0),AUTO_CONFIG_DONE_CYCLE(0),AS,NOT RESET,'0');
|
|
|
|
FDCPE_AUTO_CONFIG_DONE1: FDCPE port map (AUTO_CONFIG_DONE(1),AUTO_CONFIG_DONE_CYCLE(1),AS,NOT RESET,'0');
|
|
|
|
FDCPE_AUTO_CONFIG_DONE2: FDCPE port map (AUTO_CONFIG_DONE(2),AUTO_CONFIG_DONE_CYCLE(2),AS,NOT RESET,'0');
|
|
|
|
FDCPE_AUTO_CONFIG_DONE_CYCLE0: FDCPE port map (AUTO_CONFIG_DONE_CYCLE(0),AUTO_CONFIG_DONE_CYCLE_D(0),ide/ide_CLKF,'0','0');
|
|
AUTO_CONFIG_DONE_CYCLE_D(0) <= ((RESET AND AUTO_CONFIG_DONE_CYCLE(0))
|
|
OR (RESET AND NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND
|
|
A(6) AND A(3) AND NOT AUTO_CONFIG_DONE(0) AND autoconfig));
|
|
|
|
FDCPE_AUTO_CONFIG_DONE_CYCLE1: FDCPE port map (AUTO_CONFIG_DONE_CYCLE(1),AUTO_CONFIG_DONE_CYCLE_D(1),ide/ide_CLKF,'0','0');
|
|
AUTO_CONFIG_DONE_CYCLE_D(1) <= ((RESET AND AUTO_CONFIG_DONE_CYCLE(1))
|
|
OR (RESET AND NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND
|
|
A(6) AND A(3) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND
|
|
autoconfig));
|
|
|
|
FDCPE_AUTO_CONFIG_DONE_CYCLE2: FDCPE port map (AUTO_CONFIG_DONE_CYCLE(2),AUTO_CONFIG_DONE_CYCLE_D(2),ide/ide_CLKF,'0','0');
|
|
AUTO_CONFIG_DONE_CYCLE_D(2) <= ((RESET AND AUTO_CONFIG_DONE_CYCLE(2))
|
|
OR (RESET AND NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND
|
|
A(6) AND A(3) AND AUTO_CONFIG_DONE(0) AND AUTO_CONFIG_DONE(1) AND
|
|
NOT AUTO_CONFIG_DONE(2) AND autoconfig));
|
|
|
|
|
|
D_I(0) <= '1';
|
|
D(0) <= D_I(0) when D_OE(0) = '1' else 'Z';
|
|
D_OE(0) <= (RW AND AUTOCONFIG_IN_PROGRESS);
|
|
|
|
|
|
D_I(1) <= '1';
|
|
D(1) <= D_I(1) when D_OE(1) = '1' else 'Z';
|
|
D_OE(1) <= (RW AND AUTOCONFIG_IN_PROGRESS);
|
|
|
|
|
|
D_I(2) <= '1';
|
|
D(2) <= D_I(2) when D_OE(2) = '1' else 'Z';
|
|
D_OE(2) <= (RW AND AUTOCONFIG_IN_PROGRESS);
|
|
|
|
|
|
D_I(3) <= '1';
|
|
D(3) <= D_I(3) when D_OE(3) = '1' else 'Z';
|
|
D_OE(3) <= (RW AND AUTOCONFIG_IN_PROGRESS);
|
|
|
|
|
|
D_I(4) <= '1';
|
|
D(4) <= D_I(4) when D_OE(4) = '1' else 'Z';
|
|
D_OE(4) <= (RW AND AUTOCONFIG_IN_PROGRESS);
|
|
|
|
|
|
D_I(5) <= '1';
|
|
D(5) <= D_I(5) when D_OE(5) = '1' else 'Z';
|
|
D_OE(5) <= (RW AND AUTOCONFIG_IN_PROGRESS);
|
|
|
|
|
|
D_I(6) <= '1';
|
|
D(6) <= D_I(6) when D_OE(6) = '1' else 'Z';
|
|
D_OE(6) <= (RW AND AUTOCONFIG_IN_PROGRESS);
|
|
|
|
|
|
D_I(7) <= '1';
|
|
D(7) <= D_I(7) when D_OE(7) = '1' else 'Z';
|
|
D_OE(7) <= (RW AND AUTOCONFIG_IN_PROGRESS);
|
|
|
|
|
|
D_I(8) <= '1';
|
|
D(8) <= D_I(8) when D_OE(8) = '1' else 'Z';
|
|
D_OE(8) <= (RW AND AUTOCONFIG_IN_PROGRESS);
|
|
|
|
|
|
D_I(9) <= '1';
|
|
D(9) <= D_I(9) when D_OE(9) = '1' else 'Z';
|
|
D_OE(9) <= (RW AND AUTOCONFIG_IN_PROGRESS);
|
|
|
|
|
|
D_I(10) <= '1';
|
|
D(10) <= D_I(10) when D_OE(10) = '1' else 'Z';
|
|
D_OE(10) <= (RW AND AUTOCONFIG_IN_PROGRESS);
|
|
|
|
|
|
D_I(11) <= '1';
|
|
D(11) <= D_I(11) when D_OE(11) = '1' else 'Z';
|
|
D_OE(11) <= (RW AND AUTOCONFIG_IN_PROGRESS);
|
|
|
|
FDCPE_D12_BUFR: FDCPE port map (D(12)_BUFR,D_D(12)_BUFR,ide/ide_CLKF,'0','0');
|
|
D_D(12)_BUFR <= ((RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND A(6) AND NOT A(3) AND
|
|
NOT A(2) AND NOT AUTO_CONFIG_DONE(0) AND autoconfig)
|
|
OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND A(6) AND NOT A(3) AND
|
|
NOT A(2) AND NOT AUTO_CONFIG_DONE(1) AND autoconfig)
|
|
OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND A(6) AND NOT A(3) AND
|
|
NOT A(2) AND NOT AUTO_CONFIG_DONE(2) AND autoconfig)
|
|
OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(1) AND NOT A(6) AND NOT A(3) AND
|
|
A(2) AND NOT AUTO_CONFIG_DONE(0) AND autoconfig)
|
|
OR (RESET AND RW AND NOT AS AND A(5) AND NOT A(4) AND A(1) AND NOT A(6) AND
|
|
A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND
|
|
autoconfig)
|
|
OR (ROM_OE_S.EXP)
|
|
OR (RESET AND NOT D(12) AND NOT RW)
|
|
OR (RESET AND NOT D(12) AND AS)
|
|
OR (RESET AND NOT D(12) AND NOT autoconfig)
|
|
OR (RESET AND NOT D(12) AND AUTO_CONFIG_DONE(0) AND
|
|
AUTO_CONFIG_DONE(1) AND AUTO_CONFIG_DONE(2))
|
|
OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND NOT A(3) AND
|
|
NOT A(2) AND NOT AUTO_CONFIG_DONE(0) AND autoconfig)
|
|
OR (RESET AND RW AND NOT AS AND NOT A(4) AND A(1) AND NOT A(6) AND NOT A(3) AND
|
|
A(2) AND NOT AUTO_CONFIG_DONE(0) AND autoconfig)
|
|
OR (RESET AND RW AND NOT AS AND NOT A(5) AND A(4) AND NOT A(6) AND A(3) AND
|
|
NOT A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND
|
|
autoconfig)
|
|
OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND NOT A(3) AND
|
|
NOT A(2) AND AUTO_CONFIG_DONE(1) AND NOT AUTO_CONFIG_DONE(2) AND
|
|
autoconfig)
|
|
OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND NOT A(3) AND
|
|
NOT A(2) AND NOT AUTO_CONFIG_DONE(1) AND AUTOBOOT_OFF AND autoconfig));
|
|
|
|
|
|
D_I(12) <= D(12)_BUFR;
|
|
D(12) <= D_I(12) when D_OE(12) = '1' else 'Z';
|
|
D_OE(12) <= (RW AND AUTOCONFIG_IN_PROGRESS);
|
|
|
|
FDCPE_D13_BUFR: FDCPE port map (D(13)_BUFR,D_D(13)_BUFR,ide/ide_CLKF,'0','0');
|
|
D_D(13)_BUFR <= ((IDE_BASEADR(6).EXP)
|
|
OR (RESET AND NOT D(13) AND NOT RW)
|
|
OR (RESET AND NOT D(13) AND AUTO_CONFIG_DONE(0) AND
|
|
AUTO_CONFIG_DONE(1) AND AUTO_CONFIG_DONE(2))
|
|
OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(6) AND NOT A(3) AND
|
|
NOT AUTO_CONFIG_DONE(0) AND autoconfig)
|
|
OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(3) AND NOT A(2) AND
|
|
NOT AUTO_CONFIG_DONE(0) AND autoconfig)
|
|
OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(3) AND NOT A(2) AND
|
|
NOT AUTO_CONFIG_DONE(1) AND autoconfig)
|
|
OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(3) AND NOT A(2) AND
|
|
NOT AUTO_CONFIG_DONE(2) AND autoconfig)
|
|
OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND A(1) AND NOT A(6) AND
|
|
NOT A(3) AND NOT AUTO_CONFIG_DONE(1) AND autoconfig)
|
|
OR (RESET AND RW AND NOT AS AND NOT A(5) AND A(1) AND NOT A(6) AND NOT A(3) AND
|
|
NOT A(2) AND NOT AUTO_CONFIG_DONE(0) AND autoconfig)
|
|
OR (RESET AND RW AND NOT AS AND NOT A(5) AND A(4) AND NOT A(1) AND NOT A(6) AND
|
|
A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND
|
|
autoconfig)
|
|
OR (RESET AND NOT D(13) AND AS)
|
|
OR (RESET AND NOT D(13) AND NOT autoconfig)
|
|
OR (RESET AND RW AND NOT AS AND NOT A(5) AND A(4) AND NOT A(6) AND A(3) AND
|
|
A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND
|
|
autoconfig)
|
|
OR (RESET AND RW AND NOT AS AND NOT A(5) AND A(1) AND NOT A(6) AND NOT A(3) AND
|
|
NOT A(2) AND AUTO_CONFIG_DONE(1) AND NOT AUTO_CONFIG_DONE(2) AND
|
|
autoconfig));
|
|
|
|
|
|
D_I(13) <= D(13)_BUFR;
|
|
D(13) <= D_I(13) when D_OE(13) = '1' else 'Z';
|
|
D_OE(13) <= (RW AND AUTOCONFIG_IN_PROGRESS);
|
|
|
|
|
|
D_I(14) <= D(14)_BUFR;
|
|
D(14) <= D_I(14) when D_OE(14) = '1' else 'Z';
|
|
D_OE(14) <= (RW AND AUTOCONFIG_IN_PROGRESS);
|
|
|
|
FDCPE_D14_BUFR: FDCPE port map (D(14)_BUFR,D_D(14)_BUFR,ide/ide_CLKF,'0','0');
|
|
D_D(14)_BUFR <= ((EXP16_.EXP)
|
|
OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND A(1) AND NOT A(3) AND
|
|
NOT A(2) AND NOT AUTO_CONFIG_DONE(0) AND autoconfig)
|
|
OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND A(6) AND NOT A(3) AND
|
|
NOT A(2) AND NOT AUTO_CONFIG_DONE(0) AND autoconfig)
|
|
OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND A(6) AND NOT A(3) AND
|
|
NOT A(2) AND NOT AUTO_CONFIG_DONE(1) AND autoconfig)
|
|
OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND A(6) AND NOT A(3) AND
|
|
NOT A(2) AND NOT AUTO_CONFIG_DONE(2) AND autoconfig)
|
|
OR (RESET AND RW AND NOT AS AND NOT A(4) AND A(1) AND NOT A(6) AND NOT A(3) AND
|
|
A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND
|
|
autoconfig)
|
|
OR (RESET AND NOT D(14) AND NOT RW)
|
|
OR (RESET AND NOT D(14) AND AS)
|
|
OR (RESET AND NOT D(14) AND NOT autoconfig)
|
|
OR (RESET AND NOT D(14) AND AUTO_CONFIG_DONE(0) AND
|
|
AUTO_CONFIG_DONE(1) AND AUTO_CONFIG_DONE(2))
|
|
OR (RESET AND RW AND NOT AS AND NOT A(5) AND A(1) AND NOT A(6) AND NOT A(3) AND
|
|
A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(2) AND
|
|
autoconfig)
|
|
OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND A(1) AND NOT A(3) AND
|
|
NOT A(2) AND NOT AUTO_CONFIG_DONE(1) AND autoconfig)
|
|
OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND A(1) AND NOT A(3) AND
|
|
NOT A(2) AND NOT AUTO_CONFIG_DONE(2) AND autoconfig)
|
|
OR (RESET AND RW AND NOT AS AND NOT A(5) AND A(1) AND NOT A(6) AND NOT A(3) AND
|
|
A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND
|
|
autoconfig)
|
|
OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(6) AND NOT A(3) AND
|
|
A(2) AND AUTO_CONFIG_DONE(0) AND AUTO_CONFIG_DONE(1) AND
|
|
NOT AUTO_CONFIG_DONE(2) AND autoconfig));
|
|
|
|
|
|
D_I(15) <= D(15)_BUFR;
|
|
D(15) <= D_I(15) when D_OE(15) = '1' else 'Z';
|
|
D_OE(15) <= (RW AND AUTOCONFIG_IN_PROGRESS);
|
|
|
|
FDCPE_D15_BUFR: FDCPE port map (D(15)_BUFR,D_D(15)_BUFR,ide/ide_CLKF,'0','0');
|
|
D_D(15)_BUFR <= ((RESET AND NOT D(15) AND AUTO_CONFIG_DONE(0) AND
|
|
AUTO_CONFIG_DONE(1) AND AUTO_CONFIG_DONE(2))
|
|
OR (RESET AND RW AND NOT AS AND NOT A(5) AND A(1) AND NOT A(6) AND NOT A(3) AND
|
|
NOT AUTO_CONFIG_DONE(0) AND autoconfig)
|
|
OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND A(6) AND NOT A(3) AND
|
|
NOT A(2) AND NOT AUTO_CONFIG_DONE(0) AND autoconfig)
|
|
OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND A(6) AND NOT A(3) AND
|
|
NOT A(2) AND NOT AUTO_CONFIG_DONE(1) AND autoconfig)
|
|
OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND A(6) AND NOT A(3) AND
|
|
NOT A(2) AND NOT AUTO_CONFIG_DONE(2) AND autoconfig)
|
|
OR (RESET AND RW AND NOT AS AND NOT A(5) AND A(1) AND NOT A(6) AND NOT A(3) AND
|
|
AUTO_CONFIG_DONE(1) AND NOT AUTO_CONFIG_DONE(2) AND autoconfig)
|
|
OR (RESET AND RW AND NOT AS AND NOT A(5) AND A(4) AND A(1) AND NOT A(6) AND
|
|
A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND
|
|
autoconfig)
|
|
OR (RESET AND RW AND NOT AS AND A(5) AND NOT A(4) AND NOT A(1) AND NOT A(6) AND
|
|
NOT A(3) AND A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND
|
|
autoconfig)
|
|
OR (RESET AND RW AND NOT AS AND NOT A(5) AND A(4) AND NOT A(1) AND NOT A(6) AND
|
|
A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND
|
|
autoconfig)
|
|
OR (RESET AND NOT D(15) AND NOT RW)
|
|
OR (RESET AND NOT D(15) AND AS)
|
|
OR (RESET AND NOT D(15) AND NOT autoconfig)
|
|
OR (RESET AND RW AND NOT AS AND NOT A(5) AND A(1) AND NOT A(6) AND NOT A(3) AND
|
|
NOT A(2) AND NOT AUTO_CONFIG_DONE(1) AND autoconfig));
|
|
|
|
|
|
DTACK_I <= '0';
|
|
DTACK <= DTACK_I when DTACK_OE = '1' else 'Z';
|
|
DTACK_OE <= '0';
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
IDE_A(0) <= A(9);
|
|
|
|
|
|
IDE_A(1) <= A(10);
|
|
|
|
|
|
IDE_A(2) <= A(11);
|
|
|
|
FTCPE_IDE_BASEADR0: FTCPE port map (IDE_BASEADR(0),IDE_BASEADR_T(0),ide/ide_CLKF,'0','0');
|
|
IDE_BASEADR_T(0) <= ((NOT RESET AND NOT IDE_BASEADR(0))
|
|
OR (NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND A(6) AND
|
|
A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND
|
|
NOT IDE_BASEADR(0) AND autoconfig AND D(8).PIN)
|
|
OR (RESET AND NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND
|
|
A(6) AND A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND
|
|
NOT AUTO_CONFIG_DONE(1) AND IDE_BASEADR(0) AND autoconfig AND NOT D(8).PIN));
|
|
|
|
FTCPE_IDE_BASEADR1: FTCPE port map (IDE_BASEADR(1),IDE_BASEADR_T(1),ide/ide_CLKF,'0','0');
|
|
IDE_BASEADR_T(1) <= ((NOT RESET AND NOT IDE_BASEADR(1))
|
|
OR (NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND A(6) AND
|
|
A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND
|
|
NOT IDE_BASEADR(1) AND autoconfig AND D(9).PIN)
|
|
OR (RESET AND NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND
|
|
A(6) AND A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND
|
|
NOT AUTO_CONFIG_DONE(1) AND IDE_BASEADR(1) AND autoconfig AND NOT D(9).PIN));
|
|
|
|
FTCPE_IDE_BASEADR2: FTCPE port map (IDE_BASEADR(2),IDE_BASEADR_T(2),ide/ide_CLKF,'0','0');
|
|
IDE_BASEADR_T(2) <= ((NOT RESET AND NOT IDE_BASEADR(2))
|
|
OR (NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND A(6) AND
|
|
A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND
|
|
NOT IDE_BASEADR(2) AND autoconfig AND D(10).PIN)
|
|
OR (RESET AND NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND
|
|
A(6) AND A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND
|
|
NOT AUTO_CONFIG_DONE(1) AND IDE_BASEADR(2) AND autoconfig AND NOT D(10).PIN));
|
|
|
|
FTCPE_IDE_BASEADR3: FTCPE port map (IDE_BASEADR(3),IDE_BASEADR_T(3),ide/ide_CLKF,'0','0');
|
|
IDE_BASEADR_T(3) <= ((NOT RESET AND NOT IDE_BASEADR(3))
|
|
OR (NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND A(6) AND
|
|
A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND
|
|
NOT IDE_BASEADR(3) AND autoconfig AND D(11).PIN)
|
|
OR (RESET AND NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND
|
|
A(6) AND A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND
|
|
NOT AUTO_CONFIG_DONE(1) AND IDE_BASEADR(3) AND autoconfig AND NOT D(11).PIN));
|
|
|
|
FTCPE_IDE_BASEADR4: FTCPE port map (IDE_BASEADR(4),IDE_BASEADR_T(4),ide/ide_CLKF,'0','0');
|
|
IDE_BASEADR_T(4) <= ((NOT RESET AND NOT IDE_BASEADR(4))
|
|
OR (NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND A(6) AND
|
|
A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND
|
|
NOT IDE_BASEADR(4) AND autoconfig AND D(12).PIN)
|
|
OR (RESET AND NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND
|
|
A(6) AND A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND
|
|
NOT AUTO_CONFIG_DONE(1) AND IDE_BASEADR(4) AND autoconfig AND NOT D(12).PIN));
|
|
|
|
FTCPE_IDE_BASEADR5: FTCPE port map (IDE_BASEADR(5),IDE_BASEADR_T(5),ide/ide_CLKF,'0','0');
|
|
IDE_BASEADR_T(5) <= ((NOT RESET AND NOT IDE_BASEADR(5))
|
|
OR (NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND A(6) AND
|
|
A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND
|
|
NOT IDE_BASEADR(5) AND autoconfig AND D(13).PIN)
|
|
OR (RESET AND NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND
|
|
A(6) AND A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND
|
|
NOT AUTO_CONFIG_DONE(1) AND IDE_BASEADR(5) AND autoconfig AND NOT D(13).PIN));
|
|
|
|
FTCPE_IDE_BASEADR6: FTCPE port map (IDE_BASEADR(6),IDE_BASEADR_T(6),ide/ide_CLKF,'0','0');
|
|
IDE_BASEADR_T(6) <= ((NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND A(6) AND
|
|
A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND
|
|
NOT IDE_BASEADR(6) AND autoconfig AND D(14).PIN)
|
|
OR (RESET AND NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND
|
|
A(6) AND A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND
|
|
NOT AUTO_CONFIG_DONE(1) AND IDE_BASEADR(6) AND autoconfig AND NOT D(14).PIN)
|
|
OR (NOT RESET AND NOT IDE_BASEADR(6)));
|
|
|
|
FTCPE_IDE_BASEADR7: FTCPE port map (IDE_BASEADR(7),IDE_BASEADR_T(7),ide/ide_CLKF,'0','0');
|
|
IDE_BASEADR_T(7) <= ((RESET AND NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND
|
|
A(6) AND A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND
|
|
NOT AUTO_CONFIG_DONE(1) AND IDE_BASEADR(7) AND autoconfig AND NOT D(15).PIN)
|
|
OR (NOT RESET AND NOT IDE_BASEADR(7))
|
|
OR (NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND A(6) AND
|
|
A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND
|
|
NOT IDE_BASEADR(7) AND autoconfig AND D(15).PIN));
|
|
|
|
|
|
IDE_CS(0) <= NOT A(12);
|
|
|
|
|
|
IDE_CS(1) <= NOT A(13);
|
|
|
|
FDCPE_IDE_ENABLE: FDCPE port map (IDE_ENABLE,IDE_ENABLE_D,ide/ide_CLKF,'0','0');
|
|
IDE_ENABLE_D <= ((RESET AND NOT IDE_ENABLE)
|
|
OR (RESET AND NOT RW AND NOT AS AND ide));
|
|
|
|
FDCPE_IDE_R: FDCPE port map (IDE_R,IDE_R_D,ide/ide_CLKF,'0','0');
|
|
IDE_R_D <= (RESET AND RW AND NOT AS AND NOT IDE_ENABLE AND ide);
|
|
|
|
FDCPE_IDE_W: FDCPE port map (IDE_W,IDE_W_D,ide/ide_CLKF,'0','0');
|
|
IDE_W_D <= (RESET AND NOT RW AND NOT AS AND ide);
|
|
|
|
|
|
ROM_B(0) <= '0';
|
|
|
|
|
|
ROM_B(1) <= '0';
|
|
|
|
FDCPE_ROM_OE: FDCPE port map (ROM_OE,ROM_OE_D,ide/ide_CLKF,'0','0');
|
|
ROM_OE_D <= (RESET AND RW AND NOT AS AND IDE_ENABLE AND ide);
|
|
|
|
FDCPE_SHUT_UP1: FDCPE port map (SHUT_UP(1),SHUT_UP_D(1),ide/ide_CLKF,'0','0');
|
|
SHUT_UP_D(1) <= ((RESET AND NOT SHUT_UP(1))
|
|
OR (RESET AND NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND
|
|
A(6) AND A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND
|
|
NOT AUTO_CONFIG_DONE(1) AND autoconfig));
|
|
|
|
FDCPE_autoconfig: FDCPE port map (autoconfig,autoconfig_D,ide/ide_CLKF,'0','0');
|
|
autoconfig_D <= ((A(23) AND A(22) AND A(21) AND A(19) AND
|
|
NOT AUTO_CONFIG_DONE(0) AND BERR AND NOT A(17) AND NOT A(16) AND NOT A(20) AND NOT A(18))
|
|
OR (A(23) AND A(22) AND A(21) AND A(19) AND
|
|
NOT AUTO_CONFIG_DONE(1) AND BERR AND NOT A(17) AND NOT A(16) AND NOT A(20) AND NOT A(18))
|
|
OR (A(23) AND A(22) AND A(21) AND A(19) AND
|
|
NOT AUTO_CONFIG_DONE(2) AND BERR AND NOT A(17) AND NOT A(16) AND NOT A(20) AND NOT A(18)));
|
|
|
|
FDCPE_ide: FDCPE port map (ide,ide_D,ide/ide_CLKF,'0','0');
|
|
ide_D <= ((SHUT_UP(1))
|
|
OR (NOT BERR)
|
|
OR (EXP20_.EXP)
|
|
OR (A(23) AND NOT IDE_BASEADR(7))
|
|
OR (NOT A(23) AND IDE_BASEADR(7))
|
|
OR (A(22) AND NOT IDE_BASEADR(6))
|
|
OR (NOT A(22) AND IDE_BASEADR(6))
|
|
OR (IDE_BASEADR(1) AND NOT A(17))
|
|
OR (autoconfig.EXP)
|
|
OR (IDE_BASEADR(0) AND NOT A(16))
|
|
OR (NOT IDE_BASEADR(0) AND A(16))
|
|
OR (NOT IDE_BASEADR(1) AND A(17))
|
|
OR (IDE_BASEADR(2) AND NOT A(18))
|
|
OR (NOT IDE_BASEADR(2) AND A(18))
|
|
OR (A(19) AND NOT IDE_BASEADR(3))
|
|
OR (NOT A(19) AND IDE_BASEADR(3)));
|
|
|
|
|
|
ide/ide_CLKF <= NOT (C3
|
|
XOR
|
|
ide/ide_CLKF <= NOT (C1);
|
|
|
|
Register Legend:
|
|
FDCPE (Q,D,C,CLR,PRE,CE);
|
|
FTCPE (Q,D,C,CLR,PRE,CE);
|
|
LDCP (Q,D,G,CLR,PRE);
|
|
|
|
****************************** Device Pin Out *****************************
|
|
|
|
Device : XC95144XL-10-TQ144
|
|
|
|
|
|
Pin Signal Pin Signal
|
|
No. Name No. Name
|
|
1 VCC 73 VCC
|
|
2 D<0> 74 KPR
|
|
3 KPR 75 AUTOBOOT_OFF
|
|
4 KPR 76 KPR
|
|
5 KPR 77 KPR
|
|
6 KPR 78 KPR
|
|
7 KPR 79 KPR
|
|
8 VCC 80 AS
|
|
9 KPR 81 UDS
|
|
10 KPR 82 KPR
|
|
11 KPR 83 RW
|
|
12 KPR 84 VCC
|
|
13 KPR 85 DTACK
|
|
14 D<6> 86 A<23>
|
|
15 D<3> 87 A<22>
|
|
16 D<7> 88 A<21>
|
|
17 D<1> 89 GND
|
|
18 GND 90 GND
|
|
19 D<8> 91 A<20>
|
|
20 D<5> 92 A<19>
|
|
21 D<4> 93 KPR
|
|
22 IDE_CS<0> 94 A<18>
|
|
23 IDE_CS<1> 95 A<17>
|
|
24 IDE_A<0> 96 KPR
|
|
25 IDE_A<2> 97 A<16>
|
|
26 IDE_A<1> 98 BERR
|
|
27 IDE_R 99 GND
|
|
28 IDE_W 100 KPR
|
|
29 GND 101 KPR
|
|
30 KPR 102 C3
|
|
31 KPR 103 C1
|
|
32 KPR 104 KPR
|
|
33 KPR 105 KPR
|
|
34 KPR 106 KPR
|
|
35 ROM_OE 107 KPR
|
|
36 GND 108 GND
|
|
37 VCC 109 VCC
|
|
38 KPR 110 KPR
|
|
39 D<2> 111 KPR
|
|
40 D<9> 112 KPR
|
|
41 D<10> 113 KPR
|
|
42 VCC 114 GND
|
|
43 D<11> 115 KPR
|
|
44 D<12> 116 KPR
|
|
45 D<13> 117 KPR
|
|
46 D<14> 118 KPR
|
|
47 GND 119 KPR
|
|
48 D<15> 120 KPR
|
|
49 A<5> 121 KPR
|
|
50 A<4> 122 TDO
|
|
51 A<6> 123 GND
|
|
52 A<3> 124 KPR
|
|
53 KPR 125 KPR
|
|
54 A<2> 126 KPR
|
|
55 VCC 127 VCC
|
|
56 KPR 128 KPR
|
|
57 A<1> 129 KPR
|
|
58 A<9> 130 KPR
|
|
59 A<10> 131 KPR
|
|
60 A<11> 132 KPR
|
|
61 A<12> 133 KPR
|
|
62 GND 134 KPR
|
|
63 TDI 135 KPR
|
|
64 A<13> 136 KPR
|
|
65 TMS 137 KPR
|
|
66 KPR 138 KPR
|
|
67 TCK 139 KPR
|
|
68 ROM_B<0> 140 KPR
|
|
69 ROM_B<1> 141 VCC
|
|
70 KPR 142 KPR
|
|
71 KPR 143 RESET
|
|
72 GND 144 GND
|
|
|
|
|
|
Legend : NC = Not Connected, unbonded pin
|
|
PGND = Unused I/O configured as additional Ground pin
|
|
TIE = Unused I/O floating -- must tie to VCC, GND or other signal
|
|
KPR = Unused I/O with weak keeper (leave unconnected)
|
|
VCC = Dedicated Power Pin
|
|
GND = Dedicated Ground Pin
|
|
TDI = Test Data In, JTAG pin
|
|
TDO = Test Data Out, JTAG pin
|
|
TCK = Test Clock, JTAG pin
|
|
TMS = Test Mode Select, JTAG pin
|
|
PROHIBITED = User reserved pin
|
|
**************************** Compiler Options ****************************
|
|
|
|
Following is a list of all global compiler options used by the fitter run.
|
|
|
|
Device(s) Specified : xc95144xl-10-TQ144
|
|
Optimization Method : SPEED
|
|
Multi-Level Logic Optimization : ON
|
|
Ignore Timing Specifications : OFF
|
|
Default Register Power Up Value : LOW
|
|
Keep User Location Constraints : ON
|
|
What-You-See-Is-What-You-Get : OFF
|
|
Exhaustive Fitting : OFF
|
|
Keep Unused Inputs : OFF
|
|
Slew Rate : FAST
|
|
Power Mode : STD
|
|
Ground on Unused IOs : OFF
|
|
Set I/O Pin Termination : KEEPER
|
|
Global Clock Optimization : ON
|
|
Global Set/Reset Optimization : ON
|
|
Global Ouput Enable Optimization : ON
|
|
Input Limit : 54
|
|
Pterm Limit : 25
|