Dominick.Vansevenant/Zorro-LAN-IDE
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IDE & Autoconfig working

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MHeinrichs
2016-12-15 20:59:46 +01:00
parent 1440afbeeb
commit 508d7a7e5c
203 changed files with 26944 additions and 182 deletions
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Logic/LAN_IDE/LAN_IDE_CP.syr
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Release 14.6 - xst P.68d (nt64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--> Parameter TMPDIR set to xst/projnav.tmp
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.11 secs
--> Parameter xsthdpdir set to xst
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.11 secs
--> Reading design: LAN_IDE_CP.prj
TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Compilation
3) Design Hierarchy Analysis
4) HDL Analysis
5) HDL Synthesis
5.1) HDL Synthesis Report
6) Advanced HDL Synthesis
6.1) Advanced HDL Synthesis Report
7) Low Level Synthesis
8) Partition Report
9) Final Report
=========================================================================
* Synthesis Options Summary *
=========================================================================
---- Source Parameters
Input File Name : "LAN_IDE_CP.prj"
Input Format : mixed
Ignore Synthesis Constraint File : NO
---- Target Parameters
Output File Name : "LAN_IDE_CP"
Output Format : NGC
Target Device : XC9500XL CPLDs
---- Source Options
Top Module Name : LAN_IDE_CP
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
Safe Implementation : No
Mux Extraction : Yes
Resource Sharing : YES
---- Target Options
Add IO Buffers : YES
MACRO Preserve : YES
XOR Preserve : YES
Equivalent register Removal : YES
---- General Options
Optimization Goal : Speed
Optimization Effort : 1
Keep Hierarchy : Yes
Netlist Hierarchy : As_Optimized
RTL Output : Yes
Hierarchy Separator : /
Bus Delimiter : <>
Case Specifier : Maintain
Verilog 2001 : YES
---- Other Options
Clock Enable : YES
wysiwyg : NO
=========================================================================
=========================================================================
* HDL Compilation *
=========================================================================
Compiling vhdl file "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.vhd" in Library work.
Entity <lan_ide_cp> compiled.
Entity <lan_ide_cp> (Architecture <behavioral>) compiled.
=========================================================================
* Design Hierarchy Analysis *
=========================================================================
Analyzing hierarchy for entity <LAN_IDE_CP> in library <work> (architecture <behavioral>).
=========================================================================
* HDL Analysis *
=========================================================================
Analyzing Entity <LAN_IDE_CP> in library <work> (Architecture <behavioral>).
Entity <LAN_IDE_CP> analyzed. Unit <LAN_IDE_CP> generated.
=========================================================================
* HDL Synthesis *
=========================================================================
Performing bidirectional port resolution...
Synthesizing Unit <LAN_IDE_CP>.
Related source file is "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.vhd".
WARNING:Xst:2565 - Inout <DQ<0>> is never assigned.
WARNING:Xst:1306 - Output <SLAVE> is never assigned.
WARNING:Xst:647 - Input <IDE_WAIT> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:2565 - Inout <DQ<1>> is never assigned.
WARNING:Xst:647 - Input <LDS> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:1306 - Output <LAN_CS> is never assigned.
WARNING:Xst:2565 - Inout <DQ<2>> is never assigned.
WARNING:Xst:1306 - Output <LAN_EN> is never assigned.
WARNING:Xst:2565 - Inout <DQ<3>> is never assigned.
WARNING:Xst:2565 - Inout <DQ<4>> is never assigned.
WARNING:Xst:2565 - Inout <DQ<10>> is never assigned.
WARNING:Xst:2565 - Inout <DQ<5>> is never assigned.
WARNING:Xst:2565 - Inout <DQ<11>> is never assigned.
WARNING:Xst:2565 - Inout <DQ<6>> is never assigned.
WARNING:Xst:2565 - Inout <DQ<12>> is never assigned.
WARNING:Xst:1306 - Output <CFOUT> is never assigned.
WARNING:Xst:2565 - Inout <DQ<7>> is never assigned.
WARNING:Xst:2565 - Inout <DQ<13>> is never assigned.
WARNING:Xst:1306 - Output <LAN_WRH> is never assigned.
WARNING:Xst:647 - Input <DS0> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DS1> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:2565 - Inout <DQ<8>> is never assigned.
WARNING:Xst:2565 - Inout <DQ<14>> is never assigned.
WARNING:Xst:647 - Input <FCS> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:2565 - Inout <DQ<9>> is never assigned.
WARNING:Xst:2565 - Inout <DQ<15>> is never assigned.
WARNING:Xst:1306 - Output <CP_CS> is never assigned.
WARNING:Xst:1306 - Output <LAN_CFG> is never assigned.
WARNING:Xst:1306 - Output <MTACK> is never assigned.
WARNING:Xst:647 - Input <LAN_INT> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:1306 - Output <INT_OUT> is never assigned.
WARNING:Xst:1306 - Output <LAN_RD> is never assigned.
WARNING:Xst:2565 - Inout <A<14>> is never assigned.
WARNING:Xst:2565 - Inout <A<15>> is never assigned.
WARNING:Xst:647 - Input <CP_IRQ> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:1306 - Output <CP_RD> is never assigned.
WARNING:Xst:647 - Input <Z3> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:2565 - Inout <A<7>> is never assigned.
WARNING:Xst:2565 - Inout <A<8>> is never assigned.
WARNING:Xst:1306 - Output <CP_WE> is never assigned.
WARNING:Xst:647 - Input <CFIN> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <CLK_EXT> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:1306 - Output <OVR> is never assigned.
WARNING:Xst:1306 - Output <OWN> is never assigned.
WARNING:Xst:647 - Input <MTCR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:1306 - Output <A_LAN> is never assigned.
WARNING:Xst:646 - Signal <SHUT_UP<2>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <SHUT_UP<0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <LAN_BASEADR> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <DTACK_S> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <CP_BASEADR> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <AS_D> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
Found 1-bit tristate buffer for signal <DTACK>.
Found 16-bit tristate buffer for signal <$mux0000>.
Found 1-bit xor2 for signal <AMIGA_CLK$xor0000> created at line 108.
Found 3-bit register for signal <AUTO_CONFIG_DONE>.
Found 3-bit register for signal <AUTO_CONFIG_DONE_CYCLE>.
Found 1-bit register for signal <autoconfig>.
Found 1-bit register for signal <AUTOCONFIG_IN_PROGRESS>.
Found 4-bit register for signal <Dout1>.
Found 1-bit register for signal <ide>.
Found 8-bit comparator not equal for signal <ide$cmp_ne0000> created at line 126.
Found 8-bit register for signal <IDE_BASEADR>.
Found 1-bit register for signal <IDE_ENABLE>.
Found 1-bit register for signal <IDE_R_S>.
Found 1-bit register for signal <IDE_W_S>.
Found 1-bit register for signal <ROM_OE_S>.
Found 1-bit register for signal <SHUT_UP<1>>.
Summary:
inferred 1 Comparator(s).
inferred 1 Xor(s).
inferred 17 Tristate(s).
Unit <LAN_IDE_CP> synthesized.
=========================================================================
HDL Synthesis Report
Macro Statistics
# Registers : 14
1-bit register : 11
3-bit register : 1
4-bit register : 1
8-bit register : 1
# Comparators : 1
8-bit comparator not equal : 1
# Tristates : 2
1-bit tristate buffer : 1
16-bit tristate buffer : 1
# Xors : 1
1-bit xor2 : 1
=========================================================================
=========================================================================
* Advanced HDL Synthesis *
=========================================================================
=========================================================================
Advanced HDL Synthesis Report
Found no macro
=========================================================================
=========================================================================
* Low Level Synthesis *
=========================================================================
Optimizing unit <LAN_IDE_CP> ...
implementation constraint: INIT=r : IDE_ENABLE
implementation constraint: INIT=r : ide
implementation constraint: INIT=r : autoconfig
implementation constraint: INIT=s : IDE_R_S
implementation constraint: INIT=s : IDE_W_S
implementation constraint: INIT=s : ROM_OE_S
implementation constraint: INIT=r : AUTOCONFIG_IN_PROGRESS
=========================================================================
* Partition Report *
=========================================================================
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
=========================================================================
* Final Report *
=========================================================================
Final Results
RTL Top Level Output File Name : LAN_IDE_CP.ngr
Top Level Output File Name : LAN_IDE_CP
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : Yes
Target Technology : XC9500XL CPLDs
Macro Preserve : YES
XOR Preserve : YES
Clock Enable : YES
wysiwyg : NO
Design Statistics
# IOs : 116
Cell Usage :
# BELS : 322
# AND2 : 75
# AND3 : 16
# AND4 : 5
# AND5 : 1
# GND : 1
# INV : 138
# OR2 : 63
# OR3 : 13
# OR4 : 2
# OR5 : 1
# VCC : 1
# XOR2 : 6
# FlipFlops/Latches : 26
# FD : 6
# FDC : 3
# FDCE : 17
# IO Buffers : 54
# IBUF : 27
# IOBUFE : 8
# OBUF : 10
# OBUFE : 9
=========================================================================
Total REAL time to Xst completion: 7.00 secs
Total CPU time to Xst completion: 7.69 secs
-->
Total memory usage is 290044 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 52 ( 0 filtered)
Number of infos : 0 ( 0 filtered)