From 508d7a7e5cf4c4ac5882c8430dca32f354ed6c50 Mon Sep 17 00:00:00 2001 From: MHeinrichs Date: Thu, 15 Dec 2016 20:59:46 +0100 Subject: [PATCH] IDE & Autoconfig working --- Bilder/Aufgebaut.jpg | Bin 336548 -> 127586 bytes Bilder/Autoconfig.jpg | Bin 0 -> 58545 bytes Bilder/Hardware.jpg | Bin 0 -> 164237 bytes Logic/LAN_IDE/LAN_IDE.gise | 80 +- Logic/LAN_IDE/LAN_IDE.xise | 174 +- Logic/LAN_IDE/LAN_IDE_CP.bld | 58 + Logic/LAN_IDE/LAN_IDE_CP.cmd_log | 42 + Logic/LAN_IDE/LAN_IDE_CP.gyd | 90 + Logic/LAN_IDE/LAN_IDE_CP.jed | 1750 +++++++ Logic/LAN_IDE/LAN_IDE_CP.lfp | 0 Logic/LAN_IDE/LAN_IDE_CP.lso | 1 + Logic/LAN_IDE/LAN_IDE_CP.mfd | 1046 +++++ Logic/LAN_IDE/LAN_IDE_CP.nga | 3 + Logic/LAN_IDE/LAN_IDE_CP.ngc | 3 + Logic/LAN_IDE/LAN_IDE_CP.ngd | 3 + Logic/LAN_IDE/LAN_IDE_CP.ngr | 3 + Logic/LAN_IDE/LAN_IDE_CP.pad | 173 + Logic/LAN_IDE/LAN_IDE_CP.pnx | 18 + Logic/LAN_IDE/LAN_IDE_CP.prj | 1 + Logic/LAN_IDE/LAN_IDE_CP.rpt | 1167 +++++ Logic/LAN_IDE/LAN_IDE_CP.stx | 0 Logic/LAN_IDE/LAN_IDE_CP.syr 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zz*|uT@6-kpU;h9}Rg&P9L9sDV%kA0B0neZrzM=qa++y%b!x9H9O6l}PkA1JeF-Q$ebJ(4Zl&~ z_RPg<<;J!q4C*>OOE&Hy9D*w*ol5T7O7c{#_wetYX_72?j;B8tpN4b(9Q-oz{yfYK zCqD}+)NwKY0O4O27T|I_yzdC^TDVvJn!6L!ZEmF1TwqHE;6Sd;EsqcQYW@A zh9=Vg0K%Z&o+8*Ph?KV+W8nV)`LtEc5QvQ3rQ#+B;Hh~k{{V8v(sKbUUk)RG6)aNc zsFhwhluNs~gHY|27jOX)iaICl9|!p}bMNC3qHpT>e#tg{Pv$4-A+*|mG(SYt_cnTt zk5T?H(e8ev{mHcDIZhuQVa$Jw>(u5thcSdB4MuG^Jw_kY;W$0cS;ySc8k~HM$C&&Y zCtn=SPl54`&R>nE6PV6t6N$9s_~w5s=4~0o+x!Uc>TH@l&4_E`cNxS#ss852xwTMuiVk_`n}KHnlnTr KS^5)yhyU5dY>+Ad literal 0 HcmV?d00001 diff --git a/Logic/LAN_IDE/LAN_IDE.gise b/Logic/LAN_IDE/LAN_IDE.gise index 9973d4b..dbbc078 100644 --- a/Logic/LAN_IDE/LAN_IDE.gise +++ b/Logic/LAN_IDE/LAN_IDE.gise @@ -21,8 +21,84 @@ - + + + + + + + + + + + + + + + + + + + + + + + - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Logic/LAN_IDE/LAN_IDE.xise b/Logic/LAN_IDE/LAN_IDE.xise index ab3d1e6..fbbe06e 100644 --- a/Logic/LAN_IDE/LAN_IDE.xise +++ b/Logic/LAN_IDE/LAN_IDE.xise @@ -19,134 +19,63 @@ + + + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -158,15 +87,8 @@ - - - - - - - @@ -178,25 +100,14 @@ - - - + - - - - - - - + - - - @@ -204,16 +115,11 @@ - - - - - @@ -221,75 +127,35 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -298,33 +164,19 @@ - - - - - - - - + - - - - - - - @@ -334,34 +186,22 @@ - - - - - - - - + - - - - - diff --git a/Logic/LAN_IDE/LAN_IDE_CP.bld b/Logic/LAN_IDE/LAN_IDE_CP.bld new file mode 100644 index 0000000..46b5398 --- /dev/null +++ b/Logic/LAN_IDE/LAN_IDE_CP.bld @@ -0,0 +1,58 @@ +Release 14.6 ngdbuild P.68d (nt64) +Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. + +Command Line: C:\Xilinx\14.6\ISE_DS\ISE\bin\nt64\unwrapped\ngdbuild.exe +-intstyle ise -dd _ngo -uc pinlist.ucf -p xc95144xl-TQ144-10 LAN_IDE_CP.ngc +LAN_IDE_CP.ngd + +Reading NGO file +"C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.ngc" +... +Gathering constraint information from source properties... +Done. + +Annotating constraints to design from ucf file "pinlist.ucf" ... +Resolving constraint associations... +Checking Constraint Associations... +Done... + +Checking expanded design ... +WARNING:NgdBuild:470 - bidirect pad net 'DQ<0>' has no legal driver +WARNING:NgdBuild:470 - bidirect pad net 'DQ<1>' has no legal driver +WARNING:NgdBuild:470 - bidirect pad net 'DQ<2>' has no legal driver +WARNING:NgdBuild:470 - bidirect pad net 'DQ<3>' has no legal driver +WARNING:NgdBuild:470 - bidirect pad net 'DQ<4>' has no legal driver +WARNING:NgdBuild:470 - bidirect pad net 'DQ<10>' has no legal driver +WARNING:NgdBuild:470 - bidirect pad net 'DQ<5>' has no legal driver +WARNING:NgdBuild:470 - bidirect pad net 'DQ<11>' has no legal driver +WARNING:NgdBuild:470 - bidirect pad net 'DQ<6>' has no legal driver +WARNING:NgdBuild:470 - bidirect pad net 'DQ<12>' has no legal driver +WARNING:NgdBuild:470 - bidirect pad net 'DQ<7>' has no legal driver +WARNING:NgdBuild:470 - bidirect pad net 'DQ<13>' has no legal driver +WARNING:NgdBuild:470 - bidirect pad net 'DQ<8>' has no legal driver +WARNING:NgdBuild:470 - bidirect pad net 'DQ<14>' has no legal driver +WARNING:NgdBuild:470 - bidirect pad net 'DQ<9>' has no legal driver +WARNING:NgdBuild:470 - bidirect pad net 'DQ<15>' has no legal driver +WARNING:NgdBuild:470 - bidirect pad net 'A<14>' has no legal driver +WARNING:NgdBuild:470 - bidirect pad net 'A<15>' has no legal driver +WARNING:NgdBuild:470 - bidirect pad net 'A<7>' has no legal driver +WARNING:NgdBuild:470 - bidirect pad net 'A<8>' has no legal driver + +Partition Implementation Status +------------------------------- + + No Partitions were found in this design. + +------------------------------- + +NGDBUILD Design Results Summary: + Number of errors: 0 + Number of warnings: 20 + +Total memory usage is 190196 kilobytes + +Writing NGD file "LAN_IDE_CP.ngd" ... +Total REAL time to NGDBUILD completion: 5 sec +Total CPU time to NGDBUILD completion: 5 sec + +Writing NGDBUILD log file "LAN_IDE_CP.bld"... diff --git a/Logic/LAN_IDE/LAN_IDE_CP.cmd_log b/Logic/LAN_IDE/LAN_IDE_CP.cmd_log new file mode 100644 index 0000000..10909b3 --- /dev/null +++ b/Logic/LAN_IDE/LAN_IDE_CP.cmd_log @@ -0,0 +1,42 @@ +xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr" +ngdbuild -intstyle ise -dd _ngo -i -p xc95144xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd +xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr" +xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr" +xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr" +xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr" +xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr" +xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr" +xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr" +ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95144xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd +cpldfit -intstyle ise -p xc95144xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd +XSLTProcess LAN_IDE_CP_build.xml +tsim -intstyle ise LAN_IDE_CP LAN_IDE_CP.nga +taengine -intstyle ise -f LAN_IDE_CP -w --format html1 -l LAN_IDE_CP_html/tim/timing_report.htm +hprep6 -s IEEE1149 -n LAN_IDE_CP -i LAN_IDE_CP +xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr" +xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr" +ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95144xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd +cpldfit -intstyle ise -p xc95144xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd +XSLTProcess LAN_IDE_CP_build.xml +tsim -intstyle ise LAN_IDE_CP LAN_IDE_CP.nga +hprep6 -s IEEE1149 -n LAN_IDE_CP -i LAN_IDE_CP +xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr" +ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95144xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd +cpldfit -intstyle ise -p xc95144xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd +XSLTProcess LAN_IDE_CP_build.xml +tsim -intstyle ise LAN_IDE_CP LAN_IDE_CP.nga +hprep6 -s IEEE1149 -n LAN_IDE_CP -i LAN_IDE_CP +xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr" +xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr" +ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95144xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd +cpldfit -intstyle ise -p xc95144xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd +XSLTProcess LAN_IDE_CP_build.xml +tsim -intstyle ise LAN_IDE_CP LAN_IDE_CP.nga +hprep6 -s IEEE1149 -n LAN_IDE_CP -i LAN_IDE_CP +xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr" +xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr" +ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95144xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd +cpldfit -intstyle ise -p xc95144xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd +XSLTProcess LAN_IDE_CP_build.xml +tsim -intstyle ise LAN_IDE_CP LAN_IDE_CP.nga +hprep6 -s IEEE1149 -n LAN_IDE_CP -i LAN_IDE_CP diff --git a/Logic/LAN_IDE/LAN_IDE_CP.gyd b/Logic/LAN_IDE/LAN_IDE_CP.gyd new file mode 100644 index 0000000..788deb2 --- /dev/null +++ b/Logic/LAN_IDE/LAN_IDE_CP.gyd @@ -0,0 +1,90 @@ +Pin Freeze File: version P.68d + +95144XL144TQ XC95144XL-10-TQ144 +AS S:PIN80 +AUTOBOOT_OFF S:PIN75 +A<12> S:PIN61 +A<13> S:PIN64 +A<16> S:PIN97 +A<17> S:PIN95 +A<18> S:PIN94 +A<19> S:PIN92 +A<1> S:PIN57 +A<20> S:PIN91 +A<21> S:PIN88 +A<22> S:PIN87 +A<23> S:PIN86 +A<2> S:PIN54 +A<3> S:PIN52 +A<4> S:PIN50 +A<5> S:PIN49 +A<6> S:PIN51 +BERR S:PIN98 +C1 S:PIN103 +C3 S:PIN102 +A<9> S:PIN58 +A<10> S:PIN59 +A<11> S:PIN60 +RESET S:PIN143 +RW S:PIN83 +UDS S:PIN81 +IDE_A<0> S:PIN24 +IDE_A<1> S:PIN26 +IDE_A<2> S:PIN25 +IDE_CS<0> S:PIN22 +IDE_CS<1> S:PIN23 +IDE_R S:PIN27 +IDE_W S:PIN28 +D<9> S:PIN40 +D<8> S:PIN19 +D<7> S:PIN16 +D<0> S:PIN2 +D<6> S:PIN14 +D<5> S:PIN20 +D<4> S:PIN21 +D<3> S:PIN15 +D<2> S:PIN39 +D<1> S:PIN17 +D<11> S:PIN43 +D<10> S:PIN41 +ROM_B<1> S:PIN69 +ROM_B<0> S:PIN68 +DTACK S:PIN85 +ROM_OE S:PIN35 +D<12> S:PIN44 +D<14> S:PIN46 +D<13> S:PIN45 +D<15> S:PIN48 + + +;The remaining section of the .gyd file is for documentation purposes only. +;It shows where your internal equations were placed in the last successful fit. + +PARTITION FB1_1 IDE_CS_1_OBUF N1$BUF1 N1$BUF7 IDE_A_2_OBUF$BUF0 + N1$BUF0 N1$BUF3 AUTOCONFIG_IN_PROGRESS N1$BUF4 + IDE_CS_0_OBUF IDE_ENABLE IDE_A_0_OBUF$BUF0 IDE_A_1_OBUF$BUF0 + +PARTITION FB1_14 IDE_R_S IDE_W_S ROM_OE_S EXP14_ + D<12>_BUFR.MC +PARTITION FB2_1 D<14>_BUFR.MC EXP15_ EXP16_ +PARTITION FB2_5 N1$BUF10 +PARTITION FB2_8 AUTO_CONFIG_DONE<2> AUTO_CONFIG_DONE<0> AUTO_CONFIG_DONE_CYCLE<2> AUTO_CONFIG_DONE_CYCLE<0> + IDE_BASEADR<7> IDE_BASEADR<6> EXP17_ D<13>_BUFR.MC + N1$BUF2 N1$BUF5 EXP18_ +PARTITION FB3_1 N1$BUF6 +PARTITION FB3_3 N1$BUF9 _10_ +PARTITION FB3_7 _11_ +PARTITION FB3_9 N1 _13_ N1$BUF8 _12_ + +PARTITION FB3_15 AUTO_CONFIG_DONE<1> AUTO_CONFIG_DONE_CYCLE<1> IDE_BASEADR<3> IDE_BASEADR<2> + +PARTITION FB4_1 ide EXP19_ EXP20_ +PARTITION FB4_16 ide/ide_CLKF autoconfig EXP21_ +PARTITION FB5_10 ROM_B_0_OBUF$BUF0 +PARTITION FB5_13 SHUT_UP<1> IDE_BASEADR<5> IDE_BASEADR<4> IDE_BASEADR<1> + ROM_B_0_OBUF IDE_BASEADR<0> +PARTITION FB6_16 EXP22_ D<15>_BUFR.MC EXP23_ +PARTITION FB7_12 ROM_B_0_OBUF$BUF1 + + + diff --git a/Logic/LAN_IDE/LAN_IDE_CP.jed b/Logic/LAN_IDE/LAN_IDE_CP.jed new file mode 100644 index 0000000..3c09d1a --- /dev/null +++ b/Logic/LAN_IDE/LAN_IDE_CP.jed @@ -0,0 +1,1750 @@ +Programmer Jedec Bit Map +Date Extracted: Thu Dec 15 19:48:51 2016 + +QF93312* +QP144* +QV0* +F0* +X0* +J0 0* +N VERSION P.68d* +N DEVICE XC95144XL-10-TQ144* +N PPMAP 12 10* +N PPMAP 112 100* +N PPMAP 113 101* +N PPMAP 114 102* +N PPMAP 115 103* +N PPMAP 116 104* +N PPMAP 117 105* +N PPMAP 118 106* +N PPMAP 119 107* +N PPMAP 13 11* +N PPMAP 123 110* +N PPMAP 124 111* +N PPMAP 125 112* +N PPMAP 127 113* +N PPMAP 129 115* +N PPMAP 130 116* +N PPMAP 132 117* +N PPMAP 133 118* +N PPMAP 134 119* +N PPMAP 14 12* +N PPMAP 135 120* +N PPMAP 136 121* +N PPMAP 139 124* +N PPMAP 140 125* +N PPMAP 141 126* +N PPMAP 143 128* +N PPMAP 144 129* +N PPMAP 15 13* +N PPMAP 145 130* +N PPMAP 146 131* +N PPMAP 147 132* +N PPMAP 148 133* +N PPMAP 149 134* +N PPMAP 152 135* +N PPMAP 153 136* +N PPMAP 154 137* +N PPMAP 155 138* +N PPMAP 156 139* +N PPMAP 16 14* +N PPMAP 157 140* +N PPMAP 159 142* +N PPMAP 160 143* +N PPMAP 17 15* +N PPMAP 18 16* +N PPMAP 19 17* +N PPMAP 21 19* +N PPMAP 2 2* +N PPMAP 22 20* +N PPMAP 23 21* +N PPMAP 24 22* +N PPMAP 25 23* +N PPMAP 26 24* +N PPMAP 27 25* +N PPMAP 28 26* +N PPMAP 29 27* +N PPMAP 30 28* +N PPMAP 4 3* +N PPMAP 33 30* +N PPMAP 34 31* +N PPMAP 35 32* +N PPMAP 36 33* +N PPMAP 37 34* +N PPMAP 39 35* +N PPMAP 42 38* +N PPMAP 43 39* +N PPMAP 5 4* +N PPMAP 44 40* +N PPMAP 45 41* +N PPMAP 47 43* +N PPMAP 48 44* +N PPMAP 49 45* +N PPMAP 50 46* +N PPMAP 52 48* +N PPMAP 54 49* +N PPMAP 6 5* +N PPMAP 56 50* +N PPMAP 57 51* +N PPMAP 58 52* +N PPMAP 59 53* +N PPMAP 60 54* +N PPMAP 62 56* +N PPMAP 63 57* +N PPMAP 64 58* +N PPMAP 66 59* +N PPMAP 8 6* +N PPMAP 68 60* +N PPMAP 69 61* +N PPMAP 72 64* +N PPMAP 74 66* +N PPMAP 76 68* +N PPMAP 77 69* +N PPMAP 9 7* +N PPMAP 78 70* +N PPMAP 79 71* +N PPMAP 82 74* +N PPMAP 84 75* +N PPMAP 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00000000 00000000 00000000 00000000 00000000 00000000* +L0092832 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000* +L0092896 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000* +L0092960 00000000 00000000 00000100 00000000 00000000 00000000 00000000 00000000* +L0093024 000000 000000 000000 000000 000000 000000 000000 000000* +L0093072 000000 000000 000000 000000 000000 000000 000000 000000* +L0093120 000000 000000 000000 000000 000000 000000 000000 000000* +L0093168 000000 000000 000000 000000 000000 000000 000000 000000* +L0093216 000000 000000 000000 000000 000000 000000 000000 000000* +L0093264 000000 000000 000000 000000 000000 000000 000000 000000* +CB6CD* +A17C diff --git a/Logic/LAN_IDE/LAN_IDE_CP.lfp b/Logic/LAN_IDE/LAN_IDE_CP.lfp new file mode 100644 index 0000000..e69de29 diff --git a/Logic/LAN_IDE/LAN_IDE_CP.lso b/Logic/LAN_IDE/LAN_IDE_CP.lso new file mode 100644 index 0000000..b8f99f5 --- /dev/null +++ b/Logic/LAN_IDE/LAN_IDE_CP.lso @@ -0,0 +1 @@ +work diff --git a/Logic/LAN_IDE/LAN_IDE_CP.mfd b/Logic/LAN_IDE/LAN_IDE_CP.mfd new file mode 100644 index 0000000..32b3f21 --- /dev/null +++ b/Logic/LAN_IDE/LAN_IDE_CP.mfd @@ -0,0 +1,1046 @@ +MDF Database: version 1.0 +MDF_INFO | LAN_IDE_CP | XC95144XL-10-TQ144 +MACROCELL | 1 | 14 | D<13>_BUFR.MC +ATTRIBUTES | 8520480 | 0 +OUTPUTMC | 1 | 2 | 11 +INPUTS | 17 | RESET | RW | AS | A<5> | A<1> | A<6> | A<3> | A<2> | AUTO_CONFIG_DONE<1> | AUTO_CONFIG_DONE<2> | autoconfig | A<4> | AUTO_CONFIG_DONE<0> | D<13> | ide/ide_CLKF | EXP17_.EXP | N1$BUF2.EXP +INPUTMC | 8 | 2 | 14 | 1 | 7 | 3 | 16 | 1 | 8 | 2 | 11 | 3 | 15 | 1 | 13 | 1 | 15 +INPUTP | 9 | 160 | 93 | 90 | 54 | 63 | 57 | 58 | 60 | 56 +IMPORTS | 2 | 1 | 13 | 1 | 15 +EQ | 39 | + !D<13>_BUFR.D = RESET & !D<13> & AS + # RESET & !D<13> & !autoconfig + # RESET & RW & !AS & !A<5> & A<4> & !A<6> & A<3> & + A<2> & AUTO_CONFIG_DONE<0> & !AUTO_CONFIG_DONE<1> & + autoconfig + # RESET & RW & !AS & !A<5> & A<1> & !A<6> & !A<3> & + !A<2> & AUTO_CONFIG_DONE<1> & !AUTO_CONFIG_DONE<2> & + autoconfig +;Imported pterms FB2_14 + # RESET & !D<13> & !RW + # RESET & !D<13> & AUTO_CONFIG_DONE<0> & + AUTO_CONFIG_DONE<1> & AUTO_CONFIG_DONE<2> + # RESET & RW & !AS & !A<5> & !A<4> & !A<6> & !A<3> & + !AUTO_CONFIG_DONE<0> & autoconfig + # RESET & RW & !AS & !A<5> & !A<4> & !A<3> & !A<2> & + !AUTO_CONFIG_DONE<0> & autoconfig + # RESET & RW & !AS & !A<5> & !A<4> & !A<3> & !A<2> & + !AUTO_CONFIG_DONE<1> & autoconfig +;Imported pterms FB2_13 + # RESET & RW & !AS & !A<5> & A<4> & !A<1> & !A<6> & + A<3> & AUTO_CONFIG_DONE<0> & !AUTO_CONFIG_DONE<1> & + autoconfig + # RESET & RW & !AS & !A<5> & !A<4> & !A<1> & !A<6> & + !A<3> & AUTO_CONFIG_DONE<1> & !AUTO_CONFIG_DONE<2> & + autoconfig + # RESET & RW & !AS & A<5> & !A<4> & !A<1> & !A<6> & + !A<3> & A<2> & AUTO_CONFIG_DONE<0> & !AUTO_CONFIG_DONE<1> & + autoconfig +;Imported pterms FB2_16 + # RESET & RW & !AS & !A<5> & !A<4> & !A<3> & !A<2> & + !AUTO_CONFIG_DONE<2> & autoconfig + # RESET & RW & !AS & !A<5> & !A<4> & A<1> & !A<6> & + !A<3> & !AUTO_CONFIG_DONE<1> & autoconfig + # RESET & RW & !AS & !A<5> & A<1> & !A<6> & !A<3> & + !A<2> & !AUTO_CONFIG_DONE<0> & autoconfig + # RESET & RW & !AS & !A<5> & A<4> & !A<1> & !A<6> & + A<2> & AUTO_CONFIG_DONE<0> & !AUTO_CONFIG_DONE<1> & + autoconfig; + D<13>_BUFR.CLK = ide/ide_CLKF; + +MACROCELL | 0 | 17 | D<12>_BUFR.MC +ATTRIBUTES | 8520480 | 0 +OUTPUTMC | 1 | 2 | 3 +INPUTS | 17 | RESET | RW | AS | A<5> | A<4> | A<1> | A<3> | A<2> | AUTO_CONFIG_DONE<1> | AUTO_CONFIG_DONE<2> | autoconfig | A<6> | AUTO_CONFIG_DONE<0> | AUTOBOOT_OFF | IDE_CS_1_OBUF.EXP | ide/ide_CLKF | EXP14_.EXP +INPUTMC | 7 | 2 | 14 | 1 | 7 | 3 | 16 | 1 | 8 | 0 | 0 | 3 | 15 | 0 | 16 +INPUTP | 10 | 160 | 93 | 90 | 54 | 56 | 63 | 58 | 60 | 57 | 84 +IMPORTS | 2 | 0 | 0 | 0 | 16 +EQ | 43 | + !D<12>_BUFR.D = RESET & RW & !AS & !A<4> & A<1> & !A<6> & !A<3> & + A<2> & !AUTO_CONFIG_DONE<0> & autoconfig + # RESET & RW & !AS & !A<5> & A<4> & !A<6> & A<3> & + !A<2> & AUTO_CONFIG_DONE<0> & !AUTO_CONFIG_DONE<1> & + autoconfig + # RESET & RW & !AS & !A<5> & !A<4> & !A<1> & !A<3> & + !A<2> & AUTO_CONFIG_DONE<1> & !AUTO_CONFIG_DONE<2> & + autoconfig + # RESET & RW & !AS & !A<5> & !A<4> & !A<1> & !A<3> & + !A<2> & !AUTO_CONFIG_DONE<1> & AUTOBOOT_OFF & autoconfig +;Imported pterms FB1_1 + # RESET & RW & !AS & !A<5> & !A<4> & A<6> & !A<3> & + !A<2> & !AUTO_CONFIG_DONE<0> & autoconfig + # RESET & RW & !AS & !A<5> & !A<4> & A<6> & !A<3> & + !A<2> & !AUTO_CONFIG_DONE<1> & autoconfig + # RESET & RW & !AS & !A<5> & !A<4> & A<6> & !A<3> & + !A<2> & !AUTO_CONFIG_DONE<2> & autoconfig + # RESET & RW & !AS & !A<5> & !A<1> & !A<6> & !A<3> & + A<2> & !AUTO_CONFIG_DONE<0> & autoconfig + # RESET & RW & !AS & A<5> & !A<4> & A<1> & !A<6> & + A<2> & AUTO_CONFIG_DONE<0> & !AUTO_CONFIG_DONE<1> & + autoconfig +;Imported pterms FB1_17 + # RESET & !D<12> & !RW + # RESET & !D<12> & AS + # RESET & !D<12> & !autoconfig + # RESET & !D<12> & AUTO_CONFIG_DONE<0> & + AUTO_CONFIG_DONE<1> & AUTO_CONFIG_DONE<2> + # RESET & RW & !AS & !A<5> & !A<4> & !A<1> & !A<3> & + !A<2> & !AUTO_CONFIG_DONE<0> & autoconfig +;Imported pterms FB1_16 + # RESET & RW & !AS & A<5> & !A<4> & A<1> & !A<6> & + !A<3> & A<2> & !AUTO_CONFIG_DONE<2> & autoconfig + # RESET & RW & !AS & A<5> & !A<4> & !A<6> & !A<3> & + A<2> & AUTO_CONFIG_DONE<0> & !AUTO_CONFIG_DONE<1> & + autoconfig + # RESET & RW & !AS & !A<5> & A<4> & A<1> & !A<6> & + A<3> & AUTO_CONFIG_DONE<0> & !AUTO_CONFIG_DONE<1> & + autoconfig + # RESET & RW & !AS & !A<5> & !A<1> & !A<6> & !A<3> & + A<2> & AUTO_CONFIG_DONE<1> & !AUTO_CONFIG_DONE<2> & + autoconfig; + D<12>_BUFR.CLK = ide/ide_CLKF; + +MACROCELL | 1 | 0 | D<14>_BUFR.MC +ATTRIBUTES | 8520480 | 0 +OUTPUTMC | 1 | 2 | 6 +INPUTS | 16 | RESET | RW | AS | A<5> | A<4> | A<6> | A<3> | A<2> | AUTO_CONFIG_DONE<0> | AUTO_CONFIG_DONE<1> | AUTO_CONFIG_DONE<2> | autoconfig | A<1> | EXP15_.EXP | ide/ide_CLKF | EXP18_.EXP +INPUTMC | 7 | 1 | 8 | 2 | 14 | 1 | 7 | 3 | 16 | 1 | 1 | 3 | 15 | 1 | 17 +INPUTP | 9 | 160 | 93 | 90 | 54 | 56 | 57 | 58 | 60 | 63 +IMPORTS | 2 | 1 | 1 | 1 | 17 +EQ | 40 | + !D<14>_BUFR.D = RESET & RW & !AS & !A<5> & !A<4> & A<1> & !A<3> & + !A<2> & !AUTO_CONFIG_DONE<1> & autoconfig + # RESET & RW & !AS & !A<5> & !A<4> & A<1> & !A<3> & + !A<2> & !AUTO_CONFIG_DONE<2> & autoconfig + # RESET & RW & !AS & !A<5> & A<1> & !A<6> & !A<3> & + A<2> & AUTO_CONFIG_DONE<0> & !AUTO_CONFIG_DONE<1> & + autoconfig + # RESET & RW & !AS & !A<5> & !A<4> & !A<6> & !A<3> & + A<2> & AUTO_CONFIG_DONE<0> & AUTO_CONFIG_DONE<1> & + !AUTO_CONFIG_DONE<2> & autoconfig +;Imported pterms FB2_2 + # RESET & RW & !AS & !A<5> & !A<4> & A<1> & !A<3> & + !A<2> & !AUTO_CONFIG_DONE<0> & autoconfig + # RESET & RW & !AS & !A<5> & !A<4> & A<6> & !A<3> & + !A<2> & !AUTO_CONFIG_DONE<0> & autoconfig + # RESET & RW & !AS & !A<5> & !A<4> & A<6> & !A<3> & + !A<2> & !AUTO_CONFIG_DONE<1> & autoconfig + # RESET & RW & !AS & !A<5> & !A<4> & A<6> & !A<3> & + !A<2> & !AUTO_CONFIG_DONE<2> & autoconfig + # RESET & RW & !AS & !A<4> & A<1> & !A<6> & !A<3> & + A<2> & AUTO_CONFIG_DONE<0> & !AUTO_CONFIG_DONE<1> & + autoconfig +;Imported pterms FB2_3 + # RESET & RW & !AS & !A<5> & A<4> & A<1> & !A<6> & + !A<3> & A<2> & !AUTO_CONFIG_DONE<0> & autoconfig + # RESET & RW & !AS & !A<5> & !A<4> & !A<1> & !A<6> & + !A<3> & A<2> & !AUTO_CONFIG_DONE<0> & autoconfig + # RESET & RW & !AS & !A<5> & A<4> & !A<1> & !A<6> & + A<3> & A<2> & AUTO_CONFIG_DONE<0> & !AUTO_CONFIG_DONE<1> & + autoconfig +;Imported pterms FB2_18 + # RESET & !D<14> & !RW + # RESET & !D<14> & AS + # RESET & !D<14> & !autoconfig + # RESET & !D<14> & AUTO_CONFIG_DONE<0> & + AUTO_CONFIG_DONE<1> & AUTO_CONFIG_DONE<2> + # RESET & RW & !AS & !A<5> & A<1> & !A<6> & !A<3> & + A<2> & AUTO_CONFIG_DONE<0> & !AUTO_CONFIG_DONE<2> & + autoconfig; + D<14>_BUFR.CLK = ide/ide_CLKF; + +MACROCELL | 5 | 16 | D<15>_BUFR.MC +ATTRIBUTES | 8520480 | 0 +OUTPUTMC | 1 | 2 | 9 +INPUTS | 14 | RESET | RW | AS | A<5> | A<1> | A<6> | A<3> | A<2> | AUTO_CONFIG_DONE<1> | autoconfig | D<15> | EXP22_.EXP | EXP23_.EXP | ide/ide_CLKF +INPUTMC | 6 | 2 | 14 | 3 | 16 | 2 | 9 | 5 | 15 | 5 | 17 | 3 | 15 +INPUTP | 8 | 160 | 93 | 90 | 54 | 63 | 57 | 58 | 60 +IMPORTS | 2 | 5 | 15 | 5 | 17 +EQ | 29 | + !D<15>_BUFR.D = RESET & !D<15> & !RW + # RESET & !D<15> & AS + # RESET & !D<15> & !autoconfig + # RESET & RW & !AS & !A<5> & A<1> & !A<6> & !A<3> & + !A<2> & !AUTO_CONFIG_DONE<1> & autoconfig +;Imported pterms FB6_16 + # RESET & !D<15> & AUTO_CONFIG_DONE<0> & + AUTO_CONFIG_DONE<1> & AUTO_CONFIG_DONE<2> + # RESET & RW & !AS & !A<5> & A<1> & !A<6> & !A<3> & + !AUTO_CONFIG_DONE<0> & autoconfig + # RESET & RW & !AS & !A<5> & !A<4> & A<6> & !A<3> & + !A<2> & !AUTO_CONFIG_DONE<0> & autoconfig + # RESET & RW & !AS & !A<5> & !A<4> & A<6> & !A<3> & + !A<2> & !AUTO_CONFIG_DONE<1> & autoconfig +;Imported pterms FB6_18 + # RESET & RW & !AS & !A<5> & !A<4> & A<6> & !A<3> & + !A<2> & !AUTO_CONFIG_DONE<2> & autoconfig + # RESET & RW & !AS & !A<5> & A<1> & !A<6> & !A<3> & + AUTO_CONFIG_DONE<1> & !AUTO_CONFIG_DONE<2> & autoconfig + # RESET & RW & !AS & !A<5> & A<4> & A<1> & !A<6> & + A<2> & AUTO_CONFIG_DONE<0> & !AUTO_CONFIG_DONE<1> & + autoconfig + # RESET & RW & !AS & A<5> & !A<4> & !A<1> & !A<6> & + !A<3> & A<2> & AUTO_CONFIG_DONE<0> & !AUTO_CONFIG_DONE<1> & + autoconfig + # RESET & RW & !AS & !A<5> & A<4> & !A<1> & !A<6> & + A<3> & !A<2> & AUTO_CONFIG_DONE<0> & !AUTO_CONFIG_DONE<1> & + autoconfig; + D<15>_BUFR.CLK = ide/ide_CLKF; + +MACROCELL | 1 | 8 | AUTO_CONFIG_DONE<0> +ATTRIBUTES | 8528672 | 0 +OUTPUTMC | 26 | 1 | 14 | 0 | 17 | 1 | 0 | 5 | 15 | 1 | 10 | 2 | 15 | 1 | 9 | 4 | 17 | 4 | 14 | 4 | 13 | 4 | 15 | 2 | 17 | 2 | 16 | 1 | 2 | 1 | 11 | 4 | 12 | 3 | 16 | 0 | 0 | 0 | 15 | 0 | 16 | 1 | 1 | 1 | 12 | 1 | 13 | 1 | 15 | 1 | 17 | 5 | 17 +INPUTS | 2 | AUTO_CONFIG_DONE_CYCLE<0> | AS +INPUTMC | 1 | 1 | 10 +INPUTP | 1 | 90 +EQ | 3 | + AUTO_CONFIG_DONE<0>.D = AUTO_CONFIG_DONE_CYCLE<0>; + AUTO_CONFIG_DONE<0>.CLK = AS; + !AUTO_CONFIG_DONE<0>.AR = RESET; // GSR +GLOBALS | 1 | 4 | RESET + +MACROCELL | 2 | 14 | AUTO_CONFIG_DONE<1> +ATTRIBUTES | 8528672 | 0 +OUTPUTMC | 27 | 1 | 14 | 0 | 17 | 1 | 0 | 5 | 16 | 2 | 15 | 1 | 9 | 4 | 17 | 4 | 14 | 4 | 13 | 4 | 15 | 2 | 17 | 2 | 16 | 1 | 10 | 1 | 11 | 4 | 12 | 3 | 16 | 0 | 0 | 0 | 15 | 0 | 16 | 1 | 1 | 1 | 2 | 1 | 12 | 1 | 13 | 1 | 15 | 1 | 17 | 5 | 15 | 5 | 17 +INPUTS | 2 | AUTO_CONFIG_DONE_CYCLE<1> | AS +INPUTMC | 1 | 2 | 15 +INPUTP | 1 | 90 +EQ | 3 | + AUTO_CONFIG_DONE<1>.D = AUTO_CONFIG_DONE_CYCLE<1>; + AUTO_CONFIG_DONE<1>.CLK = AS; + !AUTO_CONFIG_DONE<1>.AR = RESET; // GSR +GLOBALS | 1 | 4 | RESET + +MACROCELL | 1 | 7 | AUTO_CONFIG_DONE<2> +ATTRIBUTES | 8528672 | 0 +OUTPUTMC | 15 | 1 | 14 | 0 | 17 | 1 | 0 | 5 | 15 | 1 | 9 | 3 | 16 | 0 | 0 | 0 | 15 | 0 | 16 | 1 | 1 | 1 | 12 | 1 | 13 | 1 | 15 | 1 | 17 | 5 | 17 +INPUTS | 2 | AUTO_CONFIG_DONE_CYCLE<2> | AS +INPUTMC | 1 | 1 | 9 +INPUTP | 1 | 90 +EQ | 3 | + AUTO_CONFIG_DONE<2>.D = AUTO_CONFIG_DONE_CYCLE<2>; + AUTO_CONFIG_DONE<2>.CLK = AS; + !AUTO_CONFIG_DONE<2>.AR = RESET; // GSR +GLOBALS | 1 | 4 | RESET + +MACROCELL | 1 | 10 | AUTO_CONFIG_DONE_CYCLE<0> +ATTRIBUTES | 8520480 | 0 +OUTPUTMC | 3 | 1 | 8 | 1 | 10 | 1 | 11 +INPUTS | 17 | RESET | AUTO_CONFIG_DONE_CYCLE<0> | UDS | RW | AS | A<5> | A<4> | A<1> | A<6> | A<3> | AUTO_CONFIG_DONE<0> | autoconfig | ide/ide_CLKF | A<2> | AUTO_CONFIG_DONE<1> | IDE_BASEADR<7> | D<15>.PIN +INPUTMC | 6 | 1 | 10 | 1 | 8 | 3 | 16 | 3 | 15 | 2 | 14 | 1 | 11 +INPUTP | 11 | 160 | 91 | 93 | 90 | 54 | 56 | 63 | 57 | 58 | 60 | 52 +EXPORTS | 1 | 1 | 11 +EQ | 7 | + AUTO_CONFIG_DONE_CYCLE<0>.D = RESET & AUTO_CONFIG_DONE_CYCLE<0> + # RESET & !UDS & !RW & !AS & !A<5> & !A<4> & !A<1> & + A<6> & A<3> & !AUTO_CONFIG_DONE<0> & autoconfig; + AUTO_CONFIG_DONE_CYCLE<0>.CLK = ide/ide_CLKF; + AUTO_CONFIG_DONE_CYCLE<0>.EXP = RESET & !UDS & !RW & !AS & !A<5> & !A<4> & !A<1> & + A<6> & A<3> & !A<2> & AUTO_CONFIG_DONE<0> & + !AUTO_CONFIG_DONE<1> & IDE_BASEADR<7> & autoconfig & !D<15>.PIN + +MACROCELL | 2 | 15 | AUTO_CONFIG_DONE_CYCLE<1> +ATTRIBUTES | 8520480 | 0 +OUTPUTMC | 2 | 2 | 14 | 2 | 15 +INPUTS | 14 | RESET | AUTO_CONFIG_DONE_CYCLE<1> | UDS | RW | AS | A<5> | A<4> | A<1> | A<6> | A<3> | AUTO_CONFIG_DONE<0> | AUTO_CONFIG_DONE<1> | autoconfig | ide/ide_CLKF +INPUTMC | 5 | 2 | 15 | 1 | 8 | 2 | 14 | 3 | 16 | 3 | 15 +INPUTP | 9 | 160 | 91 | 93 | 90 | 54 | 56 | 63 | 57 | 58 +EQ | 5 | + AUTO_CONFIG_DONE_CYCLE<1>.D = RESET & AUTO_CONFIG_DONE_CYCLE<1> + # RESET & !UDS & !RW & !AS & !A<5> & !A<4> & !A<1> & + A<6> & A<3> & AUTO_CONFIG_DONE<0> & !AUTO_CONFIG_DONE<1> & + autoconfig; + AUTO_CONFIG_DONE_CYCLE<1>.CLK = ide/ide_CLKF; + +MACROCELL | 1 | 9 | AUTO_CONFIG_DONE_CYCLE<2> +ATTRIBUTES | 8520480 | 0 +OUTPUTMC | 2 | 1 | 7 | 1 | 9 +INPUTS | 15 | RESET | AUTO_CONFIG_DONE_CYCLE<2> | UDS | RW | AS | A<5> | A<4> | A<1> | A<6> | A<3> | AUTO_CONFIG_DONE<0> | AUTO_CONFIG_DONE<1> | AUTO_CONFIG_DONE<2> | autoconfig | ide/ide_CLKF +INPUTMC | 6 | 1 | 9 | 1 | 8 | 2 | 14 | 1 | 7 | 3 | 16 | 3 | 15 +INPUTP | 9 | 160 | 91 | 93 | 90 | 54 | 56 | 63 | 57 | 58 +EQ | 5 | + AUTO_CONFIG_DONE_CYCLE<2>.D = RESET & AUTO_CONFIG_DONE_CYCLE<2> + # RESET & !UDS & !RW & !AS & !A<5> & !A<4> & !A<1> & + A<6> & A<3> & AUTO_CONFIG_DONE<0> & AUTO_CONFIG_DONE<1> & + !AUTO_CONFIG_DONE<2> & autoconfig; + AUTO_CONFIG_DONE_CYCLE<2>.CLK = ide/ide_CLKF; + +MACROCELL | 4 | 17 | IDE_BASEADR<0> +ATTRIBUTES | 4326176 | 0 +OUTPUTMC | 2 | 4 | 17 | 3 | 17 +INPUTS | 16 | RESET | IDE_BASEADR<0> | UDS | RW | AS | A<5> | A<4> | A<1> | A<6> | A<3> | A<2> | AUTO_CONFIG_DONE<0> | AUTO_CONFIG_DONE<1> | autoconfig | D<8>.PIN | ide/ide_CLKF +INPUTMC | 5 | 4 | 17 | 1 | 8 | 2 | 14 | 3 | 16 | 3 | 15 +INPUTP | 11 | 160 | 91 | 93 | 90 | 54 | 56 | 63 | 57 | 58 | 60 | 21 +EQ | 8 | + IDE_BASEADR<0>.T = !RESET & !IDE_BASEADR<0> + # !UDS & !RW & !AS & !A<5> & !A<4> & !A<1> & A<6> & + A<3> & !A<2> & AUTO_CONFIG_DONE<0> & !AUTO_CONFIG_DONE<1> & + !IDE_BASEADR<0> & autoconfig & D<8>.PIN + # RESET & !UDS & !RW & !AS & !A<5> & !A<4> & !A<1> & + A<6> & A<3> & !A<2> & AUTO_CONFIG_DONE<0> & + !AUTO_CONFIG_DONE<1> & IDE_BASEADR<0> & autoconfig & !D<8>.PIN; + IDE_BASEADR<0>.CLK = ide/ide_CLKF; + +MACROCELL | 4 | 14 | IDE_BASEADR<4> +ATTRIBUTES | 4326176 | 0 +OUTPUTMC | 2 | 4 | 14 | 3 | 2 +INPUTS | 16 | RESET | IDE_BASEADR<4> | UDS | RW | AS | A<5> | A<4> | A<1> | A<6> | A<3> | A<2> | AUTO_CONFIG_DONE<0> | AUTO_CONFIG_DONE<1> | autoconfig | D<12>.PIN | ide/ide_CLKF +INPUTMC | 5 | 4 | 14 | 1 | 8 | 2 | 14 | 3 | 16 | 3 | 15 +INPUTP | 11 | 160 | 91 | 93 | 90 | 54 | 56 | 63 | 57 | 58 | 60 | 48 +EQ | 8 | + IDE_BASEADR<4>.T = !RESET & !IDE_BASEADR<4> + # !UDS & !RW & !AS & !A<5> & !A<4> & !A<1> & A<6> & + A<3> & !A<2> & AUTO_CONFIG_DONE<0> & !AUTO_CONFIG_DONE<1> & + !IDE_BASEADR<4> & autoconfig & D<12>.PIN + # RESET & !UDS & !RW & !AS & !A<5> & !A<4> & !A<1> & + A<6> & A<3> & !A<2> & AUTO_CONFIG_DONE<0> & + !AUTO_CONFIG_DONE<1> & IDE_BASEADR<4> & autoconfig & !D<12>.PIN; + IDE_BASEADR<4>.CLK = ide/ide_CLKF; + +MACROCELL | 4 | 13 | IDE_BASEADR<5> +ATTRIBUTES | 4326176 | 0 +OUTPUTMC | 3 | 4 | 13 | 3 | 2 | 3 | 16 +INPUTS | 16 | RESET | IDE_BASEADR<5> | UDS | RW | AS | A<5> | A<4> | A<1> | A<6> | A<3> | A<2> | AUTO_CONFIG_DONE<0> | AUTO_CONFIG_DONE<1> | autoconfig | D<13>.PIN | ide/ide_CLKF +INPUTMC | 5 | 4 | 13 | 1 | 8 | 2 | 14 | 3 | 16 | 3 | 15 +INPUTP | 11 | 160 | 91 | 93 | 90 | 54 | 56 | 63 | 57 | 58 | 60 | 49 +EQ | 8 | + IDE_BASEADR<5>.T = !RESET & !IDE_BASEADR<5> + # !UDS & !RW & !AS & !A<5> & !A<4> & !A<1> & A<6> & + A<3> & !A<2> & AUTO_CONFIG_DONE<0> & !AUTO_CONFIG_DONE<1> & + !IDE_BASEADR<5> & autoconfig & D<13>.PIN + # RESET & !UDS & !RW & !AS & !A<5> & !A<4> & !A<1> & + A<6> & A<3> & !A<2> & AUTO_CONFIG_DONE<0> & + !AUTO_CONFIG_DONE<1> & IDE_BASEADR<5> & autoconfig & !D<13>.PIN; + IDE_BASEADR<5>.CLK = ide/ide_CLKF; + +MACROCELL | 0 | 9 | IDE_ENABLE +ATTRIBUTES | 8520480 | 0 +OUTPUTMC | 3 | 0 | 9 | 0 | 13 | 0 | 14 +INPUTS | 6 | RESET | IDE_ENABLE | RW | AS | ide | ide/ide_CLKF +INPUTMC | 3 | 0 | 9 | 3 | 0 | 3 | 15 +INPUTP | 3 | 160 | 93 | 90 +EQ | 3 | + !IDE_ENABLE.D = RESET & !IDE_ENABLE + # RESET & !RW & !AS & ide; + IDE_ENABLE.CLK = ide/ide_CLKF; + +MACROCELL | 4 | 15 | IDE_BASEADR<1> +ATTRIBUTES | 4326176 | 0 +OUTPUTMC | 3 | 4 | 15 | 3 | 1 | 3 | 17 +INPUTS | 16 | RESET | IDE_BASEADR<1> | UDS | RW | AS | A<5> | A<4> | A<1> | A<6> | A<3> | A<2> | AUTO_CONFIG_DONE<0> | AUTO_CONFIG_DONE<1> | autoconfig | D<9>.PIN | ide/ide_CLKF +INPUTMC | 5 | 4 | 15 | 1 | 8 | 2 | 14 | 3 | 16 | 3 | 15 +INPUTP | 11 | 160 | 91 | 93 | 90 | 54 | 56 | 63 | 57 | 58 | 60 | 44 +EQ | 8 | + IDE_BASEADR<1>.T = !RESET & !IDE_BASEADR<1> + # !UDS & !RW & !AS & !A<5> & !A<4> & !A<1> & A<6> & + A<3> & !A<2> & AUTO_CONFIG_DONE<0> & !AUTO_CONFIG_DONE<1> & + !IDE_BASEADR<1> & autoconfig & D<9>.PIN + # RESET & !UDS & !RW & !AS & !A<5> & !A<4> & !A<1> & + A<6> & A<3> & !A<2> & AUTO_CONFIG_DONE<0> & + !AUTO_CONFIG_DONE<1> & IDE_BASEADR<1> & autoconfig & !D<9>.PIN; + IDE_BASEADR<1>.CLK = ide/ide_CLKF; + +MACROCELL | 2 | 17 | IDE_BASEADR<2> +ATTRIBUTES | 4326176 | 0 +OUTPUTMC | 2 | 2 | 17 | 3 | 17 +INPUTS | 16 | RESET | IDE_BASEADR<2> | UDS | RW | AS | A<5> | A<4> | A<1> | A<6> | A<3> | A<2> | AUTO_CONFIG_DONE<0> | AUTO_CONFIG_DONE<1> | autoconfig | D<10>.PIN | ide/ide_CLKF +INPUTMC | 5 | 2 | 17 | 1 | 8 | 2 | 14 | 3 | 16 | 3 | 15 +INPUTP | 11 | 160 | 91 | 93 | 90 | 54 | 56 | 63 | 57 | 58 | 60 | 45 +EQ | 8 | + IDE_BASEADR<2>.T = !RESET & !IDE_BASEADR<2> + # !UDS & !RW & !AS & !A<5> & !A<4> & !A<1> & A<6> & + A<3> & !A<2> & AUTO_CONFIG_DONE<0> & !AUTO_CONFIG_DONE<1> & + !IDE_BASEADR<2> & autoconfig & D<10>.PIN + # RESET & !UDS & !RW & !AS & !A<5> & !A<4> & !A<1> & + A<6> & A<3> & !A<2> & AUTO_CONFIG_DONE<0> & + !AUTO_CONFIG_DONE<1> & IDE_BASEADR<2> & autoconfig & !D<10>.PIN; + IDE_BASEADR<2>.CLK = ide/ide_CLKF; + +MACROCELL | 2 | 16 | IDE_BASEADR<3> +ATTRIBUTES | 4326176 | 0 +OUTPUTMC | 2 | 2 | 16 | 3 | 0 +INPUTS | 16 | RESET | IDE_BASEADR<3> | UDS | RW | AS | A<5> | A<4> | A<1> | A<6> | A<3> | A<2> | AUTO_CONFIG_DONE<0> | AUTO_CONFIG_DONE<1> | autoconfig | D<11>.PIN | ide/ide_CLKF +INPUTMC | 5 | 2 | 16 | 1 | 8 | 2 | 14 | 3 | 16 | 3 | 15 +INPUTP | 11 | 160 | 91 | 93 | 90 | 54 | 56 | 63 | 57 | 58 | 60 | 47 +EQ | 8 | + IDE_BASEADR<3>.T = !RESET & !IDE_BASEADR<3> + # !UDS & !RW & !AS & !A<5> & !A<4> & !A<1> & A<6> & + A<3> & !A<2> & AUTO_CONFIG_DONE<0> & !AUTO_CONFIG_DONE<1> & + !IDE_BASEADR<3> & autoconfig & D<11>.PIN + # RESET & !UDS & !RW & !AS & !A<5> & !A<4> & !A<1> & + A<6> & A<3> & !A<2> & AUTO_CONFIG_DONE<0> & + !AUTO_CONFIG_DONE<1> & IDE_BASEADR<3> & autoconfig & !D<11>.PIN; + IDE_BASEADR<3>.CLK = ide/ide_CLKF; + +MACROCELL | 1 | 12 | IDE_BASEADR<6> +ATTRIBUTES | 4326176 | 0 +OUTPUTMC | 4 | 1 | 12 | 1 | 11 | 3 | 1 | 1 | 13 +INPUTS | 16 | RESET | IDE_BASEADR<6> | RW | AS | A<5> | A<4> | A<1> | A<6> | A<3> | AUTO_CONFIG_DONE<0> | AUTO_CONFIG_DONE<1> | autoconfig | AUTO_CONFIG_DONE<2> | A<2> | IDE_BASEADR<7>.EXP | ide/ide_CLKF +INPUTMC | 7 | 1 | 12 | 1 | 8 | 2 | 14 | 3 | 16 | 1 | 7 | 1 | 11 | 3 | 15 +INPUTP | 9 | 160 | 93 | 90 | 54 | 56 | 63 | 57 | 58 | 60 +EXPORTS | 1 | 1 | 13 +IMPORTS | 1 | 1 | 11 +EQ | 18 | + IDE_BASEADR<6>.T = !RESET & !IDE_BASEADR<6> +;Imported pterms FB2_12 + # !UDS & !RW & !AS & !A<5> & !A<4> & !A<1> & A<6> & + A<3> & !A<2> & AUTO_CONFIG_DONE<0> & !AUTO_CONFIG_DONE<1> & + !IDE_BASEADR<6> & autoconfig & D<14>.PIN + # RESET & !UDS & !RW & !AS & !A<5> & !A<4> & !A<1> & + A<6> & A<3> & !A<2> & AUTO_CONFIG_DONE<0> & + !AUTO_CONFIG_DONE<1> & IDE_BASEADR<6> & autoconfig & !D<14>.PIN; + IDE_BASEADR<6>.CLK = ide/ide_CLKF; + IDE_BASEADR<6>.EXP = RESET & RW & !AS & !A<5> & A<4> & !A<1> & !A<6> & + A<3> & AUTO_CONFIG_DONE<0> & !AUTO_CONFIG_DONE<1> & + autoconfig + # RESET & RW & !AS & !A<5> & !A<4> & !A<1> & !A<6> & + !A<3> & AUTO_CONFIG_DONE<1> & !AUTO_CONFIG_DONE<2> & + autoconfig + # RESET & RW & !AS & A<5> & !A<4> & !A<1> & !A<6> & + !A<3> & A<2> & AUTO_CONFIG_DONE<0> & !AUTO_CONFIG_DONE<1> & + autoconfig + +MACROCELL | 1 | 11 | IDE_BASEADR<7> +ATTRIBUTES | 4326176 | 0 +OUTPUTMC | 4 | 1 | 11 | 1 | 10 | 3 | 1 | 1 | 12 +INPUTS | 19 | RESET | IDE_BASEADR<7> | UDS | RW | AS | A<5> | A<4> | A<1> | A<6> | A<3> | A<2> | AUTO_CONFIG_DONE<0> | AUTO_CONFIG_DONE<1> | autoconfig | D<15>.PIN | ide/ide_CLKF | IDE_BASEADR<6> | D<14>.PIN | AUTO_CONFIG_DONE_CYCLE<0>.EXP +INPUTMC | 7 | 1 | 11 | 1 | 8 | 2 | 14 | 3 | 16 | 3 | 15 | 1 | 12 | 1 | 10 +INPUTP | 12 | 160 | 91 | 93 | 90 | 54 | 56 | 63 | 57 | 58 | 60 | 52 | 50 +EXPORTS | 1 | 1 | 12 +IMPORTS | 1 | 1 | 10 +EQ | 15 | + IDE_BASEADR<7>.T = !RESET & !IDE_BASEADR<7> + # !UDS & !RW & !AS & !A<5> & !A<4> & !A<1> & A<6> & + A<3> & !A<2> & AUTO_CONFIG_DONE<0> & !AUTO_CONFIG_DONE<1> & + !IDE_BASEADR<7> & autoconfig & D<15>.PIN +;Imported pterms FB2_11 + # RESET & !UDS & !RW & !AS & !A<5> & !A<4> & !A<1> & + A<6> & A<3> & !A<2> & AUTO_CONFIG_DONE<0> & + !AUTO_CONFIG_DONE<1> & IDE_BASEADR<7> & autoconfig & !D<15>.PIN; + IDE_BASEADR<7>.CLK = ide/ide_CLKF; + IDE_BASEADR<7>.EXP = !UDS & !RW & !AS & !A<5> & !A<4> & !A<1> & A<6> & + A<3> & !A<2> & AUTO_CONFIG_DONE<0> & !AUTO_CONFIG_DONE<1> & + !IDE_BASEADR<6> & autoconfig & D<14>.PIN + # RESET & !UDS & !RW & !AS & !A<5> & !A<4> & !A<1> & + A<6> & A<3> & !A<2> & AUTO_CONFIG_DONE<0> & + !AUTO_CONFIG_DONE<1> & IDE_BASEADR<6> & autoconfig & !D<14>.PIN + +MACROCELL | 4 | 12 | SHUT_UP<1> +ATTRIBUTES | 8520480 | 0 +OUTPUTMC | 2 | 4 | 12 | 3 | 0 +INPUTS | 15 | RESET | SHUT_UP<1> | UDS | RW | AS | A<5> | A<4> | A<1> | A<6> | A<3> | A<2> | AUTO_CONFIG_DONE<0> | AUTO_CONFIG_DONE<1> | autoconfig | ide/ide_CLKF +INPUTMC | 5 | 4 | 12 | 1 | 8 | 2 | 14 | 3 | 16 | 3 | 15 +INPUTP | 10 | 160 | 91 | 93 | 90 | 54 | 56 | 63 | 57 | 58 | 60 +EQ | 5 | + !SHUT_UP<1>.D = RESET & !SHUT_UP<1> + # RESET & !UDS & !RW & !AS & !A<5> & !A<4> & !A<1> & + A<6> & A<3> & !A<2> & AUTO_CONFIG_DONE<0> & + !AUTO_CONFIG_DONE<1> & autoconfig; + SHUT_UP<1>.CLK = ide/ide_CLKF; + +MACROCELL | 3 | 16 | autoconfig +ATTRIBUTES | 8520480 | 0 +OUTPUTMC | 28 | 1 | 14 | 0 | 17 | 1 | 0 | 5 | 16 | 1 | 10 | 2 | 15 | 1 | 9 | 4 | 17 | 4 | 14 | 4 | 13 | 4 | 15 | 2 | 17 | 2 | 16 | 1 | 2 | 1 | 11 | 4 | 12 | 0 | 6 | 0 | 0 | 0 | 15 | 0 | 16 | 1 | 1 | 1 | 12 | 1 | 13 | 1 | 15 | 1 | 17 | 5 | 15 | 5 | 17 | 3 | 17 +INPUTS | 14 | A<23> | A<22> | A<21> | A<19> | AUTO_CONFIG_DONE<0> | BERR | A<17> | A<16> | A<20> | A<18> | AUTO_CONFIG_DONE<1> | AUTO_CONFIG_DONE<2> | ide/ide_CLKF | IDE_BASEADR<5> +INPUTMC | 5 | 1 | 8 | 2 | 14 | 1 | 7 | 3 | 15 | 4 | 13 +INPUTP | 9 | 96 | 97 | 98 | 103 | 109 | 106 | 108 | 102 | 105 +EXPORTS | 1 | 3 | 17 +EQ | 8 | + autoconfig.D = A<23> & A<22> & A<21> & A<19> & + !AUTO_CONFIG_DONE<0> & BERR & !A<17> & !A<16> & !A<20> & !A<18> + # A<23> & A<22> & A<21> & A<19> & + !AUTO_CONFIG_DONE<1> & BERR & !A<17> & !A<16> & !A<20> & !A<18> + # A<23> & A<22> & A<21> & A<19> & + !AUTO_CONFIG_DONE<2> & BERR & !A<17> & !A<16> & !A<20> & !A<18>; + autoconfig.CLK = ide/ide_CLKF; + autoconfig.EXP = A<21> & !IDE_BASEADR<5> + +MACROCELL | 3 | 0 | ide +ATTRIBUTES | 8520480 | 0 +OUTPUTMC | 3 | 0 | 9 | 0 | 13 | 0 | 14 +INPUTS | 7 | BERR | SHUT_UP<1> | A<19> | IDE_BASEADR<3> | EXP19_.EXP | EXP21_.EXP | ide/ide_CLKF +INPUTMC | 5 | 4 | 12 | 2 | 16 | 3 | 1 | 3 | 17 | 3 | 15 +INPUTP | 2 | 109 | 103 +IMPORTS | 2 | 3 | 1 | 3 | 17 +EQ | 23 | + !ide.D = SHUT_UP<1> + # !BERR + # A<19> & !IDE_BASEADR<3> + # !A<19> & IDE_BASEADR<3> +;Imported pterms FB4_2 + # A<23> & !IDE_BASEADR<7> + # !A<23> & IDE_BASEADR<7> + # A<22> & !IDE_BASEADR<6> + # !A<22> & IDE_BASEADR<6> + # IDE_BASEADR<1> & !A<17> +;Imported pterms FB4_3 + # !A<21> & IDE_BASEADR<5> + # IDE_BASEADR<4> & !A<20> + # !IDE_BASEADR<4> & A<20> +;Imported pterms FB4_18 + # IDE_BASEADR<0> & !A<16> + # !IDE_BASEADR<0> & A<16> + # !IDE_BASEADR<1> & A<17> + # IDE_BASEADR<2> & !A<18> + # !IDE_BASEADR<2> & A<18> +;Imported pterms FB4_17 + # A<21> & !IDE_BASEADR<5>; + ide.CLK = ide/ide_CLKF; + +MACROCELL | 0 | 6 | AUTOCONFIG_IN_PROGRESS +ATTRIBUTES | 8520480 | 0 +OUTPUTMC | 16 | 2 | 11 | 2 | 3 | 2 | 6 | 2 | 9 | 2 | 8 | 0 | 4 | 0 | 1 | 1 | 4 | 1 | 15 | 0 | 5 | 0 | 7 | 1 | 16 | 2 | 0 | 0 | 2 | 2 | 10 | 2 | 2 +INPUTS | 3 | AS | autoconfig | ide/ide_CLKF +INPUTMC | 2 | 3 | 16 | 3 | 15 +INPUTP | 1 | 90 +EQ | 2 | + AUTOCONFIG_IN_PROGRESS.D = !AS & autoconfig; + AUTOCONFIG_IN_PROGRESS.CLK = ide/ide_CLKF; + +MACROCELL | 0 | 13 | IDE_R_S +ATTRIBUTES | 8651558 | 0 +INPUTS | 6 | RESET | RW | AS | IDE_ENABLE | ide | ide/ide_CLKF +INPUTMC | 3 | 0 | 9 | 3 | 0 | 3 | 15 +INPUTP | 3 | 160 | 93 | 90 +EQ | 2 | + !IDE_R.D = RESET & RW & !AS & !IDE_ENABLE & ide; + IDE_R.CLK = ide/ide_CLKF; + +MACROCELL | 0 | 14 | IDE_W_S +ATTRIBUTES | 8651558 | 0 +OUTPUTMC | 1 | 0 | 15 +INPUTS | 6 | RESET | RW | AS | ide | ide/ide_CLKF | IDE_ENABLE +INPUTMC | 3 | 3 | 0 | 3 | 15 | 0 | 9 +INPUTP | 3 | 160 | 93 | 90 +EXPORTS | 1 | 0 | 15 +EQ | 3 | + !IDE_W.D = RESET & !RW & !AS & ide; + IDE_W.CLK = ide/ide_CLKF; + IDE_W_S.EXP = RESET & RW & !AS & IDE_ENABLE & ide + +MACROCELL | 0 | 15 | ROM_OE_S +ATTRIBUTES | 8651558 | 0 +OUTPUTMC | 1 | 0 | 16 +INPUTS | 15 | RESET | RW | AS | A<5> | A<4> | ide/ide_CLKF | A<1> | A<6> | A<3> | A<2> | AUTO_CONFIG_DONE<2> | autoconfig | AUTO_CONFIG_DONE<0> | AUTO_CONFIG_DONE<1> | IDE_W_S.EXP +INPUTMC | 6 | 3 | 15 | 1 | 7 | 3 | 16 | 1 | 8 | 2 | 14 | 0 | 14 +INPUTP | 9 | 160 | 93 | 90 | 54 | 56 | 63 | 57 | 58 | 60 +EXPORTS | 1 | 0 | 16 +IMPORTS | 1 | 0 | 14 +EQ | 14 | + !ROM_OE.D = ;Imported pterms FB1_15 + RESET & RW & !AS & IDE_ENABLE & ide; + ROM_OE.CLK = ide/ide_CLKF; + ROM_OE_S.EXP = RESET & RW & !AS & A<5> & !A<4> & A<1> & !A<6> & + !A<3> & A<2> & !AUTO_CONFIG_DONE<2> & autoconfig + # RESET & RW & !AS & A<5> & !A<4> & !A<6> & !A<3> & + A<2> & AUTO_CONFIG_DONE<0> & !AUTO_CONFIG_DONE<1> & + autoconfig + # RESET & RW & !AS & !A<5> & A<4> & A<1> & !A<6> & + A<3> & AUTO_CONFIG_DONE<0> & !AUTO_CONFIG_DONE<1> & + autoconfig + # RESET & RW & !AS & !A<5> & !A<1> & !A<6> & !A<3> & + A<2> & AUTO_CONFIG_DONE<1> & !AUTO_CONFIG_DONE<2> & + autoconfig + +MACROCELL | 2 | 8 | N1 +ATTRIBUTES | 265986 | 0 +INPUTS | 2 | RW | AUTOCONFIG_IN_PROGRESS +INPUTMC | 1 | 0 | 6 +INPUTP | 1 | 93 +EQ | 2 | + D<9> = Vcc; + D<9>.OE = RW & AUTOCONFIG_IN_PROGRESS; + +MACROCELL | 0 | 4 | N1$BUF0 +ATTRIBUTES | 265986 | 0 +INPUTS | 2 | RW | AUTOCONFIG_IN_PROGRESS +INPUTMC | 1 | 0 | 6 +INPUTP | 1 | 93 +EQ | 2 | + D<8> = Vcc; + D<8>.OE = RW & AUTOCONFIG_IN_PROGRESS; + +MACROCELL | 0 | 1 | N1$BUF1 +ATTRIBUTES | 265986 | 0 +OUTPUTMC | 1 | 0 | 0 +INPUTS | 3 | RW | AUTOCONFIG_IN_PROGRESS | A<13> +INPUTMC | 1 | 0 | 6 +INPUTP | 2 | 93 | 72 +EXPORTS | 1 | 0 | 0 +EQ | 3 | + D<7> = Vcc; + D<7>.OE = RW & AUTOCONFIG_IN_PROGRESS; + N1$BUF1.EXP = !A<13> + +MACROCELL | 1 | 4 | N1$BUF10 +ATTRIBUTES | 265986 | 0 +INPUTS | 2 | RW | AUTOCONFIG_IN_PROGRESS +INPUTMC | 1 | 0 | 6 +INPUTP | 1 | 93 +EQ | 2 | + D<0> = Vcc; + D<0>.OE = RW & AUTOCONFIG_IN_PROGRESS; + +MACROCELL | 1 | 15 | N1$BUF2 +ATTRIBUTES | 265986 | 0 +OUTPUTMC | 1 | 1 | 14 +INPUTS | 14 | RW | AUTOCONFIG_IN_PROGRESS | RESET | AS | A<5> | A<4> | A<3> | A<2> | AUTO_CONFIG_DONE<2> | autoconfig | A<1> | A<6> | AUTO_CONFIG_DONE<1> | AUTO_CONFIG_DONE<0> +INPUTMC | 5 | 0 | 6 | 1 | 7 | 3 | 16 | 2 | 14 | 1 | 8 +INPUTP | 9 | 93 | 160 | 90 | 54 | 56 | 58 | 60 | 63 | 57 +EXPORTS | 1 | 1 | 14 +EQ | 11 | + D<6> = Vcc; + D<6>.OE = RW & AUTOCONFIG_IN_PROGRESS; + N1$BUF2.EXP = RESET & RW & !AS & !A<5> & !A<4> & !A<3> & !A<2> & + !AUTO_CONFIG_DONE<2> & autoconfig + # RESET & RW & !AS & !A<5> & !A<4> & A<1> & !A<6> & + !A<3> & !AUTO_CONFIG_DONE<1> & autoconfig + # RESET & RW & !AS & !A<5> & A<1> & !A<6> & !A<3> & + !A<2> & !AUTO_CONFIG_DONE<0> & autoconfig + # RESET & RW & !AS & !A<5> & A<4> & !A<1> & !A<6> & + A<2> & AUTO_CONFIG_DONE<0> & !AUTO_CONFIG_DONE<1> & + autoconfig + +MACROCELL | 0 | 5 | N1$BUF3 +ATTRIBUTES | 265986 | 0 +INPUTS | 2 | RW | AUTOCONFIG_IN_PROGRESS +INPUTMC | 1 | 0 | 6 +INPUTP | 1 | 93 +EQ | 2 | + D<5> = Vcc; + D<5>.OE = RW & AUTOCONFIG_IN_PROGRESS; + +MACROCELL | 0 | 7 | N1$BUF4 +ATTRIBUTES | 265986 | 0 +INPUTS | 2 | RW | AUTOCONFIG_IN_PROGRESS +INPUTMC | 1 | 0 | 6 +INPUTP | 1 | 93 +EQ | 2 | + D<4> = Vcc; + D<4>.OE = RW & AUTOCONFIG_IN_PROGRESS; + +MACROCELL | 1 | 16 | N1$BUF5 +ATTRIBUTES | 265986 | 0 +INPUTS | 2 | RW | AUTOCONFIG_IN_PROGRESS +INPUTMC | 1 | 0 | 6 +INPUTP | 1 | 93 +EQ | 2 | + D<3> = Vcc; + D<3>.OE = RW & AUTOCONFIG_IN_PROGRESS; + +MACROCELL | 2 | 0 | N1$BUF6 +ATTRIBUTES | 265986 | 0 +INPUTS | 2 | RW | AUTOCONFIG_IN_PROGRESS +INPUTMC | 1 | 0 | 6 +INPUTP | 1 | 93 +EQ | 2 | + D<2> = Vcc; + D<2>.OE = RW & AUTOCONFIG_IN_PROGRESS; + +MACROCELL | 0 | 2 | N1$BUF7 +ATTRIBUTES | 265986 | 0 +INPUTS | 2 | RW | AUTOCONFIG_IN_PROGRESS +INPUTMC | 1 | 0 | 6 +INPUTP | 1 | 93 +EQ | 2 | + D<1> = Vcc; + D<1>.OE = RW & AUTOCONFIG_IN_PROGRESS; + +MACROCELL | 2 | 10 | N1$BUF8 +ATTRIBUTES | 265986 | 0 +INPUTS | 2 | RW | AUTOCONFIG_IN_PROGRESS +INPUTMC | 1 | 0 | 6 +INPUTP | 1 | 93 +EQ | 2 | + D<11> = Vcc; + D<11>.OE = RW & AUTOCONFIG_IN_PROGRESS; + +MACROCELL | 2 | 2 | N1$BUF9 +ATTRIBUTES | 265986 | 0 +INPUTS | 2 | RW | AUTOCONFIG_IN_PROGRESS +INPUTMC | 1 | 0 | 6 +INPUTP | 1 | 93 +EQ | 2 | + D<10> = Vcc; + D<10>.OE = RW & AUTOCONFIG_IN_PROGRESS; + +MACROCELL | 0 | 10 | IDE_A_0_OBUF$BUF0 +ATTRIBUTES | 264962 | 0 +INPUTS | 1 | A<9> +INPUTP | 1 | 64 +EQ | 1 | + IDE_A<0> = A<9>; + +MACROCELL | 0 | 11 | IDE_A_1_OBUF$BUF0 +ATTRIBUTES | 264962 | 0 +INPUTS | 1 | A<10> +INPUTP | 1 | 66 +EQ | 1 | + IDE_A<1> = A<10>; + +MACROCELL | 0 | 3 | IDE_A_2_OBUF$BUF0 +ATTRIBUTES | 264962 | 0 +INPUTS | 1 | A<11> +INPUTP | 1 | 68 +EQ | 1 | + IDE_A<2> = A<11>; + +MACROCELL | 0 | 8 | IDE_CS_0_OBUF +ATTRIBUTES | 264962 | 0 +INPUTS | 1 | A<12> +INPUTP | 1 | 69 +EQ | 1 | + IDE_CS<0> = !A<12>; + +MACROCELL | 0 | 0 | IDE_CS_1_OBUF +ATTRIBUTES | 264962 | 0 +OUTPUTMC | 1 | 0 | 17 +INPUTS | 14 | RESET | RW | AS | A<5> | A<4> | A<6> | A<3> | A<2> | AUTO_CONFIG_DONE<0> | autoconfig | AUTO_CONFIG_DONE<1> | AUTO_CONFIG_DONE<2> | A<1> | N1$BUF1.EXP +INPUTMC | 5 | 1 | 8 | 3 | 16 | 2 | 14 | 1 | 7 | 0 | 1 +INPUTP | 9 | 160 | 93 | 90 | 54 | 56 | 57 | 58 | 60 | 63 +EXPORTS | 1 | 0 | 17 +IMPORTS | 1 | 0 | 1 +EQ | 13 | + IDE_CS<1> = ;Imported pterms FB1_2 + !A<13>; + IDE_CS_1_OBUF.EXP = RESET & RW & !AS & !A<5> & !A<4> & A<6> & !A<3> & + !A<2> & !AUTO_CONFIG_DONE<0> & autoconfig + # RESET & RW & !AS & !A<5> & !A<4> & A<6> & !A<3> & + !A<2> & !AUTO_CONFIG_DONE<1> & autoconfig + # RESET & RW & !AS & !A<5> & !A<4> & A<6> & !A<3> & + !A<2> & !AUTO_CONFIG_DONE<2> & autoconfig + # RESET & RW & !AS & !A<5> & !A<1> & !A<6> & !A<3> & + A<2> & !AUTO_CONFIG_DONE<0> & autoconfig + # RESET & RW & !AS & A<5> & !A<4> & A<1> & !A<6> & + A<2> & AUTO_CONFIG_DONE<0> & !AUTO_CONFIG_DONE<1> & + autoconfig + +MACROCELL | 6 | 11 | ROM_B_0_OBUF$BUF1 +ATTRIBUTES | 265986 | 0 +INPUTS | 0 +EQ | 2 | + DTACK = Gnd; + DTACK.OE = Gnd; + +MACROCELL | 4 | 16 | ROM_B_0_OBUF +ATTRIBUTES | 264962 | 0 +INPUTS | 0 +EQ | 1 | + ROM_B<1> = Gnd; + +MACROCELL | 4 | 9 | ROM_B_0_OBUF$BUF0 +ATTRIBUTES | 264962 | 0 +INPUTS | 0 +EQ | 1 | + ROM_B<0> = Gnd; + +MACROCELL | 3 | 15 | ide/ide_CLKF +ATTRIBUTES | 133888 | 0 +OUTPUTMC | 23 | 1 | 14 | 0 | 17 | 1 | 0 | 5 | 16 | 1 | 10 | 2 | 15 | 1 | 9 | 4 | 17 | 4 | 14 | 4 | 13 | 0 | 9 | 4 | 15 | 2 | 17 | 2 | 16 | 1 | 12 | 1 | 11 | 4 | 12 | 3 | 16 | 3 | 0 | 0 | 6 | 0 | 13 | 0 | 14 | 0 | 15 +INPUTS | 2 | C3 | C1 +INPUTP | 2 | 114 | 115 +EQ | 2 | + !ide/ide_CLKF = C3 + $ C1; + +MACROCELL | 2 | 3 | _10_ +ATTRIBUTES | 397058 | 0 +OUTPUTMC | 1 | 0 | 16 +INPUTS | 3 | RW | AUTOCONFIG_IN_PROGRESS | D<12>_BUFR +INPUTMC | 2 | 0 | 6 | 0 | 17 +INPUTP | 1 | 93 +EQ | 2 | + D<12> = D<12>_BUFR; + D<12>.OE = RW & AUTOCONFIG_IN_PROGRESS; + +MACROCELL | 2 | 6 | _11_ +ATTRIBUTES | 397058 | 0 +OUTPUTMC | 1 | 1 | 17 +INPUTS | 3 | RW | AUTOCONFIG_IN_PROGRESS | D<14>_BUFR +INPUTMC | 2 | 0 | 6 | 1 | 0 +INPUTP | 1 | 93 +EQ | 2 | + D<14> = D<14>_BUFR; + D<14>.OE = RW & AUTOCONFIG_IN_PROGRESS; + +MACROCELL | 2 | 11 | _12_ +ATTRIBUTES | 397058 | 0 +OUTPUTMC | 2 | 1 | 14 | 1 | 13 +INPUTS | 3 | RW | AUTOCONFIG_IN_PROGRESS | D<13>_BUFR +INPUTMC | 2 | 0 | 6 | 1 | 14 +INPUTP | 1 | 93 +EQ | 2 | + D<13> = D<13>_BUFR; + D<13>.OE = RW & AUTOCONFIG_IN_PROGRESS; + +MACROCELL | 2 | 9 | _13_ +ATTRIBUTES | 397058 | 0 +OUTPUTMC | 2 | 5 | 16 | 5 | 15 +INPUTS | 3 | RW | AUTOCONFIG_IN_PROGRESS | D<15>_BUFR +INPUTMC | 2 | 0 | 6 | 5 | 16 +INPUTP | 1 | 93 +EQ | 2 | + D<15> = D<15>_BUFR; + D<15>.OE = RW & AUTOCONFIG_IN_PROGRESS; + +MACROCELL | 0 | 16 | EXP14_ +ATTRIBUTES | 2048 | 0 +OUTPUTMC | 1 | 0 | 17 +INPUTS | 14 | RESET | D<12> | RW | AS | autoconfig | AUTO_CONFIG_DONE<0> | AUTO_CONFIG_DONE<1> | AUTO_CONFIG_DONE<2> | A<5> | A<4> | A<1> | A<3> | A<2> | ROM_OE_S.EXP +INPUTMC | 6 | 2 | 3 | 3 | 16 | 1 | 8 | 2 | 14 | 1 | 7 | 0 | 15 +INPUTP | 8 | 160 | 93 | 90 | 54 | 56 | 63 | 58 | 60 +EXPORTS | 1 | 0 | 17 +IMPORTS | 1 | 0 | 15 +EQ | 19 | + EXP14_.EXP = RESET & !D<12> & !RW + # RESET & !D<12> & AS + # RESET & !D<12> & !autoconfig + # RESET & !D<12> & AUTO_CONFIG_DONE<0> & + AUTO_CONFIG_DONE<1> & AUTO_CONFIG_DONE<2> + # RESET & RW & !AS & !A<5> & !A<4> & !A<1> & !A<3> & + !A<2> & !AUTO_CONFIG_DONE<0> & autoconfig +;Imported pterms FB1_16 + # RESET & RW & !AS & A<5> & !A<4> & A<1> & !A<6> & + !A<3> & A<2> & !AUTO_CONFIG_DONE<2> & autoconfig + # RESET & RW & !AS & A<5> & !A<4> & !A<6> & !A<3> & + A<2> & AUTO_CONFIG_DONE<0> & !AUTO_CONFIG_DONE<1> & + autoconfig + # RESET & RW & !AS & !A<5> & A<4> & A<1> & !A<6> & + A<3> & AUTO_CONFIG_DONE<0> & !AUTO_CONFIG_DONE<1> & + autoconfig + # RESET & RW & !AS & !A<5> & !A<1> & !A<6> & !A<3> & + A<2> & AUTO_CONFIG_DONE<1> & !AUTO_CONFIG_DONE<2> & + autoconfig + +MACROCELL | 1 | 1 | EXP15_ +ATTRIBUTES | 2048 | 0 +OUTPUTMC | 1 | 1 | 0 +INPUTS | 14 | RESET | RW | AS | A<5> | A<4> | A<1> | A<3> | A<2> | AUTO_CONFIG_DONE<0> | autoconfig | A<6> | AUTO_CONFIG_DONE<1> | AUTO_CONFIG_DONE<2> | EXP16_.EXP +INPUTMC | 5 | 1 | 8 | 3 | 16 | 2 | 14 | 1 | 7 | 1 | 2 +INPUTP | 9 | 160 | 93 | 90 | 54 | 56 | 63 | 58 | 60 | 57 +EXPORTS | 1 | 1 | 0 +IMPORTS | 1 | 1 | 2 +EQ | 19 | + EXP15_.EXP = RESET & RW & !AS & !A<5> & !A<4> & A<1> & !A<3> & + !A<2> & !AUTO_CONFIG_DONE<0> & autoconfig + # RESET & RW & !AS & !A<5> & !A<4> & A<6> & !A<3> & + !A<2> & !AUTO_CONFIG_DONE<0> & autoconfig + # RESET & RW & !AS & !A<5> & !A<4> & A<6> & !A<3> & + !A<2> & !AUTO_CONFIG_DONE<1> & autoconfig + # RESET & RW & !AS & !A<5> & !A<4> & A<6> & !A<3> & + !A<2> & !AUTO_CONFIG_DONE<2> & autoconfig + # RESET & RW & !AS & !A<4> & A<1> & !A<6> & !A<3> & + A<2> & AUTO_CONFIG_DONE<0> & !AUTO_CONFIG_DONE<1> & + autoconfig +;Imported pterms FB2_3 + # RESET & RW & !AS & !A<5> & A<4> & A<1> & !A<6> & + !A<3> & A<2> & !AUTO_CONFIG_DONE<0> & autoconfig + # RESET & RW & !AS & !A<5> & !A<4> & !A<1> & !A<6> & + !A<3> & A<2> & !AUTO_CONFIG_DONE<0> & autoconfig + # RESET & RW & !AS & !A<5> & A<4> & !A<1> & !A<6> & + A<3> & A<2> & AUTO_CONFIG_DONE<0> & !AUTO_CONFIG_DONE<1> & + autoconfig + +MACROCELL | 1 | 2 | EXP16_ +ATTRIBUTES | 2048 | 0 +OUTPUTMC | 1 | 1 | 1 +INPUTS | 12 | RESET | RW | AS | A<5> | A<4> | A<1> | A<6> | A<3> | A<2> | AUTO_CONFIG_DONE<0> | autoconfig | AUTO_CONFIG_DONE<1> +INPUTMC | 3 | 1 | 8 | 3 | 16 | 2 | 14 +INPUTP | 9 | 160 | 93 | 90 | 54 | 56 | 63 | 57 | 58 | 60 +EXPORTS | 1 | 1 | 1 +EQ | 7 | + EXP16_.EXP = RESET & RW & !AS & !A<5> & A<4> & A<1> & !A<6> & + !A<3> & A<2> & !AUTO_CONFIG_DONE<0> & autoconfig + # RESET & RW & !AS & !A<5> & !A<4> & !A<1> & !A<6> & + !A<3> & A<2> & !AUTO_CONFIG_DONE<0> & autoconfig + # RESET & RW & !AS & !A<5> & A<4> & !A<1> & !A<6> & + A<3> & A<2> & AUTO_CONFIG_DONE<0> & !AUTO_CONFIG_DONE<1> & + autoconfig + +MACROCELL | 1 | 13 | EXP17_ +ATTRIBUTES | 2048 | 0 +OUTPUTMC | 1 | 1 | 14 +INPUTS | 14 | RESET | D<13> | RW | AUTO_CONFIG_DONE<0> | AUTO_CONFIG_DONE<1> | AUTO_CONFIG_DONE<2> | AS | A<5> | A<4> | A<6> | A<3> | autoconfig | A<2> | IDE_BASEADR<6>.EXP +INPUTMC | 6 | 2 | 11 | 1 | 8 | 2 | 14 | 1 | 7 | 3 | 16 | 1 | 12 +INPUTP | 8 | 160 | 93 | 90 | 54 | 56 | 57 | 58 | 60 +EXPORTS | 1 | 1 | 14 +IMPORTS | 1 | 1 | 12 +EQ | 19 | + EXP17_.EXP = RESET & !D<13> & !RW + # RESET & !D<13> & AUTO_CONFIG_DONE<0> & + AUTO_CONFIG_DONE<1> & AUTO_CONFIG_DONE<2> + # RESET & RW & !AS & !A<5> & !A<4> & !A<6> & !A<3> & + !AUTO_CONFIG_DONE<0> & autoconfig + # RESET & RW & !AS & !A<5> & !A<4> & !A<3> & !A<2> & + !AUTO_CONFIG_DONE<0> & autoconfig + # RESET & RW & !AS & !A<5> & !A<4> & !A<3> & !A<2> & + !AUTO_CONFIG_DONE<1> & autoconfig +;Imported pterms FB2_13 + # RESET & RW & !AS & !A<5> & A<4> & !A<1> & !A<6> & + A<3> & AUTO_CONFIG_DONE<0> & !AUTO_CONFIG_DONE<1> & + autoconfig + # RESET & RW & !AS & !A<5> & !A<4> & !A<1> & !A<6> & + !A<3> & AUTO_CONFIG_DONE<1> & !AUTO_CONFIG_DONE<2> & + autoconfig + # RESET & RW & !AS & A<5> & !A<4> & !A<1> & !A<6> & + !A<3> & A<2> & AUTO_CONFIG_DONE<0> & !AUTO_CONFIG_DONE<1> & + autoconfig + +MACROCELL | 1 | 17 | EXP18_ +ATTRIBUTES | 2048 | 0 +OUTPUTMC | 1 | 1 | 0 +INPUTS | 13 | RESET | D<14> | RW | AS | autoconfig | AUTO_CONFIG_DONE<0> | AUTO_CONFIG_DONE<1> | AUTO_CONFIG_DONE<2> | A<5> | A<1> | A<6> | A<3> | A<2> +INPUTMC | 5 | 2 | 6 | 3 | 16 | 1 | 8 | 2 | 14 | 1 | 7 +INPUTP | 8 | 160 | 93 | 90 | 54 | 63 | 57 | 58 | 60 +EXPORTS | 1 | 1 | 0 +EQ | 8 | + EXP18_.EXP = RESET & !D<14> & !RW + # RESET & !D<14> & AS + # RESET & !D<14> & !autoconfig + # RESET & !D<14> & AUTO_CONFIG_DONE<0> & + AUTO_CONFIG_DONE<1> & AUTO_CONFIG_DONE<2> + # RESET & RW & !AS & !A<5> & A<1> & !A<6> & !A<3> & + A<2> & AUTO_CONFIG_DONE<0> & !AUTO_CONFIG_DONE<2> & + autoconfig + +MACROCELL | 3 | 1 | EXP19_ +ATTRIBUTES | 2048 | 0 +OUTPUTMC | 1 | 3 | 0 +INPUTS | 7 | A<23> | IDE_BASEADR<7> | A<22> | IDE_BASEADR<6> | IDE_BASEADR<1> | A<17> | EXP20_.EXP +INPUTMC | 4 | 1 | 11 | 1 | 12 | 4 | 15 | 3 | 2 +INPUTP | 3 | 96 | 97 | 106 +EXPORTS | 1 | 3 | 0 +IMPORTS | 1 | 3 | 2 +EQ | 9 | + EXP19_.EXP = A<23> & !IDE_BASEADR<7> + # !A<23> & IDE_BASEADR<7> + # A<22> & !IDE_BASEADR<6> + # !A<22> & IDE_BASEADR<6> + # IDE_BASEADR<1> & !A<17> +;Imported pterms FB4_3 + # !A<21> & IDE_BASEADR<5> + # IDE_BASEADR<4> & !A<20> + # !IDE_BASEADR<4> & A<20> + +MACROCELL | 3 | 2 | EXP20_ +ATTRIBUTES | 2048 | 0 +OUTPUTMC | 1 | 3 | 1 +INPUTS | 4 | A<21> | IDE_BASEADR<5> | IDE_BASEADR<4> | A<20> +INPUTMC | 2 | 4 | 13 | 4 | 14 +INPUTP | 2 | 98 | 102 +EXPORTS | 1 | 3 | 1 +EQ | 3 | + EXP20_.EXP = !A<21> & IDE_BASEADR<5> + # IDE_BASEADR<4> & !A<20> + # !IDE_BASEADR<4> & A<20> + +MACROCELL | 3 | 17 | EXP21_ +ATTRIBUTES | 2048 | 0 +OUTPUTMC | 1 | 3 | 0 +INPUTS | 7 | IDE_BASEADR<0> | A<16> | IDE_BASEADR<1> | A<17> | IDE_BASEADR<2> | A<18> | autoconfig.EXP +INPUTMC | 4 | 4 | 17 | 4 | 15 | 2 | 17 | 3 | 16 +INPUTP | 3 | 108 | 106 | 105 +EXPORTS | 1 | 3 | 0 +IMPORTS | 1 | 3 | 16 +EQ | 7 | + EXP21_.EXP = IDE_BASEADR<0> & !A<16> + # !IDE_BASEADR<0> & A<16> + # !IDE_BASEADR<1> & A<17> + # IDE_BASEADR<2> & !A<18> + # !IDE_BASEADR<2> & A<18> +;Imported pterms FB4_17 + # A<21> & !IDE_BASEADR<5> + +MACROCELL | 5 | 15 | EXP22_ +ATTRIBUTES | 2048 | 0 +OUTPUTMC | 1 | 5 | 16 +INPUTS | 14 | RESET | D<15> | AUTO_CONFIG_DONE<0> | AUTO_CONFIG_DONE<1> | AUTO_CONFIG_DONE<2> | RW | AS | A<5> | A<1> | A<6> | A<3> | autoconfig | A<4> | A<2> +INPUTMC | 5 | 2 | 9 | 1 | 8 | 2 | 14 | 1 | 7 | 3 | 16 +INPUTP | 9 | 160 | 93 | 90 | 54 | 63 | 57 | 58 | 56 | 60 +EXPORTS | 1 | 5 | 16 +EQ | 8 | + EXP22_.EXP = RESET & !D<15> & AUTO_CONFIG_DONE<0> & + AUTO_CONFIG_DONE<1> & AUTO_CONFIG_DONE<2> + # RESET & RW & !AS & !A<5> & A<1> & !A<6> & !A<3> & + !AUTO_CONFIG_DONE<0> & autoconfig + # RESET & RW & !AS & !A<5> & !A<4> & A<6> & !A<3> & + !A<2> & !AUTO_CONFIG_DONE<0> & autoconfig + # RESET & RW & !AS & !A<5> & !A<4> & A<6> & !A<3> & + !A<2> & !AUTO_CONFIG_DONE<1> & autoconfig + +MACROCELL | 5 | 17 | EXP23_ +ATTRIBUTES | 2048 | 0 +OUTPUTMC | 1 | 5 | 16 +INPUTS | 13 | RESET | RW | AS | A<5> | A<4> | A<6> | A<3> | A<2> | AUTO_CONFIG_DONE<2> | autoconfig | A<1> | AUTO_CONFIG_DONE<1> | AUTO_CONFIG_DONE<0> +INPUTMC | 4 | 1 | 7 | 3 | 16 | 2 | 14 | 1 | 8 +INPUTP | 9 | 160 | 93 | 90 | 54 | 56 | 57 | 58 | 60 | 63 +EXPORTS | 1 | 5 | 16 +EQ | 13 | + EXP23_.EXP = RESET & RW & !AS & !A<5> & !A<4> & A<6> & !A<3> & + !A<2> & !AUTO_CONFIG_DONE<2> & autoconfig + # RESET & RW & !AS & !A<5> & A<1> & !A<6> & !A<3> & + AUTO_CONFIG_DONE<1> & !AUTO_CONFIG_DONE<2> & autoconfig + # RESET & RW & !AS & !A<5> & A<4> & A<1> & !A<6> & + A<2> & AUTO_CONFIG_DONE<0> & !AUTO_CONFIG_DONE<1> & + autoconfig + # RESET & RW & !AS & A<5> & !A<4> & !A<1> & !A<6> & + !A<3> & A<2> & AUTO_CONFIG_DONE<0> & !AUTO_CONFIG_DONE<1> & + autoconfig + # RESET & RW & !AS & !A<5> & A<4> & !A<1> & !A<6> & + A<3> & !A<2> & AUTO_CONFIG_DONE<0> & !AUTO_CONFIG_DONE<1> & + autoconfig + +PIN | RESET | 65600 | 0 | N/A | 160 | 32 | 1 | 14 | 0 | 17 | 1 | 0 | 5 | 16 | 1 | 10 | 2 | 15 | 1 | 9 | 4 | 17 | 4 | 14 | 4 | 13 | 0 | 9 | 4 | 15 | 2 | 17 | 2 | 16 | 1 | 12 | 1 | 11 | 4 | 12 | 0 | 13 | 0 | 14 | 0 | 0 | 0 | 15 | 0 | 16 | 1 | 1 | 1 | 2 | 1 | 13 | 1 | 15 | 1 | 17 | 5 | 15 | 5 | 17 | 1 | 8 | 2 | 14 | 1 | 7 +PIN | RW | 64 | 0 | N/A | 93 | 44 | 1 | 14 | 0 | 17 | 1 | 0 | 5 | 16 | 1 | 10 | 2 | 15 | 1 | 9 | 4 | 17 | 4 | 14 | 4 | 13 | 0 | 9 | 4 | 15 | 2 | 17 | 2 | 16 | 1 | 2 | 1 | 11 | 4 | 12 | 0 | 13 | 0 | 14 | 0 | 0 | 2 | 8 | 0 | 4 | 0 | 1 | 1 | 4 | 1 | 15 | 0 | 5 | 0 | 7 | 1 | 16 | 2 | 0 | 0 | 2 | 2 | 10 | 2 | 2 | 2 | 3 | 2 | 6 | 2 | 11 | 2 | 9 | 0 | 15 | 0 | 16 | 1 | 1 | 1 | 12 | 1 | 13 | 1 | 17 | 5 | 15 | 5 | 17 +PIN | A<1> | 64 | 0 | N/A | 63 | 25 | 1 | 14 | 0 | 17 | 1 | 0 | 5 | 16 | 1 | 10 | 2 | 15 | 1 | 9 | 4 | 17 | 4 | 14 | 4 | 13 | 4 | 15 | 2 | 17 | 2 | 16 | 1 | 2 | 1 | 11 | 4 | 12 | 0 | 0 | 0 | 15 | 0 | 16 | 1 | 1 | 1 | 12 | 1 | 15 | 1 | 17 | 5 | 15 | 5 | 17 +PIN | A<2> | 64 | 0 | N/A | 60 | 24 | 1 | 14 | 0 | 17 | 1 | 0 | 5 | 16 | 4 | 17 | 4 | 14 | 4 | 13 | 4 | 15 | 2 | 17 | 2 | 16 | 1 | 10 | 1 | 11 | 4 | 12 | 0 | 0 | 0 | 15 | 0 | 16 | 1 | 1 | 1 | 2 | 1 | 12 | 1 | 13 | 1 | 15 | 1 | 17 | 5 | 15 | 5 | 17 +PIN | A<5> | 64 | 0 | N/A | 54 | 26 | 1 | 14 | 0 | 17 | 1 | 0 | 5 | 16 | 1 | 10 | 2 | 15 | 1 | 9 | 4 | 17 | 4 | 14 | 4 | 13 | 4 | 15 | 2 | 17 | 2 | 16 | 1 | 2 | 1 | 11 | 4 | 12 | 0 | 0 | 0 | 15 | 0 | 16 | 1 | 1 | 1 | 12 | 1 | 13 | 1 | 15 | 1 | 17 | 5 | 15 | 5 | 17 +PIN | A<6> | 64 | 0 | N/A | 57 | 25 | 1 | 14 | 0 | 17 | 1 | 0 | 5 | 16 | 1 | 10 | 2 | 15 | 1 | 9 | 4 | 17 | 4 | 14 | 4 | 13 | 4 | 15 | 2 | 17 | 2 | 16 | 1 | 2 | 1 | 11 | 4 | 12 | 0 | 0 | 0 | 15 | 1 | 1 | 1 | 12 | 1 | 13 | 1 | 15 | 1 | 17 | 5 | 15 | 5 | 17 +PIN | A<3> | 64 | 0 | N/A | 58 | 26 | 1 | 14 | 0 | 17 | 1 | 0 | 5 | 16 | 1 | 10 | 2 | 15 | 1 | 9 | 4 | 17 | 4 | 14 | 4 | 13 | 4 | 15 | 2 | 17 | 2 | 16 | 1 | 2 | 1 | 11 | 4 | 12 | 0 | 0 | 0 | 15 | 0 | 16 | 1 | 1 | 1 | 12 | 1 | 13 | 1 | 15 | 1 | 17 | 5 | 15 | 5 | 17 +PIN | AS | 64 | 0 | N/A | 90 | 33 | 1 | 14 | 0 | 17 | 1 | 0 | 5 | 16 | 1 | 8 | 2 | 14 | 1 | 7 | 1 | 10 | 2 | 15 | 1 | 9 | 4 | 17 | 4 | 14 | 4 | 13 | 0 | 9 | 4 | 15 | 2 | 17 | 2 | 16 | 1 | 2 | 1 | 11 | 4 | 12 | 0 | 6 | 0 | 13 | 0 | 14 | 0 | 0 | 0 | 15 | 0 | 16 | 1 | 1 | 1 | 12 | 1 | 13 | 1 | 15 | 1 | 17 | 5 | 15 | 5 | 17 +PIN | A<4> | 64 | 0 | N/A | 56 | 24 | 1 | 14 | 0 | 17 | 1 | 0 | 5 | 15 | 1 | 10 | 2 | 15 | 1 | 9 | 4 | 17 | 4 | 14 | 4 | 13 | 4 | 15 | 2 | 17 | 2 | 16 | 1 | 2 | 1 | 11 | 4 | 12 | 0 | 0 | 0 | 15 | 0 | 16 | 1 | 1 | 1 | 12 | 1 | 13 | 1 | 15 | 5 | 17 +PIN | AUTOBOOT_OFF | 64 | 0 | N/A | 84 | 1 | 0 | 17 +PIN | UDS | 64 | 0 | N/A | 91 | 11 | 1 | 10 | 2 | 15 | 1 | 9 | 4 | 17 | 4 | 14 | 4 | 13 | 4 | 15 | 2 | 17 | 2 | 16 | 4 | 12 | 1 | 11 +PIN | A<23> | 64 | 0 | N/A | 96 | 2 | 3 | 16 | 3 | 1 +PIN | A<22> | 64 | 0 | N/A | 97 | 2 | 3 | 16 | 3 | 1 +PIN | A<21> | 64 | 0 | N/A | 98 | 2 | 3 | 16 | 3 | 2 +PIN | A<19> | 64 | 0 | N/A | 103 | 2 | 3 | 16 | 3 | 0 +PIN | BERR | 64 | 0 | N/A | 109 | 2 | 3 | 16 | 3 | 0 +PIN | C1 | 64 | 0 | N/A | 115 | 1 | 3 | 15 +PIN | C3 | 64 | 0 | N/A | 114 | 1 | 3 | 15 +PIN | A<16> | 64 | 0 | N/A | 108 | 2 | 3 | 16 | 3 | 17 +PIN | A<20> | 64 | 0 | N/A | 102 | 2 | 3 | 16 | 3 | 2 +PIN | A<17> | 64 | 0 | N/A | 106 | 3 | 3 | 16 | 3 | 1 | 3 | 17 +PIN | A<18> | 64 | 0 | N/A | 105 | 2 | 3 | 16 | 3 | 17 +PIN | A<9> | 64 | 0 | N/A | 64 | 1 | 0 | 10 +PIN | A<10> | 64 | 0 | N/A | 66 | 1 | 0 | 11 +PIN | A<11> | 64 | 0 | N/A | 68 | 1 | 0 | 3 +PIN | A<12> | 64 | 0 | N/A | 69 | 1 | 0 | 8 +PIN | A<13> | 64 | 0 | N/A | 72 | 1 | 0 | 1 +PIN | IDE_R | 536871040 | 0 | N/A | 29 +PIN | IDE_W | 536871040 | 0 | N/A | 30 +PIN | ROM_OE | 536871040 | 0 | N/A | 39 +PIN | D<7> | 536871040 | 0 | N/A | 18 +PIN | D<0> | 536871040 | 0 | N/A | 2 +PIN | D<6> | 536871040 | 0 | N/A | 16 +PIN | D<5> | 536871040 | 0 | N/A | 22 +PIN | D<4> | 536871040 | 0 | N/A | 23 +PIN | D<3> | 536871040 | 0 | N/A | 17 +PIN | D<2> | 536871040 | 0 | N/A | 43 +PIN | D<1> | 536871040 | 0 | N/A | 19 +PIN | IDE_A<0> | 536871040 | 0 | N/A | 26 +PIN | IDE_A<1> | 536871040 | 0 | N/A | 28 +PIN | IDE_A<2> | 536871040 | 0 | N/A | 27 +PIN | IDE_CS<0> | 536871040 | 0 | N/A | 24 +PIN | IDE_CS<1> | 536871040 | 0 | N/A | 25 +PIN | DTACK | 536871040 | 0 | N/A | 95 +PIN | ROM_B<1> | 536871040 | 0 | N/A | 77 +PIN | ROM_B<0> | 536871040 | 0 | N/A | 76 +PIN | D<13> | 536870976 | 0 | N/A | 49 | 1 | 4 | 13 +PIN | D<12> | 536870976 | 0 | N/A | 48 | 1 | 4 | 14 +PIN | D<14> | 536870976 | 0 | N/A | 50 | 1 | 1 | 11 +PIN | D<15> | 536870976 | 0 | N/A | 52 | 2 | 1 | 11 | 1 | 10 +PIN | D<9> | 536870976 | 0 | N/A | 44 | 1 | 4 | 15 +PIN | D<8> | 536870976 | 0 | N/A | 21 | 1 | 4 | 17 +PIN | D<11> | 536870976 | 0 | N/A | 47 | 1 | 2 | 16 +PIN | D<10> | 536870976 | 0 | N/A | 45 | 1 | 2 | 17 diff --git a/Logic/LAN_IDE/LAN_IDE_CP.nga b/Logic/LAN_IDE/LAN_IDE_CP.nga new file mode 100644 index 0000000..b09b633 --- /dev/null +++ b/Logic/LAN_IDE/LAN_IDE_CP.nga @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.6e +$2760=#Zl|/;6&?:183-c=/83:1<$.'0;294,773!;;<=4>01295567!890$3:*2056728>;<=4>4123-46< 8=;<7?80182356.991#=5>?:0:34?7?89#:<6&=712962672;=;<$??;)0;45<509:1>5>?)028,667839;<=4<012*64=/;9:;6>>?0;1345/' :?;<7=:0180156.991#?8>?:2734?5289#o7%:?0;634?278 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-0,0 +1,173 @@ +Release 8.1i - Fit P.68d +Copyright(c) 1995-2003 Xilinx Inc. All rights reserved + +12-15-2016 7:48PM + +NOTE: This file is designed to be imported into a spreadsheet program +such as Microsoft Excel for viewing, printing and sorting. The pipe '|' +character is used as the data field separator. +This file is also designed to support parsing. + +Input file: LAN_IDE_CP.ngd +output file: LAN_IDE_CP.pad +Part type: xc95144xl +Speed grade: -10 +Package: tq144 + +Pinout by Pin Number: + +-----|-----|-----|-----|-----|-----|-----|-----|-----|-----| +Pin Number|Signal Name|Pin Usage|Pin Name|Direction|IO Standard|IO Bank Number|{blank}|Slew Rate|Termination|{blank}|Voltage|Constraint| +P1|VCC||VCCIO|||||||||| +P2|D<0>|O|I/O/GTS3|OUTPUT||||||||| +P3|TIE||I/O/GTS4|||||||||| +P4|TIE||I/O|||||||||| +P5|TIE||I/O/GTS1|||||||||| +P6|TIE||I/O/GTS2|||||||||| +P7|TIE||I/O|||||||||| +P8|VCC||VCCINT|||||||||| +P9|TIE||I/O|||||||||| +P10|TIE||I/O|||||||||| +P11|TIE||I/O|||||||||| +P12|TIE||I/O|||||||||| +P13|TIE||I/O|||||||||| +P14|D<6>|O|I/O|OUTPUT||||||||| +P15|D<3>|O|I/O|OUTPUT||||||||| +P16|D<7>|O|I/O|OUTPUT||||||||| +P17|D<1>|O|I/O|OUTPUT||||||||| +P18|GND||GND|||||||||| +P19|D<8>|I/O|I/O|BIDIR||||||||| +P20|D<5>|O|I/O|OUTPUT||||||||| +P21|D<4>|O|I/O|OUTPUT||||||||| +P22|IDE_CS<0>|O|I/O|OUTPUT||||||||| +P23|IDE_CS<1>|O|I/O|OUTPUT||||||||| +P24|IDE_A<0>|O|I/O|OUTPUT||||||||| +P25|IDE_A<2>|O|I/O|OUTPUT||||||||| +P26|IDE_A<1>|O|I/O|OUTPUT||||||||| +P27|IDE_R|O|I/O|OUTPUT||||||||| +P28|IDE_W|O|I/O|OUTPUT||||||||| +P29|GND||GND|||||||||| +P30|TIE||I/O/GCK1|||||||||| +P31|TIE||I/O|||||||||| +P32|TIE||I/O/GCK2|||||||||| +P33|TIE||I/O|||||||||| +P34|TIE||I/O|||||||||| +P35|ROM_OE|O|I/O|OUTPUT||||||||| +P36|GND||GND|||||||||| +P37|VCC||VCCIO|||||||||| +P38|TIE||I/O/GCK3|||||||||| +P39|D<2>|O|I/O|OUTPUT||||||||| +P40|D<9>|I/O|I/O|BIDIR||||||||| +P41|D<10>|I/O|I/O|BIDIR||||||||| +P42|VCC||VCCINT|||||||||| +P43|D<11>|I/O|I/O|BIDIR||||||||| +P44|D<12>|I/O|I/O|BIDIR||||||||| +P45|D<13>|I/O|I/O|BIDIR||||||||| +P46|D<14>|I/O|I/O|BIDIR||||||||| +P47|GND||GND|||||||||| +P48|D<15>|I/O|I/O|BIDIR||||||||| +P49|A<5>|I|I/O|INPUT||||||||| +P50|A<4>|I|I/O|INPUT||||||||| +P51|A<6>|I|I/O|INPUT||||||||| +P52|A<3>|I|I/O|INPUT||||||||| +P53|TIE||I/O|||||||||| +P54|A<2>|I|I/O|INPUT||||||||| +P55|VCC||VCCIO|||||||||| +P56|TIE||I/O|||||||||| +P57|A<1>|I|I/O|INPUT||||||||| +P58|A<9>|I|I/O|INPUT||||||||| +P59|A<10>|I|I/O|INPUT||||||||| +P60|A<11>|I|I/O|INPUT||||||||| +P61|A<12>|I|I/O|INPUT||||||||| +P62|GND||GND|||||||||| +P63|TDI||TDI|||||||||| +P64|A<13>|I|I/O|INPUT||||||||| +P65|TMS||TMS|||||||||| +P66|TIE||I/O|||||||||| +P67|TCK||TCK|||||||||| +P68|ROM_B<0>|O|I/O|OUTPUT||||||||| +P69|ROM_B<1>|O|I/O|OUTPUT||||||||| +P70|TIE||I/O|||||||||| +P71|TIE||I/O|||||||||| +P72|GND||GND|||||||||| +P73|VCC||VCCIO|||||||||| +P74|TIE||I/O|||||||||| +P75|AUTOBOOT_OFF|I|I/O|INPUT||||||||| +P76|TIE||I/O|||||||||| +P77|TIE||I/O|||||||||| +P78|TIE||I/O|||||||||| +P79|TIE||I/O|||||||||| +P80|AS|I|I/O|INPUT||||||||| +P81|UDS|I|I/O|INPUT||||||||| +P82|TIE||I/O|||||||||| +P83|RW|I|I/O|INPUT||||||||| +P84|VCC||VCCINT|||||||||| +P85|DTACK|O|I/O|OUTPUT||||||||| +P86|A<23>|I|I/O|INPUT||||||||| +P87|A<22>|I|I/O|INPUT||||||||| +P88|A<21>|I|I/O|INPUT||||||||| +P89|GND||GND|||||||||| +P90|GND||GND|||||||||| +P91|A<20>|I|I/O|INPUT||||||||| +P92|A<19>|I|I/O|INPUT||||||||| +P93|TIE||I/O|||||||||| +P94|A<18>|I|I/O|INPUT||||||||| +P95|A<17>|I|I/O|INPUT||||||||| +P96|TIE||I/O|||||||||| +P97|A<16>|I|I/O|INPUT||||||||| +P98|BERR|I|I/O|INPUT||||||||| +P99|GND||GND|||||||||| +P100|TIE||I/O|||||||||| +P101|TIE||I/O|||||||||| +P102|C3|I|I/O|INPUT||||||||| +P103|C1|I|I/O|INPUT||||||||| +P104|TIE||I/O|||||||||| +P105|TIE||I/O|||||||||| +P106|TIE||I/O|||||||||| +P107|TIE||I/O|||||||||| +P108|GND||GND|||||||||| +P109|VCC||VCCIO|||||||||| +P110|TIE||I/O|||||||||| +P111|TIE||I/O|||||||||| +P112|TIE||I/O|||||||||| +P113|TIE||I/O|||||||||| +P114|GND||GND|||||||||| +P115|TIE||I/O|||||||||| +P116|TIE||I/O|||||||||| +P117|TIE||I/O|||||||||| +P118|TIE||I/O|||||||||| +P119|TIE||I/O|||||||||| +P120|TIE||I/O|||||||||| +P121|TIE||I/O|||||||||| +P122|TDO||TDO|||||||||| +P123|GND||GND|||||||||| +P124|TIE||I/O|||||||||| +P125|TIE||I/O|||||||||| +P126|TIE||I/O|||||||||| +P127|VCC||VCCIO|||||||||| +P128|TIE||I/O|||||||||| +P129|TIE||I/O|||||||||| +P130|TIE||I/O|||||||||| +P131|TIE||I/O|||||||||| +P132|TIE||I/O|||||||||| +P133|TIE||I/O|||||||||| +P134|TIE||I/O|||||||||| +P135|TIE||I/O|||||||||| +P136|TIE||I/O|||||||||| +P137|TIE||I/O|||||||||| +P138|TIE||I/O|||||||||| +P139|TIE||I/O|||||||||| +P140|TIE||I/O|||||||||| +P141|VCC||VCCINT|||||||||| +P142|TIE||I/O|||||||||| +P143|RESET|GSR/I|I/O/GSR|||||||||| +P144|GND||GND|||||||||| + +To preserve the pinout above for future design iterations in +Project Navigator simply execute the (Lock Pins) process +located under the (Implement Design) process in a toolbox named +(Optional Implementation Tools) or invoke PIN2UCF from the +command line. The location constraints will be written into your +specified UCF file + + diff --git a/Logic/LAN_IDE/LAN_IDE_CP.pnx b/Logic/LAN_IDE/LAN_IDE_CP.pnx new file mode 100644 index 0000000..08cda4f --- /dev/null +++ b/Logic/LAN_IDE/LAN_IDE_CP.pnx @@ -0,0 +1,18 @@ + + + + + + +]> + diff --git a/Logic/LAN_IDE/LAN_IDE_CP.prj b/Logic/LAN_IDE/LAN_IDE_CP.prj new file mode 100644 index 0000000..3370765 --- /dev/null +++ b/Logic/LAN_IDE/LAN_IDE_CP.prj @@ -0,0 +1 @@ +vhdl work "LAN_IDE_CP.vhd" diff --git a/Logic/LAN_IDE/LAN_IDE_CP.rpt b/Logic/LAN_IDE/LAN_IDE_CP.rpt new file mode 100644 index 0000000..159d140 --- /dev/null +++ b/Logic/LAN_IDE/LAN_IDE_CP.rpt @@ -0,0 +1,1167 @@ + +cpldfit: version P.68d Xilinx Inc. + Fitter Report +Design Name: LAN_IDE_CP Date: 12-15-2016, 7:48PM +Device Used: XC95144XL-10-TQ144 +Fitting Status: Successful + +************************* Mapped Resource Summary ************************** + +Macrocells Product Terms Function Block Registers Pins +Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot +51 /144 ( 35%) 179 /720 ( 25%) 134/432 ( 31%) 26 /144 ( 18%) 54 /117 ( 46%) + +** Function Block Resources ** + +Function Mcells FB Inps Pterms IO +Block Used/Tot Used/Tot Used/Tot Used/Tot +FB1 16/18 24/54 40/90 13/15 +FB2 11/18 24/54 56/90 4/15 +FB3 12/18 24/54 25/90 11/15 +FB4 3/18 24/54 25/90 0/15 +FB5 7/18 23/54 19/90 10/14 +FB6 1/18 15/54 14/90 0/13 +FB7 1/18 0/54 0/90 8/15 +FB8 0/18 0/54 0/90 8/15 + ----- ----- ----- ----- + 51/144 134/432 179/720 54/117 + +* - Resource is exhausted + +** Global Control Resources ** + +Global clock net(s) unused. +Global output enable net(s) unused. +Signal 'RESET' mapped onto global set/reset net GSR. + +** Pin Resources ** + +Signal Type Required Mapped | Pin Type Used Total +------------------------------------|------------------------------------ +Input : 26 26 | I/O : 52 109 +Output : 19 19 | GCK/IO : 0 3 +Bidirectional : 8 8 | GTS/IO : 1 4 +GCK : 0 0 | GSR/IO : 1 1 +GTS : 0 0 | +GSR : 1 1 | + ---- ---- + Total 54 54 + +** Power Data ** + +There are 51 macrocells in high performance mode (MCHP). +There are 0 macrocells in low power mode (MCLP). +End of Mapped Resource Summary + ************************** Errors and Warnings *************************** + +WARNING:Cpld - Unable to retrieve the path to the iSE Project Repository. Will + use the default filename of 'LAN_IDE_CP.ise'. +INFO:Cpld - Inferring BUFG constraint for signal 'CLK_EXT' based upon the LOC + constraint 'P30'. It is recommended that you declare this BUFG explicitedly + in your design. Note that for certain device families the output of a BUFG + constraint can not drive a gated clock, and the BUFG constraint will be + ignored. +WARNING:Cpld:936 - The output buffer 'SLAVE_OBUF' is missing an input and will + be deleted. +WARNING:Cpld:936 - The output buffer 'OWN_OBUF' is missing an input and will be + deleted. +WARNING:Cpld:936 - The output buffer 'OVR_OBUF' is missing an input and will be + deleted. +WARNING:Cpld:936 - The output buffer 'MTACK_OBUF' is missing an input and will + be deleted. +WARNING:Cpld:936 - The output buffer 'LAN_WRH_OBUF' is missing an input and will + be deleted. +WARNING:Cpld:936 - The output buffer 'LAN_RD_OBUF' is missing an input and will + be deleted. +WARNING:Cpld:936 - The output buffer 'LAN_EN_OBUF' is missing an input and will + be deleted. +WARNING:Cpld:936 - The output buffer 'LAN_CS_OBUF' is missing an input and will + be deleted. +WARNING:Cpld:936 - The output buffer 'LAN_CFG<4>_OBUF' is missing an input and + will be deleted. +WARNING:Cpld:936 - The output buffer 'LAN_CFG<3>_OBUF' is missing an input and + will be deleted. +WARNING:Cpld:936 - The output buffer 'LAN_CFG<2>_OBUF' is missing an input and + will be deleted. +WARNING:Cpld:936 - The output buffer 'LAN_CFG<1>_OBUF' is missing an input and + will be deleted. +WARNING:Cpld:936 - The output buffer 'INT_OUT_OBUF' is missing an input and will + be deleted. +WARNING:Cpld:936 - The output buffer 'CP_WE_OBUF' is missing an input and will + be deleted. +WARNING:Cpld:936 - The output buffer 'CP_RD_OBUF' is missing an input and will + be deleted. +WARNING:Cpld:936 - The output buffer 'CP_CS_OBUF' is missing an input and will + be deleted. +WARNING:Cpld:936 - The output buffer 'CFOUT_OBUF' is missing an input and will + be deleted. +WARNING:Cpld:936 - The output buffer 'A_LAN<9>_OBUF' is missing an input and + will be deleted. +WARNING:Cpld:936 - The output buffer 'A_LAN<8>_OBUF' is missing an input and + will be deleted. +WARNING:Cpld:936 - The output buffer 'A_LAN<7>_OBUF' is missing an input and + will be deleted. +WARNING:Cpld:936 - The output buffer 'A_LAN<6>_OBUF' is missing an input and + will be deleted. +WARNING:Cpld:936 - The output buffer 'A_LAN<5>_OBUF' is missing an input and + will be deleted. +WARNING:Cpld:936 - The output buffer 'A_LAN<4>_OBUF' is missing an input and + will be deleted. +WARNING:Cpld:936 - The output buffer 'A_LAN<3>_OBUF' is missing an input and + will be deleted. +WARNING:Cpld:936 - The output buffer 'A_LAN<2>_OBUF' is missing an input and + will be deleted. +WARNING:Cpld:936 - The output buffer 'A_LAN<1>_OBUF' is missing an input and + will be deleted. +WARNING:Cpld:936 - The output buffer 'A_LAN<13>_OBUF' is missing an input and + will be deleted. +WARNING:Cpld:936 - The output buffer 'A_LAN<12>_OBUF' is missing an input and + will be deleted. +WARNING:Cpld:936 - The output buffer 'A_LAN<11>_OBUF' is missing an input and + will be deleted. +WARNING:Cpld:936 - The output buffer 'A_LAN<10>_OBUF' is missing an input and + will be deleted. +WARNING:Cpld:936 - The output buffer 'A_LAN<0>_OBUF' is missing an input and + will be deleted. +WARNING:Cpld:1007 - Removing unused input(s) 'A<14>'. The input(s) are unused + after optimization. Please verify functionality via simulation. +WARNING:Cpld:1007 - Removing unused input(s) 'A<15>'. The input(s) are unused + after optimization. Please verify functionality via simulation. +WARNING:Cpld:1007 - Removing unused input(s) 'A<7>'. The input(s) are unused + after optimization. Please verify functionality via simulation. +WARNING:Cpld:1007 - Removing unused input(s) 'A<8>'. The input(s) are unused + after optimization. Please verify functionality via simulation. +WARNING:Cpld:1007 - Removing unused input(s) 'CFIN'. The input(s) are unused + after optimization. Please verify functionality via simulation. +WARNING:Cpld:1007 - Removing unused input(s) 'CLK_EXT'. The input(s) are unused + after optimization. Please verify functionality via simulation. +WARNING:Cpld:1007 - Removing unused input(s) 'CP_IRQ'. The input(s) are unused + after optimization. Please verify functionality via simulation. +WARNING:Cpld:1007 - Removing unused input(s) 'DQ<0>'. The input(s) are unused + after optimization. Please verify functionality via simulation. +WARNING:Cpld:1007 - Removing unused input(s) 'DQ<10>'. The input(s) are unused + after optimization. Please verify functionality via simulation. +WARNING:Cpld:1007 - Removing unused input(s) 'DQ<11>'. The input(s) are unused + after optimization. Please verify functionality via simulation. +WARNING:Cpld:1007 - Removing unused input(s) 'DQ<12>'. The input(s) are unused + after optimization. Please verify functionality via simulation. +WARNING:Cpld:1007 - Removing unused input(s) 'DQ<13>'. The input(s) are unused + after optimization. Please verify functionality via simulation. +WARNING:Cpld:1007 - Removing unused input(s) 'DQ<14>'. The input(s) are unused + after optimization. Please verify functionality via simulation. +WARNING:Cpld:1007 - Removing unused input(s) 'DQ<15>'. The input(s) are unused + after optimization. Please verify functionality via simulation. +WARNING:Cpld:1007 - Removing unused input(s) 'DQ<1>'. The input(s) are unused + after optimization. Please verify functionality via simulation. +WARNING:Cpld:1007 - Removing unused input(s) 'DQ<2>'. The input(s) are unused + after optimization. Please verify functionality via simulation. +WARNING:Cpld:1007 - Removing unused input(s) 'DQ<3>'. The input(s) are unused + after optimization. Please verify functionality via simulation. +WARNING:Cpld:1007 - Removing unused input(s) 'DQ<4>'. The input(s) are unused + after optimization. Please verify functionality via simulation. +WARNING:Cpld:1007 - Removing unused input(s) 'DQ<5>'. The input(s) are unused + after optimization. Please verify functionality via simulation. +WARNING:Cpld:1007 - Removing unused input(s) 'DQ<6>'. The input(s) are unused + after optimization. Please verify functionality via simulation. +WARNING:Cpld:1007 - Removing unused input(s) 'DQ<7>'. The input(s) are unused + after optimization. Please verify functionality via simulation. +WARNING:Cpld:1007 - Removing unused input(s) 'DQ<8>'. The input(s) are unused + after optimization. Please verify functionality via simulation. +WARNING:Cpld:1007 - Removing unused input(s) 'DQ<9>'. The input(s) are unused + after optimization. Please verify functionality via simulation. +WARNING:Cpld:1007 - Removing unused input(s) 'DS0'. The input(s) are unused + after optimization. Please verify functionality via simulation. +WARNING:Cpld:1007 - Removing unused input(s) 'DS1'. The input(s) are unused + after optimization. Please verify functionality via simulation. +WARNING:Cpld:1007 - Removing unused input(s) 'FCS'. The input(s) are unused + after optimization. Please verify functionality via simulation. +WARNING:Cpld:1007 - Removing unused input(s) 'IDE_WAIT'. The input(s) are + unused after optimization. Please verify functionality via simulation. +WARNING:Cpld:1007 - Removing unused input(s) 'LAN_INT'. The input(s) are unused + after optimization. Please verify functionality via simulation. +WARNING:Cpld:1007 - Removing unused input(s) 'LDS'. The input(s) are unused + after optimization. Please verify functionality via simulation. +WARNING:Cpld:1007 - Removing unused input(s) 'MTCR'. The input(s) are unused + after optimization. Please verify functionality via simulation. +WARNING:Cpld:1007 - Removing unused input(s) 'Z3'. The input(s) are unused + after optimization. Please verify functionality via simulation. +WARNING:Cpld:896 - Unable to map all desired signals into function block, FB3, + because too many function block product terms are required. Buffering output + signal D<12> to allow all signals assigned to this function block to be + placed. +WARNING:Cpld:896 - Unable to map all desired signals into function block, FB3, + because too many function block product terms are required. Buffering output + signal D<14> to allow all signals assigned to this function block to be + placed. +WARNING:Cpld:896 - Unable to map all desired signals into function block, FB3, + because too many function block product terms are required. Buffering output + signal D<13> to allow all signals assigned to this function block to be + placed. +WARNING:Cpld:896 - Unable to map all desired signals into function block, FB3, + because too many function block product terms are required. Buffering output + signal D<15> to allow all signals assigned to this function block to be + placed. + ************************* Summary of Mapped Logic ************************ + +** 27 Outputs ** + +Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init +Name Pts Inps No. Type Use Mode Rate State +IDE_CS<1> 1 1 FB1_1 23 I/O O STD FAST +D<7> 1 2 FB1_2 16 I/O O STD FAST +D<1> 1 2 FB1_3 17 I/O O STD FAST +IDE_A<2> 1 1 FB1_4 25 I/O O STD FAST +D<8> 1 2 FB1_5 19 I/O I/O STD FAST +D<5> 1 2 FB1_6 20 I/O O STD FAST +D<4> 1 2 FB1_8 21 I/O O STD FAST +IDE_CS<0> 1 1 FB1_9 22 I/O O STD FAST +IDE_A<0> 1 1 FB1_11 24 I/O O STD FAST +IDE_A<1> 1 1 FB1_12 26 I/O O STD FAST +IDE_R 2 6 FB1_14 27 I/O O STD FAST SET +IDE_W 2 5 FB1_15 28 I/O O STD FAST SET +ROM_OE 2 6 FB1_16 35 I/O O STD FAST SET +D<0> 1 2 FB2_5 2 GTS/I/O O STD FAST +D<6> 1 2 FB2_16 14 I/O O STD FAST +D<3> 1 2 FB2_17 15 I/O O STD FAST +D<2> 1 2 FB3_1 39 I/O O STD FAST +D<10> 1 2 FB3_3 41 I/O I/O STD FAST +D<12> 2 3 FB3_4 44 I/O I/O STD FAST +D<14> 2 3 FB3_7 46 I/O I/O STD FAST +D<9> 1 2 FB3_9 40 I/O I/O STD FAST +D<15> 2 3 FB3_10 48 I/O I/O STD FAST +D<11> 1 2 FB3_11 43 I/O I/O STD FAST +D<13> 2 3 FB3_12 45 I/O I/O STD FAST +ROM_B<0> 0 0 FB5_10 68 I/O O STD FAST +ROM_B<1> 0 0 FB5_17 69 I/O O STD FAST +DTACK 0 0 FB7_12 85 I/O O STD FAST + +** 24 Buried Nodes ** + +Signal Total Total Loc Pwr Reg Init +Name Pts Inps Mode State +AUTOCONFIG_IN_PROGRESS 2 3 FB1_7 STD RESET +IDE_ENABLE 3 6 FB1_10 STD RESET +D<12>_BUFR 19 16 FB1_18 STD RESET +D<14>_BUFR 18 15 FB2_1 STD RESET +AUTO_CONFIG_DONE<2> 2 2 FB2_8 STD RESET +AUTO_CONFIG_DONE<0> 2 2 FB2_9 STD RESET +AUTO_CONFIG_DONE_CYCLE<2> 3 15 FB2_10 STD RESET +AUTO_CONFIG_DONE_CYCLE<0> 3 13 FB2_11 STD RESET +IDE_BASEADR<7> 4 16 FB2_12 STD RESET +IDE_BASEADR<6> 4 16 FB2_13 STD RESET +D<13>_BUFR 17 15 FB2_15 STD RESET +AUTO_CONFIG_DONE<1> 2 2 FB3_15 STD RESET +AUTO_CONFIG_DONE_CYCLE<1> 3 14 FB3_16 STD RESET +IDE_BASEADR<3> 4 16 FB3_17 STD RESET +IDE_BASEADR<2> 4 16 FB3_18 STD RESET +ide 19 19 FB4_1 STD RESET +ide/ide_CLKF 2 2 FB4_16 STD +autoconfig 4 13 FB4_17 STD RESET +SHUT_UP<1> 3 15 FB5_13 STD RESET +IDE_BASEADR<5> 4 16 FB5_14 STD RESET +IDE_BASEADR<4> 4 16 FB5_15 STD RESET +IDE_BASEADR<1> 4 16 FB5_16 STD RESET +IDE_BASEADR<0> 4 16 FB5_18 STD RESET +D<15>_BUFR 14 15 FB6_17 STD RESET + +** 27 Inputs ** + +Signal Loc Pin Pin Pin +Name No. Type Use +RESET FB2_2 143 GSR/I/O GSR/I +A<5> FB3_14 49 I/O I +A<4> FB3_15 50 I/O I +A<6> FB3_17 51 I/O I +A<3> FB5_2 52 I/O I +A<10> FB5_3 59 I/O I +A<2> FB5_6 54 I/O I +A<1> FB5_9 57 I/O I +A<9> FB5_11 58 I/O I +A<11> FB5_12 60 I/O I +A<12> FB5_14 61 I/O I +A<13> FB5_15 64 I/O I +AUTOBOOT_OFF FB7_3 75 I/O I +AS FB7_9 80 I/O I +UDS FB7_13 81 I/O I +A<23> FB7_14 86 I/O I +A<22> FB7_15 87 I/O I +RW FB7_16 83 I/O I +A<21> FB7_17 88 I/O I +A<20> FB8_2 91 I/O I +A<17> FB8_3 95 I/O I +A<16> FB8_4 97 I/O I +A<19> FB8_5 92 I/O I +A<18> FB8_8 94 I/O I +BERR FB8_11 98 I/O I +C1 FB8_13 103 I/O I +C3 FB8_14 102 I/O I + +Legend: +Pin No. - ~ - User Assigned + ************************** Function Block Details ************************ +Legend: +Total Pt - Total product terms used by the macrocell signal +Imp Pt - Product terms imported from other macrocells +Exp Pt - Product terms exported to other macrocells + in direction shown +Unused Pt - Unused local product terms remaining in macrocell +Loc - Location where logic was mapped in device +Pin Type/Use - I - Input GCK - Global Clock + O - Output GTS - Global Output Enable + (b) - Buried macrocell GSR - Global Set/Reset +X - Signal used as input to the macrocell logic. +Pin No. - ~ - User Assigned + *********************************** FB1 *********************************** +Number of function block inputs used/remaining: 24/30 +Number of signals used by logic mapping into function block: 24 +Signal Total Imp Exp Unused Loc Pin Pin Pin +Name Pt Pt Pt Pt # Type Use +IDE_CS<1> 1 1<- /\5 0 FB1_1 23 I/O O +D<7> 1 0 /\1 3 FB1_2 16 I/O O +D<1> 1 0 0 4 FB1_3 17 I/O O +IDE_A<2> 1 0 0 4 FB1_4 25 I/O O +D<8> 1 0 0 4 FB1_5 19 I/O I/O +D<5> 1 0 0 4 FB1_6 20 I/O O +AUTOCONFIG_IN_PROGRESS + 2 0 0 3 FB1_7 (b) (b) +D<4> 1 0 0 4 FB1_8 21 I/O O +IDE_CS<0> 1 0 0 4 FB1_9 22 I/O O +IDE_ENABLE 3 0 0 2 FB1_10 31 I/O (b) +IDE_A<0> 1 0 0 4 FB1_11 24 I/O O +IDE_A<1> 1 0 0 4 FB1_12 26 I/O O +(unused) 0 0 0 5 FB1_13 (b) +IDE_R 2 0 0 3 FB1_14 27 I/O O +IDE_W 2 0 \/1 2 FB1_15 28 I/O O +ROM_OE 2 1<- \/4 0 FB1_16 35 I/O O +(unused) 0 0 \/5 0 FB1_17 30 GCK/I/O (b) +D<12>_BUFR 19 14<- 0 0 FB1_18 (b) (b) + +Signals Used by Logic in Function Block + 1: AS 9: A<1> 17: A<10> + 2: AUTOBOOT_OFF 10: A<2> 18: A<11> + 3: AUTOCONFIG_IN_PROGRESS 11: A<3> 19: IDE_ENABLE + 4: AUTO_CONFIG_DONE<0> 12: A<4> 20: RESET + 5: AUTO_CONFIG_DONE<1> 13: A<5> 21: RW + 6: AUTO_CONFIG_DONE<2> 14: A<6> 22: autoconfig + 7: A<12> 15: D<12> 23: ide + 8: A<13> 16: A<9> 24: ide/ide_CLKF + +Signal 1 2 3 4 FB +Name 0----+----0----+----0----+----0----+----0 Inputs +IDE_CS<1> .......X................................ 1 +D<7> ..X.................X................... 2 +D<1> ..X.................X................... 2 +IDE_A<2> .................X...................... 1 +D<8> ..X.................X................... 2 +D<5> ..X.................X................... 2 +AUTOCONFIG_IN_PROGRESS + X....................X.X................ 3 +D<4> ..X.................X................... 2 +IDE_CS<0> ......X................................. 1 +IDE_ENABLE X.................XXX.XX................ 6 +IDE_A<0> ...............X........................ 1 +IDE_A<1> ................X....................... 1 +IDE_R X.................XXX.XX................ 6 +IDE_W X..................XX.XX................ 5 +ROM_OE X.................XXX.XX................ 6 +D<12>_BUFR XX.XXX..XXXXXXX....XXX.X................ 16 + 0----+----1----+----2----+----3----+----4 + 0 0 0 0 + *********************************** FB2 *********************************** +Number of function block inputs used/remaining: 24/30 +Number of signals used by logic mapping into function block: 24 +Signal Total Imp Exp Unused Loc Pin Pin Pin +Name Pt Pt Pt Pt # Type Use +D<14>_BUFR 18 13<- 0 0 FB2_1 142 I/O (b) +(unused) 0 0 /\5 0 FB2_2 143 GSR/I/O GSR/I +(unused) 0 0 /\3 2 FB2_3 (b) (b) +(unused) 0 0 0 5 FB2_4 4 I/O +D<0> 1 0 0 4 FB2_5 2 GTS/I/O O +(unused) 0 0 0 5 FB2_6 3 GTS/I/O +(unused) 0 0 0 5 FB2_7 (b) +AUTO_CONFIG_DONE<2> 2 0 0 3 FB2_8 5 GTS/I/O (b) +AUTO_CONFIG_DONE<0> 2 0 0 3 FB2_9 6 GTS/I/O (b) +AUTO_CONFIG_DONE_CYCLE<2> + 3 0 0 2 FB2_10 7 I/O (b) +AUTO_CONFIG_DONE_CYCLE<0> + 3 0 \/1 1 FB2_11 9 I/O (b) +IDE_BASEADR<7> 4 1<- \/2 0 FB2_12 10 I/O (b) +IDE_BASEADR<6> 4 2<- \/3 0 FB2_13 12 I/O (b) +(unused) 0 0 \/5 0 FB2_14 11 I/O (b) +D<13>_BUFR 17 12<- 0 0 FB2_15 13 I/O (b) +D<6> 1 0 /\4 0 FB2_16 14 I/O O +D<3> 1 0 0 4 FB2_17 15 I/O O +(unused) 0 0 \/5 0 FB2_18 (b) (b) + +Signals Used by Logic in Function Block + 1: AS 9: A<2> 17: IDE_BASEADR<7> + 2: AUTOCONFIG_IN_PROGRESS 10: A<3> 18: D<14>.PIN + 3: AUTO_CONFIG_DONE<0> 11: A<4> 19: D<15>.PIN + 4: AUTO_CONFIG_DONE<1> 12: A<5> 20: RESET + 5: AUTO_CONFIG_DONE<2> 13: A<6> 21: RW + 6: AUTO_CONFIG_DONE_CYCLE<0> 14: D<13> 22: UDS + 7: AUTO_CONFIG_DONE_CYCLE<2> 15: D<14> 23: autoconfig + 8: A<1> 16: IDE_BASEADR<6> 24: ide/ide_CLKF + +Signal 1 2 3 4 FB +Name 0----+----0----+----0----+----0----+----0 Inputs +D<14>_BUFR X.XXX..XXXXXX.X....XX.XX................ 15 +D<0> .X..................X................... 2 +AUTO_CONFIG_DONE<2> X.....X................................. 2 +AUTO_CONFIG_DONE<0> X....X.................................. 2 +AUTO_CONFIG_DONE_CYCLE<2> + X.XXX.XX.XXXX......XXXXX................ 15 +AUTO_CONFIG_DONE_CYCLE<0> + X.X..X.X.XXXX......XXXXX................ 13 +IDE_BASEADR<7> X.XX...XXXXXX...X.XXXXXX................ 16 +IDE_BASEADR<6> X.XX...XXXXXX..X.X.XXXXX................ 16 +D<13>_BUFR X.XXX..XXXXXXX.....XX.XX................ 15 +D<6> .X..................X................... 2 +D<3> .X..................X................... 2 + 0----+----1----+----2----+----3----+----4 + 0 0 0 0 + *********************************** FB3 *********************************** +Number of function block inputs used/remaining: 24/30 +Number of signals used by logic mapping into function block: 24 +Signal Total Imp Exp Unused Loc Pin Pin Pin +Name Pt Pt Pt Pt # Type Use +D<2> 1 0 0 4 FB3_1 39 I/O O +(unused) 0 0 0 5 FB3_2 32 GCK/I/O +D<10> 1 0 0 4 FB3_3 41 I/O I/O +D<12> 2 0 0 3 FB3_4 44 I/O I/O +(unused) 0 0 0 5 FB3_5 33 I/O +(unused) 0 0 0 5 FB3_6 34 I/O +D<14> 2 0 0 3 FB3_7 46 I/O I/O +(unused) 0 0 0 5 FB3_8 38 GCK/I/O +D<9> 1 0 0 4 FB3_9 40 I/O I/O +D<15> 2 0 0 3 FB3_10 48 I/O I/O +D<11> 1 0 0 4 FB3_11 43 I/O I/O +D<13> 2 0 0 3 FB3_12 45 I/O I/O +(unused) 0 0 0 5 FB3_13 (b) +(unused) 0 0 0 5 FB3_14 49 I/O I +AUTO_CONFIG_DONE<1> 2 0 0 3 FB3_15 50 I/O I +AUTO_CONFIG_DONE_CYCLE<1> + 3 0 0 2 FB3_16 (b) (b) +IDE_BASEADR<3> 4 0 0 1 FB3_17 51 I/O I +IDE_BASEADR<2> 4 0 0 1 FB3_18 (b) (b) + +Signals Used by Logic in Function Block + 1: AS 9: A<4> 17: IDE_BASEADR<3> + 2: AUTOCONFIG_IN_PROGRESS 10: A<5> 18: D<11>.PIN + 3: AUTO_CONFIG_DONE<0> 11: A<6> 19: D<10>.PIN + 4: AUTO_CONFIG_DONE<1> 12: D<12>_BUFR 20: RESET + 5: AUTO_CONFIG_DONE_CYCLE<1> 13: D<13>_BUFR 21: RW + 6: A<1> 14: D<14>_BUFR 22: UDS + 7: A<2> 15: D<15>_BUFR 23: autoconfig + 8: A<3> 16: IDE_BASEADR<2> 24: ide/ide_CLKF + +Signal 1 2 3 4 FB +Name 0----+----0----+----0----+----0----+----0 Inputs +D<2> .X..................X................... 2 +D<10> .X..................X................... 2 +D<12> .X.........X........X................... 3 +D<14> .X...........X......X................... 3 +D<9> .X..................X................... 2 +D<15> .X............X.....X................... 3 +D<11> .X..................X................... 2 +D<13> .X..........X.......X................... 3 +AUTO_CONFIG_DONE<1> X...X................................... 2 +AUTO_CONFIG_DONE_CYCLE<1> + X.XXXX.XXXX........XXXXX................ 14 +IDE_BASEADR<3> X.XX.XXXXXX.....XX.XXXXX................ 16 +IDE_BASEADR<2> X.XX.XXXXXX....X..XXXXXX................ 16 + 0----+----1----+----2----+----3----+----4 + 0 0 0 0 + *********************************** FB4 *********************************** +Number of function block inputs used/remaining: 24/30 +Number of signals used by logic mapping into function block: 24 +Signal Total Imp Exp Unused Loc Pin Pin Pin +Name Pt Pt Pt Pt # Type Use +ide 19 14<- 0 0 FB4_1 118 I/O (b) +(unused) 0 0 /\5 0 FB4_2 126 I/O (b) +(unused) 0 0 /\3 2 FB4_3 133 I/O (b) +(unused) 0 0 0 5 FB4_4 (b) +(unused) 0 0 0 5 FB4_5 128 I/O +(unused) 0 0 0 5 FB4_6 129 I/O +(unused) 0 0 0 5 FB4_7 (b) +(unused) 0 0 0 5 FB4_8 130 I/O +(unused) 0 0 0 5 FB4_9 131 I/O +(unused) 0 0 0 5 FB4_10 135 I/O +(unused) 0 0 0 5 FB4_11 132 I/O +(unused) 0 0 0 5 FB4_12 134 I/O +(unused) 0 0 0 5 FB4_13 137 I/O +(unused) 0 0 0 5 FB4_14 136 I/O +(unused) 0 0 0 5 FB4_15 138 I/O +ide/ide_CLKF 2 0 0 3 FB4_16 139 I/O (b) +autoconfig 4 0 \/1 0 FB4_17 140 I/O (b) +(unused) 0 0 \/5 0 FB4_18 (b) (b) + +Signals Used by Logic in Function Block + 1: AUTO_CONFIG_DONE<0> 9: A<21> 17: IDE_BASEADR<2> + 2: AUTO_CONFIG_DONE<1> 10: A<22> 18: IDE_BASEADR<3> + 3: AUTO_CONFIG_DONE<2> 11: A<23> 19: IDE_BASEADR<4> + 4: A<16> 12: BERR 20: IDE_BASEADR<5> + 5: A<17> 13: C1 21: IDE_BASEADR<6> + 6: A<18> 14: C3 22: IDE_BASEADR<7> + 7: A<19> 15: IDE_BASEADR<0> 23: SHUT_UP<1> + 8: A<20> 16: IDE_BASEADR<1> 24: ide/ide_CLKF + +Signal 1 2 3 4 FB +Name 0----+----0----+----0----+----0----+----0 Inputs +ide ...XXXXXXXXX..XXXXXXXXXX................ 19 +ide/ide_CLKF ............XX.......................... 2 +autoconfig XXXXXXXXXXXX...........X................ 13 + 0----+----1----+----2----+----3----+----4 + 0 0 0 0 + *********************************** FB5 *********************************** +Number of function block inputs used/remaining: 23/31 +Number of signals used by logic mapping into function block: 23 +Signal Total Imp Exp Unused Loc Pin Pin Pin +Name Pt Pt Pt Pt # Type Use +(unused) 0 0 0 5 FB5_1 (b) +(unused) 0 0 0 5 FB5_2 52 I/O I +(unused) 0 0 0 5 FB5_3 59 I/O I +(unused) 0 0 0 5 FB5_4 (b) +(unused) 0 0 0 5 FB5_5 53 I/O +(unused) 0 0 0 5 FB5_6 54 I/O I +(unused) 0 0 0 5 FB5_7 66 I/O +(unused) 0 0 0 5 FB5_8 56 I/O +(unused) 0 0 0 5 FB5_9 57 I/O I +ROM_B<0> 0 0 0 5 FB5_10 68 I/O O +(unused) 0 0 0 5 FB5_11 58 I/O I +(unused) 0 0 0 5 FB5_12 60 I/O I +SHUT_UP<1> 3 0 0 2 FB5_13 70 I/O (b) +IDE_BASEADR<5> 4 0 0 1 FB5_14 61 I/O I +IDE_BASEADR<4> 4 0 0 1 FB5_15 64 I/O I +IDE_BASEADR<1> 4 0 0 1 FB5_16 (b) (b) +ROM_B<1> 0 0 0 5 FB5_17 69 I/O O +IDE_BASEADR<0> 4 0 0 1 FB5_18 (b) (b) + +Signals Used by Logic in Function Block + 1: AS 9: A<6> 17: D<9>.PIN + 2: AUTO_CONFIG_DONE<0> 10: IDE_BASEADR<0> 18: RESET + 3: AUTO_CONFIG_DONE<1> 11: IDE_BASEADR<1> 19: RW + 4: A<1> 12: IDE_BASEADR<4> 20: SHUT_UP<1> + 5: A<2> 13: IDE_BASEADR<5> 21: UDS + 6: A<3> 14: D<12>.PIN 22: autoconfig + 7: A<4> 15: D<13>.PIN 23: ide/ide_CLKF + 8: A<5> 16: D<8>.PIN + +Signal 1 2 3 4 FB +Name 0----+----0----+----0----+----0----+----0 Inputs +ROM_B<0> ........................................ 0 +SHUT_UP<1> XXXXXXXXX........XXXXXX................. 15 +IDE_BASEADR<5> XXXXXXXXX...X.X..XX.XXX................. 16 +IDE_BASEADR<4> XXXXXXXXX..X.X...XX.XXX................. 16 +IDE_BASEADR<1> XXXXXXXXX.X.....XXX.XXX................. 16 +ROM_B<1> ........................................ 0 +IDE_BASEADR<0> XXXXXXXXXX.....X.XX.XXX................. 16 + 0----+----1----+----2----+----3----+----4 + 0 0 0 0 + *********************************** FB6 *********************************** +Number of function block inputs used/remaining: 15/39 +Number of signals used by logic mapping into function block: 15 +Signal Total Imp Exp Unused Loc Pin Pin Pin +Name Pt Pt Pt Pt # Type Use +(unused) 0 0 0 5 FB6_1 (b) +(unused) 0 0 0 5 FB6_2 106 I/O +(unused) 0 0 0 5 FB6_3 (b) +(unused) 0 0 0 5 FB6_4 111 I/O +(unused) 0 0 0 5 FB6_5 110 I/O +(unused) 0 0 0 5 FB6_6 112 I/O +(unused) 0 0 0 5 FB6_7 (b) +(unused) 0 0 0 5 FB6_8 113 I/O +(unused) 0 0 0 5 FB6_9 116 I/O +(unused) 0 0 0 5 FB6_10 115 I/O +(unused) 0 0 0 5 FB6_11 119 I/O +(unused) 0 0 0 5 FB6_12 120 I/O +(unused) 0 0 0 5 FB6_13 (b) +(unused) 0 0 0 5 FB6_14 121 I/O +(unused) 0 0 0 5 FB6_15 124 I/O +(unused) 0 0 \/4 1 FB6_16 117 I/O (b) +D<15>_BUFR 14 9<- 0 0 FB6_17 125 I/O (b) +(unused) 0 0 /\5 0 FB6_18 (b) (b) + +Signals Used by Logic in Function Block + 1: AS 6: A<2> 11: D<15> + 2: AUTO_CONFIG_DONE<0> 7: A<3> 12: RESET + 3: AUTO_CONFIG_DONE<1> 8: A<4> 13: RW + 4: AUTO_CONFIG_DONE<2> 9: A<5> 14: autoconfig + 5: A<1> 10: A<6> 15: ide/ide_CLKF + +Signal 1 2 3 4 FB +Name 0----+----0----+----0----+----0----+----0 Inputs +D<15>_BUFR XXXXXXXXXXXXXXX......................... 15 + 0----+----1----+----2----+----3----+----4 + 0 0 0 0 + *********************************** FB7 *********************************** +Number of function block inputs used/remaining: 0/54 +Number of signals used by logic mapping into function block: 0 +Signal Total Imp Exp Unused Loc Pin Pin Pin +Name Pt Pt Pt Pt # Type Use +(unused) 0 0 0 5 FB7_1 (b) +(unused) 0 0 0 5 FB7_2 71 I/O +(unused) 0 0 0 5 FB7_3 75 I/O I +(unused) 0 0 0 5 FB7_4 (b) +(unused) 0 0 0 5 FB7_5 74 I/O +(unused) 0 0 0 5 FB7_6 76 I/O +(unused) 0 0 0 5 FB7_7 77 I/O +(unused) 0 0 0 5 FB7_8 78 I/O +(unused) 0 0 0 5 FB7_9 80 I/O I +(unused) 0 0 0 5 FB7_10 79 I/O +(unused) 0 0 0 5 FB7_11 82 I/O +DTACK 0 0 0 5 FB7_12 85 I/O O +(unused) 0 0 0 5 FB7_13 81 I/O I +(unused) 0 0 0 5 FB7_14 86 I/O I +(unused) 0 0 0 5 FB7_15 87 I/O I +(unused) 0 0 0 5 FB7_16 83 I/O I +(unused) 0 0 0 5 FB7_17 88 I/O I +(unused) 0 0 0 5 FB7_18 (b) + +Signals Used by Logic in Function Block + +Signal 1 2 3 4 FB +Name 0----+----0----+----0----+----0----+----0 Inputs +DTACK ........................................ 0 + 0----+----1----+----2----+----3----+----4 + 0 0 0 0 + *********************************** FB8 *********************************** +Number of function block inputs used/remaining: 0/54 +Number of signals used by logic mapping into function block: 0 +Signal Total Imp Exp Unused Loc Pin Pin Pin +Name Pt Pt Pt Pt # Type Use +(unused) 0 0 0 5 FB8_1 (b) +(unused) 0 0 0 5 FB8_2 91 I/O I +(unused) 0 0 0 5 FB8_3 95 I/O I +(unused) 0 0 0 5 FB8_4 97 I/O I +(unused) 0 0 0 5 FB8_5 92 I/O I +(unused) 0 0 0 5 FB8_6 93 I/O +(unused) 0 0 0 5 FB8_7 (b) +(unused) 0 0 0 5 FB8_8 94 I/O I +(unused) 0 0 0 5 FB8_9 96 I/O +(unused) 0 0 0 5 FB8_10 101 I/O +(unused) 0 0 0 5 FB8_11 98 I/O I +(unused) 0 0 0 5 FB8_12 100 I/O +(unused) 0 0 0 5 FB8_13 103 I/O I +(unused) 0 0 0 5 FB8_14 102 I/O I +(unused) 0 0 0 5 FB8_15 104 I/O +(unused) 0 0 0 5 FB8_16 107 I/O +(unused) 0 0 0 5 FB8_17 105 I/O +(unused) 0 0 0 5 FB8_18 (b) + ******************************* Equations ******************************** + +********** Mapped Logic ********** + +FDCPE_AUTOCONFIG_IN_PROGRESS: FDCPE port map (AUTOCONFIG_IN_PROGRESS,AUTOCONFIG_IN_PROGRESS_D,ide/ide_CLKF,'0','0'); +AUTOCONFIG_IN_PROGRESS_D <= (NOT AS AND autoconfig); + +FDCPE_AUTO_CONFIG_DONE0: FDCPE port map (AUTO_CONFIG_DONE(0),AUTO_CONFIG_DONE_CYCLE(0),AS,NOT RESET,'0'); + +FDCPE_AUTO_CONFIG_DONE1: FDCPE port map (AUTO_CONFIG_DONE(1),AUTO_CONFIG_DONE_CYCLE(1),AS,NOT RESET,'0'); + +FDCPE_AUTO_CONFIG_DONE2: FDCPE port map (AUTO_CONFIG_DONE(2),AUTO_CONFIG_DONE_CYCLE(2),AS,NOT RESET,'0'); + +FDCPE_AUTO_CONFIG_DONE_CYCLE0: FDCPE port map (AUTO_CONFIG_DONE_CYCLE(0),AUTO_CONFIG_DONE_CYCLE_D(0),ide/ide_CLKF,'0','0'); +AUTO_CONFIG_DONE_CYCLE_D(0) <= ((RESET AND AUTO_CONFIG_DONE_CYCLE(0)) + OR (RESET AND NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND + A(6) AND A(3) AND NOT AUTO_CONFIG_DONE(0) AND autoconfig)); + +FDCPE_AUTO_CONFIG_DONE_CYCLE1: FDCPE port map (AUTO_CONFIG_DONE_CYCLE(1),AUTO_CONFIG_DONE_CYCLE_D(1),ide/ide_CLKF,'0','0'); +AUTO_CONFIG_DONE_CYCLE_D(1) <= ((RESET AND AUTO_CONFIG_DONE_CYCLE(1)) + OR (RESET AND NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND + A(6) AND A(3) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND + autoconfig)); + +FDCPE_AUTO_CONFIG_DONE_CYCLE2: FDCPE port map (AUTO_CONFIG_DONE_CYCLE(2),AUTO_CONFIG_DONE_CYCLE_D(2),ide/ide_CLKF,'0','0'); +AUTO_CONFIG_DONE_CYCLE_D(2) <= ((RESET AND AUTO_CONFIG_DONE_CYCLE(2)) + OR (RESET AND NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND + A(6) AND A(3) AND AUTO_CONFIG_DONE(0) AND AUTO_CONFIG_DONE(1) AND + NOT AUTO_CONFIG_DONE(2) AND autoconfig)); + + +D_I(0) <= '1'; +D(0) <= D_I(0) when D_OE(0) = '1' else 'Z'; +D_OE(0) <= (RW AND AUTOCONFIG_IN_PROGRESS); + + +D_I(1) <= '1'; +D(1) <= D_I(1) when D_OE(1) = '1' else 'Z'; +D_OE(1) <= (RW AND AUTOCONFIG_IN_PROGRESS); + + +D_I(2) <= '1'; +D(2) <= D_I(2) when D_OE(2) = '1' else 'Z'; +D_OE(2) <= (RW AND AUTOCONFIG_IN_PROGRESS); + + +D_I(3) <= '1'; +D(3) <= D_I(3) when D_OE(3) = '1' else 'Z'; +D_OE(3) <= (RW AND AUTOCONFIG_IN_PROGRESS); + + +D_I(4) <= '1'; +D(4) <= D_I(4) when D_OE(4) = '1' else 'Z'; +D_OE(4) <= (RW AND AUTOCONFIG_IN_PROGRESS); + + +D_I(5) <= '1'; +D(5) <= D_I(5) when D_OE(5) = '1' else 'Z'; +D_OE(5) <= (RW AND AUTOCONFIG_IN_PROGRESS); + + +D_I(6) <= '1'; +D(6) <= D_I(6) when D_OE(6) = '1' else 'Z'; +D_OE(6) <= (RW AND AUTOCONFIG_IN_PROGRESS); + + +D_I(7) <= '1'; +D(7) <= D_I(7) when D_OE(7) = '1' else 'Z'; +D_OE(7) <= (RW AND AUTOCONFIG_IN_PROGRESS); + + +D_I(8) <= '1'; +D(8) <= D_I(8) when D_OE(8) = '1' else 'Z'; +D_OE(8) <= (RW AND AUTOCONFIG_IN_PROGRESS); + + +D_I(9) <= '1'; +D(9) <= D_I(9) when D_OE(9) = '1' else 'Z'; +D_OE(9) <= (RW AND AUTOCONFIG_IN_PROGRESS); + + +D_I(10) <= '1'; +D(10) <= D_I(10) when D_OE(10) = '1' else 'Z'; +D_OE(10) <= (RW AND AUTOCONFIG_IN_PROGRESS); + + +D_I(11) <= '1'; +D(11) <= D_I(11) when D_OE(11) = '1' else 'Z'; +D_OE(11) <= (RW AND AUTOCONFIG_IN_PROGRESS); + +FDCPE_D12_BUFR: FDCPE port map (D(12)_BUFR,D_D(12)_BUFR,ide/ide_CLKF,'0','0'); +D_D(12)_BUFR <= ((RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND A(6) AND NOT A(3) AND + NOT A(2) AND NOT AUTO_CONFIG_DONE(0) AND autoconfig) + OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND A(6) AND NOT A(3) AND + NOT A(2) AND NOT AUTO_CONFIG_DONE(1) AND autoconfig) + OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND A(6) AND NOT A(3) AND + NOT A(2) AND NOT AUTO_CONFIG_DONE(2) AND autoconfig) + OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(1) AND NOT A(6) AND NOT A(3) AND + A(2) AND NOT AUTO_CONFIG_DONE(0) AND autoconfig) + OR (RESET AND RW AND NOT AS AND A(5) AND NOT A(4) AND A(1) AND NOT A(6) AND + A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND + autoconfig) + OR (ROM_OE_S.EXP) + OR (RESET AND NOT D(12) AND NOT RW) + OR (RESET AND NOT D(12) AND AS) + OR (RESET AND NOT D(12) AND NOT autoconfig) + OR (RESET AND NOT D(12) AND AUTO_CONFIG_DONE(0) AND + AUTO_CONFIG_DONE(1) AND AUTO_CONFIG_DONE(2)) + OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND NOT A(3) AND + NOT A(2) AND NOT AUTO_CONFIG_DONE(0) AND autoconfig) + OR (RESET AND RW AND NOT AS AND NOT A(4) AND A(1) AND NOT A(6) AND NOT A(3) AND + A(2) AND NOT AUTO_CONFIG_DONE(0) AND autoconfig) + OR (RESET AND RW AND NOT AS AND NOT A(5) AND A(4) AND NOT A(6) AND A(3) AND + NOT A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND + autoconfig) + OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND NOT A(3) AND + NOT A(2) AND AUTO_CONFIG_DONE(1) AND NOT AUTO_CONFIG_DONE(2) AND + autoconfig) + OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND NOT A(3) AND + NOT A(2) AND NOT AUTO_CONFIG_DONE(1) AND AUTOBOOT_OFF AND autoconfig)); + + +D_I(12) <= D(12)_BUFR; +D(12) <= D_I(12) when D_OE(12) = '1' else 'Z'; +D_OE(12) <= (RW AND AUTOCONFIG_IN_PROGRESS); + +FDCPE_D13_BUFR: FDCPE port map (D(13)_BUFR,D_D(13)_BUFR,ide/ide_CLKF,'0','0'); +D_D(13)_BUFR <= ((IDE_BASEADR(6).EXP) + OR (RESET AND NOT D(13) AND NOT RW) + OR (RESET AND NOT D(13) AND AUTO_CONFIG_DONE(0) AND + AUTO_CONFIG_DONE(1) AND AUTO_CONFIG_DONE(2)) + OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(6) AND NOT A(3) AND + NOT AUTO_CONFIG_DONE(0) AND autoconfig) + OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(3) AND NOT A(2) AND + NOT AUTO_CONFIG_DONE(0) AND autoconfig) + OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(3) AND NOT A(2) AND + NOT AUTO_CONFIG_DONE(1) AND autoconfig) + OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(3) AND NOT A(2) AND + NOT AUTO_CONFIG_DONE(2) AND autoconfig) + OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND A(1) AND NOT A(6) AND + NOT A(3) AND NOT AUTO_CONFIG_DONE(1) AND autoconfig) + OR (RESET AND RW AND NOT AS AND NOT A(5) AND A(1) AND NOT A(6) AND NOT A(3) AND + NOT A(2) AND NOT AUTO_CONFIG_DONE(0) AND autoconfig) + OR (RESET AND RW AND NOT AS AND NOT A(5) AND A(4) AND NOT A(1) AND NOT A(6) AND + A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND + autoconfig) + OR (RESET AND NOT D(13) AND AS) + OR (RESET AND NOT D(13) AND NOT autoconfig) + OR (RESET AND RW AND NOT AS AND NOT A(5) AND A(4) AND NOT A(6) AND A(3) AND + A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND + autoconfig) + OR (RESET AND RW AND NOT AS AND NOT A(5) AND A(1) AND NOT A(6) AND NOT A(3) AND + NOT A(2) AND AUTO_CONFIG_DONE(1) AND NOT AUTO_CONFIG_DONE(2) AND + autoconfig)); + + +D_I(13) <= D(13)_BUFR; +D(13) <= D_I(13) when D_OE(13) = '1' else 'Z'; +D_OE(13) <= (RW AND AUTOCONFIG_IN_PROGRESS); + + +D_I(14) <= D(14)_BUFR; +D(14) <= D_I(14) when D_OE(14) = '1' else 'Z'; +D_OE(14) <= (RW AND AUTOCONFIG_IN_PROGRESS); + +FDCPE_D14_BUFR: FDCPE port map (D(14)_BUFR,D_D(14)_BUFR,ide/ide_CLKF,'0','0'); +D_D(14)_BUFR <= ((EXP16_.EXP) + OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND A(1) AND NOT A(3) AND + NOT A(2) AND NOT AUTO_CONFIG_DONE(0) AND autoconfig) + OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND A(6) AND NOT A(3) AND + NOT A(2) AND NOT AUTO_CONFIG_DONE(0) AND autoconfig) + OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND A(6) AND NOT A(3) AND + NOT A(2) AND NOT AUTO_CONFIG_DONE(1) AND autoconfig) + OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND A(6) AND NOT A(3) AND + NOT A(2) AND NOT AUTO_CONFIG_DONE(2) AND autoconfig) + OR (RESET AND RW AND NOT AS AND NOT A(4) AND A(1) AND NOT A(6) AND NOT A(3) AND + A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND + autoconfig) + OR (RESET AND NOT D(14) AND NOT RW) + OR (RESET AND NOT D(14) AND AS) + OR (RESET AND NOT D(14) AND NOT autoconfig) + OR (RESET AND NOT D(14) AND AUTO_CONFIG_DONE(0) AND + AUTO_CONFIG_DONE(1) AND AUTO_CONFIG_DONE(2)) + OR (RESET AND RW AND NOT AS AND NOT A(5) AND A(1) AND NOT A(6) AND NOT A(3) AND + A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(2) AND + autoconfig) + OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND A(1) AND NOT A(3) AND + NOT A(2) AND NOT AUTO_CONFIG_DONE(1) AND autoconfig) + OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND A(1) AND NOT A(3) AND + NOT A(2) AND NOT AUTO_CONFIG_DONE(2) AND autoconfig) + OR (RESET AND RW AND NOT AS AND NOT A(5) AND A(1) AND NOT A(6) AND NOT A(3) AND + A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND + autoconfig) + OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(6) AND NOT A(3) AND + A(2) AND AUTO_CONFIG_DONE(0) AND AUTO_CONFIG_DONE(1) AND + NOT AUTO_CONFIG_DONE(2) AND autoconfig)); + + +D_I(15) <= D(15)_BUFR; +D(15) <= D_I(15) when D_OE(15) = '1' else 'Z'; +D_OE(15) <= (RW AND AUTOCONFIG_IN_PROGRESS); + +FDCPE_D15_BUFR: FDCPE port map (D(15)_BUFR,D_D(15)_BUFR,ide/ide_CLKF,'0','0'); +D_D(15)_BUFR <= ((RESET AND NOT D(15) AND AUTO_CONFIG_DONE(0) AND + AUTO_CONFIG_DONE(1) AND AUTO_CONFIG_DONE(2)) + OR (RESET AND RW AND NOT AS AND NOT A(5) AND A(1) AND NOT A(6) AND NOT A(3) AND + NOT AUTO_CONFIG_DONE(0) AND autoconfig) + OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND A(6) AND NOT A(3) AND + NOT A(2) AND NOT AUTO_CONFIG_DONE(0) AND autoconfig) + OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND A(6) AND NOT A(3) AND + NOT A(2) AND NOT AUTO_CONFIG_DONE(1) AND autoconfig) + OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND A(6) AND NOT A(3) AND + NOT A(2) AND NOT AUTO_CONFIG_DONE(2) AND autoconfig) + OR (RESET AND RW AND NOT AS AND NOT A(5) AND A(1) AND NOT A(6) AND NOT A(3) AND + AUTO_CONFIG_DONE(1) AND NOT AUTO_CONFIG_DONE(2) AND autoconfig) + OR (RESET AND RW AND NOT AS AND NOT A(5) AND A(4) AND A(1) AND NOT A(6) AND + A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND + autoconfig) + OR (RESET AND RW AND NOT AS AND A(5) AND NOT A(4) AND NOT A(1) AND NOT A(6) AND + NOT A(3) AND A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND + autoconfig) + OR (RESET AND RW AND NOT AS AND NOT A(5) AND A(4) AND NOT A(1) AND NOT A(6) AND + A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND + autoconfig) + OR (RESET AND NOT D(15) AND NOT RW) + OR (RESET AND NOT D(15) AND AS) + OR (RESET AND NOT D(15) AND NOT autoconfig) + OR (RESET AND RW AND NOT AS AND NOT A(5) AND A(1) AND NOT A(6) AND NOT A(3) AND + NOT A(2) AND NOT AUTO_CONFIG_DONE(1) AND autoconfig)); + + +DTACK_I <= '0'; +DTACK <= DTACK_I when DTACK_OE = '1' else 'Z'; +DTACK_OE <= '0'; + + + + + + + + + + + + + + + + + + + + + + +IDE_A(0) <= A(9); + + +IDE_A(1) <= A(10); + + +IDE_A(2) <= A(11); + +FTCPE_IDE_BASEADR0: FTCPE port map (IDE_BASEADR(0),IDE_BASEADR_T(0),ide/ide_CLKF,'0','0'); +IDE_BASEADR_T(0) <= ((NOT RESET AND NOT IDE_BASEADR(0)) + OR (NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND A(6) AND + A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND + NOT IDE_BASEADR(0) AND autoconfig AND D(8).PIN) + OR (RESET AND NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND + A(6) AND A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND + NOT AUTO_CONFIG_DONE(1) AND IDE_BASEADR(0) AND autoconfig AND NOT D(8).PIN)); + +FTCPE_IDE_BASEADR1: FTCPE port map (IDE_BASEADR(1),IDE_BASEADR_T(1),ide/ide_CLKF,'0','0'); +IDE_BASEADR_T(1) <= ((NOT RESET AND NOT IDE_BASEADR(1)) + OR (NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND A(6) AND + A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND + NOT IDE_BASEADR(1) AND autoconfig AND D(9).PIN) + OR (RESET AND NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND + A(6) AND A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND + NOT AUTO_CONFIG_DONE(1) AND IDE_BASEADR(1) AND autoconfig AND NOT D(9).PIN)); + +FTCPE_IDE_BASEADR2: FTCPE port map (IDE_BASEADR(2),IDE_BASEADR_T(2),ide/ide_CLKF,'0','0'); +IDE_BASEADR_T(2) <= ((NOT RESET AND NOT IDE_BASEADR(2)) + OR (NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND A(6) AND + A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND + NOT IDE_BASEADR(2) AND autoconfig AND D(10).PIN) + OR (RESET AND NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND + A(6) AND A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND + NOT AUTO_CONFIG_DONE(1) AND IDE_BASEADR(2) AND autoconfig AND NOT D(10).PIN)); + +FTCPE_IDE_BASEADR3: FTCPE port map (IDE_BASEADR(3),IDE_BASEADR_T(3),ide/ide_CLKF,'0','0'); +IDE_BASEADR_T(3) <= ((NOT RESET AND NOT IDE_BASEADR(3)) + OR (NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND A(6) AND + A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND + NOT IDE_BASEADR(3) AND autoconfig AND D(11).PIN) + OR (RESET AND NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND + A(6) AND A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND + NOT AUTO_CONFIG_DONE(1) AND IDE_BASEADR(3) AND autoconfig AND NOT D(11).PIN)); + +FTCPE_IDE_BASEADR4: FTCPE port map (IDE_BASEADR(4),IDE_BASEADR_T(4),ide/ide_CLKF,'0','0'); +IDE_BASEADR_T(4) <= ((NOT RESET AND NOT IDE_BASEADR(4)) + OR (NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND A(6) AND + A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND + NOT IDE_BASEADR(4) AND autoconfig AND D(12).PIN) + OR (RESET AND NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND + A(6) AND A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND + NOT AUTO_CONFIG_DONE(1) AND IDE_BASEADR(4) AND autoconfig AND NOT D(12).PIN)); + +FTCPE_IDE_BASEADR5: FTCPE port map (IDE_BASEADR(5),IDE_BASEADR_T(5),ide/ide_CLKF,'0','0'); +IDE_BASEADR_T(5) <= ((NOT RESET AND NOT IDE_BASEADR(5)) + OR (NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND A(6) AND + A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND + NOT IDE_BASEADR(5) AND autoconfig AND D(13).PIN) + OR (RESET AND NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND + A(6) AND A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND + NOT AUTO_CONFIG_DONE(1) AND IDE_BASEADR(5) AND autoconfig AND NOT D(13).PIN)); + +FTCPE_IDE_BASEADR6: FTCPE port map (IDE_BASEADR(6),IDE_BASEADR_T(6),ide/ide_CLKF,'0','0'); +IDE_BASEADR_T(6) <= ((NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND A(6) AND + A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND + NOT IDE_BASEADR(6) AND autoconfig AND D(14).PIN) + OR (RESET AND NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND + A(6) AND A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND + NOT AUTO_CONFIG_DONE(1) AND IDE_BASEADR(6) AND autoconfig AND NOT D(14).PIN) + OR (NOT RESET AND NOT IDE_BASEADR(6))); + +FTCPE_IDE_BASEADR7: FTCPE port map (IDE_BASEADR(7),IDE_BASEADR_T(7),ide/ide_CLKF,'0','0'); +IDE_BASEADR_T(7) <= ((RESET AND NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND + A(6) AND A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND + NOT AUTO_CONFIG_DONE(1) AND IDE_BASEADR(7) AND autoconfig AND NOT D(15).PIN) + OR (NOT RESET AND NOT IDE_BASEADR(7)) + OR (NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND A(6) AND + A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND + NOT IDE_BASEADR(7) AND autoconfig AND D(15).PIN)); + + +IDE_CS(0) <= NOT A(12); + + +IDE_CS(1) <= NOT A(13); + +FDCPE_IDE_ENABLE: FDCPE port map (IDE_ENABLE,IDE_ENABLE_D,ide/ide_CLKF,'0','0'); +IDE_ENABLE_D <= ((RESET AND NOT IDE_ENABLE) + OR (RESET AND NOT RW AND NOT AS AND ide)); + +FDCPE_IDE_R: FDCPE port map (IDE_R,IDE_R_D,ide/ide_CLKF,'0','0'); +IDE_R_D <= (RESET AND RW AND NOT AS AND NOT IDE_ENABLE AND ide); + +FDCPE_IDE_W: FDCPE port map (IDE_W,IDE_W_D,ide/ide_CLKF,'0','0'); +IDE_W_D <= (RESET AND NOT RW AND NOT AS AND ide); + + +ROM_B(0) <= '0'; + + +ROM_B(1) <= '0'; + +FDCPE_ROM_OE: FDCPE port map (ROM_OE,ROM_OE_D,ide/ide_CLKF,'0','0'); +ROM_OE_D <= (RESET AND RW AND NOT AS AND IDE_ENABLE AND ide); + +FDCPE_SHUT_UP1: FDCPE port map (SHUT_UP(1),SHUT_UP_D(1),ide/ide_CLKF,'0','0'); +SHUT_UP_D(1) <= ((RESET AND NOT SHUT_UP(1)) + OR (RESET AND NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND + A(6) AND A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND + NOT AUTO_CONFIG_DONE(1) AND autoconfig)); + +FDCPE_autoconfig: FDCPE port map (autoconfig,autoconfig_D,ide/ide_CLKF,'0','0'); +autoconfig_D <= ((A(23) AND A(22) AND A(21) AND A(19) AND + NOT AUTO_CONFIG_DONE(0) AND BERR AND NOT A(17) AND NOT A(16) AND NOT A(20) AND NOT A(18)) + OR (A(23) AND A(22) AND A(21) AND A(19) AND + NOT AUTO_CONFIG_DONE(1) AND BERR AND NOT A(17) AND NOT A(16) AND NOT A(20) AND NOT A(18)) + OR (A(23) AND A(22) AND A(21) AND A(19) AND + NOT AUTO_CONFIG_DONE(2) AND BERR AND NOT A(17) AND NOT A(16) AND NOT A(20) AND NOT A(18))); + +FDCPE_ide: FDCPE port map (ide,ide_D,ide/ide_CLKF,'0','0'); +ide_D <= ((SHUT_UP(1)) + OR (NOT BERR) + OR (EXP20_.EXP) + OR (A(23) AND NOT IDE_BASEADR(7)) + OR (NOT A(23) AND IDE_BASEADR(7)) + OR (A(22) AND NOT IDE_BASEADR(6)) + OR (NOT A(22) AND IDE_BASEADR(6)) + OR (IDE_BASEADR(1) AND NOT A(17)) + OR (autoconfig.EXP) + OR (IDE_BASEADR(0) AND NOT A(16)) + OR (NOT IDE_BASEADR(0) AND A(16)) + OR (NOT IDE_BASEADR(1) AND A(17)) + OR (IDE_BASEADR(2) AND NOT A(18)) + OR (NOT IDE_BASEADR(2) AND A(18)) + OR (A(19) AND NOT IDE_BASEADR(3)) + OR (NOT A(19) AND IDE_BASEADR(3))); + + +ide/ide_CLKF <= NOT (C3 + XOR +ide/ide_CLKF <= NOT (C1); + +Register Legend: + FDCPE (Q,D,C,CLR,PRE,CE); + FTCPE (Q,D,C,CLR,PRE,CE); + LDCP (Q,D,G,CLR,PRE); + + ****************************** Device Pin Out ***************************** + +Device : XC95144XL-10-TQ144 + + +Pin Signal Pin Signal +No. Name No. Name + 1 VCC 73 VCC + 2 D<0> 74 KPR + 3 KPR 75 AUTOBOOT_OFF + 4 KPR 76 KPR + 5 KPR 77 KPR + 6 KPR 78 KPR + 7 KPR 79 KPR + 8 VCC 80 AS + 9 KPR 81 UDS + 10 KPR 82 KPR + 11 KPR 83 RW + 12 KPR 84 VCC + 13 KPR 85 DTACK + 14 D<6> 86 A<23> + 15 D<3> 87 A<22> + 16 D<7> 88 A<21> + 17 D<1> 89 GND + 18 GND 90 GND + 19 D<8> 91 A<20> + 20 D<5> 92 A<19> + 21 D<4> 93 KPR + 22 IDE_CS<0> 94 A<18> + 23 IDE_CS<1> 95 A<17> + 24 IDE_A<0> 96 KPR + 25 IDE_A<2> 97 A<16> + 26 IDE_A<1> 98 BERR + 27 IDE_R 99 GND + 28 IDE_W 100 KPR + 29 GND 101 KPR + 30 KPR 102 C3 + 31 KPR 103 C1 + 32 KPR 104 KPR + 33 KPR 105 KPR + 34 KPR 106 KPR + 35 ROM_OE 107 KPR + 36 GND 108 GND + 37 VCC 109 VCC + 38 KPR 110 KPR + 39 D<2> 111 KPR + 40 D<9> 112 KPR + 41 D<10> 113 KPR + 42 VCC 114 GND + 43 D<11> 115 KPR + 44 D<12> 116 KPR + 45 D<13> 117 KPR + 46 D<14> 118 KPR + 47 GND 119 KPR + 48 D<15> 120 KPR + 49 A<5> 121 KPR + 50 A<4> 122 TDO + 51 A<6> 123 GND + 52 A<3> 124 KPR + 53 KPR 125 KPR + 54 A<2> 126 KPR + 55 VCC 127 VCC + 56 KPR 128 KPR + 57 A<1> 129 KPR + 58 A<9> 130 KPR + 59 A<10> 131 KPR + 60 A<11> 132 KPR + 61 A<12> 133 KPR + 62 GND 134 KPR + 63 TDI 135 KPR + 64 A<13> 136 KPR + 65 TMS 137 KPR + 66 KPR 138 KPR + 67 TCK 139 KPR + 68 ROM_B<0> 140 KPR + 69 ROM_B<1> 141 VCC + 70 KPR 142 KPR + 71 KPR 143 RESET + 72 GND 144 GND + + +Legend : NC = Not Connected, unbonded pin + PGND = Unused I/O configured as additional Ground pin + TIE = Unused I/O floating -- must tie to VCC, GND or other signal + KPR = Unused I/O with weak keeper (leave unconnected) + VCC = Dedicated Power Pin + GND = Dedicated Ground Pin + TDI = Test Data In, JTAG pin + TDO = Test Data Out, JTAG pin + TCK = Test Clock, JTAG pin + TMS = Test Mode Select, JTAG pin + PROHIBITED = User reserved pin + **************************** Compiler Options **************************** + +Following is a list of all global compiler options used by the fitter run. + +Device(s) Specified : xc95144xl-10-TQ144 +Optimization Method : SPEED +Multi-Level Logic Optimization : ON +Ignore Timing Specifications : OFF +Default Register Power Up Value : LOW +Keep User Location Constraints : ON +What-You-See-Is-What-You-Get : OFF +Exhaustive Fitting : OFF +Keep Unused Inputs : OFF +Slew Rate : FAST +Power Mode : STD +Ground on Unused IOs : OFF +Set I/O Pin Termination : KEEPER +Global Clock Optimization : ON +Global Set/Reset Optimization : ON +Global Ouput Enable Optimization : ON +Input Limit : 54 +Pterm Limit : 25 diff --git a/Logic/LAN_IDE/LAN_IDE_CP.stx b/Logic/LAN_IDE/LAN_IDE_CP.stx new file mode 100644 index 0000000..e69de29 diff --git a/Logic/LAN_IDE/LAN_IDE_CP.syr b/Logic/LAN_IDE/LAN_IDE_CP.syr new file mode 100644 index 0000000..4bafe65 --- /dev/null +++ b/Logic/LAN_IDE/LAN_IDE_CP.syr @@ -0,0 +1,286 @@ +Release 14.6 - xst P.68d (nt64) +Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. +--> Parameter TMPDIR set to xst/projnav.tmp + + +Total REAL time to Xst completion: 0.00 secs +Total CPU time to Xst completion: 0.11 secs + +--> Parameter xsthdpdir set to xst + + +Total REAL time to Xst completion: 0.00 secs +Total CPU time to Xst completion: 0.11 secs + +--> Reading design: LAN_IDE_CP.prj + +TABLE OF CONTENTS + 1) Synthesis Options Summary + 2) HDL Compilation + 3) Design Hierarchy Analysis + 4) HDL Analysis + 5) HDL Synthesis + 5.1) HDL Synthesis Report + 6) Advanced HDL Synthesis + 6.1) Advanced HDL Synthesis Report + 7) Low Level Synthesis + 8) Partition Report + 9) Final Report + +========================================================================= +* Synthesis Options Summary * +========================================================================= +---- Source Parameters +Input File Name : "LAN_IDE_CP.prj" +Input Format : mixed +Ignore Synthesis Constraint File : NO + +---- Target Parameters +Output File Name : "LAN_IDE_CP" +Output Format : NGC +Target Device : XC9500XL CPLDs + +---- Source Options +Top Module Name : LAN_IDE_CP +Automatic FSM Extraction : YES +FSM Encoding Algorithm : Auto +Safe Implementation : No +Mux Extraction : Yes +Resource Sharing : YES + +---- Target Options +Add IO Buffers : YES +MACRO Preserve : YES +XOR Preserve : YES +Equivalent register Removal : YES + +---- General Options +Optimization Goal : Speed +Optimization Effort : 1 +Keep Hierarchy : Yes +Netlist Hierarchy : As_Optimized +RTL Output : Yes +Hierarchy Separator : / +Bus Delimiter : <> +Case Specifier : Maintain +Verilog 2001 : YES + +---- Other Options +Clock Enable : YES +wysiwyg : NO + +========================================================================= + + +========================================================================= +* HDL Compilation * +========================================================================= +Compiling vhdl file "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.vhd" in Library work. +Entity compiled. +Entity (Architecture ) compiled. + +========================================================================= +* Design Hierarchy Analysis * +========================================================================= +Analyzing hierarchy for entity in library (architecture ). + + +========================================================================= +* HDL Analysis * +========================================================================= +Analyzing Entity in library (Architecture ). +Entity analyzed. Unit generated. + + +========================================================================= +* HDL Synthesis * +========================================================================= + +Performing bidirectional port resolution... + +Synthesizing Unit . + Related source file is "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.vhd". +WARNING:Xst:2565 - Inout > is never assigned. +WARNING:Xst:1306 - Output is never assigned. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:2565 - Inout > is never assigned. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:1306 - Output is never assigned. +WARNING:Xst:2565 - Inout > is never assigned. +WARNING:Xst:1306 - Output is never assigned. +WARNING:Xst:2565 - Inout > is never assigned. +WARNING:Xst:2565 - Inout > is never assigned. +WARNING:Xst:2565 - Inout > is never assigned. +WARNING:Xst:2565 - Inout > is never assigned. +WARNING:Xst:2565 - Inout > is never assigned. +WARNING:Xst:2565 - Inout > is never assigned. +WARNING:Xst:2565 - Inout > is never assigned. +WARNING:Xst:1306 - Output is never assigned. +WARNING:Xst:2565 - Inout > is never assigned. +WARNING:Xst:2565 - Inout > is never assigned. +WARNING:Xst:1306 - Output is never assigned. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:2565 - Inout > is never assigned. +WARNING:Xst:2565 - Inout > is never assigned. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:2565 - Inout > is never assigned. +WARNING:Xst:2565 - Inout > is never assigned. +WARNING:Xst:1306 - Output is never assigned. +WARNING:Xst:1306 - Output is never assigned. +WARNING:Xst:1306 - Output is never assigned. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:1306 - Output is never assigned. +WARNING:Xst:1306 - Output is never assigned. +WARNING:Xst:2565 - Inout > is never assigned. +WARNING:Xst:2565 - Inout > is never assigned. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:1306 - Output is never assigned. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:2565 - Inout > is never assigned. +WARNING:Xst:2565 - Inout > is never assigned. +WARNING:Xst:1306 - Output is never assigned. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:1306 - Output is never assigned. +WARNING:Xst:1306 - Output is never assigned. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:1306 - Output is never assigned. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. + Found 1-bit tristate buffer for signal . + Found 16-bit tristate buffer for signal <$mux0000>. + Found 1-bit xor2 for signal created at line 108. + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 8-bit comparator not equal for signal created at line 126. + Found 8-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal >. + Summary: + inferred 1 Comparator(s). + inferred 1 Xor(s). + inferred 17 Tristate(s). +Unit synthesized. + + +========================================================================= +HDL Synthesis Report + +Macro Statistics +# Registers : 14 + 1-bit register : 11 + 3-bit register : 1 + 4-bit register : 1 + 8-bit register : 1 +# Comparators : 1 + 8-bit comparator not equal : 1 +# Tristates : 2 + 1-bit tristate buffer : 1 + 16-bit tristate buffer : 1 +# Xors : 1 + 1-bit xor2 : 1 + +========================================================================= + +========================================================================= +* Advanced HDL Synthesis * +========================================================================= + + +========================================================================= +Advanced HDL Synthesis Report + +Found no macro +========================================================================= + +========================================================================= +* Low Level Synthesis * +========================================================================= + +Optimizing unit ... + implementation constraint: INIT=r : IDE_ENABLE + implementation constraint: INIT=r : ide + implementation constraint: INIT=r : autoconfig + implementation constraint: INIT=s : IDE_R_S + implementation constraint: INIT=s : IDE_W_S + implementation constraint: INIT=s : ROM_OE_S + implementation constraint: INIT=r : AUTOCONFIG_IN_PROGRESS + +========================================================================= +* Partition Report * +========================================================================= + +Partition Implementation Status +------------------------------- + + No Partitions were found in this design. + +------------------------------- + +========================================================================= +* Final Report * +========================================================================= +Final Results +RTL Top Level Output File Name : LAN_IDE_CP.ngr +Top Level Output File Name : LAN_IDE_CP +Output Format : NGC +Optimization Goal : Speed +Keep Hierarchy : Yes +Target Technology : XC9500XL CPLDs +Macro Preserve : YES +XOR Preserve : YES +Clock Enable : YES +wysiwyg : NO + +Design Statistics +# IOs : 116 + +Cell Usage : +# BELS : 322 +# AND2 : 75 +# AND3 : 16 +# AND4 : 5 +# AND5 : 1 +# GND : 1 +# INV : 138 +# OR2 : 63 +# OR3 : 13 +# OR4 : 2 +# OR5 : 1 +# VCC : 1 +# XOR2 : 6 +# FlipFlops/Latches : 26 +# FD : 6 +# FDC : 3 +# FDCE : 17 +# IO Buffers : 54 +# IBUF : 27 +# IOBUFE : 8 +# OBUF : 10 +# OBUFE : 9 +========================================================================= + + +Total REAL time to Xst completion: 7.00 secs +Total CPU time to Xst completion: 7.69 secs + +--> + +Total memory usage is 290044 kilobytes + +Number of errors : 0 ( 0 filtered) +Number of warnings : 52 ( 0 filtered) +Number of infos : 0 ( 0 filtered) + diff --git a/Logic/LAN_IDE/LAN_IDE_CP.tim b/Logic/LAN_IDE/LAN_IDE_CP.tim new file mode 100644 index 0000000..e69de29 diff --git a/Logic/LAN_IDE/LAN_IDE_CP.tspec b/Logic/LAN_IDE/LAN_IDE_CP.tspec new file mode 100644 index 0000000..6b5d04c --- /dev/null +++ b/Logic/LAN_IDE/LAN_IDE_CP.tspec @@ -0,0 +1,278 @@ +AUTO_TS_P2P:FROM:C3:TO:IDE_R:1 +AUTO_TS_P2P:FROM:C1:TO:IDE_R:1 +AUTO_TS_F2P:FROM:IDE_R_S.Q:TO:IDE_R:1 +AUTO_TS_P2P:FROM:C3:TO:IDE_W:1 +AUTO_TS_P2P:FROM:C1:TO:IDE_W:1 +AUTO_TS_F2P:FROM:IDE_W_S.Q:TO:IDE_W:1 +AUTO_TS_P2P:FROM:C3:TO:ROM_OE:1 +AUTO_TS_P2P:FROM:C1:TO:ROM_OE:1 +AUTO_TS_F2P:FROM:ROM_OE_S.Q:TO:ROM_OE:1 +AUTO_TS_P2P:FROM:A<9>:TO:IDE_A<0>:1 +AUTO_TS_P2P:FROM:A<10>:TO:IDE_A<1>:1 +AUTO_TS_P2P:FROM:A<11>:TO:IDE_A<2>:1 +AUTO_TS_P2P:FROM:A<12>:TO:IDE_CS<0>:1 +AUTO_TS_P2P:FROM:A<13>:TO:IDE_CS<1>:1 +AUTO_TS_F2F:FROM:AUTO_CONFIG_DONE_CYCLE<1>.Q:TO:AUTO_CONFIG_DONE_CYCLE<1>.D:1 +AUTO_TS_F2F:FROM:autoconfig.Q:TO:AUTO_CONFIG_DONE_CYCLE<1>.D:1 +AUTO_TS_F2F:FROM:AUTO_CONFIG_DONE<1>.Q:TO:AUTO_CONFIG_DONE_CYCLE<1>.D:1 +AUTO_TS_F2F:FROM:AUTO_CONFIG_DONE<0>.Q:TO:AUTO_CONFIG_DONE_CYCLE<1>.D:1 +AUTO_TS_P2F:FROM:RESET:TO:AUTO_CONFIG_DONE_CYCLE<1>.D:1 +AUTO_TS_P2F:FROM:C3:TO:AUTO_CONFIG_DONE_CYCLE<1>.D:1 +AUTO_TS_P2F:FROM:C1:TO:AUTO_CONFIG_DONE_CYCLE<1>.D:1 +AUTO_TS_P2F:FROM:AS:TO:AUTO_CONFIG_DONE_CYCLE<1>.D:1 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+AUTO_TS_P2F:FROM:C3:TO:IDE_ENABLE.D:1 +AUTO_TS_P2F:FROM:C1:TO:IDE_ENABLE.D:1 +AUTO_TS_P2F:FROM:AS:TO:IDE_ENABLE.D:1 +AUTO_TS_P2F:FROM:RW:TO:IDE_ENABLE.D:1 +AUTO_TS_F2F:FROM:IDE_BASEADR<1>.Q:TO:IDE_BASEADR<1>.D:1 +AUTO_TS_F2F:FROM:autoconfig.Q:TO:IDE_BASEADR<1>.D:1 +AUTO_TS_F2F:FROM:AUTO_CONFIG_DONE<1>.Q:TO:IDE_BASEADR<1>.D:1 +AUTO_TS_F2F:FROM:AUTO_CONFIG_DONE<0>.Q:TO:IDE_BASEADR<1>.D:1 +AUTO_TS_P2F:FROM:RESET:TO:IDE_BASEADR<1>.D:1 +AUTO_TS_P2F:FROM:C3:TO:IDE_BASEADR<1>.D:1 +AUTO_TS_P2F:FROM:C1:TO:IDE_BASEADR<1>.D:1 +AUTO_TS_P2F:FROM:AS:TO:IDE_BASEADR<1>.D:1 +AUTO_TS_P2F:FROM:RW:TO:IDE_BASEADR<1>.D:1 +AUTO_TS_P2F:FROM:A<1>:TO:IDE_BASEADR<1>.D:1 +AUTO_TS_P2F:FROM:A<3>:TO:IDE_BASEADR<1>.D:1 +AUTO_TS_P2F:FROM:A<4>:TO:IDE_BASEADR<1>.D:1 +AUTO_TS_P2F:FROM:A<5>:TO:IDE_BASEADR<1>.D:1 +AUTO_TS_P2F:FROM:A<6>:TO:IDE_BASEADR<1>.D:1 +AUTO_TS_P2F:FROM:UDS:TO:IDE_BASEADR<1>.D:1 +AUTO_TS_P2F:FROM:A<2>:TO:IDE_BASEADR<1>.D:1 +AUTO_TS_P2F:FROM:D<9>:TO:IDE_BASEADR<1>.D:1 +AUTO_TS_F2F:FROM:IDE_BASEADR<2>.Q:TO:IDE_BASEADR<2>.D:1 +AUTO_TS_F2F:FROM:autoconfig.Q:TO:IDE_BASEADR<2>.D:1 +AUTO_TS_F2F:FROM:AUTO_CONFIG_DONE<1>.Q:TO:IDE_BASEADR<2>.D:1 +AUTO_TS_F2F:FROM:AUTO_CONFIG_DONE<0>.Q:TO:IDE_BASEADR<2>.D:1 +AUTO_TS_P2F:FROM:RESET:TO:IDE_BASEADR<2>.D:1 +AUTO_TS_P2F:FROM:C3:TO:IDE_BASEADR<2>.D:1 +AUTO_TS_P2F:FROM:C1:TO:IDE_BASEADR<2>.D:1 +AUTO_TS_P2F:FROM:AS:TO:IDE_BASEADR<2>.D:1 +AUTO_TS_P2F:FROM:RW:TO:IDE_BASEADR<2>.D:1 +AUTO_TS_P2F:FROM:A<1>:TO:IDE_BASEADR<2>.D:1 +AUTO_TS_P2F:FROM:A<3>:TO:IDE_BASEADR<2>.D:1 +AUTO_TS_P2F:FROM:A<4>:TO:IDE_BASEADR<2>.D:1 +AUTO_TS_P2F:FROM:A<5>:TO:IDE_BASEADR<2>.D:1 +AUTO_TS_P2F:FROM:A<6>:TO:IDE_BASEADR<2>.D:1 +AUTO_TS_P2F:FROM:UDS:TO:IDE_BASEADR<2>.D:1 +AUTO_TS_P2F:FROM:A<2>:TO:IDE_BASEADR<2>.D:1 +AUTO_TS_P2F:FROM:D<10>:TO:IDE_BASEADR<2>.D:1 +AUTO_TS_F2F:FROM:IDE_BASEADR<3>.Q:TO:IDE_BASEADR<3>.D:1 +AUTO_TS_F2F:FROM:autoconfig.Q:TO:IDE_BASEADR<3>.D:1 +AUTO_TS_F2F:FROM:AUTO_CONFIG_DONE<1>.Q:TO:IDE_BASEADR<3>.D:1 +AUTO_TS_F2F:FROM:AUTO_CONFIG_DONE<0>.Q:TO:IDE_BASEADR<3>.D:1 +AUTO_TS_P2F:FROM:RESET:TO:IDE_BASEADR<3>.D:1 +AUTO_TS_P2F:FROM:C3:TO:IDE_BASEADR<3>.D:1 +AUTO_TS_P2F:FROM:C1:TO:IDE_BASEADR<3>.D:1 +AUTO_TS_P2F:FROM:AS:TO:IDE_BASEADR<3>.D:1 +AUTO_TS_P2F:FROM:RW:TO:IDE_BASEADR<3>.D:1 +AUTO_TS_P2F:FROM:A<1>:TO:IDE_BASEADR<3>.D:1 +AUTO_TS_P2F:FROM:A<3>:TO:IDE_BASEADR<3>.D:1 +AUTO_TS_P2F:FROM:A<4>:TO:IDE_BASEADR<3>.D:1 +AUTO_TS_P2F:FROM:A<5>:TO:IDE_BASEADR<3>.D:1 +AUTO_TS_P2F:FROM:A<6>:TO:IDE_BASEADR<3>.D:1 +AUTO_TS_P2F:FROM:UDS:TO:IDE_BASEADR<3>.D:1 +AUTO_TS_P2F:FROM:A<2>:TO:IDE_BASEADR<3>.D:1 +AUTO_TS_P2F:FROM:D<11>:TO:IDE_BASEADR<3>.D:1 +AUTO_TS_F2F:FROM:IDE_BASEADR<6>.Q:TO:IDE_BASEADR<6>.D:1 +AUTO_TS_F2F:FROM:autoconfig.Q:TO:IDE_BASEADR<6>.D:1 +AUTO_TS_F2F:FROM:AUTO_CONFIG_DONE<1>.Q:TO:IDE_BASEADR<6>.D:1 +AUTO_TS_F2F:FROM:AUTO_CONFIG_DONE<0>.Q:TO:IDE_BASEADR<6>.D:1 +AUTO_TS_P2F:FROM:RESET:TO:IDE_BASEADR<6>.D:1 +AUTO_TS_P2F:FROM:C3:TO:IDE_BASEADR<6>.D:1 +AUTO_TS_P2F:FROM:C1:TO:IDE_BASEADR<6>.D:1 +AUTO_TS_P2F:FROM:AS:TO:IDE_BASEADR<6>.D:1 +AUTO_TS_P2F:FROM:RW:TO:IDE_BASEADR<6>.D:1 +AUTO_TS_P2F:FROM:A<1>:TO:IDE_BASEADR<6>.D:1 +AUTO_TS_P2F:FROM:A<3>:TO:IDE_BASEADR<6>.D:1 +AUTO_TS_P2F:FROM:A<4>:TO:IDE_BASEADR<6>.D:1 +AUTO_TS_P2F:FROM:A<5>:TO:IDE_BASEADR<6>.D:1 +AUTO_TS_P2F:FROM:A<6>:TO:IDE_BASEADR<6>.D:1 +AUTO_TS_P2F:FROM:UDS:TO:IDE_BASEADR<6>.D:1 +AUTO_TS_P2F:FROM:A<2>:TO:IDE_BASEADR<6>.D:1 +AUTO_TS_P2F:FROM:D<14>:TO:IDE_BASEADR<6>.D:1 +AUTO_TS_F2F:FROM:IDE_BASEADR<7>.Q:TO:IDE_BASEADR<7>.D:1 +AUTO_TS_F2F:FROM:autoconfig.Q:TO:IDE_BASEADR<7>.D:1 +AUTO_TS_F2F:FROM:AUTO_CONFIG_DONE<1>.Q:TO:IDE_BASEADR<7>.D:1 +AUTO_TS_F2F:FROM:AUTO_CONFIG_DONE<0>.Q:TO:IDE_BASEADR<7>.D:1 +AUTO_TS_P2F:FROM:RESET:TO:IDE_BASEADR<7>.D:1 +AUTO_TS_P2F:FROM:C3:TO:IDE_BASEADR<7>.D:1 +AUTO_TS_P2F:FROM:C1:TO:IDE_BASEADR<7>.D:1 +AUTO_TS_P2F:FROM:AS:TO:IDE_BASEADR<7>.D:1 +AUTO_TS_P2F:FROM:RW:TO:IDE_BASEADR<7>.D:1 +AUTO_TS_P2F:FROM:A<1>:TO:IDE_BASEADR<7>.D:1 +AUTO_TS_P2F:FROM:A<3>:TO:IDE_BASEADR<7>.D:1 +AUTO_TS_P2F:FROM:A<4>:TO:IDE_BASEADR<7>.D:1 +AUTO_TS_P2F:FROM:A<5>:TO:IDE_BASEADR<7>.D:1 +AUTO_TS_P2F:FROM:A<6>:TO:IDE_BASEADR<7>.D:1 +AUTO_TS_P2F:FROM:UDS:TO:IDE_BASEADR<7>.D:1 +AUTO_TS_P2F:FROM:A<2>:TO:IDE_BASEADR<7>.D:1 +AUTO_TS_P2F:FROM:D<15>:TO:IDE_BASEADR<7>.D:1 +AUTO_TS_F2F:FROM:SHUT_UP<1>.Q:TO:SHUT_UP<1>.D:1 +AUTO_TS_F2F:FROM:autoconfig.Q:TO:SHUT_UP<1>.D:1 +AUTO_TS_F2F:FROM:AUTO_CONFIG_DONE<1>.Q:TO:SHUT_UP<1>.D:1 +AUTO_TS_F2F:FROM:AUTO_CONFIG_DONE<0>.Q:TO:SHUT_UP<1>.D:1 +AUTO_TS_P2F:FROM:RESET:TO:SHUT_UP<1>.D:1 +AUTO_TS_P2F:FROM:C3:TO:SHUT_UP<1>.D:1 +AUTO_TS_P2F:FROM:C1:TO:SHUT_UP<1>.D:1 +AUTO_TS_P2F:FROM:AS:TO:SHUT_UP<1>.D:1 +AUTO_TS_P2F:FROM:RW:TO:SHUT_UP<1>.D:1 +AUTO_TS_P2F:FROM:A<1>:TO:SHUT_UP<1>.D:1 +AUTO_TS_P2F:FROM:A<3>:TO:SHUT_UP<1>.D:1 +AUTO_TS_P2F:FROM:A<4>:TO:SHUT_UP<1>.D:1 +AUTO_TS_P2F:FROM:A<5>:TO:SHUT_UP<1>.D:1 +AUTO_TS_P2F:FROM:A<6>:TO:SHUT_UP<1>.D:1 +AUTO_TS_P2F:FROM:UDS:TO:SHUT_UP<1>.D:1 +AUTO_TS_P2F:FROM:A<2>:TO:SHUT_UP<1>.D:1 +AUTO_TS_F2F:FROM:SHUT_UP<1>.Q:TO:ide.D:1 +AUTO_TS_F2F:FROM:IDE_BASEADR<5>.Q:TO:ide.D:1 +AUTO_TS_F2F:FROM:IDE_BASEADR<4>.Q:TO:ide.D:1 +AUTO_TS_F2F:FROM:IDE_BASEADR<0>.Q:TO:ide.D:1 +AUTO_TS_F2F:FROM:IDE_BASEADR<1>.Q:TO:ide.D:1 +AUTO_TS_F2F:FROM:IDE_BASEADR<2>.Q:TO:ide.D:1 +AUTO_TS_F2F:FROM:IDE_BASEADR<7>.Q:TO:ide.D:1 +AUTO_TS_F2F:FROM:IDE_BASEADR<6>.Q:TO:ide.D:1 +AUTO_TS_F2F:FROM:IDE_BASEADR<3>.Q:TO:ide.D:1 +AUTO_TS_P2F:FROM:C3:TO:ide.D:1 +AUTO_TS_P2F:FROM:C1:TO:ide.D:1 +AUTO_TS_P2F:FROM:BERR:TO:ide.D:1 +AUTO_TS_P2F:FROM:A<21>:TO:ide.D:1 +AUTO_TS_P2F:FROM:A<20>:TO:ide.D:1 +AUTO_TS_P2F:FROM:A<16>:TO:ide.D:1 +AUTO_TS_P2F:FROM:A<17>:TO:ide.D:1 +AUTO_TS_P2F:FROM:A<18>:TO:ide.D:1 +AUTO_TS_P2F:FROM:A<23>:TO:ide.D:1 +AUTO_TS_P2F:FROM:A<22>:TO:ide.D:1 +AUTO_TS_P2F:FROM:A<19>:TO:ide.D:1 +AUTO_TS_F2F:FROM:IDE_ENABLE.Q:TO:IDE_R_S.D:1 +AUTO_TS_F2F:FROM:ide.Q:TO:IDE_R_S.D:1 +AUTO_TS_P2F:FROM:AS:TO:IDE_R_S.D:1 +AUTO_TS_P2F:FROM:RESET:TO:IDE_R_S.D:1 +AUTO_TS_P2F:FROM:RW:TO:IDE_R_S.D:1 +AUTO_TS_P2F:FROM:C3:TO:IDE_R_S.D:1 +AUTO_TS_P2F:FROM:C1:TO:IDE_R_S.D:1 +AUTO_TS_F2F:FROM:ide.Q:TO:IDE_W_S.D:1 +AUTO_TS_P2F:FROM:AS:TO:IDE_W_S.D:1 +AUTO_TS_P2F:FROM:RESET:TO:IDE_W_S.D:1 +AUTO_TS_P2F:FROM:RW:TO:IDE_W_S.D:1 +AUTO_TS_P2F:FROM:C3:TO:IDE_W_S.D:1 +AUTO_TS_P2F:FROM:C1:TO:IDE_W_S.D:1 +AUTO_TS_F2F:FROM:IDE_ENABLE.Q:TO:ROM_OE_S.D:1 +AUTO_TS_F2F:FROM:ide.Q:TO:ROM_OE_S.D:1 +AUTO_TS_P2F:FROM:AS:TO:ROM_OE_S.D:1 +AUTO_TS_P2F:FROM:RESET:TO:ROM_OE_S.D:1 +AUTO_TS_P2F:FROM:RW:TO:ROM_OE_S.D:1 +AUTO_TS_P2F:FROM:C3:TO:ROM_OE_S.D:1 +AUTO_TS_P2F:FROM:C1:TO:ROM_OE_S.D:1 +AUTO_TS_F2F:FROM:AUTO_CONFIG_DONE_CYCLE<1>.Q:TO:AUTO_CONFIG_DONE<1>.D:1 +AUTO_TS_P2F:FROM:C3:TO:AUTO_CONFIG_DONE<1>.D:1 +AUTO_TS_P2F:FROM:C1:TO:AUTO_CONFIG_DONE<1>.D:1 +AUTO_TS_F2F:FROM:AUTO_CONFIG_DONE<1>.Q:TO:autoconfig.D:1 +AUTO_TS_F2F:FROM:AUTO_CONFIG_DONE<0>.Q:TO:autoconfig.D:1 +AUTO_TS_P2F:FROM:A<23>:TO:autoconfig.D:1 +AUTO_TS_P2F:FROM:A<22>:TO:autoconfig.D:1 +AUTO_TS_P2F:FROM:A<21>:TO:autoconfig.D:1 +AUTO_TS_P2F:FROM:A<19>:TO:autoconfig.D:1 +AUTO_TS_P2F:FROM:AS:TO:autoconfig.D:1 +AUTO_TS_P2F:FROM:BERR:TO:autoconfig.D:1 +AUTO_TS_P2F:FROM:A<18>:TO:autoconfig.D:1 +AUTO_TS_P2F:FROM:A<16>:TO:autoconfig.D:1 +AUTO_TS_P2F:FROM:A<17>:TO:autoconfig.D:1 +AUTO_TS_P2F:FROM:A<20>:TO:autoconfig.D:1 +AUTO_TS_P2F:FROM:AS:TO:AUTO_CONFIG_DONE<1>.CLKF:1 +AUTO_TS_P2F:FROM:RESET:TO:FSR-IO_0:1 +AUTO_TS_P2F:FROM:C3:TO:AUTO_CONFIG_DONE_CYCLE<1>.CLKF:1 +AUTO_TS_P2F:FROM:C1:TO:AUTO_CONFIG_DONE_CYCLE<1>.CLKF:1 +AUTO_TS_P2F:FROM:C3:TO:IDE_BASEADR<0>.CLKF:1 +AUTO_TS_P2F:FROM:C1:TO:IDE_BASEADR<0>.CLKF:1 +AUTO_TS_P2F:FROM:C3:TO:IDE_BASEADR<4>.CLKF:1 +AUTO_TS_P2F:FROM:C1:TO:IDE_BASEADR<4>.CLKF:1 +AUTO_TS_P2F:FROM:C3:TO:IDE_BASEADR<5>.CLKF:1 +AUTO_TS_P2F:FROM:C1:TO:IDE_BASEADR<5>.CLKF:1 +AUTO_TS_P2F:FROM:C3:TO:IDE_ENABLE.CLKF:1 +AUTO_TS_P2F:FROM:C1:TO:IDE_ENABLE.CLKF:1 +AUTO_TS_P2F:FROM:C3:TO:IDE_BASEADR<1>.CLKF:1 +AUTO_TS_P2F:FROM:C1:TO:IDE_BASEADR<1>.CLKF:1 +AUTO_TS_P2F:FROM:C3:TO:IDE_BASEADR<2>.CLKF:1 +AUTO_TS_P2F:FROM:C1:TO:IDE_BASEADR<2>.CLKF:1 +AUTO_TS_P2F:FROM:C3:TO:IDE_BASEADR<3>.CLKF:1 +AUTO_TS_P2F:FROM:C1:TO:IDE_BASEADR<3>.CLKF:1 +AUTO_TS_P2F:FROM:C3:TO:IDE_BASEADR<6>.CLKF:1 +AUTO_TS_P2F:FROM:C1:TO:IDE_BASEADR<6>.CLKF:1 +AUTO_TS_P2F:FROM:C3:TO:IDE_BASEADR<7>.CLKF:1 +AUTO_TS_P2F:FROM:C1:TO:IDE_BASEADR<7>.CLKF:1 +AUTO_TS_P2F:FROM:C3:TO:SHUT_UP<1>.CLKF:1 +AUTO_TS_P2F:FROM:C1:TO:SHUT_UP<1>.CLKF:1 +AUTO_TS_P2F:FROM:AS:TO:AUTO_CONFIG_DONE<0>.CLKF:1 +AUTO_TS_P2F:FROM:C3:TO:ide.CLKF:1 +AUTO_TS_P2F:FROM:C1:TO:ide.CLKF:1 +AUTO_TS_P2F:FROM:C3:TO:autoconfig.CLKF:1 +AUTO_TS_P2F:FROM:C1:TO:autoconfig.CLKF:1 +AUTO_TS_P2F:FROM:C3:TO:IDE_R_S.CLKF:1 +AUTO_TS_P2F:FROM:C1:TO:IDE_R_S.CLKF:1 +AUTO_TS_P2F:FROM:C3:TO:IDE_W_S.CLKF:1 +AUTO_TS_P2F:FROM:C1:TO:IDE_W_S.CLKF:1 +AUTO_TS_P2F:FROM:C3:TO:ROM_OE_S.CLKF:1 +AUTO_TS_P2F:FROM:C1:TO:ROM_OE_S.CLKF:1 diff --git a/Logic/LAN_IDE/LAN_IDE_CP.vhd b/Logic/LAN_IDE/LAN_IDE_CP.vhd index 642e7ea..998a2fb 100644 --- a/Logic/LAN_IDE/LAN_IDE_CP.vhd +++ b/Logic/LAN_IDE/LAN_IDE_CP.vhd @@ -30,7 +30,7 @@ use IEEE.STD_LOGIC_1164.ALL; --use UNISIM.VComponents.all; entity LAN_IDE_CP is - Port ( A : inout STD_LOGIC_VECTOR (23 downto 0); + Port ( A : inout STD_LOGIC_VECTOR (23 downto 1); D : inout STD_LOGIC_VECTOR (15 downto 0); DQ : inout STD_LOGIC_VECTOR (15 downto 0); A_LAN : out STD_LOGIC_VECTOR (13 downto 0); @@ -49,6 +49,7 @@ entity LAN_IDE_CP is UDS : in STD_LOGIC; LDS : in STD_LOGIC; AS : in STD_LOGIC; + RW : in STD_LOGIC; Z3 : in STD_LOGIC; DS1 : in STD_LOGIC; FCS : in STD_LOGIC; @@ -77,8 +78,271 @@ end LAN_IDE_CP; architecture Behavioral of LAN_IDE_CP is -begin + SIGNAL ide: STD_LOGIC:= '0'; + SIGNAL autoconfig: STD_LOGIC:= '0'; + SIGNAL AUTOCONFIG_IN_PROGRESS: STD_LOGIC:= '0'; + signal Dout1:STD_LOGIC_VECTOR(3 downto 0); + signal AUTO_CONFIG_DONE:STD_LOGIC_VECTOR(2 downto 0); + signal AUTO_CONFIG_DONE_CYCLE:STD_LOGIC_VECTOR(2 downto 0); + signal SHUT_UP:STD_LOGIC_VECTOR(2 downto 0); + signal IDE_BASEADR:STD_LOGIC_VECTOR(7 downto 0); + signal LAN_BASEADR:STD_LOGIC_VECTOR(7 downto 0); + signal CP_BASEADR:STD_LOGIC_VECTOR(7 downto 0); + signal IDE_ENABLE:STD_LOGIC:= '0'; + signal ROM_OE_S:STD_LOGIC:= '1'; + signal IDE_R_S:STD_LOGIC:= '1'; + signal IDE_W_S:STD_LOGIC:= '1'; + signal DTACK_S:STD_LOGIC:= '1'; + signal AS_D: std_logic:= '1'; + signal AMIGA_CLK: std_logic:= '1'; + Function to_std_logic(X: in Boolean) return Std_Logic is + variable ret : std_logic; + begin + if x then ret := '1'; else ret := '0'; end if; + return ret; + end to_std_logic; + +begin + + AMIGA_CLK <= not (C1 xor C3); + + ADDRESS_DECODE: process(AMIGA_CLK) + begin + if(rising_edge(AMIGA_CLK))then + if(AS='0')then + AUTOCONFIG_IN_PROGRESS<= autoconfig; + else + AUTOCONFIG_IN_PROGRESS<= '0'; + end if; + + if(BERR='1') then + if(A(23 downto 16) = x"E8" and not(AUTO_CONFIG_DONE ="111"))then + autoconfig <='1'; + else + autoconfig <='0'; + end if; + + if(A(23 downto 16) = IDE_BASEADR and SHUT_UP(1) = '0')then + ide <='1'; + else + ide <='0'; + end if; + else + autoconfig <='0'; + ide <='0'; + end if; + end if; + end process ADDRESS_DECODE; + + --ide + -- this is the clocked process + ide_rw_gen: process (AMIGA_CLK) + begin + + if rising_edge(AMIGA_CLK) then + if (reset = '0') then + IDE_R_S <= '1'; + IDE_W_S <= '1'; + ROM_OE_S <= '1'; + IDE_ENABLE <= '1'; + elsif(AS='0' and ide='1')then + if(RW='0')then + --the write goes to the hdd! + IDE_ENABLE <= '0'; -- enable IDE on first read + IDE_W_S <= '0'; + IDE_R_S <= '1'; + ROM_OE_S <= '1'; + else + IDE_W_S <= '1'; + IDE_R_S <= IDE_ENABLE; --read from IDE instead from ROM + ROM_OE_S <= not IDE_ENABLE; + end if; + else + IDE_R_S <= '1'; + IDE_W_S <= '1'; + ROM_OE_S <= '1'; + end if; + + end if; + end process ide_rw_gen; + + + --autoconfig + + autoconfig_done: process (reset, AS) + begin + if reset = '0' then + -- reset active ... + AUTO_CONFIG_DONE <="000"; + elsif rising_edge(AS) then -- no reset, so wait for rising edge of the nAS + AUTO_CONFIG_DONE <= AUTO_CONFIG_DONE_CYCLE; + end if; + end process autoconfig_done; + + + autoconfig_proc: process (reset, AMIGA_CLK) + begin + if rising_edge(AMIGA_CLK) then -- no reset, so wait for rising edge of the clock + if reset = '0' then + -- reset active ... + AUTO_CONFIG_DONE_CYCLE <="000"; + Dout1<="1111"; + --Dout2<="1111"; + SHUT_UP <="111"; + IDE_BASEADR<=x"FF"; + LAN_BASEADR<=x"FF"; + CP_BASEADR<=x"FF"; + elsif(autoconfig= '1' and AS='0') then + if(RW='1') then + if(AUTO_CONFIG_DONE(0)='0')then + case A(6 downto 1) is + when "000000" => + Dout1 <= "1100" ; --ZII, System-Memory, no ROM + when "000001" => Dout1 <= "0001" ; --one Card, 64KB =001 + when "000010" => Dout1 <= "1000" ; --ProductID high nibble : E->0001 + when "000011" => Dout1 <= "0100" ; --ProductID low nibble: F->0000 + --when "0001000" => Dout1 <= "1111" ; --Config HIGH: 0x20 and no shut down + --when "0001010" => Dout1 <= "1111" ; --Config LOW + --when "0010000" => Dout1 <= "1111" ; --Ventor ID 0 + when "001001" => Dout1 <= "0101" ; --Ventor ID 1 + when "001010" => Dout1 <= "1110" ; --Ventor ID 2 + when "001011" => Dout1 <= "0011" ; --Ventor ID 3 : $0A1C: A1K.org + --when "0011000" => Dout1 <= "1111" ; --Serial byte 0 (msb) high nibble + --when "0011010" => Dout1 <= "1111" ; --Serial byte 0 (msb) low nibble + --when "0011100" => Dout1 <= "1111" ; --Serial byte 1 high nibble + --when "0011110" => Dout1 <= "1111" ; --Serial byte 1 low nibble + --when "0100000" => Dout1 <= "1111" ; --Serial byte 2 high nibble + --when "0100010" => Dout1 <= "1111" ; --Serial byte 2 low nibble + --when "0100100" => Dout1 <= "1111" ; --Serial byte 3 (lsb) high nibble + --when "010001" => Dout1 <= "1000" ; --Serial byte 2 low nibble + when "010011" => Dout1 <= "1110" ; --Serial byte 3 (lsb) low nibble + when "100000" => Dout1 <= "0000" ; --Interrupt config: all zero + when "100001" => Dout1 <= "0000" ; --Interrupt config: all zero + when others => Dout1 <= "1111" ; + end case; + elsif(AUTO_CONFIG_DONE(1)='0')then + case A(6 downto 1) is + when "000000" => + if(AUTOBOOT_OFF ='0') then + Dout1 <= "1101" ; --ZII, no System-Memory, ROM + else + Dout1 <= "1100" ; --ZII, no System-Memory, no ROM + end if; + when "000001" => Dout1 <= "0001" ; --one Card, 64kb = 001 + --when "0000100" => Dout2 <= "1111" ; --ProductID high nibble : F->0000=0 + when "000011" => Dout1 <= "1001" ; --ProductID low nibble: 9->0110=6 + --when "0001000" => Dout <= "1111" ; --Config HIGH: 0x20 and no shut down + --when "0001010" => Dout2 <= "1111" ; --Config LOW + --when "0010000" => Dout2 <= "1111" ; --Ventor ID 0 + when "001001" => Dout1 <= "0111" ; --Ventor ID 1 + when "001010" => Dout1 <= "1101" ; --Ventor ID 2 + when "001011" => Dout1 <= "0011" ; --Ventor ID 3 : $082C: BSC + when "001100" => Dout1 <= "0100" ; --Serial byte 0 (msb) high nibble + when "001101" => Dout1 <= "1110" ; --Serial byte 0 (msb) low nibble + when "001110" => Dout1 <= "1001" ; --Serial byte 1 high nibble + when "001111" => Dout1 <= "0100" ; --Serial byte 1 low nibble + --when "0100000" => Dout2 <= "1111" ; --Serial byte 2 high nibble + --when "0100010" => Dout2 <= "1111" ; --Serial byte 2 low nibble + when "010010" => Dout1 <= "0100" ; --Serial byte 3 (lsb) high nibble + when "010011" => Dout1 <= "1010" ; --Serial byte 3 (lsb) low nibble: B16B00B5 + --when "0101000" => Dout2 <= "1111" ; --Rom vector high byte high nibble + --when "0101010" => Dout2 <= "1111" ; --Rom vector high byte low nibble + --when "0101100" => Dout2 <= "1111" ; --Rom vector low byte high nibble + when "010111" => Dout1 <= "1110" ; --Rom vector low byte low nibble + when "100000" => Dout1 <= "0000" ; --Interrupt config: all zero + when "100001" => Dout1 <= "0000" ; --Interrupt config: all zero + when others => Dout1 <= "1111" ; + end case; + elsif(AUTO_CONFIG_DONE(2)='0')then + case A(6 downto 1) is + when "000000" => + Dout1 <= "1100" ; --ZII, System-Memory, no ROM + when "000001" => Dout1 <= "0001" ; --one Card, 64KB =001 + when "000010" => Dout1 <= "1000" ; --ProductID high nibble : E->0001 + when "000011" => Dout1 <= "0011" ; --ProductID low nibble: F->0000 + --when "0001000" => Dout1 <= "1111" ; --Config HIGH: 0x20 and no shut down + --when "0001010" => Dout1 <= "1111" ; --Config LOW + --when "0010000" => Dout1 <= "1111" ; --Ventor ID 0 + when "001001" => Dout1 <= "0101" ; --Ventor ID 1 + when "001010" => Dout1 <= "1110" ; --Ventor ID 2 + when "001011" => Dout1 <= "0011" ; --Ventor ID 3 : $0A1C: A1K.org + --when "0011000" => Dout1 <= "1111" ; --Serial byte 0 (msb) high nibble + --when "0011010" => Dout1 <= "1111" ; --Serial byte 0 (msb) low nibble + --when "0011100" => Dout1 <= "1111" ; --Serial byte 1 high nibble + --when "0011110" => Dout1 <= "1111" ; --Serial byte 1 low nibble + --when "0100000" => Dout1 <= "1111" ; --Serial byte 2 high nibble + --when "0100010" => Dout1 <= "1111" ; --Serial byte 2 low nibble + --when "0100100" => Dout1 <= "1111" ; --Serial byte 3 (lsb) high nibble + --when "010001" => Dout1 <= "1000" ; --Serial byte 2 low nibble + when "010011" => Dout1 <= "1110" ; --Serial byte 3 (lsb) low nibble + when "100000" => Dout1 <= "0000" ; --Interrupt config: all zero + when "100001" => Dout1 <= "0000" ; --Interrupt config: all zero + when others => Dout1 <= "1111" ; + end case; + elsif(AUTO_CONFIG_DONE(1)='0')then + end if; + else --write + if( UDS='0' )then + if(AUTO_CONFIG_DONE(0)='0')then + if(A (6 downto 1)="100100")then + LAN_BASEADR(7 downto 0) <= D(15 downto 8); --Base adress + AUTO_CONFIG_DONE_CYCLE(0) <='1'; --done here + SHUT_UP(0) <='0'; --enable board + elsif(A (6 downto 1)="100110")then + AUTO_CONFIG_DONE_CYCLE(0) <='1'; --done here + end if; + elsif(AUTO_CONFIG_DONE(1)='0')then + -- if(AUTO_CONFIG_DONE(1)='0')then + if(A (6 downto 1)="100100")then + IDE_BASEADR(7 downto 0) <= D(15 downto 8); --Base adress + SHUT_UP(1) <= '0'; --enable board + AUTO_CONFIG_DONE_CYCLE(1) <='1'; --done here + elsif(A (6 downto 1)="100110")then + AUTO_CONFIG_DONE_CYCLE(1) <='1'; --done here + end if; + elsif(AUTO_CONFIG_DONE(2)='0')then + -- if(AUTO_CONFIG_DONE(1)='0')then + if(A (6 downto 1)="100100")then + CP_BASEADR(7 downto 0) <= D(15 downto 8); --Base adress + SHUT_UP(2) <= '0'; --enable board + AUTO_CONFIG_DONE_CYCLE(2) <='1'; --done here + elsif(A (6 downto 1)="100110")then + AUTO_CONFIG_DONE_CYCLE(2) <='1'; --done here + end if; + end if; + end if; + end if; + end if; + end if; + end process autoconfig_proc; --- that's all + + + + --signal assignment + D <= --RAM_D when RW='1' and TRANSFER_IN_PROGRES ='1' else + Dout1 & "111111111111" when RW='1' and AUTOCONFIG_IN_PROGRESS ='1' else + "ZZZZZZZZZZZZZZZZ"; +-- +-- DRAM <= D when RW='0' and AS ='0' else +-- "ZZZZZZZZZZZZZZZZ"; + + IDE_W <= IDE_W_S; + IDE_R <= IDE_R_S; + IDE_CS(0)<= not(A(12)); + IDE_CS(1)<= not(A(13)); + IDE_A(0) <= A(9); + IDE_A(1) <= A(10); + IDE_A(2) <= A(11); + ROM_B <= "00"; + ROM_OE <= ROM_OE_S; + + +-- DTACK <= DTACK_S when --TRANSFER_IN_PROGRES ='1' or +-- AUTOCONFIG_IN_PROGRES ='1' +-- else 'Z'; + + DTACK <= 'Z'; end Behavioral; diff --git a/Logic/LAN_IDE/LAN_IDE_CP.vm6 b/Logic/LAN_IDE/LAN_IDE_CP.vm6 new file mode 100644 index 0000000..9147c94 --- /dev/null +++ b/Logic/LAN_IDE/LAN_IDE_CP.vm6 @@ -0,0 +1,4110 @@ +NDS Database: version P.68d + +NDS_INFO | xc9500xl | 95144XL144TQ | XC95144XL-10-TQ144 + +DEVICE | 95144XL | 95144XL144TQ | + +NETWORK | LAN_IDE_CP | 0 | 0 | 16391 + +INPUT_INSTANCE | 0 | 0 | NULL | RESET_IBUF | LAN_IDE_CP_COPY_0_COPY_0 | 16 | 1 | 2 +INPUT_NODE_TYPE | 0 | 5 | II_IN +NODE | RESET | 5041 | PI | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE +OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX +NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX +OUTPUT_NODE_TYPE | 9 | 5 | II_FSRINV +NODE | FSR-IO_0 | 4911 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 9 | 5 | II_FSRINV + +INPUT_INSTANCE | 0 | 0 | NULL | RW_IBUF | LAN_IDE_CP_COPY_0_COPY_0 | 16 | 1 | 1 +INPUT_NODE_TYPE | 0 | 5 | II_IN +NODE | RW | 5043 | PI | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE +OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX +NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX + +INPUT_INSTANCE | 0 | 0 | NULL | A_1_IBUF | LAN_IDE_CP_COPY_0_COPY_0 | 16 | 1 | 1 +INPUT_NODE_TYPE | 0 | 5 | II_IN +NODE | A<1> | 5047 | PI | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE +OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX +NODE | A_1_IBUF | 4929 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_1_IBUF | 0 | 5 | II_IMUX + +INPUT_INSTANCE | 0 | 0 | NULL | A_2_IBUF | LAN_IDE_CP_COPY_0_COPY_0 | 16 | 1 | 1 +INPUT_NODE_TYPE | 0 | 5 | II_IN +NODE | A<2> | 5050 | PI | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE +OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX +NODE | A_2_IBUF | 4932 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX + +INPUT_INSTANCE | 0 | 0 | NULL | A_5_IBUF | LAN_IDE_CP_COPY_0_COPY_0 | 16 | 1 | 1 +INPUT_NODE_TYPE | 0 | 5 | II_IN +NODE | A<5> | 5045 | PI | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE +OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX +NODE | A_5_IBUF | 4927 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX + +INPUT_INSTANCE | 0 | 0 | NULL | A_6_IBUF | LAN_IDE_CP_COPY_0_COPY_0 | 16 | 1 | 1 +INPUT_NODE_TYPE | 0 | 5 | II_IN +NODE | A<6> | 5048 | PI | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE +OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX +NODE | A_6_IBUF | 4930 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_6_IBUF | 0 | 5 | II_IMUX + +INPUT_INSTANCE | 0 | 0 | NULL | A_3_IBUF | LAN_IDE_CP_COPY_0_COPY_0 | 16 | 1 | 1 +INPUT_NODE_TYPE | 0 | 5 | II_IN +NODE | A<3> | 5049 | PI | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE +OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX +NODE | A_3_IBUF | 4931 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX + +INPUT_INSTANCE | 0 | 0 | NULL | AS_IBUF | LAN_IDE_CP_COPY_0_COPY_0 | 16 | 1 | 1 +INPUT_NODE_TYPE | 0 | 5 | II_IN +NODE | AS | 5044 | PI | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE +OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX +NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX + +INPUT_INSTANCE | 0 | 0 | NULL | A_4_IBUF | LAN_IDE_CP_COPY_0_COPY_0 | 16 | 1 | 1 +INPUT_NODE_TYPE | 0 | 5 | II_IN +NODE | A<4> | 5046 | PI | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE +OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX +NODE | A_4_IBUF | 4928 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_4_IBUF | 0 | 5 | II_IMUX + +MACROCELL_INSTANCE | NoOpt+Inv+PrldLow+PinTrst+OptxMapped | D<13>_BUFR.MC | LAN_IDE_CP_COPY_0_COPY_0 | 2155889936 | 17 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_5_IBUF | 4927 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_1_IBUF | 4929 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_6_IBUF | 4930 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_6_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_3_IBUF | 4931 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_2_IBUF | 4932 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<1> | 4938 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<1>.Q | AUTO_CONFIG_DONE<1> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<2> | 4939 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<2>.Q | AUTO_CONFIG_DONE<2> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | autoconfig | 4957 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.Q | autoconfig | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_4_IBUF | 4928 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_4_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<0> | 4937 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<0>.Q | AUTO_CONFIG_DONE<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | Dout1<1>.UIM | 4913 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | HPART_CREATED_2.Q | _12_ | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | ide/ide_CLKF.UIM | 5040 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ide/ide_CLKF.Q | ide/ide_CLKF | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | EXP17_.EXP | 5371 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | EXP17_.EXP | EXP17_ | 4 | 0 | MC_EXPORT +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | N1$BUF2.EXP | 5372 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | N1$BUF2.EXP | N1$BUF2 | 4 | 0 | MC_EXPORT +OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM +NODE | D<13>_BUFR | 5335 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | Dout1<1>.Q | D<13>_BUFR.MC | 1 | 0 | MC_UIM + +SIGNAL_INSTANCE | Dout1<1>.SI | D<13>_BUFR.MC | 0 | 17 | 3 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_5_IBUF | 4927 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_1_IBUF | 4929 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_6_IBUF | 4930 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_6_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_3_IBUF | 4931 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_2_IBUF | 4932 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<1> | 4938 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<1>.Q | AUTO_CONFIG_DONE<1> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<2> | 4939 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<2>.Q | AUTO_CONFIG_DONE<2> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | autoconfig | 4957 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.Q | autoconfig | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_4_IBUF | 4928 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_4_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<0> | 4937 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<0>.Q | AUTO_CONFIG_DONE<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | Dout1<1>.UIM | 4913 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | HPART_CREATED_2.Q | _12_ | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | ide/ide_CLKF.UIM | 5040 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ide/ide_CLKF.Q | ide/ide_CLKF | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | EXP17_.EXP | 5371 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | EXP17_.EXP | EXP17_ | 4 | 0 | MC_EXPORT +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | N1$BUF2.EXP | 5372 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | N1$BUF2.EXP | N1$BUF2 | 4 | 0 | MC_EXPORT +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | Dout1<1>.D1 | 5069 | ? | 0 | 4096 | D<13>_BUFR.MC | NULL | NULL | Dout1<1>.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | Dout1<1>.D2 | 5070 | ? | 0 | 4096 | D<13>_BUFR.MC | NULL | NULL | Dout1<1>.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 1 | IV_TRUE | EXP17_.EXP +SPPTERM | 1 | IV_TRUE | N1$BUF2.EXP +SPPTERM | 3 | IV_TRUE | RESET_IBUF | IV_FALSE | Dout1<1>.UIM | IV_TRUE | AS_IBUF +SPPTERM | 3 | IV_TRUE | RESET_IBUF | IV_FALSE | Dout1<1>.UIM | IV_FALSE | autoconfig +SPPTERM | 11 | IV_TRUE | RESET_IBUF | IV_TRUE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_TRUE | A_4_IBUF | IV_FALSE | A_6_IBUF | IV_TRUE | A_3_IBUF | IV_TRUE | A_2_IBUF | IV_TRUE | AUTO_CONFIG_DONE<0> | IV_FALSE | AUTO_CONFIG_DONE<1> | IV_TRUE | autoconfig +SPPTERM | 11 | IV_TRUE | RESET_IBUF | IV_TRUE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_TRUE | A_1_IBUF | IV_FALSE | A_6_IBUF | IV_FALSE | A_3_IBUF | IV_FALSE | A_2_IBUF | IV_TRUE | AUTO_CONFIG_DONE<1> | IV_FALSE | AUTO_CONFIG_DONE<2> | IV_TRUE | autoconfig +OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF +SIGNAL | NODE | Dout1<1>.CLKF | 5071 | ? | 0 | 4096 | D<13>_BUFR.MC | NULL | NULL | Dout1<1>.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 1 | IV_TRUE | ide/ide_CLKF.UIM + +SRFF_INSTANCE | Dout1<1>.REG | D<13>_BUFR.MC | 0 | 2 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | Dout1<1>.D | 5068 | ? | 0 | 0 | D<13>_BUFR.MC | NULL | NULL | Dout1<1>.XOR | 0 | 7 | ALU_F +INPUT_NODE_TYPE | 1 | 8 | SRFF_C +SIGNAL | NODE | Dout1<1>.CLKF | 5071 | ? | 0 | 4096 | D<13>_BUFR.MC | NULL | NULL | Dout1<1>.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 1 | IV_TRUE | ide/ide_CLKF.UIM +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | Dout1<1>.Q | 5074 | ? | 0 | 0 | D<13>_BUFR.MC | NULL | NULL | Dout1<1>.REG | 0 | 8 | SRFF_Q + +INPUT_INSTANCE | 0 | 0 | NULL | AUTOBOOT_OFF_IBUF | LAN_IDE_CP_COPY_0_COPY_0 | 16 | 1 | 1 +INPUT_NODE_TYPE | 0 | 5 | II_IN +NODE | AUTOBOOT_OFF | 5055 | PI | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE +OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX +NODE | AUTOBOOT_OFF_IBUF | 4953 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AUTOBOOT_OFF_IBUF | 0 | 5 | II_IMUX + +MACROCELL_INSTANCE | NoOpt+Inv+PrldLow+PinTrst+OptxMapped | D<12>_BUFR.MC | LAN_IDE_CP_COPY_0_COPY_0 | 2155889936 | 17 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_5_IBUF | 4927 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_4_IBUF | 4928 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_4_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_1_IBUF | 4929 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_3_IBUF | 4931 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_2_IBUF | 4932 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<1> | 4938 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<1>.Q | AUTO_CONFIG_DONE<1> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<2> | 4939 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<2>.Q | AUTO_CONFIG_DONE<2> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | autoconfig | 4957 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.Q | autoconfig | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_6_IBUF | 4930 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_6_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<0> | 4937 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<0>.Q | AUTO_CONFIG_DONE<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTOBOOT_OFF_IBUF | 4953 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AUTOBOOT_OFF_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | IDE_CS_1_OBUF.EXP | 5353 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_CS_1_OBUF.EXP | IDE_CS_1_OBUF | 4 | 0 | MC_EXPORT +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | ide/ide_CLKF.UIM | 5040 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ide/ide_CLKF.Q | ide/ide_CLKF | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | EXP14_.EXP | 5357 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | EXP14_.EXP | EXP14_ | 4 | 0 | MC_EXPORT +OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM +NODE | D<12>_BUFR | 5319 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | Dout1<0>.Q | D<12>_BUFR.MC | 1 | 0 | MC_UIM + +SIGNAL_INSTANCE | Dout1<0>.SI | D<12>_BUFR.MC | 0 | 17 | 3 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_5_IBUF | 4927 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_4_IBUF | 4928 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_4_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_1_IBUF | 4929 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_3_IBUF | 4931 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_2_IBUF | 4932 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<1> | 4938 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<1>.Q | AUTO_CONFIG_DONE<1> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<2> | 4939 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<2>.Q | AUTO_CONFIG_DONE<2> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | autoconfig | 4957 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.Q | autoconfig | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_6_IBUF | 4930 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_6_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<0> | 4937 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<0>.Q | AUTO_CONFIG_DONE<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTOBOOT_OFF_IBUF | 4953 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AUTOBOOT_OFF_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | IDE_CS_1_OBUF.EXP | 5353 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_CS_1_OBUF.EXP | IDE_CS_1_OBUF | 4 | 0 | MC_EXPORT +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | ide/ide_CLKF.UIM | 5040 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ide/ide_CLKF.Q | ide/ide_CLKF | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | EXP14_.EXP | 5357 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | EXP14_.EXP | EXP14_ | 4 | 0 | MC_EXPORT +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | Dout1<0>.D1 | 5076 | ? | 0 | 4096 | D<12>_BUFR.MC | NULL | NULL | Dout1<0>.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | Dout1<0>.D2 | 5077 | ? | 0 | 4096 | D<12>_BUFR.MC | NULL | NULL | Dout1<0>.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 1 | IV_TRUE | IDE_CS_1_OBUF.EXP +SPPTERM | 1 | IV_TRUE | EXP14_.EXP +SPPTERM | 10 | IV_TRUE | RESET_IBUF | IV_TRUE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_4_IBUF | IV_TRUE | A_1_IBUF | IV_FALSE | A_6_IBUF | IV_FALSE | A_3_IBUF | IV_TRUE | A_2_IBUF | IV_FALSE | AUTO_CONFIG_DONE<0> | IV_TRUE | autoconfig +SPPTERM | 11 | IV_TRUE | RESET_IBUF | IV_TRUE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_TRUE | A_4_IBUF | IV_FALSE | A_6_IBUF | IV_TRUE | A_3_IBUF | IV_FALSE | A_2_IBUF | IV_TRUE | AUTO_CONFIG_DONE<0> | IV_FALSE | AUTO_CONFIG_DONE<1> | IV_TRUE | autoconfig +SPPTERM | 11 | IV_TRUE | RESET_IBUF | IV_TRUE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_FALSE | A_4_IBUF | IV_FALSE | A_1_IBUF | IV_FALSE | A_3_IBUF | IV_FALSE | A_2_IBUF | IV_TRUE | AUTO_CONFIG_DONE<1> | IV_FALSE | AUTO_CONFIG_DONE<2> | IV_TRUE | autoconfig +SPPTERM | 11 | IV_TRUE | RESET_IBUF | IV_TRUE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_FALSE | A_4_IBUF | IV_FALSE | A_1_IBUF | IV_FALSE | A_3_IBUF | IV_FALSE | A_2_IBUF | IV_FALSE | AUTO_CONFIG_DONE<1> | IV_TRUE | AUTOBOOT_OFF_IBUF | IV_TRUE | autoconfig +OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF +SIGNAL | NODE | Dout1<0>.CLKF | 5078 | ? | 0 | 4096 | D<12>_BUFR.MC | NULL | NULL | Dout1<0>.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 1 | IV_TRUE | ide/ide_CLKF.UIM + +SRFF_INSTANCE | Dout1<0>.REG | D<12>_BUFR.MC | 0 | 2 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | Dout1<0>.D | 5075 | ? | 0 | 0 | D<12>_BUFR.MC | NULL | NULL | Dout1<0>.XOR | 0 | 7 | ALU_F +INPUT_NODE_TYPE | 1 | 8 | SRFF_C +SIGNAL | NODE | Dout1<0>.CLKF | 5078 | ? | 0 | 4096 | D<12>_BUFR.MC | NULL | NULL | Dout1<0>.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 1 | IV_TRUE | ide/ide_CLKF.UIM +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | Dout1<0>.Q | 5081 | ? | 0 | 0 | D<12>_BUFR.MC | NULL | NULL | Dout1<0>.REG | 0 | 8 | SRFF_Q + +MACROCELL_INSTANCE | NoOpt+Inv+PrldLow+PinTrst+OptxMapped | D<14>_BUFR.MC | LAN_IDE_CP_COPY_0_COPY_0 | 2155889936 | 16 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_5_IBUF | 4927 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_4_IBUF | 4928 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_4_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_6_IBUF | 4930 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_6_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_3_IBUF | 4931 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_2_IBUF | 4932 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<0> | 4937 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<0>.Q | AUTO_CONFIG_DONE<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<1> | 4938 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<1>.Q | AUTO_CONFIG_DONE<1> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<2> | 4939 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<2>.Q | AUTO_CONFIG_DONE<2> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | autoconfig | 4957 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.Q | autoconfig | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_1_IBUF | 4929 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | EXP15_.EXP | 5366 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | EXP15_.EXP | EXP15_ | 4 | 0 | MC_EXPORT +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | ide/ide_CLKF.UIM | 5040 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ide/ide_CLKF.Q | ide/ide_CLKF | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | EXP18_.EXP | 5373 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | EXP18_.EXP | EXP18_ | 4 | 0 | MC_EXPORT +OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM +NODE | D<14>_BUFR | 5327 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | Dout1<2>.Q | D<14>_BUFR.MC | 1 | 0 | MC_UIM + +SIGNAL_INSTANCE | Dout1<2>.SI | D<14>_BUFR.MC | 0 | 16 | 3 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_5_IBUF | 4927 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_4_IBUF | 4928 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_4_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_6_IBUF | 4930 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_6_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_3_IBUF | 4931 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_2_IBUF | 4932 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<0> | 4937 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<0>.Q | AUTO_CONFIG_DONE<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<1> | 4938 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<1>.Q | AUTO_CONFIG_DONE<1> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<2> | 4939 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<2>.Q | AUTO_CONFIG_DONE<2> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | autoconfig | 4957 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.Q | autoconfig | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_1_IBUF | 4929 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | EXP15_.EXP | 5366 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | EXP15_.EXP | EXP15_ | 4 | 0 | MC_EXPORT +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | ide/ide_CLKF.UIM | 5040 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ide/ide_CLKF.Q | ide/ide_CLKF | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | EXP18_.EXP | 5373 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | EXP18_.EXP | EXP18_ | 4 | 0 | MC_EXPORT +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | Dout1<2>.D1 | 5083 | ? | 0 | 4096 | D<14>_BUFR.MC | NULL | NULL | Dout1<2>.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | Dout1<2>.D2 | 5084 | ? | 0 | 4096 | D<14>_BUFR.MC | NULL | NULL | Dout1<2>.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 1 | IV_TRUE | EXP15_.EXP +SPPTERM | 1 | IV_TRUE | EXP18_.EXP +SPPTERM | 10 | IV_TRUE | RESET_IBUF | IV_TRUE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_FALSE | A_4_IBUF | IV_TRUE | A_1_IBUF | IV_FALSE | A_3_IBUF | IV_FALSE | A_2_IBUF | IV_FALSE | AUTO_CONFIG_DONE<1> | IV_TRUE | autoconfig +SPPTERM | 10 | IV_TRUE | RESET_IBUF | IV_TRUE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_FALSE | A_4_IBUF | IV_TRUE | A_1_IBUF | IV_FALSE | A_3_IBUF | IV_FALSE | A_2_IBUF | IV_FALSE | AUTO_CONFIG_DONE<2> | IV_TRUE | autoconfig +SPPTERM | 11 | IV_TRUE | RESET_IBUF | IV_TRUE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_TRUE | A_1_IBUF | IV_FALSE | A_6_IBUF | IV_FALSE | A_3_IBUF | IV_TRUE | A_2_IBUF | IV_TRUE | AUTO_CONFIG_DONE<0> | IV_FALSE | AUTO_CONFIG_DONE<1> | IV_TRUE | autoconfig +SPPTERM | 12 | IV_TRUE | RESET_IBUF | IV_TRUE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_FALSE | A_4_IBUF | IV_FALSE | A_6_IBUF | IV_FALSE | A_3_IBUF | IV_TRUE | A_2_IBUF | IV_TRUE | AUTO_CONFIG_DONE<0> | IV_TRUE | AUTO_CONFIG_DONE<1> | IV_FALSE | AUTO_CONFIG_DONE<2> | IV_TRUE | autoconfig +OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF +SIGNAL | NODE | Dout1<2>.CLKF | 5085 | ? | 0 | 4096 | D<14>_BUFR.MC | NULL | NULL | Dout1<2>.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 1 | IV_TRUE | ide/ide_CLKF.UIM + +SRFF_INSTANCE | Dout1<2>.REG | D<14>_BUFR.MC | 0 | 2 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | Dout1<2>.D | 5082 | ? | 0 | 0 | D<14>_BUFR.MC | NULL | NULL | Dout1<2>.XOR | 0 | 7 | ALU_F +INPUT_NODE_TYPE | 1 | 8 | SRFF_C +SIGNAL | NODE | Dout1<2>.CLKF | 5085 | ? | 0 | 4096 | D<14>_BUFR.MC | NULL | NULL | Dout1<2>.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 1 | IV_TRUE | ide/ide_CLKF.UIM +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | Dout1<2>.Q | 5088 | ? | 0 | 0 | D<14>_BUFR.MC | NULL | NULL | Dout1<2>.REG | 0 | 8 | SRFF_Q + +MACROCELL_INSTANCE | NoOpt+Inv+PrldLow+PinTrst+OptxMapped | D<15>_BUFR.MC | LAN_IDE_CP_COPY_0_COPY_0 | 2155889936 | 14 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_5_IBUF | 4927 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_1_IBUF | 4929 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_6_IBUF | 4930 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_6_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_3_IBUF | 4931 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_2_IBUF | 4932 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<1> | 4938 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<1>.Q | AUTO_CONFIG_DONE<1> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | autoconfig | 4957 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.Q | autoconfig | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | Dout1<3>.UIM | 4922 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | HPART_CREATED_3.Q | _13_ | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | EXP22_.EXP | 5384 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | EXP22_.EXP | EXP22_ | 4 | 0 | MC_EXPORT +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | EXP23_.EXP | 5385 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | EXP23_.EXP | EXP23_ | 4 | 0 | MC_EXPORT +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | ide/ide_CLKF.UIM | 5040 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ide/ide_CLKF.Q | ide/ide_CLKF | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM +NODE | D<15>_BUFR | 5343 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | Dout1<3>.Q | D<15>_BUFR.MC | 1 | 0 | MC_UIM + +SIGNAL_INSTANCE | Dout1<3>.SI | D<15>_BUFR.MC | 0 | 14 | 3 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_5_IBUF | 4927 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_1_IBUF | 4929 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_6_IBUF | 4930 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_6_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_3_IBUF | 4931 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_2_IBUF | 4932 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<1> | 4938 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<1>.Q | AUTO_CONFIG_DONE<1> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | autoconfig | 4957 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.Q | autoconfig | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | Dout1<3>.UIM | 4922 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | HPART_CREATED_3.Q | _13_ | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | EXP22_.EXP | 5384 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | EXP22_.EXP | EXP22_ | 4 | 0 | MC_EXPORT +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | EXP23_.EXP | 5385 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | EXP23_.EXP | EXP23_ | 4 | 0 | MC_EXPORT +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | ide/ide_CLKF.UIM | 5040 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ide/ide_CLKF.Q | ide/ide_CLKF | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | Dout1<3>.D1 | 5090 | ? | 0 | 4096 | D<15>_BUFR.MC | NULL | NULL | Dout1<3>.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | Dout1<3>.D2 | 5091 | ? | 0 | 4096 | D<15>_BUFR.MC | NULL | NULL | Dout1<3>.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 1 | IV_TRUE | EXP22_.EXP +SPPTERM | 1 | IV_TRUE | EXP23_.EXP +SPPTERM | 3 | IV_TRUE | RESET_IBUF | IV_FALSE | Dout1<3>.UIM | IV_FALSE | RW_IBUF +SPPTERM | 3 | IV_TRUE | RESET_IBUF | IV_FALSE | Dout1<3>.UIM | IV_TRUE | AS_IBUF +SPPTERM | 3 | IV_TRUE | RESET_IBUF | IV_FALSE | Dout1<3>.UIM | IV_FALSE | autoconfig +SPPTERM | 10 | IV_TRUE | RESET_IBUF | IV_TRUE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_TRUE | A_1_IBUF | IV_FALSE | A_6_IBUF | IV_FALSE | A_3_IBUF | IV_FALSE | A_2_IBUF | IV_FALSE | AUTO_CONFIG_DONE<1> | IV_TRUE | autoconfig +OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF +SIGNAL | NODE | Dout1<3>.CLKF | 5092 | ? | 0 | 4096 | D<15>_BUFR.MC | NULL | NULL | Dout1<3>.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 1 | IV_TRUE | ide/ide_CLKF.UIM + +SRFF_INSTANCE | Dout1<3>.REG | D<15>_BUFR.MC | 0 | 2 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | Dout1<3>.D | 5089 | ? | 0 | 0 | D<15>_BUFR.MC | NULL | NULL | Dout1<3>.XOR | 0 | 7 | ALU_F +INPUT_NODE_TYPE | 1 | 8 | SRFF_C +SIGNAL | NODE | Dout1<3>.CLKF | 5092 | ? | 0 | 4096 | D<15>_BUFR.MC | NULL | NULL | Dout1<3>.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 1 | IV_TRUE | ide/ide_CLKF.UIM +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | Dout1<3>.Q | 5095 | ? | 0 | 0 | D<15>_BUFR.MC | NULL | NULL | Dout1<3>.REG | 0 | 8 | SRFF_Q + +INPUT_INSTANCE | 0 | 0 | NULL | UDS_IBUF | LAN_IDE_CP_COPY_0_COPY_0 | 16 | 1 | 1 +INPUT_NODE_TYPE | 0 | 5 | II_IN +NODE | UDS | 5042 | PI | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE +OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX +NODE | UDS_IBUF | 4924 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | UDS_IBUF | 0 | 5 | II_IMUX + +INPUT_INSTANCE | 0 | 0 | NULL | A_23_IBUF | LAN_IDE_CP_COPY_0_COPY_0 | 16 | 1 | 1 +INPUT_NODE_TYPE | 0 | 5 | II_IN +NODE | A<23> | 5051 | PI | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE +OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX +NODE | A_23_IBUF | 4933 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_23_IBUF | 0 | 5 | II_IMUX + +INPUT_INSTANCE | 0 | 0 | NULL | A_22_IBUF | LAN_IDE_CP_COPY_0_COPY_0 | 16 | 1 | 1 +INPUT_NODE_TYPE | 0 | 5 | II_IN +NODE | A<22> | 5052 | PI | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE +OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX +NODE | A_22_IBUF | 4934 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_22_IBUF | 0 | 5 | II_IMUX + +INPUT_INSTANCE | 0 | 0 | NULL | A_21_IBUF | LAN_IDE_CP_COPY_0_COPY_0 | 16 | 1 | 1 +INPUT_NODE_TYPE | 0 | 5 | II_IN +NODE | A<21> | 5053 | PI | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE +OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX +NODE | A_21_IBUF | 4935 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_21_IBUF | 0 | 5 | II_IMUX + +INPUT_INSTANCE | 0 | 0 | NULL | A_19_IBUF | LAN_IDE_CP_COPY_0_COPY_0 | 16 | 1 | 1 +INPUT_NODE_TYPE | 0 | 5 | II_IN +NODE | A<19> | 5054 | PI | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE +OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX +NODE | A_19_IBUF | 4936 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_19_IBUF | 0 | 5 | II_IMUX + +MACROCELL_INSTANCE | PrldLow+OptxMapped | AUTO_CONFIG_DONE<0> | LAN_IDE_CP_COPY_0_COPY_0 | 2155873280 | 3 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE_CYCLE<0> | 4940 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE_CYCLE<0>.Q | AUTO_CONFIG_DONE_CYCLE<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | FSR-IO_0 | 4911 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 9 | 5 | II_FSRINV +OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM +NODE | AUTO_CONFIG_DONE<0> | 4937 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<0>.Q | AUTO_CONFIG_DONE<0> | 1 | 0 | MC_UIM + +SIGNAL_INSTANCE | AUTO_CONFIG_DONE<0>.SI | AUTO_CONFIG_DONE<0> | 0 | 2 | 3 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE_CYCLE<0> | 4940 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE_CYCLE<0>.Q | AUTO_CONFIG_DONE_CYCLE<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | AUTO_CONFIG_DONE<0>.D1 | 5097 | ? | 0 | 4096 | AUTO_CONFIG_DONE<0> | NULL | NULL | AUTO_CONFIG_DONE<0>.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | AUTO_CONFIG_DONE<0>.D2 | 5098 | ? | 0 | 4096 | AUTO_CONFIG_DONE<0> | NULL | NULL | AUTO_CONFIG_DONE<0>.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 1 | IV_TRUE | AUTO_CONFIG_DONE_CYCLE<0> +OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF +SIGNAL | NODE | AUTO_CONFIG_DONE<0>.CLKF | 5099 | ? | 0 | 4096 | AUTO_CONFIG_DONE<0> | NULL | NULL | AUTO_CONFIG_DONE<0>.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 1 | IV_TRUE | AS_IBUF + +SRFF_INSTANCE | AUTO_CONFIG_DONE<0>.REG | AUTO_CONFIG_DONE<0> | 0 | 3 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | AUTO_CONFIG_DONE<0>.D | 5096 | ? | 0 | 0 | AUTO_CONFIG_DONE<0> | NULL | NULL | AUTO_CONFIG_DONE<0>.XOR | 0 | 7 | ALU_F +INPUT_NODE_TYPE | 1 | 8 | SRFF_C +SIGNAL | NODE | AUTO_CONFIG_DONE<0>.CLKF | 5099 | ? | 0 | 4096 | AUTO_CONFIG_DONE<0> | NULL | NULL | AUTO_CONFIG_DONE<0>.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 1 | IV_TRUE | AS_IBUF +INPUT_NODE_TYPE | 3 | 8 | SRFF_R +NODE | FSR-IO_0 | 4911 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 9 | 5 | II_FSRINV +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | AUTO_CONFIG_DONE<0>.Q | 5100 | ? | 0 | 0 | AUTO_CONFIG_DONE<0> | NULL | NULL | AUTO_CONFIG_DONE<0>.REG | 0 | 8 | SRFF_Q + +MACROCELL_INSTANCE | PrldLow+OptxMapped | AUTO_CONFIG_DONE<1> | LAN_IDE_CP_COPY_0_COPY_0 | 2155873280 | 3 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE_CYCLE<1> | 4941 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE_CYCLE<1>.Q | AUTO_CONFIG_DONE_CYCLE<1> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | FSR-IO_0 | 4911 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 9 | 5 | II_FSRINV +OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM +NODE | AUTO_CONFIG_DONE<1> | 4938 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<1>.Q | AUTO_CONFIG_DONE<1> | 1 | 0 | MC_UIM + +SIGNAL_INSTANCE | AUTO_CONFIG_DONE<1>.SI | AUTO_CONFIG_DONE<1> | 0 | 2 | 3 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE_CYCLE<1> | 4941 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE_CYCLE<1>.Q | AUTO_CONFIG_DONE_CYCLE<1> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | AUTO_CONFIG_DONE<1>.D1 | 5102 | ? | 0 | 4096 | AUTO_CONFIG_DONE<1> | NULL | NULL | AUTO_CONFIG_DONE<1>.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | AUTO_CONFIG_DONE<1>.D2 | 5103 | ? | 0 | 4096 | AUTO_CONFIG_DONE<1> | NULL | NULL | AUTO_CONFIG_DONE<1>.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 1 | IV_TRUE | AUTO_CONFIG_DONE_CYCLE<1> +OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF +SIGNAL | NODE | AUTO_CONFIG_DONE<1>.CLKF | 5104 | ? | 0 | 4096 | AUTO_CONFIG_DONE<1> | NULL | NULL | AUTO_CONFIG_DONE<1>.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 1 | IV_TRUE | AS_IBUF + +SRFF_INSTANCE | AUTO_CONFIG_DONE<1>.REG | AUTO_CONFIG_DONE<1> | 0 | 3 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | AUTO_CONFIG_DONE<1>.D | 5101 | ? | 0 | 0 | AUTO_CONFIG_DONE<1> | NULL | NULL | AUTO_CONFIG_DONE<1>.XOR | 0 | 7 | ALU_F +INPUT_NODE_TYPE | 1 | 8 | SRFF_C +SIGNAL | NODE | AUTO_CONFIG_DONE<1>.CLKF | 5104 | ? | 0 | 4096 | AUTO_CONFIG_DONE<1> | NULL | NULL | AUTO_CONFIG_DONE<1>.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 1 | IV_TRUE | AS_IBUF +INPUT_NODE_TYPE | 3 | 8 | SRFF_R +NODE | FSR-IO_0 | 4911 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 9 | 5 | II_FSRINV +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | AUTO_CONFIG_DONE<1>.Q | 5105 | ? | 0 | 0 | AUTO_CONFIG_DONE<1> | NULL | NULL | AUTO_CONFIG_DONE<1>.REG | 0 | 8 | SRFF_Q + +MACROCELL_INSTANCE | PrldLow+OptxMapped | AUTO_CONFIG_DONE<2> | LAN_IDE_CP_COPY_0_COPY_0 | 2155873280 | 3 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE_CYCLE<2> | 4942 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE_CYCLE<2>.Q | AUTO_CONFIG_DONE_CYCLE<2> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | FSR-IO_0 | 4911 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 9 | 5 | II_FSRINV +OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM +NODE | AUTO_CONFIG_DONE<2> | 4939 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<2>.Q | AUTO_CONFIG_DONE<2> | 1 | 0 | MC_UIM + +SIGNAL_INSTANCE | AUTO_CONFIG_DONE<2>.SI | AUTO_CONFIG_DONE<2> | 0 | 2 | 3 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE_CYCLE<2> | 4942 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE_CYCLE<2>.Q | AUTO_CONFIG_DONE_CYCLE<2> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | AUTO_CONFIG_DONE<2>.D1 | 5107 | ? | 0 | 4096 | AUTO_CONFIG_DONE<2> | NULL | NULL | AUTO_CONFIG_DONE<2>.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | AUTO_CONFIG_DONE<2>.D2 | 5108 | ? | 0 | 4096 | AUTO_CONFIG_DONE<2> | NULL | NULL | AUTO_CONFIG_DONE<2>.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 1 | IV_TRUE | AUTO_CONFIG_DONE_CYCLE<2> +OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF +SIGNAL | NODE | AUTO_CONFIG_DONE<2>.CLKF | 5109 | ? | 0 | 4096 | AUTO_CONFIG_DONE<2> | NULL | NULL | AUTO_CONFIG_DONE<2>.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 1 | IV_TRUE | AS_IBUF + +SRFF_INSTANCE | AUTO_CONFIG_DONE<2>.REG | AUTO_CONFIG_DONE<2> | 0 | 3 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | AUTO_CONFIG_DONE<2>.D | 5106 | ? | 0 | 0 | AUTO_CONFIG_DONE<2> | NULL | NULL | AUTO_CONFIG_DONE<2>.XOR | 0 | 7 | ALU_F +INPUT_NODE_TYPE | 1 | 8 | SRFF_C +SIGNAL | NODE | AUTO_CONFIG_DONE<2>.CLKF | 5109 | ? | 0 | 4096 | AUTO_CONFIG_DONE<2> | NULL | NULL | AUTO_CONFIG_DONE<2>.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 1 | IV_TRUE | AS_IBUF +INPUT_NODE_TYPE | 3 | 8 | SRFF_R +NODE | FSR-IO_0 | 4911 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 9 | 5 | II_FSRINV +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | AUTO_CONFIG_DONE<2>.Q | 5110 | ? | 0 | 0 | AUTO_CONFIG_DONE<2> | NULL | NULL | AUTO_CONFIG_DONE<2>.REG | 0 | 8 | SRFF_Q + +MACROCELL_INSTANCE | PrldLow+OptxMapped | AUTO_CONFIG_DONE_CYCLE<0> | LAN_IDE_CP_COPY_0_COPY_0 | 2155873280 | 17 | 2 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE_CYCLE<0> | 4940 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE_CYCLE<0>.Q | AUTO_CONFIG_DONE_CYCLE<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | UDS_IBUF | 4924 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | UDS_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_5_IBUF | 4927 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_4_IBUF | 4928 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_4_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_1_IBUF | 4929 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_6_IBUF | 4930 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_6_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_3_IBUF | 4931 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<0> | 4937 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<0>.Q | AUTO_CONFIG_DONE<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | autoconfig | 4957 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.Q | autoconfig | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | ide/ide_CLKF.UIM | 5040 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ide/ide_CLKF.Q | ide/ide_CLKF | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_2_IBUF | 4932 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<1> | 4938 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<1>.Q | AUTO_CONFIG_DONE<1> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | IDE_BASEADR<7> | 4951 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_BASEADR<7>.Q | IDE_BASEADR<7> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | N4 | 4967 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | N4 | 0 | 5 | II_IMUX +OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM +NODE | AUTO_CONFIG_DONE_CYCLE<0> | 4940 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE_CYCLE<0>.Q | AUTO_CONFIG_DONE_CYCLE<0> | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 4 | 0 | MC_EXPORT +NODE | AUTO_CONFIG_DONE_CYCLE<0>.EXP | 5368 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE_CYCLE<0>.EXP | AUTO_CONFIG_DONE_CYCLE<0> | 4 | 0 | MC_EXPORT + +SIGNAL_INSTANCE | AUTO_CONFIG_DONE_CYCLE<0>.SI | AUTO_CONFIG_DONE_CYCLE<0> | 0 | 17 | 4 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE_CYCLE<0> | 4940 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE_CYCLE<0>.Q | AUTO_CONFIG_DONE_CYCLE<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | UDS_IBUF | 4924 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | UDS_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_5_IBUF | 4927 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_4_IBUF | 4928 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_4_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_1_IBUF | 4929 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_6_IBUF | 4930 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_6_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_3_IBUF | 4931 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<0> | 4937 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<0>.Q | AUTO_CONFIG_DONE<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | autoconfig | 4957 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.Q | autoconfig | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | ide/ide_CLKF.UIM | 5040 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ide/ide_CLKF.Q | ide/ide_CLKF | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_2_IBUF | 4932 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<1> | 4938 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<1>.Q | AUTO_CONFIG_DONE<1> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | IDE_BASEADR<7> | 4951 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_BASEADR<7>.Q | IDE_BASEADR<7> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | N4 | 4967 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | N4 | 0 | 5 | II_IMUX +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | AUTO_CONFIG_DONE_CYCLE<0>.D1 | 5112 | ? | 0 | 4096 | AUTO_CONFIG_DONE_CYCLE<0> | NULL | NULL | AUTO_CONFIG_DONE_CYCLE<0>.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | AUTO_CONFIG_DONE_CYCLE<0>.D2 | 5113 | ? | 0 | 4096 | AUTO_CONFIG_DONE_CYCLE<0> | NULL | NULL | AUTO_CONFIG_DONE_CYCLE<0>.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 2 | IV_TRUE | RESET_IBUF | IV_TRUE | AUTO_CONFIG_DONE_CYCLE<0> +SPPTERM | 11 | IV_TRUE | RESET_IBUF | IV_FALSE | UDS_IBUF | IV_FALSE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_FALSE | A_4_IBUF | IV_FALSE | A_1_IBUF | IV_TRUE | A_6_IBUF | IV_TRUE | A_3_IBUF | IV_FALSE | AUTO_CONFIG_DONE<0> | IV_TRUE | autoconfig +OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF +SIGNAL | NODE | AUTO_CONFIG_DONE_CYCLE<0>.CLKF | 5114 | ? | 0 | 4096 | AUTO_CONFIG_DONE_CYCLE<0> | NULL | NULL | AUTO_CONFIG_DONE_CYCLE<0>.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 1 | IV_TRUE | ide/ide_CLKF.UIM +OUTPUT_NODE_TYPE | 7 | 9 | MC_SI_EXPORT +SIGNAL | NODE | AUTO_CONFIG_DONE_CYCLE<0>.EXP | 5360 | ? | 0 | 0 | AUTO_CONFIG_DONE_CYCLE<0> | NULL | NULL | AUTO_CONFIG_DONE_CYCLE<0>.SI | 7 | 9 | MC_SI_EXPORT +SPPTERM | 15 | IV_TRUE | RESET_IBUF | IV_FALSE | UDS_IBUF | IV_FALSE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_FALSE | A_4_IBUF | IV_FALSE | A_1_IBUF | IV_TRUE | A_6_IBUF | IV_TRUE | A_3_IBUF | IV_FALSE | A_2_IBUF | IV_TRUE | AUTO_CONFIG_DONE<0> | IV_FALSE | AUTO_CONFIG_DONE<1> | IV_TRUE | IDE_BASEADR<7> | IV_TRUE | autoconfig | IV_FALSE | N4 + +SRFF_INSTANCE | AUTO_CONFIG_DONE_CYCLE<0>.REG | AUTO_CONFIG_DONE_CYCLE<0> | 0 | 2 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | AUTO_CONFIG_DONE_CYCLE<0>.D | 5111 | ? | 0 | 0 | AUTO_CONFIG_DONE_CYCLE<0> | NULL | NULL | AUTO_CONFIG_DONE_CYCLE<0>.XOR | 0 | 7 | ALU_F +INPUT_NODE_TYPE | 1 | 8 | SRFF_C +SIGNAL | NODE | AUTO_CONFIG_DONE_CYCLE<0>.CLKF | 5114 | ? | 0 | 4096 | AUTO_CONFIG_DONE_CYCLE<0> | NULL | NULL | AUTO_CONFIG_DONE_CYCLE<0>.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 1 | IV_TRUE | ide/ide_CLKF.UIM +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | AUTO_CONFIG_DONE_CYCLE<0>.Q | 5115 | ? | 0 | 0 | AUTO_CONFIG_DONE_CYCLE<0> | NULL | NULL | AUTO_CONFIG_DONE_CYCLE<0>.REG | 0 | 8 | SRFF_Q + +MACROCELL_INSTANCE | PrldLow+OptxMapped | AUTO_CONFIG_DONE_CYCLE<1> | LAN_IDE_CP_COPY_0_COPY_0 | 2155873280 | 14 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE_CYCLE<1> | 4941 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE_CYCLE<1>.Q | AUTO_CONFIG_DONE_CYCLE<1> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | UDS_IBUF | 4924 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | UDS_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_5_IBUF | 4927 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_4_IBUF | 4928 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_4_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_1_IBUF | 4929 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_6_IBUF | 4930 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_6_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_3_IBUF | 4931 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<0> | 4937 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<0>.Q | AUTO_CONFIG_DONE<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<1> | 4938 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<1>.Q | AUTO_CONFIG_DONE<1> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | autoconfig | 4957 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.Q | autoconfig | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | ide/ide_CLKF.UIM | 5040 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ide/ide_CLKF.Q | ide/ide_CLKF | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM +NODE | AUTO_CONFIG_DONE_CYCLE<1> | 4941 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE_CYCLE<1>.Q | AUTO_CONFIG_DONE_CYCLE<1> | 1 | 0 | MC_UIM + +SIGNAL_INSTANCE | AUTO_CONFIG_DONE_CYCLE<1>.SI | AUTO_CONFIG_DONE_CYCLE<1> | 0 | 14 | 3 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE_CYCLE<1> | 4941 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE_CYCLE<1>.Q | AUTO_CONFIG_DONE_CYCLE<1> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | UDS_IBUF | 4924 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | UDS_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_5_IBUF | 4927 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_4_IBUF | 4928 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_4_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_1_IBUF | 4929 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_6_IBUF | 4930 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_6_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_3_IBUF | 4931 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<0> | 4937 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<0>.Q | AUTO_CONFIG_DONE<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<1> | 4938 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<1>.Q | AUTO_CONFIG_DONE<1> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | autoconfig | 4957 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.Q | autoconfig | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | ide/ide_CLKF.UIM | 5040 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ide/ide_CLKF.Q | ide/ide_CLKF | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | AUTO_CONFIG_DONE_CYCLE<1>.D1 | 5117 | ? | 0 | 4096 | AUTO_CONFIG_DONE_CYCLE<1> | NULL | NULL | AUTO_CONFIG_DONE_CYCLE<1>.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | AUTO_CONFIG_DONE_CYCLE<1>.D2 | 5118 | ? | 0 | 4096 | AUTO_CONFIG_DONE_CYCLE<1> | NULL | NULL | AUTO_CONFIG_DONE_CYCLE<1>.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 2 | IV_TRUE | RESET_IBUF | IV_TRUE | AUTO_CONFIG_DONE_CYCLE<1> +SPPTERM | 12 | IV_TRUE | RESET_IBUF | IV_FALSE | UDS_IBUF | IV_FALSE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_FALSE | A_4_IBUF | IV_FALSE | A_1_IBUF | IV_TRUE | A_6_IBUF | IV_TRUE | A_3_IBUF | IV_TRUE | AUTO_CONFIG_DONE<0> | IV_FALSE | AUTO_CONFIG_DONE<1> | IV_TRUE | autoconfig +OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF +SIGNAL | NODE | AUTO_CONFIG_DONE_CYCLE<1>.CLKF | 5119 | ? | 0 | 4096 | AUTO_CONFIG_DONE_CYCLE<1> | NULL | NULL | AUTO_CONFIG_DONE_CYCLE<1>.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 1 | IV_TRUE | ide/ide_CLKF.UIM + +SRFF_INSTANCE | AUTO_CONFIG_DONE_CYCLE<1>.REG | AUTO_CONFIG_DONE_CYCLE<1> | 0 | 2 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | AUTO_CONFIG_DONE_CYCLE<1>.D | 5116 | ? | 0 | 0 | AUTO_CONFIG_DONE_CYCLE<1> | NULL | NULL | AUTO_CONFIG_DONE_CYCLE<1>.XOR | 0 | 7 | ALU_F +INPUT_NODE_TYPE | 1 | 8 | SRFF_C +SIGNAL | NODE | AUTO_CONFIG_DONE_CYCLE<1>.CLKF | 5119 | ? | 0 | 4096 | AUTO_CONFIG_DONE_CYCLE<1> | NULL | NULL | AUTO_CONFIG_DONE_CYCLE<1>.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 1 | IV_TRUE | ide/ide_CLKF.UIM +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | AUTO_CONFIG_DONE_CYCLE<1>.Q | 5120 | ? | 0 | 0 | AUTO_CONFIG_DONE_CYCLE<1> | NULL | NULL | AUTO_CONFIG_DONE_CYCLE<1>.REG | 0 | 8 | SRFF_Q + +MACROCELL_INSTANCE | PrldLow+OptxMapped | AUTO_CONFIG_DONE_CYCLE<2> | LAN_IDE_CP_COPY_0_COPY_0 | 2155873280 | 15 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE_CYCLE<2> | 4942 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE_CYCLE<2>.Q | AUTO_CONFIG_DONE_CYCLE<2> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | UDS_IBUF | 4924 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | UDS_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_5_IBUF | 4927 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_4_IBUF | 4928 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_4_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_1_IBUF | 4929 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_6_IBUF | 4930 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_6_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_3_IBUF | 4931 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<0> | 4937 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<0>.Q | AUTO_CONFIG_DONE<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<1> | 4938 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<1>.Q | AUTO_CONFIG_DONE<1> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<2> | 4939 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<2>.Q | AUTO_CONFIG_DONE<2> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | autoconfig | 4957 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.Q | autoconfig | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | ide/ide_CLKF.UIM | 5040 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ide/ide_CLKF.Q | ide/ide_CLKF | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM +NODE | AUTO_CONFIG_DONE_CYCLE<2> | 4942 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE_CYCLE<2>.Q | AUTO_CONFIG_DONE_CYCLE<2> | 1 | 0 | MC_UIM + +SIGNAL_INSTANCE | AUTO_CONFIG_DONE_CYCLE<2>.SI | AUTO_CONFIG_DONE_CYCLE<2> | 0 | 15 | 3 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE_CYCLE<2> | 4942 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE_CYCLE<2>.Q | AUTO_CONFIG_DONE_CYCLE<2> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | UDS_IBUF | 4924 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | UDS_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_5_IBUF | 4927 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_4_IBUF | 4928 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_4_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_1_IBUF | 4929 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_6_IBUF | 4930 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_6_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_3_IBUF | 4931 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<0> | 4937 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<0>.Q | AUTO_CONFIG_DONE<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<1> | 4938 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<1>.Q | AUTO_CONFIG_DONE<1> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<2> | 4939 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<2>.Q | AUTO_CONFIG_DONE<2> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | autoconfig | 4957 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.Q | autoconfig | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | ide/ide_CLKF.UIM | 5040 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ide/ide_CLKF.Q | ide/ide_CLKF | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | AUTO_CONFIG_DONE_CYCLE<2>.D1 | 5122 | ? | 0 | 4096 | AUTO_CONFIG_DONE_CYCLE<2> | NULL | NULL | AUTO_CONFIG_DONE_CYCLE<2>.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | AUTO_CONFIG_DONE_CYCLE<2>.D2 | 5123 | ? | 0 | 4096 | AUTO_CONFIG_DONE_CYCLE<2> | NULL | NULL | AUTO_CONFIG_DONE_CYCLE<2>.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 2 | IV_TRUE | RESET_IBUF | IV_TRUE | AUTO_CONFIG_DONE_CYCLE<2> +SPPTERM | 13 | IV_TRUE | RESET_IBUF | IV_FALSE | UDS_IBUF | IV_FALSE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_FALSE | A_4_IBUF | IV_FALSE | A_1_IBUF | IV_TRUE | A_6_IBUF | IV_TRUE | A_3_IBUF | IV_TRUE | AUTO_CONFIG_DONE<0> | IV_TRUE | AUTO_CONFIG_DONE<1> | IV_FALSE | AUTO_CONFIG_DONE<2> | IV_TRUE | autoconfig +OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF +SIGNAL | NODE | AUTO_CONFIG_DONE_CYCLE<2>.CLKF | 5124 | ? | 0 | 4096 | AUTO_CONFIG_DONE_CYCLE<2> | NULL | NULL | AUTO_CONFIG_DONE_CYCLE<2>.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 1 | IV_TRUE | ide/ide_CLKF.UIM + +SRFF_INSTANCE | AUTO_CONFIG_DONE_CYCLE<2>.REG | AUTO_CONFIG_DONE_CYCLE<2> | 0 | 2 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | AUTO_CONFIG_DONE_CYCLE<2>.D | 5121 | ? | 0 | 0 | AUTO_CONFIG_DONE_CYCLE<2> | NULL | NULL | AUTO_CONFIG_DONE_CYCLE<2>.XOR | 0 | 7 | ALU_F +INPUT_NODE_TYPE | 1 | 8 | SRFF_C +SIGNAL | NODE | AUTO_CONFIG_DONE_CYCLE<2>.CLKF | 5124 | ? | 0 | 4096 | AUTO_CONFIG_DONE_CYCLE<2> | NULL | NULL | AUTO_CONFIG_DONE_CYCLE<2>.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 1 | IV_TRUE | ide/ide_CLKF.UIM +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | AUTO_CONFIG_DONE_CYCLE<2>.Q | 5125 | ? | 0 | 0 | AUTO_CONFIG_DONE_CYCLE<2> | NULL | NULL | AUTO_CONFIG_DONE_CYCLE<2>.REG | 0 | 8 | SRFF_Q + +INPUT_INSTANCE | 0 | 0 | NULL | N5 | LAN_IDE_CP_COPY_0_COPY_0 | 16 | 1 | 1 +INPUT_NODE_TYPE | 0 | 5 | II_IN +NODE | D<8> | 5021 | PIPO | 0 | 64 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | D<8> | 0 | 6 | OI_OUT +OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX +NODE | N5 | 4960 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | N5 | 0 | 5 | II_IMUX + +MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped | IDE_BASEADR<0> | LAN_IDE_CP_COPY_0_COPY_0 | 2155877376 | 16 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | IDE_BASEADR<0> | 4943 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_BASEADR<0>.Q | IDE_BASEADR<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | UDS_IBUF | 4924 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | UDS_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_5_IBUF | 4927 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_4_IBUF | 4928 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_4_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_1_IBUF | 4929 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_6_IBUF | 4930 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_6_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_3_IBUF | 4931 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_2_IBUF | 4932 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<0> | 4937 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<0>.Q | AUTO_CONFIG_DONE<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<1> | 4938 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<1>.Q | AUTO_CONFIG_DONE<1> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | autoconfig | 4957 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.Q | autoconfig | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | N5 | 4960 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | N5 | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | ide/ide_CLKF.UIM | 5040 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ide/ide_CLKF.Q | ide/ide_CLKF | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM +NODE | IDE_BASEADR<0> | 4943 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_BASEADR<0>.Q | IDE_BASEADR<0> | 1 | 0 | MC_UIM + +SIGNAL_INSTANCE | IDE_BASEADR<0>.SI | IDE_BASEADR<0> | 0 | 16 | 3 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | IDE_BASEADR<0> | 4943 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_BASEADR<0>.Q | IDE_BASEADR<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | UDS_IBUF | 4924 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | UDS_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_5_IBUF | 4927 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_4_IBUF | 4928 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_4_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_1_IBUF | 4929 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_6_IBUF | 4930 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_6_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_3_IBUF | 4931 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_2_IBUF | 4932 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<0> | 4937 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<0>.Q | AUTO_CONFIG_DONE<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<1> | 4938 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<1>.Q | AUTO_CONFIG_DONE<1> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | autoconfig | 4957 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.Q | autoconfig | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | N5 | 4960 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | N5 | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | ide/ide_CLKF.UIM | 5040 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ide/ide_CLKF.Q | ide/ide_CLKF | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | IDE_BASEADR<0>.D1 | 5127 | ? | 0 | 4096 | IDE_BASEADR<0> | NULL | NULL | IDE_BASEADR<0>.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | IDE_BASEADR<0>.D2 | 5128 | ? | 0 | 4096 | IDE_BASEADR<0> | NULL | NULL | IDE_BASEADR<0>.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 2 | IV_FALSE | RESET_IBUF | IV_FALSE | IDE_BASEADR<0> +SPPTERM | 14 | IV_FALSE | UDS_IBUF | IV_FALSE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_FALSE | A_4_IBUF | IV_FALSE | A_1_IBUF | IV_TRUE | A_6_IBUF | IV_TRUE | A_3_IBUF | IV_FALSE | A_2_IBUF | IV_TRUE | AUTO_CONFIG_DONE<0> | IV_FALSE | AUTO_CONFIG_DONE<1> | IV_FALSE | IDE_BASEADR<0> | IV_TRUE | autoconfig | IV_TRUE | N5 +SPPTERM | 15 | IV_TRUE | RESET_IBUF | IV_FALSE | UDS_IBUF | IV_FALSE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_FALSE | A_4_IBUF | IV_FALSE | A_1_IBUF | IV_TRUE | A_6_IBUF | IV_TRUE | A_3_IBUF | IV_FALSE | A_2_IBUF | IV_TRUE | AUTO_CONFIG_DONE<0> | IV_FALSE | AUTO_CONFIG_DONE<1> | IV_TRUE | IDE_BASEADR<0> | IV_TRUE | autoconfig | IV_FALSE | N5 +OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF +SIGNAL | NODE | IDE_BASEADR<0>.CLKF | 5129 | ? | 0 | 4096 | IDE_BASEADR<0> | NULL | NULL | IDE_BASEADR<0>.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 1 | IV_TRUE | ide/ide_CLKF.UIM + +SRFF_INSTANCE | IDE_BASEADR<0>.REG | IDE_BASEADR<0> | 0 | 2 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | IDE_BASEADR<0>.D | 5126 | ? | 0 | 0 | IDE_BASEADR<0> | NULL | NULL | IDE_BASEADR<0>.XOR | 0 | 7 | ALU_F +INPUT_NODE_TYPE | 1 | 8 | SRFF_C +SIGNAL | NODE | IDE_BASEADR<0>.CLKF | 5129 | ? | 0 | 4096 | IDE_BASEADR<0> | NULL | NULL | IDE_BASEADR<0>.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 1 | IV_TRUE | ide/ide_CLKF.UIM +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | IDE_BASEADR<0>.Q | 5130 | ? | 0 | 0 | IDE_BASEADR<0> | NULL | NULL | IDE_BASEADR<0>.REG | 0 | 8 | SRFF_Q + +INPUT_INSTANCE | 0 | 0 | NULL | N11 | LAN_IDE_CP_COPY_0_COPY_0 | 16 | 1 | 1 +INPUT_NODE_TYPE | 0 | 5 | II_IN +NODE | D<12> | 5014 | PIPO | 0 | 64 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | D<12> | 0 | 6 | OI_OUT +OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX +NODE | N11 | 4964 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | N11 | 0 | 5 | II_IMUX + +MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped | IDE_BASEADR<4> | LAN_IDE_CP_COPY_0_COPY_0 | 2155877376 | 16 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | IDE_BASEADR<4> | 4944 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_BASEADR<4>.Q | IDE_BASEADR<4> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | UDS_IBUF | 4924 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | UDS_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_5_IBUF | 4927 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_4_IBUF | 4928 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_4_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_1_IBUF | 4929 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_6_IBUF | 4930 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_6_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_3_IBUF | 4931 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_2_IBUF | 4932 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<0> | 4937 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<0>.Q | AUTO_CONFIG_DONE<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<1> | 4938 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<1>.Q | AUTO_CONFIG_DONE<1> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | autoconfig | 4957 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.Q | autoconfig | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | N11 | 4964 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | N11 | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | ide/ide_CLKF.UIM | 5040 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ide/ide_CLKF.Q | ide/ide_CLKF | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM +NODE | IDE_BASEADR<4> | 4944 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_BASEADR<4>.Q | IDE_BASEADR<4> | 1 | 0 | MC_UIM + +SIGNAL_INSTANCE | IDE_BASEADR<4>.SI | IDE_BASEADR<4> | 0 | 16 | 3 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | IDE_BASEADR<4> | 4944 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_BASEADR<4>.Q | IDE_BASEADR<4> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | UDS_IBUF | 4924 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | UDS_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_5_IBUF | 4927 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_4_IBUF | 4928 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_4_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_1_IBUF | 4929 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_6_IBUF | 4930 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_6_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_3_IBUF | 4931 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_2_IBUF | 4932 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<0> | 4937 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<0>.Q | AUTO_CONFIG_DONE<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<1> | 4938 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<1>.Q | AUTO_CONFIG_DONE<1> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | autoconfig | 4957 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.Q | autoconfig | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | N11 | 4964 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | N11 | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | ide/ide_CLKF.UIM | 5040 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ide/ide_CLKF.Q | ide/ide_CLKF | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | IDE_BASEADR<4>.D1 | 5132 | ? | 0 | 4096 | IDE_BASEADR<4> | NULL | NULL | IDE_BASEADR<4>.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | IDE_BASEADR<4>.D2 | 5133 | ? | 0 | 4096 | IDE_BASEADR<4> | NULL | NULL | IDE_BASEADR<4>.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 2 | IV_FALSE | RESET_IBUF | IV_FALSE | IDE_BASEADR<4> +SPPTERM | 14 | IV_FALSE | UDS_IBUF | IV_FALSE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_FALSE | A_4_IBUF | IV_FALSE | A_1_IBUF | IV_TRUE | A_6_IBUF | IV_TRUE | A_3_IBUF | IV_FALSE | A_2_IBUF | IV_TRUE | AUTO_CONFIG_DONE<0> | IV_FALSE | AUTO_CONFIG_DONE<1> | IV_FALSE | IDE_BASEADR<4> | IV_TRUE | autoconfig | IV_TRUE | N11 +SPPTERM | 15 | IV_TRUE | RESET_IBUF | IV_FALSE | UDS_IBUF | IV_FALSE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_FALSE | A_4_IBUF | IV_FALSE | A_1_IBUF | IV_TRUE | A_6_IBUF | IV_TRUE | A_3_IBUF | IV_FALSE | A_2_IBUF | IV_TRUE | AUTO_CONFIG_DONE<0> | IV_FALSE | AUTO_CONFIG_DONE<1> | IV_TRUE | IDE_BASEADR<4> | IV_TRUE | autoconfig | IV_FALSE | N11 +OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF +SIGNAL | NODE | IDE_BASEADR<4>.CLKF | 5134 | ? | 0 | 4096 | IDE_BASEADR<4> | NULL | NULL | IDE_BASEADR<4>.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 1 | IV_TRUE | ide/ide_CLKF.UIM + +SRFF_INSTANCE | IDE_BASEADR<4>.REG | IDE_BASEADR<4> | 0 | 2 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | IDE_BASEADR<4>.D | 5131 | ? | 0 | 0 | IDE_BASEADR<4> | NULL | NULL | IDE_BASEADR<4>.XOR | 0 | 7 | ALU_F +INPUT_NODE_TYPE | 1 | 8 | SRFF_C +SIGNAL | NODE | IDE_BASEADR<4>.CLKF | 5134 | ? | 0 | 4096 | IDE_BASEADR<4> | NULL | NULL | IDE_BASEADR<4>.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 1 | IV_TRUE | ide/ide_CLKF.UIM +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | IDE_BASEADR<4>.Q | 5135 | ? | 0 | 0 | IDE_BASEADR<4> | NULL | NULL | IDE_BASEADR<4>.REG | 0 | 8 | SRFF_Q + +INPUT_INSTANCE | 0 | 0 | NULL | N2 | LAN_IDE_CP_COPY_0_COPY_0 | 16 | 1 | 1 +INPUT_NODE_TYPE | 0 | 5 | II_IN +NODE | D<13> | 5013 | PIPO | 0 | 64 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | D<13> | 0 | 6 | OI_OUT +OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX +NODE | N2 | 4965 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | N2 | 0 | 5 | II_IMUX + +MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped | IDE_BASEADR<5> | LAN_IDE_CP_COPY_0_COPY_0 | 2155877376 | 16 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | IDE_BASEADR<5> | 4945 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_BASEADR<5>.Q | IDE_BASEADR<5> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | UDS_IBUF | 4924 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | UDS_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_5_IBUF | 4927 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_4_IBUF | 4928 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_4_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_1_IBUF | 4929 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_6_IBUF | 4930 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_6_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_3_IBUF | 4931 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_2_IBUF | 4932 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<0> | 4937 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<0>.Q | AUTO_CONFIG_DONE<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<1> | 4938 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<1>.Q | AUTO_CONFIG_DONE<1> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | autoconfig | 4957 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.Q | autoconfig | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | N2 | 4965 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | N2 | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | ide/ide_CLKF.UIM | 5040 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ide/ide_CLKF.Q | ide/ide_CLKF | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM +NODE | IDE_BASEADR<5> | 4945 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_BASEADR<5>.Q | IDE_BASEADR<5> | 1 | 0 | MC_UIM + +SIGNAL_INSTANCE | IDE_BASEADR<5>.SI | IDE_BASEADR<5> | 0 | 16 | 3 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | IDE_BASEADR<5> | 4945 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_BASEADR<5>.Q | IDE_BASEADR<5> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | UDS_IBUF | 4924 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | UDS_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_5_IBUF | 4927 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_4_IBUF | 4928 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_4_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_1_IBUF | 4929 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_6_IBUF | 4930 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_6_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_3_IBUF | 4931 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_2_IBUF | 4932 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<0> | 4937 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<0>.Q | AUTO_CONFIG_DONE<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<1> | 4938 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<1>.Q | AUTO_CONFIG_DONE<1> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | autoconfig | 4957 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.Q | autoconfig | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | N2 | 4965 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | N2 | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | ide/ide_CLKF.UIM | 5040 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ide/ide_CLKF.Q | ide/ide_CLKF | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | IDE_BASEADR<5>.D1 | 5137 | ? | 0 | 4096 | IDE_BASEADR<5> | NULL | NULL | IDE_BASEADR<5>.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | IDE_BASEADR<5>.D2 | 5138 | ? | 0 | 4096 | IDE_BASEADR<5> | NULL | NULL | IDE_BASEADR<5>.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 2 | IV_FALSE | RESET_IBUF | IV_FALSE | IDE_BASEADR<5> +SPPTERM | 14 | IV_FALSE | UDS_IBUF | IV_FALSE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_FALSE | A_4_IBUF | IV_FALSE | A_1_IBUF | IV_TRUE | A_6_IBUF | IV_TRUE | A_3_IBUF | IV_FALSE | A_2_IBUF | IV_TRUE | AUTO_CONFIG_DONE<0> | IV_FALSE | AUTO_CONFIG_DONE<1> | IV_FALSE | IDE_BASEADR<5> | IV_TRUE | autoconfig | IV_TRUE | N2 +SPPTERM | 15 | IV_TRUE | RESET_IBUF | IV_FALSE | UDS_IBUF | IV_FALSE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_FALSE | A_4_IBUF | IV_FALSE | A_1_IBUF | IV_TRUE | A_6_IBUF | IV_TRUE | A_3_IBUF | IV_FALSE | A_2_IBUF | IV_TRUE | AUTO_CONFIG_DONE<0> | IV_FALSE | AUTO_CONFIG_DONE<1> | IV_TRUE | IDE_BASEADR<5> | IV_TRUE | autoconfig | IV_FALSE | N2 +OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF +SIGNAL | NODE | IDE_BASEADR<5>.CLKF | 5139 | ? | 0 | 4096 | IDE_BASEADR<5> | NULL | NULL | IDE_BASEADR<5>.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 1 | IV_TRUE | ide/ide_CLKF.UIM + +SRFF_INSTANCE | IDE_BASEADR<5>.REG | IDE_BASEADR<5> | 0 | 2 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | IDE_BASEADR<5>.D | 5136 | ? | 0 | 0 | IDE_BASEADR<5> | NULL | NULL | IDE_BASEADR<5>.XOR | 0 | 7 | ALU_F +INPUT_NODE_TYPE | 1 | 8 | SRFF_C +SIGNAL | NODE | IDE_BASEADR<5>.CLKF | 5139 | ? | 0 | 4096 | IDE_BASEADR<5> | NULL | NULL | IDE_BASEADR<5>.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 1 | IV_TRUE | ide/ide_CLKF.UIM +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | IDE_BASEADR<5>.Q | 5140 | ? | 0 | 0 | IDE_BASEADR<5> | NULL | NULL | IDE_BASEADR<5>.REG | 0 | 8 | SRFF_Q + +MACROCELL_INSTANCE | Inv+PrldLow+OptxMapped | IDE_ENABLE | LAN_IDE_CP_COPY_0_COPY_0 | 2155873536 | 6 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | IDE_ENABLE | 4946 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_ENABLE.Q | IDE_ENABLE | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | ide | 4958 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ide.Q | ide | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | ide/ide_CLKF.UIM | 5040 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ide/ide_CLKF.Q | ide/ide_CLKF | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM +NODE | IDE_ENABLE | 4946 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_ENABLE.Q | IDE_ENABLE | 1 | 0 | MC_UIM + +SIGNAL_INSTANCE | IDE_ENABLE.SI | IDE_ENABLE | 0 | 6 | 3 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | IDE_ENABLE | 4946 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_ENABLE.Q | IDE_ENABLE | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | ide | 4958 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ide.Q | ide | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | ide/ide_CLKF.UIM | 5040 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ide/ide_CLKF.Q | ide/ide_CLKF | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | IDE_ENABLE.D1 | 5142 | ? | 0 | 4096 | IDE_ENABLE | NULL | NULL | IDE_ENABLE.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | IDE_ENABLE.D2 | 5143 | ? | 0 | 4096 | IDE_ENABLE | NULL | NULL | IDE_ENABLE.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 2 | IV_TRUE | RESET_IBUF | IV_FALSE | IDE_ENABLE +SPPTERM | 4 | IV_TRUE | RESET_IBUF | IV_FALSE | RW_IBUF | IV_FALSE | AS_IBUF | IV_TRUE | ide +OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF +SIGNAL | NODE | IDE_ENABLE.CLKF | 5144 | ? | 0 | 4096 | IDE_ENABLE | NULL | NULL | IDE_ENABLE.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 1 | IV_TRUE | ide/ide_CLKF.UIM + +SRFF_INSTANCE | IDE_ENABLE.REG | IDE_ENABLE | 0 | 2 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | IDE_ENABLE.D | 5141 | ? | 0 | 0 | IDE_ENABLE | NULL | NULL | IDE_ENABLE.XOR | 0 | 7 | ALU_F +INPUT_NODE_TYPE | 1 | 8 | SRFF_C +SIGNAL | NODE | IDE_ENABLE.CLKF | 5144 | ? | 0 | 4096 | IDE_ENABLE | NULL | NULL | IDE_ENABLE.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 1 | IV_TRUE | ide/ide_CLKF.UIM +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | IDE_ENABLE.Q | 5145 | ? | 0 | 0 | IDE_ENABLE | NULL | NULL | IDE_ENABLE.REG | 0 | 8 | SRFF_Q + +INPUT_INSTANCE | 0 | 0 | NULL | N6 | LAN_IDE_CP_COPY_0_COPY_0 | 16 | 1 | 1 +INPUT_NODE_TYPE | 0 | 5 | II_IN +NODE | D<9> | 5020 | PIPO | 0 | 64 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | D<9> | 0 | 6 | OI_OUT +OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX +NODE | N6 | 4961 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | N6 | 0 | 5 | II_IMUX + +MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped | IDE_BASEADR<1> | LAN_IDE_CP_COPY_0_COPY_0 | 2155877376 | 16 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | IDE_BASEADR<1> | 4947 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_BASEADR<1>.Q | IDE_BASEADR<1> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | UDS_IBUF | 4924 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | UDS_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_5_IBUF | 4927 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_4_IBUF | 4928 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_4_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_1_IBUF | 4929 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_6_IBUF | 4930 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_6_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_3_IBUF | 4931 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_2_IBUF | 4932 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<0> | 4937 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<0>.Q | AUTO_CONFIG_DONE<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<1> | 4938 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<1>.Q | AUTO_CONFIG_DONE<1> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | autoconfig | 4957 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.Q | autoconfig | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | N6 | 4961 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | N6 | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | ide/ide_CLKF.UIM | 5040 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ide/ide_CLKF.Q | ide/ide_CLKF | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM +NODE | IDE_BASEADR<1> | 4947 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_BASEADR<1>.Q | IDE_BASEADR<1> | 1 | 0 | MC_UIM + +SIGNAL_INSTANCE | IDE_BASEADR<1>.SI | IDE_BASEADR<1> | 0 | 16 | 3 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | IDE_BASEADR<1> | 4947 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_BASEADR<1>.Q | IDE_BASEADR<1> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | UDS_IBUF | 4924 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | UDS_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_5_IBUF | 4927 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_4_IBUF | 4928 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_4_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_1_IBUF | 4929 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_6_IBUF | 4930 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_6_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_3_IBUF | 4931 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_2_IBUF | 4932 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<0> | 4937 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<0>.Q | AUTO_CONFIG_DONE<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<1> | 4938 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<1>.Q | AUTO_CONFIG_DONE<1> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | autoconfig | 4957 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.Q | autoconfig | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | N6 | 4961 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | N6 | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | ide/ide_CLKF.UIM | 5040 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ide/ide_CLKF.Q | ide/ide_CLKF | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | IDE_BASEADR<1>.D1 | 5147 | ? | 0 | 4096 | IDE_BASEADR<1> | NULL | NULL | IDE_BASEADR<1>.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | IDE_BASEADR<1>.D2 | 5148 | ? | 0 | 4096 | IDE_BASEADR<1> | NULL | NULL | IDE_BASEADR<1>.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 2 | IV_FALSE | RESET_IBUF | IV_FALSE | IDE_BASEADR<1> +SPPTERM | 14 | IV_FALSE | UDS_IBUF | IV_FALSE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_FALSE | A_4_IBUF | IV_FALSE | A_1_IBUF | IV_TRUE | A_6_IBUF | IV_TRUE | A_3_IBUF | IV_FALSE | A_2_IBUF | IV_TRUE | AUTO_CONFIG_DONE<0> | IV_FALSE | AUTO_CONFIG_DONE<1> | IV_FALSE | IDE_BASEADR<1> | IV_TRUE | autoconfig | IV_TRUE | N6 +SPPTERM | 15 | IV_TRUE | RESET_IBUF | IV_FALSE | UDS_IBUF | IV_FALSE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_FALSE | A_4_IBUF | IV_FALSE | A_1_IBUF | IV_TRUE | A_6_IBUF | IV_TRUE | A_3_IBUF | IV_FALSE | A_2_IBUF | IV_TRUE | AUTO_CONFIG_DONE<0> | IV_FALSE | AUTO_CONFIG_DONE<1> | IV_TRUE | IDE_BASEADR<1> | IV_TRUE | autoconfig | IV_FALSE | N6 +OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF +SIGNAL | NODE | IDE_BASEADR<1>.CLKF | 5149 | ? | 0 | 4096 | IDE_BASEADR<1> | NULL | NULL | IDE_BASEADR<1>.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 1 | IV_TRUE | ide/ide_CLKF.UIM + +SRFF_INSTANCE | IDE_BASEADR<1>.REG | IDE_BASEADR<1> | 0 | 2 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | IDE_BASEADR<1>.D | 5146 | ? | 0 | 0 | IDE_BASEADR<1> | NULL | NULL | IDE_BASEADR<1>.XOR | 0 | 7 | ALU_F +INPUT_NODE_TYPE | 1 | 8 | SRFF_C +SIGNAL | NODE | IDE_BASEADR<1>.CLKF | 5149 | ? | 0 | 4096 | IDE_BASEADR<1> | NULL | NULL | IDE_BASEADR<1>.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 1 | IV_TRUE | ide/ide_CLKF.UIM +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | IDE_BASEADR<1>.Q | 5150 | ? | 0 | 0 | IDE_BASEADR<1> | NULL | NULL | IDE_BASEADR<1>.REG | 0 | 8 | SRFF_Q + +INPUT_INSTANCE | 0 | 0 | NULL | N7 | LAN_IDE_CP_COPY_0_COPY_0 | 16 | 1 | 1 +INPUT_NODE_TYPE | 0 | 5 | II_IN +NODE | D<10> | 5031 | PIPO | 0 | 64 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | D<10> | 0 | 6 | OI_OUT +OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX +NODE | N7 | 4962 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | N7 | 0 | 5 | II_IMUX + +MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped | IDE_BASEADR<2> | LAN_IDE_CP_COPY_0_COPY_0 | 2155877376 | 16 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | IDE_BASEADR<2> | 4948 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_BASEADR<2>.Q | IDE_BASEADR<2> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | UDS_IBUF | 4924 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | UDS_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_5_IBUF | 4927 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_4_IBUF | 4928 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_4_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_1_IBUF | 4929 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_6_IBUF | 4930 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_6_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_3_IBUF | 4931 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_2_IBUF | 4932 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<0> | 4937 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<0>.Q | AUTO_CONFIG_DONE<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<1> | 4938 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<1>.Q | AUTO_CONFIG_DONE<1> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | autoconfig | 4957 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.Q | autoconfig | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | N7 | 4962 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | N7 | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | ide/ide_CLKF.UIM | 5040 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ide/ide_CLKF.Q | ide/ide_CLKF | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM +NODE | IDE_BASEADR<2> | 4948 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_BASEADR<2>.Q | IDE_BASEADR<2> | 1 | 0 | MC_UIM + +SIGNAL_INSTANCE | IDE_BASEADR<2>.SI | IDE_BASEADR<2> | 0 | 16 | 3 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | IDE_BASEADR<2> | 4948 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_BASEADR<2>.Q | IDE_BASEADR<2> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | UDS_IBUF | 4924 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | UDS_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_5_IBUF | 4927 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_4_IBUF | 4928 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_4_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_1_IBUF | 4929 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_6_IBUF | 4930 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_6_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_3_IBUF | 4931 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_2_IBUF | 4932 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<0> | 4937 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<0>.Q | AUTO_CONFIG_DONE<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<1> | 4938 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<1>.Q | AUTO_CONFIG_DONE<1> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | autoconfig | 4957 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.Q | autoconfig | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | N7 | 4962 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | N7 | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | ide/ide_CLKF.UIM | 5040 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ide/ide_CLKF.Q | ide/ide_CLKF | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | IDE_BASEADR<2>.D1 | 5152 | ? | 0 | 4096 | IDE_BASEADR<2> | NULL | NULL | IDE_BASEADR<2>.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | IDE_BASEADR<2>.D2 | 5153 | ? | 0 | 4096 | IDE_BASEADR<2> | NULL | NULL | IDE_BASEADR<2>.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 2 | IV_FALSE | RESET_IBUF | IV_FALSE | IDE_BASEADR<2> +SPPTERM | 14 | IV_FALSE | UDS_IBUF | IV_FALSE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_FALSE | A_4_IBUF | IV_FALSE | A_1_IBUF | IV_TRUE | A_6_IBUF | IV_TRUE | A_3_IBUF | IV_FALSE | A_2_IBUF | IV_TRUE | AUTO_CONFIG_DONE<0> | IV_FALSE | AUTO_CONFIG_DONE<1> | IV_FALSE | IDE_BASEADR<2> | IV_TRUE | autoconfig | IV_TRUE | N7 +SPPTERM | 15 | IV_TRUE | RESET_IBUF | IV_FALSE | UDS_IBUF | IV_FALSE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_FALSE | A_4_IBUF | IV_FALSE | A_1_IBUF | IV_TRUE | A_6_IBUF | IV_TRUE | A_3_IBUF | IV_FALSE | A_2_IBUF | IV_TRUE | AUTO_CONFIG_DONE<0> | IV_FALSE | AUTO_CONFIG_DONE<1> | IV_TRUE | IDE_BASEADR<2> | IV_TRUE | autoconfig | IV_FALSE | N7 +OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF +SIGNAL | NODE | IDE_BASEADR<2>.CLKF | 5154 | ? | 0 | 4096 | IDE_BASEADR<2> | NULL | NULL | IDE_BASEADR<2>.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 1 | IV_TRUE | ide/ide_CLKF.UIM + +SRFF_INSTANCE | IDE_BASEADR<2>.REG | IDE_BASEADR<2> | 0 | 2 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | IDE_BASEADR<2>.D | 5151 | ? | 0 | 0 | IDE_BASEADR<2> | NULL | NULL | IDE_BASEADR<2>.XOR | 0 | 7 | ALU_F +INPUT_NODE_TYPE | 1 | 8 | SRFF_C +SIGNAL | NODE | IDE_BASEADR<2>.CLKF | 5154 | ? | 0 | 4096 | IDE_BASEADR<2> | NULL | NULL | IDE_BASEADR<2>.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 1 | IV_TRUE | ide/ide_CLKF.UIM +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | IDE_BASEADR<2>.Q | 5155 | ? | 0 | 0 | IDE_BASEADR<2> | NULL | NULL | IDE_BASEADR<2>.REG | 0 | 8 | SRFF_Q + +INPUT_INSTANCE | 0 | 0 | NULL | N0 | LAN_IDE_CP_COPY_0_COPY_0 | 16 | 1 | 1 +INPUT_NODE_TYPE | 0 | 5 | II_IN +NODE | D<11> | 5030 | PIPO | 0 | 64 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | D<11> | 0 | 6 | OI_OUT +OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX +NODE | N0 | 4963 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | N0 | 0 | 5 | II_IMUX + +MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped | IDE_BASEADR<3> | LAN_IDE_CP_COPY_0_COPY_0 | 2155877376 | 16 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | IDE_BASEADR<3> | 4949 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_BASEADR<3>.Q | IDE_BASEADR<3> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | UDS_IBUF | 4924 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | UDS_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_5_IBUF | 4927 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_4_IBUF | 4928 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_4_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_1_IBUF | 4929 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_6_IBUF | 4930 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_6_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_3_IBUF | 4931 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_2_IBUF | 4932 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<0> | 4937 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<0>.Q | AUTO_CONFIG_DONE<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<1> | 4938 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<1>.Q | AUTO_CONFIG_DONE<1> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | autoconfig | 4957 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.Q | autoconfig | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | N0 | 4963 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | N0 | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | ide/ide_CLKF.UIM | 5040 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ide/ide_CLKF.Q | ide/ide_CLKF | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM +NODE | IDE_BASEADR<3> | 4949 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_BASEADR<3>.Q | IDE_BASEADR<3> | 1 | 0 | MC_UIM + +SIGNAL_INSTANCE | IDE_BASEADR<3>.SI | IDE_BASEADR<3> | 0 | 16 | 3 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | IDE_BASEADR<3> | 4949 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_BASEADR<3>.Q | IDE_BASEADR<3> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | UDS_IBUF | 4924 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | UDS_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_5_IBUF | 4927 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_4_IBUF | 4928 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_4_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_1_IBUF | 4929 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_6_IBUF | 4930 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_6_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_3_IBUF | 4931 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_2_IBUF | 4932 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<0> | 4937 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<0>.Q | AUTO_CONFIG_DONE<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<1> | 4938 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<1>.Q | AUTO_CONFIG_DONE<1> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | autoconfig | 4957 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.Q | autoconfig | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | N0 | 4963 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | N0 | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | ide/ide_CLKF.UIM | 5040 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ide/ide_CLKF.Q | ide/ide_CLKF | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | IDE_BASEADR<3>.D1 | 5157 | ? | 0 | 4096 | IDE_BASEADR<3> | NULL | NULL | IDE_BASEADR<3>.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | IDE_BASEADR<3>.D2 | 5158 | ? | 0 | 4096 | IDE_BASEADR<3> | NULL | NULL | IDE_BASEADR<3>.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 2 | IV_FALSE | RESET_IBUF | IV_FALSE | IDE_BASEADR<3> +SPPTERM | 14 | IV_FALSE | UDS_IBUF | IV_FALSE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_FALSE | A_4_IBUF | IV_FALSE | A_1_IBUF | IV_TRUE | A_6_IBUF | IV_TRUE | A_3_IBUF | IV_FALSE | A_2_IBUF | IV_TRUE | AUTO_CONFIG_DONE<0> | IV_FALSE | AUTO_CONFIG_DONE<1> | IV_FALSE | IDE_BASEADR<3> | IV_TRUE | autoconfig | IV_TRUE | N0 +SPPTERM | 15 | IV_TRUE | RESET_IBUF | IV_FALSE | UDS_IBUF | IV_FALSE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_FALSE | A_4_IBUF | IV_FALSE | A_1_IBUF | IV_TRUE | A_6_IBUF | IV_TRUE | A_3_IBUF | IV_FALSE | A_2_IBUF | IV_TRUE | AUTO_CONFIG_DONE<0> | IV_FALSE | AUTO_CONFIG_DONE<1> | IV_TRUE | IDE_BASEADR<3> | IV_TRUE | autoconfig | IV_FALSE | N0 +OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF +SIGNAL | NODE | IDE_BASEADR<3>.CLKF | 5159 | ? | 0 | 4096 | IDE_BASEADR<3> | NULL | NULL | IDE_BASEADR<3>.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 1 | IV_TRUE | ide/ide_CLKF.UIM + +SRFF_INSTANCE | IDE_BASEADR<3>.REG | IDE_BASEADR<3> | 0 | 2 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | IDE_BASEADR<3>.D | 5156 | ? | 0 | 0 | IDE_BASEADR<3> | NULL | NULL | IDE_BASEADR<3>.XOR | 0 | 7 | ALU_F +INPUT_NODE_TYPE | 1 | 8 | SRFF_C +SIGNAL | NODE | IDE_BASEADR<3>.CLKF | 5159 | ? | 0 | 4096 | IDE_BASEADR<3> | NULL | NULL | IDE_BASEADR<3>.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 1 | IV_TRUE | ide/ide_CLKF.UIM +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | IDE_BASEADR<3>.Q | 5160 | ? | 0 | 0 | IDE_BASEADR<3> | NULL | NULL | IDE_BASEADR<3>.REG | 0 | 8 | SRFF_Q + +INPUT_INSTANCE | 0 | 0 | NULL | N3 | LAN_IDE_CP_COPY_0_COPY_0 | 16 | 1 | 1 +INPUT_NODE_TYPE | 0 | 5 | II_IN +NODE | D<14> | 5015 | PIPO | 0 | 64 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | D<14> | 0 | 6 | OI_OUT +OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX +NODE | N3 | 4966 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | N3 | 0 | 5 | II_IMUX + +MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped | IDE_BASEADR<6> | LAN_IDE_CP_COPY_0_COPY_0 | 2155877376 | 16 | 2 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | IDE_BASEADR<6> | 4950 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_BASEADR<6>.Q | IDE_BASEADR<6> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_5_IBUF | 4927 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_4_IBUF | 4928 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_4_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_1_IBUF | 4929 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_6_IBUF | 4930 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_6_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_3_IBUF | 4931 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<0> | 4937 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<0>.Q | AUTO_CONFIG_DONE<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<1> | 4938 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<1>.Q | AUTO_CONFIG_DONE<1> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | autoconfig | 4957 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.Q | autoconfig | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<2> | 4939 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<2>.Q | AUTO_CONFIG_DONE<2> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_2_IBUF | 4932 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | IDE_BASEADR<7>.EXP | 5369 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_BASEADR<7>.EXP | IDE_BASEADR<7> | 4 | 0 | MC_EXPORT +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | ide/ide_CLKF.UIM | 5040 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ide/ide_CLKF.Q | ide/ide_CLKF | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM +NODE | IDE_BASEADR<6> | 4950 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_BASEADR<6>.Q | IDE_BASEADR<6> | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 4 | 0 | MC_EXPORT +NODE | IDE_BASEADR<6>.EXP | 5370 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_BASEADR<6>.EXP | IDE_BASEADR<6> | 4 | 0 | MC_EXPORT + +SIGNAL_INSTANCE | IDE_BASEADR<6>.SI | IDE_BASEADR<6> | 0 | 16 | 4 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | IDE_BASEADR<6> | 4950 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_BASEADR<6>.Q | IDE_BASEADR<6> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_5_IBUF | 4927 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_4_IBUF | 4928 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_4_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_1_IBUF | 4929 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_6_IBUF | 4930 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_6_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_3_IBUF | 4931 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<0> | 4937 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<0>.Q | AUTO_CONFIG_DONE<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<1> | 4938 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<1>.Q | AUTO_CONFIG_DONE<1> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | autoconfig | 4957 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.Q | autoconfig | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<2> | 4939 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<2>.Q | AUTO_CONFIG_DONE<2> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_2_IBUF | 4932 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | IDE_BASEADR<7>.EXP | 5369 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_BASEADR<7>.EXP | IDE_BASEADR<7> | 4 | 0 | MC_EXPORT +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | ide/ide_CLKF.UIM | 5040 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ide/ide_CLKF.Q | ide/ide_CLKF | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | IDE_BASEADR<6>.D1 | 5162 | ? | 0 | 4096 | IDE_BASEADR<6> | NULL | NULL | IDE_BASEADR<6>.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | IDE_BASEADR<6>.D2 | 5163 | ? | 0 | 4096 | IDE_BASEADR<6> | NULL | NULL | IDE_BASEADR<6>.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 1 | IV_TRUE | IDE_BASEADR<7>.EXP +SPPTERM | 2 | IV_FALSE | RESET_IBUF | IV_FALSE | IDE_BASEADR<6> +OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF +SIGNAL | NODE | IDE_BASEADR<6>.CLKF | 5164 | ? | 0 | 4096 | IDE_BASEADR<6> | NULL | NULL | IDE_BASEADR<6>.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 1 | IV_TRUE | ide/ide_CLKF.UIM +OUTPUT_NODE_TYPE | 7 | 9 | MC_SI_EXPORT +SIGNAL | NODE | IDE_BASEADR<6>.EXP | 5362 | ? | 0 | 0 | IDE_BASEADR<6> | NULL | NULL | IDE_BASEADR<6>.SI | 7 | 9 | MC_SI_EXPORT +SPPTERM | 11 | IV_TRUE | RESET_IBUF | IV_TRUE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_TRUE | A_4_IBUF | IV_FALSE | A_1_IBUF | IV_FALSE | A_6_IBUF | IV_TRUE | A_3_IBUF | IV_TRUE | AUTO_CONFIG_DONE<0> | IV_FALSE | AUTO_CONFIG_DONE<1> | IV_TRUE | autoconfig +SPPTERM | 11 | IV_TRUE | RESET_IBUF | IV_TRUE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_FALSE | A_4_IBUF | IV_FALSE | A_1_IBUF | IV_FALSE | A_6_IBUF | IV_FALSE | A_3_IBUF | IV_TRUE | AUTO_CONFIG_DONE<1> | IV_FALSE | AUTO_CONFIG_DONE<2> | IV_TRUE | autoconfig +SPPTERM | 12 | IV_TRUE | RESET_IBUF | IV_TRUE | RW_IBUF | IV_FALSE | AS_IBUF | IV_TRUE | A_5_IBUF | IV_FALSE | A_4_IBUF | IV_FALSE | A_1_IBUF | IV_FALSE | A_6_IBUF | IV_FALSE | A_3_IBUF | IV_TRUE | A_2_IBUF | IV_TRUE | AUTO_CONFIG_DONE<0> | IV_FALSE | AUTO_CONFIG_DONE<1> | IV_TRUE | autoconfig + +SRFF_INSTANCE | IDE_BASEADR<6>.REG | IDE_BASEADR<6> | 0 | 2 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | IDE_BASEADR<6>.D | 5161 | ? | 0 | 0 | IDE_BASEADR<6> | NULL | NULL | IDE_BASEADR<6>.XOR | 0 | 7 | ALU_F +INPUT_NODE_TYPE | 1 | 8 | SRFF_C +SIGNAL | NODE | IDE_BASEADR<6>.CLKF | 5164 | ? | 0 | 4096 | IDE_BASEADR<6> | NULL | NULL | IDE_BASEADR<6>.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 1 | IV_TRUE | ide/ide_CLKF.UIM +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | IDE_BASEADR<6>.Q | 5165 | ? | 0 | 0 | IDE_BASEADR<6> | NULL | NULL | IDE_BASEADR<6>.REG | 0 | 8 | SRFF_Q + +INPUT_INSTANCE | 0 | 0 | NULL | N4 | LAN_IDE_CP_COPY_0_COPY_0 | 16 | 1 | 1 +INPUT_NODE_TYPE | 0 | 5 | II_IN +NODE | D<15> | 5016 | PIPO | 0 | 64 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | D<15> | 0 | 6 | OI_OUT +OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX +NODE | N4 | 4967 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | N4 | 0 | 5 | II_IMUX + +MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped | IDE_BASEADR<7> | LAN_IDE_CP_COPY_0_COPY_0 | 2155877376 | 19 | 2 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | IDE_BASEADR<7> | 4951 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_BASEADR<7>.Q | IDE_BASEADR<7> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | UDS_IBUF | 4924 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | UDS_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_5_IBUF | 4927 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_4_IBUF | 4928 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_4_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_1_IBUF | 4929 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_6_IBUF | 4930 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_6_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_3_IBUF | 4931 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_2_IBUF | 4932 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<0> | 4937 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<0>.Q | AUTO_CONFIG_DONE<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<1> | 4938 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<1>.Q | AUTO_CONFIG_DONE<1> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | autoconfig | 4957 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.Q | autoconfig | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | N4 | 4967 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | N4 | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | ide/ide_CLKF.UIM | 5040 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ide/ide_CLKF.Q | ide/ide_CLKF | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | IDE_BASEADR<6> | 4950 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_BASEADR<6>.Q | IDE_BASEADR<6> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | N3 | 4966 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | N3 | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE_CYCLE<0>.EXP | 5368 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE_CYCLE<0>.EXP | AUTO_CONFIG_DONE_CYCLE<0> | 4 | 0 | MC_EXPORT +OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM +NODE | IDE_BASEADR<7> | 4951 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_BASEADR<7>.Q | IDE_BASEADR<7> | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 4 | 0 | MC_EXPORT +NODE | IDE_BASEADR<7>.EXP | 5369 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_BASEADR<7>.EXP | IDE_BASEADR<7> | 4 | 0 | MC_EXPORT + +SIGNAL_INSTANCE | IDE_BASEADR<7>.SI | IDE_BASEADR<7> | 0 | 19 | 4 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | IDE_BASEADR<7> | 4951 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_BASEADR<7>.Q | IDE_BASEADR<7> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | UDS_IBUF | 4924 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | UDS_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_5_IBUF | 4927 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_4_IBUF | 4928 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_4_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_1_IBUF | 4929 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_6_IBUF | 4930 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_6_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_3_IBUF | 4931 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_2_IBUF | 4932 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<0> | 4937 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<0>.Q | AUTO_CONFIG_DONE<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<1> | 4938 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<1>.Q | AUTO_CONFIG_DONE<1> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | autoconfig | 4957 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.Q | autoconfig | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | N4 | 4967 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | N4 | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | ide/ide_CLKF.UIM | 5040 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ide/ide_CLKF.Q | ide/ide_CLKF | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | IDE_BASEADR<6> | 4950 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_BASEADR<6>.Q | IDE_BASEADR<6> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | N3 | 4966 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | N3 | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE_CYCLE<0>.EXP | 5368 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE_CYCLE<0>.EXP | AUTO_CONFIG_DONE_CYCLE<0> | 4 | 0 | MC_EXPORT +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | IDE_BASEADR<7>.D1 | 5167 | ? | 0 | 4096 | IDE_BASEADR<7> | NULL | NULL | IDE_BASEADR<7>.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | IDE_BASEADR<7>.D2 | 5168 | ? | 0 | 4096 | IDE_BASEADR<7> | NULL | NULL | IDE_BASEADR<7>.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 1 | IV_TRUE | AUTO_CONFIG_DONE_CYCLE<0>.EXP +SPPTERM | 2 | IV_FALSE | RESET_IBUF | IV_FALSE | IDE_BASEADR<7> +SPPTERM | 14 | IV_FALSE | UDS_IBUF | IV_FALSE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_FALSE | A_4_IBUF | IV_FALSE | A_1_IBUF | IV_TRUE | A_6_IBUF | IV_TRUE | A_3_IBUF | IV_FALSE | A_2_IBUF | IV_TRUE | AUTO_CONFIG_DONE<0> | IV_FALSE | AUTO_CONFIG_DONE<1> | IV_FALSE | IDE_BASEADR<7> | IV_TRUE | autoconfig | IV_TRUE | N4 +OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF +SIGNAL | NODE | IDE_BASEADR<7>.CLKF | 5169 | ? | 0 | 4096 | IDE_BASEADR<7> | NULL | NULL | IDE_BASEADR<7>.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 1 | IV_TRUE | ide/ide_CLKF.UIM +OUTPUT_NODE_TYPE | 7 | 9 | MC_SI_EXPORT +SIGNAL | NODE | IDE_BASEADR<7>.EXP | 5361 | ? | 0 | 0 | IDE_BASEADR<7> | NULL | NULL | IDE_BASEADR<7>.SI | 7 | 9 | MC_SI_EXPORT +SPPTERM | 14 | IV_FALSE | UDS_IBUF | IV_FALSE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_FALSE | A_4_IBUF | IV_FALSE | A_1_IBUF | IV_TRUE | A_6_IBUF | IV_TRUE | A_3_IBUF | IV_FALSE | A_2_IBUF | IV_TRUE | AUTO_CONFIG_DONE<0> | IV_FALSE | AUTO_CONFIG_DONE<1> | IV_FALSE | IDE_BASEADR<6> | IV_TRUE | autoconfig | IV_TRUE | N3 +SPPTERM | 15 | IV_TRUE | RESET_IBUF | IV_FALSE | UDS_IBUF | IV_FALSE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_FALSE | A_4_IBUF | IV_FALSE | A_1_IBUF | IV_TRUE | A_6_IBUF | IV_TRUE | A_3_IBUF | IV_FALSE | A_2_IBUF | IV_TRUE | AUTO_CONFIG_DONE<0> | IV_FALSE | AUTO_CONFIG_DONE<1> | IV_TRUE | IDE_BASEADR<6> | IV_TRUE | autoconfig | IV_FALSE | N3 + +SRFF_INSTANCE | IDE_BASEADR<7>.REG | IDE_BASEADR<7> | 0 | 2 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | IDE_BASEADR<7>.D | 5166 | ? | 0 | 0 | IDE_BASEADR<7> | NULL | NULL | IDE_BASEADR<7>.XOR | 0 | 7 | ALU_F +INPUT_NODE_TYPE | 1 | 8 | SRFF_C +SIGNAL | NODE | IDE_BASEADR<7>.CLKF | 5169 | ? | 0 | 4096 | IDE_BASEADR<7> | NULL | NULL | IDE_BASEADR<7>.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 1 | IV_TRUE | ide/ide_CLKF.UIM +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | IDE_BASEADR<7>.Q | 5170 | ? | 0 | 0 | IDE_BASEADR<7> | NULL | NULL | IDE_BASEADR<7>.REG | 0 | 8 | SRFF_Q + +MACROCELL_INSTANCE | Inv+PrldLow+OptxMapped | SHUT_UP<1> | LAN_IDE_CP_COPY_0_COPY_0 | 2155873536 | 15 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | SHUT_UP<1> | 4952 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | SHUT_UP<1>.Q | SHUT_UP<1> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | UDS_IBUF | 4924 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | UDS_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_5_IBUF | 4927 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_4_IBUF | 4928 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_4_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_1_IBUF | 4929 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_6_IBUF | 4930 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_6_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_3_IBUF | 4931 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_2_IBUF | 4932 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<0> | 4937 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<0>.Q | AUTO_CONFIG_DONE<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<1> | 4938 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<1>.Q | AUTO_CONFIG_DONE<1> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | autoconfig | 4957 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.Q | autoconfig | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | ide/ide_CLKF.UIM | 5040 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ide/ide_CLKF.Q | ide/ide_CLKF | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM +NODE | SHUT_UP<1> | 4952 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | SHUT_UP<1>.Q | SHUT_UP<1> | 1 | 0 | MC_UIM + +SIGNAL_INSTANCE | SHUT_UP<1>.SI | SHUT_UP<1> | 0 | 15 | 3 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | SHUT_UP<1> | 4952 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | SHUT_UP<1>.Q | SHUT_UP<1> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | UDS_IBUF | 4924 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | UDS_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_5_IBUF | 4927 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_4_IBUF | 4928 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_4_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_1_IBUF | 4929 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_6_IBUF | 4930 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_6_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_3_IBUF | 4931 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_2_IBUF | 4932 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<0> | 4937 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<0>.Q | AUTO_CONFIG_DONE<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<1> | 4938 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<1>.Q | AUTO_CONFIG_DONE<1> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | autoconfig | 4957 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.Q | autoconfig | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | ide/ide_CLKF.UIM | 5040 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ide/ide_CLKF.Q | ide/ide_CLKF | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | SHUT_UP<1>.D1 | 5172 | ? | 0 | 4096 | SHUT_UP<1> | NULL | NULL | SHUT_UP<1>.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | SHUT_UP<1>.D2 | 5173 | ? | 0 | 4096 | SHUT_UP<1> | NULL | NULL | SHUT_UP<1>.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 2 | IV_TRUE | RESET_IBUF | IV_FALSE | SHUT_UP<1> +SPPTERM | 13 | IV_TRUE | RESET_IBUF | IV_FALSE | UDS_IBUF | IV_FALSE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_FALSE | A_4_IBUF | IV_FALSE | A_1_IBUF | IV_TRUE | A_6_IBUF | IV_TRUE | A_3_IBUF | IV_FALSE | A_2_IBUF | IV_TRUE | AUTO_CONFIG_DONE<0> | IV_FALSE | AUTO_CONFIG_DONE<1> | IV_TRUE | autoconfig +OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF +SIGNAL | NODE | SHUT_UP<1>.CLKF | 5174 | ? | 0 | 4096 | SHUT_UP<1> | NULL | NULL | SHUT_UP<1>.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 1 | IV_TRUE | ide/ide_CLKF.UIM + +SRFF_INSTANCE | SHUT_UP<1>.REG | SHUT_UP<1> | 0 | 2 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | SHUT_UP<1>.D | 5171 | ? | 0 | 0 | SHUT_UP<1> | NULL | NULL | SHUT_UP<1>.XOR | 0 | 7 | ALU_F +INPUT_NODE_TYPE | 1 | 8 | SRFF_C +SIGNAL | NODE | SHUT_UP<1>.CLKF | 5174 | ? | 0 | 4096 | SHUT_UP<1> | NULL | NULL | SHUT_UP<1>.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 1 | IV_TRUE | ide/ide_CLKF.UIM +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | SHUT_UP<1>.Q | 5175 | ? | 0 | 0 | SHUT_UP<1> | NULL | NULL | SHUT_UP<1>.REG | 0 | 8 | SRFF_Q + +INPUT_INSTANCE | 0 | 0 | NULL | BERR_IBUF | LAN_IDE_CP_COPY_0_COPY_0 | 16 | 1 | 1 +INPUT_NODE_TYPE | 0 | 5 | II_IN +NODE | BERR | 5056 | PI | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE +OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX +NODE | BERR_IBUF | 4954 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | BERR_IBUF | 0 | 5 | II_IMUX + +INPUT_INSTANCE | 0 | 0 | NULL | C1_IBUF | LAN_IDE_CP_COPY_0_COPY_0 | 16 | 1 | 1 +INPUT_NODE_TYPE | 0 | 5 | II_IN +NODE | C1 | 5057 | PI | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE +OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX +NODE | C1_IBUF | 4955 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | C1_IBUF | 0 | 5 | II_IMUX + +INPUT_INSTANCE | 0 | 0 | NULL | C3_IBUF | LAN_IDE_CP_COPY_0_COPY_0 | 16 | 1 | 1 +INPUT_NODE_TYPE | 0 | 5 | II_IN +NODE | C3 | 5058 | PI | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE +OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX +NODE | C3_IBUF | 4956 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | C3_IBUF | 0 | 5 | II_IMUX + +INPUT_INSTANCE | 0 | 0 | NULL | A_16_IBUF | LAN_IDE_CP_COPY_0_COPY_0 | 16 | 1 | 1 +INPUT_NODE_TYPE | 0 | 5 | II_IN +NODE | A<16> | 5060 | PI | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE +OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX +NODE | A_16_IBUF | 4969 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_16_IBUF | 0 | 5 | II_IMUX + +INPUT_INSTANCE | 0 | 0 | NULL | A_20_IBUF | LAN_IDE_CP_COPY_0_COPY_0 | 16 | 1 | 1 +INPUT_NODE_TYPE | 0 | 5 | II_IN +NODE | A<20> | 5061 | PI | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE +OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX +NODE | A_20_IBUF | 4970 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_20_IBUF | 0 | 5 | II_IMUX + +INPUT_INSTANCE | 0 | 0 | NULL | A_17_IBUF | LAN_IDE_CP_COPY_0_COPY_0 | 16 | 1 | 1 +INPUT_NODE_TYPE | 0 | 5 | II_IN +NODE | A<17> | 5059 | PI | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE +OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX +NODE | A_17_IBUF | 4968 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_17_IBUF | 0 | 5 | II_IMUX + +INPUT_INSTANCE | 0 | 0 | NULL | A_18_IBUF | LAN_IDE_CP_COPY_0_COPY_0 | 16 | 1 | 1 +INPUT_NODE_TYPE | 0 | 5 | II_IN +NODE | A<18> | 5062 | PI | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE +OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX +NODE | A_18_IBUF | 4971 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_18_IBUF | 0 | 5 | II_IMUX + +MACROCELL_INSTANCE | PrldLow+OptxMapped | autoconfig | LAN_IDE_CP_COPY_0_COPY_0 | 2155873280 | 14 | 2 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_23_IBUF | 4933 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_23_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_22_IBUF | 4934 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_22_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_21_IBUF | 4935 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_21_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_19_IBUF | 4936 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_19_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<0> | 4937 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<0>.Q | AUTO_CONFIG_DONE<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | BERR_IBUF | 4954 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | BERR_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_17_IBUF | 4968 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_17_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_16_IBUF | 4969 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_16_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_20_IBUF | 4970 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_20_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_18_IBUF | 4971 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_18_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<1> | 4938 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<1>.Q | AUTO_CONFIG_DONE<1> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<2> | 4939 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<2>.Q | AUTO_CONFIG_DONE<2> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | ide/ide_CLKF.UIM | 5040 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ide/ide_CLKF.Q | ide/ide_CLKF | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | IDE_BASEADR<5> | 4945 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_BASEADR<5>.Q | IDE_BASEADR<5> | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM +NODE | autoconfig | 4957 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.Q | autoconfig | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 4 | 0 | MC_EXPORT +NODE | autoconfig.EXP | 5380 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.EXP | autoconfig | 4 | 0 | MC_EXPORT + +SIGNAL_INSTANCE | autoconfig.SI | autoconfig | 0 | 14 | 4 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_23_IBUF | 4933 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_23_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_22_IBUF | 4934 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_22_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_21_IBUF | 4935 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_21_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_19_IBUF | 4936 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_19_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<0> | 4937 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<0>.Q | AUTO_CONFIG_DONE<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | BERR_IBUF | 4954 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | BERR_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_17_IBUF | 4968 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_17_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_16_IBUF | 4969 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_16_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_20_IBUF | 4970 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_20_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_18_IBUF | 4971 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_18_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<1> | 4938 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<1>.Q | AUTO_CONFIG_DONE<1> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<2> | 4939 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<2>.Q | AUTO_CONFIG_DONE<2> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | ide/ide_CLKF.UIM | 5040 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ide/ide_CLKF.Q | ide/ide_CLKF | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | IDE_BASEADR<5> | 4945 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_BASEADR<5>.Q | IDE_BASEADR<5> | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | autoconfig.D1 | 5177 | ? | 0 | 4096 | autoconfig | NULL | NULL | autoconfig.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | autoconfig.D2 | 5178 | ? | 0 | 4096 | autoconfig | NULL | NULL | autoconfig.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 10 | IV_TRUE | A_23_IBUF | IV_TRUE | A_22_IBUF | IV_TRUE | A_21_IBUF | IV_TRUE | A_19_IBUF | IV_FALSE | AUTO_CONFIG_DONE<0> | IV_TRUE | BERR_IBUF | IV_FALSE | A_17_IBUF | IV_FALSE | A_16_IBUF | IV_FALSE | A_20_IBUF | IV_FALSE | A_18_IBUF +SPPTERM | 10 | IV_TRUE | A_23_IBUF | IV_TRUE | A_22_IBUF | IV_TRUE | A_21_IBUF | IV_TRUE | A_19_IBUF | IV_FALSE | AUTO_CONFIG_DONE<1> | IV_TRUE | BERR_IBUF | IV_FALSE | A_17_IBUF | IV_FALSE | A_16_IBUF | IV_FALSE | A_20_IBUF | IV_FALSE | A_18_IBUF +SPPTERM | 10 | IV_TRUE | A_23_IBUF | IV_TRUE | A_22_IBUF | IV_TRUE | A_21_IBUF | IV_TRUE | A_19_IBUF | IV_FALSE | AUTO_CONFIG_DONE<2> | IV_TRUE | BERR_IBUF | IV_FALSE | A_17_IBUF | IV_FALSE | A_16_IBUF | IV_FALSE | A_20_IBUF | IV_FALSE | A_18_IBUF +OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF +SIGNAL | NODE | autoconfig.CLKF | 5179 | ? | 0 | 4096 | autoconfig | NULL | NULL | autoconfig.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 1 | IV_TRUE | ide/ide_CLKF.UIM +OUTPUT_NODE_TYPE | 7 | 9 | MC_SI_EXPORT +SIGNAL | NODE | autoconfig.EXP | 5376 | ? | 0 | 0 | autoconfig | NULL | NULL | autoconfig.SI | 7 | 9 | MC_SI_EXPORT +SPPTERM | 2 | IV_TRUE | A_21_IBUF | IV_FALSE | IDE_BASEADR<5> + +SRFF_INSTANCE | autoconfig.REG | autoconfig | 0 | 2 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | autoconfig.D | 5176 | ? | 0 | 0 | autoconfig | NULL | NULL | autoconfig.XOR | 0 | 7 | ALU_F +INPUT_NODE_TYPE | 1 | 8 | SRFF_C +SIGNAL | NODE | autoconfig.CLKF | 5179 | ? | 0 | 4096 | autoconfig | NULL | NULL | autoconfig.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 1 | IV_TRUE | ide/ide_CLKF.UIM +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | autoconfig.Q | 5180 | ? | 0 | 0 | autoconfig | NULL | NULL | autoconfig.REG | 0 | 8 | SRFF_Q + +MACROCELL_INSTANCE | Inv+PrldLow+OptxMapped | ide | LAN_IDE_CP_COPY_0_COPY_0 | 2155873536 | 7 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | BERR_IBUF | 4954 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | BERR_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | SHUT_UP<1> | 4952 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | SHUT_UP<1>.Q | SHUT_UP<1> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_19_IBUF | 4936 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_19_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | IDE_BASEADR<3> | 4949 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_BASEADR<3>.Q | IDE_BASEADR<3> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | EXP19_.EXP | 5378 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | EXP19_.EXP | EXP19_ | 4 | 0 | MC_EXPORT +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | EXP21_.EXP | 5381 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | EXP21_.EXP | EXP21_ | 4 | 0 | MC_EXPORT +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | ide/ide_CLKF.UIM | 5040 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ide/ide_CLKF.Q | ide/ide_CLKF | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM +NODE | ide | 4958 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ide.Q | ide | 1 | 0 | MC_UIM + +SIGNAL_INSTANCE | ide.SI | ide | 0 | 7 | 3 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | BERR_IBUF | 4954 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | BERR_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | SHUT_UP<1> | 4952 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | SHUT_UP<1>.Q | SHUT_UP<1> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_19_IBUF | 4936 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_19_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | IDE_BASEADR<3> | 4949 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_BASEADR<3>.Q | IDE_BASEADR<3> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | EXP19_.EXP | 5378 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | EXP19_.EXP | EXP19_ | 4 | 0 | MC_EXPORT +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | EXP21_.EXP | 5381 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | EXP21_.EXP | EXP21_ | 4 | 0 | MC_EXPORT +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | ide/ide_CLKF.UIM | 5040 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ide/ide_CLKF.Q | ide/ide_CLKF | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | ide.D1 | 5182 | ? | 0 | 4096 | ide | NULL | NULL | ide.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | ide.D2 | 5183 | ? | 0 | 4096 | ide | NULL | NULL | ide.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 1 | IV_TRUE | SHUT_UP<1> +SPPTERM | 1 | IV_FALSE | BERR_IBUF +SPPTERM | 1 | IV_TRUE | EXP19_.EXP +SPPTERM | 1 | IV_TRUE | EXP21_.EXP +SPPTERM | 2 | IV_TRUE | A_19_IBUF | IV_FALSE | IDE_BASEADR<3> +SPPTERM | 2 | IV_FALSE | A_19_IBUF | IV_TRUE | IDE_BASEADR<3> +OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF +SIGNAL | NODE | ide.CLKF | 5184 | ? | 0 | 4096 | ide | NULL | NULL | ide.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 1 | IV_TRUE | ide/ide_CLKF.UIM + +SRFF_INSTANCE | ide.REG | ide | 0 | 2 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | ide.D | 5181 | ? | 0 | 0 | ide | NULL | NULL | ide.XOR | 0 | 7 | ALU_F +INPUT_NODE_TYPE | 1 | 8 | SRFF_C +SIGNAL | NODE | ide.CLKF | 5184 | ? | 0 | 4096 | ide | NULL | NULL | ide.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 1 | IV_TRUE | ide/ide_CLKF.UIM +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | ide.Q | 5185 | ? | 0 | 0 | ide | NULL | NULL | ide.REG | 0 | 8 | SRFF_Q + +MACROCELL_INSTANCE | PrldLow+OptxMapped | AUTOCONFIG_IN_PROGRESS | LAN_IDE_CP_COPY_0_COPY_0 | 2155873280 | 3 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | autoconfig | 4957 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.Q | autoconfig | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | ide/ide_CLKF.UIM | 5040 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ide/ide_CLKF.Q | ide/ide_CLKF | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM +NODE | AUTOCONFIG_IN_PROGRESS | 4959 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTOCONFIG_IN_PROGRESS.Q | AUTOCONFIG_IN_PROGRESS | 1 | 0 | MC_UIM + +SIGNAL_INSTANCE | AUTOCONFIG_IN_PROGRESS.SI | AUTOCONFIG_IN_PROGRESS | 0 | 3 | 3 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | autoconfig | 4957 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.Q | autoconfig | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | ide/ide_CLKF.UIM | 5040 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ide/ide_CLKF.Q | ide/ide_CLKF | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | AUTOCONFIG_IN_PROGRESS.D1 | 5187 | ? | 0 | 4096 | AUTOCONFIG_IN_PROGRESS | NULL | NULL | AUTOCONFIG_IN_PROGRESS.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | AUTOCONFIG_IN_PROGRESS.D2 | 5188 | ? | 0 | 4096 | AUTOCONFIG_IN_PROGRESS | NULL | NULL | AUTOCONFIG_IN_PROGRESS.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 2 | IV_FALSE | AS_IBUF | IV_TRUE | autoconfig +OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF +SIGNAL | NODE | AUTOCONFIG_IN_PROGRESS.CLKF | 5189 | ? | 0 | 4096 | AUTOCONFIG_IN_PROGRESS | NULL | NULL | AUTOCONFIG_IN_PROGRESS.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 1 | IV_TRUE | ide/ide_CLKF.UIM + +SRFF_INSTANCE | AUTOCONFIG_IN_PROGRESS.REG | AUTOCONFIG_IN_PROGRESS | 0 | 2 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | AUTOCONFIG_IN_PROGRESS.D | 5186 | ? | 0 | 0 | AUTOCONFIG_IN_PROGRESS | NULL | NULL | AUTOCONFIG_IN_PROGRESS.XOR | 0 | 7 | ALU_F +INPUT_NODE_TYPE | 1 | 8 | SRFF_C +SIGNAL | NODE | AUTOCONFIG_IN_PROGRESS.CLKF | 5189 | ? | 0 | 4096 | AUTOCONFIG_IN_PROGRESS | NULL | NULL | AUTOCONFIG_IN_PROGRESS.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 1 | IV_TRUE | ide/ide_CLKF.UIM +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | AUTOCONFIG_IN_PROGRESS.Q | 5190 | ? | 0 | 0 | AUTOCONFIG_IN_PROGRESS | NULL | NULL | AUTOCONFIG_IN_PROGRESS.REG | 0 | 8 | SRFF_Q + +MACROCELL_INSTANCE | Inv+PrldHigh+OptxMapped | IDE_R_S | LAN_IDE_CP_COPY_0_COPY_0 | 2155873024 | 6 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | IDE_ENABLE | 4946 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_ENABLE.Q | IDE_ENABLE | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | ide | 4958 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ide.Q | ide | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | ide/ide_CLKF.UIM | 5040 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ide/ide_CLKF.Q | ide/ide_CLKF | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 0 | 0 | MC_Q +NODE | IDE_R_S | 4972 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_R_S.Q | IDE_R_S | 0 | 0 | MC_Q + +SIGNAL_INSTANCE | IDE_R_S.SI | IDE_R_S | 0 | 6 | 3 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | IDE_ENABLE | 4946 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_ENABLE.Q | IDE_ENABLE | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | ide | 4958 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ide.Q | ide | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | ide/ide_CLKF.UIM | 5040 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ide/ide_CLKF.Q | ide/ide_CLKF | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | IDE_R_S.D1 | 5192 | ? | 0 | 4096 | IDE_R_S | NULL | NULL | IDE_R_S.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | IDE_R_S.D2 | 5193 | ? | 0 | 4096 | IDE_R_S | NULL | NULL | IDE_R_S.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 5 | IV_TRUE | RESET_IBUF | IV_TRUE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | IDE_ENABLE | IV_TRUE | ide +OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF +SIGNAL | NODE | IDE_R_S.CLKF | 5194 | ? | 0 | 4096 | IDE_R_S | NULL | NULL | IDE_R_S.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 1 | IV_TRUE | ide/ide_CLKF.UIM + +SRFF_INSTANCE | IDE_R_S.REG | IDE_R_S | 0 | 2 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | IDE_R_S.D | 5191 | ? | 0 | 0 | IDE_R_S | NULL | NULL | IDE_R_S.XOR | 0 | 7 | ALU_F +INPUT_NODE_TYPE | 1 | 8 | SRFF_C +SIGNAL | NODE | IDE_R_S.CLKF | 5194 | ? | 0 | 4096 | IDE_R_S | NULL | NULL | IDE_R_S.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 1 | IV_TRUE | ide/ide_CLKF.UIM +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | IDE_R_S.Q | 5195 | ? | 0 | 0 | IDE_R_S | NULL | NULL | IDE_R_S.REG | 0 | 8 | SRFF_Q + +MACROCELL_INSTANCE | Inv+PrldHigh+OptxMapped | IDE_W_S | LAN_IDE_CP_COPY_0_COPY_0 | 2155873024 | 6 | 2 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | ide | 4958 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ide.Q | ide | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | ide/ide_CLKF.UIM | 5040 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ide/ide_CLKF.Q | ide/ide_CLKF | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | IDE_ENABLE | 4946 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_ENABLE.Q | IDE_ENABLE | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 0 | 0 | MC_Q +NODE | IDE_W_S | 4973 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_W_S.Q | IDE_W_S | 0 | 0 | MC_Q +OUTPUT_NODE_TYPE | 4 | 0 | MC_EXPORT +NODE | IDE_W_S.EXP | 5355 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_W_S.EXP | IDE_W_S | 4 | 0 | MC_EXPORT + +SIGNAL_INSTANCE | IDE_W_S.SI | IDE_W_S | 0 | 6 | 4 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | ide | 4958 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ide.Q | ide | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | ide/ide_CLKF.UIM | 5040 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ide/ide_CLKF.Q | ide/ide_CLKF | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | IDE_ENABLE | 4946 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_ENABLE.Q | IDE_ENABLE | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | IDE_W_S.D1 | 5197 | ? | 0 | 4096 | IDE_W_S | NULL | NULL | IDE_W_S.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | IDE_W_S.D2 | 5198 | ? | 0 | 4096 | IDE_W_S | NULL | NULL | IDE_W_S.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 4 | IV_TRUE | RESET_IBUF | IV_FALSE | RW_IBUF | IV_FALSE | AS_IBUF | IV_TRUE | ide +OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF +SIGNAL | NODE | IDE_W_S.CLKF | 5199 | ? | 0 | 4096 | IDE_W_S | NULL | NULL | IDE_W_S.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 1 | IV_TRUE | ide/ide_CLKF.UIM +OUTPUT_NODE_TYPE | 7 | 9 | MC_SI_EXPORT +SIGNAL | NODE | IDE_W_S.EXP | 5350 | ? | 0 | 0 | IDE_W_S | NULL | NULL | IDE_W_S.SI | 7 | 9 | MC_SI_EXPORT +SPPTERM | 5 | IV_TRUE | RESET_IBUF | IV_TRUE | RW_IBUF | IV_FALSE | AS_IBUF | IV_TRUE | IDE_ENABLE | IV_TRUE | ide + +SRFF_INSTANCE | IDE_W_S.REG | IDE_W_S | 0 | 2 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | IDE_W_S.D | 5196 | ? | 0 | 0 | IDE_W_S | NULL | NULL | IDE_W_S.XOR | 0 | 7 | ALU_F +INPUT_NODE_TYPE | 1 | 8 | SRFF_C +SIGNAL | NODE | IDE_W_S.CLKF | 5199 | ? | 0 | 4096 | IDE_W_S | NULL | NULL | IDE_W_S.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 1 | IV_TRUE | ide/ide_CLKF.UIM +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | IDE_W_S.Q | 5200 | ? | 0 | 0 | IDE_W_S | NULL | NULL | IDE_W_S.REG | 0 | 8 | SRFF_Q + +MACROCELL_INSTANCE | Inv+PrldHigh+OptxMapped | ROM_OE_S | LAN_IDE_CP_COPY_0_COPY_0 | 2155873024 | 15 | 2 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_5_IBUF | 4927 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_4_IBUF | 4928 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_4_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | ide/ide_CLKF.UIM | 5040 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ide/ide_CLKF.Q | ide/ide_CLKF | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_1_IBUF | 4929 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_6_IBUF | 4930 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_6_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_3_IBUF | 4931 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_2_IBUF | 4932 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<2> | 4939 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<2>.Q | AUTO_CONFIG_DONE<2> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | autoconfig | 4957 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.Q | autoconfig | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<0> | 4937 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<0>.Q | AUTO_CONFIG_DONE<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<1> | 4938 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<1>.Q | AUTO_CONFIG_DONE<1> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | IDE_W_S.EXP | 5355 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_W_S.EXP | IDE_W_S | 4 | 0 | MC_EXPORT +OUTPUT_NODE_TYPE | 0 | 0 | MC_Q +NODE | ROM_OE_S | 4974 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ROM_OE_S.Q | ROM_OE_S | 0 | 0 | MC_Q +OUTPUT_NODE_TYPE | 4 | 0 | MC_EXPORT +NODE | ROM_OE_S.EXP | 5356 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ROM_OE_S.EXP | ROM_OE_S | 4 | 0 | MC_EXPORT + +SIGNAL_INSTANCE | ROM_OE_S.SI | ROM_OE_S | 0 | 15 | 4 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_5_IBUF | 4927 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_4_IBUF | 4928 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_4_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | ide/ide_CLKF.UIM | 5040 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ide/ide_CLKF.Q | ide/ide_CLKF | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_1_IBUF | 4929 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_6_IBUF | 4930 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_6_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_3_IBUF | 4931 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_2_IBUF | 4932 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<2> | 4939 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<2>.Q | AUTO_CONFIG_DONE<2> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | autoconfig | 4957 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.Q | autoconfig | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<0> | 4937 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<0>.Q | AUTO_CONFIG_DONE<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<1> | 4938 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<1>.Q | AUTO_CONFIG_DONE<1> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | IDE_W_S.EXP | 5355 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_W_S.EXP | IDE_W_S | 4 | 0 | MC_EXPORT +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | ROM_OE_S.D1 | 5202 | ? | 0 | 4096 | ROM_OE_S | NULL | NULL | ROM_OE_S.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | ROM_OE_S.D2 | 5203 | ? | 0 | 4096 | ROM_OE_S | NULL | NULL | ROM_OE_S.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 1 | IV_TRUE | IDE_W_S.EXP +OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF +SIGNAL | NODE | ROM_OE_S.CLKF | 5204 | ? | 0 | 4096 | ROM_OE_S | NULL | NULL | ROM_OE_S.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 1 | IV_TRUE | ide/ide_CLKF.UIM +OUTPUT_NODE_TYPE | 7 | 9 | MC_SI_EXPORT +SIGNAL | NODE | ROM_OE_S.EXP | 5351 | ? | 0 | 0 | ROM_OE_S | NULL | NULL | ROM_OE_S.SI | 7 | 9 | MC_SI_EXPORT +SPPTERM | 11 | IV_TRUE | RESET_IBUF | IV_TRUE | RW_IBUF | IV_FALSE | AS_IBUF | IV_TRUE | A_5_IBUF | IV_FALSE | A_4_IBUF | IV_TRUE | A_1_IBUF | IV_FALSE | A_6_IBUF | IV_FALSE | A_3_IBUF | IV_TRUE | A_2_IBUF | IV_FALSE | AUTO_CONFIG_DONE<2> | IV_TRUE | autoconfig +SPPTERM | 11 | IV_TRUE | RESET_IBUF | IV_TRUE | RW_IBUF | IV_FALSE | AS_IBUF | IV_TRUE | A_5_IBUF | IV_FALSE | A_4_IBUF | IV_FALSE | A_6_IBUF | IV_FALSE | A_3_IBUF | IV_TRUE | A_2_IBUF | IV_TRUE | AUTO_CONFIG_DONE<0> | IV_FALSE | AUTO_CONFIG_DONE<1> | IV_TRUE | autoconfig +SPPTERM | 11 | IV_TRUE | RESET_IBUF | IV_TRUE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_TRUE | A_4_IBUF | IV_TRUE | A_1_IBUF | IV_FALSE | A_6_IBUF | IV_TRUE | A_3_IBUF | IV_TRUE | AUTO_CONFIG_DONE<0> | IV_FALSE | AUTO_CONFIG_DONE<1> | IV_TRUE | autoconfig +SPPTERM | 11 | IV_TRUE | RESET_IBUF | IV_TRUE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_FALSE | A_1_IBUF | IV_FALSE | A_6_IBUF | IV_FALSE | A_3_IBUF | IV_TRUE | A_2_IBUF | IV_TRUE | AUTO_CONFIG_DONE<1> | IV_FALSE | AUTO_CONFIG_DONE<2> | IV_TRUE | autoconfig + +SRFF_INSTANCE | ROM_OE_S.REG | ROM_OE_S | 0 | 2 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | ROM_OE_S.D | 5201 | ? | 0 | 0 | ROM_OE_S | NULL | NULL | ROM_OE_S.XOR | 0 | 7 | ALU_F +INPUT_NODE_TYPE | 1 | 8 | SRFF_C +SIGNAL | NODE | ROM_OE_S.CLKF | 5204 | ? | 0 | 4096 | ROM_OE_S | NULL | NULL | ROM_OE_S.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 1 | IV_TRUE | ide/ide_CLKF.UIM +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | ROM_OE_S.Q | 5205 | ? | 0 | 0 | ROM_OE_S | NULL | NULL | ROM_OE_S.REG | 0 | 8 | SRFF_Q + +MACROCELL_INSTANCE | FbkInv+PinTrst+Merge+OptxMapped | N1 | LAN_IDE_CP_COPY_0_COPY_0 | 2155923456 | 2 | 2 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTOCONFIG_IN_PROGRESS | 4959 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTOCONFIG_IN_PROGRESS.Q | AUTOCONFIG_IN_PROGRESS | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 0 | 0 | MC_Q +NODE | N1$Q | 4975 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | N1.Q | N1 | 0 | 0 | MC_Q +OUTPUT_NODE_TYPE | 2 | 0 | MC_OE +NODE | N1$OE | 4976 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | N1.BUFOE.OUT | N1 | 2 | 0 | MC_OE + +SIGNAL_INSTANCE | N1.SI | N1 | 0 | 2 | 3 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTOCONFIG_IN_PROGRESS | 4959 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTOCONFIG_IN_PROGRESS.Q | AUTOCONFIG_IN_PROGRESS | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | N1.D1 | 5207 | ? | 0 | 4096 | N1 | NULL | NULL | N1.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | N1.D2 | 5208 | ? | 0 | 4096 | N1 | NULL | NULL | N1.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 0 | IV_DC +OUTPUT_NODE_TYPE | 4 | 9 | MC_SI_TRST +SIGNAL | NODE | N1.TRST | 5210 | ? | 0 | 4096 | N1 | NULL | NULL | N1.SI | 4 | 9 | MC_SI_TRST +SPPTERM | 2 | IV_TRUE | RW_IBUF | IV_TRUE | AUTOCONFIG_IN_PROGRESS + +SRFF_INSTANCE | N1.REG | N1 | 0 | 1 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | N1.D | 5206 | ? | 0 | 0 | N1 | NULL | NULL | N1.XOR | 0 | 7 | ALU_F +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | N1.Q | 5211 | ? | 0 | 0 | N1 | NULL | NULL | N1.REG | 0 | 8 | SRFF_Q + +BUF_INSTANCE | N1.BUFOE | N1 | 0 | 1 | 1 +INPUT_NODE_TYPE | 0 | 10 | CTOR_UNKNOWN +SIGNAL | NODE | N1.TRST | 5210 | ? | 0 | 4096 | N1 | NULL | NULL | N1.SI | 4 | 9 | MC_SI_TRST +SPPTERM | 2 | IV_TRUE | RW_IBUF | IV_TRUE | AUTOCONFIG_IN_PROGRESS +OUTPUT_NODE_TYPE | 0 | 10 | BUF_OUT +NODE | N1.BUFOE.OUT | 5209 | ? | 0 | 0 | N1 | NULL | NULL | N1.BUFOE | 0 | 10 | BUF_OUT + +MACROCELL_INSTANCE | PinTrst+OptxMapped | N1$BUF0 | LAN_IDE_CP_COPY_0_COPY_0 | 2155888640 | 2 | 2 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTOCONFIG_IN_PROGRESS | 4959 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTOCONFIG_IN_PROGRESS.Q | AUTOCONFIG_IN_PROGRESS | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 0 | 0 | MC_Q +NODE | N1$BUF0 | 4977 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | N1$BUF0.Q | N1$BUF0 | 0 | 0 | MC_Q +OUTPUT_NODE_TYPE | 2 | 0 | MC_OE +NODE | N1$BUF0$OE | 4978 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | N1$BUF0.BUFOE.OUT | N1$BUF0 | 2 | 0 | MC_OE + +SIGNAL_INSTANCE | N1$BUF0.SI | N1$BUF0 | 0 | 2 | 3 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTOCONFIG_IN_PROGRESS | 4959 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTOCONFIG_IN_PROGRESS.Q | AUTOCONFIG_IN_PROGRESS | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | N1$BUF0.D1 | 5213 | ? | 0 | 4096 | N1$BUF0 | NULL | NULL | N1$BUF0.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | N1$BUF0.D2 | 5214 | ? | 0 | 6144 | N1$BUF0 | NULL | NULL | N1$BUF0.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 0 | IV_DC +OUTPUT_NODE_TYPE | 4 | 9 | MC_SI_TRST +SIGNAL | NODE | N1$BUF0.TRST | 5216 | ? | 0 | 4096 | N1$BUF0 | NULL | NULL | N1$BUF0.SI | 4 | 9 | MC_SI_TRST +SPPTERM | 2 | IV_TRUE | RW_IBUF | IV_TRUE | AUTOCONFIG_IN_PROGRESS + +SRFF_INSTANCE | N1$BUF0.REG | N1$BUF0 | 0 | 1 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | N1$BUF0.D | 5212 | ? | 0 | 0 | N1$BUF0 | NULL | NULL | N1$BUF0.XOR | 0 | 7 | ALU_F +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | N1$BUF0.Q | 5217 | ? | 0 | 0 | N1$BUF0 | NULL | NULL | N1$BUF0.REG | 0 | 8 | SRFF_Q + +BUF_INSTANCE | N1$BUF0.BUFOE | N1$BUF0 | 0 | 1 | 1 +INPUT_NODE_TYPE | 0 | 10 | CTOR_UNKNOWN +SIGNAL | NODE | N1$BUF0.TRST | 5216 | ? | 0 | 4096 | N1$BUF0 | NULL | NULL | N1$BUF0.SI | 4 | 9 | MC_SI_TRST +SPPTERM | 2 | IV_TRUE | RW_IBUF | IV_TRUE | AUTOCONFIG_IN_PROGRESS +OUTPUT_NODE_TYPE | 0 | 10 | BUF_OUT +NODE | N1$BUF0.BUFOE.OUT | 5215 | ? | 0 | 0 | N1$BUF0 | NULL | NULL | N1$BUF0.BUFOE | 0 | 10 | BUF_OUT + +MACROCELL_INSTANCE | PinTrst+OptxMapped | N1$BUF1 | LAN_IDE_CP_COPY_0_COPY_0 | 2155888640 | 3 | 3 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTOCONFIG_IN_PROGRESS | 4959 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTOCONFIG_IN_PROGRESS.Q | AUTOCONFIG_IN_PROGRESS | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_13_IBUF | 5007 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_13_IBUF | 0 | 5 | II_IMUX +OUTPUT_NODE_TYPE | 0 | 0 | MC_Q +NODE | N1$BUF1 | 4979 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | N1$BUF1.Q | N1$BUF1 | 0 | 0 | MC_Q +OUTPUT_NODE_TYPE | 4 | 0 | MC_EXPORT +NODE | N1$BUF1.EXP | 5354 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | N1$BUF1.EXP | N1$BUF1 | 4 | 0 | MC_EXPORT +OUTPUT_NODE_TYPE | 2 | 0 | MC_OE +NODE | N1$BUF1$OE | 4980 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | N1$BUF1.BUFOE.OUT | N1$BUF1 | 2 | 0 | MC_OE + +SIGNAL_INSTANCE | N1$BUF1.SI | N1$BUF1 | 0 | 3 | 4 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTOCONFIG_IN_PROGRESS | 4959 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTOCONFIG_IN_PROGRESS.Q | AUTOCONFIG_IN_PROGRESS | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_13_IBUF | 5007 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_13_IBUF | 0 | 5 | II_IMUX +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | N1$BUF1.D1 | 5219 | ? | 0 | 4096 | N1$BUF1 | NULL | NULL | N1$BUF1.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | N1$BUF1.D2 | 5220 | ? | 0 | 6144 | N1$BUF1 | NULL | NULL | N1$BUF1.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 0 | IV_DC +OUTPUT_NODE_TYPE | 4 | 9 | MC_SI_TRST +SIGNAL | NODE | N1$BUF1.TRST | 5222 | ? | 0 | 4096 | N1$BUF1 | NULL | NULL | N1$BUF1.SI | 4 | 9 | MC_SI_TRST +SPPTERM | 2 | IV_TRUE | RW_IBUF | IV_TRUE | AUTOCONFIG_IN_PROGRESS +OUTPUT_NODE_TYPE | 7 | 9 | MC_SI_EXPORT +SIGNAL | NODE | N1$BUF1.EXP | 5349 | ? | 0 | 0 | N1$BUF1 | NULL | NULL | N1$BUF1.SI | 7 | 9 | MC_SI_EXPORT +SPPTERM | 1 | IV_FALSE | A_13_IBUF + +SRFF_INSTANCE | N1$BUF1.REG | N1$BUF1 | 0 | 1 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | N1$BUF1.D | 5218 | ? | 0 | 0 | N1$BUF1 | NULL | NULL | N1$BUF1.XOR | 0 | 7 | ALU_F +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | N1$BUF1.Q | 5223 | ? | 0 | 0 | N1$BUF1 | NULL | NULL | N1$BUF1.REG | 0 | 8 | SRFF_Q + +BUF_INSTANCE | N1$BUF1.BUFOE | N1$BUF1 | 0 | 1 | 1 +INPUT_NODE_TYPE | 0 | 10 | CTOR_UNKNOWN +SIGNAL | NODE | N1$BUF1.TRST | 5222 | ? | 0 | 4096 | N1$BUF1 | NULL | NULL | N1$BUF1.SI | 4 | 9 | MC_SI_TRST +SPPTERM | 2 | IV_TRUE | RW_IBUF | IV_TRUE | AUTOCONFIG_IN_PROGRESS +OUTPUT_NODE_TYPE | 0 | 10 | BUF_OUT +NODE | N1$BUF1.BUFOE.OUT | 5221 | ? | 0 | 0 | N1$BUF1 | NULL | NULL | N1$BUF1.BUFOE | 0 | 10 | BUF_OUT + +MACROCELL_INSTANCE | PinTrst+OptxMapped | N1$BUF10 | LAN_IDE_CP_COPY_0_COPY_0 | 2155888640 | 2 | 2 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTOCONFIG_IN_PROGRESS | 4959 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTOCONFIG_IN_PROGRESS.Q | AUTOCONFIG_IN_PROGRESS | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 0 | 0 | MC_Q +NODE | N1$BUF10 | 4981 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | N1$BUF10.Q | N1$BUF10 | 0 | 0 | MC_Q +OUTPUT_NODE_TYPE | 2 | 0 | MC_OE +NODE | N1$BUF10$OE | 4982 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | N1$BUF10.BUFOE.OUT | N1$BUF10 | 2 | 0 | MC_OE + +SIGNAL_INSTANCE | N1$BUF10.SI | N1$BUF10 | 0 | 2 | 3 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTOCONFIG_IN_PROGRESS | 4959 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTOCONFIG_IN_PROGRESS.Q | AUTOCONFIG_IN_PROGRESS | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | N1$BUF10.D1 | 5225 | ? | 0 | 4096 | N1$BUF10 | NULL | NULL | N1$BUF10.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | N1$BUF10.D2 | 5226 | ? | 0 | 6144 | N1$BUF10 | NULL | NULL | N1$BUF10.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 0 | IV_DC +OUTPUT_NODE_TYPE | 4 | 9 | MC_SI_TRST +SIGNAL | NODE | N1$BUF10.TRST | 5228 | ? | 0 | 4096 | N1$BUF10 | NULL | NULL | N1$BUF10.SI | 4 | 9 | MC_SI_TRST +SPPTERM | 2 | IV_TRUE | RW_IBUF | IV_TRUE | AUTOCONFIG_IN_PROGRESS + +SRFF_INSTANCE | N1$BUF10.REG | N1$BUF10 | 0 | 1 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | N1$BUF10.D | 5224 | ? | 0 | 0 | N1$BUF10 | NULL | NULL | N1$BUF10.XOR | 0 | 7 | ALU_F +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | N1$BUF10.Q | 5229 | ? | 0 | 0 | N1$BUF10 | NULL | NULL | N1$BUF10.REG | 0 | 8 | SRFF_Q + +BUF_INSTANCE | N1$BUF10.BUFOE | N1$BUF10 | 0 | 1 | 1 +INPUT_NODE_TYPE | 0 | 10 | CTOR_UNKNOWN +SIGNAL | NODE | N1$BUF10.TRST | 5228 | ? | 0 | 4096 | N1$BUF10 | NULL | NULL | N1$BUF10.SI | 4 | 9 | MC_SI_TRST +SPPTERM | 2 | IV_TRUE | RW_IBUF | IV_TRUE | AUTOCONFIG_IN_PROGRESS +OUTPUT_NODE_TYPE | 0 | 10 | BUF_OUT +NODE | N1$BUF10.BUFOE.OUT | 5227 | ? | 0 | 0 | N1$BUF10 | NULL | NULL | N1$BUF10.BUFOE | 0 | 10 | BUF_OUT + +MACROCELL_INSTANCE | PinTrst+OptxMapped | N1$BUF2 | LAN_IDE_CP_COPY_0_COPY_0 | 2155888640 | 14 | 3 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTOCONFIG_IN_PROGRESS | 4959 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTOCONFIG_IN_PROGRESS.Q | AUTOCONFIG_IN_PROGRESS | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_5_IBUF | 4927 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_4_IBUF | 4928 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_4_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_3_IBUF | 4931 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_2_IBUF | 4932 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<2> | 4939 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<2>.Q | AUTO_CONFIG_DONE<2> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | autoconfig | 4957 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.Q | autoconfig | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_1_IBUF | 4929 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_6_IBUF | 4930 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_6_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<1> | 4938 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<1>.Q | AUTO_CONFIG_DONE<1> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<0> | 4937 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<0>.Q | AUTO_CONFIG_DONE<0> | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 0 | 0 | MC_Q +NODE | N1$BUF2 | 4983 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | N1$BUF2.Q | N1$BUF2 | 0 | 0 | MC_Q +OUTPUT_NODE_TYPE | 4 | 0 | MC_EXPORT +NODE | N1$BUF2.EXP | 5372 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | N1$BUF2.EXP | N1$BUF2 | 4 | 0 | MC_EXPORT +OUTPUT_NODE_TYPE | 2 | 0 | MC_OE +NODE | N1$BUF2$OE | 4984 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | N1$BUF2.BUFOE.OUT | N1$BUF2 | 2 | 0 | MC_OE + +SIGNAL_INSTANCE | N1$BUF2.SI | N1$BUF2 | 0 | 14 | 4 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTOCONFIG_IN_PROGRESS | 4959 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTOCONFIG_IN_PROGRESS.Q | AUTOCONFIG_IN_PROGRESS | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_5_IBUF | 4927 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_4_IBUF | 4928 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_4_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_3_IBUF | 4931 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_2_IBUF | 4932 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<2> | 4939 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<2>.Q | AUTO_CONFIG_DONE<2> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | autoconfig | 4957 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.Q | autoconfig | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_1_IBUF | 4929 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_6_IBUF | 4930 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_6_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<1> | 4938 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<1>.Q | AUTO_CONFIG_DONE<1> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<0> | 4937 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<0>.Q | AUTO_CONFIG_DONE<0> | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | N1$BUF2.D1 | 5231 | ? | 0 | 4096 | N1$BUF2 | NULL | NULL | N1$BUF2.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | N1$BUF2.D2 | 5232 | ? | 0 | 6144 | N1$BUF2 | NULL | NULL | N1$BUF2.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 0 | IV_DC +OUTPUT_NODE_TYPE | 4 | 9 | MC_SI_TRST +SIGNAL | NODE | N1$BUF2.TRST | 5234 | ? | 0 | 4096 | N1$BUF2 | NULL | NULL | N1$BUF2.SI | 4 | 9 | MC_SI_TRST +SPPTERM | 2 | IV_TRUE | RW_IBUF | IV_TRUE | AUTOCONFIG_IN_PROGRESS +OUTPUT_NODE_TYPE | 7 | 9 | MC_SI_EXPORT +SIGNAL | NODE | N1$BUF2.EXP | 5364 | ? | 0 | 0 | N1$BUF2 | NULL | NULL | N1$BUF2.SI | 7 | 9 | MC_SI_EXPORT +SPPTERM | 9 | IV_TRUE | RESET_IBUF | IV_TRUE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_FALSE | A_4_IBUF | IV_FALSE | A_3_IBUF | IV_FALSE | A_2_IBUF | IV_FALSE | AUTO_CONFIG_DONE<2> | IV_TRUE | autoconfig +SPPTERM | 10 | IV_TRUE | RESET_IBUF | IV_TRUE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_FALSE | A_4_IBUF | IV_TRUE | A_1_IBUF | IV_FALSE | A_6_IBUF | IV_FALSE | A_3_IBUF | IV_FALSE | AUTO_CONFIG_DONE<1> | IV_TRUE | autoconfig +SPPTERM | 10 | IV_TRUE | RESET_IBUF | IV_TRUE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_TRUE | A_1_IBUF | IV_FALSE | A_6_IBUF | IV_FALSE | A_3_IBUF | IV_FALSE | A_2_IBUF | IV_FALSE | AUTO_CONFIG_DONE<0> | IV_TRUE | autoconfig +SPPTERM | 11 | IV_TRUE | RESET_IBUF | IV_TRUE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_TRUE | A_4_IBUF | IV_FALSE | A_1_IBUF | IV_FALSE | A_6_IBUF | IV_TRUE | A_2_IBUF | IV_TRUE | AUTO_CONFIG_DONE<0> | IV_FALSE | AUTO_CONFIG_DONE<1> | IV_TRUE | autoconfig + +SRFF_INSTANCE | N1$BUF2.REG | N1$BUF2 | 0 | 1 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | N1$BUF2.D | 5230 | ? | 0 | 0 | N1$BUF2 | NULL | NULL | N1$BUF2.XOR | 0 | 7 | ALU_F +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | N1$BUF2.Q | 5235 | ? | 0 | 0 | N1$BUF2 | NULL | NULL | N1$BUF2.REG | 0 | 8 | SRFF_Q + +BUF_INSTANCE | N1$BUF2.BUFOE | N1$BUF2 | 0 | 1 | 1 +INPUT_NODE_TYPE | 0 | 10 | CTOR_UNKNOWN +SIGNAL | NODE | N1$BUF2.TRST | 5234 | ? | 0 | 4096 | N1$BUF2 | NULL | NULL | N1$BUF2.SI | 4 | 9 | MC_SI_TRST +SPPTERM | 2 | IV_TRUE | RW_IBUF | IV_TRUE | AUTOCONFIG_IN_PROGRESS +OUTPUT_NODE_TYPE | 0 | 10 | BUF_OUT +NODE | N1$BUF2.BUFOE.OUT | 5233 | ? | 0 | 0 | N1$BUF2 | NULL | NULL | N1$BUF2.BUFOE | 0 | 10 | BUF_OUT + +MACROCELL_INSTANCE | PinTrst+OptxMapped | N1$BUF3 | LAN_IDE_CP_COPY_0_COPY_0 | 2155888640 | 2 | 2 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTOCONFIG_IN_PROGRESS | 4959 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTOCONFIG_IN_PROGRESS.Q | AUTOCONFIG_IN_PROGRESS | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 0 | 0 | MC_Q +NODE | N1$BUF3 | 4985 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | N1$BUF3.Q | N1$BUF3 | 0 | 0 | MC_Q +OUTPUT_NODE_TYPE | 2 | 0 | MC_OE +NODE | N1$BUF3$OE | 4986 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | N1$BUF3.BUFOE.OUT | N1$BUF3 | 2 | 0 | MC_OE + +SIGNAL_INSTANCE | N1$BUF3.SI | N1$BUF3 | 0 | 2 | 3 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTOCONFIG_IN_PROGRESS | 4959 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTOCONFIG_IN_PROGRESS.Q | AUTOCONFIG_IN_PROGRESS | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | N1$BUF3.D1 | 5237 | ? | 0 | 4096 | N1$BUF3 | NULL | NULL | N1$BUF3.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | N1$BUF3.D2 | 5238 | ? | 0 | 6144 | N1$BUF3 | NULL | NULL | N1$BUF3.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 0 | IV_DC +OUTPUT_NODE_TYPE | 4 | 9 | MC_SI_TRST +SIGNAL | NODE | N1$BUF3.TRST | 5240 | ? | 0 | 4096 | N1$BUF3 | NULL | NULL | N1$BUF3.SI | 4 | 9 | MC_SI_TRST +SPPTERM | 2 | IV_TRUE | RW_IBUF | IV_TRUE | AUTOCONFIG_IN_PROGRESS + +SRFF_INSTANCE | N1$BUF3.REG | N1$BUF3 | 0 | 1 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | N1$BUF3.D | 5236 | ? | 0 | 0 | N1$BUF3 | NULL | NULL | N1$BUF3.XOR | 0 | 7 | ALU_F +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | N1$BUF3.Q | 5241 | ? | 0 | 0 | N1$BUF3 | NULL | NULL | N1$BUF3.REG | 0 | 8 | SRFF_Q + +BUF_INSTANCE | N1$BUF3.BUFOE | N1$BUF3 | 0 | 1 | 1 +INPUT_NODE_TYPE | 0 | 10 | CTOR_UNKNOWN +SIGNAL | NODE | N1$BUF3.TRST | 5240 | ? | 0 | 4096 | N1$BUF3 | NULL | NULL | N1$BUF3.SI | 4 | 9 | MC_SI_TRST +SPPTERM | 2 | IV_TRUE | RW_IBUF | IV_TRUE | AUTOCONFIG_IN_PROGRESS +OUTPUT_NODE_TYPE | 0 | 10 | BUF_OUT +NODE | N1$BUF3.BUFOE.OUT | 5239 | ? | 0 | 0 | N1$BUF3 | NULL | NULL | N1$BUF3.BUFOE | 0 | 10 | BUF_OUT + +MACROCELL_INSTANCE | PinTrst+OptxMapped | N1$BUF4 | LAN_IDE_CP_COPY_0_COPY_0 | 2155888640 | 2 | 2 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTOCONFIG_IN_PROGRESS | 4959 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTOCONFIG_IN_PROGRESS.Q | AUTOCONFIG_IN_PROGRESS | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 0 | 0 | MC_Q +NODE | N1$BUF4 | 4987 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | N1$BUF4.Q | N1$BUF4 | 0 | 0 | MC_Q +OUTPUT_NODE_TYPE | 2 | 0 | MC_OE +NODE | N1$BUF4$OE | 4988 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | N1$BUF4.BUFOE.OUT | N1$BUF4 | 2 | 0 | MC_OE + +SIGNAL_INSTANCE | N1$BUF4.SI | N1$BUF4 | 0 | 2 | 3 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTOCONFIG_IN_PROGRESS | 4959 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTOCONFIG_IN_PROGRESS.Q | AUTOCONFIG_IN_PROGRESS | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | N1$BUF4.D1 | 5243 | ? | 0 | 4096 | N1$BUF4 | NULL | NULL | N1$BUF4.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | N1$BUF4.D2 | 5244 | ? | 0 | 6144 | N1$BUF4 | NULL | NULL | N1$BUF4.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 0 | IV_DC +OUTPUT_NODE_TYPE | 4 | 9 | MC_SI_TRST +SIGNAL | NODE | N1$BUF4.TRST | 5246 | ? | 0 | 4096 | N1$BUF4 | NULL | NULL | N1$BUF4.SI | 4 | 9 | MC_SI_TRST +SPPTERM | 2 | IV_TRUE | RW_IBUF | IV_TRUE | AUTOCONFIG_IN_PROGRESS + +SRFF_INSTANCE | N1$BUF4.REG | N1$BUF4 | 0 | 1 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | N1$BUF4.D | 5242 | ? | 0 | 0 | N1$BUF4 | NULL | NULL | N1$BUF4.XOR | 0 | 7 | ALU_F +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | N1$BUF4.Q | 5247 | ? | 0 | 0 | N1$BUF4 | NULL | NULL | N1$BUF4.REG | 0 | 8 | SRFF_Q + +BUF_INSTANCE | N1$BUF4.BUFOE | N1$BUF4 | 0 | 1 | 1 +INPUT_NODE_TYPE | 0 | 10 | CTOR_UNKNOWN +SIGNAL | NODE | N1$BUF4.TRST | 5246 | ? | 0 | 4096 | N1$BUF4 | NULL | NULL | N1$BUF4.SI | 4 | 9 | MC_SI_TRST +SPPTERM | 2 | IV_TRUE | RW_IBUF | IV_TRUE | AUTOCONFIG_IN_PROGRESS +OUTPUT_NODE_TYPE | 0 | 10 | BUF_OUT +NODE | N1$BUF4.BUFOE.OUT | 5245 | ? | 0 | 0 | N1$BUF4 | NULL | NULL | N1$BUF4.BUFOE | 0 | 10 | BUF_OUT + +MACROCELL_INSTANCE | PinTrst+OptxMapped | N1$BUF5 | LAN_IDE_CP_COPY_0_COPY_0 | 2155888640 | 2 | 2 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTOCONFIG_IN_PROGRESS | 4959 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTOCONFIG_IN_PROGRESS.Q | AUTOCONFIG_IN_PROGRESS | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 0 | 0 | MC_Q +NODE | N1$BUF5 | 4989 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | N1$BUF5.Q | N1$BUF5 | 0 | 0 | MC_Q +OUTPUT_NODE_TYPE | 2 | 0 | MC_OE +NODE | N1$BUF5$OE | 4990 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | N1$BUF5.BUFOE.OUT | N1$BUF5 | 2 | 0 | MC_OE + +SIGNAL_INSTANCE | N1$BUF5.SI | N1$BUF5 | 0 | 2 | 3 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTOCONFIG_IN_PROGRESS | 4959 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTOCONFIG_IN_PROGRESS.Q | AUTOCONFIG_IN_PROGRESS | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | N1$BUF5.D1 | 5249 | ? | 0 | 4096 | N1$BUF5 | NULL | NULL | N1$BUF5.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | N1$BUF5.D2 | 5250 | ? | 0 | 6144 | N1$BUF5 | NULL | NULL | N1$BUF5.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 0 | IV_DC +OUTPUT_NODE_TYPE | 4 | 9 | MC_SI_TRST +SIGNAL | NODE | N1$BUF5.TRST | 5252 | ? | 0 | 4096 | N1$BUF5 | NULL | NULL | N1$BUF5.SI | 4 | 9 | MC_SI_TRST +SPPTERM | 2 | IV_TRUE | RW_IBUF | IV_TRUE | AUTOCONFIG_IN_PROGRESS + +SRFF_INSTANCE | N1$BUF5.REG | N1$BUF5 | 0 | 1 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | N1$BUF5.D | 5248 | ? | 0 | 0 | N1$BUF5 | NULL | NULL | N1$BUF5.XOR | 0 | 7 | ALU_F +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | N1$BUF5.Q | 5253 | ? | 0 | 0 | N1$BUF5 | NULL | NULL | N1$BUF5.REG | 0 | 8 | SRFF_Q + +BUF_INSTANCE | N1$BUF5.BUFOE | N1$BUF5 | 0 | 1 | 1 +INPUT_NODE_TYPE | 0 | 10 | CTOR_UNKNOWN +SIGNAL | NODE | N1$BUF5.TRST | 5252 | ? | 0 | 4096 | N1$BUF5 | NULL | NULL | N1$BUF5.SI | 4 | 9 | MC_SI_TRST +SPPTERM | 2 | IV_TRUE | RW_IBUF | IV_TRUE | AUTOCONFIG_IN_PROGRESS +OUTPUT_NODE_TYPE | 0 | 10 | BUF_OUT +NODE | N1$BUF5.BUFOE.OUT | 5251 | ? | 0 | 0 | N1$BUF5 | NULL | NULL | N1$BUF5.BUFOE | 0 | 10 | BUF_OUT + +MACROCELL_INSTANCE | PinTrst+OptxMapped | N1$BUF6 | LAN_IDE_CP_COPY_0_COPY_0 | 2155888640 | 2 | 2 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTOCONFIG_IN_PROGRESS | 4959 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTOCONFIG_IN_PROGRESS.Q | AUTOCONFIG_IN_PROGRESS | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 0 | 0 | MC_Q +NODE | N1$BUF6 | 4991 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | N1$BUF6.Q | N1$BUF6 | 0 | 0 | MC_Q +OUTPUT_NODE_TYPE | 2 | 0 | MC_OE +NODE | N1$BUF6$OE | 4992 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | N1$BUF6.BUFOE.OUT | N1$BUF6 | 2 | 0 | MC_OE + +SIGNAL_INSTANCE | N1$BUF6.SI | N1$BUF6 | 0 | 2 | 3 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTOCONFIG_IN_PROGRESS | 4959 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTOCONFIG_IN_PROGRESS.Q | AUTOCONFIG_IN_PROGRESS | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | N1$BUF6.D1 | 5255 | ? | 0 | 4096 | N1$BUF6 | NULL | NULL | N1$BUF6.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | N1$BUF6.D2 | 5256 | ? | 0 | 6144 | N1$BUF6 | NULL | NULL | N1$BUF6.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 0 | IV_DC +OUTPUT_NODE_TYPE | 4 | 9 | MC_SI_TRST +SIGNAL | NODE | N1$BUF6.TRST | 5258 | ? | 0 | 4096 | N1$BUF6 | NULL | NULL | N1$BUF6.SI | 4 | 9 | MC_SI_TRST +SPPTERM | 2 | IV_TRUE | RW_IBUF | IV_TRUE | AUTOCONFIG_IN_PROGRESS + +SRFF_INSTANCE | N1$BUF6.REG | N1$BUF6 | 0 | 1 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | N1$BUF6.D | 5254 | ? | 0 | 0 | N1$BUF6 | NULL | NULL | N1$BUF6.XOR | 0 | 7 | ALU_F +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | N1$BUF6.Q | 5259 | ? | 0 | 0 | N1$BUF6 | NULL | NULL | N1$BUF6.REG | 0 | 8 | SRFF_Q + +BUF_INSTANCE | N1$BUF6.BUFOE | N1$BUF6 | 0 | 1 | 1 +INPUT_NODE_TYPE | 0 | 10 | CTOR_UNKNOWN +SIGNAL | NODE | N1$BUF6.TRST | 5258 | ? | 0 | 4096 | N1$BUF6 | NULL | NULL | N1$BUF6.SI | 4 | 9 | MC_SI_TRST +SPPTERM | 2 | IV_TRUE | RW_IBUF | IV_TRUE | AUTOCONFIG_IN_PROGRESS +OUTPUT_NODE_TYPE | 0 | 10 | BUF_OUT +NODE | N1$BUF6.BUFOE.OUT | 5257 | ? | 0 | 0 | N1$BUF6 | NULL | NULL | N1$BUF6.BUFOE | 0 | 10 | BUF_OUT + +MACROCELL_INSTANCE | PinTrst+OptxMapped | N1$BUF7 | LAN_IDE_CP_COPY_0_COPY_0 | 2155888640 | 2 | 2 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTOCONFIG_IN_PROGRESS | 4959 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTOCONFIG_IN_PROGRESS.Q | AUTOCONFIG_IN_PROGRESS | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 0 | 0 | MC_Q +NODE | N1$BUF7 | 4993 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | N1$BUF7.Q | N1$BUF7 | 0 | 0 | MC_Q +OUTPUT_NODE_TYPE | 2 | 0 | MC_OE +NODE | N1$BUF7$OE | 4994 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | N1$BUF7.BUFOE.OUT | N1$BUF7 | 2 | 0 | MC_OE + +SIGNAL_INSTANCE | N1$BUF7.SI | N1$BUF7 | 0 | 2 | 3 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTOCONFIG_IN_PROGRESS | 4959 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTOCONFIG_IN_PROGRESS.Q | AUTOCONFIG_IN_PROGRESS | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | N1$BUF7.D1 | 5261 | ? | 0 | 4096 | N1$BUF7 | NULL | NULL | N1$BUF7.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | N1$BUF7.D2 | 5262 | ? | 0 | 6144 | N1$BUF7 | NULL | NULL | N1$BUF7.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 0 | IV_DC +OUTPUT_NODE_TYPE | 4 | 9 | MC_SI_TRST +SIGNAL | NODE | N1$BUF7.TRST | 5264 | ? | 0 | 4096 | N1$BUF7 | NULL | NULL | N1$BUF7.SI | 4 | 9 | MC_SI_TRST +SPPTERM | 2 | IV_TRUE | RW_IBUF | IV_TRUE | AUTOCONFIG_IN_PROGRESS + +SRFF_INSTANCE | N1$BUF7.REG | N1$BUF7 | 0 | 1 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | N1$BUF7.D | 5260 | ? | 0 | 0 | N1$BUF7 | NULL | NULL | N1$BUF7.XOR | 0 | 7 | ALU_F +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | N1$BUF7.Q | 5265 | ? | 0 | 0 | N1$BUF7 | NULL | NULL | N1$BUF7.REG | 0 | 8 | SRFF_Q + +BUF_INSTANCE | N1$BUF7.BUFOE | N1$BUF7 | 0 | 1 | 1 +INPUT_NODE_TYPE | 0 | 10 | CTOR_UNKNOWN +SIGNAL | NODE | N1$BUF7.TRST | 5264 | ? | 0 | 4096 | N1$BUF7 | NULL | NULL | N1$BUF7.SI | 4 | 9 | MC_SI_TRST +SPPTERM | 2 | IV_TRUE | RW_IBUF | IV_TRUE | AUTOCONFIG_IN_PROGRESS +OUTPUT_NODE_TYPE | 0 | 10 | BUF_OUT +NODE | N1$BUF7.BUFOE.OUT | 5263 | ? | 0 | 0 | N1$BUF7 | NULL | NULL | N1$BUF7.BUFOE | 0 | 10 | BUF_OUT + +MACROCELL_INSTANCE | PinTrst+OptxMapped | N1$BUF8 | LAN_IDE_CP_COPY_0_COPY_0 | 2155888640 | 2 | 2 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTOCONFIG_IN_PROGRESS | 4959 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTOCONFIG_IN_PROGRESS.Q | AUTOCONFIG_IN_PROGRESS | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 0 | 0 | MC_Q +NODE | N1$BUF8 | 4995 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | N1$BUF8.Q | N1$BUF8 | 0 | 0 | MC_Q +OUTPUT_NODE_TYPE | 2 | 0 | MC_OE +NODE | N1$BUF8$OE | 4996 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | N1$BUF8.BUFOE.OUT | N1$BUF8 | 2 | 0 | MC_OE + +SIGNAL_INSTANCE | N1$BUF8.SI | N1$BUF8 | 0 | 2 | 3 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTOCONFIG_IN_PROGRESS | 4959 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTOCONFIG_IN_PROGRESS.Q | AUTOCONFIG_IN_PROGRESS | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | N1$BUF8.D1 | 5267 | ? | 0 | 4096 | N1$BUF8 | NULL | NULL | N1$BUF8.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | N1$BUF8.D2 | 5268 | ? | 0 | 6144 | N1$BUF8 | NULL | NULL | N1$BUF8.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 0 | IV_DC +OUTPUT_NODE_TYPE | 4 | 9 | MC_SI_TRST +SIGNAL | NODE | N1$BUF8.TRST | 5270 | ? | 0 | 4096 | N1$BUF8 | NULL | NULL | N1$BUF8.SI | 4 | 9 | MC_SI_TRST +SPPTERM | 2 | IV_TRUE | RW_IBUF | IV_TRUE | AUTOCONFIG_IN_PROGRESS + +SRFF_INSTANCE | N1$BUF8.REG | N1$BUF8 | 0 | 1 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | N1$BUF8.D | 5266 | ? | 0 | 0 | N1$BUF8 | NULL | NULL | N1$BUF8.XOR | 0 | 7 | ALU_F +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | N1$BUF8.Q | 5271 | ? | 0 | 0 | N1$BUF8 | NULL | NULL | N1$BUF8.REG | 0 | 8 | SRFF_Q + +BUF_INSTANCE | N1$BUF8.BUFOE | N1$BUF8 | 0 | 1 | 1 +INPUT_NODE_TYPE | 0 | 10 | CTOR_UNKNOWN +SIGNAL | NODE | N1$BUF8.TRST | 5270 | ? | 0 | 4096 | N1$BUF8 | NULL | NULL | N1$BUF8.SI | 4 | 9 | MC_SI_TRST +SPPTERM | 2 | IV_TRUE | RW_IBUF | IV_TRUE | AUTOCONFIG_IN_PROGRESS +OUTPUT_NODE_TYPE | 0 | 10 | BUF_OUT +NODE | N1$BUF8.BUFOE.OUT | 5269 | ? | 0 | 0 | N1$BUF8 | NULL | NULL | N1$BUF8.BUFOE | 0 | 10 | BUF_OUT + +MACROCELL_INSTANCE | PinTrst+OptxMapped | N1$BUF9 | LAN_IDE_CP_COPY_0_COPY_0 | 2155888640 | 2 | 2 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTOCONFIG_IN_PROGRESS | 4959 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTOCONFIG_IN_PROGRESS.Q | AUTOCONFIG_IN_PROGRESS | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 0 | 0 | MC_Q +NODE | N1$BUF9 | 4997 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | N1$BUF9.Q | N1$BUF9 | 0 | 0 | MC_Q +OUTPUT_NODE_TYPE | 2 | 0 | MC_OE +NODE | N1$BUF9$OE | 4998 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | N1$BUF9.BUFOE.OUT | N1$BUF9 | 2 | 0 | MC_OE + +SIGNAL_INSTANCE | N1$BUF9.SI | N1$BUF9 | 0 | 2 | 3 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTOCONFIG_IN_PROGRESS | 4959 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTOCONFIG_IN_PROGRESS.Q | AUTOCONFIG_IN_PROGRESS | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | N1$BUF9.D1 | 5273 | ? | 0 | 4096 | N1$BUF9 | NULL | NULL | N1$BUF9.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | N1$BUF9.D2 | 5274 | ? | 0 | 6144 | N1$BUF9 | NULL | NULL | N1$BUF9.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 0 | IV_DC +OUTPUT_NODE_TYPE | 4 | 9 | MC_SI_TRST +SIGNAL | NODE | N1$BUF9.TRST | 5276 | ? | 0 | 4096 | N1$BUF9 | NULL | NULL | N1$BUF9.SI | 4 | 9 | MC_SI_TRST +SPPTERM | 2 | IV_TRUE | RW_IBUF | IV_TRUE | AUTOCONFIG_IN_PROGRESS + +SRFF_INSTANCE | N1$BUF9.REG | N1$BUF9 | 0 | 1 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | N1$BUF9.D | 5272 | ? | 0 | 0 | N1$BUF9 | NULL | NULL | N1$BUF9.XOR | 0 | 7 | ALU_F +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | N1$BUF9.Q | 5277 | ? | 0 | 0 | N1$BUF9 | NULL | NULL | N1$BUF9.REG | 0 | 8 | SRFF_Q + +BUF_INSTANCE | N1$BUF9.BUFOE | N1$BUF9 | 0 | 1 | 1 +INPUT_NODE_TYPE | 0 | 10 | CTOR_UNKNOWN +SIGNAL | NODE | N1$BUF9.TRST | 5276 | ? | 0 | 4096 | N1$BUF9 | NULL | NULL | N1$BUF9.SI | 4 | 9 | MC_SI_TRST +SPPTERM | 2 | IV_TRUE | RW_IBUF | IV_TRUE | AUTOCONFIG_IN_PROGRESS +OUTPUT_NODE_TYPE | 0 | 10 | BUF_OUT +NODE | N1$BUF9.BUFOE.OUT | 5275 | ? | 0 | 0 | N1$BUF9 | NULL | NULL | N1$BUF9.BUFOE | 0 | 10 | BUF_OUT + +INPUT_INSTANCE | 0 | 0 | NULL | IDE_A_0_OBUF | LAN_IDE_CP_COPY_0_COPY_0 | 16 | 1 | 1 +INPUT_NODE_TYPE | 0 | 5 | II_IN +NODE | A<9> | 5063 | PI | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE +OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX +NODE | IDE_A_0_OBUF | 4999 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | IDE_A_0_OBUF | 0 | 5 | II_IMUX + +MACROCELL_INSTANCE | OptxMapped | IDE_A_0_OBUF$BUF0 | LAN_IDE_CP_COPY_0_COPY_0 | 2155872256 | 1 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | IDE_A_0_OBUF | 4999 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | IDE_A_0_OBUF | 0 | 5 | II_IMUX +OUTPUT_NODE_TYPE | 0 | 0 | MC_Q +NODE | IDE_A_0_OBUF$BUF0 | 5000 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_A_0_OBUF$BUF0.Q | IDE_A_0_OBUF$BUF0 | 0 | 0 | MC_Q + +SIGNAL_INSTANCE | IDE_A_0_OBUF$BUF0.SI | IDE_A_0_OBUF$BUF0 | 0 | 1 | 2 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | IDE_A_0_OBUF | 4999 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | IDE_A_0_OBUF | 0 | 5 | II_IMUX +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | IDE_A_0_OBUF$BUF0.D1 | 5279 | ? | 0 | 4096 | IDE_A_0_OBUF$BUF0 | NULL | NULL | IDE_A_0_OBUF$BUF0.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | IDE_A_0_OBUF$BUF0.D2 | 5280 | ? | 0 | 4096 | IDE_A_0_OBUF$BUF0 | NULL | NULL | IDE_A_0_OBUF$BUF0.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 1 | IV_TRUE | IDE_A_0_OBUF + +SRFF_INSTANCE | IDE_A_0_OBUF$BUF0.REG | IDE_A_0_OBUF$BUF0 | 0 | 1 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | IDE_A_0_OBUF$BUF0.D | 5278 | ? | 0 | 0 | IDE_A_0_OBUF$BUF0 | NULL | NULL | IDE_A_0_OBUF$BUF0.XOR | 0 | 7 | ALU_F +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | IDE_A_0_OBUF$BUF0.Q | 5281 | ? | 0 | 0 | IDE_A_0_OBUF$BUF0 | NULL | NULL | IDE_A_0_OBUF$BUF0.REG | 0 | 8 | SRFF_Q + +INPUT_INSTANCE | 0 | 0 | NULL | IDE_A_1_OBUF | LAN_IDE_CP_COPY_0_COPY_0 | 16 | 1 | 1 +INPUT_NODE_TYPE | 0 | 5 | II_IN +NODE | A<10> | 5064 | PI | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE +OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX +NODE | IDE_A_1_OBUF | 5001 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | IDE_A_1_OBUF | 0 | 5 | II_IMUX + +MACROCELL_INSTANCE | OptxMapped | IDE_A_1_OBUF$BUF0 | LAN_IDE_CP_COPY_0_COPY_0 | 2155872256 | 1 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | IDE_A_1_OBUF | 5001 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | IDE_A_1_OBUF | 0 | 5 | II_IMUX +OUTPUT_NODE_TYPE | 0 | 0 | MC_Q +NODE | IDE_A_1_OBUF$BUF0 | 5002 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_A_1_OBUF$BUF0.Q | IDE_A_1_OBUF$BUF0 | 0 | 0 | MC_Q + +SIGNAL_INSTANCE | IDE_A_1_OBUF$BUF0.SI | IDE_A_1_OBUF$BUF0 | 0 | 1 | 2 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | IDE_A_1_OBUF | 5001 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | IDE_A_1_OBUF | 0 | 5 | II_IMUX +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | IDE_A_1_OBUF$BUF0.D1 | 5283 | ? | 0 | 4096 | IDE_A_1_OBUF$BUF0 | NULL | NULL | IDE_A_1_OBUF$BUF0.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | IDE_A_1_OBUF$BUF0.D2 | 5284 | ? | 0 | 4096 | IDE_A_1_OBUF$BUF0 | NULL | NULL | IDE_A_1_OBUF$BUF0.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 1 | IV_TRUE | IDE_A_1_OBUF + +SRFF_INSTANCE | IDE_A_1_OBUF$BUF0.REG | IDE_A_1_OBUF$BUF0 | 0 | 1 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | IDE_A_1_OBUF$BUF0.D | 5282 | ? | 0 | 0 | IDE_A_1_OBUF$BUF0 | NULL | NULL | IDE_A_1_OBUF$BUF0.XOR | 0 | 7 | ALU_F +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | IDE_A_1_OBUF$BUF0.Q | 5285 | ? | 0 | 0 | IDE_A_1_OBUF$BUF0 | NULL | NULL | IDE_A_1_OBUF$BUF0.REG | 0 | 8 | SRFF_Q + +INPUT_INSTANCE | 0 | 0 | NULL | IDE_A_2_OBUF | LAN_IDE_CP_COPY_0_COPY_0 | 16 | 1 | 1 +INPUT_NODE_TYPE | 0 | 5 | II_IN +NODE | A<11> | 5065 | PI | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE +OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX +NODE | IDE_A_2_OBUF | 5003 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | IDE_A_2_OBUF | 0 | 5 | II_IMUX + +MACROCELL_INSTANCE | OptxMapped | IDE_A_2_OBUF$BUF0 | LAN_IDE_CP_COPY_0_COPY_0 | 2155872256 | 1 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | IDE_A_2_OBUF | 5003 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | IDE_A_2_OBUF | 0 | 5 | II_IMUX +OUTPUT_NODE_TYPE | 0 | 0 | MC_Q +NODE | IDE_A_2_OBUF$BUF0 | 5004 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_A_2_OBUF$BUF0.Q | IDE_A_2_OBUF$BUF0 | 0 | 0 | MC_Q + +SIGNAL_INSTANCE | IDE_A_2_OBUF$BUF0.SI | IDE_A_2_OBUF$BUF0 | 0 | 1 | 2 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | IDE_A_2_OBUF | 5003 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | IDE_A_2_OBUF | 0 | 5 | II_IMUX +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | IDE_A_2_OBUF$BUF0.D1 | 5287 | ? | 0 | 4096 | IDE_A_2_OBUF$BUF0 | NULL | NULL | IDE_A_2_OBUF$BUF0.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | IDE_A_2_OBUF$BUF0.D2 | 5288 | ? | 0 | 4096 | IDE_A_2_OBUF$BUF0 | NULL | NULL | IDE_A_2_OBUF$BUF0.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 1 | IV_TRUE | IDE_A_2_OBUF + +SRFF_INSTANCE | IDE_A_2_OBUF$BUF0.REG | IDE_A_2_OBUF$BUF0 | 0 | 1 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | IDE_A_2_OBUF$BUF0.D | 5286 | ? | 0 | 0 | IDE_A_2_OBUF$BUF0 | NULL | NULL | IDE_A_2_OBUF$BUF0.XOR | 0 | 7 | ALU_F +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | IDE_A_2_OBUF$BUF0.Q | 5289 | ? | 0 | 0 | IDE_A_2_OBUF$BUF0 | NULL | NULL | IDE_A_2_OBUF$BUF0.REG | 0 | 8 | SRFF_Q + +INPUT_INSTANCE | 0 | 0 | NULL | A_12_IBUF | LAN_IDE_CP_COPY_0_COPY_0 | 16 | 1 | 1 +INPUT_NODE_TYPE | 0 | 5 | II_IN +NODE | A<12> | 5066 | PI | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE +OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX +NODE | A_12_IBUF | 5005 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_12_IBUF | 0 | 5 | II_IMUX + +MACROCELL_INSTANCE | OptxMapped | IDE_CS_0_OBUF | LAN_IDE_CP_COPY_0_COPY_0 | 2155872256 | 1 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_12_IBUF | 5005 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_12_IBUF | 0 | 5 | II_IMUX +OUTPUT_NODE_TYPE | 0 | 0 | MC_Q +NODE | IDE_CS_0_OBUF | 5006 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_CS_0_OBUF.Q | IDE_CS_0_OBUF | 0 | 0 | MC_Q + +SIGNAL_INSTANCE | IDE_CS_0_OBUF.SI | IDE_CS_0_OBUF | 0 | 1 | 2 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_12_IBUF | 5005 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_12_IBUF | 0 | 5 | II_IMUX +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | IDE_CS_0_OBUF.D1 | 5291 | ? | 0 | 4096 | IDE_CS_0_OBUF | NULL | NULL | IDE_CS_0_OBUF.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | IDE_CS_0_OBUF.D2 | 5292 | ? | 0 | 4096 | IDE_CS_0_OBUF | NULL | NULL | IDE_CS_0_OBUF.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 1 | IV_FALSE | A_12_IBUF + +SRFF_INSTANCE | IDE_CS_0_OBUF.REG | IDE_CS_0_OBUF | 0 | 1 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | IDE_CS_0_OBUF.D | 5290 | ? | 0 | 0 | IDE_CS_0_OBUF | NULL | NULL | IDE_CS_0_OBUF.XOR | 0 | 7 | ALU_F +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | IDE_CS_0_OBUF.Q | 5293 | ? | 0 | 0 | IDE_CS_0_OBUF | NULL | NULL | IDE_CS_0_OBUF.REG | 0 | 8 | SRFF_Q + +INPUT_INSTANCE | 0 | 0 | NULL | A_13_IBUF | LAN_IDE_CP_COPY_0_COPY_0 | 16 | 1 | 1 +INPUT_NODE_TYPE | 0 | 5 | II_IN +NODE | A<13> | 5067 | PI | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE +OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX +NODE | A_13_IBUF | 5007 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_13_IBUF | 0 | 5 | II_IMUX + +MACROCELL_INSTANCE | OptxMapped | IDE_CS_1_OBUF | LAN_IDE_CP_COPY_0_COPY_0 | 2155872256 | 14 | 2 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_5_IBUF | 4927 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_4_IBUF | 4928 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_4_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_6_IBUF | 4930 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_6_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_3_IBUF | 4931 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_2_IBUF | 4932 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<0> | 4937 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<0>.Q | AUTO_CONFIG_DONE<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | autoconfig | 4957 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.Q | autoconfig | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<1> | 4938 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<1>.Q | AUTO_CONFIG_DONE<1> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<2> | 4939 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<2>.Q | AUTO_CONFIG_DONE<2> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_1_IBUF | 4929 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | N1$BUF1.EXP | 5354 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | N1$BUF1.EXP | N1$BUF1 | 4 | 0 | MC_EXPORT +OUTPUT_NODE_TYPE | 0 | 0 | MC_Q +NODE | IDE_CS_1_OBUF | 5008 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_CS_1_OBUF.Q | IDE_CS_1_OBUF | 0 | 0 | MC_Q +OUTPUT_NODE_TYPE | 4 | 0 | MC_EXPORT +NODE | IDE_CS_1_OBUF.EXP | 5353 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_CS_1_OBUF.EXP | IDE_CS_1_OBUF | 4 | 0 | MC_EXPORT + +SIGNAL_INSTANCE | IDE_CS_1_OBUF.SI | IDE_CS_1_OBUF | 0 | 14 | 3 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_5_IBUF | 4927 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_4_IBUF | 4928 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_4_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_6_IBUF | 4930 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_6_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_3_IBUF | 4931 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_2_IBUF | 4932 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<0> | 4937 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<0>.Q | AUTO_CONFIG_DONE<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | autoconfig | 4957 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.Q | autoconfig | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<1> | 4938 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<1>.Q | AUTO_CONFIG_DONE<1> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<2> | 4939 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<2>.Q | AUTO_CONFIG_DONE<2> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_1_IBUF | 4929 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | N1$BUF1.EXP | 5354 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | N1$BUF1.EXP | N1$BUF1 | 4 | 0 | MC_EXPORT +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | IDE_CS_1_OBUF.D1 | 5295 | ? | 0 | 4096 | IDE_CS_1_OBUF | NULL | NULL | IDE_CS_1_OBUF.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | IDE_CS_1_OBUF.D2 | 5296 | ? | 0 | 4096 | IDE_CS_1_OBUF | NULL | NULL | IDE_CS_1_OBUF.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 1 | IV_TRUE | N1$BUF1.EXP +OUTPUT_NODE_TYPE | 7 | 9 | MC_SI_EXPORT +SIGNAL | NODE | IDE_CS_1_OBUF.EXP | 5348 | ? | 0 | 0 | IDE_CS_1_OBUF | NULL | NULL | IDE_CS_1_OBUF.SI | 7 | 9 | MC_SI_EXPORT +SPPTERM | 10 | IV_TRUE | RESET_IBUF | IV_TRUE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_FALSE | A_4_IBUF | IV_TRUE | A_6_IBUF | IV_FALSE | A_3_IBUF | IV_FALSE | A_2_IBUF | IV_FALSE | AUTO_CONFIG_DONE<0> | IV_TRUE | autoconfig +SPPTERM | 10 | IV_TRUE | RESET_IBUF | IV_TRUE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_FALSE | A_4_IBUF | IV_TRUE | A_6_IBUF | IV_FALSE | A_3_IBUF | IV_FALSE | A_2_IBUF | IV_FALSE | AUTO_CONFIG_DONE<1> | IV_TRUE | autoconfig +SPPTERM | 10 | IV_TRUE | RESET_IBUF | IV_TRUE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_FALSE | A_4_IBUF | IV_TRUE | A_6_IBUF | IV_FALSE | A_3_IBUF | IV_FALSE | A_2_IBUF | IV_FALSE | AUTO_CONFIG_DONE<2> | IV_TRUE | autoconfig +SPPTERM | 10 | IV_TRUE | RESET_IBUF | IV_TRUE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_FALSE | A_1_IBUF | IV_FALSE | A_6_IBUF | IV_FALSE | A_3_IBUF | IV_TRUE | A_2_IBUF | IV_FALSE | AUTO_CONFIG_DONE<0> | IV_TRUE | autoconfig +SPPTERM | 11 | IV_TRUE | RESET_IBUF | IV_TRUE | RW_IBUF | IV_FALSE | AS_IBUF | IV_TRUE | A_5_IBUF | IV_FALSE | A_4_IBUF | IV_TRUE | A_1_IBUF | IV_FALSE | A_6_IBUF | IV_TRUE | A_2_IBUF | IV_TRUE | AUTO_CONFIG_DONE<0> | IV_FALSE | AUTO_CONFIG_DONE<1> | IV_TRUE | autoconfig + +SRFF_INSTANCE | IDE_CS_1_OBUF.REG | IDE_CS_1_OBUF | 0 | 1 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | IDE_CS_1_OBUF.D | 5294 | ? | 0 | 0 | IDE_CS_1_OBUF | NULL | NULL | IDE_CS_1_OBUF.XOR | 0 | 7 | ALU_F +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | IDE_CS_1_OBUF.Q | 5297 | ? | 0 | 0 | IDE_CS_1_OBUF | NULL | NULL | IDE_CS_1_OBUF.REG | 0 | 8 | SRFF_Q + +MACROCELL_INSTANCE | PinTrst+OptxMapped | ROM_B_0_OBUF$BUF1 | LAN_IDE_CP_COPY_0_COPY_0 | 2155888640 | 0 | 2 +OUTPUT_NODE_TYPE | 0 | 0 | MC_Q +NODE | ROM_B_0_OBUF$BUF1 | 5009 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ROM_B_0_OBUF$BUF1.Q | ROM_B_0_OBUF$BUF1 | 0 | 0 | MC_Q +OUTPUT_NODE_TYPE | 2 | 0 | MC_OE +NODE | ROM_B_0_OBUF$BUF1$OE | 5010 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ROM_B_0_OBUF$BUF1.BUFOE.OUT | ROM_B_0_OBUF$BUF1 | 2 | 0 | MC_OE + +SIGNAL_INSTANCE | ROM_B_0_OBUF$BUF1.SI | ROM_B_0_OBUF$BUF1 | 0 | 0 | 3 +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | ROM_B_0_OBUF$BUF1.D1 | 5299 | ? | 0 | 4096 | ROM_B_0_OBUF$BUF1 | NULL | NULL | ROM_B_0_OBUF$BUF1.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | ROM_B_0_OBUF$BUF1.D2 | 5300 | ? | 0 | 6144 | ROM_B_0_OBUF$BUF1 | NULL | NULL | ROM_B_0_OBUF$BUF1.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 4 | 9 | MC_SI_TRST +SIGNAL | NODE | ROM_B_0_OBUF$BUF1.TRST | 5302 | ? | 0 | 6144 | ROM_B_0_OBUF$BUF1 | NULL | NULL | ROM_B_0_OBUF$BUF1.SI | 4 | 9 | MC_SI_TRST +SPPTERM | 0 | IV_ZERO + +SRFF_INSTANCE | ROM_B_0_OBUF$BUF1.REG | ROM_B_0_OBUF$BUF1 | 0 | 1 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | ROM_B_0_OBUF$BUF1.D | 5298 | ? | 0 | 0 | ROM_B_0_OBUF$BUF1 | NULL | NULL | ROM_B_0_OBUF$BUF1.XOR | 0 | 7 | ALU_F +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | ROM_B_0_OBUF$BUF1.Q | 5303 | ? | 0 | 0 | ROM_B_0_OBUF$BUF1 | NULL | NULL | ROM_B_0_OBUF$BUF1.REG | 0 | 8 | SRFF_Q + +BUF_INSTANCE | ROM_B_0_OBUF$BUF1.BUFOE | ROM_B_0_OBUF$BUF1 | 0 | 1 | 1 +INPUT_NODE_TYPE | 0 | 10 | CTOR_UNKNOWN +SIGNAL | NODE | ROM_B_0_OBUF$BUF1.TRST | 5302 | ? | 0 | 6144 | ROM_B_0_OBUF$BUF1 | NULL | NULL | ROM_B_0_OBUF$BUF1.SI | 4 | 9 | MC_SI_TRST +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 0 | 10 | BUF_OUT +NODE | ROM_B_0_OBUF$BUF1.BUFOE.OUT | 5301 | ? | 0 | 0 | ROM_B_0_OBUF$BUF1 | NULL | NULL | ROM_B_0_OBUF$BUF1.BUFOE | 0 | 10 | BUF_OUT + +MACROCELL_INSTANCE | FbkInv+Merge+OptxMapped | ROM_B_0_OBUF | LAN_IDE_CP_COPY_0_COPY_0 | 2155907072 | 0 | 1 +OUTPUT_NODE_TYPE | 0 | 0 | MC_Q +NODE | ROM_B_0_OBUF$Q | 5011 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ROM_B_0_OBUF.Q | ROM_B_0_OBUF | 0 | 0 | MC_Q + +SIGNAL_INSTANCE | ROM_B_0_OBUF.SI | ROM_B_0_OBUF | 0 | 0 | 2 +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | ROM_B_0_OBUF.D1 | 5305 | ? | 0 | 4096 | ROM_B_0_OBUF | NULL | NULL | ROM_B_0_OBUF.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | ROM_B_0_OBUF.D2 | 5306 | ? | 0 | 4096 | ROM_B_0_OBUF | NULL | NULL | ROM_B_0_OBUF.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 0 | IV_ZERO + +SRFF_INSTANCE | ROM_B_0_OBUF.REG | ROM_B_0_OBUF | 0 | 1 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | ROM_B_0_OBUF.D | 5304 | ? | 0 | 0 | ROM_B_0_OBUF | NULL | NULL | ROM_B_0_OBUF.XOR | 0 | 7 | ALU_F +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | ROM_B_0_OBUF.Q | 5307 | ? | 0 | 0 | ROM_B_0_OBUF | NULL | NULL | ROM_B_0_OBUF.REG | 0 | 8 | SRFF_Q + +MACROCELL_INSTANCE | OptxMapped | ROM_B_0_OBUF$BUF0 | LAN_IDE_CP_COPY_0_COPY_0 | 2155872256 | 0 | 1 +OUTPUT_NODE_TYPE | 0 | 0 | MC_Q +NODE | ROM_B_0_OBUF$BUF0 | 5012 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ROM_B_0_OBUF$BUF0.Q | ROM_B_0_OBUF$BUF0 | 0 | 0 | MC_Q + +SIGNAL_INSTANCE | ROM_B_0_OBUF$BUF0.SI | ROM_B_0_OBUF$BUF0 | 0 | 0 | 2 +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | ROM_B_0_OBUF$BUF0.D1 | 5309 | ? | 0 | 4096 | ROM_B_0_OBUF$BUF0 | NULL | NULL | ROM_B_0_OBUF$BUF0.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | ROM_B_0_OBUF$BUF0.D2 | 5310 | ? | 0 | 6144 | ROM_B_0_OBUF$BUF0 | NULL | NULL | ROM_B_0_OBUF$BUF0.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 0 | IV_ZERO + +SRFF_INSTANCE | ROM_B_0_OBUF$BUF0.REG | ROM_B_0_OBUF$BUF0 | 0 | 1 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | ROM_B_0_OBUF$BUF0.D | 5308 | ? | 0 | 0 | ROM_B_0_OBUF$BUF0 | NULL | NULL | ROM_B_0_OBUF$BUF0.XOR | 0 | 7 | ALU_F +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | ROM_B_0_OBUF$BUF0.Q | 5311 | ? | 0 | 0 | ROM_B_0_OBUF$BUF0 | NULL | NULL | ROM_B_0_OBUF$BUF0.REG | 0 | 8 | SRFF_Q + +OUTPUT_INSTANCE | 0 | D<13> | LAN_IDE_CP_COPY_0_COPY_0 | 7 | 2 | 1 +INPUT_NODE_TYPE | 0 | 6 | OI_IN +NODE | Dout1<1> | 5339 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | HPART_CREATED_2.Q | _12_ | 0 | 0 | MC_Q +INPUT_NODE_TYPE | 2 | 6 | OI_OE +NODE | Dout1<1>$OE | 4914 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | HPART_CREATED_2.BUFOE.OUT | _12_ | 2 | 0 | MC_OE +OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT +NODE | D<13> | 5013 | PIPO | 0 | 64 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | D<13> | 0 | 6 | OI_OUT + +OUTPUT_INSTANCE | 0 | D<12> | LAN_IDE_CP_COPY_0_COPY_0 | 7 | 2 | 1 +INPUT_NODE_TYPE | 0 | 6 | OI_IN +NODE | Dout1<0> | 5323 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | HPART_CREATED_0.Q | _10_ | 0 | 0 | MC_Q +INPUT_NODE_TYPE | 2 | 6 | OI_OE +NODE | Dout1<0>$OE | 4917 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | HPART_CREATED_0.BUFOE.OUT | _10_ | 2 | 0 | MC_OE +OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT +NODE | D<12> | 5014 | PIPO | 0 | 64 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | D<12> | 0 | 6 | OI_OUT + +OUTPUT_INSTANCE | 0 | D<14> | LAN_IDE_CP_COPY_0_COPY_0 | 7 | 2 | 1 +INPUT_NODE_TYPE | 0 | 6 | OI_IN +NODE | Dout1<2> | 5331 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | HPART_CREATED_1.Q | _11_ | 0 | 0 | MC_Q +INPUT_NODE_TYPE | 2 | 6 | OI_OE +NODE | Dout1<2>$OE | 4920 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | HPART_CREATED_1.BUFOE.OUT | _11_ | 2 | 0 | MC_OE +OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT +NODE | D<14> | 5015 | PIPO | 0 | 64 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | D<14> | 0 | 6 | OI_OUT + +OUTPUT_INSTANCE | 0 | D<15> | LAN_IDE_CP_COPY_0_COPY_0 | 7 | 2 | 1 +INPUT_NODE_TYPE | 0 | 6 | OI_IN +NODE | Dout1<3> | 5347 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | HPART_CREATED_3.Q | _13_ | 0 | 0 | MC_Q +INPUT_NODE_TYPE | 2 | 6 | OI_OE +NODE | Dout1<3>$OE | 4923 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | HPART_CREATED_3.BUFOE.OUT | _13_ | 2 | 0 | MC_OE +OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT +NODE | D<15> | 5016 | PIPO | 0 | 64 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | D<15> | 0 | 6 | OI_OUT + +OUTPUT_INSTANCE | 0 | IDE_R | LAN_IDE_CP_COPY_0_COPY_0 | 7 | 1 | 1 +INPUT_NODE_TYPE | 0 | 6 | OI_IN +NODE | IDE_R_S | 4972 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_R_S.Q | IDE_R_S | 0 | 0 | MC_Q +OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT +NODE | IDE_R | 5017 | PO | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | IDE_R | 0 | 6 | OI_OUT + +OUTPUT_INSTANCE | 0 | IDE_W | LAN_IDE_CP_COPY_0_COPY_0 | 7 | 1 | 1 +INPUT_NODE_TYPE | 0 | 6 | OI_IN +NODE | IDE_W_S | 4973 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_W_S.Q | IDE_W_S | 0 | 0 | MC_Q +OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT +NODE | IDE_W | 5018 | PO | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | IDE_W | 0 | 6 | OI_OUT + +OUTPUT_INSTANCE | 0 | ROM_OE | LAN_IDE_CP_COPY_0_COPY_0 | 7 | 1 | 1 +INPUT_NODE_TYPE | 0 | 6 | OI_IN +NODE | ROM_OE_S | 4974 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ROM_OE_S.Q | ROM_OE_S | 0 | 0 | MC_Q +OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT +NODE | ROM_OE | 5019 | PO | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | ROM_OE | 0 | 6 | OI_OUT + +OUTPUT_INSTANCE | 0 | D<9> | LAN_IDE_CP_COPY_0_COPY_0 | 7 | 2 | 1 +INPUT_NODE_TYPE | 0 | 6 | OI_IN +NODE | N1$Q | 4975 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | N1.Q | N1 | 0 | 0 | MC_Q +INPUT_NODE_TYPE | 2 | 6 | OI_OE +NODE | N1$OE | 4976 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | N1.BUFOE.OUT | N1 | 2 | 0 | MC_OE +OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT +NODE | D<9> | 5020 | PIPO | 0 | 64 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | D<9> | 0 | 6 | OI_OUT + +OUTPUT_INSTANCE | 0 | D<8> | LAN_IDE_CP_COPY_0_COPY_0 | 7 | 2 | 1 +INPUT_NODE_TYPE | 0 | 6 | OI_IN +NODE | N1$BUF0 | 4977 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | N1$BUF0.Q | N1$BUF0 | 0 | 0 | MC_Q +INPUT_NODE_TYPE | 2 | 6 | OI_OE +NODE | N1$BUF0$OE | 4978 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | N1$BUF0.BUFOE.OUT | N1$BUF0 | 2 | 0 | MC_OE +OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT +NODE | D<8> | 5021 | PIPO | 0 | 64 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | D<8> | 0 | 6 | OI_OUT + +OUTPUT_INSTANCE | 0 | D<7> | LAN_IDE_CP_COPY_0_COPY_0 | 7 | 2 | 1 +INPUT_NODE_TYPE | 0 | 6 | OI_IN +NODE | N1$BUF1 | 4979 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | N1$BUF1.Q | N1$BUF1 | 0 | 0 | MC_Q +INPUT_NODE_TYPE | 2 | 6 | OI_OE +NODE | N1$BUF1$OE | 4980 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | N1$BUF1.BUFOE.OUT | N1$BUF1 | 2 | 0 | MC_OE +OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT +NODE | D<7> | 5022 | PO | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | D<7> | 0 | 6 | OI_OUT + +OUTPUT_INSTANCE | 0 | D<0> | LAN_IDE_CP_COPY_0_COPY_0 | 7 | 2 | 1 +INPUT_NODE_TYPE | 0 | 6 | OI_IN +NODE | N1$BUF10 | 4981 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | N1$BUF10.Q | N1$BUF10 | 0 | 0 | MC_Q +INPUT_NODE_TYPE | 2 | 6 | OI_OE +NODE | N1$BUF10$OE | 4982 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | N1$BUF10.BUFOE.OUT | N1$BUF10 | 2 | 0 | MC_OE +OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT +NODE | D<0> | 5023 | PO | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | D<0> | 0 | 6 | OI_OUT + +OUTPUT_INSTANCE | 0 | D<6> | LAN_IDE_CP_COPY_0_COPY_0 | 7 | 2 | 1 +INPUT_NODE_TYPE | 0 | 6 | OI_IN +NODE | N1$BUF2 | 4983 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | N1$BUF2.Q | N1$BUF2 | 0 | 0 | MC_Q +INPUT_NODE_TYPE | 2 | 6 | OI_OE +NODE | N1$BUF2$OE | 4984 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | N1$BUF2.BUFOE.OUT | N1$BUF2 | 2 | 0 | MC_OE +OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT +NODE | D<6> | 5024 | PO | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | D<6> | 0 | 6 | OI_OUT + +OUTPUT_INSTANCE | 0 | D<5> | LAN_IDE_CP_COPY_0_COPY_0 | 7 | 2 | 1 +INPUT_NODE_TYPE | 0 | 6 | OI_IN +NODE | N1$BUF3 | 4985 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | N1$BUF3.Q | N1$BUF3 | 0 | 0 | MC_Q +INPUT_NODE_TYPE | 2 | 6 | OI_OE +NODE | N1$BUF3$OE | 4986 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | N1$BUF3.BUFOE.OUT | N1$BUF3 | 2 | 0 | MC_OE +OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT +NODE | D<5> | 5025 | PO | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | D<5> | 0 | 6 | OI_OUT + +OUTPUT_INSTANCE | 0 | D<4> | LAN_IDE_CP_COPY_0_COPY_0 | 7 | 2 | 1 +INPUT_NODE_TYPE | 0 | 6 | OI_IN +NODE | N1$BUF4 | 4987 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | N1$BUF4.Q | N1$BUF4 | 0 | 0 | MC_Q +INPUT_NODE_TYPE | 2 | 6 | OI_OE +NODE | N1$BUF4$OE | 4988 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | N1$BUF4.BUFOE.OUT | N1$BUF4 | 2 | 0 | MC_OE +OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT +NODE | D<4> | 5026 | PO | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | D<4> | 0 | 6 | OI_OUT + +OUTPUT_INSTANCE | 0 | D<3> | LAN_IDE_CP_COPY_0_COPY_0 | 7 | 2 | 1 +INPUT_NODE_TYPE | 0 | 6 | OI_IN +NODE | N1$BUF5 | 4989 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | N1$BUF5.Q | N1$BUF5 | 0 | 0 | MC_Q +INPUT_NODE_TYPE | 2 | 6 | OI_OE +NODE | N1$BUF5$OE | 4990 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | N1$BUF5.BUFOE.OUT | N1$BUF5 | 2 | 0 | MC_OE +OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT +NODE | D<3> | 5027 | PO | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | D<3> | 0 | 6 | OI_OUT + +OUTPUT_INSTANCE | 0 | D<2> | LAN_IDE_CP_COPY_0_COPY_0 | 7 | 2 | 1 +INPUT_NODE_TYPE | 0 | 6 | OI_IN +NODE | N1$BUF6 | 4991 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | N1$BUF6.Q | N1$BUF6 | 0 | 0 | MC_Q +INPUT_NODE_TYPE | 2 | 6 | OI_OE +NODE | N1$BUF6$OE | 4992 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | N1$BUF6.BUFOE.OUT | N1$BUF6 | 2 | 0 | MC_OE +OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT +NODE | D<2> | 5028 | PO | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | D<2> | 0 | 6 | OI_OUT + +OUTPUT_INSTANCE | 0 | D<1> | LAN_IDE_CP_COPY_0_COPY_0 | 7 | 2 | 1 +INPUT_NODE_TYPE | 0 | 6 | OI_IN +NODE | N1$BUF7 | 4993 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | N1$BUF7.Q | N1$BUF7 | 0 | 0 | MC_Q +INPUT_NODE_TYPE | 2 | 6 | OI_OE +NODE | N1$BUF7$OE | 4994 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | N1$BUF7.BUFOE.OUT | N1$BUF7 | 2 | 0 | MC_OE +OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT +NODE | D<1> | 5029 | PO | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | D<1> | 0 | 6 | OI_OUT + +OUTPUT_INSTANCE | 0 | D<11> | LAN_IDE_CP_COPY_0_COPY_0 | 7 | 2 | 1 +INPUT_NODE_TYPE | 0 | 6 | OI_IN +NODE | N1$BUF8 | 4995 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | N1$BUF8.Q | N1$BUF8 | 0 | 0 | MC_Q +INPUT_NODE_TYPE | 2 | 6 | OI_OE +NODE | N1$BUF8$OE | 4996 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | N1$BUF8.BUFOE.OUT | N1$BUF8 | 2 | 0 | MC_OE +OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT +NODE | D<11> | 5030 | PIPO | 0 | 64 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | D<11> | 0 | 6 | OI_OUT + +OUTPUT_INSTANCE | 0 | D<10> | LAN_IDE_CP_COPY_0_COPY_0 | 7 | 2 | 1 +INPUT_NODE_TYPE | 0 | 6 | OI_IN +NODE | N1$BUF9 | 4997 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | N1$BUF9.Q | N1$BUF9 | 0 | 0 | MC_Q +INPUT_NODE_TYPE | 2 | 6 | OI_OE +NODE | N1$BUF9$OE | 4998 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | N1$BUF9.BUFOE.OUT | N1$BUF9 | 2 | 0 | MC_OE +OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT +NODE | D<10> | 5031 | PIPO | 0 | 64 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | D<10> | 0 | 6 | OI_OUT + +OUTPUT_INSTANCE | 0 | IDE_A<0> | LAN_IDE_CP_COPY_0_COPY_0 | 7 | 1 | 1 +INPUT_NODE_TYPE | 0 | 6 | OI_IN +NODE | IDE_A_0_OBUF$BUF0 | 5000 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_A_0_OBUF$BUF0.Q | IDE_A_0_OBUF$BUF0 | 0 | 0 | MC_Q +OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT +NODE | IDE_A<0> | 5032 | PO | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | IDE_A<0> | 0 | 6 | OI_OUT + +OUTPUT_INSTANCE | 0 | IDE_A<1> | LAN_IDE_CP_COPY_0_COPY_0 | 7 | 1 | 1 +INPUT_NODE_TYPE | 0 | 6 | OI_IN +NODE | IDE_A_1_OBUF$BUF0 | 5002 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_A_1_OBUF$BUF0.Q | IDE_A_1_OBUF$BUF0 | 0 | 0 | MC_Q +OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT +NODE | IDE_A<1> | 5033 | PO | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | IDE_A<1> | 0 | 6 | OI_OUT + +OUTPUT_INSTANCE | 0 | IDE_A<2> | LAN_IDE_CP_COPY_0_COPY_0 | 7 | 1 | 1 +INPUT_NODE_TYPE | 0 | 6 | OI_IN +NODE | IDE_A_2_OBUF$BUF0 | 5004 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_A_2_OBUF$BUF0.Q | IDE_A_2_OBUF$BUF0 | 0 | 0 | MC_Q +OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT +NODE | IDE_A<2> | 5034 | PO | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | IDE_A<2> | 0 | 6 | OI_OUT + +OUTPUT_INSTANCE | 0 | IDE_CS<0> | LAN_IDE_CP_COPY_0_COPY_0 | 7 | 1 | 1 +INPUT_NODE_TYPE | 0 | 6 | OI_IN +NODE | IDE_CS_0_OBUF | 5006 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_CS_0_OBUF.Q | IDE_CS_0_OBUF | 0 | 0 | MC_Q +OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT +NODE | IDE_CS<0> | 5035 | PO | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | IDE_CS<0> | 0 | 6 | OI_OUT + +OUTPUT_INSTANCE | 0 | IDE_CS<1> | LAN_IDE_CP_COPY_0_COPY_0 | 7 | 1 | 1 +INPUT_NODE_TYPE | 0 | 6 | OI_IN +NODE | IDE_CS_1_OBUF | 5008 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_CS_1_OBUF.Q | IDE_CS_1_OBUF | 0 | 0 | MC_Q +OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT +NODE | IDE_CS<1> | 5036 | PO | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | IDE_CS<1> | 0 | 6 | OI_OUT + +OUTPUT_INSTANCE | 0 | DTACK | LAN_IDE_CP_COPY_0_COPY_0 | 7 | 2 | 1 +INPUT_NODE_TYPE | 0 | 6 | OI_IN +NODE | ROM_B_0_OBUF$BUF1 | 5009 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ROM_B_0_OBUF$BUF1.Q | ROM_B_0_OBUF$BUF1 | 0 | 0 | MC_Q +INPUT_NODE_TYPE | 2 | 6 | OI_OE +NODE | ROM_B_0_OBUF$BUF1$OE | 5010 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ROM_B_0_OBUF$BUF1.BUFOE.OUT | ROM_B_0_OBUF$BUF1 | 2 | 0 | MC_OE +OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT +NODE | DTACK | 5037 | PO | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | DTACK | 0 | 6 | OI_OUT + +OUTPUT_INSTANCE | 0 | ROM_B<1> | LAN_IDE_CP_COPY_0_COPY_0 | 7 | 1 | 1 +INPUT_NODE_TYPE | 0 | 6 | OI_IN +NODE | ROM_B_0_OBUF$Q | 5011 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ROM_B_0_OBUF.Q | ROM_B_0_OBUF | 0 | 0 | MC_Q +OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT +NODE | ROM_B<1> | 5038 | PO | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | ROM_B<1> | 0 | 6 | OI_OUT + +OUTPUT_INSTANCE | 0 | ROM_B<0> | LAN_IDE_CP_COPY_0_COPY_0 | 7 | 1 | 1 +INPUT_NODE_TYPE | 0 | 6 | OI_IN +NODE | ROM_B_0_OBUF$BUF0 | 5012 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ROM_B_0_OBUF$BUF0.Q | ROM_B_0_OBUF$BUF0 | 0 | 0 | MC_Q +OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT +NODE | ROM_B<0> | 5039 | PO | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | ROM_B<0> | 0 | 6 | OI_OUT + +MACROCELL_INSTANCE | Inv+SoftPfbk | ide/ide_CLKF | LAN_IDE_CP_COPY_0_COPY_0 | 2181038336 | 2 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | C3_IBUF | 4956 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | C3_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | C1_IBUF | 4955 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | C1_IBUF | 0 | 5 | II_IMUX +OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM +NODE | ide/ide_CLKF.UIM | 5040 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ide/ide_CLKF.Q | ide/ide_CLKF | 1 | 0 | MC_UIM + +SIGNAL_INSTANCE | ide/ide_CLKF.SI | ide/ide_CLKF | 0 | 2 | 2 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | C3_IBUF | 4956 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | C3_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | C1_IBUF | 4955 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | C1_IBUF | 0 | 5 | II_IMUX +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | ide/ide_CLKF.D1 | 5313 | ? | 0 | 4096 | ide/ide_CLKF | NULL | NULL | ide/ide_CLKF.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 1 | IV_TRUE | C3_IBUF +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | ide/ide_CLKF.D2 | 5314 | ? | 0 | 4096 | ide/ide_CLKF | NULL | NULL | ide/ide_CLKF.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 1 | IV_TRUE | C1_IBUF + +SRFF_INSTANCE | ide/ide_CLKF.REG | ide/ide_CLKF | 0 | 1 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | ide/ide_CLKF.D | 5312 | ? | 0 | 0 | ide/ide_CLKF | NULL | NULL | ide/ide_CLKF.XOR | 0 | 7 | ALU_F +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | ide/ide_CLKF.Q | 5315 | ? | 0 | 0 | ide/ide_CLKF | NULL | NULL | ide/ide_CLKF.REG | 0 | 8 | SRFF_Q + +MACROCELL_INSTANCE | PinTrst+OptxMapped | _10_ | LAN_IDE_CP_COPY_0_COPY_0 | 2155888640 | 3 | 3 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTOCONFIG_IN_PROGRESS | 4959 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTOCONFIG_IN_PROGRESS.Q | AUTOCONFIG_IN_PROGRESS | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | D<12>_BUFR | 5319 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | Dout1<0>.Q | D<12>_BUFR.MC | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 0 | 0 | MC_Q +NODE | Dout1<0> | 5323 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | HPART_CREATED_0.Q | _10_ | 0 | 0 | MC_Q +OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM +NODE | Dout1<0>.UIM | 4916 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | HPART_CREATED_0.Q | _10_ | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 2 | 0 | MC_OE +NODE | Dout1<0>$OE | 4917 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | HPART_CREATED_0.BUFOE.OUT | _10_ | 2 | 0 | MC_OE + +SIGNAL_INSTANCE | HPART_CREATED_0.SI | _10_ | 0 | 3 | 3 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTOCONFIG_IN_PROGRESS | 4959 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTOCONFIG_IN_PROGRESS.Q | AUTOCONFIG_IN_PROGRESS | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | D<12>_BUFR | 5319 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | Dout1<0>.Q | D<12>_BUFR.MC | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | HPART_CREATED_0.D1 | 5322 | ? | 0 | 0 | _10_ | NULL | NULL | HPART_CREATED_0.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | HPART_CREATED_0.D2 | 5321 | ? | 0 | 0 | _10_ | NULL | NULL | HPART_CREATED_0.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 1 | IV_TRUE | D<12>_BUFR +OUTPUT_NODE_TYPE | 4 | 9 | MC_SI_TRST +SIGNAL | NODE | HPART_CREATED_0.TRST | 5317 | ? | 0 | 0 | _10_ | NULL | NULL | HPART_CREATED_0.SI | 4 | 9 | MC_SI_TRST +SPPTERM | 2 | IV_TRUE | RW_IBUF | IV_TRUE | AUTOCONFIG_IN_PROGRESS + +SRFF_INSTANCE | HPART_CREATED_0.REG | _10_ | 0 | 1 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | HPART_CREATED_0.D | 5320 | ? | 0 | 0 | _10_ | NULL | NULL | HPART_CREATED_0.XOR | 0 | 7 | ALU_F +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | HPART_CREATED_0.Q | 5318 | ? | 0 | 0 | _10_ | NULL | NULL | HPART_CREATED_0.REG | 0 | 8 | SRFF_Q + +BUF_INSTANCE | HPART_CREATED_0.BUFOE | _10_ | 0 | 1 | 1 +INPUT_NODE_TYPE | 0 | 10 | CTOR_UNKNOWN +SIGNAL | NODE | HPART_CREATED_0.TRST | 5317 | ? | 0 | 0 | _10_ | NULL | NULL | HPART_CREATED_0.SI | 4 | 9 | MC_SI_TRST +SPPTERM | 2 | IV_TRUE | RW_IBUF | IV_TRUE | AUTOCONFIG_IN_PROGRESS +OUTPUT_NODE_TYPE | 0 | 10 | BUF_OUT +NODE | HPART_CREATED_0.BUFOE.OUT | 5316 | ? | 0 | 0 | _10_ | NULL | NULL | HPART_CREATED_0.BUFOE | 0 | 10 | BUF_OUT + +MACROCELL_INSTANCE | PinTrst+OptxMapped | _11_ | LAN_IDE_CP_COPY_0_COPY_0 | 2155888640 | 3 | 3 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTOCONFIG_IN_PROGRESS | 4959 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTOCONFIG_IN_PROGRESS.Q | AUTOCONFIG_IN_PROGRESS | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | D<14>_BUFR | 5327 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | Dout1<2>.Q | D<14>_BUFR.MC | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 0 | 0 | MC_Q +NODE | Dout1<2> | 5331 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | HPART_CREATED_1.Q | _11_ | 0 | 0 | MC_Q +OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM +NODE | Dout1<2>.UIM | 4919 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | HPART_CREATED_1.Q | _11_ | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 2 | 0 | MC_OE +NODE | Dout1<2>$OE | 4920 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | HPART_CREATED_1.BUFOE.OUT | _11_ | 2 | 0 | MC_OE + +SIGNAL_INSTANCE | HPART_CREATED_1.SI | _11_ | 0 | 3 | 3 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTOCONFIG_IN_PROGRESS | 4959 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTOCONFIG_IN_PROGRESS.Q | AUTOCONFIG_IN_PROGRESS | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | D<14>_BUFR | 5327 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | Dout1<2>.Q | D<14>_BUFR.MC | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | HPART_CREATED_1.D1 | 5330 | ? | 0 | 0 | _11_ | NULL | NULL | HPART_CREATED_1.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | HPART_CREATED_1.D2 | 5329 | ? | 0 | 0 | _11_ | NULL | NULL | HPART_CREATED_1.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 1 | IV_TRUE | D<14>_BUFR +OUTPUT_NODE_TYPE | 4 | 9 | MC_SI_TRST +SIGNAL | NODE | HPART_CREATED_1.TRST | 5325 | ? | 0 | 0 | _11_ | NULL | NULL | HPART_CREATED_1.SI | 4 | 9 | MC_SI_TRST +SPPTERM | 2 | IV_TRUE | RW_IBUF | IV_TRUE | AUTOCONFIG_IN_PROGRESS + +SRFF_INSTANCE | HPART_CREATED_1.REG | _11_ | 0 | 1 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | HPART_CREATED_1.D | 5328 | ? | 0 | 0 | _11_ | NULL | NULL | HPART_CREATED_1.XOR | 0 | 7 | ALU_F +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | HPART_CREATED_1.Q | 5326 | ? | 0 | 0 | _11_ | NULL | NULL | HPART_CREATED_1.REG | 0 | 8 | SRFF_Q + +BUF_INSTANCE | HPART_CREATED_1.BUFOE | _11_ | 0 | 1 | 1 +INPUT_NODE_TYPE | 0 | 10 | CTOR_UNKNOWN +SIGNAL | NODE | HPART_CREATED_1.TRST | 5325 | ? | 0 | 0 | _11_ | NULL | NULL | HPART_CREATED_1.SI | 4 | 9 | MC_SI_TRST +SPPTERM | 2 | IV_TRUE | RW_IBUF | IV_TRUE | AUTOCONFIG_IN_PROGRESS +OUTPUT_NODE_TYPE | 0 | 10 | BUF_OUT +NODE | HPART_CREATED_1.BUFOE.OUT | 5324 | ? | 0 | 0 | _11_ | NULL | NULL | HPART_CREATED_1.BUFOE | 0 | 10 | BUF_OUT + +MACROCELL_INSTANCE | PinTrst+OptxMapped | _12_ | LAN_IDE_CP_COPY_0_COPY_0 | 2155888640 | 3 | 3 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTOCONFIG_IN_PROGRESS | 4959 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTOCONFIG_IN_PROGRESS.Q | AUTOCONFIG_IN_PROGRESS | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | D<13>_BUFR | 5335 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | Dout1<1>.Q | D<13>_BUFR.MC | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 0 | 0 | MC_Q +NODE | Dout1<1> | 5339 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | HPART_CREATED_2.Q | _12_ | 0 | 0 | MC_Q +OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM +NODE | Dout1<1>.UIM | 4913 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | HPART_CREATED_2.Q | _12_ | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 2 | 0 | MC_OE +NODE | Dout1<1>$OE | 4914 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | HPART_CREATED_2.BUFOE.OUT | _12_ | 2 | 0 | MC_OE + +SIGNAL_INSTANCE | HPART_CREATED_2.SI | _12_ | 0 | 3 | 3 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTOCONFIG_IN_PROGRESS | 4959 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTOCONFIG_IN_PROGRESS.Q | AUTOCONFIG_IN_PROGRESS | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | D<13>_BUFR | 5335 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | Dout1<1>.Q | D<13>_BUFR.MC | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | HPART_CREATED_2.D1 | 5338 | ? | 0 | 0 | _12_ | NULL | NULL | HPART_CREATED_2.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | HPART_CREATED_2.D2 | 5337 | ? | 0 | 0 | _12_ | NULL | NULL | HPART_CREATED_2.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 1 | IV_TRUE | D<13>_BUFR +OUTPUT_NODE_TYPE | 4 | 9 | MC_SI_TRST +SIGNAL | NODE | HPART_CREATED_2.TRST | 5333 | ? | 0 | 0 | _12_ | NULL | NULL | HPART_CREATED_2.SI | 4 | 9 | MC_SI_TRST +SPPTERM | 2 | IV_TRUE | RW_IBUF | IV_TRUE | AUTOCONFIG_IN_PROGRESS + +SRFF_INSTANCE | HPART_CREATED_2.REG | _12_ | 0 | 1 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | HPART_CREATED_2.D | 5336 | ? | 0 | 0 | _12_ | NULL | NULL | HPART_CREATED_2.XOR | 0 | 7 | ALU_F +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | HPART_CREATED_2.Q | 5334 | ? | 0 | 0 | _12_ | NULL | NULL | HPART_CREATED_2.REG | 0 | 8 | SRFF_Q + +BUF_INSTANCE | HPART_CREATED_2.BUFOE | _12_ | 0 | 1 | 1 +INPUT_NODE_TYPE | 0 | 10 | CTOR_UNKNOWN +SIGNAL | NODE | HPART_CREATED_2.TRST | 5333 | ? | 0 | 0 | _12_ | NULL | NULL | HPART_CREATED_2.SI | 4 | 9 | MC_SI_TRST +SPPTERM | 2 | IV_TRUE | RW_IBUF | IV_TRUE | AUTOCONFIG_IN_PROGRESS +OUTPUT_NODE_TYPE | 0 | 10 | BUF_OUT +NODE | HPART_CREATED_2.BUFOE.OUT | 5332 | ? | 0 | 0 | _12_ | NULL | NULL | HPART_CREATED_2.BUFOE | 0 | 10 | BUF_OUT + +MACROCELL_INSTANCE | PinTrst+OptxMapped | _13_ | LAN_IDE_CP_COPY_0_COPY_0 | 2155888640 | 3 | 3 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTOCONFIG_IN_PROGRESS | 4959 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTOCONFIG_IN_PROGRESS.Q | AUTOCONFIG_IN_PROGRESS | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | D<15>_BUFR | 5343 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | Dout1<3>.Q | D<15>_BUFR.MC | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 0 | 0 | MC_Q +NODE | Dout1<3> | 5347 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | HPART_CREATED_3.Q | _13_ | 0 | 0 | MC_Q +OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM +NODE | Dout1<3>.UIM | 4922 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | HPART_CREATED_3.Q | _13_ | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 2 | 0 | MC_OE +NODE | Dout1<3>$OE | 4923 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | HPART_CREATED_3.BUFOE.OUT | _13_ | 2 | 0 | MC_OE + +SIGNAL_INSTANCE | HPART_CREATED_3.SI | _13_ | 0 | 3 | 3 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTOCONFIG_IN_PROGRESS | 4959 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTOCONFIG_IN_PROGRESS.Q | AUTOCONFIG_IN_PROGRESS | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | D<15>_BUFR | 5343 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | Dout1<3>.Q | D<15>_BUFR.MC | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | HPART_CREATED_3.D1 | 5346 | ? | 0 | 0 | _13_ | NULL | NULL | HPART_CREATED_3.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | HPART_CREATED_3.D2 | 5345 | ? | 0 | 0 | _13_ | NULL | NULL | HPART_CREATED_3.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 1 | IV_TRUE | D<15>_BUFR +OUTPUT_NODE_TYPE | 4 | 9 | MC_SI_TRST +SIGNAL | NODE | HPART_CREATED_3.TRST | 5341 | ? | 0 | 0 | _13_ | NULL | NULL | HPART_CREATED_3.SI | 4 | 9 | MC_SI_TRST +SPPTERM | 2 | IV_TRUE | RW_IBUF | IV_TRUE | AUTOCONFIG_IN_PROGRESS + +SRFF_INSTANCE | HPART_CREATED_3.REG | _13_ | 0 | 1 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | HPART_CREATED_3.D | 5344 | ? | 0 | 0 | _13_ | NULL | NULL | HPART_CREATED_3.XOR | 0 | 7 | ALU_F +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | HPART_CREATED_3.Q | 5342 | ? | 0 | 0 | _13_ | NULL | NULL | HPART_CREATED_3.REG | 0 | 8 | SRFF_Q + +BUF_INSTANCE | HPART_CREATED_3.BUFOE | _13_ | 0 | 1 | 1 +INPUT_NODE_TYPE | 0 | 10 | CTOR_UNKNOWN +SIGNAL | NODE | HPART_CREATED_3.TRST | 5341 | ? | 0 | 0 | _13_ | NULL | NULL | HPART_CREATED_3.SI | 4 | 9 | MC_SI_TRST +SPPTERM | 2 | IV_TRUE | RW_IBUF | IV_TRUE | AUTOCONFIG_IN_PROGRESS +OUTPUT_NODE_TYPE | 0 | 10 | BUF_OUT +NODE | HPART_CREATED_3.BUFOE.OUT | 5340 | ? | 0 | 0 | _13_ | NULL | NULL | HPART_CREATED_3.BUFOE | 0 | 10 | BUF_OUT + +MACROCELL_INSTANCE | NULL | EXP14_ | LAN_IDE_CP_COPY_0_COPY_0 | 2147483648 | 14 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | Dout1<0>.UIM | 4916 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | HPART_CREATED_0.Q | _10_ | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | autoconfig | 4957 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.Q | autoconfig | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<0> | 4937 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<0>.Q | AUTO_CONFIG_DONE<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<1> | 4938 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<1>.Q | AUTO_CONFIG_DONE<1> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<2> | 4939 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<2>.Q | AUTO_CONFIG_DONE<2> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_5_IBUF | 4927 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_4_IBUF | 4928 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_4_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_1_IBUF | 4929 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_3_IBUF | 4931 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_2_IBUF | 4932 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | ROM_OE_S.EXP | 5356 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ROM_OE_S.EXP | ROM_OE_S | 4 | 0 | MC_EXPORT +OUTPUT_NODE_TYPE | 4 | 0 | MC_EXPORT +NODE | EXP14_.EXP | 5357 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | EXP14_.EXP | EXP14_ | 4 | 0 | MC_EXPORT + +SIGNAL_INSTANCE | EXP14_.SI | EXP14_ | 0 | 14 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | Dout1<0>.UIM | 4916 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | HPART_CREATED_0.Q | _10_ | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | autoconfig | 4957 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.Q | autoconfig | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<0> | 4937 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<0>.Q | AUTO_CONFIG_DONE<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<1> | 4938 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<1>.Q | AUTO_CONFIG_DONE<1> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<2> | 4939 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<2>.Q | AUTO_CONFIG_DONE<2> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_5_IBUF | 4927 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_4_IBUF | 4928 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_4_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_1_IBUF | 4929 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_3_IBUF | 4931 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_2_IBUF | 4932 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | ROM_OE_S.EXP | 5356 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ROM_OE_S.EXP | ROM_OE_S | 4 | 0 | MC_EXPORT +OUTPUT_NODE_TYPE | 7 | 9 | MC_SI_EXPORT +SIGNAL | NODE | EXP14_.EXP | 5352 | ? | 0 | 0 | EXP14_ | NULL | NULL | EXP14_.SI | 7 | 9 | MC_SI_EXPORT +SPPTERM | 1 | IV_TRUE | ROM_OE_S.EXP +SPPTERM | 3 | IV_TRUE | RESET_IBUF | IV_FALSE | Dout1<0>.UIM | IV_FALSE | RW_IBUF +SPPTERM | 3 | IV_TRUE | RESET_IBUF | IV_FALSE | Dout1<0>.UIM | IV_TRUE | AS_IBUF +SPPTERM | 3 | IV_TRUE | RESET_IBUF | IV_FALSE | Dout1<0>.UIM | IV_FALSE | autoconfig +SPPTERM | 5 | IV_TRUE | RESET_IBUF | IV_FALSE | Dout1<0>.UIM | IV_TRUE | AUTO_CONFIG_DONE<0> | IV_TRUE | AUTO_CONFIG_DONE<1> | IV_TRUE | AUTO_CONFIG_DONE<2> +SPPTERM | 10 | IV_TRUE | RESET_IBUF | IV_TRUE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_FALSE | A_4_IBUF | IV_FALSE | A_1_IBUF | IV_FALSE | A_3_IBUF | IV_FALSE | A_2_IBUF | IV_FALSE | AUTO_CONFIG_DONE<0> | IV_TRUE | autoconfig + +MACROCELL_INSTANCE | NULL | EXP15_ | LAN_IDE_CP_COPY_0_COPY_0 | 2147483648 | 14 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_5_IBUF | 4927 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_4_IBUF | 4928 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_4_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_1_IBUF | 4929 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_3_IBUF | 4931 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_2_IBUF | 4932 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<0> | 4937 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<0>.Q | AUTO_CONFIG_DONE<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | autoconfig | 4957 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.Q | autoconfig | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_6_IBUF | 4930 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_6_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<1> | 4938 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<1>.Q | AUTO_CONFIG_DONE<1> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<2> | 4939 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<2>.Q | AUTO_CONFIG_DONE<2> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | EXP16_.EXP | 5367 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | EXP16_.EXP | EXP16_ | 4 | 0 | MC_EXPORT +OUTPUT_NODE_TYPE | 4 | 0 | MC_EXPORT +NODE | EXP15_.EXP | 5366 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | EXP15_.EXP | EXP15_ | 4 | 0 | MC_EXPORT + +SIGNAL_INSTANCE | EXP15_.SI | EXP15_ | 0 | 14 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_5_IBUF | 4927 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_4_IBUF | 4928 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_4_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_1_IBUF | 4929 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_3_IBUF | 4931 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_2_IBUF | 4932 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<0> | 4937 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<0>.Q | AUTO_CONFIG_DONE<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | autoconfig | 4957 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.Q | autoconfig | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_6_IBUF | 4930 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_6_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<1> | 4938 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<1>.Q | AUTO_CONFIG_DONE<1> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<2> | 4939 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<2>.Q | AUTO_CONFIG_DONE<2> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | EXP16_.EXP | 5367 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | EXP16_.EXP | EXP16_ | 4 | 0 | MC_EXPORT +OUTPUT_NODE_TYPE | 7 | 9 | MC_SI_EXPORT +SIGNAL | NODE | EXP15_.EXP | 5358 | ? | 0 | 0 | EXP15_ | NULL | NULL | EXP15_.SI | 7 | 9 | MC_SI_EXPORT +SPPTERM | 1 | IV_TRUE | EXP16_.EXP +SPPTERM | 10 | IV_TRUE | RESET_IBUF | IV_TRUE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_FALSE | A_4_IBUF | IV_TRUE | A_1_IBUF | IV_FALSE | A_3_IBUF | IV_FALSE | A_2_IBUF | IV_FALSE | AUTO_CONFIG_DONE<0> | IV_TRUE | autoconfig +SPPTERM | 10 | IV_TRUE | RESET_IBUF | IV_TRUE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_FALSE | A_4_IBUF | IV_TRUE | A_6_IBUF | IV_FALSE | A_3_IBUF | IV_FALSE | A_2_IBUF | IV_FALSE | AUTO_CONFIG_DONE<0> | IV_TRUE | autoconfig +SPPTERM | 10 | IV_TRUE | RESET_IBUF | IV_TRUE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_FALSE | A_4_IBUF | IV_TRUE | A_6_IBUF | IV_FALSE | A_3_IBUF | IV_FALSE | A_2_IBUF | IV_FALSE | AUTO_CONFIG_DONE<1> | IV_TRUE | autoconfig +SPPTERM | 10 | IV_TRUE | RESET_IBUF | IV_TRUE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_FALSE | A_4_IBUF | IV_TRUE | A_6_IBUF | IV_FALSE | A_3_IBUF | IV_FALSE | A_2_IBUF | IV_FALSE | AUTO_CONFIG_DONE<2> | IV_TRUE | autoconfig +SPPTERM | 11 | IV_TRUE | RESET_IBUF | IV_TRUE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_4_IBUF | IV_TRUE | A_1_IBUF | IV_FALSE | A_6_IBUF | IV_FALSE | A_3_IBUF | IV_TRUE | A_2_IBUF | IV_TRUE | AUTO_CONFIG_DONE<0> | IV_FALSE | AUTO_CONFIG_DONE<1> | IV_TRUE | autoconfig + +MACROCELL_INSTANCE | NULL | EXP16_ | LAN_IDE_CP_COPY_0_COPY_0 | 2147483648 | 12 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_5_IBUF | 4927 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_4_IBUF | 4928 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_4_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_1_IBUF | 4929 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_6_IBUF | 4930 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_6_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_3_IBUF | 4931 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_2_IBUF | 4932 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<0> | 4937 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<0>.Q | AUTO_CONFIG_DONE<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | autoconfig | 4957 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.Q | autoconfig | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<1> | 4938 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<1>.Q | AUTO_CONFIG_DONE<1> | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 4 | 0 | MC_EXPORT +NODE | EXP16_.EXP | 5367 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | EXP16_.EXP | EXP16_ | 4 | 0 | MC_EXPORT + +SIGNAL_INSTANCE | EXP16_.SI | EXP16_ | 0 | 12 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_5_IBUF | 4927 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_4_IBUF | 4928 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_4_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_1_IBUF | 4929 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_6_IBUF | 4930 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_6_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_3_IBUF | 4931 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_2_IBUF | 4932 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<0> | 4937 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<0>.Q | AUTO_CONFIG_DONE<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | autoconfig | 4957 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.Q | autoconfig | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<1> | 4938 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<1>.Q | AUTO_CONFIG_DONE<1> | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 7 | 9 | MC_SI_EXPORT +SIGNAL | NODE | EXP16_.EXP | 5359 | ? | 0 | 0 | EXP16_ | NULL | NULL | EXP16_.SI | 7 | 9 | MC_SI_EXPORT +SPPTERM | 11 | IV_TRUE | RESET_IBUF | IV_TRUE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_TRUE | A_4_IBUF | IV_TRUE | A_1_IBUF | IV_FALSE | A_6_IBUF | IV_FALSE | A_3_IBUF | IV_TRUE | A_2_IBUF | IV_FALSE | AUTO_CONFIG_DONE<0> | IV_TRUE | autoconfig +SPPTERM | 11 | IV_TRUE | RESET_IBUF | IV_TRUE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_FALSE | A_4_IBUF | IV_FALSE | A_1_IBUF | IV_FALSE | A_6_IBUF | IV_FALSE | A_3_IBUF | IV_TRUE | A_2_IBUF | IV_FALSE | AUTO_CONFIG_DONE<0> | IV_TRUE | autoconfig +SPPTERM | 12 | IV_TRUE | RESET_IBUF | IV_TRUE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_TRUE | A_4_IBUF | IV_FALSE | A_1_IBUF | IV_FALSE | A_6_IBUF | IV_TRUE | A_3_IBUF | IV_TRUE | A_2_IBUF | IV_TRUE | AUTO_CONFIG_DONE<0> | IV_FALSE | AUTO_CONFIG_DONE<1> | IV_TRUE | autoconfig + +MACROCELL_INSTANCE | NULL | EXP17_ | LAN_IDE_CP_COPY_0_COPY_0 | 2147483648 | 14 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | Dout1<1>.UIM | 4913 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | HPART_CREATED_2.Q | _12_ | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<0> | 4937 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<0>.Q | AUTO_CONFIG_DONE<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<1> | 4938 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<1>.Q | AUTO_CONFIG_DONE<1> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<2> | 4939 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<2>.Q | AUTO_CONFIG_DONE<2> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_5_IBUF | 4927 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_4_IBUF | 4928 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_4_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_6_IBUF | 4930 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_6_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_3_IBUF | 4931 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | autoconfig | 4957 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.Q | autoconfig | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_2_IBUF | 4932 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | IDE_BASEADR<6>.EXP | 5370 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_BASEADR<6>.EXP | IDE_BASEADR<6> | 4 | 0 | MC_EXPORT +OUTPUT_NODE_TYPE | 4 | 0 | MC_EXPORT +NODE | EXP17_.EXP | 5371 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | EXP17_.EXP | EXP17_ | 4 | 0 | MC_EXPORT + +SIGNAL_INSTANCE | EXP17_.SI | EXP17_ | 0 | 14 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | Dout1<1>.UIM | 4913 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | HPART_CREATED_2.Q | _12_ | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<0> | 4937 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<0>.Q | AUTO_CONFIG_DONE<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<1> | 4938 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<1>.Q | AUTO_CONFIG_DONE<1> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<2> | 4939 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<2>.Q | AUTO_CONFIG_DONE<2> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_5_IBUF | 4927 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_4_IBUF | 4928 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_4_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_6_IBUF | 4930 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_6_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_3_IBUF | 4931 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | autoconfig | 4957 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.Q | autoconfig | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_2_IBUF | 4932 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | IDE_BASEADR<6>.EXP | 5370 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_BASEADR<6>.EXP | IDE_BASEADR<6> | 4 | 0 | MC_EXPORT +OUTPUT_NODE_TYPE | 7 | 9 | MC_SI_EXPORT +SIGNAL | NODE | EXP17_.EXP | 5363 | ? | 0 | 0 | EXP17_ | NULL | NULL | EXP17_.SI | 7 | 9 | MC_SI_EXPORT +SPPTERM | 1 | IV_TRUE | IDE_BASEADR<6>.EXP +SPPTERM | 3 | IV_TRUE | RESET_IBUF | IV_FALSE | Dout1<1>.UIM | IV_FALSE | RW_IBUF +SPPTERM | 5 | IV_TRUE | RESET_IBUF | IV_FALSE | Dout1<1>.UIM | IV_TRUE | AUTO_CONFIG_DONE<0> | IV_TRUE | AUTO_CONFIG_DONE<1> | IV_TRUE | AUTO_CONFIG_DONE<2> +SPPTERM | 9 | IV_TRUE | RESET_IBUF | IV_TRUE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_FALSE | A_4_IBUF | IV_FALSE | A_6_IBUF | IV_FALSE | A_3_IBUF | IV_FALSE | AUTO_CONFIG_DONE<0> | IV_TRUE | autoconfig +SPPTERM | 9 | IV_TRUE | RESET_IBUF | IV_TRUE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_FALSE | A_4_IBUF | IV_FALSE | A_3_IBUF | IV_FALSE | A_2_IBUF | IV_FALSE | AUTO_CONFIG_DONE<0> | IV_TRUE | autoconfig +SPPTERM | 9 | IV_TRUE | RESET_IBUF | IV_TRUE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_FALSE | A_4_IBUF | IV_FALSE | A_3_IBUF | IV_FALSE | A_2_IBUF | IV_FALSE | AUTO_CONFIG_DONE<1> | IV_TRUE | autoconfig + +MACROCELL_INSTANCE | NULL | EXP18_ | LAN_IDE_CP_COPY_0_COPY_0 | 2147483648 | 13 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | Dout1<2>.UIM | 4919 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | HPART_CREATED_1.Q | _11_ | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | autoconfig | 4957 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.Q | autoconfig | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<0> | 4937 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<0>.Q | AUTO_CONFIG_DONE<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<1> | 4938 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<1>.Q | AUTO_CONFIG_DONE<1> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<2> | 4939 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<2>.Q | AUTO_CONFIG_DONE<2> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_5_IBUF | 4927 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_1_IBUF | 4929 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_6_IBUF | 4930 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_6_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_3_IBUF | 4931 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_2_IBUF | 4932 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX +OUTPUT_NODE_TYPE | 4 | 0 | MC_EXPORT +NODE | EXP18_.EXP | 5373 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | EXP18_.EXP | EXP18_ | 4 | 0 | MC_EXPORT + +SIGNAL_INSTANCE | EXP18_.SI | EXP18_ | 0 | 13 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | Dout1<2>.UIM | 4919 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | HPART_CREATED_1.Q | _11_ | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | autoconfig | 4957 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.Q | autoconfig | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<0> | 4937 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<0>.Q | AUTO_CONFIG_DONE<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<1> | 4938 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<1>.Q | AUTO_CONFIG_DONE<1> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<2> | 4939 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<2>.Q | AUTO_CONFIG_DONE<2> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_5_IBUF | 4927 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_1_IBUF | 4929 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_6_IBUF | 4930 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_6_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_3_IBUF | 4931 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_2_IBUF | 4932 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX +OUTPUT_NODE_TYPE | 7 | 9 | MC_SI_EXPORT +SIGNAL | NODE | EXP18_.EXP | 5365 | ? | 0 | 0 | EXP18_ | NULL | NULL | EXP18_.SI | 7 | 9 | MC_SI_EXPORT +SPPTERM | 3 | IV_TRUE | RESET_IBUF | IV_FALSE | Dout1<2>.UIM | IV_FALSE | RW_IBUF +SPPTERM | 3 | IV_TRUE | RESET_IBUF | IV_FALSE | Dout1<2>.UIM | IV_TRUE | AS_IBUF +SPPTERM | 3 | IV_TRUE | RESET_IBUF | IV_FALSE | Dout1<2>.UIM | IV_FALSE | autoconfig +SPPTERM | 5 | IV_TRUE | RESET_IBUF | IV_FALSE | Dout1<2>.UIM | IV_TRUE | AUTO_CONFIG_DONE<0> | IV_TRUE | AUTO_CONFIG_DONE<1> | IV_TRUE | AUTO_CONFIG_DONE<2> +SPPTERM | 11 | IV_TRUE | RESET_IBUF | IV_TRUE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_TRUE | A_1_IBUF | IV_FALSE | A_6_IBUF | IV_FALSE | A_3_IBUF | IV_TRUE | A_2_IBUF | IV_TRUE | AUTO_CONFIG_DONE<0> | IV_FALSE | AUTO_CONFIG_DONE<2> | IV_TRUE | autoconfig + +MACROCELL_INSTANCE | NULL | EXP19_ | LAN_IDE_CP_COPY_0_COPY_0 | 2147483648 | 7 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_23_IBUF | 4933 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_23_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | IDE_BASEADR<7> | 4951 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_BASEADR<7>.Q | IDE_BASEADR<7> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_22_IBUF | 4934 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_22_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | IDE_BASEADR<6> | 4950 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_BASEADR<6>.Q | IDE_BASEADR<6> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | IDE_BASEADR<1> | 4947 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_BASEADR<1>.Q | IDE_BASEADR<1> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_17_IBUF | 4968 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_17_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | EXP20_.EXP | 5379 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | EXP20_.EXP | EXP20_ | 4 | 0 | MC_EXPORT +OUTPUT_NODE_TYPE | 4 | 0 | MC_EXPORT +NODE | EXP19_.EXP | 5378 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | EXP19_.EXP | EXP19_ | 4 | 0 | MC_EXPORT + +SIGNAL_INSTANCE | EXP19_.SI | EXP19_ | 0 | 7 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_23_IBUF | 4933 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_23_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | IDE_BASEADR<7> | 4951 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_BASEADR<7>.Q | IDE_BASEADR<7> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_22_IBUF | 4934 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_22_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | IDE_BASEADR<6> | 4950 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_BASEADR<6>.Q | IDE_BASEADR<6> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | IDE_BASEADR<1> | 4947 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_BASEADR<1>.Q | IDE_BASEADR<1> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_17_IBUF | 4968 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_17_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | EXP20_.EXP | 5379 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | EXP20_.EXP | EXP20_ | 4 | 0 | MC_EXPORT +OUTPUT_NODE_TYPE | 7 | 9 | MC_SI_EXPORT +SIGNAL | NODE | EXP19_.EXP | 5374 | ? | 0 | 0 | EXP19_ | NULL | NULL | EXP19_.SI | 7 | 9 | MC_SI_EXPORT +SPPTERM | 1 | IV_TRUE | EXP20_.EXP +SPPTERM | 2 | IV_TRUE | A_23_IBUF | IV_FALSE | IDE_BASEADR<7> +SPPTERM | 2 | IV_FALSE | A_23_IBUF | IV_TRUE | IDE_BASEADR<7> +SPPTERM | 2 | IV_TRUE | A_22_IBUF | IV_FALSE | IDE_BASEADR<6> +SPPTERM | 2 | IV_FALSE | A_22_IBUF | IV_TRUE | IDE_BASEADR<6> +SPPTERM | 2 | IV_TRUE | IDE_BASEADR<1> | IV_FALSE | A_17_IBUF + +MACROCELL_INSTANCE | NULL | EXP20_ | LAN_IDE_CP_COPY_0_COPY_0 | 2147483648 | 4 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_21_IBUF | 4935 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_21_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | IDE_BASEADR<5> | 4945 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_BASEADR<5>.Q | IDE_BASEADR<5> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | IDE_BASEADR<4> | 4944 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_BASEADR<4>.Q | IDE_BASEADR<4> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_20_IBUF | 4970 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_20_IBUF | 0 | 5 | II_IMUX +OUTPUT_NODE_TYPE | 4 | 0 | MC_EXPORT +NODE | EXP20_.EXP | 5379 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | EXP20_.EXP | EXP20_ | 4 | 0 | MC_EXPORT + +SIGNAL_INSTANCE | EXP20_.SI | EXP20_ | 0 | 4 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_21_IBUF | 4935 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_21_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | IDE_BASEADR<5> | 4945 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_BASEADR<5>.Q | IDE_BASEADR<5> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | IDE_BASEADR<4> | 4944 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_BASEADR<4>.Q | IDE_BASEADR<4> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_20_IBUF | 4970 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_20_IBUF | 0 | 5 | II_IMUX +OUTPUT_NODE_TYPE | 7 | 9 | MC_SI_EXPORT +SIGNAL | NODE | EXP20_.EXP | 5375 | ? | 0 | 0 | EXP20_ | NULL | NULL | EXP20_.SI | 7 | 9 | MC_SI_EXPORT +SPPTERM | 2 | IV_FALSE | A_21_IBUF | IV_TRUE | IDE_BASEADR<5> +SPPTERM | 2 | IV_TRUE | IDE_BASEADR<4> | IV_FALSE | A_20_IBUF +SPPTERM | 2 | IV_FALSE | IDE_BASEADR<4> | IV_TRUE | A_20_IBUF + +MACROCELL_INSTANCE | NULL | EXP21_ | LAN_IDE_CP_COPY_0_COPY_0 | 2147483648 | 7 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | IDE_BASEADR<0> | 4943 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_BASEADR<0>.Q | IDE_BASEADR<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_16_IBUF | 4969 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_16_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | IDE_BASEADR<1> | 4947 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_BASEADR<1>.Q | IDE_BASEADR<1> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_17_IBUF | 4968 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_17_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | IDE_BASEADR<2> | 4948 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_BASEADR<2>.Q | IDE_BASEADR<2> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_18_IBUF | 4971 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_18_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | autoconfig.EXP | 5380 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.EXP | autoconfig | 4 | 0 | MC_EXPORT +OUTPUT_NODE_TYPE | 4 | 0 | MC_EXPORT +NODE | EXP21_.EXP | 5381 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | EXP21_.EXP | EXP21_ | 4 | 0 | MC_EXPORT + +SIGNAL_INSTANCE | EXP21_.SI | EXP21_ | 0 | 7 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | IDE_BASEADR<0> | 4943 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_BASEADR<0>.Q | IDE_BASEADR<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_16_IBUF | 4969 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_16_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | IDE_BASEADR<1> | 4947 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_BASEADR<1>.Q | IDE_BASEADR<1> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_17_IBUF | 4968 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_17_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | IDE_BASEADR<2> | 4948 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_BASEADR<2>.Q | IDE_BASEADR<2> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_18_IBUF | 4971 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_18_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | autoconfig.EXP | 5380 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.EXP | autoconfig | 4 | 0 | MC_EXPORT +OUTPUT_NODE_TYPE | 7 | 9 | MC_SI_EXPORT +SIGNAL | NODE | EXP21_.EXP | 5377 | ? | 0 | 0 | EXP21_ | NULL | NULL | EXP21_.SI | 7 | 9 | MC_SI_EXPORT +SPPTERM | 1 | IV_TRUE | autoconfig.EXP +SPPTERM | 2 | IV_TRUE | IDE_BASEADR<0> | IV_FALSE | A_16_IBUF +SPPTERM | 2 | IV_FALSE | IDE_BASEADR<0> | IV_TRUE | A_16_IBUF +SPPTERM | 2 | IV_FALSE | IDE_BASEADR<1> | IV_TRUE | A_17_IBUF +SPPTERM | 2 | IV_TRUE | IDE_BASEADR<2> | IV_FALSE | A_18_IBUF +SPPTERM | 2 | IV_FALSE | IDE_BASEADR<2> | IV_TRUE | A_18_IBUF + +MACROCELL_INSTANCE | NULL | EXP22_ | LAN_IDE_CP_COPY_0_COPY_0 | 2147483648 | 14 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | Dout1<3>.UIM | 4922 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | HPART_CREATED_3.Q | _13_ | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<0> | 4937 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<0>.Q | AUTO_CONFIG_DONE<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<1> | 4938 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<1>.Q | AUTO_CONFIG_DONE<1> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<2> | 4939 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<2>.Q | AUTO_CONFIG_DONE<2> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_5_IBUF | 4927 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_1_IBUF | 4929 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_6_IBUF | 4930 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_6_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_3_IBUF | 4931 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | autoconfig | 4957 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.Q | autoconfig | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_4_IBUF | 4928 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_4_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_2_IBUF | 4932 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX +OUTPUT_NODE_TYPE | 4 | 0 | MC_EXPORT +NODE | EXP22_.EXP | 5384 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | EXP22_.EXP | EXP22_ | 4 | 0 | MC_EXPORT + +SIGNAL_INSTANCE | EXP22_.SI | EXP22_ | 0 | 14 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | Dout1<3>.UIM | 4922 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | HPART_CREATED_3.Q | _13_ | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<0> | 4937 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<0>.Q | AUTO_CONFIG_DONE<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<1> | 4938 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<1>.Q | AUTO_CONFIG_DONE<1> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<2> | 4939 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<2>.Q | AUTO_CONFIG_DONE<2> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_5_IBUF | 4927 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_1_IBUF | 4929 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_6_IBUF | 4930 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_6_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_3_IBUF | 4931 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | autoconfig | 4957 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.Q | autoconfig | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_4_IBUF | 4928 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_4_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_2_IBUF | 4932 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX +OUTPUT_NODE_TYPE | 7 | 9 | MC_SI_EXPORT +SIGNAL | NODE | EXP22_.EXP | 5382 | ? | 0 | 0 | EXP22_ | NULL | NULL | EXP22_.SI | 7 | 9 | MC_SI_EXPORT +SPPTERM | 5 | IV_TRUE | RESET_IBUF | IV_FALSE | Dout1<3>.UIM | IV_TRUE | AUTO_CONFIG_DONE<0> | IV_TRUE | AUTO_CONFIG_DONE<1> | IV_TRUE | AUTO_CONFIG_DONE<2> +SPPTERM | 9 | IV_TRUE | RESET_IBUF | IV_TRUE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_TRUE | A_1_IBUF | IV_FALSE | A_6_IBUF | IV_FALSE | A_3_IBUF | IV_FALSE | AUTO_CONFIG_DONE<0> | IV_TRUE | autoconfig +SPPTERM | 10 | IV_TRUE | RESET_IBUF | IV_TRUE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_FALSE | A_4_IBUF | IV_TRUE | A_6_IBUF | IV_FALSE | A_3_IBUF | IV_FALSE | A_2_IBUF | IV_FALSE | AUTO_CONFIG_DONE<0> | IV_TRUE | autoconfig +SPPTERM | 10 | IV_TRUE | RESET_IBUF | IV_TRUE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_FALSE | A_4_IBUF | IV_TRUE | A_6_IBUF | IV_FALSE | A_3_IBUF | IV_FALSE | A_2_IBUF | IV_FALSE | AUTO_CONFIG_DONE<1> | IV_TRUE | autoconfig + +MACROCELL_INSTANCE | NULL | EXP23_ | LAN_IDE_CP_COPY_0_COPY_0 | 2147483648 | 13 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_5_IBUF | 4927 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_4_IBUF | 4928 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_4_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_6_IBUF | 4930 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_6_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_3_IBUF | 4931 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_2_IBUF | 4932 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<2> | 4939 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<2>.Q | AUTO_CONFIG_DONE<2> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | autoconfig | 4957 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.Q | autoconfig | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_1_IBUF | 4929 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<1> | 4938 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<1>.Q | AUTO_CONFIG_DONE<1> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<0> | 4937 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<0>.Q | AUTO_CONFIG_DONE<0> | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 4 | 0 | MC_EXPORT +NODE | EXP23_.EXP | 5385 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | EXP23_.EXP | EXP23_ | 4 | 0 | MC_EXPORT + +SIGNAL_INSTANCE | EXP23_.SI | EXP23_ | 0 | 13 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_5_IBUF | 4927 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_4_IBUF | 4928 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_4_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_6_IBUF | 4930 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_6_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_3_IBUF | 4931 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_2_IBUF | 4932 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<2> | 4939 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<2>.Q | AUTO_CONFIG_DONE<2> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | autoconfig | 4957 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.Q | autoconfig | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_1_IBUF | 4929 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<1> | 4938 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<1>.Q | AUTO_CONFIG_DONE<1> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | AUTO_CONFIG_DONE<0> | 4937 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<0>.Q | AUTO_CONFIG_DONE<0> | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 7 | 9 | MC_SI_EXPORT +SIGNAL | NODE | EXP23_.EXP | 5383 | ? | 0 | 0 | EXP23_ | NULL | NULL | EXP23_.SI | 7 | 9 | MC_SI_EXPORT +SPPTERM | 10 | IV_TRUE | RESET_IBUF | IV_TRUE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_FALSE | A_4_IBUF | IV_TRUE | A_6_IBUF | IV_FALSE | A_3_IBUF | IV_FALSE | A_2_IBUF | IV_FALSE | AUTO_CONFIG_DONE<2> | IV_TRUE | autoconfig +SPPTERM | 10 | IV_TRUE | RESET_IBUF | IV_TRUE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_TRUE | A_1_IBUF | IV_FALSE | A_6_IBUF | IV_FALSE | A_3_IBUF | IV_TRUE | AUTO_CONFIG_DONE<1> | IV_FALSE | AUTO_CONFIG_DONE<2> | IV_TRUE | autoconfig +SPPTERM | 11 | IV_TRUE | RESET_IBUF | IV_TRUE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_TRUE | A_4_IBUF | IV_TRUE | A_1_IBUF | IV_FALSE | A_6_IBUF | IV_TRUE | A_2_IBUF | IV_TRUE | AUTO_CONFIG_DONE<0> | IV_FALSE | AUTO_CONFIG_DONE<1> | IV_TRUE | autoconfig +SPPTERM | 12 | IV_TRUE | RESET_IBUF | IV_TRUE | RW_IBUF | IV_FALSE | AS_IBUF | IV_TRUE | A_5_IBUF | IV_FALSE | A_4_IBUF | IV_FALSE | A_1_IBUF | IV_FALSE | A_6_IBUF | IV_FALSE | A_3_IBUF | IV_TRUE | A_2_IBUF | IV_TRUE | AUTO_CONFIG_DONE<0> | IV_FALSE | AUTO_CONFIG_DONE<1> | IV_TRUE | autoconfig +SPPTERM | 12 | IV_TRUE | RESET_IBUF | IV_TRUE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_TRUE | A_4_IBUF | IV_FALSE | A_1_IBUF | IV_FALSE | A_6_IBUF | IV_TRUE | A_3_IBUF | IV_FALSE | A_2_IBUF | IV_TRUE | AUTO_CONFIG_DONE<0> | IV_FALSE | AUTO_CONFIG_DONE<1> | IV_TRUE | autoconfig + +FB_INSTANCE | FOOBAR1_ | LAN_IDE_CP_COPY_0_COPY_0 | 0 | 0 | 0 +FBPIN | 1 | IDE_CS_1_OBUF | 1 | NULL | 0 | IDE_CS<1> | 1 | 23 | 49152 +FBPIN | 2 | N1$BUF1 | 1 | NULL | 0 | D<7> | 1 | 16 | 49152 +FBPIN | 3 | N1$BUF7 | 1 | NULL | 0 | D<1> | 1 | 17 | 49152 +FBPIN | 4 | IDE_A_2_OBUF$BUF0 | 1 | NULL | 0 | IDE_A<2> | 1 | 25 | 49152 +FBPIN | 5 | N1$BUF0 | 1 | N5 | 1 | D<8> | 1 | 19 | 49152 +FBPIN | 6 | N1$BUF3 | 1 | NULL | 0 | D<5> | 1 | 20 | 49152 +FBPIN | 7 | AUTOCONFIG_IN_PROGRESS | 1 | NULL | 0 | NULL | 0 +FBPIN | 8 | N1$BUF4 | 1 | NULL | 0 | D<4> | 1 | 21 | 49152 +FBPIN | 9 | IDE_CS_0_OBUF | 1 | NULL | 0 | IDE_CS<0> | 1 | 22 | 49152 +FBPIN | 10 | IDE_ENABLE | 1 | NULL | 0 | NULL | 0 | 31 | 49152 +FBPIN | 11 | IDE_A_0_OBUF$BUF0 | 1 | NULL | 0 | IDE_A<0> | 1 | 24 | 49152 +FBPIN | 12 | IDE_A_1_OBUF$BUF0 | 1 | NULL | 0 | IDE_A<1> | 1 | 26 | 49152 +FBPIN | 14 | IDE_R_S | 1 | NULL | 0 | IDE_R | 1 | 27 | 49152 +FBPIN | 15 | IDE_W_S | 1 | NULL | 0 | IDE_W | 1 | 28 | 49152 +FBPIN | 16 | ROM_OE_S | 1 | NULL | 0 | ROM_OE | 1 | 35 | 49152 +FBPIN | 17 | EXP14_ | 1 | NULL | 0 | NULL | 0 | 30 | 57344 +FBPIN | 18 | D<12>_BUFR.MC | 1 | NULL | 0 | NULL | 0 + +FB_INSTANCE | FOOBAR2_ | LAN_IDE_CP_COPY_0_COPY_0 | 0 | 0 | 0 +FBPIN | 1 | D<14>_BUFR.MC | 1 | NULL | 0 | NULL | 0 | 142 | 49152 +FBPIN | 2 | EXP15_ | 1 | RESET_IBUF | 1 | NULL | 0 | 143 | 51200 +FBPIN | 3 | EXP16_ | 1 | NULL | 0 | NULL | 0 +FBPIN | 5 | N1$BUF10 | 1 | NULL | 0 | D<0> | 1 | 2 | 53248 +FBPIN | 8 | AUTO_CONFIG_DONE<2> | 1 | NULL | 0 | NULL | 0 | 5 | 53248 +FBPIN | 9 | AUTO_CONFIG_DONE<0> | 1 | NULL | 0 | NULL | 0 | 6 | 53248 +FBPIN | 10 | AUTO_CONFIG_DONE_CYCLE<2> | 1 | NULL | 0 | NULL | 0 | 7 | 49152 +FBPIN | 11 | AUTO_CONFIG_DONE_CYCLE<0> | 1 | NULL | 0 | NULL | 0 | 9 | 49152 +FBPIN | 12 | IDE_BASEADR<7> | 1 | NULL | 0 | NULL | 0 | 10 | 49152 +FBPIN | 13 | IDE_BASEADR<6> | 1 | NULL | 0 | NULL | 0 | 12 | 49152 +FBPIN | 14 | EXP17_ | 1 | NULL | 0 | NULL | 0 | 11 | 49152 +FBPIN | 15 | D<13>_BUFR.MC | 1 | NULL | 0 | NULL | 0 | 13 | 49152 +FBPIN | 16 | N1$BUF2 | 1 | NULL | 0 | D<6> | 1 | 14 | 49152 +FBPIN | 17 | N1$BUF5 | 1 | NULL | 0 | D<3> | 1 | 15 | 49152 +FBPIN | 18 | EXP18_ | 1 | NULL | 0 | NULL | 0 + +FB_INSTANCE | FOOBAR3_ | LAN_IDE_CP_COPY_0_COPY_0 | 0 | 0 | 0 +FBPIN | 1 | N1$BUF6 | 1 | NULL | 0 | D<2> | 1 | 39 | 49152 +FBPIN | 3 | N1$BUF9 | 1 | N7 | 1 | D<10> | 1 | 41 | 49152 +FBPIN | 4 | _10_ | 1 | N11 | 1 | D<12> | 1 | 44 | 49152 +FBPIN | 7 | _11_ | 1 | N3 | 1 | D<14> | 1 | 46 | 49152 +FBPIN | 9 | N1 | 1 | N6 | 1 | D<9> | 1 | 40 | 49152 +FBPIN | 10 | _13_ | 1 | N4 | 1 | D<15> | 1 | 48 | 49152 +FBPIN | 11 | N1$BUF8 | 1 | N0 | 1 | D<11> | 1 | 43 | 49152 +FBPIN | 12 | _12_ | 1 | N2 | 1 | D<13> | 1 | 45 | 49152 +FBPIN | 14 | NULL | 0 | A_5_IBUF | 1 | NULL | 0 | 49 | 49152 +FBPIN | 15 | AUTO_CONFIG_DONE<1> | 1 | A_4_IBUF | 1 | NULL | 0 | 50 | 49152 +FBPIN | 16 | AUTO_CONFIG_DONE_CYCLE<1> | 1 | NULL | 0 | NULL | 0 +FBPIN | 17 | IDE_BASEADR<3> | 1 | A_6_IBUF | 1 | NULL | 0 | 51 | 49152 +FBPIN | 18 | IDE_BASEADR<2> | 1 | NULL | 0 | NULL | 0 + +FB_INSTANCE | FOOBAR4_ | LAN_IDE_CP_COPY_0_COPY_0 | 0 | 0 | 0 +FBPIN | 1 | ide | 1 | NULL | 0 | NULL | 0 | 118 | 49152 +FBPIN | 2 | EXP19_ | 1 | NULL | 0 | NULL | 0 | 126 | 49152 +FBPIN | 3 | EXP20_ | 1 | NULL | 0 | NULL | 0 | 133 | 49152 +FBPIN | 16 | ide/ide_CLKF | 1 | NULL | 0 | NULL | 0 | 139 | 49152 +FBPIN | 17 | autoconfig | 1 | NULL | 0 | NULL | 0 | 140 | 49152 +FBPIN | 18 | EXP21_ | 1 | NULL | 0 | NULL | 0 + +FB_INSTANCE | FOOBAR5_ | LAN_IDE_CP_COPY_0_COPY_0 | 0 | 0 | 0 +FBPIN | 2 | NULL | 0 | A_3_IBUF | 1 | NULL | 0 | 52 | 49152 +FBPIN | 3 | NULL | 0 | IDE_A_1_OBUF | 1 | NULL | 0 | 59 | 49152 +FBPIN | 6 | NULL | 0 | A_2_IBUF | 1 | NULL | 0 | 54 | 49152 +FBPIN | 9 | NULL | 0 | A_1_IBUF | 1 | NULL | 0 | 57 | 49152 +FBPIN | 10 | ROM_B_0_OBUF$BUF0 | 1 | NULL | 0 | ROM_B<0> | 1 | 68 | 49152 +FBPIN | 11 | NULL | 0 | IDE_A_0_OBUF | 1 | NULL | 0 | 58 | 49152 +FBPIN | 12 | NULL | 0 | IDE_A_2_OBUF | 1 | NULL | 0 | 60 | 49152 +FBPIN | 13 | SHUT_UP<1> | 1 | NULL | 0 | NULL | 0 | 70 | 49152 +FBPIN | 14 | IDE_BASEADR<5> | 1 | A_12_IBUF | 1 | NULL | 0 | 61 | 49152 +FBPIN | 15 | IDE_BASEADR<4> | 1 | A_13_IBUF | 1 | NULL | 0 | 64 | 49152 +FBPIN | 16 | IDE_BASEADR<1> | 1 | NULL | 0 | NULL | 0 +FBPIN | 17 | ROM_B_0_OBUF | 1 | NULL | 0 | ROM_B<1> | 1 | 69 | 49152 +FBPIN | 18 | IDE_BASEADR<0> | 1 | NULL | 0 | NULL | 0 + +FB_INSTANCE | FOOBAR6_ | LAN_IDE_CP_COPY_0_COPY_0 | 0 | 0 | 0 +FBPIN | 16 | EXP22_ | 1 | NULL | 0 | NULL | 0 | 117 | 49152 +FBPIN | 17 | D<15>_BUFR.MC | 1 | NULL | 0 | NULL | 0 | 125 | 49152 +FBPIN | 18 | EXP23_ | 1 | NULL | 0 | NULL | 0 + +FB_INSTANCE | FOOBAR7_ | LAN_IDE_CP_COPY_0_COPY_0 | 0 | 0 | 0 +FBPIN | 3 | NULL | 0 | AUTOBOOT_OFF_IBUF | 1 | NULL | 0 | 75 | 49152 +FBPIN | 9 | NULL | 0 | AS_IBUF | 1 | NULL | 0 | 80 | 49152 +FBPIN | 12 | ROM_B_0_OBUF$BUF1 | 1 | NULL | 0 | DTACK | 1 | 85 | 49152 +FBPIN | 13 | NULL | 0 | UDS_IBUF | 1 | NULL | 0 | 81 | 49152 +FBPIN | 14 | NULL | 0 | A_23_IBUF | 1 | NULL | 0 | 86 | 49152 +FBPIN | 15 | NULL | 0 | A_22_IBUF | 1 | NULL | 0 | 87 | 49152 +FBPIN | 16 | NULL | 0 | RW_IBUF | 1 | NULL | 0 | 83 | 49152 +FBPIN | 17 | NULL | 0 | A_21_IBUF | 1 | NULL | 0 | 88 | 49152 + +FB_INSTANCE | FOOBAR8_ | LAN_IDE_CP_COPY_0_COPY_0 | 0 | 0 | 0 +FBPIN | 2 | NULL | 0 | A_20_IBUF | 1 | NULL | 0 | 91 | 49152 +FBPIN | 3 | NULL | 0 | A_17_IBUF | 1 | NULL | 0 | 95 | 49152 +FBPIN | 4 | NULL | 0 | A_16_IBUF | 1 | NULL | 0 | 97 | 49152 +FBPIN | 5 | NULL | 0 | A_19_IBUF | 1 | NULL | 0 | 92 | 49152 +FBPIN | 8 | NULL | 0 | A_18_IBUF | 1 | NULL | 0 | 94 | 49152 +FBPIN | 11 | NULL | 0 | BERR_IBUF | 1 | NULL | 0 | 98 | 49152 +FBPIN | 13 | NULL | 0 | C1_IBUF | 1 | NULL | 0 | 103 | 49152 +FBPIN | 14 | NULL | 0 | C3_IBUF | 1 | NULL | 0 | 102 | 49152 + +FB_INSTANCE | INPUTPINS_FOOBAR9_ | LAN_IDE_CP_COPY_0_COPY_0 | 0 | 0 | 0 + +BUSINFO | A<23:1> | 23 | 0 | 0 | A<10> | 13 | A<11> | 12 | A<12> | 11 | A<13> | 10 | A<14> | 9 | A<15> | 8 | A<16> | 7 | A<17> | 6 | A<18> | 5 | A<19> | 4 | A<1> | 22 | A<20> | 3 | A<21> | 2 | A<22> | 1 | A<23> | 0 | A<2> | 21 | A<3> | 20 | A<4> | 19 | A<5> | 18 | A<6> | 17 | A<7> | 16 | A<8> | 15 | A<9> | 14 +BUSINFO | D<15:0> | 16 | 0 | 2 | D<0> | 15 | D<10> | 5 | D<11> | 4 | D<12> | 3 | D<13> | 2 | D<14> | 1 | D<15> | 0 | D<1> | 14 | D<2> | 13 | D<3> | 12 | D<4> | 11 | D<5> | 10 | D<6> | 9 | D<7> | 8 | D<8> | 7 | D<9> | 6 +BUSINFO | DQ<15:0> | 16 | 0 | 0 | DQ<0> | 15 | DQ<10> | 5 | DQ<11> | 4 | DQ<12> | 3 | DQ<13> | 2 | DQ<14> | 1 | DQ<15> | 0 | DQ<1> | 14 | DQ<2> | 13 | DQ<3> | 12 | DQ<4> | 11 | DQ<5> | 10 | DQ<6> | 9 | DQ<7> | 8 | DQ<8> | 7 | DQ<9> | 6 +BUSINFO | IDE_A<2:0> | 3 | 0 | 1 | IDE_A<0> | 2 | IDE_A<1> | 1 | IDE_A<2> | 0 +BUSINFO | IDE_CS<1:0> | 2 | 0 | 1 | IDE_CS<0> | 1 | IDE_CS<1> | 0 +BUSINFO | ROM_B<1:0> | 2 | 0 | 1 | ROM_B<0> | 1 | ROM_B<1> | 0 + +FB_ORDER_OF_INPUTS | FOOBAR1_ | 0 | RESET | 143 | 1 | AS | 80 | 3 | Dout1<0>.UIM | NULL | 6 | AUTOCONFIG_IN_PROGRESS | NULL | 7 | AUTO_CONFIG_DONE<2> | NULL +FB_ORDER_OF_INPUTS | FOOBAR1_ | 12 | RW | 83 | 13 | AUTOBOOT_OFF | 75 | 14 | A<12> | 61 | 19 | A<10> | 59 | 20 | ide | NULL +FB_ORDER_OF_INPUTS | FOOBAR1_ | 21 | AUTO_CONFIG_DONE<0> | NULL | 22 | A<6> | 51 | 24 | A<2> | 54 | 27 | A<4> | 50 | 28 | autoconfig | NULL +FB_ORDER_OF_INPUTS | FOOBAR1_ | 32 | A<9> | 58 | 35 | AUTO_CONFIG_DONE<1> | NULL | 36 | A<5> | 49 | 38 | A<1> | 57 | 40 | A<13> | 64 +FB_ORDER_OF_INPUTS | FOOBAR1_ | 47 | A<3> | 52 | 50 | ide/ide_CLKF.UIM | NULL | 51 | IDE_ENABLE | NULL | 53 | A<11> | 60 + +FB_IMUX_INDEX | FOOBAR1_ | 176 | 227 | -1 | 39 | -1 | -1 | 6 | 25 | -1 | -1 | -1 | -1 | 221 | 239 | 257 | -1 | -1 | -1 | -1 | 263 | 54 | 26 | 274 | -1 | 273 | -1 | -1 | 272 | 70 | -1 | -1 | -1 | 267 | -1 | -1 | 50 | 268 | -1 | 269 | -1 | 255 | -1 | -1 | -1 | -1 | -1 | -1 | 276 | -1 | -1 | 69 | 9 | -1 | 259 + + +FB_ORDER_OF_INPUTS | FOOBAR2_ | 0 | RESET | 143 | 1 | AS | 80 | 2 | D<14> | 46 | 4 | D<15> | 48 | 6 | AUTOCONFIG_IN_PROGRESS | NULL +FB_ORDER_OF_INPUTS | FOOBAR2_ | 7 | AUTO_CONFIG_DONE<2> | NULL | 9 | AUTO_CONFIG_DONE_CYCLE<2> | NULL | 10 | AUTO_CONFIG_DONE_CYCLE<0> | NULL | 11 | IDE_BASEADR<7> | NULL | 12 | RW | 83 +FB_ORDER_OF_INPUTS | FOOBAR2_ | 16 | UDS | 81 | 21 | AUTO_CONFIG_DONE<0> | NULL | 22 | A<6> | 51 | 23 | Dout1<2>.UIM | NULL | 24 | A<2> | 54 +FB_ORDER_OF_INPUTS | FOOBAR2_ | 27 | A<4> | 50 | 28 | autoconfig | NULL | 34 | Dout1<1>.UIM | NULL | 35 | AUTO_CONFIG_DONE<1> | NULL | 36 | A<5> | 49 +FB_ORDER_OF_INPUTS | FOOBAR2_ | 38 | A<1> | 57 | 45 | IDE_BASEADR<6> | NULL | 47 | A<3> | 52 | 50 | ide/ide_CLKF.UIM | NULL + +FB_IMUX_INDEX | FOOBAR2_ | 176 | 227 | 262 | -1 | 264 | -1 | 6 | 25 | -1 | 27 | 28 | 29 | 221 | -1 | -1 | -1 | 225 | -1 | -1 | -1 | -1 | 26 | 274 | 42 | 273 | -1 | -1 | 272 | 70 | -1 | -1 | -1 | -1 | -1 | 47 | 50 | 268 | -1 | 269 | -1 | -1 | -1 | -1 | -1 | -1 | 30 | -1 | 276 | -1 | -1 | 69 | -1 | -1 | -1 + + +FB_ORDER_OF_INPUTS | FOOBAR3_ | 0 | RESET | 143 | 1 | AS | 80 | 6 | AUTOCONFIG_IN_PROGRESS | NULL | 11 | D<10> | 41 | 12 | RW | 83 +FB_ORDER_OF_INPUTS | FOOBAR3_ | 16 | UDS | 81 | 17 | IDE_BASEADR<2> | NULL | 18 | D<11> | 43 | 21 | AUTO_CONFIG_DONE<0> | NULL | 22 | A<6> | 51 +FB_ORDER_OF_INPUTS | FOOBAR3_ | 24 | A<2> | 54 | 26 | D<12>_BUFR | NULL | 27 | A<4> | 50 | 28 | autoconfig | NULL | 31 | D<15>_BUFR | NULL +FB_ORDER_OF_INPUTS | FOOBAR3_ | 35 | AUTO_CONFIG_DONE<1> | NULL | 36 | A<5> | 49 | 37 | D<13>_BUFR | NULL | 38 | A<1> | 57 | 47 | A<3> | 52 +FB_ORDER_OF_INPUTS | FOOBAR3_ | 49 | D<14>_BUFR | NULL | 50 | ide/ide_CLKF.UIM | NULL | 52 | AUTO_CONFIG_DONE_CYCLE<1> | NULL | 53 | IDE_BASEADR<3> | NULL + +FB_IMUX_INDEX | FOOBAR3_ | 176 | 227 | -1 | -1 | -1 | -1 | 6 | -1 | -1 | -1 | -1 | 254 | 221 | -1 | -1 | -1 | 225 | 53 | 256 | -1 | -1 | 26 | 274 | -1 | 273 | -1 | 17 | 272 | 70 | -1 | -1 | 106 | -1 | -1 | -1 | 50 | 268 | 32 | 269 | -1 | -1 | -1 | -1 | -1 | -1 | -1 | -1 | 276 | -1 | 18 | 69 | -1 | 51 | 52 + + +FB_ORDER_OF_INPUTS | FOOBAR4_ | 0 | A<19> | 92 | 2 | A<20> | 91 | 6 | A<22> | 87 | 7 | AUTO_CONFIG_DONE<2> | NULL | 11 | IDE_BASEADR<7> | NULL +FB_ORDER_OF_INPUTS | FOOBAR4_ | 12 | SHUT_UP<1> | NULL | 13 | IDE_BASEADR<5> | NULL | 16 | IDE_BASEADR<3> | NULL | 17 | A<21> | 88 | 21 | AUTO_CONFIG_DONE<0> | NULL +FB_ORDER_OF_INPUTS | FOOBAR4_ | 22 | IDE_BASEADR<4> | NULL | 23 | C3 | 102 | 26 | IDE_BASEADR<1> | NULL | 27 | A<23> | 86 | 28 | IDE_BASEADR<2> | NULL +FB_ORDER_OF_INPUTS | FOOBAR4_ | 29 | A<18> | 94 | 34 | BERR | 98 | 35 | AUTO_CONFIG_DONE<1> | NULL | 36 | A<16> | 97 | 44 | IDE_BASEADR<0> | NULL +FB_ORDER_OF_INPUTS | FOOBAR4_ | 47 | IDE_BASEADR<6> | NULL | 50 | ide/ide_CLKF.UIM | NULL | 51 | A<17> | 95 | 53 | C1 | 103 + +FB_IMUX_INDEX | FOOBAR4_ | 209 | -1 | 211 | -1 | -1 | -1 | 215 | 25 | -1 | -1 | -1 | 29 | 84 | 85 | -1 | -1 | 52 | 213 | -1 | -1 | -1 | 26 | 86 | 189 | -1 | -1 | 87 | 217 | 53 | 205 | -1 | -1 | -1 | -1 | 197 | 50 | 199 | -1 | -1 | -1 | -1 | -1 | -1 | -1 | 89 | -1 | -1 | 30 | -1 | -1 | 69 | 203 | -1 | 187 + + +FB_ORDER_OF_INPUTS | FOOBAR5_ | 0 | RESET | 143 | 1 | AS | 80 | 12 | RW | 83 | 13 | IDE_BASEADR<5> | NULL | 14 | IDE_BASEADR<4> | NULL +FB_ORDER_OF_INPUTS | FOOBAR5_ | 15 | D<12> | 44 | 16 | UDS | 81 | 19 | SHUT_UP<1> | NULL | 21 | AUTO_CONFIG_DONE<0> | NULL | 22 | A<6> | 51 +FB_ORDER_OF_INPUTS | FOOBAR5_ | 24 | A<2> | 54 | 26 | IDE_BASEADR<1> | NULL | 27 | A<4> | 50 | 28 | autoconfig | NULL | 29 | D<13> | 45 +FB_ORDER_OF_INPUTS | FOOBAR5_ | 35 | AUTO_CONFIG_DONE<1> | NULL | 36 | A<5> | 49 | 38 | A<1> | 57 | 44 | IDE_BASEADR<0> | NULL | 46 | D<8> | 19 +FB_ORDER_OF_INPUTS | FOOBAR5_ | 47 | A<3> | 52 | 50 | ide/ide_CLKF.UIM | NULL | 52 | D<9> | 40 + +FB_IMUX_INDEX | FOOBAR5_ | 176 | 227 | -1 | -1 | -1 | -1 | -1 | -1 | -1 | -1 | -1 | -1 | 221 | 85 | 86 | 258 | 225 | -1 | -1 | 84 | -1 | 26 | 274 | -1 | 273 | -1 | 87 | 272 | 70 | 260 | -1 | -1 | -1 | -1 | -1 | 50 | 268 | -1 | 269 | -1 | -1 | -1 | -1 | -1 | 89 | -1 | 212 | 276 | -1 | -1 | 69 | -1 | 252 | -1 + + +FB_ORDER_OF_INPUTS | FOOBAR6_ | 0 | RESET | 143 | 1 | AS | 80 | 7 | AUTO_CONFIG_DONE<2> | NULL | 12 | RW | 83 | 18 | Dout1<3>.UIM | NULL +FB_ORDER_OF_INPUTS | FOOBAR6_ | 21 | AUTO_CONFIG_DONE<0> | NULL | 22 | A<6> | 51 | 24 | A<2> | 54 | 27 | A<4> | 50 | 28 | autoconfig | NULL +FB_ORDER_OF_INPUTS | FOOBAR6_ | 35 | AUTO_CONFIG_DONE<1> | NULL | 36 | A<5> | 49 | 38 | A<1> | 57 | 47 | A<3> | 52 | 50 | ide/ide_CLKF.UIM | NULL + +FB_IMUX_INDEX | FOOBAR6_ | 176 | 227 | -1 | -1 | -1 | -1 | -1 | 25 | -1 | -1 | -1 | -1 | 221 | -1 | -1 | -1 | -1 | -1 | 45 | -1 | -1 | 26 | 274 | -1 | 273 | -1 | -1 | 272 | 70 | -1 | -1 | -1 | -1 | -1 | -1 | 50 | 268 | -1 | 269 | -1 | -1 | -1 | -1 | -1 | -1 | -1 | -1 | 276 | -1 | -1 | 69 | -1 | -1 | -1 + + +GLOBAL_FSR | RESET | 0 | 0 diff --git a/Logic/LAN_IDE/LAN_IDE_CP.xml b/Logic/LAN_IDE/LAN_IDE_CP.xml new file mode 100644 index 0000000..1b59ec2 --- /dev/null +++ b/Logic/LAN_IDE/LAN_IDE_CP.xml @@ -0,0 +1,3 @@ + + +LAN_IDE_CP.rptC:/Xilinx/14.6/ISE_DS/ISE/xc9500xl/data/xc95144xl.chpLAN_IDE_CP.mfd
Cpld - Unable to retrieve the path to the iSE Project Repository. Will use the default filename of 'LAN_IDE_CP.ise'.INFO:Cpld - Inferring BUFG constraint for signal 'CLK_EXT' based upon the LOC constraint 'P30'. It is recommended that you declare this BUFG explicitedly in your design. Note that for certain device families the output of a BUFG constraint can not drive a gated clock, and the BUFG constraint will be ignored.Cpld:936 - The output buffer 'SLAVE_OBUF' is missing an input and will be deleted.Cpld:936 - The output buffer 'OWN_OBUF' is missing an input and will be deleted.Cpld:936 - The output buffer 'OVR_OBUF' is missing an input and will be deleted.Cpld:936 - The output buffer 'MTACK_OBUF' is missing an input and will be deleted.Cpld:936 - The output buffer 'LAN_WRH_OBUF' is missing an input and will be deleted.Cpld:936 - The output buffer 'LAN_RD_OBUF' is missing an input and will be deleted.Cpld:936 - The output buffer 'LAN_EN_OBUF' is missing an input and will be deleted.Cpld:936 - The output buffer 'LAN_CS_OBUF' is missing an input and will be deleted.Cpld:936 - The output buffer 'LAN_CFG<4>_OBUF' is missing an input and will be deleted.Cpld:936 - The output buffer 'LAN_CFG<3>_OBUF' is missing an input and will be deleted.Cpld:936 - The output buffer 'LAN_CFG<2>_OBUF' is missing an input and will be deleted.Cpld:936 - The output buffer 'LAN_CFG<1>_OBUF' is missing an input and will be deleted.Cpld:936 - The output buffer 'INT_OUT_OBUF' is missing an input and will be deleted.Cpld:936 - The output buffer 'CP_WE_OBUF' is missing an input and will be deleted.Cpld:936 - The output buffer 'CP_RD_OBUF' is missing an input and will be deleted.Cpld:936 - The output buffer 'CP_CS_OBUF' is missing an input and will be deleted.Cpld:936 - The output buffer 'CFOUT_OBUF' is missing an input and will be deleted.Cpld:936 - The output buffer 'A_LAN<9>_OBUF' is missing an input and will be deleted.Cpld:936 - The output buffer 'A_LAN<8>_OBUF' is missing an input and will be deleted.Cpld:936 - The output buffer 'A_LAN<7>_OBUF' is missing an input and will be deleted.Cpld:936 - The output buffer 'A_LAN<6>_OBUF' is missing an input and will be deleted.Cpld:936 - The output buffer 'A_LAN<5>_OBUF' is missing an input and will be deleted.Cpld:936 - The output buffer 'A_LAN<4>_OBUF' is missing an input and will be deleted.Cpld:936 - The output buffer 'A_LAN<3>_OBUF' is missing an input and will be deleted.Cpld:936 - The output buffer 'A_LAN<2>_OBUF' is missing an input and will be deleted.Cpld:936 - The output buffer 'A_LAN<1>_OBUF' is missing an input and will be deleted.Cpld:936 - The output buffer 'A_LAN<13>_OBUF' is missing an input and will be deleted.Cpld:936 - The output buffer 'A_LAN<12>_OBUF' is missing an input and will be deleted.Cpld:936 - The output buffer 'A_LAN<11>_OBUF' is missing an input and will be deleted.Cpld:936 - The output buffer 'A_LAN<10>_OBUF' is missing an input and will be deleted.Cpld:936 - The output buffer 'A_LAN<0>_OBUF' is missing an input and will be deleted.Cpld:1007 - Removing unused input(s) 'A<14>'. The input(s) are unused after optimization. Please verify functionality via simulation.Cpld:1007 - Removing unused input(s) 'A<15>'. The input(s) are unused after optimization. Please verify functionality via simulation.Cpld:1007 - Removing unused input(s) 'A<7>'. The input(s) are unused after optimization. Please verify functionality via simulation.Cpld:1007 - Removing unused input(s) 'A<8>'. The input(s) are unused after optimization. Please verify functionality via simulation.Cpld:1007 - Removing unused input(s) 'CFIN'. The input(s) are unused after optimization. Please verify functionality via simulation.Cpld:1007 - Removing unused input(s) 'CLK_EXT'. The input(s) are unused after optimization. Please verify functionality via simulation.Cpld:1007 - Removing unused input(s) 'CP_IRQ'. The input(s) are unused after optimization. Please verify functionality via simulation.Cpld:1007 - Removing unused input(s) 'DQ<0>'. The input(s) are unused after optimization. Please verify functionality via simulation.Cpld:1007 - Removing unused input(s) 'DQ<10>'. The input(s) are unused after optimization. Please verify functionality via simulation.Cpld:1007 - Removing unused input(s) 'DQ<11>'. The input(s) are unused after optimization. Please verify functionality via simulation.Cpld:1007 - Removing unused input(s) 'DQ<12>'. The input(s) are unused after optimization. Please verify functionality via simulation.Cpld:1007 - Removing unused input(s) 'DQ<13>'. The input(s) are unused after optimization. Please verify functionality via simulation.Cpld:1007 - Removing unused input(s) 'DQ<14>'. The input(s) are unused after optimization. Please verify functionality via simulation.Cpld:1007 - Removing unused input(s) 'DQ<15>'. The input(s) are unused after optimization. Please verify functionality via simulation.Cpld:1007 - Removing unused input(s) 'DQ<1>'. The input(s) are unused after optimization. Please verify functionality via simulation.Cpld:1007 - Removing unused input(s) 'DQ<2>'. The input(s) are unused after optimization. Please verify functionality via simulation.Cpld:1007 - Removing unused input(s) 'DQ<3>'. The input(s) are unused after optimization. Please verify functionality via simulation.Cpld:1007 - Removing unused input(s) 'DQ<4>'. The input(s) are unused after optimization. Please verify functionality via simulation.Cpld:1007 - Removing unused input(s) 'DQ<5>'. The input(s) are unused after optimization. Please verify functionality via simulation.Cpld:1007 - Removing unused input(s) 'DQ<6>'. The input(s) are unused after optimization. Please verify functionality via simulation.Cpld:1007 - Removing unused input(s) 'DQ<7>'. The input(s) are unused after optimization. Please verify functionality via simulation.Cpld:1007 - Removing unused input(s) 'DQ<8>'. The input(s) are unused after optimization. Please verify functionality via simulation.Cpld:1007 - Removing unused input(s) 'DQ<9>'. The input(s) are unused after optimization. Please verify functionality via simulation.Cpld:1007 - Removing unused input(s) 'DS0'. The input(s) are unused after optimization. Please verify functionality via simulation.Cpld:1007 - Removing unused input(s) 'DS1'. The input(s) are unused after optimization. Please verify functionality via simulation.Cpld:1007 - Removing unused input(s) 'FCS'. The input(s) are unused after optimization. Please verify functionality via simulation.Cpld:1007 - Removing unused input(s) 'IDE_WAIT'. The input(s) are unused after optimization. Please verify functionality via simulation.Cpld:1007 - Removing unused input(s) 'LAN_INT'. The input(s) are unused after optimization. Please verify functionality via simulation.Cpld:1007 - Removing unused input(s) 'LDS'. The input(s) are unused after optimization. Please verify functionality via simulation.Cpld:1007 - Removing unused input(s) 'MTCR'. The input(s) are unused after optimization. Please verify functionality via simulation.Cpld:1007 - Removing unused input(s) 'Z3'. The input(s) are unused after optimization. Please verify functionality via simulation.Cpld:896 - Unable to map all desired signals into function block, FB3, because too many function block product terms are required. Buffering output signal D<12> to allow all signals assigned to this function block to be placed.Cpld:896 - Unable to map all desired signals into function block, FB3, because too many function block product terms are required. Buffering output signal D<14> to allow all signals assigned to this function block to be placed.Cpld:896 - Unable to map all desired signals into function block, FB3, because too many function block product terms are required. Buffering output signal D<13> to allow all signals assigned to this function block to be placed.Cpld:896 - Unable to map all desired signals into function block, FB3, because too many function block product terms are required. Buffering output signal D<15> to allow all signals assigned to this function block to be placed. diff --git a/Logic/LAN_IDE/LAN_IDE_CP.xst b/Logic/LAN_IDE/LAN_IDE_CP.xst new file mode 100644 index 0000000..20c79ef --- /dev/null +++ b/Logic/LAN_IDE/LAN_IDE_CP.xst @@ -0,0 +1,29 @@ +set -tmpdir "xst/projnav.tmp" +set -xsthdpdir "xst" +run +-ifn LAN_IDE_CP.prj +-ifmt mixed +-ofn LAN_IDE_CP +-ofmt NGC +-p xc9500xl +-top LAN_IDE_CP +-opt_mode Speed +-opt_level 1 +-iuc NO +-keep_hierarchy Yes +-netlist_hierarchy As_Optimized +-rtlview Yes +-hierarchy_separator / +-bus_delimiter <> +-case Maintain +-verilog2001 YES +-fsm_extract YES -fsm_encoding Auto +-safe_implementation No +-mux_extract Yes +-resource_sharing YES +-iobuf YES +-pld_mp YES +-pld_xp YES +-pld_ce YES +-wysiwyg NO +-equivalent_register_removal YES diff --git a/Logic/LAN_IDE/LAN_IDE_CP_build.xml b/Logic/LAN_IDE/LAN_IDE_CP_build.xml new file mode 100644 index 0000000..8123f19 --- /dev/null +++ b/Logic/LAN_IDE/LAN_IDE_CP_build.xml @@ -0,0 +1,249 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Logic/LAN_IDE/LAN_IDE_CP_envsettings.html b/Logic/LAN_IDE/LAN_IDE_CP_envsettings.html new file mode 100644 index 0000000..5c8516f --- /dev/null +++ b/Logic/LAN_IDE/LAN_IDE_CP_envsettings.html @@ -0,0 +1,244 @@ +Xilinx System Settings Report + +
System Settings

+ + 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Environment Settings
Environment Variablexstngdbuild
PATHEXT.COM;
.EXE;
.BAT;
.CMD;
.VBS;
.VBE;
.JS;
.JSE;
.WSF;
.WSH;
.MSC;
.PY		.COM;
.EXE;
.BAT;
.CMD;
.VBS;
.VBE;
.JS;
.JSE;
.WSF;
.WSH;
.MSC;
.PY
PathC:\Xilinx\14.6\ISE_DS\ISE\\lib\nt64;
C:\Xilinx\14.6\ISE_DS\ISE\\bin\nt64;
C:\Xilinx\14.6\ISE_DS\ISE\bin\nt64;
C:\Xilinx\14.6\ISE_DS\ISE\lib\nt64;
C:\Xilinx\14.6\ISE_DS\ISE\..\..\..\DocNav;
C:\Xilinx\14.6\ISE_DS\PlanAhead\bin;
C:\Xilinx\14.6\ISE_DS\EDK\bin\nt64;
C:\Xilinx\14.6\ISE_DS\EDK\lib\nt64;
C:\Xilinx\14.6\ISE_DS\EDK\gnu\microblaze\nt\bin;
C:\Xilinx\14.6\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;
C:\Xilinx\14.6\ISE_DS\EDK\gnuwin\bin;
C:\Xilinx\14.6\ISE_DS\EDK\gnu\arm\nt\bin;
C:\Xilinx\14.6\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;
C:\Xilinx\14.6\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;
C:\Xilinx\14.6\ISE_DS\common\bin\nt64;
C:\Xilinx\14.6\ISE_DS\common\lib\nt64;
E:\ispLEVER_Classic2_0\ispcpld\bin;
E:\ispLEVER_Classic2_0\ispFPGA\bin\nt;
E:\ispLEVER_Classic2_0\active-hdl\BIN;
C:\ProgramData\Oracle\Java\javapath;
C:\SynaptiCAD\bin\win32;
C:\Program Files\Java\jre7\bin;
C\Windows\System32;
C:\Program Files (x86)\WinAVR\bin;
C:\Program Files (x86)\WinAVR\utils\bin;
C:\Program Files\Common Files\Microsoft Shared\Windows Live;
C:\Program Files (x86)\SSH Communications Security\SSH Secure Shell;
C:\Program Files (x86)\UltraEdit;
c:\Xilinx\14.6\ISE_DS\ISE\bin\nt64C:\ispLever\ispcpld\bin;
C:\ispLever\ispFPGA\bin\nt;
C:\ispLever\active-hdl\BIN;
C:\Program Files\WinRAR;
C:\SynaptiCAD\bin;
C:\Program Files (x86)\Windows Kits\8.1\Windows Performance Toolkit\;
C:\Program Files\Microsoft SQL Server\110\Tools\Binn\;
C:\Program Files (x86)\Microsoft SDKs\TypeScript\1.0\;
C:\Program Files\Microsoft SQL Server\120\Tools\Binn\;
C:\WINDOWS\system32;
C:\WINDOWS;
C:\WINDOWS\System32\Wbem;
C:\WINDOWS\System32\WindowsPowerShell\v1.0\;
C:\Program Files (x86)\ATI Technologies\ATI.ACE\Core-Static;
%PATH;
C:\Program Files (x86)\IDM Computer Solutions\UltraEdit\;
C:\Program Files (x86)\UltraEdit\;
C:\Program Files\Java\jdk1.7.0_02\bin;
C:\Users\Matze\AppData\Local\Microsoft\WindowsApps		C:\Xilinx\14.6\ISE_DS\ISE\\lib\nt64;
C:\Xilinx\14.6\ISE_DS\ISE\\bin\nt64;
C:\Xilinx\14.6\ISE_DS\ISE\bin\nt64;
C:\Xilinx\14.6\ISE_DS\ISE\lib\nt64;
C:\Xilinx\14.6\ISE_DS\ISE\..\..\..\DocNav;
C:\Xilinx\14.6\ISE_DS\PlanAhead\bin;
C:\Xilinx\14.6\ISE_DS\EDK\bin\nt64;
C:\Xilinx\14.6\ISE_DS\EDK\lib\nt64;
C:\Xilinx\14.6\ISE_DS\EDK\gnu\microblaze\nt\bin;
C:\Xilinx\14.6\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;
C:\Xilinx\14.6\ISE_DS\EDK\gnuwin\bin;
C:\Xilinx\14.6\ISE_DS\EDK\gnu\arm\nt\bin;
C:\Xilinx\14.6\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;
C:\Xilinx\14.6\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;
C:\Xilinx\14.6\ISE_DS\common\bin\nt64;
C:\Xilinx\14.6\ISE_DS\common\lib\nt64;
E:\ispLEVER_Classic2_0\ispcpld\bin;
E:\ispLEVER_Classic2_0\ispFPGA\bin\nt;
E:\ispLEVER_Classic2_0\active-hdl\BIN;
C:\ProgramData\Oracle\Java\javapath;
C:\SynaptiCAD\bin\win32;
C:\Program Files\Java\jre7\bin;
C\Windows\System32;
C:\Program Files (x86)\WinAVR\bin;
C:\Program Files (x86)\WinAVR\utils\bin;
C:\Program Files\Common Files\Microsoft Shared\Windows Live;
C:\Program Files (x86)\SSH Communications Security\SSH Secure Shell;
C:\Program Files (x86)\UltraEdit;
c:\Xilinx\14.6\ISE_DS\ISE\bin\nt64C:\ispLever\ispcpld\bin;
C:\ispLever\ispFPGA\bin\nt;
C:\ispLever\active-hdl\BIN;
C:\Program Files\WinRAR;
C:\SynaptiCAD\bin;
C:\Program Files (x86)\Windows Kits\8.1\Windows Performance Toolkit\;
C:\Program Files\Microsoft SQL Server\110\Tools\Binn\;
C:\Program Files (x86)\Microsoft SDKs\TypeScript\1.0\;
C:\Program Files\Microsoft SQL Server\120\Tools\Binn\;
C:\WINDOWS\system32;
C:\WINDOWS;
C:\WINDOWS\System32\Wbem;
C:\WINDOWS\System32\WindowsPowerShell\v1.0\;
C:\Program Files (x86)\ATI Technologies\ATI.ACE\Core-Static;
%PATH;
C:\Program Files (x86)\IDM Computer Solutions\UltraEdit\;
C:\Program Files (x86)\UltraEdit\;
C:\Program Files\Java\jdk1.7.0_02\bin;
C:\Users\Matze\AppData\Local\Microsoft\WindowsApps
XILINXC:\Xilinx\14.6\ISE_DS\ISE\C:\Xilinx\14.6\ISE_DS\ISE\
XILINX_DSPC:\Xilinx\14.6\ISE_DS\ISEC:\Xilinx\14.6\ISE_DS\ISE
XILINX_EDKC:\Xilinx\14.6\ISE_DS\EDKC:\Xilinx\14.6\ISE_DS\EDK
XILINX_PLANAHEADC:\Xilinx\14.6\ISE_DS\PlanAheadC:\Xilinx\14.6\ISE_DS\PlanAhead
+ + 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Synthesis Property Settings
Switch NameProperty NameValueDefault Value
-ifn LAN_IDE_CP.prj 
-ifmt mixedMIXED
-ofn LAN_IDE_CP 
-ofmt NGCNGC
-p xc9500xl 
-top LAN_IDE_CP 
-opt_modeOptimization GoalSpeedSPEED
-opt_levelOptimization Effort11
-iucUse synthesis Constraints FileNONO
-keep_hierarchyKeep HierarchyYesYES
-netlist_hierarchyNetlist HierarchyAs_Optimizedas_optimized
-rtlviewGenerate RTL SchematicYesNO
-bus_delimiterBus Delimiter<><>
-verilog2001Verilog 2001YESYES
-fsm_extract YESYES
-fsm_encoding AutoAUTO
-safe_implementation NoNO
-resource_sharing YESYES
-iobuf YESYES
-equivalent_register_removal YESYES
+ + 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Translation Property Settings
Switch NameProperty NameValueDefault Value
-intstyle iseNone
-dd _ngoNone
-p xc95144xl-TQ144-10None
-uc pinlist.ucfNone
+ + 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Operating System Information
Operating System Informationxstngdbuild
CPU Architecture/SpeedAMD Phenom(tm) II X6 1090T Processor/3200 MHzAMD Phenom(tm) II X6 1090T Processor/3200 MHz
HostDeepThoughtDeepThought
OS NameMicrosoft , 64-bitMicrosoft , 64-bit
OS Releasemajor release (build 9200)major release (build 9200)
+ \ No newline at end of file diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/applet.js b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/applet.js new file mode 100644 index 0000000..d255dd2 --- /dev/null +++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/applet.js @@ -0,0 +1,128 @@ + var tmpStr = ""; + var waitWin; + + function openWait() { + waitWin = window.open("wait.htm", "wait", + "toolbar=no,location=no,"+ + "directories=no,status=no,menubar=no,scrollbars=no,"+ + "resizable=no,width=300,height=50" ); + } + + function closeWait() { if (waitWin) waitWin.close(); } + + function setMsg(msg){ + + parent.leftnav.setAppletMsg( msg ); + // now send it reload forces + // call to applet paint + location.reload(); + } + + function getMsg(){ + + return( parent.leftnav.getAppletMsg() ); + } + + function resetMsg(){ parent.leftnav.setAppletMsg(""); } + + function printAppletPkg() { + if( isNS() ){ + setMsg("cmd printPkg "); + } + else{ + document.ChipViewerApplet.PrintPkg(); + } + } + + function showAppletGraphicMC(mc) { + if( isNS() ){ + setMsg("cmd showMac " + mc); + } + else{ + document.ChipViewerApplet.ShowMac(mc); + } + } + + function ShowMC() { showAppletGraphicMC(tmpStr); } + + function showAppletGraphicFB(fb) { + if( isNS() ){ + setMsg("cmd showFB " + fb); + } + else{ + document.ChipViewerApplet.ShowFB(fb); + } + } + + function showAppletGraphicPin(pin) { + if( isNS() ){ + setMsg("cmd showPin " + pin); + } + else{ + document.ChipViewerApplet.ShowPin(pin); + } + } + + function ShowFB() { showAppletGraphicFB(tmpStr); } + + function isNS() { + return ((navigator.appName.indexOf("Netscape") >= 0) && (parseFloat(navigator.appVersion) < 5) ) ? true : false; + } + + function isIE(){ + var agt=navigator.userAgent.toLowerCase(); + return( ( (agt.indexOf("msie") != -1) && (agt.indexOf("opera") == -1) ) ? true: false ); + } + + function waitUntilOK() { + if (!waitWin) openWait(); + if (isNS()) { + if (document.ChipViewerApplet.isActive()) closeWait(); + else settimeout("waitUntilOK()",100); + } + else { + if (document.ChipViewerApplet.readyState == 4) closeWait(); + else settimeout("waitUntilOK()",100); + } + } + + + // check that the applet if file has been generated + // this can only be done if the applets been loaded. + function fileExists(fileName){ + + if( document.ChipViewerApplet.readyState != 4 ) { + window.alert("Navigation disabled until the applet is loaded." ); + } + if( isIE() ){ + if( parent.leftnav.getAppletPermission() == 1 ){ + if( document.ChipViewerApplet.TestFileExists(fileName) == 1 ){ + window.alert("file exist tests true" ); + return( true ); + } + } + else{ + window.alert("file exist returns true no permission" ); + return( true ); + } + } + else{ + return( true ); + } + window.alert("file exist returns false" ); + return( false ); + } + + + + function setPermission(){ + + if( isIE() ){ + if( document.ChipViewerApplet.granted() ){ + parent.leftnav.setAppletPermission(); + } + } + else{ + return( true ); + } + } diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/appletref.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/appletref.htm new file mode 100644 index 0000000..2182301 --- /dev/null +++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/appletref.htm @@ -0,0 +1,14 @@ + + + + + + + + + + + + + + diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/ascii.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/ascii.htm new file mode 100644 index 0000000..811ab7e --- /dev/null +++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/ascii.htm @@ -0,0 +1,1175 @@ + +
+ 
+cpldfit:  version P.68d                             Xilinx Inc.
+                                  Fitter Report
+Design Name: LAN_IDE_CP                          Date: 12-15-2016,  7:48PM
+Device Used: XC95144XL-10-TQ144
+Fitting Status: Successful
+
+*************************  Mapped Resource Summary  **************************
+
+Macrocells     Product Terms    Function Block   Registers      Pins           
+Used/Tot       Used/Tot         Inps Used/Tot    Used/Tot       Used/Tot       
+51 /144 ( 35%) 179 /720  ( 25%) 134/432 ( 31%)   26 /144 ( 18%) 54 /117 ( 46%)
+
+** Function Block Resources **
+
+Function    Mcells      FB Inps     Pterms      IO          
+Block       Used/Tot    Used/Tot    Used/Tot    Used/Tot    
+FB1          16/18       24/54       40/90      13/15
+FB2          11/18       24/54       56/90       4/15
+FB3          12/18       24/54       25/90      11/15
+FB4           3/18       24/54       25/90       0/15
+FB5           7/18       23/54       19/90      10/14
+FB6           1/18       15/54       14/90       0/13
+FB7           1/18        0/54        0/90       8/15
+FB8           0/18        0/54        0/90       8/15
+             -----       -----       -----      -----    
+             51/144     134/432     179/720     54/117
+
+* - Resource is exhausted
+
+** Global Control Resources **
+
+Global clock net(s) unused.
+Global output enable net(s) unused.
+Signal 'RESET' mapped onto global set/reset net GSR.
+
+** Pin Resources **
+
+Signal Type    Required     Mapped  |  Pin Type            Used    Total 
+------------------------------------|------------------------------------
+Input         :   26          26    |  I/O              :    52     109
+Output        :   19          19    |  GCK/IO           :     0       3
+Bidirectional :    8           8    |  GTS/IO           :     1       4
+GCK           :    0           0    |  GSR/IO           :     1       1
+GTS           :    0           0    |
+GSR           :    1           1    |
+                 ----        ----
+        Total     54          54
+
+** Power Data **
+
+There are 51 macrocells in high performance mode (MCHP).
+There are 0 macrocells in low power mode (MCLP).
+End of Mapped Resource Summary
+**************************  Errors and Warnings  ***************************
+
+WARNING:Cpld - Unable to retrieve the path to the iSE Project Repository. Will
+   use the default filename of 'LAN_IDE_CP.ise'.
+INFO:Cpld - Inferring BUFG constraint for signal 'CLK_EXT' based upon the LOC
+   constraint 'P30'. It is recommended that you declare this BUFG explicitedly
+   in your design. Note that for certain device families the output of a BUFG
+   constraint can not drive a gated clock, and the BUFG constraint will be
+   ignored.
+WARNING:Cpld:936 - The output buffer 'SLAVE_OBUF' is missing an input and will
+   be deleted.
+WARNING:Cpld:936 - The output buffer 'OWN_OBUF' is missing an input and will be
+   deleted.
+WARNING:Cpld:936 - The output buffer 'OVR_OBUF' is missing an input and will be
+   deleted.
+WARNING:Cpld:936 - The output buffer 'MTACK_OBUF' is missing an input and will
+   be deleted.
+WARNING:Cpld:936 - The output buffer 'LAN_WRH_OBUF' is missing an input and will
+   be deleted.
+WARNING:Cpld:936 - The output buffer 'LAN_RD_OBUF' is missing an input and will
+   be deleted.
+WARNING:Cpld:936 - The output buffer 'LAN_EN_OBUF' is missing an input and will
+   be deleted.
+WARNING:Cpld:936 - The output buffer 'LAN_CS_OBUF' is missing an input and will
+   be deleted.
+WARNING:Cpld:936 - The output buffer 'LAN_CFG<4>_OBUF' is missing an input and
+   will be deleted.
+WARNING:Cpld:936 - The output buffer 'LAN_CFG<3>_OBUF' is missing an input and
+   will be deleted.
+WARNING:Cpld:936 - The output buffer 'LAN_CFG<2>_OBUF' is missing an input and
+   will be deleted.
+WARNING:Cpld:936 - The output buffer 'LAN_CFG<1>_OBUF' is missing an input and
+   will be deleted.
+WARNING:Cpld:936 - The output buffer 'INT_OUT_OBUF' is missing an input and will
+   be deleted.
+WARNING:Cpld:936 - The output buffer 'CP_WE_OBUF' is missing an input and will
+   be deleted.
+WARNING:Cpld:936 - The output buffer 'CP_RD_OBUF' is missing an input and will
+   be deleted.
+WARNING:Cpld:936 - The output buffer 'CP_CS_OBUF' is missing an input and will
+   be deleted.
+WARNING:Cpld:936 - The output buffer 'CFOUT_OBUF' is missing an input and will
+   be deleted.
+WARNING:Cpld:936 - The output buffer 'A_LAN<9>_OBUF' is missing an input and
+   will be deleted.
+WARNING:Cpld:936 - The output buffer 'A_LAN<8>_OBUF' is missing an input and
+   will be deleted.
+WARNING:Cpld:936 - The output buffer 'A_LAN<7>_OBUF' is missing an input and
+   will be deleted.
+WARNING:Cpld:936 - The output buffer 'A_LAN<6>_OBUF' is missing an input and
+   will be deleted.
+WARNING:Cpld:936 - The output buffer 'A_LAN<5>_OBUF' is missing an input and
+   will be deleted.
+WARNING:Cpld:936 - The output buffer 'A_LAN<4>_OBUF' is missing an input and
+   will be deleted.
+WARNING:Cpld:936 - The output buffer 'A_LAN<3>_OBUF' is missing an input and
+   will be deleted.
+WARNING:Cpld:936 - The output buffer 'A_LAN<2>_OBUF' is missing an input and
+   will be deleted.
+WARNING:Cpld:936 - The output buffer 'A_LAN<1>_OBUF' is missing an input and
+   will be deleted.
+WARNING:Cpld:936 - The output buffer 'A_LAN<13>_OBUF' is missing an input and
+   will be deleted.
+WARNING:Cpld:936 - The output buffer 'A_LAN<12>_OBUF' is missing an input and
+   will be deleted.
+WARNING:Cpld:936 - The output buffer 'A_LAN<11>_OBUF' is missing an input and
+   will be deleted.
+WARNING:Cpld:936 - The output buffer 'A_LAN<10>_OBUF' is missing an input and
+   will be deleted.
+WARNING:Cpld:936 - The output buffer 'A_LAN<0>_OBUF' is missing an input and
+   will be deleted.
+WARNING:Cpld:1007 - Removing unused input(s) 'A<14>'.  The input(s) are unused
+   after optimization. Please verify functionality via simulation.
+WARNING:Cpld:1007 - Removing unused input(s) 'A<15>'.  The input(s) are unused
+   after optimization. Please verify functionality via simulation.
+WARNING:Cpld:1007 - Removing unused input(s) 'A<7>'.  The input(s) are unused
+   after optimization. Please verify functionality via simulation.
+WARNING:Cpld:1007 - Removing unused input(s) 'A<8>'.  The input(s) are unused
+   after optimization. Please verify functionality via simulation.
+WARNING:Cpld:1007 - Removing unused input(s) 'CFIN'.  The input(s) are unused
+   after optimization. Please verify functionality via simulation.
+WARNING:Cpld:1007 - Removing unused input(s) 'CLK_EXT'.  The input(s) are unused
+   after optimization. Please verify functionality via simulation.
+WARNING:Cpld:1007 - Removing unused input(s) 'CP_IRQ'.  The input(s) are unused
+   after optimization. Please verify functionality via simulation.
+WARNING:Cpld:1007 - Removing unused input(s) 'DQ<0>'.  The input(s) are unused
+   after optimization. Please verify functionality via simulation.
+WARNING:Cpld:1007 - Removing unused input(s) 'DQ<10>'.  The input(s) are unused
+   after optimization. Please verify functionality via simulation.
+WARNING:Cpld:1007 - Removing unused input(s) 'DQ<11>'.  The input(s) are unused
+   after optimization. Please verify functionality via simulation.
+WARNING:Cpld:1007 - Removing unused input(s) 'DQ<12>'.  The input(s) are unused
+   after optimization. Please verify functionality via simulation.
+WARNING:Cpld:1007 - Removing unused input(s) 'DQ<13>'.  The input(s) are unused
+   after optimization. Please verify functionality via simulation.
+WARNING:Cpld:1007 - Removing unused input(s) 'DQ<14>'.  The input(s) are unused
+   after optimization. Please verify functionality via simulation.
+WARNING:Cpld:1007 - Removing unused input(s) 'DQ<15>'.  The input(s) are unused
+   after optimization. Please verify functionality via simulation.
+WARNING:Cpld:1007 - Removing unused input(s) 'DQ<1>'.  The input(s) are unused
+   after optimization. Please verify functionality via simulation.
+WARNING:Cpld:1007 - Removing unused input(s) 'DQ<2>'.  The input(s) are unused
+   after optimization. Please verify functionality via simulation.
+WARNING:Cpld:1007 - Removing unused input(s) 'DQ<3>'.  The input(s) are unused
+   after optimization. Please verify functionality via simulation.
+WARNING:Cpld:1007 - Removing unused input(s) 'DQ<4>'.  The input(s) are unused
+   after optimization. Please verify functionality via simulation.
+WARNING:Cpld:1007 - Removing unused input(s) 'DQ<5>'.  The input(s) are unused
+   after optimization. Please verify functionality via simulation.
+WARNING:Cpld:1007 - Removing unused input(s) 'DQ<6>'.  The input(s) are unused
+   after optimization. Please verify functionality via simulation.
+WARNING:Cpld:1007 - Removing unused input(s) 'DQ<7>'.  The input(s) are unused
+   after optimization. Please verify functionality via simulation.
+WARNING:Cpld:1007 - Removing unused input(s) 'DQ<8>'.  The input(s) are unused
+   after optimization. Please verify functionality via simulation.
+WARNING:Cpld:1007 - Removing unused input(s) 'DQ<9>'.  The input(s) are unused
+   after optimization. Please verify functionality via simulation.
+WARNING:Cpld:1007 - Removing unused input(s) 'DS0'.  The input(s) are unused
+   after optimization. Please verify functionality via simulation.
+WARNING:Cpld:1007 - Removing unused input(s) 'DS1'.  The input(s) are unused
+   after optimization. Please verify functionality via simulation.
+WARNING:Cpld:1007 - Removing unused input(s) 'FCS'.  The input(s) are unused
+   after optimization. Please verify functionality via simulation.
+WARNING:Cpld:1007 - Removing unused input(s) 'IDE_WAIT'.  The input(s) are
+   unused after optimization. Please verify functionality via simulation.
+WARNING:Cpld:1007 - Removing unused input(s) 'LAN_INT'.  The input(s) are unused
+   after optimization. Please verify functionality via simulation.
+WARNING:Cpld:1007 - Removing unused input(s) 'LDS'.  The input(s) are unused
+   after optimization. Please verify functionality via simulation.
+WARNING:Cpld:1007 - Removing unused input(s) 'MTCR'.  The input(s) are unused
+   after optimization. Please verify functionality via simulation.
+WARNING:Cpld:1007 - Removing unused input(s) 'Z3'.  The input(s) are unused
+   after optimization. Please verify functionality via simulation.
+WARNING:Cpld:896 - Unable to map all desired signals into function block, FB3,
+   because too many function block product terms are required. Buffering output
+   signal D<12> to allow all signals assigned to this function block to be
+   placed.
+WARNING:Cpld:896 - Unable to map all desired signals into function block, FB3,
+   because too many function block product terms are required. Buffering output
+   signal D<14> to allow all signals assigned to this function block to be
+   placed.
+WARNING:Cpld:896 - Unable to map all desired signals into function block, FB3,
+   because too many function block product terms are required. Buffering output
+   signal D<13> to allow all signals assigned to this function block to be
+   placed.
+WARNING:Cpld:896 - Unable to map all desired signals into function block, FB3,
+   because too many function block product terms are required. Buffering output
+   signal D<15> to allow all signals assigned to this function block to be
+   placed.
+*************************  Summary of Mapped Logic  ************************
+
+** 27 Outputs **
+
+Signal                     Total Total Loc     Pin  Pin     Pin     Pwr  Slew Reg Init
+Name                       Pts   Inps          No.  Type    Use     Mode Rate State
+IDE_CS<1>                  1     1     FB1_1   23   I/O     O       STD  FAST 
+D<7>                       1     2     FB1_2   16   I/O     O       STD  FAST 
+D<1>                       1     2     FB1_3   17   I/O     O       STD  FAST 
+IDE_A<2>                   1     1     FB1_4   25   I/O     O       STD  FAST 
+D<8>                       1     2     FB1_5   19   I/O     I/O     STD  FAST 
+D<5>                       1     2     FB1_6   20   I/O     O       STD  FAST 
+D<4>                       1     2     FB1_8   21   I/O     O       STD  FAST 
+IDE_CS<0>                  1     1     FB1_9   22   I/O     O       STD  FAST 
+IDE_A<0>                   1     1     FB1_11  24   I/O     O       STD  FAST 
+IDE_A<1>                   1     1     FB1_12  26   I/O     O       STD  FAST 
+IDE_R                      2     6     FB1_14  27   I/O     O       STD  FAST SET
+IDE_W                      2     5     FB1_15  28   I/O     O       STD  FAST SET
+ROM_OE                     2     6     FB1_16  35   I/O     O       STD  FAST SET
+D<0>                       1     2     FB2_5   2    GTS/I/O O       STD  FAST 
+D<6>                       1     2     FB2_16  14   I/O     O       STD  FAST 
+D<3>                       1     2     FB2_17  15   I/O     O       STD  FAST 
+D<2>                       1     2     FB3_1   39   I/O     O       STD  FAST 
+D<10>                      1     2     FB3_3   41   I/O     I/O     STD  FAST 
+D<12>                      2     3     FB3_4   44   I/O     I/O     STD  FAST 
+D<14>                      2     3     FB3_7   46   I/O     I/O     STD  FAST 
+D<9>                       1     2     FB3_9   40   I/O     I/O     STD  FAST 
+D<15>                      2     3     FB3_10  48   I/O     I/O     STD  FAST 
+D<11>                      1     2     FB3_11  43   I/O     I/O     STD  FAST 
+D<13>                      2     3     FB3_12  45   I/O     I/O     STD  FAST 
+ROM_B<0>                   0     0     FB5_10  68   I/O     O       STD  FAST 
+ROM_B<1>                   0     0     FB5_17  69   I/O     O       STD  FAST 
+DTACK                      0     0     FB7_12  85   I/O     O       STD  FAST 
+
+** 24 Buried Nodes **
+
+Signal                     Total Total Loc     Pwr  Reg Init
+Name                       Pts   Inps          Mode State
+AUTOCONFIG_IN_PROGRESS     2     3     FB1_7   STD  RESET
+IDE_ENABLE                 3     6     FB1_10  STD  RESET
+D<12>_BUFR                 19    16    FB1_18  STD  RESET
+D<14>_BUFR                 18    15    FB2_1   STD  RESET
+AUTO_CONFIG_DONE<2>        2     2     FB2_8   STD  RESET
+AUTO_CONFIG_DONE<0>        2     2     FB2_9   STD  RESET
+AUTO_CONFIG_DONE_CYCLE<2>  3     15    FB2_10  STD  RESET
+AUTO_CONFIG_DONE_CYCLE<0>  3     13    FB2_11  STD  RESET
+IDE_BASEADR<7>             4     16    FB2_12  STD  RESET
+IDE_BASEADR<6>             4     16    FB2_13  STD  RESET
+D<13>_BUFR                 17    15    FB2_15  STD  RESET
+AUTO_CONFIG_DONE<1>        2     2     FB3_15  STD  RESET
+AUTO_CONFIG_DONE_CYCLE<1>  3     14    FB3_16  STD  RESET
+IDE_BASEADR<3>             4     16    FB3_17  STD  RESET
+IDE_BASEADR<2>             4     16    FB3_18  STD  RESET
+ide                        19    19    FB4_1   STD  RESET
+ide/ide_CLKF               2     2     FB4_16  STD  
+autoconfig                 4     13    FB4_17  STD  RESET
+SHUT_UP<1>                 3     15    FB5_13  STD  RESET
+IDE_BASEADR<5>             4     16    FB5_14  STD  RESET
+IDE_BASEADR<4>             4     16    FB5_15  STD  RESET
+IDE_BASEADR<1>             4     16    FB5_16  STD  RESET
+IDE_BASEADR<0>             4     16    FB5_18  STD  RESET
+D<15>_BUFR                 14    15    FB6_17  STD  RESET
+
+** 27 Inputs **
+
+Signal                     Loc     Pin  Pin     Pin     
+Name                               No.  Type    Use     
+RESET                      FB2_2   143  GSR/I/O GSR/I
+A<5>                       FB3_14  49   I/O     I
+A<4>                       FB3_15  50   I/O     I
+A<6>                       FB3_17  51   I/O     I
+A<3>                       FB5_2   52   I/O     I
+A<10>                      FB5_3   59   I/O     I
+A<2>                       FB5_6   54   I/O     I
+A<1>                       FB5_9   57   I/O     I
+A<9>                       FB5_11  58   I/O     I
+A<11>                      FB5_12  60   I/O     I
+A<12>                      FB5_14  61   I/O     I
+A<13>                      FB5_15  64   I/O     I
+AUTOBOOT_OFF               FB7_3   75   I/O     I
+AS                         FB7_9   80   I/O     I
+UDS                        FB7_13  81   I/O     I
+A<23>                      FB7_14  86   I/O     I
+A<22>                      FB7_15  87   I/O     I
+RW                         FB7_16  83   I/O     I
+A<21>                      FB7_17  88   I/O     I
+A<20>                      FB8_2   91   I/O     I
+A<17>                      FB8_3   95   I/O     I
+A<16>                      FB8_4   97   I/O     I
+A<19>                      FB8_5   92   I/O     I
+A<18>                      FB8_8   94   I/O     I
+BERR                       FB8_11  98   I/O     I
+C1                         FB8_13  103  I/O     I
+C3                         FB8_14  102  I/O     I
+
+Legend:
+Pin No. - ~ - User Assigned
+**************************  Function Block Details  ************************
+Legend:
+Total Pt     - Total product terms used by the macrocell signal
+Imp Pt       - Product terms imported from other macrocells
+Exp Pt       - Product terms exported to other macrocells
+               in direction shown
+Unused Pt    - Unused local product terms remaining in macrocell
+Loc          - Location where logic was mapped in device
+Pin Type/Use - I  - Input             GCK - Global Clock
+               O  - Output            GTS - Global Output Enable
+              (b) - Buried macrocell  GSR - Global Set/Reset
+X            - Signal used as input to the macrocell logic.
+Pin No.      - ~  - User Assigned
+*********************************** FB1  ***********************************
+Number of function block inputs used/remaining:               24/30
+Number of signals used by logic mapping into function block:  24
+Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
+Name                Pt      Pt    Pt  Pt               #    Type    Use
+IDE_CS<1>             1       1<- /\5   0     FB1_1   23    I/O     O
+D<7>                  1       0   /\1   3     FB1_2   16    I/O     O
+D<1>                  1       0     0   4     FB1_3   17    I/O     O
+IDE_A<2>              1       0     0   4     FB1_4   25    I/O     O
+D<8>                  1       0     0   4     FB1_5   19    I/O     I/O
+D<5>                  1       0     0   4     FB1_6   20    I/O     O
+AUTOCONFIG_IN_PROGRESS
+                      2       0     0   3     FB1_7         (b)     (b)
+D<4>                  1       0     0   4     FB1_8   21    I/O     O
+IDE_CS<0>             1       0     0   4     FB1_9   22    I/O     O
+IDE_ENABLE            3       0     0   2     FB1_10  31    I/O     (b)
+IDE_A<0>              1       0     0   4     FB1_11  24    I/O     O
+IDE_A<1>              1       0     0   4     FB1_12  26    I/O     O
+(unused)              0       0     0   5     FB1_13        (b)     
+IDE_R                 2       0     0   3     FB1_14  27    I/O     O
+IDE_W                 2       0   \/1   2     FB1_15  28    I/O     O
+ROM_OE                2       1<- \/4   0     FB1_16  35    I/O     O
+(unused)              0       0   \/5   0     FB1_17  30    GCK/I/O (b)
+D<12>_BUFR           19      14<-   0   0     FB1_18        (b)     (b)
+
+Signals Used by Logic in Function Block
+  1: AS                       9: A<1>              17: A<10> 
+  2: AUTOBOOT_OFF            10: A<2>              18: A<11> 
+  3: AUTOCONFIG_IN_PROGRESS  11: A<3>              19: IDE_ENABLE 
+  4: AUTO_CONFIG_DONE<0>     12: A<4>              20: RESET 
+  5: AUTO_CONFIG_DONE<1>     13: A<5>              21: RW 
+  6: AUTO_CONFIG_DONE<2>     14: A<6>              22: autoconfig 
+  7: A<12>                   15: D<12>             23: ide 
+  8: A<13>                   16: A<9>              24: ide/ide_CLKF 
+
+Signal                        1         2         3         4 FB
+Name                0----+----0----+----0----+----0----+----0 Inputs
+IDE_CS<1>            .......X................................ 1
+D<7>                 ..X.................X................... 2
+D<1>                 ..X.................X................... 2
+IDE_A<2>             .................X...................... 1
+D<8>                 ..X.................X................... 2
+D<5>                 ..X.................X................... 2
+AUTOCONFIG_IN_PROGRESS 
+                     X....................X.X................ 3
+D<4>                 ..X.................X................... 2
+IDE_CS<0>            ......X................................. 1
+IDE_ENABLE           X.................XXX.XX................ 6
+IDE_A<0>             ...............X........................ 1
+IDE_A<1>             ................X....................... 1
+IDE_R                X.................XXX.XX................ 6
+IDE_W                X..................XX.XX................ 5
+ROM_OE               X.................XXX.XX................ 6
+D<12>_BUFR           XX.XXX..XXXXXXX....XXX.X................ 16
+                    0----+----1----+----2----+----3----+----4
+                              0         0         0         0
+*********************************** FB2  ***********************************
+Number of function block inputs used/remaining:               24/30
+Number of signals used by logic mapping into function block:  24
+Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
+Name                Pt      Pt    Pt  Pt               #    Type    Use
+D<14>_BUFR           18      13<-   0   0     FB2_1   142   I/O     (b)
+(unused)              0       0   /\5   0     FB2_2   143   GSR/I/O GSR/I
+(unused)              0       0   /\3   2     FB2_3         (b)     (b)
+(unused)              0       0     0   5     FB2_4   4     I/O     
+D<0>                  1       0     0   4     FB2_5   2     GTS/I/O O
+(unused)              0       0     0   5     FB2_6   3     GTS/I/O 
+(unused)              0       0     0   5     FB2_7         (b)     
+AUTO_CONFIG_DONE<2>   2       0     0   3     FB2_8   5     GTS/I/O (b)
+AUTO_CONFIG_DONE<0>   2       0     0   3     FB2_9   6     GTS/I/O (b)
+AUTO_CONFIG_DONE_CYCLE<2>
+                      3       0     0   2     FB2_10  7     I/O     (b)
+AUTO_CONFIG_DONE_CYCLE<0>
+                      3       0   \/1   1     FB2_11  9     I/O     (b)
+IDE_BASEADR<7>        4       1<- \/2   0     FB2_12  10    I/O     (b)
+IDE_BASEADR<6>        4       2<- \/3   0     FB2_13  12    I/O     (b)
+(unused)              0       0   \/5   0     FB2_14  11    I/O     (b)
+D<13>_BUFR           17      12<-   0   0     FB2_15  13    I/O     (b)
+D<6>                  1       0   /\4   0     FB2_16  14    I/O     O
+D<3>                  1       0     0   4     FB2_17  15    I/O     O
+(unused)              0       0   \/5   0     FB2_18        (b)     (b)
+
+Signals Used by Logic in Function Block
+  1: AS                          9: A<2>              17: IDE_BASEADR<7> 
+  2: AUTOCONFIG_IN_PROGRESS     10: A<3>              18: D<14>.PIN 
+  3: AUTO_CONFIG_DONE<0>        11: A<4>              19: D<15>.PIN 
+  4: AUTO_CONFIG_DONE<1>        12: A<5>              20: RESET 
+  5: AUTO_CONFIG_DONE<2>        13: A<6>              21: RW 
+  6: AUTO_CONFIG_DONE_CYCLE<0>  14: D<13>             22: UDS 
+  7: AUTO_CONFIG_DONE_CYCLE<2>  15: D<14>             23: autoconfig 
+  8: A<1>                       16: IDE_BASEADR<6>    24: ide/ide_CLKF 
+
+Signal                        1         2         3         4 FB
+Name                0----+----0----+----0----+----0----+----0 Inputs
+D<14>_BUFR           X.XXX..XXXXXX.X....XX.XX................ 15
+D<0>                 .X..................X................... 2
+AUTO_CONFIG_DONE<2>  X.....X................................. 2
+AUTO_CONFIG_DONE<0>  X....X.................................. 2
+AUTO_CONFIG_DONE_CYCLE<2> 
+                     X.XXX.XX.XXXX......XXXXX................ 15
+AUTO_CONFIG_DONE_CYCLE<0> 
+                     X.X..X.X.XXXX......XXXXX................ 13
+IDE_BASEADR<7>       X.XX...XXXXXX...X.XXXXXX................ 16
+IDE_BASEADR<6>       X.XX...XXXXXX..X.X.XXXXX................ 16
+D<13>_BUFR           X.XXX..XXXXXXX.....XX.XX................ 15
+D<6>                 .X..................X................... 2
+D<3>                 .X..................X................... 2
+                    0----+----1----+----2----+----3----+----4
+                              0         0         0         0
+*********************************** FB3  ***********************************
+Number of function block inputs used/remaining:               24/30
+Number of signals used by logic mapping into function block:  24
+Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
+Name                Pt      Pt    Pt  Pt               #    Type    Use
+D<2>                  1       0     0   4     FB3_1   39    I/O     O
+(unused)              0       0     0   5     FB3_2   32    GCK/I/O 
+D<10>                 1       0     0   4     FB3_3   41    I/O     I/O
+D<12>                 2       0     0   3     FB3_4   44    I/O     I/O
+(unused)              0       0     0   5     FB3_5   33    I/O     
+(unused)              0       0     0   5     FB3_6   34    I/O     
+D<14>                 2       0     0   3     FB3_7   46    I/O     I/O
+(unused)              0       0     0   5     FB3_8   38    GCK/I/O 
+D<9>                  1       0     0   4     FB3_9   40    I/O     I/O
+D<15>                 2       0     0   3     FB3_10  48    I/O     I/O
+D<11>                 1       0     0   4     FB3_11  43    I/O     I/O
+D<13>                 2       0     0   3     FB3_12  45    I/O     I/O
+(unused)              0       0     0   5     FB3_13        (b)     
+(unused)              0       0     0   5     FB3_14  49    I/O     I
+AUTO_CONFIG_DONE<1>   2       0     0   3     FB3_15  50    I/O     I
+AUTO_CONFIG_DONE_CYCLE<1>
+                      3       0     0   2     FB3_16        (b)     (b)
+IDE_BASEADR<3>        4       0     0   1     FB3_17  51    I/O     I
+IDE_BASEADR<2>        4       0     0   1     FB3_18        (b)     (b)
+
+Signals Used by Logic in Function Block
+  1: AS                          9: A<4>              17: IDE_BASEADR<3> 
+  2: AUTOCONFIG_IN_PROGRESS     10: A<5>              18: D<11>.PIN 
+  3: AUTO_CONFIG_DONE<0>        11: A<6>              19: D<10>.PIN 
+  4: AUTO_CONFIG_DONE<1>        12: D<12>_BUFR        20: RESET 
+  5: AUTO_CONFIG_DONE_CYCLE<1>  13: D<13>_BUFR        21: RW 
+  6: A<1>                       14: D<14>_BUFR        22: UDS 
+  7: A<2>                       15: D<15>_BUFR        23: autoconfig 
+  8: A<3>                       16: IDE_BASEADR<2>    24: ide/ide_CLKF 
+
+Signal                        1         2         3         4 FB
+Name                0----+----0----+----0----+----0----+----0 Inputs
+D<2>                 .X..................X................... 2
+D<10>                .X..................X................... 2
+D<12>                .X.........X........X................... 3
+D<14>                .X...........X......X................... 3
+D<9>                 .X..................X................... 2
+D<15>                .X............X.....X................... 3
+D<11>                .X..................X................... 2
+D<13>                .X..........X.......X................... 3
+AUTO_CONFIG_DONE<1>  X...X................................... 2
+AUTO_CONFIG_DONE_CYCLE<1> 
+                     X.XXXX.XXXX........XXXXX................ 14
+IDE_BASEADR<3>       X.XX.XXXXXX.....XX.XXXXX................ 16
+IDE_BASEADR<2>       X.XX.XXXXXX....X..XXXXXX................ 16
+                    0----+----1----+----2----+----3----+----4
+                              0         0         0         0
+*********************************** FB4  ***********************************
+Number of function block inputs used/remaining:               24/30
+Number of signals used by logic mapping into function block:  24
+Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
+Name                Pt      Pt    Pt  Pt               #    Type    Use
+ide                  19      14<-   0   0     FB4_1   118   I/O     (b)
+(unused)              0       0   /\5   0     FB4_2   126   I/O     (b)
+(unused)              0       0   /\3   2     FB4_3   133   I/O     (b)
+(unused)              0       0     0   5     FB4_4         (b)     
+(unused)              0       0     0   5     FB4_5   128   I/O     
+(unused)              0       0     0   5     FB4_6   129   I/O     
+(unused)              0       0     0   5     FB4_7         (b)     
+(unused)              0       0     0   5     FB4_8   130   I/O     
+(unused)              0       0     0   5     FB4_9   131   I/O     
+(unused)              0       0     0   5     FB4_10  135   I/O     
+(unused)              0       0     0   5     FB4_11  132   I/O     
+(unused)              0       0     0   5     FB4_12  134   I/O     
+(unused)              0       0     0   5     FB4_13  137   I/O     
+(unused)              0       0     0   5     FB4_14  136   I/O     
+(unused)              0       0     0   5     FB4_15  138   I/O     
+ide/ide_CLKF          2       0     0   3     FB4_16  139   I/O     (b)
+autoconfig            4       0   \/1   0     FB4_17  140   I/O     (b)
+(unused)              0       0   \/5   0     FB4_18        (b)     (b)
+
+Signals Used by Logic in Function Block
+  1: AUTO_CONFIG_DONE<0>   9: A<21>             17: IDE_BASEADR<2> 
+  2: AUTO_CONFIG_DONE<1>  10: A<22>             18: IDE_BASEADR<3> 
+  3: AUTO_CONFIG_DONE<2>  11: A<23>             19: IDE_BASEADR<4> 
+  4: A<16>                12: BERR              20: IDE_BASEADR<5> 
+  5: A<17>                13: C1                21: IDE_BASEADR<6> 
+  6: A<18>                14: C3                22: IDE_BASEADR<7> 
+  7: A<19>                15: IDE_BASEADR<0>    23: SHUT_UP<1> 
+  8: A<20>                16: IDE_BASEADR<1>    24: ide/ide_CLKF 
+
+Signal                        1         2         3         4 FB
+Name                0----+----0----+----0----+----0----+----0 Inputs
+ide                  ...XXXXXXXXX..XXXXXXXXXX................ 19
+ide/ide_CLKF         ............XX.......................... 2
+autoconfig           XXXXXXXXXXXX...........X................ 13
+                    0----+----1----+----2----+----3----+----4
+                              0         0         0         0
+*********************************** FB5  ***********************************
+Number of function block inputs used/remaining:               23/31
+Number of signals used by logic mapping into function block:  23
+Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
+Name                Pt      Pt    Pt  Pt               #    Type    Use
+(unused)              0       0     0   5     FB5_1         (b)     
+(unused)              0       0     0   5     FB5_2   52    I/O     I
+(unused)              0       0     0   5     FB5_3   59    I/O     I
+(unused)              0       0     0   5     FB5_4         (b)     
+(unused)              0       0     0   5     FB5_5   53    I/O     
+(unused)              0       0     0   5     FB5_6   54    I/O     I
+(unused)              0       0     0   5     FB5_7   66    I/O     
+(unused)              0       0     0   5     FB5_8   56    I/O     
+(unused)              0       0     0   5     FB5_9   57    I/O     I
+ROM_B<0>              0       0     0   5     FB5_10  68    I/O     O
+(unused)              0       0     0   5     FB5_11  58    I/O     I
+(unused)              0       0     0   5     FB5_12  60    I/O     I
+SHUT_UP<1>            3       0     0   2     FB5_13  70    I/O     (b)
+IDE_BASEADR<5>        4       0     0   1     FB5_14  61    I/O     I
+IDE_BASEADR<4>        4       0     0   1     FB5_15  64    I/O     I
+IDE_BASEADR<1>        4       0     0   1     FB5_16        (b)     (b)
+ROM_B<1>              0       0     0   5     FB5_17  69    I/O     O
+IDE_BASEADR<0>        4       0     0   1     FB5_18        (b)     (b)
+
+Signals Used by Logic in Function Block
+  1: AS                    9: A<6>              17: D<9>.PIN 
+  2: AUTO_CONFIG_DONE<0>  10: IDE_BASEADR<0>    18: RESET 
+  3: AUTO_CONFIG_DONE<1>  11: IDE_BASEADR<1>    19: RW 
+  4: A<1>                 12: IDE_BASEADR<4>    20: SHUT_UP<1> 
+  5: A<2>                 13: IDE_BASEADR<5>    21: UDS 
+  6: A<3>                 14: D<12>.PIN         22: autoconfig 
+  7: A<4>                 15: D<13>.PIN         23: ide/ide_CLKF 
+  8: A<5>                 16: D<8>.PIN         
+
+Signal                        1         2         3         4 FB
+Name                0----+----0----+----0----+----0----+----0 Inputs
+ROM_B<0>             ........................................ 0
+SHUT_UP<1>           XXXXXXXXX........XXXXXX................. 15
+IDE_BASEADR<5>       XXXXXXXXX...X.X..XX.XXX................. 16
+IDE_BASEADR<4>       XXXXXXXXX..X.X...XX.XXX................. 16
+IDE_BASEADR<1>       XXXXXXXXX.X.....XXX.XXX................. 16
+ROM_B<1>             ........................................ 0
+IDE_BASEADR<0>       XXXXXXXXXX.....X.XX.XXX................. 16
+                    0----+----1----+----2----+----3----+----4
+                              0         0         0         0
+*********************************** FB6  ***********************************
+Number of function block inputs used/remaining:               15/39
+Number of signals used by logic mapping into function block:  15
+Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
+Name                Pt      Pt    Pt  Pt               #    Type    Use
+(unused)              0       0     0   5     FB6_1         (b)     
+(unused)              0       0     0   5     FB6_2   106   I/O     
+(unused)              0       0     0   5     FB6_3         (b)     
+(unused)              0       0     0   5     FB6_4   111   I/O     
+(unused)              0       0     0   5     FB6_5   110   I/O     
+(unused)              0       0     0   5     FB6_6   112   I/O     
+(unused)              0       0     0   5     FB6_7         (b)     
+(unused)              0       0     0   5     FB6_8   113   I/O     
+(unused)              0       0     0   5     FB6_9   116   I/O     
+(unused)              0       0     0   5     FB6_10  115   I/O     
+(unused)              0       0     0   5     FB6_11  119   I/O     
+(unused)              0       0     0   5     FB6_12  120   I/O     
+(unused)              0       0     0   5     FB6_13        (b)     
+(unused)              0       0     0   5     FB6_14  121   I/O     
+(unused)              0       0     0   5     FB6_15  124   I/O     
+(unused)              0       0   \/4   1     FB6_16  117   I/O     (b)
+D<15>_BUFR           14       9<-   0   0     FB6_17  125   I/O     (b)
+(unused)              0       0   /\5   0     FB6_18        (b)     (b)
+
+Signals Used by Logic in Function Block
+  1: AS                    6: A<2>              11: D<15> 
+  2: AUTO_CONFIG_DONE<0>   7: A<3>              12: RESET 
+  3: AUTO_CONFIG_DONE<1>   8: A<4>              13: RW 
+  4: AUTO_CONFIG_DONE<2>   9: A<5>              14: autoconfig 
+  5: A<1>                 10: A<6>              15: ide/ide_CLKF 
+
+Signal                        1         2         3         4 FB
+Name                0----+----0----+----0----+----0----+----0 Inputs
+D<15>_BUFR           XXXXXXXXXXXXXXX......................... 15
+                    0----+----1----+----2----+----3----+----4
+                              0         0         0         0
+*********************************** FB7  ***********************************
+Number of function block inputs used/remaining:               0/54
+Number of signals used by logic mapping into function block:  0
+Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
+Name                Pt      Pt    Pt  Pt               #    Type    Use
+(unused)              0       0     0   5     FB7_1         (b)     
+(unused)              0       0     0   5     FB7_2   71    I/O     
+(unused)              0       0     0   5     FB7_3   75    I/O     I
+(unused)              0       0     0   5     FB7_4         (b)     
+(unused)              0       0     0   5     FB7_5   74    I/O     
+(unused)              0       0     0   5     FB7_6   76    I/O     
+(unused)              0       0     0   5     FB7_7   77    I/O     
+(unused)              0       0     0   5     FB7_8   78    I/O     
+(unused)              0       0     0   5     FB7_9   80    I/O     I
+(unused)              0       0     0   5     FB7_10  79    I/O     
+(unused)              0       0     0   5     FB7_11  82    I/O     
+DTACK                 0       0     0   5     FB7_12  85    I/O     O
+(unused)              0       0     0   5     FB7_13  81    I/O     I
+(unused)              0       0     0   5     FB7_14  86    I/O     I
+(unused)              0       0     0   5     FB7_15  87    I/O     I
+(unused)              0       0     0   5     FB7_16  83    I/O     I
+(unused)              0       0     0   5     FB7_17  88    I/O     I
+(unused)              0       0     0   5     FB7_18        (b)     
+
+Signals Used by Logic in Function Block
+
+Signal                        1         2         3         4 FB
+Name                0----+----0----+----0----+----0----+----0 Inputs
+DTACK                ........................................ 0
+                    0----+----1----+----2----+----3----+----4
+                              0         0         0         0
+*********************************** FB8  ***********************************
+Number of function block inputs used/remaining:               0/54
+Number of signals used by logic mapping into function block:  0
+Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
+Name                Pt      Pt    Pt  Pt               #    Type    Use
+(unused)              0       0     0   5     FB8_1         (b)     
+(unused)              0       0     0   5     FB8_2   91    I/O     I
+(unused)              0       0     0   5     FB8_3   95    I/O     I
+(unused)              0       0     0   5     FB8_4   97    I/O     I
+(unused)              0       0     0   5     FB8_5   92    I/O     I
+(unused)              0       0     0   5     FB8_6   93    I/O     
+(unused)              0       0     0   5     FB8_7         (b)     
+(unused)              0       0     0   5     FB8_8   94    I/O     I
+(unused)              0       0     0   5     FB8_9   96    I/O     
+(unused)              0       0     0   5     FB8_10  101   I/O     
+(unused)              0       0     0   5     FB8_11  98    I/O     I
+(unused)              0       0     0   5     FB8_12  100   I/O     
+(unused)              0       0     0   5     FB8_13  103   I/O     I
+(unused)              0       0     0   5     FB8_14  102   I/O     I
+(unused)              0       0     0   5     FB8_15  104   I/O     
+(unused)              0       0     0   5     FB8_16  107   I/O     
+(unused)              0       0     0   5     FB8_17  105   I/O     
+(unused)              0       0     0   5     FB8_18        (b)     
+*******************************  Equations  ********************************
+
+********** Mapped Logic **********
+
+FDCPE_AUTOCONFIG_IN_PROGRESS: FDCPE port map (AUTOCONFIG_IN_PROGRESS,AUTOCONFIG_IN_PROGRESS_D,ide/ide_CLKF,'0','0');
+AUTOCONFIG_IN_PROGRESS_D <= (NOT AS AND autoconfig);
+
+FDCPE_AUTO_CONFIG_DONE0: FDCPE port map (AUTO_CONFIG_DONE(0),AUTO_CONFIG_DONE_CYCLE(0),AS,NOT RESET,'0');
+
+FDCPE_AUTO_CONFIG_DONE1: FDCPE port map (AUTO_CONFIG_DONE(1),AUTO_CONFIG_DONE_CYCLE(1),AS,NOT RESET,'0');
+
+FDCPE_AUTO_CONFIG_DONE2: FDCPE port map (AUTO_CONFIG_DONE(2),AUTO_CONFIG_DONE_CYCLE(2),AS,NOT RESET,'0');
+
+FDCPE_AUTO_CONFIG_DONE_CYCLE0: FDCPE port map (AUTO_CONFIG_DONE_CYCLE(0),AUTO_CONFIG_DONE_CYCLE_D(0),ide/ide_CLKF,'0','0');
+AUTO_CONFIG_DONE_CYCLE_D(0) <= ((RESET AND AUTO_CONFIG_DONE_CYCLE(0))
+	OR (RESET AND NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND 
+	A(6) AND A(3) AND NOT AUTO_CONFIG_DONE(0) AND autoconfig));
+
+FDCPE_AUTO_CONFIG_DONE_CYCLE1: FDCPE port map (AUTO_CONFIG_DONE_CYCLE(1),AUTO_CONFIG_DONE_CYCLE_D(1),ide/ide_CLKF,'0','0');
+AUTO_CONFIG_DONE_CYCLE_D(1) <= ((RESET AND AUTO_CONFIG_DONE_CYCLE(1))
+	OR (RESET AND NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND 
+	A(6) AND A(3) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND 
+	autoconfig));
+
+FDCPE_AUTO_CONFIG_DONE_CYCLE2: FDCPE port map (AUTO_CONFIG_DONE_CYCLE(2),AUTO_CONFIG_DONE_CYCLE_D(2),ide/ide_CLKF,'0','0');
+AUTO_CONFIG_DONE_CYCLE_D(2) <= ((RESET AND AUTO_CONFIG_DONE_CYCLE(2))
+	OR (RESET AND NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND 
+	A(6) AND A(3) AND AUTO_CONFIG_DONE(0) AND AUTO_CONFIG_DONE(1) AND 
+	NOT AUTO_CONFIG_DONE(2) AND autoconfig));
+
+
+D_I(0) <= '1';
+D(0) <= D_I(0) when D_OE(0) = '1' else 'Z';
+D_OE(0) <= (RW AND AUTOCONFIG_IN_PROGRESS);
+
+
+D_I(1) <= '1';
+D(1) <= D_I(1) when D_OE(1) = '1' else 'Z';
+D_OE(1) <= (RW AND AUTOCONFIG_IN_PROGRESS);
+
+
+D_I(2) <= '1';
+D(2) <= D_I(2) when D_OE(2) = '1' else 'Z';
+D_OE(2) <= (RW AND AUTOCONFIG_IN_PROGRESS);
+
+
+D_I(3) <= '1';
+D(3) <= D_I(3) when D_OE(3) = '1' else 'Z';
+D_OE(3) <= (RW AND AUTOCONFIG_IN_PROGRESS);
+
+
+D_I(4) <= '1';
+D(4) <= D_I(4) when D_OE(4) = '1' else 'Z';
+D_OE(4) <= (RW AND AUTOCONFIG_IN_PROGRESS);
+
+
+D_I(5) <= '1';
+D(5) <= D_I(5) when D_OE(5) = '1' else 'Z';
+D_OE(5) <= (RW AND AUTOCONFIG_IN_PROGRESS);
+
+
+D_I(6) <= '1';
+D(6) <= D_I(6) when D_OE(6) = '1' else 'Z';
+D_OE(6) <= (RW AND AUTOCONFIG_IN_PROGRESS);
+
+
+D_I(7) <= '1';
+D(7) <= D_I(7) when D_OE(7) = '1' else 'Z';
+D_OE(7) <= (RW AND AUTOCONFIG_IN_PROGRESS);
+
+
+D_I(8) <= '1';
+D(8) <= D_I(8) when D_OE(8) = '1' else 'Z';
+D_OE(8) <= (RW AND AUTOCONFIG_IN_PROGRESS);
+
+
+D_I(9) <= '1';
+D(9) <= D_I(9) when D_OE(9) = '1' else 'Z';
+D_OE(9) <= (RW AND AUTOCONFIG_IN_PROGRESS);
+
+
+D_I(10) <= '1';
+D(10) <= D_I(10) when D_OE(10) = '1' else 'Z';
+D_OE(10) <= (RW AND AUTOCONFIG_IN_PROGRESS);
+
+
+D_I(11) <= '1';
+D(11) <= D_I(11) when D_OE(11) = '1' else 'Z';
+D_OE(11) <= (RW AND AUTOCONFIG_IN_PROGRESS);
+
+FDCPE_D12_BUFR: FDCPE port map (D(12)_BUFR,D_D(12)_BUFR,ide/ide_CLKF,'0','0');
+D_D(12)_BUFR <= ((RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND A(6) AND NOT A(3) AND 
+	NOT A(2) AND NOT AUTO_CONFIG_DONE(0) AND autoconfig)
+	OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND A(6) AND NOT A(3) AND 
+	NOT A(2) AND NOT AUTO_CONFIG_DONE(1) AND autoconfig)
+	OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND A(6) AND NOT A(3) AND 
+	NOT A(2) AND NOT AUTO_CONFIG_DONE(2) AND autoconfig)
+	OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(1) AND NOT A(6) AND NOT A(3) AND 
+	A(2) AND NOT AUTO_CONFIG_DONE(0) AND autoconfig)
+	OR (RESET AND RW AND NOT AS AND A(5) AND NOT A(4) AND A(1) AND NOT A(6) AND 
+	A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND 
+	autoconfig)
+	OR (ROM_OE_S.EXP)
+	OR (RESET AND NOT D(12) AND NOT RW)
+	OR (RESET AND NOT D(12) AND AS)
+	OR (RESET AND NOT D(12) AND NOT autoconfig)
+	OR (RESET AND NOT D(12) AND AUTO_CONFIG_DONE(0) AND 
+	AUTO_CONFIG_DONE(1) AND AUTO_CONFIG_DONE(2))
+	OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND NOT A(3) AND 
+	NOT A(2) AND NOT AUTO_CONFIG_DONE(0) AND autoconfig)
+	OR (RESET AND RW AND NOT AS AND NOT A(4) AND A(1) AND NOT A(6) AND NOT A(3) AND 
+	A(2) AND NOT AUTO_CONFIG_DONE(0) AND autoconfig)
+	OR (RESET AND RW AND NOT AS AND NOT A(5) AND A(4) AND NOT A(6) AND A(3) AND 
+	NOT A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND 
+	autoconfig)
+	OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND NOT A(3) AND 
+	NOT A(2) AND AUTO_CONFIG_DONE(1) AND NOT AUTO_CONFIG_DONE(2) AND 
+	autoconfig)
+	OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND NOT A(3) AND 
+	NOT A(2) AND NOT AUTO_CONFIG_DONE(1) AND AUTOBOOT_OFF AND autoconfig));
+
+
+D_I(12) <= D(12)_BUFR;
+D(12) <= D_I(12) when D_OE(12) = '1' else 'Z';
+D_OE(12) <= (RW AND AUTOCONFIG_IN_PROGRESS);
+
+FDCPE_D13_BUFR: FDCPE port map (D(13)_BUFR,D_D(13)_BUFR,ide/ide_CLKF,'0','0');
+D_D(13)_BUFR <= ((IDE_BASEADR(6).EXP)
+	OR (RESET AND NOT D(13) AND NOT RW)
+	OR (RESET AND NOT D(13) AND AUTO_CONFIG_DONE(0) AND 
+	AUTO_CONFIG_DONE(1) AND AUTO_CONFIG_DONE(2))
+	OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(6) AND NOT A(3) AND 
+	NOT AUTO_CONFIG_DONE(0) AND autoconfig)
+	OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(3) AND NOT A(2) AND 
+	NOT AUTO_CONFIG_DONE(0) AND autoconfig)
+	OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(3) AND NOT A(2) AND 
+	NOT AUTO_CONFIG_DONE(1) AND autoconfig)
+	OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(3) AND NOT A(2) AND 
+	NOT AUTO_CONFIG_DONE(2) AND autoconfig)
+	OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND A(1) AND NOT A(6) AND 
+	NOT A(3) AND NOT AUTO_CONFIG_DONE(1) AND autoconfig)
+	OR (RESET AND RW AND NOT AS AND NOT A(5) AND A(1) AND NOT A(6) AND NOT A(3) AND 
+	NOT A(2) AND NOT AUTO_CONFIG_DONE(0) AND autoconfig)
+	OR (RESET AND RW AND NOT AS AND NOT A(5) AND A(4) AND NOT A(1) AND NOT A(6) AND 
+	A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND 
+	autoconfig)
+	OR (RESET AND NOT D(13) AND AS)
+	OR (RESET AND NOT D(13) AND NOT autoconfig)
+	OR (RESET AND RW AND NOT AS AND NOT A(5) AND A(4) AND NOT A(6) AND A(3) AND 
+	A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND 
+	autoconfig)
+	OR (RESET AND RW AND NOT AS AND NOT A(5) AND A(1) AND NOT A(6) AND NOT A(3) AND 
+	NOT A(2) AND AUTO_CONFIG_DONE(1) AND NOT AUTO_CONFIG_DONE(2) AND 
+	autoconfig));
+
+
+D_I(13) <= D(13)_BUFR;
+D(13) <= D_I(13) when D_OE(13) = '1' else 'Z';
+D_OE(13) <= (RW AND AUTOCONFIG_IN_PROGRESS);
+
+
+D_I(14) <= D(14)_BUFR;
+D(14) <= D_I(14) when D_OE(14) = '1' else 'Z';
+D_OE(14) <= (RW AND AUTOCONFIG_IN_PROGRESS);
+
+FDCPE_D14_BUFR: FDCPE port map (D(14)_BUFR,D_D(14)_BUFR,ide/ide_CLKF,'0','0');
+D_D(14)_BUFR <= ((EXP16_.EXP)
+	OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND A(1) AND NOT A(3) AND 
+	NOT A(2) AND NOT AUTO_CONFIG_DONE(0) AND autoconfig)
+	OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND A(6) AND NOT A(3) AND 
+	NOT A(2) AND NOT AUTO_CONFIG_DONE(0) AND autoconfig)
+	OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND A(6) AND NOT A(3) AND 
+	NOT A(2) AND NOT AUTO_CONFIG_DONE(1) AND autoconfig)
+	OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND A(6) AND NOT A(3) AND 
+	NOT A(2) AND NOT AUTO_CONFIG_DONE(2) AND autoconfig)
+	OR (RESET AND RW AND NOT AS AND NOT A(4) AND A(1) AND NOT A(6) AND NOT A(3) AND 
+	A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND 
+	autoconfig)
+	OR (RESET AND NOT D(14) AND NOT RW)
+	OR (RESET AND NOT D(14) AND AS)
+	OR (RESET AND NOT D(14) AND NOT autoconfig)
+	OR (RESET AND NOT D(14) AND AUTO_CONFIG_DONE(0) AND 
+	AUTO_CONFIG_DONE(1) AND AUTO_CONFIG_DONE(2))
+	OR (RESET AND RW AND NOT AS AND NOT A(5) AND A(1) AND NOT A(6) AND NOT A(3) AND 
+	A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(2) AND 
+	autoconfig)
+	OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND A(1) AND NOT A(3) AND 
+	NOT A(2) AND NOT AUTO_CONFIG_DONE(1) AND autoconfig)
+	OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND A(1) AND NOT A(3) AND 
+	NOT A(2) AND NOT AUTO_CONFIG_DONE(2) AND autoconfig)
+	OR (RESET AND RW AND NOT AS AND NOT A(5) AND A(1) AND NOT A(6) AND NOT A(3) AND 
+	A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND 
+	autoconfig)
+	OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(6) AND NOT A(3) AND 
+	A(2) AND AUTO_CONFIG_DONE(0) AND AUTO_CONFIG_DONE(1) AND 
+	NOT AUTO_CONFIG_DONE(2) AND autoconfig));
+
+
+D_I(15) <= D(15)_BUFR;
+D(15) <= D_I(15) when D_OE(15) = '1' else 'Z';
+D_OE(15) <= (RW AND AUTOCONFIG_IN_PROGRESS);
+
+FDCPE_D15_BUFR: FDCPE port map (D(15)_BUFR,D_D(15)_BUFR,ide/ide_CLKF,'0','0');
+D_D(15)_BUFR <= ((RESET AND NOT D(15) AND AUTO_CONFIG_DONE(0) AND 
+	AUTO_CONFIG_DONE(1) AND AUTO_CONFIG_DONE(2))
+	OR (RESET AND RW AND NOT AS AND NOT A(5) AND A(1) AND NOT A(6) AND NOT A(3) AND 
+	NOT AUTO_CONFIG_DONE(0) AND autoconfig)
+	OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND A(6) AND NOT A(3) AND 
+	NOT A(2) AND NOT AUTO_CONFIG_DONE(0) AND autoconfig)
+	OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND A(6) AND NOT A(3) AND 
+	NOT A(2) AND NOT AUTO_CONFIG_DONE(1) AND autoconfig)
+	OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND A(6) AND NOT A(3) AND 
+	NOT A(2) AND NOT AUTO_CONFIG_DONE(2) AND autoconfig)
+	OR (RESET AND RW AND NOT AS AND NOT A(5) AND A(1) AND NOT A(6) AND NOT A(3) AND 
+	AUTO_CONFIG_DONE(1) AND NOT AUTO_CONFIG_DONE(2) AND autoconfig)
+	OR (RESET AND RW AND NOT AS AND NOT A(5) AND A(4) AND A(1) AND NOT A(6) AND 
+	A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND 
+	autoconfig)
+	OR (RESET AND RW AND NOT AS AND A(5) AND NOT A(4) AND NOT A(1) AND NOT A(6) AND 
+	NOT A(3) AND A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND 
+	autoconfig)
+	OR (RESET AND RW AND NOT AS AND NOT A(5) AND A(4) AND NOT A(1) AND NOT A(6) AND 
+	A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND 
+	autoconfig)
+	OR (RESET AND NOT D(15) AND NOT RW)
+	OR (RESET AND NOT D(15) AND AS)
+	OR (RESET AND NOT D(15) AND NOT autoconfig)
+	OR (RESET AND RW AND NOT AS AND NOT A(5) AND A(1) AND NOT A(6) AND NOT A(3) AND 
+	NOT A(2) AND NOT AUTO_CONFIG_DONE(1) AND autoconfig));
+
+
+DTACK_I <= '0';
+DTACK <= DTACK_I when DTACK_OE = '1' else 'Z';
+DTACK_OE <= '0';
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+IDE_A(0) <= A(9);
+
+
+IDE_A(1) <= A(10);
+
+
+IDE_A(2) <= A(11);
+
+FTCPE_IDE_BASEADR0: FTCPE port map (IDE_BASEADR(0),IDE_BASEADR_T(0),ide/ide_CLKF,'0','0');
+IDE_BASEADR_T(0) <= ((NOT RESET AND NOT IDE_BASEADR(0))
+	OR (NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND A(6) AND 
+	A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND 
+	NOT IDE_BASEADR(0) AND autoconfig AND D(8).PIN)
+	OR (RESET AND NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND 
+	A(6) AND A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND 
+	NOT AUTO_CONFIG_DONE(1) AND IDE_BASEADR(0) AND autoconfig AND NOT D(8).PIN));
+
+FTCPE_IDE_BASEADR1: FTCPE port map (IDE_BASEADR(1),IDE_BASEADR_T(1),ide/ide_CLKF,'0','0');
+IDE_BASEADR_T(1) <= ((NOT RESET AND NOT IDE_BASEADR(1))
+	OR (NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND A(6) AND 
+	A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND 
+	NOT IDE_BASEADR(1) AND autoconfig AND D(9).PIN)
+	OR (RESET AND NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND 
+	A(6) AND A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND 
+	NOT AUTO_CONFIG_DONE(1) AND IDE_BASEADR(1) AND autoconfig AND NOT D(9).PIN));
+
+FTCPE_IDE_BASEADR2: FTCPE port map (IDE_BASEADR(2),IDE_BASEADR_T(2),ide/ide_CLKF,'0','0');
+IDE_BASEADR_T(2) <= ((NOT RESET AND NOT IDE_BASEADR(2))
+	OR (NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND A(6) AND 
+	A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND 
+	NOT IDE_BASEADR(2) AND autoconfig AND D(10).PIN)
+	OR (RESET AND NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND 
+	A(6) AND A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND 
+	NOT AUTO_CONFIG_DONE(1) AND IDE_BASEADR(2) AND autoconfig AND NOT D(10).PIN));
+
+FTCPE_IDE_BASEADR3: FTCPE port map (IDE_BASEADR(3),IDE_BASEADR_T(3),ide/ide_CLKF,'0','0');
+IDE_BASEADR_T(3) <= ((NOT RESET AND NOT IDE_BASEADR(3))
+	OR (NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND A(6) AND 
+	A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND 
+	NOT IDE_BASEADR(3) AND autoconfig AND D(11).PIN)
+	OR (RESET AND NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND 
+	A(6) AND A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND 
+	NOT AUTO_CONFIG_DONE(1) AND IDE_BASEADR(3) AND autoconfig AND NOT D(11).PIN));
+
+FTCPE_IDE_BASEADR4: FTCPE port map (IDE_BASEADR(4),IDE_BASEADR_T(4),ide/ide_CLKF,'0','0');
+IDE_BASEADR_T(4) <= ((NOT RESET AND NOT IDE_BASEADR(4))
+	OR (NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND A(6) AND 
+	A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND 
+	NOT IDE_BASEADR(4) AND autoconfig AND D(12).PIN)
+	OR (RESET AND NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND 
+	A(6) AND A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND 
+	NOT AUTO_CONFIG_DONE(1) AND IDE_BASEADR(4) AND autoconfig AND NOT D(12).PIN));
+
+FTCPE_IDE_BASEADR5: FTCPE port map (IDE_BASEADR(5),IDE_BASEADR_T(5),ide/ide_CLKF,'0','0');
+IDE_BASEADR_T(5) <= ((NOT RESET AND NOT IDE_BASEADR(5))
+	OR (NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND A(6) AND 
+	A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND 
+	NOT IDE_BASEADR(5) AND autoconfig AND D(13).PIN)
+	OR (RESET AND NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND 
+	A(6) AND A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND 
+	NOT AUTO_CONFIG_DONE(1) AND IDE_BASEADR(5) AND autoconfig AND NOT D(13).PIN));
+
+FTCPE_IDE_BASEADR6: FTCPE port map (IDE_BASEADR(6),IDE_BASEADR_T(6),ide/ide_CLKF,'0','0');
+IDE_BASEADR_T(6) <= ((NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND A(6) AND 
+	A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND 
+	NOT IDE_BASEADR(6) AND autoconfig AND D(14).PIN)
+	OR (RESET AND NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND 
+	A(6) AND A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND 
+	NOT AUTO_CONFIG_DONE(1) AND IDE_BASEADR(6) AND autoconfig AND NOT D(14).PIN)
+	OR (NOT RESET AND NOT IDE_BASEADR(6)));
+
+FTCPE_IDE_BASEADR7: FTCPE port map (IDE_BASEADR(7),IDE_BASEADR_T(7),ide/ide_CLKF,'0','0');
+IDE_BASEADR_T(7) <= ((RESET AND NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND 
+	A(6) AND A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND 
+	NOT AUTO_CONFIG_DONE(1) AND IDE_BASEADR(7) AND autoconfig AND NOT D(15).PIN)
+	OR (NOT RESET AND NOT IDE_BASEADR(7))
+	OR (NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND A(6) AND 
+	A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND 
+	NOT IDE_BASEADR(7) AND autoconfig AND D(15).PIN));
+
+
+IDE_CS(0) <= NOT A(12);
+
+
+IDE_CS(1) <= NOT A(13);
+
+FDCPE_IDE_ENABLE: FDCPE port map (IDE_ENABLE,IDE_ENABLE_D,ide/ide_CLKF,'0','0');
+IDE_ENABLE_D <= ((RESET AND NOT IDE_ENABLE)
+	OR (RESET AND NOT RW AND NOT AS AND ide));
+
+FDCPE_IDE_R: FDCPE port map (IDE_R,IDE_R_D,ide/ide_CLKF,'0','0');
+IDE_R_D <= (RESET AND RW AND NOT AS AND NOT IDE_ENABLE AND ide);
+
+FDCPE_IDE_W: FDCPE port map (IDE_W,IDE_W_D,ide/ide_CLKF,'0','0');
+IDE_W_D <= (RESET AND NOT RW AND NOT AS AND ide);
+
+
+ROM_B(0) <= '0';
+
+
+ROM_B(1) <= '0';
+
+FDCPE_ROM_OE: FDCPE port map (ROM_OE,ROM_OE_D,ide/ide_CLKF,'0','0');
+ROM_OE_D <= (RESET AND RW AND NOT AS AND IDE_ENABLE AND ide);
+
+FDCPE_SHUT_UP1: FDCPE port map (SHUT_UP(1),SHUT_UP_D(1),ide/ide_CLKF,'0','0');
+SHUT_UP_D(1) <= ((RESET AND NOT SHUT_UP(1))
+	OR (RESET AND NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND 
+	A(6) AND A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND 
+	NOT AUTO_CONFIG_DONE(1) AND autoconfig));
+
+FDCPE_autoconfig: FDCPE port map (autoconfig,autoconfig_D,ide/ide_CLKF,'0','0');
+autoconfig_D <= ((A(23) AND A(22) AND A(21) AND A(19) AND 
+	NOT AUTO_CONFIG_DONE(0) AND BERR AND NOT A(17) AND NOT A(16) AND NOT A(20) AND NOT A(18))
+	OR (A(23) AND A(22) AND A(21) AND A(19) AND 
+	NOT AUTO_CONFIG_DONE(1) AND BERR AND NOT A(17) AND NOT A(16) AND NOT A(20) AND NOT A(18))
+	OR (A(23) AND A(22) AND A(21) AND A(19) AND 
+	NOT AUTO_CONFIG_DONE(2) AND BERR AND NOT A(17) AND NOT A(16) AND NOT A(20) AND NOT A(18)));
+
+FDCPE_ide: FDCPE port map (ide,ide_D,ide/ide_CLKF,'0','0');
+ide_D <= ((SHUT_UP(1))
+	OR (NOT BERR)
+	OR (EXP20_.EXP)
+	OR (A(23) AND NOT IDE_BASEADR(7))
+	OR (NOT A(23) AND IDE_BASEADR(7))
+	OR (A(22) AND NOT IDE_BASEADR(6))
+	OR (NOT A(22) AND IDE_BASEADR(6))
+	OR (IDE_BASEADR(1) AND NOT A(17))
+	OR (autoconfig.EXP)
+	OR (IDE_BASEADR(0) AND NOT A(16))
+	OR (NOT IDE_BASEADR(0) AND A(16))
+	OR (NOT IDE_BASEADR(1) AND A(17))
+	OR (IDE_BASEADR(2) AND NOT A(18))
+	OR (NOT IDE_BASEADR(2) AND A(18))
+	OR (A(19) AND NOT IDE_BASEADR(3))
+	OR (NOT A(19) AND IDE_BASEADR(3)));
+
+
+ide/ide_CLKF <= NOT (C3
+	 XOR 
+ide/ide_CLKF <= NOT (C1);
+
+Register Legend:
+ FDCPE (Q,D,C,CLR,PRE,CE); 
+ FTCPE (Q,D,C,CLR,PRE,CE); 
+ LDCP  (Q,D,G,CLR,PRE); 
+
+******************************  Device Pin Out *****************************
+
+Device : XC95144XL-10-TQ144
+
+
+Pin Signal                         Pin Signal                        
+No. Name                           No. Name                          
+  1 VCC                              73 VCC                           
+  2 D<0>                             74 KPR                           
+  3 KPR                              75 AUTOBOOT_OFF                  
+  4 KPR                              76 KPR                           
+  5 KPR                              77 KPR                           
+  6 KPR                              78 KPR                           
+  7 KPR                              79 KPR                           
+  8 VCC                              80 AS                            
+  9 KPR                              81 UDS                           
+ 10 KPR                              82 KPR                           
+ 11 KPR                              83 RW                            
+ 12 KPR                              84 VCC                           
+ 13 KPR                              85 DTACK                         
+ 14 D<6>                             86 A<23>                         
+ 15 D<3>                             87 A<22>                         
+ 16 D<7>                             88 A<21>                         
+ 17 D<1>                             89 GND                           
+ 18 GND                              90 GND                           
+ 19 D<8>                             91 A<20>                         
+ 20 D<5>                             92 A<19>                         
+ 21 D<4>                             93 KPR                           
+ 22 IDE_CS<0>                        94 A<18>                         
+ 23 IDE_CS<1>                        95 A<17>                         
+ 24 IDE_A<0>                         96 KPR                           
+ 25 IDE_A<2>                         97 A<16>                         
+ 26 IDE_A<1>                         98 BERR                          
+ 27 IDE_R                            99 GND                           
+ 28 IDE_W                           100 KPR                           
+ 29 GND                             101 KPR                           
+ 30 KPR                             102 C3                            
+ 31 KPR                             103 C1                            
+ 32 KPR                             104 KPR                           
+ 33 KPR                             105 KPR                           
+ 34 KPR                             106 KPR                           
+ 35 ROM_OE                          107 KPR                           
+ 36 GND                             108 GND                           
+ 37 VCC                             109 VCC                           
+ 38 KPR                             110 KPR                           
+ 39 D<2>                            111 KPR                           
+ 40 D<9>                            112 KPR                           
+ 41 D<10>                           113 KPR                           
+ 42 VCC                             114 GND                           
+ 43 D<11>                           115 KPR                           
+ 44 D<12>                           116 KPR                           
+ 45 D<13>                           117 KPR                           
+ 46 D<14>                           118 KPR                           
+ 47 GND                             119 KPR                           
+ 48 D<15>                           120 KPR                           
+ 49 A<5>                            121 KPR                           
+ 50 A<4>                            122 TDO                           
+ 51 A<6>                            123 GND                           
+ 52 A<3>                            124 KPR                           
+ 53 KPR                             125 KPR                           
+ 54 A<2>                            126 KPR                           
+ 55 VCC                             127 VCC                           
+ 56 KPR                             128 KPR                           
+ 57 A<1>                            129 KPR                           
+ 58 A<9>                            130 KPR                           
+ 59 A<10>                           131 KPR                           
+ 60 A<11>                           132 KPR                           
+ 61 A<12>                           133 KPR                           
+ 62 GND                             134 KPR                           
+ 63 TDI                             135 KPR                           
+ 64 A<13>                           136 KPR                           
+ 65 TMS                             137 KPR                           
+ 66 KPR                             138 KPR                           
+ 67 TCK                             139 KPR                           
+ 68 ROM_B<0>                        140 KPR                           
+ 69 ROM_B<1>                        141 VCC                           
+ 70 KPR                             142 KPR                           
+ 71 KPR                             143 RESET                         
+ 72 GND                             144 GND                           
+
+
+Legend :  NC  = Not Connected, unbonded pin
+         PGND = Unused I/O configured as additional Ground pin
+         TIE  = Unused I/O floating -- must tie to VCC, GND or other signal
+         KPR  = Unused I/O with weak keeper (leave unconnected)
+         VCC  = Dedicated Power Pin
+         GND  = Dedicated Ground Pin
+         TDI  = Test Data In, JTAG pin
+         TDO  = Test Data Out, JTAG pin
+         TCK  = Test Clock, JTAG pin
+         TMS  = Test Mode Select, JTAG pin
+  PROHIBITED  = User reserved pin
+****************************  Compiler Options  ****************************
+
+Following is a list of all global compiler options used by the fitter run.
+
+Device(s) Specified                         : xc95144xl-10-TQ144
+Optimization Method                         : SPEED
+Multi-Level Logic Optimization              : ON
+Ignore Timing Specifications                : OFF
+Default Register Power Up Value             : LOW
+Keep User Location Constraints              : ON
+What-You-See-Is-What-You-Get                : OFF
+Exhaustive Fitting                          : OFF
+Keep Unused Inputs                          : OFF
+Slew Rate                                   : FAST
+Power Mode                                  : STD
+Ground on Unused IOs                        : OFF
+Set I/O Pin Termination                     : KEEPER
+Global Clock Optimization                   : ON
+Global Set/Reset Optimization               : ON
+Global Ouput Enable Optimization            : ON
+Input Limit                                 : 54
+Pterm Limit                                 : 25
+
+
+ + +
+ diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/ascii.tmp b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/ascii.tmp new file mode 100644 index 0000000..9b23fb5 --- /dev/null +++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/ascii.tmp @@ -0,0 +1,4 @@ +
+ + +
diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/asciidoc.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/asciidoc.htm new file mode 100644 index 0000000..3455598 --- /dev/null +++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/asciidoc.htm @@ -0,0 +1,71 @@ + + + + + + + + + + +Text Report + + + + + + + + + + + + + + + + + + + + + + + + +

Text Report

+ +

Selecting Text + Report from the left-hand frame will give you a printable text version + of the fitter report.  It + contains sections similar to those of the XML report (a summary section, + errors and warnings, mapped logic, function blocks, function block details, + a text-graphical display of the pinout, and a summary of compiler options), + but it is not easily navigable.  It + is best to use the text report only when you need to print out a hard + copy of the fitter results.

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Equations

+ + +
+
+********** Mapped Logic ********** +
+FDCPE_AUTOCONFIG_IN_PROGRESS: FDCPE port map (AUTOCONFIG_IN_PROGRESS,AUTOCONFIG_IN_PROGRESS_D,ide/ide_CLKF,'0','0'); +
     AUTOCONFIG_IN_PROGRESS_D <= (NOT AS AND autoconfig); +
+FDCPE_AUTO_CONFIG_DONE0: FDCPE port map (AUTO_CONFIG_DONE(0),AUTO_CONFIG_DONE_CYCLE(0),AS,NOT RESET,'0'); +
+FDCPE_AUTO_CONFIG_DONE1: FDCPE port map (AUTO_CONFIG_DONE(1),AUTO_CONFIG_DONE_CYCLE(1),AS,NOT RESET,'0'); +
+FDCPE_AUTO_CONFIG_DONE2: FDCPE port map (AUTO_CONFIG_DONE(2),AUTO_CONFIG_DONE_CYCLE(2),AS,NOT RESET,'0'); +
+FDCPE_AUTO_CONFIG_DONE_CYCLE0: FDCPE port map (AUTO_CONFIG_DONE_CYCLE(0),AUTO_CONFIG_DONE_CYCLE_D(0),ide/ide_CLKF,'0','0'); +
     AUTO_CONFIG_DONE_CYCLE_D(0) <= ((RESET AND AUTO_CONFIG_DONE_CYCLE(0)) +
      OR (RESET AND NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND +
      A(6) AND A(3) AND NOT AUTO_CONFIG_DONE(0) AND autoconfig)); +
+FDCPE_AUTO_CONFIG_DONE_CYCLE1: FDCPE port map (AUTO_CONFIG_DONE_CYCLE(1),AUTO_CONFIG_DONE_CYCLE_D(1),ide/ide_CLKF,'0','0'); +
     AUTO_CONFIG_DONE_CYCLE_D(1) <= ((RESET AND AUTO_CONFIG_DONE_CYCLE(1)) +
      OR (RESET AND NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND +
      A(6) AND A(3) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND +
      autoconfig)); +
+FDCPE_AUTO_CONFIG_DONE_CYCLE2: FDCPE port map (AUTO_CONFIG_DONE_CYCLE(2),AUTO_CONFIG_DONE_CYCLE_D(2),ide/ide_CLKF,'0','0'); +
     AUTO_CONFIG_DONE_CYCLE_D(2) <= ((RESET AND AUTO_CONFIG_DONE_CYCLE(2)) +
      OR (RESET AND NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND +
      A(6) AND A(3) AND AUTO_CONFIG_DONE(0) AND AUTO_CONFIG_DONE(1) AND +
      NOT AUTO_CONFIG_DONE(2) AND autoconfig)); +
+
+D_I(0) <= '1'; +
     D(0) <= D_I(0) when D_OE(0) = '1' else 'Z'; +
     D_OE(0) <= (RW AND AUTOCONFIG_IN_PROGRESS); +
+
+D_I(1) <= '1'; +
     D(1) <= D_I(1) when D_OE(1) = '1' else 'Z'; +
     D_OE(1) <= (RW AND AUTOCONFIG_IN_PROGRESS); +
+
+D_I(2) <= '1'; +
     D(2) <= D_I(2) when D_OE(2) = '1' else 'Z'; +
     D_OE(2) <= (RW AND AUTOCONFIG_IN_PROGRESS); +
+
+D_I(3) <= '1'; +
     D(3) <= D_I(3) when D_OE(3) = '1' else 'Z'; +
     D_OE(3) <= (RW AND AUTOCONFIG_IN_PROGRESS); +
+
+D_I(4) <= '1'; +
     D(4) <= D_I(4) when D_OE(4) = '1' else 'Z'; +
     D_OE(4) <= (RW AND AUTOCONFIG_IN_PROGRESS); +
+
+D_I(5) <= '1'; +
     D(5) <= D_I(5) when D_OE(5) = '1' else 'Z'; +
     D_OE(5) <= (RW AND AUTOCONFIG_IN_PROGRESS); +
+
+D_I(6) <= '1'; +
     D(6) <= D_I(6) when D_OE(6) = '1' else 'Z'; +
     D_OE(6) <= (RW AND AUTOCONFIG_IN_PROGRESS); +
+
+D_I(7) <= '1'; +
     D(7) <= D_I(7) when D_OE(7) = '1' else 'Z'; +
     D_OE(7) <= (RW AND AUTOCONFIG_IN_PROGRESS); +
+
+D_I(8) <= '1'; +
     D(8) <= D_I(8) when D_OE(8) = '1' else 'Z'; +
     D_OE(8) <= (RW AND AUTOCONFIG_IN_PROGRESS); +
+
+D_I(9) <= '1'; +
     D(9) <= D_I(9) when D_OE(9) = '1' else 'Z'; +
     D_OE(9) <= (RW AND AUTOCONFIG_IN_PROGRESS); +
+
+D_I(10) <= '1'; +
     D(10) <= D_I(10) when D_OE(10) = '1' else 'Z'; +
     D_OE(10) <= (RW AND AUTOCONFIG_IN_PROGRESS); +
+
+D_I(11) <= '1'; +
     D(11) <= D_I(11) when D_OE(11) = '1' else 'Z'; +
     D_OE(11) <= (RW AND AUTOCONFIG_IN_PROGRESS); +
+FDCPE_D12_BUFR: FDCPE port map (D(12)_BUFR,D_D(12)_BUFR,ide/ide_CLKF,'0','0'); +
     D_D(12)_BUFR <= ((RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND A(6) AND NOT A(3) AND +
      NOT A(2) AND NOT AUTO_CONFIG_DONE(0) AND autoconfig) +
      OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND A(6) AND NOT A(3) AND +
      NOT A(2) AND NOT AUTO_CONFIG_DONE(1) AND autoconfig) +
      OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND A(6) AND NOT A(3) AND +
      NOT A(2) AND NOT AUTO_CONFIG_DONE(2) AND autoconfig) +
      OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(1) AND NOT A(6) AND NOT A(3) AND +
      A(2) AND NOT AUTO_CONFIG_DONE(0) AND autoconfig) +
      OR (RESET AND RW AND NOT AS AND A(5) AND NOT A(4) AND A(1) AND NOT A(6) AND +
      A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND +
      autoconfig) +
      OR (ROM_OE_S.EXP) +
      OR (RESET AND NOT D(12) AND NOT RW) +
      OR (RESET AND NOT D(12) AND AS) +
      OR (RESET AND NOT D(12) AND NOT autoconfig) +
      OR (RESET AND NOT D(12) AND AUTO_CONFIG_DONE(0) AND +
      AUTO_CONFIG_DONE(1) AND AUTO_CONFIG_DONE(2)) +
      OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND NOT A(3) AND +
      NOT A(2) AND NOT AUTO_CONFIG_DONE(0) AND autoconfig) +
      OR (RESET AND RW AND NOT AS AND NOT A(4) AND A(1) AND NOT A(6) AND NOT A(3) AND +
      A(2) AND NOT AUTO_CONFIG_DONE(0) AND autoconfig) +
      OR (RESET AND RW AND NOT AS AND NOT A(5) AND A(4) AND NOT A(6) AND A(3) AND +
      NOT A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND +
      autoconfig) +
      OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND NOT A(3) AND +
      NOT A(2) AND AUTO_CONFIG_DONE(1) AND NOT AUTO_CONFIG_DONE(2) AND +
      autoconfig) +
      OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND NOT A(3) AND +
      NOT A(2) AND NOT AUTO_CONFIG_DONE(1) AND AUTOBOOT_OFF AND autoconfig)); +
+
+D_I(12) <= D(12)_BUFR; +
     D(12) <= D_I(12) when D_OE(12) = '1' else 'Z'; +
     D_OE(12) <= (RW AND AUTOCONFIG_IN_PROGRESS); +
+FDCPE_D13_BUFR: FDCPE port map (D(13)_BUFR,D_D(13)_BUFR,ide/ide_CLKF,'0','0'); +
     D_D(13)_BUFR <= ((IDE_BASEADR(6).EXP) +
      OR (RESET AND NOT D(13) AND NOT RW) +
      OR (RESET AND NOT D(13) AND AUTO_CONFIG_DONE(0) AND +
      AUTO_CONFIG_DONE(1) AND AUTO_CONFIG_DONE(2)) +
      OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(6) AND NOT A(3) AND +
      NOT AUTO_CONFIG_DONE(0) AND autoconfig) +
      OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(3) AND NOT A(2) AND +
      NOT AUTO_CONFIG_DONE(0) AND autoconfig) +
      OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(3) AND NOT A(2) AND +
      NOT AUTO_CONFIG_DONE(1) AND autoconfig) +
      OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(3) AND NOT A(2) AND +
      NOT AUTO_CONFIG_DONE(2) AND autoconfig) +
      OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND A(1) AND NOT A(6) AND +
      NOT A(3) AND NOT AUTO_CONFIG_DONE(1) AND autoconfig) +
      OR (RESET AND RW AND NOT AS AND NOT A(5) AND A(1) AND NOT A(6) AND NOT A(3) AND +
      NOT A(2) AND NOT AUTO_CONFIG_DONE(0) AND autoconfig) +
      OR (RESET AND RW AND NOT AS AND NOT A(5) AND A(4) AND NOT A(1) AND NOT A(6) AND +
      A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND +
      autoconfig) +
      OR (RESET AND NOT D(13) AND AS) +
      OR (RESET AND NOT D(13) AND NOT autoconfig) +
      OR (RESET AND RW AND NOT AS AND NOT A(5) AND A(4) AND NOT A(6) AND A(3) AND +
      A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND +
      autoconfig) +
      OR (RESET AND RW AND NOT AS AND NOT A(5) AND A(1) AND NOT A(6) AND NOT A(3) AND +
      NOT A(2) AND AUTO_CONFIG_DONE(1) AND NOT AUTO_CONFIG_DONE(2) AND +
      autoconfig)); +
+
+D_I(13) <= D(13)_BUFR; +
     D(13) <= D_I(13) when D_OE(13) = '1' else 'Z'; +
     D_OE(13) <= (RW AND AUTOCONFIG_IN_PROGRESS); +
+
+D_I(14) <= D(14)_BUFR; +
     D(14) <= D_I(14) when D_OE(14) = '1' else 'Z'; +
     D_OE(14) <= (RW AND AUTOCONFIG_IN_PROGRESS); +
+FDCPE_D14_BUFR: FDCPE port map (D(14)_BUFR,D_D(14)_BUFR,ide/ide_CLKF,'0','0'); +
     D_D(14)_BUFR <= ((EXP16_.EXP) +
      OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND A(1) AND NOT A(3) AND +
      NOT A(2) AND NOT AUTO_CONFIG_DONE(0) AND autoconfig) +
      OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND A(6) AND NOT A(3) AND +
      NOT A(2) AND NOT AUTO_CONFIG_DONE(0) AND autoconfig) +
      OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND A(6) AND NOT A(3) AND +
      NOT A(2) AND NOT AUTO_CONFIG_DONE(1) AND autoconfig) +
      OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND A(6) AND NOT A(3) AND +
      NOT A(2) AND NOT AUTO_CONFIG_DONE(2) AND autoconfig) +
      OR (RESET AND RW AND NOT AS AND NOT A(4) AND A(1) AND NOT A(6) AND NOT A(3) AND +
      A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND +
      autoconfig) +
      OR (RESET AND NOT D(14) AND NOT RW) +
      OR (RESET AND NOT D(14) AND AS) +
      OR (RESET AND NOT D(14) AND NOT autoconfig) +
      OR (RESET AND NOT D(14) AND AUTO_CONFIG_DONE(0) AND +
      AUTO_CONFIG_DONE(1) AND AUTO_CONFIG_DONE(2)) +
      OR (RESET AND RW AND NOT AS AND NOT A(5) AND A(1) AND NOT A(6) AND NOT A(3) AND +
      A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(2) AND +
      autoconfig) +
      OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND A(1) AND NOT A(3) AND +
      NOT A(2) AND NOT AUTO_CONFIG_DONE(1) AND autoconfig) +
      OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND A(1) AND NOT A(3) AND +
      NOT A(2) AND NOT AUTO_CONFIG_DONE(2) AND autoconfig) +
      OR (RESET AND RW AND NOT AS AND NOT A(5) AND A(1) AND NOT A(6) AND NOT A(3) AND +
      A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND +
      autoconfig) +
      OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(6) AND NOT A(3) AND +
      A(2) AND AUTO_CONFIG_DONE(0) AND AUTO_CONFIG_DONE(1) AND +
      NOT AUTO_CONFIG_DONE(2) AND autoconfig)); +
+
+D_I(15) <= D(15)_BUFR; +
     D(15) <= D_I(15) when D_OE(15) = '1' else 'Z'; +
     D_OE(15) <= (RW AND AUTOCONFIG_IN_PROGRESS); +
+FDCPE_D15_BUFR: FDCPE port map (D(15)_BUFR,D_D(15)_BUFR,ide/ide_CLKF,'0','0'); +
     D_D(15)_BUFR <= ((RESET AND NOT D(15) AND AUTO_CONFIG_DONE(0) AND +
      AUTO_CONFIG_DONE(1) AND AUTO_CONFIG_DONE(2)) +
      OR (RESET AND RW AND NOT AS AND NOT A(5) AND A(1) AND NOT A(6) AND NOT A(3) AND +
      NOT AUTO_CONFIG_DONE(0) AND autoconfig) +
      OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND A(6) AND NOT A(3) AND +
      NOT A(2) AND NOT AUTO_CONFIG_DONE(0) AND autoconfig) +
      OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND A(6) AND NOT A(3) AND +
      NOT A(2) AND NOT AUTO_CONFIG_DONE(1) AND autoconfig) +
      OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND A(6) AND NOT A(3) AND +
      NOT A(2) AND NOT AUTO_CONFIG_DONE(2) AND autoconfig) +
      OR (RESET AND RW AND NOT AS AND NOT A(5) AND A(1) AND NOT A(6) AND NOT A(3) AND +
      AUTO_CONFIG_DONE(1) AND NOT AUTO_CONFIG_DONE(2) AND autoconfig) +
      OR (RESET AND RW AND NOT AS AND NOT A(5) AND A(4) AND A(1) AND NOT A(6) AND +
      A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND +
      autoconfig) +
      OR (RESET AND RW AND NOT AS AND A(5) AND NOT A(4) AND NOT A(1) AND NOT A(6) AND +
      NOT A(3) AND A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND +
      autoconfig) +
      OR (RESET AND RW AND NOT AS AND NOT A(5) AND A(4) AND NOT A(1) AND NOT A(6) AND +
      A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND +
      autoconfig) +
      OR (RESET AND NOT D(15) AND NOT RW) +
      OR (RESET AND NOT D(15) AND AS) +
      OR (RESET AND NOT D(15) AND NOT autoconfig) +
      OR (RESET AND RW AND NOT AS AND NOT A(5) AND A(1) AND NOT A(6) AND NOT A(3) AND +
      NOT A(2) AND NOT AUTO_CONFIG_DONE(1) AND autoconfig)); +
+
+DTACK_I <= '0'; +
     DTACK <= DTACK_I when DTACK_OE = '1' else 'Z'; +
     DTACK_OE <= '0'; +
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+IDE_A(0) <= A(9); +
+
+IDE_A(1) <= A(10); +
+
+IDE_A(2) <= A(11); +
+FTCPE_IDE_BASEADR0: FTCPE port map (IDE_BASEADR(0),IDE_BASEADR_T(0),ide/ide_CLKF,'0','0'); +
     IDE_BASEADR_T(0) <= ((NOT RESET AND NOT IDE_BASEADR(0)) +
      OR (NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND A(6) AND +
      A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND +
      NOT IDE_BASEADR(0) AND autoconfig AND D(8).PIN) +
      OR (RESET AND NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND +
      A(6) AND A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND +
      NOT AUTO_CONFIG_DONE(1) AND IDE_BASEADR(0) AND autoconfig AND NOT D(8).PIN)); +
+FTCPE_IDE_BASEADR1: FTCPE port map (IDE_BASEADR(1),IDE_BASEADR_T(1),ide/ide_CLKF,'0','0'); +
     IDE_BASEADR_T(1) <= ((NOT RESET AND NOT IDE_BASEADR(1)) +
      OR (NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND A(6) AND +
      A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND +
      NOT IDE_BASEADR(1) AND autoconfig AND D(9).PIN) +
      OR (RESET AND NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND +
      A(6) AND A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND +
      NOT AUTO_CONFIG_DONE(1) AND IDE_BASEADR(1) AND autoconfig AND NOT D(9).PIN)); +
+FTCPE_IDE_BASEADR2: FTCPE port map (IDE_BASEADR(2),IDE_BASEADR_T(2),ide/ide_CLKF,'0','0'); +
     IDE_BASEADR_T(2) <= ((NOT RESET AND NOT IDE_BASEADR(2)) +
      OR (NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND A(6) AND +
      A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND +
      NOT IDE_BASEADR(2) AND autoconfig AND D(10).PIN) +
      OR (RESET AND NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND +
      A(6) AND A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND +
      NOT AUTO_CONFIG_DONE(1) AND IDE_BASEADR(2) AND autoconfig AND NOT D(10).PIN)); +
+FTCPE_IDE_BASEADR3: FTCPE port map (IDE_BASEADR(3),IDE_BASEADR_T(3),ide/ide_CLKF,'0','0'); +
     IDE_BASEADR_T(3) <= ((NOT RESET AND NOT IDE_BASEADR(3)) +
      OR (NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND A(6) AND +
      A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND +
      NOT IDE_BASEADR(3) AND autoconfig AND D(11).PIN) +
      OR (RESET AND NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND +
      A(6) AND A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND +
      NOT AUTO_CONFIG_DONE(1) AND IDE_BASEADR(3) AND autoconfig AND NOT D(11).PIN)); +
+FTCPE_IDE_BASEADR4: FTCPE port map (IDE_BASEADR(4),IDE_BASEADR_T(4),ide/ide_CLKF,'0','0'); +
     IDE_BASEADR_T(4) <= ((NOT RESET AND NOT IDE_BASEADR(4)) +
      OR (NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND A(6) AND +
      A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND +
      NOT IDE_BASEADR(4) AND autoconfig AND D(12).PIN) +
      OR (RESET AND NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND +
      A(6) AND A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND +
      NOT AUTO_CONFIG_DONE(1) AND IDE_BASEADR(4) AND autoconfig AND NOT D(12).PIN)); +
+FTCPE_IDE_BASEADR5: FTCPE port map (IDE_BASEADR(5),IDE_BASEADR_T(5),ide/ide_CLKF,'0','0'); +
     IDE_BASEADR_T(5) <= ((NOT RESET AND NOT IDE_BASEADR(5)) +
      OR (NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND A(6) AND +
      A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND +
      NOT IDE_BASEADR(5) AND autoconfig AND D(13).PIN) +
      OR (RESET AND NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND +
      A(6) AND A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND +
      NOT AUTO_CONFIG_DONE(1) AND IDE_BASEADR(5) AND autoconfig AND NOT D(13).PIN)); +
+FTCPE_IDE_BASEADR6: FTCPE port map (IDE_BASEADR(6),IDE_BASEADR_T(6),ide/ide_CLKF,'0','0'); +
     IDE_BASEADR_T(6) <= ((NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND A(6) AND +
      A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND +
      NOT IDE_BASEADR(6) AND autoconfig AND D(14).PIN) +
      OR (RESET AND NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND +
      A(6) AND A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND +
      NOT AUTO_CONFIG_DONE(1) AND IDE_BASEADR(6) AND autoconfig AND NOT D(14).PIN) +
      OR (NOT RESET AND NOT IDE_BASEADR(6))); +
+FTCPE_IDE_BASEADR7: FTCPE port map (IDE_BASEADR(7),IDE_BASEADR_T(7),ide/ide_CLKF,'0','0'); +
     IDE_BASEADR_T(7) <= ((RESET AND NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND +
      A(6) AND A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND +
      NOT AUTO_CONFIG_DONE(1) AND IDE_BASEADR(7) AND autoconfig AND NOT D(15).PIN) +
      OR (NOT RESET AND NOT IDE_BASEADR(7)) +
      OR (NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND A(6) AND +
      A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND +
      NOT IDE_BASEADR(7) AND autoconfig AND D(15).PIN)); +
+
+IDE_CS(0) <= NOT A(12); +
+
+IDE_CS(1) <= NOT A(13); +
+FDCPE_IDE_ENABLE: FDCPE port map (IDE_ENABLE,IDE_ENABLE_D,ide/ide_CLKF,'0','0'); +
     IDE_ENABLE_D <= ((RESET AND NOT IDE_ENABLE) +
      OR (RESET AND NOT RW AND NOT AS AND ide)); +
+FDCPE_IDE_R: FDCPE port map (IDE_R,IDE_R_D,ide/ide_CLKF,'0','0'); +
     IDE_R_D <= (RESET AND RW AND NOT AS AND NOT IDE_ENABLE AND ide); +
+FDCPE_IDE_W: FDCPE port map (IDE_W,IDE_W_D,ide/ide_CLKF,'0','0'); +
     IDE_W_D <= (RESET AND NOT RW AND NOT AS AND ide); +
+
+ROM_B(0) <= '0'; +
+
+ROM_B(1) <= '0'; +
+FDCPE_ROM_OE: FDCPE port map (ROM_OE,ROM_OE_D,ide/ide_CLKF,'0','0'); +
     ROM_OE_D <= (RESET AND RW AND NOT AS AND IDE_ENABLE AND ide); +
+FDCPE_SHUT_UP1: FDCPE port map (SHUT_UP(1),SHUT_UP_D(1),ide/ide_CLKF,'0','0'); +
     SHUT_UP_D(1) <= ((RESET AND NOT SHUT_UP(1)) +
      OR (RESET AND NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND +
      A(6) AND A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND +
      NOT AUTO_CONFIG_DONE(1) AND autoconfig)); +
+FDCPE_autoconfig: FDCPE port map (autoconfig,autoconfig_D,ide/ide_CLKF,'0','0'); +
     autoconfig_D <= ((A(23) AND A(22) AND A(21) AND A(19) AND +
      NOT AUTO_CONFIG_DONE(0) AND BERR AND NOT A(17) AND NOT A(16) AND NOT A(20) AND NOT A(18)) +
      OR (A(23) AND A(22) AND A(21) AND A(19) AND +
      NOT AUTO_CONFIG_DONE(1) AND BERR AND NOT A(17) AND NOT A(16) AND NOT A(20) AND NOT A(18)) +
      OR (A(23) AND A(22) AND A(21) AND A(19) AND +
      NOT AUTO_CONFIG_DONE(2) AND BERR AND NOT A(17) AND NOT A(16) AND NOT A(20) AND NOT A(18))); +
+FDCPE_ide: FDCPE port map (ide,ide_D,ide/ide_CLKF,'0','0'); +
     ide_D <= ((SHUT_UP(1)) +
      OR (NOT BERR) +
      OR (EXP20_.EXP) +
      OR (A(23) AND NOT IDE_BASEADR(7)) +
      OR (NOT A(23) AND IDE_BASEADR(7)) +
      OR (A(22) AND NOT IDE_BASEADR(6)) +
      OR (NOT A(22) AND IDE_BASEADR(6)) +
      OR (IDE_BASEADR(1) AND NOT A(17)) +
      OR (autoconfig.EXP) +
      OR (IDE_BASEADR(0) AND NOT A(16)) +
      OR (NOT IDE_BASEADR(0) AND A(16)) +
      OR (NOT IDE_BASEADR(1) AND A(17)) +
      OR (IDE_BASEADR(2) AND NOT A(18)) +
      OR (NOT IDE_BASEADR(2) AND A(18)) +
      OR (A(19) AND NOT IDE_BASEADR(3)) +
      OR (NOT A(19) AND IDE_BASEADR(3))); +
+
+ide/ide_CLKF <= NOT (C3 +
      XOR +
     ide/ide_CLKF <= NOT (C1); +
+Register Legend: +
      FDCPE (Q,D,C,CLR,PRE,CE); +
      FTCPE (Q,D,C,CLR,PRE,CE); +
      LDCP (Q,D,G,CLR,PRE); +
+
+
+ + +
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"; +var tabStr = spcStr + spcStr + spcStr + spcStr + spcStr; +var nlTabStr = nlStr + tabStr; +var rClrS = ""; +var rClrE = ""; +var cClrS = ""; +var cClrE = ""; + +var abelOper = new Array(); +abelOper["GND"] = new Array("Gnd"); +abelOper["VCC"] = new Array("Vcc"); +abelOper["NOT"] = new Array(rClrS + "!" + rClrE); +abelOper["AND"] = new Array(rClrS + "&" + rClrE); +abelOper["OR"] = new Array(rClrS + "#" + rClrE); +abelOper["XOR"] = new Array(rClrS + "$" + rClrE); +abelOper["EQUAL_COLON"] = new Array(":= "); +abelOper["EQUAL"] = new Array("= "); +abelOper["ASSIGN"] = new Array(""); +abelOper["OPEN_NEGATE"] = new Array("("); +abelOper["CLOSE_NEGATE"] = new Array(")"); +abelOper["OPEN_PTERM"] = new Array(""); +abelOper["CLOSE_PTERM"] = new Array(""); +abelOper["OPEN_BRACE"] = new Array("<"); +abelOper["CLOSE_BRACE"] = new Array(">"); +abelOper["INVALID_OPEN_BRACE"] = new Array("<"); +abelOper["INVALID_CLOSE_BRACE"] = new Array(">"); + +abelOper["ENDLN"] = new Array(";"); +abelOper["COMMENT"] = new Array("//"); +abelOper["IMPORT"] = new Array(";Imported pterms "); +abelOper["GCK_COM"] = new Array("GCK"); +abelOper["GTS_COM"] = new Array("GTS"); +abelOper["GSR_COM"] = new Array("GSR"); +abelOper["OD_COM"] = new Array("Open Drain"); +abelOper["START_EQN"] = new Array(""); +abelOper["END_EQN"] = new Array(""); + +abelOper["_I"] = new Array(".I"); +abelOper["_T"] = new Array(".T"); +abelOper["_D"] = new Array(".D"); +abelOper["_C"] = new Array(".CLK"); +abelOper["_DEC"] = new Array(".DEC"); +abelOper["_LH"] = new Array(".LH"); +abelOper["_CLR"] = new Array(".AR"); +abelOper["_PRE"] = new Array(".AP"); +abelOper["_CE"] = new Array(".CE"); +abelOper["_OE"] = new Array(".OE"); + +abelOper["OE_START"] = new Array(" <= "); +abelOper["OE_WHEN"] = new Array(" when "); +abelOper["OE_EQUAL"] = new Array(" = "); +abelOper["OE_ELSE"] = new Array(" else "); +abelOper["B0"] = new Array("'0'"); +abelOper["B1"] = new Array("'1'"); +abelOper["BZ"] = new Array("'Z'"); + +abelOper["FD"] = new Array(".D"); +abelOper["FT"] = new Array(".T"); +abelOper["FDD"] = new Array(".DEC"); +abelOper["FTD"] = new Array(".T"); +abelOper["LD"] = new Array(".LH"); +abelOper["Q"] = new Array(".Q"); + +var vhdlOper = new Array(); +vhdlOper["GND"] = new Array("'0'"); +vhdlOper["VCC"] = new Array("'1'"); +vhdlOper["NOT"] = new Array(rClrS + "NOT " + rClrE); +vhdlOper["AND"] = new Array(rClrS + "AND" + rClrE); +vhdlOper["OR"] = new Array(rClrS + "OR" + rClrE); +vhdlOper["XOR"] = new Array(rClrS + "XOR" + rClrE); +vhdlOper["EQUAL_COLON"] = new Array("<= "); +vhdlOper["EQUAL"] = new Array("<= "); +vhdlOper["ASSIGN"] = new Array(""); +vhdlOper["OPEN_NEGATE"] = new Array("("); +vhdlOper["CLOSE_NEGATE"] = new Array(")"); +vhdlOper["OPEN_PTERM"] = new Array("("); +vhdlOper["CLOSE_PTERM"] = new Array(")"); +vhdlOper["OPEN_BRACE"] = new Array("("); +vhdlOper["CLOSE_BRACE"] = new Array(")"); +vhdlOper["INVALID_OPEN_BRACE"] = new Array("<"); +vhdlOper["INVALID_CLOSE_BRACE"] = new Array(">"); + +vhdlOper["ENDLN"] = new Array(";"); +vhdlOper["COMMENT"] = new Array("--"); +vhdlOper["IMPORT"] = new Array(""); +vhdlOper["GCK_COM"] = new Array("GCK"); +vhdlOper["GTS_COM"] = new Array("GTS"); +vhdlOper["GSR_COM"] = new Array("GSR"); +vhdlOper["OD_COM"] = new Array("Open Drain"); +vhdlOper["START_EQN"] = new Array(rClrS + "port map" + rClrE + " ("); +vhdlOper["END_EQN"] = new Array(")"); + +vhdlOper["_I"] = new Array("_I"); +vhdlOper["_T"] = new Array("_T"); +vhdlOper["_D"] = new Array("_D"); +vhdlOper["_C"] = new Array("_C"); +vhdlOper["_DEC"] = new Array("_C"); +vhdlOper["_LH"] = new Array("_C"); +vhdlOper["_CLR"] = new Array("_CLR"); +vhdlOper["_PRE"] = new Array("_PRE"); +vhdlOper["_CE"] = new Array("_CE"); +vhdlOper["_OE"] = new Array("_OE"); + +vhdlOper["OE_START"] = new Array(" <= "); +vhdlOper["OE_WHEN"] = new Array(" when "); +vhdlOper["OE_EQUAL"] = new Array(" = "); +vhdlOper["OE_ELSE"] = new Array(" else "); +vhdlOper["B0"] = new Array("'0'"); +vhdlOper["B1"] = new Array("'1'"); +vhdlOper["BZ"] = new Array("'Z'"); + +vhdlOper["FD"] = new Array("FDCPE"); +vhdlOper["FT"] = new Array("FTCPE"); +vhdlOper["FDD"] = new Array("FDDCPE"); +vhdlOper["FTD"] = new Array("FTDCPE"); +vhdlOper["LD"] = new Array("LDCP"); +vhdlOper["Q"] = new Array(""); + +var verOper = new Array(); +verOper["GND"] = new Array("1'b0"); +verOper["VCC"] = new Array("1'b1"); +verOper["NOT"] = new Array(rClrS + "!" + rClrE); +verOper["AND"] = new Array(rClrS + "&&" + rClrE); +verOper["OR"] = new Array(rClrS + "||" + rClrE); +verOper["XOR"] = new Array(rClrS + "XOR" + rClrE); +verOper["EQUAL_COLON"] = new Array("= "); +verOper["EQUAL"] = new Array("= "); +verOper["ASSIGN"] = new Array("assign "); +verOper["OPEN_NEGATE"] = new Array("("); +verOper["CLOSE_NEGATE"] = new Array(")"); +verOper["OPEN_PTERM"] = new Array("("); +verOper["CLOSE_PTERM"] = new Array(")"); +verOper["OPEN_BRACE"] = new Array("["); +verOper["CLOSE_BRACE"] = new Array("]"); +verOper["INVALID_OPEN_BRACE"] = new Array("<"); +verOper["INVALID_CLOSE_BRACE"] = new Array(">"); + +verOper["ENDLN"] = new Array(";"); +verOper["COMMENT"] = new Array("//"); +verOper["IMPORT"] = new Array(""); +verOper["GCK_COM"] = new Array("GCK"); +verOper["GTS_COM"] = new Array("GTS"); +verOper["GSR_COM"] = new Array("GSR"); +verOper["OD_COM"] = new Array("Open Drain"); +verOper["START_EQN"] = new Array(" ("); +verOper["END_EQN"] = new Array(")"); + +verOper["_I"] = new Array("_I"); +verOper["_T"] = new Array("_T"); +verOper["_D"] = new Array("_D"); +verOper["_C"] = new Array("_C"); +verOper["_DEC"] = new Array("_C"); +verOper["_LH"] = new Array("_C"); +verOper["_CLR"] = new Array("_CLR"); +verOper["_PRE"] = new Array("_PRE"); +verOper["_CE"] = new Array("_CE"); +verOper["_OE"] = new Array("_OE"); + +verOper["OE_START"] = new Array(" = "); +verOper["OE_WHEN"] = new Array(" ? "); +verOper["OE_EQUAL"] = new Array(""); +verOper["OE_ELSE"] = new Array(" : "); +verOper["B0"] = new Array("1'b0"); +verOper["B1"] = new Array("1'b1"); +verOper["BZ"] = new Array("1'bz"); + +verOper["FD"] = new Array("FDCPE"); +verOper["FT"] = new Array("FTCPE"); +verOper["FDD"] = new Array("FDDCPE"); +verOper["FTD"] = new Array("FTDCPE"); +verOper["LD"] = new Array("LDCP"); +verOper["Q"] = new Array(""); + +var operator = abelOper; + +var pterms = new Array(); +var d1 = new Array(); +var d2 = new Array(); +var clk = new Array(); +var set = new Array(); +var rst = new Array(); +var trst = new Array(); +var d1imp = new Array(); +var d2imp = new Array(); +var clkimp = new Array(); +var setimp = new Array(); +var rstimp = new Array(); +var trstimp = new Array(); +var gblclk = new Array(); +var gblset = new Array(); +var gblrst = new Array(); +var gbltrst = new Array(); +var ce = new Array(); +var ceimp = new Array(); +var prld = new Array(); +var specSig = new Array(); +var clkNegs = new Array(); +var setNegs = new Array(); +var rstNegs = new Array(); +var trstNegs = new Array(); +var ceNegs = new Array(); +var fbnand = new Array(); +var inreg = new Array(); +var iostyle = new Array(); + +var dOneLit = true; + +function setOper(type) { + if (type == "1") { operator = vhdlOper; eqnType = 1; } + else if (type == "2") { operator = verOper; eqnType = 2; } + else { operator = abelOper; eqnType = 0; } +} + +function isXC95() { + if (device.indexOf("95") != -1) return true; + return false; +} + +function is9500() { + if ((device.indexOf("95") != -1) && + (device.indexOf("XL") == -1) && + (device.indexOf("XV") == -1)) return true; + return false; +} + +function retSigType(s) { + var sigType = sigTypes[s]; + var str = operator["Q"]; + if (sigType == "D") str = operator["FD"]; + else if (sigType == "T") str = operator["FT"]; + else if (sigType.indexOf("LATCH") != -1) str = operator["LD"]; + else if (sigType.indexOf("DDEFF") != -1) str = operator["FDD"]; + else if (sigType.indexOf("DEFF") != -1) str = operator["FD"]; + else if (sigType.indexOf("DDFF") != -1) str = operator["FDD"]; + else if (sigType.indexOf("TDFF") != -1) str = operator["FTD"]; + else if (sigType.indexOf("DFF") != -1) str = operator["FD"]; + else if (sigType.indexOf("TFF") != -1) str = operator["FT"]; + return str; +} + +function retSigIndex(signal) { + for (s=0; s 1) str += operator["OPEN_PTERM"]; + for (p=0; p0) str += " " + operator["AND"] + " "; + var neg = 0; + if (sig.indexOf("/") != -1) { + sig = sig.substring(1, sig.length); + str += operator["NOT"]; + neg = 1; + } + + str += retSigName(sig); + } + if (pterms[pt].length > 1) str += operator["CLOSE_PTERM"]; + + return str; +} + +function retFBMC(str) { + return str.substring(0,str.length-2) + nlStr + tabStr; +} + +function retD1D2(signal) { + var str = ""; + + dOneLit = true; + if (d1[signal]) { + var currImp = ""; + for (i=0; i0) str += nlTabStr + operator["OR"] + spcStr; + str += retPterm(d1[signal][i]); + } + + if (d2[signal]) str += nlTabStr + operator["XOR"]+ spcStr; + } + + if (d2[signal]) { + var currImp = ""; + for (i=0; i0) str += nlTabStr + operator["OR"] + spcStr; + str += retPterm(d2[signal][i]); + } + } + + if (str == "GND") str = operator["GND"]; + else if (str == "VCC") str = operator["VCC"]; + else if (!isOneLiteral(str)) { + dOneLit = false; + + var type = retSigType(retSigIndex(signal)); + if ((type == operator["FD"]) || + (type == operator["FDD"])) type = operator["_D"]; + else if ((type == operator["FT"]) || + (type == operator["FTD"])) type = operator["_T"]; + else if (type == operator["LD"] && eqnType) type = "_D"; + + var tmpStr = updateName(retSigName(signal), type); + tmpStr += spcStr + operator["EQUAL_COLON"]; + var idx = retSigIndex(signal); + if (eqnType && sigNegs[idx] == "ON") tmpStr += operator["NOT"] + operator["OPEN_NEGATE"]; + str = tmpStr + str; + if (eqnType && sigNegs[idx] == "ON") str += operator["CLOSE_NEGATE"]; + str += operator["ENDLN"]; + } + + return str; +} + +function retClk(signal) { + var str = ""; + + if (clk[signal]) { + if (clk[signal].length == 1) { + var pterm = retPterm(clk[signal][0]); + if (clkNegs[signal]) { + str += operator["NOT"]; + if (!isOneLiteral(pterm)) str += operator["OPEN_NEGATE"]; + } + str += pterm; + if (clkNegs[signal] && !isOneLiteral(pterm)) str += operator["CLOSE_NEGATE"]; + } + else { + if (clkNegs[signal]) str += operator["NOT"] + operator["OPEN_NEGATE"]; + var currImp = ""; + for (i=0; i0) str += nlTabStr + operator["OR"] + spcStr; + str += retPterm(clk[signal][i]); + } + if (clkNegs[signal]) str += operator["CLOSE_NEGATE"]; + str += operator["ENDLN"]; + } + } + else if (gblclk[signal]) { + if (gblclk[signal].length == 1) { + var pterm = retPterm(gblclk[signal][0]); + if (clkNegs[signal]) { + str += operator["NOT"]; + if (!isOneLiteral(pterm)) str += operator["OPEN_NEGATE"]; + } + str += pterm; + if (clkNegs[signal] && !isOneLiteral(pterm)) str += operator["CLOSE_NEGATE"]; + } + else { + if (clkNegs[signal]) str += operator["NOT"] + operator["OPEN_NEGATE"]; + for (i=0; i0) str += nlTabStr + operator["OR"] + spcStr; + str += retPterm(gblclk[signal][i]); + } + if (clkNegs[signal]) str += operator["CLOSE_NEGATE"]; + str += operator["ENDLN"] + tabStr + cClrS + + operator["COMMENT"] + spcStr + operator["GCK_COM"] + cClrE; + } + } + else if (eqnType) str += operator["B0"]; + + return str; +} + +function retRst(signal) { + var str = ""; + + if (rst[signal]) { + if (rst[signal].length == 1) { + var currImp; + if (!eqnType && rstimp[signal] && (rstimp[signal][0] == "1")) { + if ((currImp != retFBMC(rst[signal][i])) && + (rst[signal][i].indexOf("FB") == 0)) { + currImp = retFBMC(rst[signal][0]); + str += nlStr + operator["IMPORT"] + currImp; + } + } + if (rstNegs[signal]) str += operator["NOT"]; + str += retPterm(rst[signal][0]); + } + else { + var currImp = ""; + if (rstNegs[signal]) str += operator["NOT"] + operator["OPEN_NEGATE"]; + for (i=0; i0) str += nlTabStr + operator["OR"] + spcStr; + str += retPterm(rst[signal][i]); + } + if (rstNegs[signal]) str += operator["CLOSE_NEGATE"]; + str += operator["ENDLN"]; + } + } + else if (gblrst[signal]) { + if (gblrst[signal].length == 1) { + if (rstNegs[signal]) str += operator["NOT"]; + str += retPterm(gblrst[signal][0]); + } + else { + if (rstNegs[signal]) str += operator["NOT"] + operator["OPEN_NEGATE"]; + for (i=0; i0) str += nlTabStr + operator["OR"] + spcStr; + str += retPterm(gblrst[signal][i]); + } + if (rstNegs[signal]) str += operator["CLOSE_NEGATE"]; + str += operator["ENDLN"] + tabStr + cClrS + + operator["COMMENT"] + spcStr + operator["GSR_COM"] + cClrE; + } + } + else if (eqnType) str += operator["B0"]; + + return str; +} + +function retSet(signal) { + var str = ""; + + if (set[signal]) { + if (set[signal].length == 1) { + var currImp = ""; + if (!eqnType && setimp[signal] && (setimp[signal][0] == "1")) { + if ((currImp != retFBMC(set[signal][i])) && + (set[signal][i].indexOf("FB") == 0)) { + currImp = retFBMC(set[signal][0]); + str += nlStr + operator["IMPORT"] + currImp; + } + } + if (setNegs[signal]) str += operator["NOT"]; + str += retPterm(set[signal][0]); + } + else { + var currImp = ""; + if (setNegs[signal]) str += operator["NOT"] + operator["OPEN_NEGATE"]; + for (i=0; i0) str += nlTabStr + operator["OR"] + spcStr; + str += retPterm(set[signal][i]); + } + if (setNegs[signal]) str += operator["CLOSE_NEGATE"]; + str += operator["ENDLN"]; + } + } + else if (gblset[signal]) { + if (gblset[signal].length == 1) { + if (setNegs[signal]) str += operator["NOT"]; + str += retPterm(gblset[signal][0]); + } + else { + if (setNegs[signal]) str += operator["NOT"] + operator["OPEN_NEGATE"]; + for (i=0; i0) str += nlTabStr + operator["OR"] + spcStr; + str += retPterm(gblset[signal][i]); + } + if (setNegs[signal]) str += operator["CLOSE_NEGATE"]; + str += operator["ENDLN"] + tabStr + cClrS + + operator["COMMENT"] + spcStr + operator["GSR_COM"] + cClrE; + } + } + else if (eqnType) str += operator["B0"]; + + return str; +} + +function retCE(signal) { + var str = ""; + + if (ce[signal]) { + if (ce[signal].length == 1) { + var currImp = ""; + if (!eqnType && ceimp[signal] && (ceimp[signal][0] == "1")) { + if ((currImp != retFBMC(ce[signal][i])) && + (ce[signal][i].indexOf("FB") == 0)) { + currImp = retFBMC(ce[signal][0]); + str += nlStr + operator["IMPORT"] + currImp; + } + } + if (ceNegs[signal]) str += operator["NOT"]; + str += retPterm(ce[signal][0]); + } + else { + var currImp = ""; + if (ceNegs[signal]) str += operator["NOT"] + operator["OPEN_NEGATE"]; + for (i=0; i0) str += nlTabStr + operator["OR"] + spcStr; + str += retPterm(ce[signal][i]); + } + if (ceNegs[signal]) str += operator["CLOSE_NEGATE"]; + str += operator["ENDLN"]; + } + } + else if (eqnType) str += operator["B1"]; + + return str; +} + +function retTrst(signal) { + var str = ""; + if (trst[signal]) { + if (trstNegs[signal]) + str += operator["NOT"] + operator["OPEN_NEGATE"]; + for (i=0; i0) str += nlTabStr + operator["OR"] + spcStr; + str += retPterm(trst[signal][i]); + } + if (trstNegs[signal]) str += operator["CLOSE_NEGATE"]; + } + else if (gbltrst[signal]) { + if (trstNegs[signal]) + str += operator["NOT"] + operator["OPEN_NEGATE"]; + for (i=0; i0) str += nlTabStr + operator["OR"] + spcStr; + str += retPterm(gbltrst[signal][i]); + } + if (trstNegs[signal]) str += operator["CLOSE_NEGATE"]; + } + + str += operator["ENDLN"]; + return str; +} + +function retEqn(signal) { + var str = inregStr = ""; + var iStr = qStr = ""; + var dStr = dEqn = ""; + var cStr = cEqn = ""; + var clrStr = clrEqn = ""; + var preStr = preEqn = ""; + var ceStr = ceEqn = ""; + var oeStr = oeEqn = ""; + var sigName = retSigName(signal); + + var type = retSigType(retSigIndex(signal)); + + if (gbltrst[signal] || trst[signal]) iStr = operator["_I"]; + if (eqnType) qStr = updateName(sigName, iStr); + + if (inreg[signal]) { + if (!eqnType) + inregStr = operator["COMMENT"] + " Direct Input Register" + nlStr; + dStr = retSigName(inreg[signal][0]); + } + else dStr = retD1D2(signal); + if (eqnType && !dOneLit) { + dEqn = dStr; + dStr = dStr.substring(0,dStr.indexOf(operator["EQUAL_COLON"])); + } + else if (!eqnType) { + if (!dOneLit) dStr = dStr.substring(dStr.indexOf(operator["EQUAL_COLON"])+2); + if (sigNegs[retSigIndex(signal)] == "ON") dEqn += operator["NOT"]; + dEqn += sigName; + if ((type == operator["FT"]) || + (type == operator["FTD"])) dEqn += operator["_T"]; + else if ((type == operator["FD"]) || + (type == operator["FTD"])|| + (type == operator["LD"])) dEqn += operator["_D"]; + dEqn += " "; + if ((type != operator["Q"]) && (type != operator["LD"])) + dEqn += operator["EQUAL_COLON"]; + else dEqn += operator["EQUAL"]; + dEqn += dStr; + if (dOneLit) { + dEqn += operator["ENDLN"]; + if (iostyle[signal] && iostyle[signal].indexOf("OD")) + dEqn += tabStr + operator["COMMENT"] + " " + operator["OD_COM"]; + } + } + + cStr = retClk(signal); + if (eqnType && !isOneLiteral(cStr)){ + cEqn = cStr; + if (cEqn.indexOf(operator["ENDLN"]) == -1) + cEqn += operator["ENDLN"]; + cStr = updateName(sigName, operator["_C"]); + } + else if (!eqnType && cStr) { + cEqn += cStr; + cStr = tabStr + sigName; + if (type == operator["LD"]) cStr += operator["_LH"]; + else if (type == operator["FDD"]) cStr += operator["_DEC"]; + else cStr += operator["_C"]; + if (cEqn.indexOf(operator["ENDLN"]) == -1) + cEqn += operator["ENDLN"]; + if (gblclk[signal]) cEqn += tabStr + operator["COMMENT"] + " " + operator["GCK_COM"]; + } + + clrStr = retRst(signal); + if (eqnType && !isOneLiteral(clrStr)){ + clrEqn = clrStr; + if (cEqn.indexOf(operator["ENDLN"]) == -1) + clrEqn += operator["ENDLN"]; + clrStr = updateName(sigName, operator["_CLR"]); + } + else if (!eqnType && clrStr) { + clrEqn += clrStr; + clrStr = tabStr + sigName + operator["_CLR"]; + if (clrEqn.indexOf(operator["ENDLN"]) == -1) + clrEqn += operator["ENDLN"]; + if (gblrst[signal]) clrEqn += tabStr + operator["COMMENT"] + " " + operator["GSR_COM"]; + } + + preStr = retSet(signal); + if (eqnType && !isOneLiteral(preStr)){ + preEqn = preStr; + if (cEqn.indexOf(operator["ENDLN"]) == -1) + preEqn += operator["ENDLN"]; + preStr = updateName(sigName, operator["_PRE"]); + } + else if (!eqnType && preStr) { + preEqn += preStr; + preStr = tabStr + sigName + operator["_PRE"]; + if (preEqn.indexOf(operator["ENDLN"]) == -1) + preEqn += operator["ENDLN"]; + if (gblset[signal]) preEqn += tabStr + operator["COMMENT"] + " " + operator["GSR_COM"]; + } + + if (!is9500()) { + ceStr = retCE(signal); + if (eqnType && !isOneLiteral(ceStr)){ + ceEqn = ceStr; + if (cEqn.indexOf(operator["ENDLN"]) == -1) + ceEqn += operator["ENDLN"]; + ceStr = updateName(sigName, operator["_CE"]); + } + else if (!eqnType && ceStr) { + ceEqn += ceStr; + ceStr = tabStr + sigName + operator["_CE"]; + if (ceEqn.indexOf(operator["ENDLN"]) == -1) + ceEqn += operator["ENDLN"]; + } + } + + if (eqnType && gbltrst[signal]) oeEqn = retTrst(signal); + else if (!eqnType && (trst[signal] || gbltrst[signal])) oeEqn = retTrst(signal); + + var newline = false; + if ((type == "") && (clrStr == "")) { + str += operator["ASSIGN"] + qStr + " " + operator["EQUAL"]; + if (dOneLit) str += dStr; + else str += dEqn.substring(dEqn.indexOf(operator["EQUAL"])+2); + if (oeEqn != "") { + var oeStr = updateName(sigName, operator["_OE"]); + if (eqnType == 1) { + str += nlStr + sigName + operator["OE_START"] + qStr + operator["OE_WHEN"] + oeStr + + operator["OE_EQUAL"] + operator["B1"] + operator["OE_ELSE"] + + operator["OE_EQUAL"] + operator["BZ"] + operator["ENDLN"]; + } + else if (eqnType == 2) { + str += nlStr + operator["ASSIGN"] + sigName + operator["OE_START"] + + oeStr + operator["OE_WHEN"] + qStr + + operator["OE_ELSE"] + operator["BZ"] + operator["ENDLN"]; + } + str += nlStr + operator["ASSIGN"] + oeStr + " " + operator["EQUAL"] + " " + oeEqn; + } + } + else { + if (eqnType == 1) { + str += type + "_" + removePar(retSigName(signal)) + + ": " + type + " " + operator["START_EQN"] + + qStr + ", " + dStr + ", " + cStr + ", " + + clrStr + ", " + preStr; + if (!is9500() && (type != operator["LD"])) str += ", " + ceStr; + str += operator["END_EQN"] + operator["ENDLN"]; + newline = true; + } + else if (eqnType == 2) { + str += type + " " + + type + "_" + removePar(retSigName(signal)) + + operator["START_EQN"] + + qStr + ", " + dStr + ", " + cStr + ", " + + clrStr + ", " + preStr; + if (!is9500() && (type != operator["LD"])) str += ", " + ceStr; + str += operator["END_EQN"] + operator["ENDLN"]; + newline = true; + } + + if (dEqn != "") { + if (newline) str += nlStr; + if (inregStr) str += inregStr; + str += operator["ASSIGN"] + dEqn; + } + + if (cEqn != "") { + if (newline || !eqnType) str += nlStr; + str += operator["ASSIGN"] + cStr + " " + operator["EQUAL"] + " " + cEqn; + } + + if (clrEqn != "") { + if (newline || !eqnType) str += nlStr; + str += operator["ASSIGN"] + clrStr + " " + operator["EQUAL"] + " " + clrEqn; + } + + + if (preEqn != "") { + if (newline || !eqnType) str += nlStr; + str += operator["ASSIGN"] + preStr + " " + operator["EQUAL"] + " " + preEqn; + } + + if (ceEqn != "") { + if (newline || !eqnType) str += nlStr; + str += operator["ASSIGN"] + ceStr + " " + operator["EQUAL"] + " " + ceEqn; + } + + if (oeEqn != "") { + if (eqnType == 1) { + // var oeStr = updateName(sigName, operator["_OE"]); + var oeStr = sigName; + str += nlStr + sigName + operator["OE_START"] + qStr + operator["OE_WHEN"] + oeStr + + operator["OE_EQUAL"] + operator["B1"] + operator["OE_ELSE"] + + operator["OE_EQUAL"] + operator["BZ"] + operator["ENDLN"]; + // str += nlStr + oeStr + " " + operator["EQUAL"] + " " + oeEqn; + } + else if (eqnType == 2) { + // var oeStr = updateName(sigName, operator["_OE"]); + var oeStr = sigName; + str += nlStr + operator["ASSIGN"] + sigName + operator["OE_START"] + oeStr + operator["OE_WHEN"] + qStr + + operator["OE_ELSE"] + operator["BZ"] + operator["ENDLN"]; + // str += nlStr + operator["ASSIGN"] + oeStr + " " + operator["EQUAL"] + " " + oeEqn; + } + else { + var oeStr = sigName + operator["_OE"]; + if (gbltrst[signal]) + oeEqn += tabStr + operator["COMMENT"] + " " + operator["GTS_COM"]; + str += nlStr + tabStr + oeStr + " " + operator["EQUAL"] + " " + oeEqn; + } + } + } + + if (iostyle[signal] && iostyle[signal].indexOf("OD")) { + if (str.indexOf("//") == -1) + str += tabStr + operator["COMMENT"] + " " + operator["OD_COM"]; + } + + return str; +} + +function retFamily() { + var family = "xc9500"; + if (device.indexOf("XC2C") != -1) { + if (device.indexOf("S") != -1) family = "cr2s"; + else family = "xbr"; + } + else if (device.indexOf("XCR3") != -1) family = "xpla3"; + else { + if (device.indexOf("XL") != -1) family = "xc9500xl"; + if (device.indexOf("XV") != -1) family = "xc9500xv"; + } + + return family; +} + +function retDesign() { return design; } + +function getPterm(pt, type) { + if (type) return type + " = " + retPterm(pt); + return "PT" + pt.substring(pt.indexOf('_')+1,pt.length) + " = " + retPterm(pt); +} + +function getPRLDName(prld) { + if (eqnType != 0) return prld; + else if (prld == "VCC") return "S"; + return "R"; +} + +function retFbnand(signal) { + var str = operator["COMMENT"] + spcStr + "Foldback NAND"; + str += nlStr + retSigName(signal) + spcStr + operator["EQUAL"] + spcStr; + for (i=0; i0) str += nlTabStr + operator["OR"] + spcStr; + str += retPterm(fbnand[signal][i]); + } + + return str; +} + +function getEqn(signal) { return retEqn(signal); } + +function retUimPterm(pt) { + var str = ""; + if (!uimPterms[pt]) return pt; + for (p=0; p0) str += spcStr + operator["AND"] + spcStr; + var sig = uimPterms[pt][p]; + if (sig.indexOf("/") != -1) sig = sig.substring(1, sig.length); + + str += retSigName(sig); + } + return str; +} + +function retUimEqn(signal) { + var str = operator["COMMENT"] + spcStr + "FC Node" + nlStr; + var neg = 0; + if (uimSigNegs[s] == "ON") str += operator["NOT"]; + str += retSigName(signal) + spcStr + operator["EQUAL"]; + str += retUimPterm(signal) + ";"; + + return str; +} + +function retLegend(url) { + var str = ""; + if (!eqnType && !isXC95()) { + str = "Legend: " + "<" + "signame" + ">" + ".COMB = combinational node mapped to "; + str += "the same physical macrocell as the FastInput \"signal\" (not logically related)"; + } + else if (eqnType) { + str = "Register Legend:"; + if (is9500()) { + str += nlTabStr + "FDCPE (Q,D,C,CLR,PRE);"; + str += nlTabStr + "FTCPE (Q,D,C,CLR,PRE);"; + str += nlTabStr + "LDCP (Q,D,G,CLR,PRE);"; + } + else if (retFamily() == "xbr") { + str += nlTabStr + "FDCPE (Q,D,C,CLR,PRE,CE);"; + str += nlTabStr + "FDDCPE (Q,D,C,CLR,PRE,CE);"; + str += nlTabStr + "FTCPE (Q,D,C,CLR,PRE,CE);"; + str += nlTabStr + "FTDCPE (Q,D,C,CLR,PRE,CE);"; + str += nlTabStr + "LDCP (Q,D,G,CLR,PRE);"; + } + else { + str += nlTabStr + "FDCPE (Q,D,C,CLR,PRE,CE);"; + str += nlTabStr + "FTCPE (Q,D,C,CLR,PRE,CE);"; + str += nlTabStr + "LDCP (Q,D,G,CLR,PRE);"; + } + } + return str; +} + diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/equations.gif b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/equations.gif new file mode 100644 index 0000000000000000000000000000000000000000..d81602dcda8c50e3a304aa4aa7320bba1e499b88 GIT binary patch literal 20290 zcmX7OWl$T=*L8{&cef(J-Mz&jxCM775Q-OXakn7FT>}&kQlPlILvSlzC@lpld4B)* z-48oEvomMzJ?Gq+y*pP8q$(+4*9jIxa5hx%M07Qa;NH`FQ`Y$>l3JgTSfhg4f!UTXp05}MM0s#RaAQ%LM zgMcUy2mk_sK_EB?gaSbUASf6Fg@d3d5DWlRQb zL!l@r3;>0Jp)fcUhJqphPy`r?fI|@|C=vigf}uz_6p8weMJNgkMZuvc)c@!NfMEbQ z41j_G0WcsK286?aC>RI;1A$>6I1Ge>K>;u*7zTyIpePs&0E2;HFgOf`f*}Af1Q>>Z z!w@JK5&%PjVMsU(iTY0&7zzwS!C@%W|0Du{5db&>fI0`1PFitfe|1$ z0)#?90SG7<0fi%=CI1-8a&p}8O7>R--QK?a`;QzVmKQp0#U=$Gk zp9B6A9t8rUK=A+6`cEVj6pVtx|6}$)LQya<3I_j=h5wRAA;2gE{J)6*3lxO}qmc0b z(EkHPp};5<{J#_P6UP6m0p9=Z|Emdk?Eh|Y=+&D`2cxjbxGg7|%ZB5KSv4Fv>$FFc zC`IhIYg<^y(-@T^>A6~glbP&><(74=PAb^|ezaV!%wsJ8^V=S+x=d%aBI>YKj09iT zxgu3H4fFg~ZJ>m-2%?)S;ld~%oMfG1M&hcKCc+ncod~X6{X{#Sy2HK3v085I9qg}Z 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a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/equationsdoc.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/equationsdoc.htm new file mode 100644 index 0000000..e335b77 --- /dev/null +++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/equationsdoc.htm @@ -0,0 +1,53 @@ + + + + + + + + + + +Equations + + + + + + + + + + + + + + + + + + + + + + +

Equations

+ +

The Equations + page provides a list of equations organized by signal name.  You + can use the pulldown menu in the left-hand frame of the page to select + ABEL, VHDL, or Verilog as your language of display.

+ +

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Errors/Warnings

+ +

The Errors/Warnings + section of the report lists all of the error, warning, and information + messages generated by the fitter. By default, this section will display + the number of each kind of message you have and the full text of the messages, + but checkboxes at the top of the screen allow you to filter message details + as you choose.

+ +

Checking all + the boxes will give you a display like this:

+ +

+ +

Deselecting + the Warning box in this particular example would result in this less detailed + display:

+ +

+ + + + diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/errs.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/errs.htm new file mode 100644 index 0000000..0fb2572 --- /dev/null +++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/errs.htm @@ -0,0 +1,81 @@ + + + + + + +

Errors and Warnings

+There are 0 error(s), 67 warning(s), and 0 information.

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
[Warning]:Cpld - Unable to retrieve the path to the iSE Project Repository. Will use the default filename of 'LAN_IDE_CP.ise'.INFO:Cpld - Inferring BUFG constraint for signal 'CLK_EXT' based upon the LOC constraint 'P30'. It is recommended that you declare this BUFG explicitedly in your design. Note that for certain device families the output of a BUFG constraint can not drive a gated clock, and the BUFG constraint will be ignored.
[Warning]:Cpld:936 - The output buffer 'SLAVE_OBUF' is missing an input and will be deleted.
[Warning]:Cpld:936 - The output buffer 'OWN_OBUF' is missing an input and will be deleted.
[Warning]:Cpld:936 - The output buffer 'OVR_OBUF' is missing an input and will be deleted.
[Warning]:Cpld:936 - The output buffer 'MTACK_OBUF' is missing an input and will be deleted.
[Warning]:Cpld:936 - The output buffer 'LAN_WRH_OBUF' is missing an input and will be deleted.
[Warning]:Cpld:936 - The output buffer 'LAN_RD_OBUF' is missing an input and will be deleted.
[Warning]:Cpld:936 - The output buffer 'LAN_EN_OBUF' is missing an input and will be deleted.
[Warning]:Cpld:936 - The output buffer 'LAN_CS_OBUF' is missing an input and will be deleted.
[Warning]:Cpld:936 - The output buffer 'LAN_CFG<4>_OBUF' is missing an input and will be deleted.
[Warning]:Cpld:936 - The output buffer 'LAN_CFG<3>_OBUF' is missing an input and will be deleted.
[Warning]:Cpld:936 - The output buffer 'LAN_CFG<2>_OBUF' is missing an input and will be deleted.
[Warning]:Cpld:936 - The output buffer 'LAN_CFG<1>_OBUF' is missing an input and will be deleted.
[Warning]:Cpld:936 - The output buffer 'INT_OUT_OBUF' is missing an input and will be deleted.
[Warning]:Cpld:936 - The output buffer 'CP_WE_OBUF' is missing an input and will be deleted.
[Warning]:Cpld:936 - The output buffer 'CP_RD_OBUF' is missing an input and will be deleted.
[Warning]:Cpld:936 - The output buffer 'CP_CS_OBUF' is missing an input and will be deleted.
[Warning]:Cpld:936 - The output buffer 'CFOUT_OBUF' is missing an input and will be deleted.
[Warning]:Cpld:936 - The output buffer 'A_LAN<9>_OBUF' is missing an input and will be deleted.
[Warning]:Cpld:936 - The output buffer 'A_LAN<8>_OBUF' is missing an input and will be deleted.
[Warning]:Cpld:936 - The output buffer 'A_LAN<7>_OBUF' is missing an input and will be deleted.
[Warning]:Cpld:936 - The output buffer 'A_LAN<6>_OBUF' is missing an input and will be deleted.
[Warning]:Cpld:936 - The output buffer 'A_LAN<5>_OBUF' is missing an input and will be deleted.
[Warning]:Cpld:936 - The output buffer 'A_LAN<4>_OBUF' is missing an input and will be deleted.
[Warning]:Cpld:936 - The output buffer 'A_LAN<3>_OBUF' is missing an input and will be deleted.
[Warning]:Cpld:936 - The output buffer 'A_LAN<2>_OBUF' is missing an input and will be deleted.
[Warning]:Cpld:936 - The output buffer 'A_LAN<1>_OBUF' is missing an input and will be deleted.
[Warning]:Cpld:936 - The output buffer 'A_LAN<13>_OBUF' is missing an input and will be deleted.
[Warning]:Cpld:936 - The output buffer 'A_LAN<12>_OBUF' is missing an input and will be deleted.
[Warning]:Cpld:936 - The output buffer 'A_LAN<11>_OBUF' is missing an input and will be deleted.
[Warning]:Cpld:936 - The output buffer 'A_LAN<10>_OBUF' is missing an input and will be deleted.
[Warning]:Cpld:936 - The output buffer 'A_LAN<0>_OBUF' is missing an input and will be deleted.
[Warning]:Cpld:1007 - Removing unused input(s) 'A<14>'. The input(s) are unused after optimization. Please verify functionality via simulation.
[Warning]:Cpld:1007 - Removing unused input(s) 'A<15>'. The input(s) are unused after optimization. Please verify functionality via simulation.
[Warning]:Cpld:1007 - Removing unused input(s) 'A<7>'. The input(s) are unused after optimization. Please verify functionality via simulation.
[Warning]:Cpld:1007 - Removing unused input(s) 'A<8>'. The input(s) are unused after optimization. Please verify functionality via simulation.
[Warning]:Cpld:1007 - Removing unused input(s) 'CFIN'. The input(s) are unused after optimization. Please verify functionality via simulation.
[Warning]:Cpld:1007 - Removing unused input(s) 'CLK_EXT'. The input(s) are unused after optimization. Please verify functionality via simulation.
[Warning]:Cpld:1007 - Removing unused input(s) 'CP_IRQ'. The input(s) are unused after optimization. Please verify functionality via simulation.
[Warning]:Cpld:1007 - Removing unused input(s) 'DQ<0>'. The input(s) are unused after optimization. Please verify functionality via simulation.
[Warning]:Cpld:1007 - Removing unused input(s) 'DQ<10>'. The input(s) are unused after optimization. Please verify functionality via simulation.
[Warning]:Cpld:1007 - Removing unused input(s) 'DQ<11>'. The input(s) are unused after optimization. Please verify functionality via simulation.
[Warning]:Cpld:1007 - Removing unused input(s) 'DQ<12>'. The input(s) are unused after optimization. Please verify functionality via simulation.
[Warning]:Cpld:1007 - Removing unused input(s) 'DQ<13>'. The input(s) are unused after optimization. Please verify functionality via simulation.
[Warning]:Cpld:1007 - Removing unused input(s) 'DQ<14>'. The input(s) are unused after optimization. Please verify functionality via simulation.
[Warning]:Cpld:1007 - Removing unused input(s) 'DQ<15>'. The input(s) are unused after optimization. Please verify functionality via simulation.
[Warning]:Cpld:1007 - Removing unused input(s) 'DQ<1>'. The input(s) are unused after optimization. Please verify functionality via simulation.
[Warning]:Cpld:1007 - Removing unused input(s) 'DQ<2>'. The input(s) are unused after optimization. Please verify functionality via simulation.
[Warning]:Cpld:1007 - Removing unused input(s) 'DQ<3>'. The input(s) are unused after optimization. Please verify functionality via simulation.
[Warning]:Cpld:1007 - Removing unused input(s) 'DQ<4>'. The input(s) are unused after optimization. Please verify functionality via simulation.
[Warning]:Cpld:1007 - Removing unused input(s) 'DQ<5>'. The input(s) are unused after optimization. Please verify functionality via simulation.
[Warning]:Cpld:1007 - Removing unused input(s) 'DQ<6>'. The input(s) are unused after optimization. Please verify functionality via simulation.
[Warning]:Cpld:1007 - Removing unused input(s) 'DQ<7>'. The input(s) are unused after optimization. Please verify functionality via simulation.
[Warning]:Cpld:1007 - Removing unused input(s) 'DQ<8>'. The input(s) are unused after optimization. Please verify functionality via simulation.
[Warning]:Cpld:1007 - Removing unused input(s) 'DQ<9>'. The input(s) are unused after optimization. Please verify functionality via simulation.
[Warning]:Cpld:1007 - Removing unused input(s) 'DS0'. The input(s) are unused after optimization. Please verify functionality via simulation.
[Warning]:Cpld:1007 - Removing unused input(s) 'DS1'. The input(s) are unused after optimization. Please verify functionality via simulation.
[Warning]:Cpld:1007 - Removing unused input(s) 'FCS'. The input(s) are unused after optimization. Please verify functionality via simulation.
[Warning]:Cpld:1007 - Removing unused input(s) 'IDE_WAIT'. The input(s) are unused after optimization. Please verify functionality via simulation.
[Warning]:Cpld:1007 - Removing unused input(s) 'LAN_INT'. The input(s) are unused after optimization. Please verify functionality via simulation.
[Warning]:Cpld:1007 - Removing unused input(s) 'LDS'. The input(s) are unused after optimization. Please verify functionality via simulation.
[Warning]:Cpld:1007 - Removing unused input(s) 'MTCR'. The input(s) are unused after optimization. Please verify functionality via simulation.
[Warning]:Cpld:1007 - Removing unused input(s) 'Z3'. The input(s) are unused after optimization. Please verify functionality via simulation.
[Warning]:Cpld:896 - Unable to map all desired signals into function block, FB3, because too many function block product terms are required. Buffering output signal D<12> to allow all signals assigned to this function block to be placed.
[Warning]:Cpld:896 - Unable to map all desired signals into function block, FB3, because too many function block product terms are required. Buffering output signal D<14> to allow all signals assigned to this function block to be placed.
[Warning]:Cpld:896 - Unable to map all desired signals into function block, FB3, because too many function block product terms are required. Buffering output signal D<13> to allow all signals assigned to this function block to be placed.
[Warning]:Cpld:896 - Unable to map all desired signals into function block, FB3, because too many function block product terms are required. Buffering output signal D<15> to allow all signals assigned to this function block to be placed.
+ + +
+ + diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/failtable.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/failtable.htm new file mode 100644 index 0000000..ed152cf --- /dev/null +++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/failtable.htm @@ -0,0 +1,42 @@ + + + + + + +

Failure Table

+ + + + + + + + + + + + + + + +
Signal NameFB1FB2FB3FB4
Signal NameFB5FB6FB7FB8
+
+ + + + + + + + + + + +
Legend:
ce - signal clock enable cannot be placed
clk - signal clock cannot be placed
fbi - insufficient function block inputs available to place signal
io - insufficient I/O pins available to place output
loc - signal cannot be placed in this FB because it is assigned to a different FB
mc - insufficient macrocells available to place signal
oe - signal output enable cannot be placed
pt - insufficient product terms available to place signal
sr - signal set/reset cannot be placed
unk - unknown reason for failure - Please contact Xilinx Support
+ +
+ + +
+ diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/failtable.js b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/failtable.js new file mode 100644 index 0000000..045081f --- /dev/null +++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/failtable.js @@ -0,0 +1 @@ +function showFailTable() { parent.leftnav.showFailTable(); } diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/failtabledoc.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/failtabledoc.htm new file mode 100644 index 0000000..c95037a --- /dev/null +++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/failtabledoc.htm @@ -0,0 +1,95 @@ + + + + + + + + + + + + + + + + Failure Table + + + + + + + + + + + +

+Failure Table

+The +Failure Table section provides a table listing all logic failing to be +placed as well as the cause for failure to fit for each individual Function +Block. The user can use this table to determine primary cause of +failure and try to correct it. +
+
The +Failure Table contains the following:  +
    +
  • +The +signal name 
    • +
+ +
Note: +Clicking on the signal name will open a new window with the equations for +that signal. 
+ +
    +
  • +A +column for each Function Block in device, with reason for failure to fit +for each FB
    • + +
  • +A +legend at the bottom listing all possible reasons for failure
    • +
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Function Blocks

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Function BlockMacrocells Used/TotalFunction Block Inputs Used/TotalProduct Terms Used/TotalPins Used/Total
FB116 / 1824 / 5440 / 9013 / 15
FB211 / 1824 / 5456 / 904 / 15
FB312 / 1824 / 5425 / 9011 / 15
FB43 / 1824 / 5425 / 900 / 15
FB57 / 1823 / 5419 / 9010 / 14
FB61 / 1815 / 5414 / 900 / 13
FB71 / 180 / 540 / 908 / 15
FB80 / 180 / 540 / 908 / 15
+ + +
+ + diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/fbs.js b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/fbs.js new file mode 100644 index 0000000..8e97ea6 --- /dev/null +++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/fbs.js @@ -0,0 +1,9 @@ +function showFBApplet(fb) { parent.leftnav.showAppletFB(fb); } +function showFB(fb) { parent.leftnav.showFB(fb); } +function showMC(mc) { parent.leftnav.showAppletMC(mc); } +function showPT(pterm, type) { parent.leftnav.showPterm(pterm, type); } +function showPin(pin) { parent.leftnav.showAppletPin(pin); } +function showEqn(sig) { parent.leftnav.showEqn(sig); } +function showFBDetail(fb) { parent.leftnav.showFB(fb); } +function showLegend(url) { parent.leftnav.showLegend(url, 650, 350); } +function showTop() { parent.leftnav.showTop(); } diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/fbs_FB1.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/fbs_FB1.htm new file mode 100644 index 0000000..319a21e --- /dev/null +++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/fbs_FB1.htm @@ -0,0 +1,260 @@ + + + + + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Signal NameTotal Product TermsProduct TermsLocationPower ModePin NumberPinTypePin Use
IDE_CS<1>1 2_2 +MC1STD23I/OO
D<7>1 2_1  +MC2STD16I/OO
D<1>1 3_1  +MC3STD17I/OO
IDE_A<2>1 4_1 +MC4STD25I/OO
D<8>1 5_1  +MC5STD19I/OI/O
D<5>1 6_1  +MC6STD20I/OO
AUTOCONFIG_IN_PROGRESS2 7_1 7_2 +MC7STD (b)(b)
D<4>1 8_1  +MC8STD21I/OO
IDE_CS<0>1 9_1 +MC9STD22I/OO
IDE_ENABLE3 10_1 10_2 10_3 +MC10STD31I/O(b)
IDE_A<0>1 11_1 +MC11STD24I/OO
IDE_A<1>1 12_1 +MC12STD26I/OO
(unused)0 MC13  (b) 
IDE_R2 14_1 14_2 +MC14STD27I/OO
IDE_W2 15_1 15_2 +MC15STD28I/OO
ROM_OE2 15_3 16_1 +MC16STD35I/OO
(unused)0 MC17 30I/O/GCK1(b)
D<12>_BUFR19 16_2 16_3 16_4 16_5 17_1 17_2 17_3 17_4 17_5 18_1 18_2 18_3 18_4 18_5 1_1 1_2 1_3 1_4 1_5 +MC18STD (b)(b)
+
+
Signals Used By Logic in Function Block
    +
  1. AS
    2. +
  2. AUTOBOOT_OFF
    3. +
  3. AUTOCONFIG_IN_PROGRESS
    4. +
  4. AUTO_CONFIG_DONE<0>
    5. +
  5. AUTO_CONFIG_DONE<1>
    6. +
  6. AUTO_CONFIG_DONE<2>
    7. +
  7. A<12>
    8. +
  8. A<13>
    9. +
  9. A<1>
    10. +
  10. A<2>
    11. +
  11. A<3>
    12. +
  12. A<4>
    13. +
  13. A<5>
    14. +
  14. A<6>
    15. +
  15. D<12>
    16. +
  16. A<9>
    17. +
  17. A<10>
    18. +
  18. A<11>
    19. +
  19. IDE_ENABLE
    20. +
  20. RESET
    21. +
  21. RW
    22. +
  22. autoconfig
    23. +
  23. ide
    24. +
  24. ide/ide_CLKF
    25. +
+ + + +
 + +
+ + diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/fbs_FB2.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/fbs_FB2.htm new file mode 100644 index 0000000..ab9109a --- /dev/null +++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/fbs_FB2.htm @@ -0,0 +1,259 @@ + + + + + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Signal NameTotal Product TermsProduct TermsLocationPower ModePin NumberPinTypePin Use
D<14>_BUFR18 18_1 18_2 18_3 18_4 18_5 1_1 1_2 1_3 1_4 1_5 2_1 2_2 2_3 2_4 2_5 3_1 3_2 3_3 +MC1STD142I/O(b)
(unused)0 MC2 143I/O/GSRGSR/I
(unused)0 MC3  (b)(b)
(unused)0 MC4 4I/O 
D<0>1 5_1  +MC5STD2I/O/GTS3O
(unused)0 MC6 3I/O/GTS4 
(unused)0 MC7  (b) 
AUTO_CONFIG_DONE<2>2 8_1 8_2 +MC8STD5I/O/GTS1(b)
AUTO_CONFIG_DONE<0>2 9_1 9_2 +MC9STD6I/O/GTS2(b)
AUTO_CONFIG_DONE_CYCLE<2>3 10_1 10_2 10_3 +MC10STD7I/O(b)
AUTO_CONFIG_DONE_CYCLE<0>3 11_1 11_2 11_3 +MC11STD9I/O(b)
IDE_BASEADR<7>4 11_4 12_1 12_2 12_3 +MC12STD10I/O(b)
IDE_BASEADR<6>4 12_4 12_5 13_1 13_2 +MC13STD12I/O(b)
(unused)0 MC14 11I/O(b)
D<13>_BUFR17 13_3 13_4 13_5 14_1 14_2 14_3 14_4 14_5 15_1 15_2 15_3 15_4 15_5 16_2 16_3 16_4 16_5 +MC15STD13I/O(b)
D<6>1 16_1  +MC16STD14I/OO
D<3>1 17_1  +MC17STD15I/OO
(unused)0 MC18  (b)(b)
+
+
Signals Used By Logic in Function Block
    +
  1. AS
    2. +
  2. AUTOCONFIG_IN_PROGRESS
    3. +
  3. AUTO_CONFIG_DONE<0>
    4. +
  4. AUTO_CONFIG_DONE<1>
    5. +
  5. AUTO_CONFIG_DONE<2>
    6. +
  6. AUTO_CONFIG_DONE_CYCLE<0>
    7. +
  7. AUTO_CONFIG_DONE_CYCLE<2>
    8. +
  8. A<1>
    9. +
  9. A<2>
    10. +
  10. A<3>
    11. +
  11. A<4>
    12. +
  12. A<5>
    13. +
  13. A<6>
    14. +
  14. D<13>
    15. +
  15. D<14>
    16. +
  16. IDE_BASEADR<6>
    17. +
  17. IDE_BASEADR<7>
    18. +
  18. D<14>.PIN
    19. +
  19. D<15>.PIN
    20. +
  20. RESET
    21. +
  21. RW
    22. +
  22. UDS
    23. +
  23. autoconfig
    24. +
  24. ide/ide_CLKF
    25. +
+ + + +
+ +    + +
 + +
+ + diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/fbs_FB3.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/fbs_FB3.htm new file mode 100644 index 0000000..408e55f --- /dev/null +++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/fbs_FB3.htm @@ -0,0 +1,260 @@ + + + + + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Signal NameTotal Product TermsProduct TermsLocationPower ModePin NumberPinTypePin Use
D<2>1 1_1  +MC1STD39I/OO
(unused)0 MC2 32I/O/GCK2 
D<10>1 3_1  +MC3STD41I/OI/O
D<12>2 4_1 4_2 +MC4STD44I/OI/O
(unused)0 MC5 33I/O 
(unused)0 MC6 34I/O 
D<14>2 7_1 7_2 +MC7STD46I/OI/O
(unused)0 MC8 38I/O/GCK3 
D<9>1 9_1  +MC9STD40I/OI/O
D<15>2 10_1 10_2 +MC10STD48I/OI/O
D<11>1 11_1  +MC11STD43I/OI/O
D<13>2 12_1 12_2 +MC12STD45I/OI/O
(unused)0 MC13  (b) 
(unused)0 MC14 49I/OI
AUTO_CONFIG_DONE<1>2 15_1 15_2 +MC15STD50I/OI
AUTO_CONFIG_DONE_CYCLE<1>3 16_1 16_2 16_3 +MC16STD (b)(b)
IDE_BASEADR<3>4 17_1 17_2 17_3 17_4 +MC17STD51I/OI
IDE_BASEADR<2>4 18_1 18_2 18_3 18_4 +MC18STD (b)(b)
+
+
Signals Used By Logic in Function Block
    +
  1. AS
    2. +
  2. AUTOCONFIG_IN_PROGRESS
    3. +
  3. AUTO_CONFIG_DONE<0>
    4. +
  4. AUTO_CONFIG_DONE<1>
    5. +
  5. AUTO_CONFIG_DONE_CYCLE<1>
    6. +
  6. A<1>
    7. +
  7. A<2>
    8. +
  8. A<3>
    9. +
  9. A<4>
    10. +
  10. A<5>
    11. +
  11. A<6>
    12. +
  12. D<12>_BUFR
    13. +
  13. D<13>_BUFR
    14. +
  14. D<14>_BUFR
    15. +
  15. D<15>_BUFR
    16. +
  16. IDE_BASEADR<2>
    17. +
  17. IDE_BASEADR<3>
    18. +
  18. D<11>.PIN
    19. +
  19. D<10>.PIN
    20. +
  20. RESET
    21. +
  21. RW
    22. +
  22. UDS
    23. +
  23. autoconfig
    24. +
  24. ide/ide_CLKF
    25. +
+ + + +
+ +    + +
 + +
+ + diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/fbs_FB4.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/fbs_FB4.htm new file mode 100644 index 0000000..40a601f --- /dev/null +++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/fbs_FB4.htm @@ -0,0 +1,251 @@ + + + + + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Signal NameTotal Product TermsProduct TermsLocationPower ModePin NumberPinTypePin Use
ide19 17_5 18_1 18_2 18_3 18_4 18_5 1_1 1_2 1_3 1_4 1_5 2_1 2_2 2_3 2_4 2_5 3_1 3_2 3_3 +MC1STD118I/O(b)
(unused)0 MC2 126I/O(b)
(unused)0 MC3 133I/O(b)
(unused)0 MC4  (b) 
(unused)0 MC5 128I/O 
(unused)0 MC6 129I/O 
(unused)0 MC7  (b) 
(unused)0 MC8 130I/O 
(unused)0 MC9 131I/O 
(unused)0 MC10 135I/O 
(unused)0 MC11 132I/O 
(unused)0 MC12 134I/O 
(unused)0 MC13 137I/O 
(unused)0 MC14 136I/O 
(unused)0 MC15 138I/O 
ide/ide_CLKF2 16_1 16_2 +MC16STD139I/O(b)
autoconfig4 17_1 17_2 17_3 17_4 +MC17STD140I/O(b)
(unused)0 MC18  (b)(b)
+
+
Signals Used By Logic in Function Block
    +
  1. AUTO_CONFIG_DONE<0>
    2. +
  2. AUTO_CONFIG_DONE<1>
    3. +
  3. AUTO_CONFIG_DONE<2>
    4. +
  4. A<16>
    5. +
  5. A<17>
    6. +
  6. A<18>
    7. +
  7. A<19>
    8. +
  8. A<20>
    9. +
  9. A<21>
    10. +
  10. A<22>
    11. +
  11. A<23>
    12. +
  12. BERR
    13. +
  13. C1
    14. +
  14. C3
    15. +
  15. IDE_BASEADR<0>
    16. +
  16. IDE_BASEADR<1>
    17. +
  17. IDE_BASEADR<2>
    18. +
  18. IDE_BASEADR<3>
    19. +
  19. IDE_BASEADR<4>
    20. +
  20. IDE_BASEADR<5>
    21. +
  21. IDE_BASEADR<6>
    22. +
  22. IDE_BASEADR<7>
    23. +
  23. SHUT_UP<1>
    24. +
  24. ide/ide_CLKF
    25. +
+ + + +
+ +    + +
 + +
+ + diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/fbs_FB5.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/fbs_FB5.htm new file mode 100644 index 0000000..ddc400f --- /dev/null +++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/fbs_FB5.htm @@ -0,0 +1,254 @@ + + + + + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Signal NameTotal Product TermsProduct TermsLocationPower ModePin NumberPinTypePin Use
(unused)0 MC1  (b) 
(unused)0 MC2 52I/OI
(unused)0 MC3 59I/OI
(unused)0 MC4  (b) 
(unused)0 MC5 53I/O 
(unused)0 MC6 54I/OI
(unused)0 MC7 66I/O 
(unused)0 MC8 56I/O 
(unused)0 MC9 57I/OI
ROM_B<0>0  +MC10STD68I/OO
(unused)0 MC11 58I/OI
(unused)0 MC12 60I/OI
SHUT_UP<1>3 13_1 13_2 13_3 +MC13STD70I/O(b)
IDE_BASEADR<5>4 14_1 14_2 14_3 14_4 +MC14STD61I/OI
IDE_BASEADR<4>4 15_1 15_2 15_3 15_4 +MC15STD64I/OI
IDE_BASEADR<1>4 16_1 16_2 16_3 16_4 +MC16STD (b)(b)
ROM_B<1>0  +MC17STD69I/OO
IDE_BASEADR<0>4 18_1 18_2 18_3 18_4 +MC18STD (b)(b)
+
+
Signals Used By Logic in Function Block
    +
  1. AS
    2. +
  2. AUTO_CONFIG_DONE<0>
    3. +
  3. AUTO_CONFIG_DONE<1>
    4. +
  4. A<1>
    5. +
  5. A<2>
    6. +
  6. A<3>
    7. +
  7. A<4>
    8. +
  8. A<5>
    9. +
  9. A<6>
    10. +
  10. IDE_BASEADR<0>
    11. +
  11. IDE_BASEADR<1>
    12. +
  12. IDE_BASEADR<4>
    13. +
  13. IDE_BASEADR<5>
    14. +
  14. D<12>.PIN
    15. +
  15. D<13>.PIN
    16. +
  16. D<8>.PIN
    17. +
  17. D<9>.PIN
    18. +
  18. RESET
    19. +
  19. RW
    20. +
  20. SHUT_UP<1>
    21. +
  21. UDS
    22. +
  22. autoconfig
    23. +
  23. ide/ide_CLKF
    24. +
+ + + +
+ +    + +
 + +
+ + diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/fbs_FB6.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/fbs_FB6.htm new file mode 100644 index 0000000..96b5d7c --- /dev/null +++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/fbs_FB6.htm @@ -0,0 +1,240 @@ + + + + + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Signal NameTotal Product TermsProduct TermsLocationPower ModePin NumberPinTypePin Use
(unused)0 MC1  (b) 
(unused)0 MC2 106I/O 
(unused)0 MC3  (b) 
(unused)0 MC4 111I/O 
(unused)0 MC5 110I/O 
(unused)0 MC6 112I/O 
(unused)0 MC7  (b) 
(unused)0 MC8 113I/O 
(unused)0 MC9 116I/O 
(unused)0 MC10 115I/O 
(unused)0 MC11 119I/O 
(unused)0 MC12 120I/O 
(unused)0 MC13  (b) 
(unused)0 MC14 121I/O 
(unused)0 MC15 124I/O 
(unused)0 MC16 117I/O(b)
D<15>_BUFR14 16_1 16_2 16_3 16_4 17_1 17_2 17_3 17_4 17_5 18_1 18_2 18_3 18_4 18_5 +MC17STD125I/O(b)
(unused)0 MC18  (b)(b)
+
+
Signals Used By Logic in Function Block
    +
  1. AS
    2. +
  2. AUTO_CONFIG_DONE<0>
    3. +
  3. AUTO_CONFIG_DONE<1>
    4. +
  4. AUTO_CONFIG_DONE<2>
    5. +
  5. A<1>
    6. +
  6. A<2>
    7. +
  7. A<3>
    8. +
  8. A<4>
    9. +
  9. A<5>
    10. +
  10. A<6>
    11. +
  11. D<15>
    12. +
  12. RESET
    13. +
  13. RW
    14. +
  14. autoconfig
    15. +
  15. ide/ide_CLKF
    16. +
+ + + +
+ +    + +
 + +
+ + diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/fbs_FB7.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/fbs_FB7.htm new file mode 100644 index 0000000..497cf70 --- /dev/null +++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/fbs_FB7.htm @@ -0,0 +1,224 @@ + + + + + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Signal NameTotal Product TermsProduct TermsLocationPower ModePin NumberPinTypePin Use
(unused)0 MC1  (b) 
(unused)0 MC2 71I/O 
(unused)0 MC3 75I/OI
(unused)0 MC4  (b) 
(unused)0 MC5 74I/O 
(unused)0 MC6 76I/O 
(unused)0 MC7 77I/O 
(unused)0 MC8 78I/O 
(unused)0 MC9 80I/OI
(unused)0 MC10 79I/O 
(unused)0 MC11 82I/O 
DTACK0   +MC12STD85I/OO
(unused)0 MC13 81I/OI
(unused)0 MC14 86I/OI
(unused)0 MC15 87I/OI
(unused)0 MC16 83I/OI
(unused)0 MC17 88I/OI
(unused)0 MC18  (b) 
+
+
Signals Used By Logic in Function Block
    + + + +
    + +    + +
    		 + +
    + + diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/fbs_FB8.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/fbs_FB8.htm new file mode 100644 index 0000000..ec5fac6 --- /dev/null +++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/fbs_FB8.htm @@ -0,0 +1,219 @@ + + + + + + + + + + +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    Signal NameTotal Product TermsProduct TermsLocationPower ModePin NumberPinTypePin Use
    (unused)0 MC1  (b) 
    (unused)0 MC2 91I/OI
    (unused)0 MC3 95I/OI
    (unused)0 MC4 97I/OI
    (unused)0 MC5 92I/OI
    (unused)0 MC6 93I/O 
    (unused)0 MC7  (b) 
    (unused)0 MC8 94I/OI
    (unused)0 MC9 96I/O 
    (unused)0 MC10 101I/O 
    (unused)0 MC11 98I/OI
    (unused)0 MC12 100I/O 
    (unused)0 MC13 103I/OI
    (unused)0 MC14 102I/OI
    (unused)0 MC15 104I/O 
    (unused)0 MC16 107I/O 
    (unused)0 MC17 105I/O 
    (unused)0 MC18  (b) 
    +
    +
    Signals Used By Logic in Function Block
      + + + +
      		 + +
      + + diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/fbs_FBdoc.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/fbs_FBdoc.htm new file mode 100644 index 0000000..36e7c96 --- /dev/null +++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/fbs_FBdoc.htm @@ -0,0 +1,310 @@ + + + + + + + + + + + + + + + Function Block Specifics + + + + + + + + + + + +

      +Function Block Specifics

      + +
      To access specific details for a particular function +block, click on that function block in either the Mapped +Logic, Mapped Inputs, or Function +Blocks sections of the fitter report. The +function block details page displays a table of details about the particular +function block you selected, a view button you can click to show a graphical +display of the function block, and a pulldown menu you can use to select +other function blocks to see.
      + + +

      The Table + +

      The View +

      + +

      +The Table

      +The +table at the top of the function block details page provides the following +information about the function block: +
        +
      • +The +signal name 
        • +
      + +
      Note: +Clicking on a signal name will open a new window with the equations for +that signal. 
      + +
        +
      • +The +total product terms used 
        • + +
      • + A +list of product terms
        • +
      + +
      Note: +Clicking on a product +term will open a new window with the equations for that term. 
      + +
        +
      • +The +macrocell number in which the function block is located
        • +
      + +
      Note: +Clicking on the underscored macrocell number will provide a graphical display +of the macrocell that looks like this:
      + + +

      +. +

        +
      • +The +power mode
        • + +
      • +The +pin number - an asterisk "*" indicates a user assignment
        • +
      + +
        +
        Note: +Clicking on the underscored pin number will provide the pin layout diagram +for the highlighted pin. Rolling +your mouse over the colored pin will pop up a tooltip with the signal name +assigned to the pin, the I/O standard, the +I/O style, the slew rate, and/or any constraints assigned to the pin:
        +
      + +
      +
      + +
        +
      • +The +pin type
        • + +
      • +The +pin use 
        • + +
      • +XPLA3 +only - The GCK (Global Clock Signal) mapping 
        • +
      + +
      Note: +Moving your mouse cursor over an "I" in the Pin Use column will display +that input signal as a tooltip.
      + +
      +
      XBR +only - Below the resource table there is another table listing the +Function Block Control Term usage, the product term mapped to the +control term is listed. Clicking on the product term will bring up a pop-up +window displaying that product term. +
      +
    1. +CTC - control term clock
      2. + +
    2. +CTR - control term reset
      3. + +
    3. +CTS - control term set
      4. + +
    4. +CTE - control term output enable
      5. +
      + +


      Below +this table you will find a list of signals used by logic in the function +block you are viewing. The +list displays output signals as links. Clicking +on an output signal link will open a new window showing the equations for +that signal. +
      + +

      Note:There +is also a  +button +below the table. Click +this button to open a new window describing all of the acronyms used in +the function block table. You +can select either brief descriptions or more detailed descriptions by clicking +the "Verbose" button at the top of the window. +

      +The View

      + +
      When you click on the  +button +above the table, a new window will open with a graphical display of the +function block you are examining. The +pins are all color-coded: input pins are green, output pins are blue, and +clocks are magenta:
      + + +

      + + +

      Right-click anywhere within the window to pull up a menu +that allows you to zoom in or out for easier viewing.  + +

      This menu also allows you choose to see all of the input +connections, all of the output connections, or both at once. Like +the pins, the signals are color-coded: inputs are red, outputs are yellow, +and macrocell connections are aqua: + +

      + + +

      To examine the signals of single pins, simply click the +pin whose signals you wish to see. To +examine multiple pins without having to see everything at once, hold down +the control key while you click the pins you want to view. + +

      To view the signals for individual macrocells: +

        +
        Click the inside edge of the macrocell to display its +macrocell connections and inputs.
        + + +

        Click the outer edge to display its output signals + +

        Click in the center to display everything + +

        Double click in the center to open a new window with a +detailed macrocell diagram

      + +
      + + + diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/fbsdoc.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/fbsdoc.htm new file mode 100644 index 0000000..04a25ff --- /dev/null +++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/fbsdoc.htm @@ -0,0 +1,103 @@ + + + + + + + + + + +Function Blocks + + + + + + + + + + + + + + + + + + + + + + + + +

      Function Blocks

      + +The Function + Blocks page provides a summary of all function blocks' resources. Clicking + on one of the function blocks in the summary table will display the specific details for that function block.   + +
        + + +
      The summary table + contains the following:   + +
        + +
      • The + function block
        • + +
      • The + number of macrocell used
        • + +
      • The + number of function block inputs used
        • + +
      • The + number of product terms used
        • + +
      • The + pins used
        • + +
      • The + local control terms used
        • + +
      • The + number of foldback NANDs used (CoolRunner only)
        • +
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VqLcg#YBz=68q$Y)6B83D{vW&9{;~i7 literal 0 HcmV?d00001 diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/home.gif b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/home.gif new file mode 100644 index 0000000000000000000000000000000000000000..d4411845fbae647a6d162b29a209ecbec85207dc GIT binary patch literal 940 zcmV;d15^A*Nk%w1VLt#J0M!5hUS3{8LPFQWWa#MR+S=8;ys{x7Ab56V{{H@FW?sw7 z!j+YZRaI3eC@4HUJcEOJwY97o8XE4_Wzy2iO-)Vv;bz3MV}*ZUZEa>WG&H8Bnya5; zTU%Ql9UZHyp)oNq#>Tu*P*7M{Sd5Hif>rt`UeLaQ;Xd`_QR6)`cn89hx11ZjY5PEmMPh%qWHEjTy@kdcy;k}5F@ zEkpxN3Iz}lBN!AJJ`tv;sHv)}tgR6RLntRb1sX3H0jC`uKD`FNz`?@9#KpqB5JCeA zI35cnB)h!7D=Q7x*xB0K+}+;E11C5d4*(w#)7C5>>>2Lw@bU8V^z$Dc2m~$U94zPt zE7oPG;lRO+006z*8>nd;KDjH@U3eO}U!w-&ODkot!5CO^q7^EPB4y|1(Dp!Q1AV!Q2fM!Dq ODXfL&t4PWa1OPi|=7Dhl literal 0 HcmV?d00001 diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/index.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/index.htm new file mode 100644 index 0000000..3b23466 --- /dev/null +++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/index.htm @@ -0,0 +1,14 @@ + + + + + + + + + + + + + + diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/inputleft.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/inputleft.htm new file mode 100644 index 0000000..83dc5e0 --- /dev/null +++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/inputleft.htm @@ -0,0 +1,14 @@ + + + + + +

      Unmapped Inputs

      + + + +
      Signal NameUser Assignment
      + + +
      + diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/inputleft.js b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/inputleft.js new file mode 100644 index 0000000..63fe42f --- /dev/null +++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/inputleft.js @@ -0,0 +1 @@ +function showInputLeft() { parent.leftnav.showInputLeft(); } diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/inputleftdoc.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/inputleftdoc.htm new file mode 100644 index 0000000..0cb5adb --- /dev/null +++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/inputleftdoc.htm @@ -0,0 +1,81 @@ + + + + + + + + + + + + + + + Mapped Logic + + + + + + + + + + + +

      +Unmapped Inputs

      +The +Unmapped Inputs section provides a table listing all inputs that failed +to fit into the specified device. The page will appear in your browser +sorted by Signal Name.  +
      +
      The +Unmapped Inputs table contains the following:  +
        +
      • +The +input signal name 
        • +
      + +
        +
      • +The +Pin/FB Assignment specified by the user.
        • +
      + + + diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/leftnav.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/leftnav.htm new file mode 100644 index 0000000..99d935f --- /dev/null +++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/leftnav.htm @@ -0,0 +1,63 @@ + + + + + +
      + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
      Fitter Report
       Summary
       Errors/Warnings
       Logic
       Inputs
       Function Blocks
       Equations
       Pin List
       Compiler Options
       Text Report
       Help
      +


      + + + + + +
      Equation Display Style
       
      +
        +
      + +
      + diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/leftnav.js b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/leftnav.js new file mode 100644 index 0000000..bbc0028 --- /dev/null +++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/leftnav.js @@ -0,0 +1,180 @@ +var noAppletOnClicked = 1; +var appletMsg = ""; +var waitWin; +var oldIn = oldOut = oldGbl = oldIsp = oldVcc = oldGnd = oldProhibit = oldUnuse = oldNc = 1; +var oldInfo = oldWarn = oldError = 1; +var verbose = 0; +var dispPage, mapLogPage, mapInPage, unLogPage, unInPage; +var javaPermission = 0; +var abelEqn = vhdlEqn = verEqn = ""; + +function IsNS() { + return ((navigator.appName.indexOf("Netscape") >= 0) && + (parseFloat(navigator.appVersion) >= 4)) ? true : false; +} + +function openWait() { + waitWin = window.open("wait.htm", "wait", + "toolbar=no,location=no,"+ + "directories=no,status=no,menubar=no,scrollbars=no,"+ + "resizable=no,width=300,height=50" ); +} + +function closeWait() { if (waitWin) waitWin.close(); } + +function popHTML(name, str) { + document.options.htmlStr.value = str; + if (name.indexOf(":") > -1) + name = name.substring(0,name.indexOf(":")) + "_COLON_" + + name.substring(name.indexOf(":")+1,name.length); + if (name.indexOf(".") > -1) + name = name.substring(0,name.indexOf(".")) + "_DOT_" + + name.substring(name.indexOf(".")+1,name.length); + var win = window.open("result.htm", "win_"+name, + "toolbar=no,location=no,"+ + "directories=no,status=no,menubar=no,scrollbars=yes,"+ + "resizable=yes,width=300,height=200" ); + win.focus(); +} + +function setAppletPermission() { appletPermission = 1; } +function getAppletPermission() { return( appletPermission); } +function getAppletMsg() { return(appletMsg); } +function setAppletMsg(msg) { appletMsg = msg; } + + +function showHTML(page, html) { + + dispPage = html; + document.options.currPage.value = page; + parent.content.location.href = html; +} + +function showTop() { showHTML(document.options.currPage.value, dispPage); } + +function setVerbose(value) { verbose = value; } + +function showLegend(url, w, h) { + if (verbose == 1) { + url = url.substring(0,name.indexOf(".htm")) + "V.htm"; + } + var win = window.open(url, 'win', + 'toolbar=no,location=no,directories=no,status=no,menubar=no,scrollbars=yes,resizable=yes,width='+w+',height='+h); + win.focus(); +} + +function showSummary() { showHTML("summary", "summary.htm"); } +function showOptions() { showHTML("options", "options.htm"); } +function showFBSum() { showHTML("fbs", "fbs.htm"); } +function showFB(fb) { showHTML("fbs_FB", "fbs_"+fb+".htm"); } +function showPinOut() { showHTML("pins", "pins.htm"); } +function showError() { showHTML("errors", "errs.htm"); } +function showFailTable() { showHTML("failtable", "failtable.htm"); } + +function showEqnAll() { + openWait(); + parent.eqns.setOper(currEqnType); + if (currEqnType == defEqnType) showHTML("equations", "defeqns.htm"); + else if (currEqnType == 0) { + if (abelEqn == "") abelEqn = parent.eqns.getEqnList(); + document.options.htmlStr.value = abelEqn; + showHTML("equations", "equations.htm"); + } + else if (currEqnType == 1) { + if (vhdlEqn == "") vhdlEqn = parent.eqns.getEqnList(); + document.options.htmlStr.value = vhdlEqn; + showHTML("equations", "equations.htm"); + } + else { + if (verEqn == "") verEqn = parent.eqns.getEqnList(); + document.options.htmlStr.value = verEqn; + showHTML("equations", "equations.htm"); + } + closeWait(); +} + +function showEqn(sig) { + popHTML(sig, parent.eqns.getEqn(sig)); +} + +function showPterm(pterm, type) { + popHTML(pterm, parent.eqns.getPterm(pterm, type)); +} + +function showAscii() { showHTML("ascii", "ascii.htm"); } + +function showHelp() { + var helpDoc = document.options.currPage.value + "doc.htm"; + popWin(helpDoc); +} + +function getMapParam(type) { + var paramStr = ""; + switch(type) { + case 1: paramStr += "10"; break; + case 2: paramStr += "01"; break; + case 3: paramStr += "11"; break; + case 4: paramStr += "02"; break; + case 5: paramStr += "12"; break; + default: paramStr += "00"; + } + + return paramStr; +} + +function showMappedLogics(type) { + showHTML("maplogic", "maplogic_" + getMapParam(type) + ".htm"); +} + +function showMappedInputs(type) { + showHTML("mapinput", "mapinput_" + getMapParam(type) + ".htm"); +} + +function showUnMappedLogics(type) { + showHTML("unmaplogic", "unmaplogic_" + getMapParam(type) + ".htm"); +} + +function showLogicLeft() { showHTML("logicleft", "logicleft.htm"); } + +function showUnMappedInputs(type) { + showHTML("unmapinput", "unmapinput_" + getMapParam(type) + ".htm"); +} + +function showInputLeft() { showHTML("inputleft", "inputleft.htm"); } + +function doEqnFormat() { + var type = document.options.eqnType.options[document.options.eqnType.options.selectedIndex].value; + currEqnType = type; + parent.eqns.setOper(currEqnType); + if (document.options.currPage.value == "equations") showEqnAll(); +} + +function showNoAppletAlert() { + window.alert("No Applet supported for this session!!!"); +} + +function showAppletMC(mc) { + if (parent.applets) parent.applets.showAppletGraphicMC(mc); + else showNoAppletAlert(); +} + +function showAppletFB(fb) { + if (parent.applets) parent.applets.showAppletGraphicFB(fb); + else showNoAppletAlert(); +} + +function showAppletPin(pin) { + if (parent.applets) parent.applets.showAppletGraphicPin(pin); + else showNoAppletAlert(); +} + +function printAppletPkg() { + if (parent.applets) parent.applets.printAppletPkg(); + else showNoAppletAlert(); +} + +function popWin(url) { + var win = window.open(url, 'win', + 'location=yes,directories=yes,menubar=yes,toolbar=yes,status=yes,scrollbars=yes,resizable=yes,width=800,height=600'); + win.focus(); +} diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/legend.gif b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/legend.gif new file mode 100644 index 0000000000000000000000000000000000000000..0aad0ebb2b70d602a5de51f334db320963aecd00 GIT binary patch literal 1213 zcmZ?wbhEHbbYYNT_|5t{|x`Z6p#k8fItW26Hs1o;P}rV&LQKmVZp&>4q>gB2!Vr4tUMwf zN5lgenL0(4!=`X-R6f=(Z(g>hLQvVYk6pkb#GqiQN1v*Xk(@mQx>{oX4}SYL3(-ZLg{PbIW?Vg46wGYMq|u zn=Q81XAM_fo9K>9t7CUNzkhZ2b*P^AE-z+oIhh>~gZomd%jWJ1On$UhL9zRb_P11* znKj1MwUvgepRad#DVKI<+KOA3ob}7Mbbc=OKeb3PJ*+0m`2O{T|9S-(SBu}@-`C76 zueZmd@CMIh?f7$hc7A?-Qr2nyI~g73jf(3Zb>I2=Ic;6U$-YHbW*xBl_EBGT_4HM7 zDan_3PFe4ftKN9-%a)sy@0}OjT>g{$!uH$FYPnCuqK#L!oNvsCY?&F5Cd$5`p|sNF zl26#yuYo?2o7^t9mit!7<*xboB_TI!YD7?2OlO3A=&D$@L|^f>Gs1hmTShF-5!z|7 zAf$k`Q@qE8OH;+&?%ejdxjtq)r^krs6&#on5|;UNYDC(~r_(~8iHRg8w0TODrc9C) HV6X-NY{uvO literal 0 HcmV?d00001 diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/legend.jpg b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/legend.jpg new file mode 100644 index 0000000000000000000000000000000000000000..1d04af024b10f70a03faa699fb2da92df25a3ced GIT binary patch literal 1256 zcmex=9X@jO*zpr5PhGlvPb?HxGHT=yahkYr<3UbkKb$@|Xn~>>0l3-%LJOC;5^8;98;2VV88*>51JHKa(Qear>Bm)mQ%? zq4QY(Gb~_T|M!Fap&jRMT>j@#*886!M)*I2TJL*7|q# z`G4m&UWt-e_v}+j#r>Sb*=1b9pC%uaJeqZQQH{W?XP<7#x*yu)pUi!}QY!vH)IF8l zb)OiDy4HT0RKWP)`rJRpf9KiwK3wa6ApF*{g^TX}XGpkVyY!3Uy}L^?4hL7?c-o=h zZ}G5c%5)A1ZGqnocF7+;KRDj|$5(9k!^$mlogLcjInFORydtZt==RL?f49sFJNY<@ zPV7kQII+;{lV1o!t*Tz<2Pe(9x=*jvXvOi`|`FD6KAU@8ln+!F=gI!^5x&@qZ0s`@bLf&%pKJ z{w-sNi+`-wWp0~g+9Ed5MDLt(0JqHgs9*E;<@{a!pW#UcP|NG){|s-oFn*qX`2MZr zBlkEzOl@yBnX7dB&9{j<)whawo{%{Cv)=3ee}=XrAFuyqT3i4A=YNJr8H*bDf8_Yf z)?d)N{_j7-{C{fwsN60M26Qdxd<-LY)=T}nD0RGho$fo+UM}%ztf_8&PgW{CUVr+n Js|e%&n*i?m6>0zg literal 0 HcmV?d00001 diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/logic_legXC95.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/logic_legXC95.htm new file mode 100644 index 0000000..e253a0b --- /dev/null +++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/logic_legXC95.htm @@ -0,0 +1,2 @@ +
      +
      diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/logic_legXbr.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/logic_legXbr.htm new file mode 100644 index 0000000..d256e25 --- /dev/null +++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/logic_legXbr.htm @@ -0,0 +1,16 @@ +
      +I/O Style - OD    - OpenDrain
+          - PU    - Pullup
+          - PN    - Pulldown
+          - KPR   - Keeper
+          - S     - SchmittTrigger
+          - DG    - DataGate
+Reg Use   - LATCH - Transparent latch
+          - DFF   - D-flip-flop
+          - DEFF  - D-flip-flop with clock enable
+          - TFF   - T-flip-flop
+          - TDFF  - Dual-edge-triggered T-flip-flop
+          - DDFF  - Dual-edge-triggered flip-flop
+          - DDEFF - Dual-edge-triggered flip-flop with clock enable
+          /S (after any above flop/latch type) indicates initial state is Set
+
      diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/logic_legXpla3.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/logic_legXpla3.htm new file mode 100644 index 0000000..c0e6f4a --- /dev/null +++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/logic_legXpla3.htm @@ -0,0 +1,3 @@ +
      +Legend: PU  - Pull Up
+
      diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/logicleft.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/logicleft.htm new file mode 100644 index 0000000..5da8011 --- /dev/null +++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/logicleft.htm @@ -0,0 +1,16 @@ + + + + + +

      Unmapped Logic

      + + + + + +
      Signal NameTotal PtermsTotal InputsUser Assignment
      + + +
      + diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/logicleft.js b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/logicleft.js new file mode 100644 index 0000000..2fa4142 --- /dev/null +++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/logicleft.js @@ -0,0 +1 @@ +function showLogicLeft() { parent.leftnav.showLogicLeft(); } diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/logicleftdoc.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/logicleftdoc.htm new file mode 100644 index 0000000..3537167 --- /dev/null +++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/logicleftdoc.htm @@ -0,0 +1,100 @@ + + + + + + + + + + + + + + + Mapped Logic + + + + + + + + + + + +

      +Unmapped Logic

      +The +Unmapped Logic section provides a table listing all logic that failed to +fit into the specified device. The page will appear in your browser sorted +by Signal Name.  +
      +
      The +Mapped Logic table contains the following:  +
        +
      • +The +signal name 
        • +
      + +
      Note: +Clicking on the signal name will open a new window with the equations for +that signal. 
      + +
        +
      • +The +total number of product terms 
        • + +
      • +The +total number of inputs 
        • + +
      • +The +I/O standard where appropriate
        • + +
      • +The +Pin/FB Assignment specified by the user.
        • +
      + + + diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/logiclegend.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/logiclegend.htm new file mode 100644 index 0000000..7033b9e --- /dev/null +++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/logiclegend.htm @@ -0,0 +1,106 @@ + + + + + + + +

      Legends

      +
      + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
      AcronymBrief Description
       * User Assigned
       (b) Buried macrocell
       FB# Function Block number
       GCK# Global Clock number
       GTS# Global Output Enable number
       GSR Global Set/Reset
       I Input
       I/O Input/Output
       Latch Transparent latch
       LOW Low Power Mode
       MC# Macrocell number
       O Output
       OD Open Drain
       PU Pullup
       /S After any flop/latch type indicates initial state is Set
       STD Standard Power Mode
       TCK Test clock
       TDI Test data input
       TDO Test data output
       TFF Toggle Flip-Flop
       TMS Test mode select
      + + +
      + + diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/logiclegendV.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/logiclegendV.htm new file mode 100644 index 0000000..e1813d1 --- /dev/null +++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/logiclegendV.htm @@ -0,0 +1,106 @@ + + + + + + + +

      Legends

      +
      + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
      AcronymVerbose Description
       * User Assigned
       (b) Buried macrocell
       FB# Function Block number
       GCK# Global Clock number
       GTS# Global Output Enable number
       GSR Global Set/Reset
       I Input
       I/O Input/Output
       Latch Transparent latch
       LOW Low Power Mode
       MC# Macrocell number
       O Output
       OD Open Drain
       PU Pullup
       /S After any flop/latch type indicates initial state is Set
       STD Standard Power Mode
       TCK One of four terminals required by (JTAG) IEEE Std 1149 or IEEE Std 1532. Test operations of the device are synchronous to TCK. Data is captured on the rising edge of TCK and outputs change on the falling edge of TCK. An internal pull-up forces TCK to a high level if left unconnected.
       TDI One of four terminals required by (JTAG) IEEE Std 1149 or IEEE Std 1532. It is the serial input for shifting data through the instruction register or selected data register. An internal pull-up forces TDI to a high level if left unconnected.
       TDO One of four terminals required by (JTAG) IEEE Std 1149 or IEEE Std 1532. It is the serial output for shifting data through the instruction register or selected data register. An internal pull-up forces TDI to a high level when it is not driven from an external source.
       TFF Toggle Flip-Flop
       TMS One of four terminals required by (JTAG) IEEE Std 1149 or IEEE Std 1532. It directs the device through its Test Access Port controller states. An internal pull-up forces TDI to a high level when it is not driven from an external source. TMS also provides the optional test reset signal of IEEE Std 1149 or IEEE Std 1532.
      + + +
      + + diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/macrocell.gif b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/macrocell.gif new file mode 100644 index 0000000000000000000000000000000000000000..ec9e68e415b6e37bc65b8284884e6a2f6f8747b6 GIT binary patch literal 7699 zcmeHIWm6mA(rsy>IHfI8qz0uprMR}Z7m7o$;_mKN8c1*r!AX!1+=3T(C%C)2Q^?zU zf5Q9uo|&DqJI`~@?Ci|W%E(Fc3;d+Pf<3-^^dAKNHv<1lf&Z$&|KRDj!te-g&FJEyA+ER|TN&kK>Z2g>5RRR?E zQ7*3PUCuAuByyu>Ux<;p5-HD1?Sj{IV#AqVU*aAxRTYfp@`f@*w!Rk|&-U?A`FsC+qH`|Wf~-tz3_j+j))4!S4EJ5&6JpPI zfwVN!M%YBsKrDQUZ$NQu3eAG|ffTM;KYvq%ZodbDC19=DUIl&bVq61r zPg<@;@^2QbMG0SSuSI{uVOo!oB)3|Rm1QVgk5lB`S&vtdX4*(l*Yu*p(d+`6CF!~E zY$Sg*E`x(jf~__omT`D=NoLG5=1{9HCW~0yMwKnF$E4RM5bnMleHsr|L|&E)c|Co$ z`iIoqoG{+q?HK?1o^4RPyUtE-%AsdrJalN z>LKGjwt|{T=1tUklFeb=b{@zcu@nqiLkULoerVKjo;z$Zzbv#%s9%NdG~3jmK9)Tp zusu$>97`!{A>^ZBY#<(0UA>JcUpz?3E`zx=X2uXNewQ z?qK)PajyELwPVrGyV?jF;^e@08J>AywHZ`D1?P^+ejuu96Xy`w80dd-&mAexVh2ON zSMWyke9xUfN2qoea!pFcMIPkoDa`UDtGuMH>6+MVxNJP(z2{Bvcsp}h=B0p1tDFx* zuv{;PaHQ6>eh#CCHG}yMuh(K^*l*Sow1^8wBA(26EQRsf)Wl>qFw+%B{+=nG+^nJT zF3@)HE!iz)E@D{;rGWA;|1z+)jn;I)zZ+etkSqPO?(XkZ?4-a{ngqA+uUpJrEp!;t zER8bFM^i0S9Q6tzw~D*pF5K?~;0$oX<<1J5Z|>`G*{9H0b)nhtwzy5t>V&yY@g1c{S>biN+zwXrA_g%B>@6FjC!|h3?U>38s%- zj9^F8Wi0eGm!PIx1U=yGd1`@x(#~&6eh7&M`YaMiXS@zYyDg+yrK^PB{ z^;bGIj%s{Ep9sqzkW!8YO{`^XPl?_NAmXmtOxjiO$|2%@BI)UG z4e)xBTjRX4?#$SJTZtM!FeZbA4LM3tz4}yK-z#%hxT3A3-r(WeO#PkZ9z-#$unhxh z&ndo`6e?&n7eO}XH*wJd15OpB=|G|U&*_lw?##o|OI7*(^Sv0k0UkEU%By_QXS?E} zc_b;>l9u8i9p&H;{n^j;8TwXnWdfMb;|bHXzMUlY18YE;R|%H9OgzHI($)#W`!Gt8 z-BHQD(s)WZUDo9$KR6-|PSVLF*-idUXmD5){N$rNkvDt#n~8#_L<@`>x`LUhrwX*y z7V5F`XoT(sLVFOQS=)y$@xCZBA}Y#-p?;Jz5NMkdk?D-@R`J@O6gx&1>21kR)z6ZZ z=+36;&mg{JGqd*$vK;&D?Y0~2G2-1PpgqD%{%k-)lI@ZW3eRBvzpA6 zrp1~`xo4)>R$eBE-g3_lYDa6H9?3Tpay^lz+weYmW3;)a%KqTVQzfnSH(CRo8q%xT z?%2f)UlSs}rY{x0*&64Zvg{-hsZ2ehmfI0f!bHx1oPyjCCauJYF@b(eBx(rVb}Fwj z-A$I%==BYfHP5iCT>E$&JD7NPO_RQ{>u)l@3C2V9Djw+-ZULKivRyTRvS@tn&i;;- zdu&JT!mdh-hsAN?7@C>IO=u>~>Se!+wdfo2$lta*A5>p~ZK5uMp;as5yD#93`fuWr zQ`Cf?P@(OG)_!G2Dt|p4oBqUV1v~nD=VgAIp>$N&8`s@_#%S48X|Sm=L|^6eg;SXJDobT(*wxi`^ z#ia;#RCYF^GaxR$EoF1J!i;SR*x#`53G+$kJ{sgd3HyHTaTQ-1sdVcP@i$8!7aaWYTc-{g;e==a%qP8K z60FUzFZCJTmEo-&+31-pfu^TQbzg+P-@B|eOt-Vlw_P|Gx@x|=KMEviTz;l}-A4Uz z41Bhyf0cUO#dlmC75#VY9mmZ>Uft-WMDV)-!x}Am z6EZH!8esjEY^Q8!4i@OL+kUlHBGJ>i1ozjdY{bg~@ZV?P@f3*+=U~#X-!YbvlA2M% zTfu3kc6-mFG$~anQ@pjWA}3O!8Z5(ZJwM`^fb%JV)8wGzR~C%?;YU5;E9TKHo_-KM zt0xK3(c*#wj8T^bfrNE2lmf~f7e;%(%$ji>L%SGffMB(!F*kXUs}x^l+eL7^+zs<% z-a+V*DOy7>!;NGDKV#~m84AM%Z(LC8wj4}BXiA3pHq)svm*Tu{O4aKA)fQrIF?myQ z4*W7L<^t6f9u_?b8aFoAbQbn)o?h3nPA=BLWRAd;c;U`34xx#lu&Dif0Xhia`-ZyW zPJ+fnBC}L7(%ssEDZ!ip0Ln8VdTJ3|$fSVdWcf4!r^8ylPIM+D?x-g@voq6wjpa-2&Hp8ILm#&pJq$}7+E%HD|6WK5YvGgS zlZC46B%J`gDs=3PJ>&KGy<6*C!uS&&ho?q)r2Vl_#oC7Q3%H4BCYi3Ku~0$-A#6n` zc9_@CX{PWJ4Bl@+{Ao9g<0Cor%HA8lFj7 z#flv;kC&e2c>#$@@rs>cN_#U4&A(xLEuTY?;7BT)Hlzi4UI?_{%_Y~(IJ}0anM2ui zGo^Mj%OaGCUp&iUi+~Ys<;JL{e5i*q3fd8n!{0}^>eVNib;G_@>I1y; zOfP}x=DZk3Q-A+5Sf8gWaC1wk@YC4XmK9t63$tct{Uvy}6rjQRl2sB`g)lD4d4 zxPFz8l9zuJEPtg?n5Y>|qF^*HZ%sp;MMmI9L0xg)VHKraK?}<5$Se6Gl*bN*f5rep zre_sd3G{hvD$kgrd8ta_btyi~U-`}9?#a^nF#az*mEJpYibXKUbR`kBW3jnKt#K(G zRI$1qrVgmq$NL(?T+WRPkiBykuJ)GnQS;C=FazmY*tln&CFInXi&4}Xb zbM!+DsZqf~s89eZ%m)R8q9Phl;5k&(9V&*pE>5T}0Ze$=ldcsM7__Rh+6FJyWmVXdGwKgcFoS1>F)n$*JCTZoa8* z*#r5_ibw7DH#|cAxu)`OmSP;wZ#lfnep|p*L*3MR*O)qmyy};30K{PFX)Gl}30UFJ zwRy}6eLpE`EGM^pm~T0)^TS0dLpK7C=Gy6mWm2i!i$QHKe2X5-#t7h5(P=lnwr$~M z&9D*3R~7D5*Xz{O>x3KsS;Rv~p#rYtnm7CONE%x^@C&5&i;W4}6}CIYkX;YSUGr64 zW;D$gcl!K7U5^2^7Q)r{n%!QkiAuKJM7XB*1Lfp8Y1}@h!Wf$Fk3Ky{^Ce&8dcgY? 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zfCP2qY*bu`1w4#1?~M&qRKc697>Yi2MOcU{!AF9xgQ pHu?wNT8*0;r9K-rhWEExe{eL*LO$C5B=XVjV9+eL#m9Xl^ncXyUyA?$ literal 0 HcmV?d00001 diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/mapinput_00.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/mapinput_00.htm new file mode 100644 index 0000000..1aafeda --- /dev/null +++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/mapinput_00.htm @@ -0,0 +1,240 @@ + + + + + + +

      Inputs

      + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
      Signal NameFunction BlockMacrocellPin NumberPin TypePin Use
      A<10>FB5MC359I/OI
      A<11>FB5MC1260I/OI
      A<12>FB5MC1461I/OI
      A<13>FB5MC1564I/OI
      A<16>FB8MC497I/OI
      A<17>FB8MC395I/OI
      A<18>FB8MC894I/OI
      A<19>FB8MC592I/OI
      A<1>FB5MC957I/OI
      A<20>FB8MC291I/OI
      A<21>FB7MC1788I/OI
      A<22>FB7MC1587I/OI
      A<23>FB7MC1486I/OI
      A<2>FB5MC654I/OI
      A<3>FB5MC252I/OI
      A<4>FB3MC1550I/OI
      A<5>FB3MC1449I/OI
      A<6>FB3MC1751I/OI
      A<9>FB5MC1158I/OI
      ASFB7MC980I/OI
      AUTOBOOT_OFFFB7MC375I/OI
      BERRFB8MC1198I/OI
      C1FB8MC13103I/OI
      C3FB8MC14102I/OI
      RESETFB2MC2143I/O/GSRGSR/I
      RWFB7MC1683I/OI
      UDSFB7MC1381I/OI
      + + +
      + +
      + + diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/mapinput_01.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/mapinput_01.htm new file mode 100644 index 0000000..078acde --- /dev/null +++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/mapinput_01.htm @@ -0,0 +1,240 @@ + + + + + + +

      Inputs

      + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
      Signal NameFunction BlockMacrocellPin NumberPin TypePin Use
      RESETFB2MC2143I/O/GSRGSR/I
      A<5>FB3MC1449I/OI
      A<4>FB3MC1550I/OI
      A<6>FB3MC1751I/OI
      A<3>FB5MC252I/OI
      A<10>FB5MC359I/OI
      A<2>FB5MC654I/OI
      A<1>FB5MC957I/OI
      A<9>FB5MC1158I/OI
      A<11>FB5MC1260I/OI
      A<12>FB5MC1461I/OI
      A<13>FB5MC1564I/OI
      AUTOBOOT_OFFFB7MC375I/OI
      ASFB7MC980I/OI
      UDSFB7MC1381I/OI
      A<23>FB7MC1486I/OI
      A<22>FB7MC1587I/OI
      RWFB7MC1683I/OI
      A<21>FB7MC1788I/OI
      A<20>FB8MC291I/OI
      A<17>FB8MC395I/OI
      A<16>FB8MC497I/OI
      A<19>FB8MC592I/OI
      A<18>FB8MC894I/OI
      BERRFB8MC1198I/OI
      C1FB8MC13103I/OI
      C3FB8MC14102I/OI
      + + +
      + +
      + + diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/mapinput_02.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/mapinput_02.htm new file mode 100644 index 0000000..cfc0057 --- /dev/null +++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/mapinput_02.htm @@ -0,0 +1,240 @@ + + + + + + +

      Inputs

      + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
      Signal NameFunction BlockMacrocellPin NumberPin TypePin Use
      A<5>FB3MC1449I/OI
      A<4>FB3MC1550I/OI
      A<6>FB3MC1751I/OI
      A<3>FB5MC252I/OI
      A<2>FB5MC654I/OI
      A<1>FB5MC957I/OI
      A<9>FB5MC1158I/OI
      A<10>FB5MC359I/OI
      A<11>FB5MC1260I/OI
      A<12>FB5MC1461I/OI
      A<13>FB5MC1564I/OI
      AUTOBOOT_OFFFB7MC375I/OI
      ASFB7MC980I/OI
      UDSFB7MC1381I/OI
      RWFB7MC1683I/OI
      A<23>FB7MC1486I/OI
      A<22>FB7MC1587I/OI
      A<21>FB7MC1788I/OI
      A<20>FB8MC291I/OI
      A<19>FB8MC592I/OI
      A<18>FB8MC894I/OI
      A<17>FB8MC395I/OI
      A<16>FB8MC497I/OI
      BERRFB8MC1198I/OI
      C3FB8MC14102I/OI
      C1FB8MC13103I/OI
      RESETFB2MC2143I/O/GSRGSR/I
      + + +
      + +
      + + diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/mapinputdoc.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/mapinputdoc.htm new file mode 100644 index 0000000..3ac20d8 --- /dev/null +++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/mapinputdoc.htm @@ -0,0 +1,147 @@ + + + + + + + + + + + + + + + Mapped Inputs + + + + + + + + + + + +

      +Mapped Inputs

      +Like +the Mapped Logic section, the Mapped Inputs +section of the report displays a table detailing the resources allocated +by the fitter to mapped inputs. Again, +the table can be sorted by Signal Name, Function Block, or Pin Number by +clicking on the appropriate table headings.  +
      +
      The +inputs table contains the following:  +
        +
      • +The +input signal name 
        • + +
      • +The +function block number - an asterisk "*" indicates a user assignment
        • +
      + +
      Note: +Clicking on the function block will provide a detailed table of all the +block's resources and a graphical display of the function block diagram +(see Function Block Specifics for more details).
      + +
        +
      • +The +macrocell number
        • +
      + +
        +
        Note: +Clicking on the underscored macrocell number will provide a graphical display +of the macrocell that looks like this:
        + +
        +
        + +
          + +
      • +The +pin number - an asterisk "*" indicates a user assignment
        • +
      + +
      Note: +Clicking on the underscored pin number will provide the pin layout diagram +for the highlighted pin. Rolling +your mouse over the colored pin will pop up a tooltip with the signal name +assigned to the pin, the I/O standard, the +I/O style, the slew rate, and/or any constraints assigned to the pin:
      + + +

      + +

        + +
        +
      • +The +pin type
        • + +
      • +The +pin use 
        • + +
      • +The +I/O standard
        • + +
      • +The +I/O style
        • +
      + + + diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/maplogic.js b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/maplogic.js new file mode 100644 index 0000000..e40c8f2 --- /dev/null +++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/maplogic.js @@ -0,0 +1,23 @@ +function showFB(fb) { parent.leftnav.showFB(fb); } +function showMC(mc) { parent.leftnav.showAppletMC(mc); } +function showEqn(sig) { parent.leftnav.showEqn(sig); } +function showPin(pin) { parent.leftnav.showAppletPin(pin); } +function showLegend(url) { parent.leftnav.showLegend(url, 650, 350); } +function showTop() { parent.leftnav.showTop(); } + +function Sort(x) { + switch (x) { + case 0: parent.leftnav.showMappedLogics(0); break; + case 1: parent.leftnav.showMappedLogics(2); break; + case 2: parent.leftnav.showMappedLogics(4); break; + case 10: parent.leftnav.showMappedInputs(0); break; + case 11: parent.leftnav.showMappedInputs(2); break; + case 12: parent.leftnav.showMappedInputs(4); break; + case 20: parent.leftnav.showUnMappedLogics(0); break; + case 21: parent.leftnav.showUnMappedLogics(2); break; + case 22: parent.leftnav.showUnMappedLogics(4); break; + case 30: parent.leftnav.showUnMappedInputs(0); break; + case 31: parent.leftnav.showUnMappedInputs(2); break; + case 32: parent.leftnav.showUnMappedInputs(4); break; + } +} diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/maplogic_00.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/maplogic_00.htm new file mode 100644 index 0000000..0ce2973 --- /dev/null +++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/maplogic_00.htm @@ -0,0 +1,692 @@ + + + + + + +

      Logic

      + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
      Signal NameTotal PtermsTotal InputsFunction BlockMacrocellPower ModeSlew RatePin NumberPin TypePin UseReg Init State
      AUTOCONFIG_IN_PROGRESS23FB1MC7STD  (b)(b)RESET
      AUTO_CONFIG_DONE<0>22FB2MC9STD 6I/O/GTS2(b)RESET
      AUTO_CONFIG_DONE<1>22FB3MC15STD 50I/OIRESET
      AUTO_CONFIG_DONE<2>22FB2MC8STD 5I/O/GTS1(b)RESET
      AUTO_CONFIG_DONE_CYCLE<0>313FB2MC11STD 9I/O(b)RESET
      AUTO_CONFIG_DONE_CYCLE<1>314FB3MC16STD  (b)(b)RESET
      AUTO_CONFIG_DONE_CYCLE<2>315FB2MC10STD 7I/O(b)RESET
      D<0>12FB2MC5STDFAST2I/O/GTS3O 
      D<10>12FB3MC3STDFAST41I/OI/O 
      D<11>12FB3MC11STDFAST43I/OI/O 
      D<12>_BUFR1916FB1MC18STD  (b)(b)RESET
      D<12>23FB3MC4STDFAST44I/OI/O 
      D<13>_BUFR1715FB2MC15STD 13I/O(b)RESET
      D<13>23FB3MC12STDFAST45I/OI/O 
      D<14>_BUFR1815FB2MC1STD 142I/O(b)RESET
      D<14>23FB3MC7STDFAST46I/OI/O 
      D<15>_BUFR1415FB6MC17STD 125I/O(b)RESET
      D<15>23FB3MC10STDFAST48I/OI/O 
      D<1>12FB1MC3STDFAST17I/OO 
      D<2>12FB3MC1STDFAST39I/OO 
      D<3>12FB2MC17STDFAST15I/OO 
      D<4>12FB1MC8STDFAST21I/OO 
      D<5>12FB1MC6STDFAST20I/OO 
      D<6>12FB2MC16STDFAST14I/OO 
      D<7>12FB1MC2STDFAST16I/OO 
      D<8>12FB1MC5STDFAST19I/OI/O 
      D<9>12FB3MC9STDFAST40I/OI/O 
      DTACK00FB7MC12STDFAST85I/OO 
      IDE_A<0>11FB1MC11STDFAST24I/OO 
      IDE_A<1>11FB1MC12STDFAST26I/OO 
      IDE_A<2>11FB1MC4STDFAST25I/OO 
      IDE_BASEADR<0>416FB5MC18STD  (b)(b)RESET
      IDE_BASEADR<1>416FB5MC16STD  (b)(b)RESET
      IDE_BASEADR<2>416FB3MC18STD  (b)(b)RESET
      IDE_BASEADR<3>416FB3MC17STD 51I/OIRESET
      IDE_BASEADR<4>416FB5MC15STD 64I/OIRESET
      IDE_BASEADR<5>416FB5MC14STD 61I/OIRESET
      IDE_BASEADR<6>416FB2MC13STD 12I/O(b)RESET
      IDE_BASEADR<7>416FB2MC12STD 10I/O(b)RESET
      IDE_CS<0>11FB1MC9STDFAST22I/OO 
      IDE_CS<1>11FB1MC1STDFAST23I/OO 
      IDE_ENABLE36FB1MC10STD 31I/O(b)RESET
      IDE_R26FB1MC14STDFAST27I/OOSET
      IDE_W25FB1MC15STDFAST28I/OOSET
      ROM_B<0>00FB5MC10STDFAST68I/OO 
      ROM_B<1>00FB5MC17STDFAST69I/OO 
      ROM_OE26FB1MC16STDFAST35I/OOSET
      SHUT_UP<1>315FB5MC13STD 70I/O(b)RESET
      autoconfig413FB4MC17STD 140I/O(b)RESET
      ide1919FB4MC1STD 118I/O(b)RESET
      ide/ide_CLKF22FB4MC16STD 139I/O(b) 
      + + +
      + +
      + + diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/maplogic_01.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/maplogic_01.htm new file mode 100644 index 0000000..da29717 --- /dev/null +++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/maplogic_01.htm @@ -0,0 +1,692 @@ + + + + + + +

      Logic

      + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
      Signal NameTotal PtermsTotal InputsFunction BlockMacrocellPower ModeSlew RatePin NumberPin TypePin UseReg Init State
      IDE_CS<1>11FB1MC1STDFAST23I/OO 
      D<7>12FB1MC2STDFAST16I/OO 
      D<1>12FB1MC3STDFAST17I/OO 
      IDE_A<2>11FB1MC4STDFAST25I/OO 
      D<8>12FB1MC5STDFAST19I/OI/O 
      D<5>12FB1MC6STDFAST20I/OO 
      AUTOCONFIG_IN_PROGRESS23FB1MC7STD  (b)(b)RESET
      D<4>12FB1MC8STDFAST21I/OO 
      IDE_CS<0>11FB1MC9STDFAST22I/OO 
      IDE_ENABLE36FB1MC10STD 31I/O(b)RESET
      IDE_A<0>11FB1MC11STDFAST24I/OO 
      IDE_A<1>11FB1MC12STDFAST26I/OO 
      IDE_R26FB1MC14STDFAST27I/OOSET
      IDE_W25FB1MC15STDFAST28I/OOSET
      ROM_OE26FB1MC16STDFAST35I/OOSET
      D<12>_BUFR1916FB1MC18STD  (b)(b)RESET
      D<14>_BUFR1815FB2MC1STD 142I/O(b)RESET
      D<0>12FB2MC5STDFAST2I/O/GTS3O 
      AUTO_CONFIG_DONE<2>22FB2MC8STD 5I/O/GTS1(b)RESET
      AUTO_CONFIG_DONE<0>22FB2MC9STD 6I/O/GTS2(b)RESET
      AUTO_CONFIG_DONE_CYCLE<2>315FB2MC10STD 7I/O(b)RESET
      AUTO_CONFIG_DONE_CYCLE<0>313FB2MC11STD 9I/O(b)RESET
      IDE_BASEADR<7>416FB2MC12STD 10I/O(b)RESET
      IDE_BASEADR<6>416FB2MC13STD 12I/O(b)RESET
      D<13>_BUFR1715FB2MC15STD 13I/O(b)RESET
      D<6>12FB2MC16STDFAST14I/OO 
      D<3>12FB2MC17STDFAST15I/OO 
      D<2>12FB3MC1STDFAST39I/OO 
      D<10>12FB3MC3STDFAST41I/OI/O 
      D<12>23FB3MC4STDFAST44I/OI/O 
      D<14>23FB3MC7STDFAST46I/OI/O 
      D<9>12FB3MC9STDFAST40I/OI/O 
      D<15>23FB3MC10STDFAST48I/OI/O 
      D<11>12FB3MC11STDFAST43I/OI/O 
      D<13>23FB3MC12STDFAST45I/OI/O 
      AUTO_CONFIG_DONE<1>22FB3MC15STD 50I/OIRESET
      AUTO_CONFIG_DONE_CYCLE<1>314FB3MC16STD  (b)(b)RESET
      IDE_BASEADR<3>416FB3MC17STD 51I/OIRESET
      IDE_BASEADR<2>416FB3MC18STD  (b)(b)RESET
      ide1919FB4MC1STD 118I/O(b)RESET
      ide/ide_CLKF22FB4MC16STD 139I/O(b) 
      autoconfig413FB4MC17STD 140I/O(b)RESET
      ROM_B<0>00FB5MC10STDFAST68I/OO 
      SHUT_UP<1>315FB5MC13STD 70I/O(b)RESET
      IDE_BASEADR<5>416FB5MC14STD 61I/OIRESET
      IDE_BASEADR<4>416FB5MC15STD 64I/OIRESET
      IDE_BASEADR<1>416FB5MC16STD  (b)(b)RESET
      ROM_B<1>00FB5MC17STDFAST69I/OO 
      IDE_BASEADR<0>416FB5MC18STD  (b)(b)RESET
      D<15>_BUFR1415FB6MC17STD 125I/O(b)RESET
      DTACK00FB7MC12STDFAST85I/OO 
      + + +
      + +
      + + diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/maplogic_02.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/maplogic_02.htm new file mode 100644 index 0000000..6fd0493 --- /dev/null +++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/maplogic_02.htm @@ -0,0 +1,710 @@ + + + + + + +

      Logic

      + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
      Signal NameTotal PtermsTotal InputsFunction BlockMacrocellPower ModeSlew RatePin NumberPin TypePin UseReg Init State
      D<0>12FB2MC5STDFAST2I/O/GTS3O 
      AUTO_CONFIG_DONE<2>22FB2MC8STD 5I/O/GTS1(b)RESET
      AUTO_CONFIG_DONE<0>22FB2MC9STD 6I/O/GTS2(b)RESET
      AUTO_CONFIG_DONE_CYCLE<2>315FB2MC10STD 7I/O(b)RESET
      AUTO_CONFIG_DONE_CYCLE<0>313FB2MC11STD 9I/O(b)RESET
      IDE_BASEADR<7>416FB2MC12STD 10I/O(b)RESET
      IDE_BASEADR<6>416FB2MC13STD 12I/O(b)RESET
      D<13>_BUFR1715FB2MC15STD 13I/O(b)RESET
      D<6>12FB2MC16STDFAST14I/OO 
      D<3>12FB2MC17STDFAST15I/OO 
      D<7>12FB1MC2STDFAST16I/OO 
      D<1>12FB1MC3STDFAST17I/OO 
      D<8>12FB1MC5STDFAST19I/OI/O 
      D<5>12FB1MC6STDFAST20I/OO 
      D<4>12FB1MC8STDFAST21I/OO 
      IDE_CS<0>11FB1MC9STDFAST22I/OO 
      IDE_CS<1>11FB1MC1STDFAST23I/OO 
      IDE_A<0>11FB1MC11STDFAST24I/OO 
      IDE_A<2>11FB1MC4STDFAST25I/OO 
      IDE_A<1>11FB1MC12STDFAST26I/OO 
      IDE_R26FB1MC14STDFAST27I/OOSET
      IDE_W25FB1MC15STDFAST28I/OOSET
      IDE_ENABLE36FB1MC10STD 31I/O(b)RESET
      ROM_OE26FB1MC16STDFAST35I/OOSET
      D<2>12FB3MC1STDFAST39I/OO 
      D<9>12FB3MC9STDFAST40I/OI/O 
      D<10>12FB3MC3STDFAST41I/OI/O 
      D<11>12FB3MC11STDFAST43I/OI/O 
      D<12>23FB3MC4STDFAST44I/OI/O 
      D<13>23FB3MC12STDFAST45I/OI/O 
      D<14>23FB3MC7STDFAST46I/OI/O 
      D<15>23FB3MC10STDFAST48I/OI/O 
      AUTO_CONFIG_DONE<1>22FB3MC15STD 50I/OIRESET
      IDE_BASEADR<3>416FB3MC17STD 51I/OIRESET
      IDE_BASEADR<5>416FB5MC14STD 61I/OIRESET
      IDE_BASEADR<4>416FB5MC15STD 64I/OIRESET
      ROM_B<0>00FB5MC10STDFAST68I/OO 
      ROM_B<1>00FB5MC17STDFAST69I/OO 
      SHUT_UP<1>315FB5MC13STD 70I/O(b)RESET
      DTACK00FB7MC12STDFAST85I/OO 
      ide1919FB4MC1STD 118I/O(b)RESET
      D<15>_BUFR1415FB6MC17STD 125I/O(b)RESET
      ide/ide_CLKF22FB4MC16STD 139I/O(b) 
      autoconfig413FB4MC17STD 140I/O(b)RESET
      D<14>_BUFR1815FB2MC1STD 142I/O(b)RESET
      AUTOCONFIG_IN_PROGRESS23FB1MC7STD  (b)(b)D  RESET
      D<12>_BUFR1916FB1MC18STD  (b)(b)D  RESET
      AUTO_CONFIG_DONE_CYCLE<1>314FB3MC16STD  (b)(b)D  RESET
      IDE_BASEADR<2>416FB3MC18STD  (b)(b)T  RESET
      IDE_BASEADR<1>416FB5MC16STD  (b)(b)T  RESET
      IDE_BASEADR<0>416FB5MC18STD  (b)(b)T  RESET
      + + +
      + +
      + + diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/maplogicdoc.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/maplogicdoc.htm new file mode 100644 index 0000000..75e0468 --- /dev/null +++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/maplogicdoc.htm @@ -0,0 +1,167 @@ + + + + + + + + + + + + + + + Mapped Logic + + + + + + + + + + + +

      +Mapped Logic

      +The +Mapped Logic section provides a table listing resources allocated by the +fitter to mapped logic. The page will appear in your browser sorted by +Signal Name, but you can choose to sort it by Signal Name, Function Block, +and Pin Number by clicking on the appropriate table headers.  +
      +
      The +Mapped Logic table contains the following:  +
        +
      • +The +output signal name 
        • +
      + +
      Note: +Clicking on the signal name will open a new window with the equations for +that signal. 
      + +
        +
      • +The +total number of product terms 
        • + +
      • +The +number of signals used 
        • + +
      • +The +function block number - an asterisk "*" indicates a user assignment 
        • +
      + +
      Note: +Clicking on the function block will provide a detailed table of all the +block's resources and a graphical display of the function block diagram +(see Function Block Specifics for more details).
      + +
        +
      • +The +macrocell number
        • +
      + +
      Note: +Clicking on the underscored macrocell number will provide a graphical display +of the macrocell that looks like this:
      + + +

      +. +

        +
      • +The +slew rate
        • + +
      • +The +pin number - an asterisk "*" indicates a user assignment 
        • +
      + +
      Note: +Clicking on the underscored pin number will provide the pin layout diagram +for the highlighted pin. Rolling +your mouse over the colored pin will pop up a tooltip with the signal name +assigned to the pin, the I/O standard, the +I/O style, the slew rate, and/or any constraints assigned to the pin:
      + + +

      + +

        +
      • +The +pin type
        • + +
      • +The +pin use
        • + +
      • +The +input register use
        • + +
      • +The +I/O standard
        • + +
      • +The +I/O style
        • +
      + + + diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/newappletref.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/newappletref.htm new file mode 100644 index 0000000..37f3d7f --- /dev/null +++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/newappletref.htm @@ -0,0 +1,14 @@ + + + + + + + + + + + + + + diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/next.jpg b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/next.jpg new file mode 100644 index 0000000000000000000000000000000000000000..b8bbb999ee5f7042c9dcbad4dacf3659aa2ee7a8 GIT binary patch literal 1079 zcmex=9X@jO*zpr5PhGlvPb?HxGHT=yahkYr<3UbkKb$@|Xn~>>0k;H_C~9n78`F`QPzJCPur8PO(e59<=M&#AB!andt81j&-><& zq0R)8)>*%}S1eCIc5p`YX|0I4_YHq$Fz?;;;rYSt*U{0tb<-VpZr`&@tnAX^l};~h z4@wFuvh)0Bc+*$ATG}JO(dzgS4jcZ(uV&>fUG1N$daHKQE6pTDX*Pvd9!8IgE0a~U zjAeMzr9*y*KC+EJcQ} z_Q%h2XUvoA_V4%D9AWcJ^)|EmddV+~w(ZY~|Jm}-{= 4)); + +var pluginDetected = false; + +// we can check for plugin existence only when browser is 'is_ie5up' or 'is_nav4up' +if(is_nav4up) { + + // Refresh 'navigator.plugins' to get newly installed plugins. + // Use 'navigator.plugins.refresh(false)' to refresh plugins + // without refreshing open documents (browser windows) + if(navigator.plugins) { + navigator.plugins.refresh(false); + } + + // check for Java plugin in installed plugins + if(navigator.mimeTypes) { + // window.alert( navigator.mimeTypes.length); + for (i=0; i < navigator.mimeTypes.length; i++) { + // window.alert( navigator.mimeTypes[i].type); + if( (navigator.mimeTypes[ i].type != null) + &&(navigator.mimeTypes[ i].type.indexOf( + "application/x-java-applet;jpi-version=1.4") != -1) ) { + //window.alert("Found"); + pluginDetected = true; + break; + } + + } + } + +} + +if (pluginDetected) { + // show applet page + document.location.href="appletref.htm"; + +} else if (confirm("Java Plugin 1.4+ not found, Do you want to download it?\n" + + "if you choose not to install the plugin the reports graphical applets will not be available.")) { + document.location.href=XilinxD; +} else { + document.location.href="appletref.htm"; +} + +} + diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/options.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/options.htm new file mode 100644 index 0000000..afaa252 --- /dev/null +++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/options.htm @@ -0,0 +1,106 @@ + + + + + + +

      Compiler Options

      + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
      OptionValue
       Device(s) Specified + xc95144xl-10-TQ144
       Optimization Method + SPEED
       Multi-Level Logic Optimization + ON
       Ignore Timing Specifications + OFF
       Default Register Power Up Value + LOW
       Slew Rate + FAST
       Keep User Location Constraints + ON
       What-You-See-Is-What-You-Get + OFF
       Exhaustive Fitting + OFF
       Keep Unused Inputs + OFF
       Power Mode + STD
       Ground on Unused IOs + OFF
       Global Clock Optimization + ON
       Global Set/Reset Optimization + ON
       Global Ouput Enable Optimization + ON
       Set I/O Pin Termination + KEEPER
       Input Limit (2-54) 54
       Pterm Limit (1-90) 25
      + + +
      + + diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/optionsdoc.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/optionsdoc.htm new file mode 100644 index 0000000..f1ee543 --- /dev/null +++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/optionsdoc.htm @@ -0,0 +1,760 @@ + + + + + + + + + + +Compiler Options + + + + + + + + + + + + + + + + + + + + + + + + +

      Compiler Options

      + +

      The Compiler + Options page provides all the fitter options settings for the device family + the fitter has selected.

      + +

      Fitter Options

      + +

      Basic Tab

      + +

      XPLA3 Advanced + Options

      + +

      CoolRunner-II + Advanced Options

      + +

      XC9500/XL/XV + Advanced Options

      + +

      Basic + Tab

      + +

      The CPLD devices + have the following fitter Implementation + Options available in + the Basic tab:

      + +
        + +

      • Use + Multi-Level Logic Optimization

        • +
      + +

      This option simplifies the total number + of logic expressions in a design, and then collapses the logic in order + to meet user objectives such as density, speed and timing constraints. + This optimization targets CPLD architecture, making it possible to collapse + to the macrocell limits, reduce levels of logic, and minimize the total + number of p-terms.

      + +

      Multi-level Logic Optimization optimizes + all combinatorial logic arcs spanning from an input pad or register output + to an output pad or register input.

      + +

      Multi-level Logic Optimization operates + on combinatorial logic according to the following rules.

      + +

      If timing constraints are set, the program + optimizes for speed to meet timing constraints.

      + +

      If timing constraints are not set, the + program optimizes either for speed or density, depending on the user setting + for the Use Timing Optimization + option.

      + +
        + +
          + +
            + +

          • If + Use Timing Optimization is turned + on, the combinatorial logic will be mapped for speed.

            • + +

          • If + Use Timing Optimization is turned + off, the combinatorial logic will be mapped for density. The goal of optimization + will then be to reduce the total number of p-terms.

            • +
          +
        +
      + +

      Logic + marked with the NOREDUCE property will not be extracted or optimized.

      + +

      By + default, this option is on.

      + +
        + +

      • Use Timing Constraints -- This + option instructs the fitter use Timing Constraints when fitting the design. +  If this + box is not checked, the fitter will ignore timing constraints, if necessary.

        • + +

      • Enable WYSIWYG + Mode -- (CoolRunner only) The + goal of the WYSIWYG options is to have a netlist reflect the user's specifications, + as much as possible. All the nodes declared in the HDL design are preserved. + By default, this property is set to Off (Checkbox is not checked) When + this property is On (checkbox is checked), XST:

        • + +
          + +

        • Preserves + all the user internal signals (nodes)

          • + +

        • Creates + source_node constraints in NGC file for all these nodes.

          • + +

        • Skips + the design optimization (collapse, factorization). Only the Boolean equation + minimization is performed.

          • +
        + +

      • Optimization Style-- The Optimization + Method allows you to select from one of two basic optimization strategies: + Density or Speed. + Density focuses on solely + on density, and Speed focuses + solely on speed.

        • + +

      • Location Constraints -- The Try selection + will attempt to fit the design with the pin assignments specified in the + design source. If the design cannot be fit with these pin assignments, + the fitter will remove the location constraints and attempt to fit the + design with no location constraints. A warning message will tell the user + if the location constraints have been removed.

        • + +
          + +

        • The + Try selection will attempt + to fit the design with the pin assignments specified in the design source. + If the design cannot be fit with these pin assignments, the fitter will + ignore the pin assignments.

          • +
        + +

      • The + On selection will attempt to fit + the design with the pin assignments specified in the design source. If + the design cannot be fit with these pin assignments, the fitter will notify + the user that the device could not fit. It will not unlock the pins under + this option.

        • + +

      • The + Off selection will attempt to + fit the design and will ignore the pin assignments specified in the design + source. If the design can be fit with no pre-assigned pins, the fitter + will assign pins, which can be viewed in the fitter report (filename.fit). + The user should take these pin assignments and incorporate them back into + the design source file. The user will be notified whether the fitting + operation was successful.

        • + +

      • Output + Slew Rate -- Use this option + to control the default output slew rate. You can control the transition + time of device output pins by setting the slew rate to Slow or Fast. Limiting + the slew rate (Slow) reduces output switching surges in the device. The + default is Fast.

        • +
      + +

      Note: + Any explicit slew rate control properties in the design or constraints + file take precedence over this Output Slew Rate setting.

      + +
        + +

      • FF Initial State -- Sets + the initial state for all Flip-Flops.  The + options are Low, High and FPGA.

        • + +

      • Collapsing + P-Term Limit -- This option + controls the degree to which the fitter flattens a design netlist. A logic + gate can collapse forward into a subsequent gate only if the number of + product terms in the resulting logic function does not exceed the p-term + limit. If the path delay of a logic function is not acceptable, increase + the p-term limit to allow the larger functions to be further flattened. + Choose a number from 3 to 48.

        • + +

      • Collapsing + Input Limit -- This is a + secondary option for controlling the degree to which the fitter flattens + a design netlist. A logic gate can collapse forward into a subsequent + gate only if the number of inputs in the resulting logic function does + not exceed the input limit. If the design fails to fit the target device + because flattening uses up too many of the function block inputs, decrease + the input limit to prevent flattening of certain high fan-in functions. +  

        • +
      + +

      XPLA Advanced + Options

      + +

      The + following options are available under XPLA Implementation + Options, Advanced tab.

      + +
        + +

      • Enable Fast + Input Registers -- Enables the use + of the Fast Input path in XPLA3 devices.

        • + +

      • Enable Use + of Foldback NANDs -- When selected, + the software will use foldback NANDs. This increases the capability to + fit a design, sometimes at the expense of speed.

        • + +

      • Reserve JTAG Pins for ISP -- Checking + this box will instruct the fitter to reserve JTAG pins.

        • +
      + +

      CoolRunner-II + Advanced Options

      + +

      The following + options are found under the Advanced tab for CoolRunner-II devices.

      + +
        + +

      • Use + Global Clock(s) -- Select this option + to allow the fitter to assign input pins used as clocks to dedicated global + clock (GCK) pins of the device. If this option is disabled, only pins + identified with the BUFG=CLK property in the design (or UCF file) will + be assigned to GCK device pins. By default, this option is on. +

        • + +

      • Use Global Output Enable(s) -- Select + this option to allow the fitter to assign input pins used as output enable + control to dedicated global OE (GTS) pins of the device. If this option + is disabled, only pins identified with the BUFG=OE property in the design + (or UCF file) will be assigned to GTS device pins. By default, this option + is on.

        • + +

      • Use Global Set/Reset -- Select this + option to allow the fitter to assign input pins used as register asynchronous + reset or preset control to the dedicated global set/reset (GSR) pin of + the device. If this option is disabled, only a pin identified with the + BUFG=SR property in the design (or UCF file) will be assigned to the GSR + device pin. By default, this option is on.

        • + +

      • Enable Fast Input Registers -- Enables + fast input registers.

        • + +

      • Ignore DATA_GATE Attributes -- Data + Gate is a power saving property that can be used in CoolRunner-II designs. +  This option + allows you to turn Data Gate off in case you want the fitter to ignore + data gate.

        • + +

      • Tristate Outputs Termination Node -- + The Tristate Output Termination Mode globally sets all tristate outputs + to the specified termination mode. By default, this field is set to Pullup.. +  The options + are Pullup, Keeper and Float.

        • + +

      • Create Programmable Ground Pins on Unused I/O + -- The Create Programmable GND Pins on Unused I/O property controls the + option to indicate that you want all unused I/O pads to be configured + as ground pins. This can reduce ground bounce. By default, this option + is set to ground.  The + options are Ground, Pullup, Keeper and Float.

        • + +
      • +

        Default + Output Voltage Standard -- set a default voltage standard for CoolRunner-II + device pins.

        + +

        IOSTANDARD + names supported by CoolRunner-II are:

        + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
        +

        I/O Standard

        		 +

        VCCIO

        		 +

        Input VREF

        		 +

        Board Termination Voltage (VTT)

        +

        LVTTL

        		+

        3.3V

        		 +

        N/A

        		 +

        N/A

        +

        LVCMOS33

        		 +

        3.3V

        		 +

        N/A

        		 +

        N/A

        +

        LVCMOS25

        		 +

        2.5V

        		 +

        N/A

        		 +

        N/A

        +

        LVCMOS18

        		 +

        1.8V

        		 +

        N/A

        		 +

        N/A

        +

        LVCMOS15

        		 +

        1.5V

        		 +

        N/A

        		 +

        N/A

        +

        HSTL_I

        		 +

        1.5V

        		 +

        0.75V

        		 +

        0.75V

        +

        SSTL2_I

        		 +

        2.5V

        		 +

        1.25V

        		 +

        1.25V

        +

        SSTL3_I

        		 +

        3.3V

        		 +

        1.5V

        		 +

        1.5V

        + +

        The software + automatically groups outputs with similar IOSTANDARD settings into the + same bank when no location constraints are specified.

        +
        • +
      + +

      XC9500/XL/XV + Advanced Options

      + +

      The following + options are found under the Advanced tab for XC9500/XL/XV.  Note + that additional options for XC9500 only are also described below.

      + +
        + +

      • Use + Global Clock(s) -- Select this option + to allow the fitter to assign input pins used as clocks to dedicated global + clock (GCK) pins of the device. If this option is disabled, only pins + identified with the BUFG=CLK property in the design (or UCF file) will + be assigned to GCK device pins. By default, this option is on. +

        • + +

      • Use Global Output Enable(s) -- Select + this option to allow the fitter to assign input pins used as output enable + control to dedicated global OE (GTS) pins of the device. If this option + is disabled, only pins identified with the BUFG=OE property in the design + (or UCF file) will be assigned to GTS device pins. By default, this option + is on.

        • + +

      • Use Global Set/Reset -- Select this + option to allow the fitter to assign input pins used as register asynchronous + reset or preset control to the dedicated global set/reset (GSR) pin of + the device. If this option is disabled, only a pin identified with the + BUFG=SR property in the design (or UCF file) will be assigned to the GSR + device pin. By default, this option is on.

        • + +

      • Create Programmable Ground Pins on Unused I/O + -- Select this option to indicate that you want all unused I/O pads to + be configured as ground pins. This can reduce ground bounce. By default, + this option is off.

        • + +

      • Macrocell Power Setting -- Use this + option to control device power consumption. Select Low or Standard to + set the default power mode for the macrocells used to implement the design. + Select Timing Driven to automatically reduce power on paths covered by + timing specifications that can meet speed requirements while operating + in low power. The default is Standard, which results in highest speed.

        • +
      + +

      Note: Any explicit power control (PWR_MODE) + properties in the design or constraints file take precedence over this + Macrocell Power Setting.

      + +
        + +

      • Enable FASTConnect/UIM Optimization (XC9500 + only) -- Enables optimization of the FASTConnect/UIM for XC9500 + devices.

        • + +

      • Use + Local Feedback (XC9500 only)

        • +
      + +

      Select this option to enable the software + to use local macrocell feedback whenever possible. The local feedback + path, running from each macrocell output to an input of the same function + block, has shorter propagation delay than the global feedback path. The + fitter always tries to use local macrocell feedback (if possible) to satisfy + timing constraints. This option allows the fitter to use local feedback + to generally improve timing on remaining paths. Using local feedback can + speed up your design but could also make it difficult to maintain the + same timing after a design change. By default, this option is on.

      + + + +
      + + +

      Note: + To force the fitter to use local feedback, manually map both + the source and load functions into the same function block using the property + LOC=FBnn, + then apply a timespec across the path. 

      + + + +
      + + +

      Note: + The XC9536 device does not have local feedback.

      + + + +
      + + +
        + +

      • Use + Pin Feedback (XC9500 only)

        • +
      + +

      Select this option to enable the software + to use I/O pin feedback whenever possible. The pin feedback path has slightly + shorter propagation delay than the global feedback path. If this option + is enabled, the software uses the pin feedback path instead of the global + feedback path for macrocell signals that do not drive 3-state outputs + or slew-rate-limited outputs, and where the associated I/O pin is not + used as input-only. By default, this option is on.

      + + + + diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/paths.js b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/paths.js new file mode 100644 index 0000000..ff4aa89 --- /dev/null +++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/paths.js @@ -0,0 +1,39 @@ +rootURL = "http://www.xilinx.com/"; +prodURL = "xlnx/xil_prodcat_product.jsp?title="; +cpldURL = "CPLD+Products"; +acr2URL = "coolrunner2_page"; +xbrURL = "coolrunner2_page"; +xpla3URL = "xpla3_page"; +xc9500URL = "xc9500_page"; +xc9500xlURL = "xc9500xl_page"; +xa9500xlURL = "xc9500xl_page"; +xc9500xvURL = "xc9500xv_page"; +marketURL= "esp"; +supportURL = "http://www.support.xilinx.com/"; +educationURL = "support/education-home.htm"; +buyURL = "http://toolbox.xilinx.com/cgi-bin/xilinx.storefront"; +contactURL = "company/contact.htm"; +searchURL = "company/search.htm"; + +docURL = rootURL + "support/documentation/"; +doc95URL = docURL + "xc9500.htm"; +doc95xlURL = docURL + "xc9500xl.htm"; +docA95xlURL = docURL + "xc9500xl.htm"; +doc95xvURL = docURL + "xc9500xv.htm"; +docXpla3URL = docURL + "coolrunner_xpla3.htm"; +docAcr2URL = docURL + "coolrunner-ii.htm"; +docXbrURL = docURL + "coolrunner-ii.htm"; +docCr2sURL = docURL + "coolrunner-ii.htm"; + +var messages = new Array(); +messages["fastinreg"] = "Direct Input Register"; +messages["inreg"] = "Direct Input Register"; +messages["fbnand"] = "Foldback NAND"; +messages["fcnode"] = "FC node"; +messages["LATCH"] = "Transparent latch"; +messages["DFF"] = "D-flip-flop"; +messages["DEFF"] = "D-flip-flop with clock enable"; +messages["TFF"] = "T-flip-flop"; +messages["TDFF"] = "Dual-edge-triggered T-flip-flop"; +messages["DDFF"] = "Dual-edge-triggered flip-flop"; +messages["DDEFF"] = "Dual-edge-triggered flip-flop with clock enable"; diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/pin.gif b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/pin.gif new file mode 100644 index 0000000000000000000000000000000000000000..f110f3df4f08db5e7b03c33b102290f713d6f6ce GIT binary patch literal 3093 zcmeH`_d6R37spFmSG8tUjiM+uiz3#g)2Q96R;#UEGh$WM2p7HfjoBfjMi4|otV-(#5vjTT!J0J1sW-ZcLRDEFM{t8p5~a8`#) zYYCK+s_h7e57Aai(>OoV`XmS(Gt=<;=Z0tqZs%K>50flvCiv%E8;DooMWdCK*|&TSLph+NEZ!Xat_6O-sRziqcYMWT?%mOG_e5lT$kkj|YOnjtXj*36T+FbX z?1)bZwM#7adaOM>R^oiTK+wgzn%OZ6b@XfqH9=M^;d&kt8gzRFDHWg|-tp?G7){nC z>0VCHT&giP0O9=zP%@mNp1HR4k?#>OJ?V)XY4ZIHaJ}$>)qu+~)Wz0~qQyTz&(Q_g=@durMF&SyY5Yq0ptxOp}G2FB?FG+?oY22-8T0O?r9h zOcj9*IMDMM&tLVXzU%_@EWc<4YnNMSHzJjvHCddAK^3g`EM}vYx$V|&2Z)rY+VX*Jmc6w$NZ9nJf%1tD( zXlJ}&)P8x>4i{xNKo!IO~-%Md||UI>wIx%^ta+y>G?KjLFI1Ze|B=x@ki`crKcuQ#&6sNTM$!YLfRCQ;lvN zEPb@|Iatnc#~iF=1(6R{;pN%;Yw^(V{dGh^@@i#KF&VsBfxZ}C%PS2`2$tNM>#xU zg~54pppSW}%uq~A(WmWx$kz8JPcU6hfScta!!P!}GuMJ7PcB%2+015HSkB$8QuNcM zhxUSGWbtS3D~EBr!1q`)S~um&Bl|buMz`40IXH%*r4r%noCR%jF{vPx{(&(*L1|XK zekU#h_uCs3b!26HoLs0?JCi^4%Pn53>lYV=cwPtR9#eP>Ed&1Kkpgr`a-ECe=e56t z3(gUW-8BR(Q(NyO&BR3sXP}|u3D5l?erd6&V0D`+$fvTUr!tI@ zmMiiX((wL8a?gwb!X|1GH^RPaQe!nV{u z$utOAu4|~lsEP5qWA4m>u-NlC;XjM@#vDv&+trb*&uzE=q}P*FDS2E;9@h3ZAIAeI z`2s}bT=KG<{o5zDl^p9v1~B>e7*B+(641mFHIkkqpQn;kV&-l#3Y(%7X%R~-g8D{t z4k^WVIZ;+|CSUV~sYqjU)E`iJ9S2ov$#k2CL9zT8$}=GUV&R4j4mE~(`ZjxRVZ*Ll ze!R*@9qmFzIgIw%BK@9d_$8qoS4}4Br>K}9ieF&eb&}bKky+DQ{*J-CyBPWstfPXzhH&;lyLd96McOmF_O{ioGZP10B&>&o2ybADVTKQH!iGY$ zrC}s{H*ueX{%iyy_fg#ft;zmly1roH8(CMmsSu-o0xRy*V}KmI4%*V7YM6Uwm-Q-= z;51rUpz3DEsaD<9K!YYm5Z9c33Xf=WeW^Sc18HAo^b!OBa;97NJe&`wfMOch;zk3< z>Hh9}v65|F<^=t=S`y;mi!e?PRN~F(QO&`EReM%F2tCv7XM+m1l_UcQ^wA@($EeRj zyP;Ckgv7F-R^_FgW7e#%p*Of2jfmcE+zq{vv9yemB3Fy%o*8U2we?NemLjNOk^k^& zO`q$y--A1jMAb`mUwGdxuq%YktBD-o7O%NvNg-=fW z$`y@z4^ghA934>wjsdN~ve|WBj=$d7-AO>{YSOR)f5j*XFea301I1mB*A4?qM+&|M zGGnsath#+;7Rf(QB3QCUNGM|PR@)b4==$xZhB!KTsf-}HzD{L$u?!L$)#`^H#f8Q3 zh+B6;vNyj8`)%)=9FBZGp&%`rHVFE7EQ(6Sr0A`5V#lZ2XK7WrSI9vTjM;{q{5o#^ totOw)q%d>8$Flhcbns|Jmw7Oh(o89~Jl=T5Je(YCrs42)k!Q~6{ts)#@;m?l literal 0 HcmV?d00001 diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/pin_legXC95.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/pin_legXC95.htm new file mode 100644 index 0000000..db88bcb --- /dev/null +++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/pin_legXC95.htm @@ -0,0 +1,13 @@ +
      +Legend :  NC  = Not Connected, unbonded pin
+         PGND = Unused I/O configured as additional Ground pin
+         TIE  = Unused I/O floating -- must tie to VCC, GND or other signal
+         VCC  = Dedicated Power Pin
+         GND  = Dedicated Ground Pin
+         TDI  = Test Data In, JTAG pin
+         TDO  = Test Data Out, JTAG pin
+         TCK  = Test Clock, JTAG pin
+         TMS  = Test Mode Select, JTAG pin
+         PE   = Port Enable pin
+  PROHIBITED  = User reserved pin
+
      diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/pin_legXbr.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/pin_legXbr.htm new file mode 100644 index 0000000..00a6d2c --- /dev/null +++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/pin_legXbr.htm @@ -0,0 +1,21 @@ +
      +Legend :  NC  = Not Connected, unbonded pin
+        PGND  = Unused I/O configured as additional Ground pin
+         KPR  = Unused I/O with weak keeper (leave unconnected)
+         WPU  = Unused I/O with weak pull up (leave unconnected)
+         WPD  = Unused I/O with weak pull down (leave unconnected)
+         TIE  = Unused I/O floating -- must tie to VCC, GND or other signal
+         VCC  = Dedicated Power Pin
+      VCCAUX  = Power supply for JTAG pins
+   VCCIO-3.3  = I/O supply voltage for LVTTL, LVCMOS33, SSTL3_I
+   VCCIO-2.5  = I/O supply voltage for LVCMOS25, SSTL2_I
+   VCCIO-1.8  = I/O supply voltage for LVCMOS18
+   VCCIO-1.5  = I/O supply voltage for LVCMOS15, HSTL_I
+        VREF  = Reference voltage for indicated input standard
+         GND  = Dedicated Ground Pin
+         TDI  = Test Data In, JTAG pin
+         TDO  = Test Data Out, JTAG pin
+         TCK  = Test Clock, JTAG pin
+         TMS  = Test Mode Select, JTAG pin
+  PROHIBITED  = User reserved pin
+
      diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/pin_legXpla3.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/pin_legXpla3.htm new file mode 100644 index 0000000..8dad55d --- /dev/null +++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/pin_legXpla3.htm @@ -0,0 +1,13 @@ +
      +Legend :  NC  = Not Connected, unbonded pin
+          PE  = Port Enable pin
+         WPU  = Unused with Internal Weak Pull Up
+         TIE  = Unused I/O floating -- must tie to VCC, GND or other signal
+         VCC  = Dedicated Power Pin
+         GND  = Dedicated Ground Pin
+         TDI  = Test Data In, JTAG pin
+         TDO  = Test Data Out, JTAG pin
+         TCK  = Test Clock, JTAG pin
+         TMS  = Test Mode Select, JTAG pin
+  PROHIBITED  = User reserved pin
+
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ztEkbIj6t_cN1f6NX8viBO~J0DCp96yW00;s_nJm zjp1IeUh&boKTGRQTXyH1;h z3y0#_t^3jIN+!N)jJV#ifB62$wzYCRkq)qh4!dW+|9WqGaKJ0NaN0fRo+05<JB0wZb(JY076sR0HK!{Lb zLWU0;E{y147pjU5EADbIX=6u@89jysd9WZ!f&x(;1o;tFGm5B^I5;^_rh_CFJ4%GO z(_zDj5^K6FNzmoZq68F1I8UvIBfOx3l)lnrP8o(z{L zb5pVvZaDIBn5AKck4<~|SK6jc(lm|MAX};k;Kz@@ zS|e|suVokZ>lHs|`Tui6=(4GrBWWS!R0^sz>?$hCp~~7~jxPyaE36@w5OWK%!Z`Ge zF$5K3X+Y7yv#UDtHk}4byLoiP6`h>TETNbf?av#wJ=p-WvD-i z^t?9S|LsQDI^vefLOJ6p$b(T6kWco2iq<>7dO^gF!@!WQGUB+mBS+BSyQ)1N`jkVcaCD)X^$&2loYR^0`vYL4sj za4Cx)eDa`P;qEZoO*y`hWgd@3duhjv9#CS=lw>PnTbD)G#40Hkx^6cu{P|=tDLOIa zC>vvPmA&?~x{}*|4dp}d+ltDAiQ|CO7wMZ7TQ_ogR$3~^8N%TxNyg!kx z@TH6iAbop?(!lQ#z4K#`4C&uP947?n9ksq7*5)Oo}pIR`uti4V;*PO8$Q-Qb$XMztm~3JP zBom4VRt}TY3w39}-%RjcV)PcQ;KZfqK(0eu>j;@72({#mD2$=0k&1}7IB89(axI}B zL+(_No1r3S5)@$+|24xB^1QBY>{Ar&xHC72L~C!q0TvS(WXCefP<2D3q5m%8lzsir zc_As)(*WqKRW0RGToM-Ex;2pqj;&6cL=pyhRkPOUuTyt>(+sU*lx6j8VYCTc;uM&; z7qX^+O7r9^)AuQj1m)=klbs1c!W*o35t)?YVL|K?9>g)Jd{T6$V2%gC9!`!rr!*M?BeS>l@Tq48 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z9OMkO2X;d5qf#t)_B6gMWHTqPDm+tP>}D$ENmz|#-~3Hpx%BBIl~*s;qC$@05Nb8b ziF3LJDaL3q7$sM(W^$JGCjw5-G;_*e2>06bWT6Bmw5+Q7mAF#%d`dD~El^6u0&D0M zr9yUM|1eo|qGffp<;=20pH4>a#+B44p9Tj;XvJz7)y$l3+VE9aG%}&$#Wf(d^I!-x zbTvZj&{`+-T6vaLLABaYgh)!wLUGMu|DYp7J|#M4&2HQfYr3LEqbzWzXY2Z zxi@~@cYWRN0p{QVS*X;&WbNTdqt|)q~=ufDsA*>ey8iH3A zLV_Rfy*7d@$ii1H_%0`qFfiC=|2}ipoVGqh)eh*KrwUI_S-l&O5IeRq!@~)n1dQv zAs*NvBp8N!xPwLbHZ+*g@H2_O7=(%BgG+c|ws->7xQo}AS5i)@rizD6n2YO}jqSLN z?>LO-qat*eju(P|^}s36n1~sIg4sAB5LtuU&S(_)kv%A>*h6h8*(zSx0kT+;XE>3) zn9;xh1m0$UgRaq-Q@d4~tmRWdz8Nd@o*pM|D zmQ@*-X*q-qxQY9tfhyUU|7+ulQ6ZB{n2w=&L&um`czK$4rJ75bn9-P;?Kqkz(3`ng zjuSwOueqDe`J2xCf`l^rGsYWDwqIMeeY>~CIv@Z5J3CUs;s5{u literal 0 HcmV?d00001 diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/pinlegend.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/pinlegend.htm new file mode 100644 index 0000000..26f2262 --- /dev/null +++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/pinlegend.htm @@ -0,0 +1,150 @@ + + + + + + + +

      Legends

      +
      + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
      AcronymBrief Description
       CLK Clock
       GCK0 Global Clock 0
       GCK1 Global Clock 1
       GCK2 Global Clock 2
       GND Ground
       GSR Global Set/Reset
       GTS0 Global Output Enable 0
       GTS1 Global Output Enable 1
       GTS2 Global Output Enable 2
       GTS3 Global Output Enable 3
       I/O Input/Output
       INIT Initial state
       ISP In system programmable
       JTAG Joint Test Action Group
       KPR Unused I/O with weak keeper
       NC No Connects
       PGND Programmable ground pin
       PROHIBITED User reserved pin
       R Reset
       S Set
       TCK Test clock
       TDI Test data input
       TDO Test data output
       TIE Unused I/O floating
       TMS Test mode select
       LVCMOS Low Voltage CMOS 3.3 Volts
       LVCMOS25 Low Voltage CMOS 2.5 Volts
       LVCMOS33 Low Voltage CMOS 2.5 to 3.3 Volts
       LVTTL Low Voltage TTL 3.3 Volts
       VCCIO Input/Output Supply Voltage
       VCC Power internal
       WPU Weak Pull Up
      + + +
      + + diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/pinlegendV.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/pinlegendV.htm new file mode 100644 index 0000000..577547a --- /dev/null +++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/pinlegendV.htm @@ -0,0 +1,150 @@ + + + + + + + +

      Legends

      +
      + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
      AcronymVerbose Description
       CLK Global Clock
       GCK0 Global clock zero
       GCK1 Global clock one
       GCK2 Global clock two
       GND Dedicated Ground Pin
       GSR Global set-reset
       GTS0 Global tristate zero (output enable)
       GTS1 Global tristate one (output enable)
       GTS2 Global tristate two (output enable)
       GTS3 Global tristate three (output enable)
       I/O Input/Output
       INIT Initial state
       ISP The use of the JTAG port to program the chip while it is powered in a system.
       JTAG IEEE Standard 1149 (JTAG) boundary-scan test standard.
       KPR Unused I/O with weak keeper (leave unconnected)
       NC Not Connected, unbonded pin
       PGND Programmable ground pin
       PROHIBITED User reserved pin
       R Reset
       S Set
       TCK One of four terminals required by (JTAG) IEEE Std 1149 or IEEE Std 1532. Test operations of the device are synchronous to TCK. Data is captured on the rising edge of TCK and outputs change on the falling edge of TCK. An internal pull-up forces TCK to a high level if left unconnected.
       TDI One of four terminals required by (JTAG) IEEE Std 1149 or IEEE Std 1532. It is the serial input for shifting data through the instruction register or selected data register. An internal pull-up forces TDI to a high level if left unconnected.
       TDO One of four terminals required by (JTAG) IEEE Std 1149 or IEEE Std 1532. It is the serial output for shifting data through the instruction register or selected data register. An internal pull-up forces TDI to a high level when it is not driven from an external source.
       TIE Unused I/O floating -- must tie to VCC, GND or other signal
       TMS One of four terminals required by (JTAG) IEEE Std 1149 or IEEE Std 1532. It directs the device through its Test Access Port controller states. An internal pull-up forces TDI to a high level when it is not driven from an external source. TMS also provides the optional test reset signal of IEEE Std 1149 or IEEE Std 1532.
       LVCMOS Low Voltage Complementary Metal Oxide Semiconductor 3.3 Volts
       LVCMOS25 External I/O supply voltage for LVCMOS25
       LVCMOS33 External I/O supply voltage for LVCMOS33
       LVTTL Low Voltage Transistor Transistor Logic 3.3Volts
       VCCIO External power for Inputs/Outputs
       VCC Dedicated Power Pin, Internal supply voltage for the device
       WPU Unused I/O with Internal Weak Pull Up (leave unconnected)
      + + +
      + + diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/pins.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/pins.htm new file mode 100644 index 0000000..503aaa4 --- /dev/null +++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/pins.htm @@ -0,0 +1,741 @@ + + + + + + +

      Pin List

      + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
      Pin NumPin TypeAssigned Signal
      1VCCIOVCC
      2I/O/GTS3D<0>
      3I/O/GTS4KPR
      4I/OKPR
      5I/O/GTS1KPR
      6I/O/GTS2KPR
      7I/OKPR
      8VCCINTVCC
      9I/OKPR
      10I/OKPR
      11I/OKPR
      12I/OKPR
      13I/OKPR
      14I/OD<6>
      15I/OD<3>
      16I/OD<7>
      17I/OD<1>
      18GNDGND
      19I/OD<8>
      20I/OD<5>
      21I/OD<4>
      22I/OIDE_CS<0>
      23I/OIDE_CS<1>
      24I/OIDE_A<0>
      25I/OIDE_A<2>
      26I/OIDE_A<1>
      27I/OIDE_R
      28I/OIDE_W
      29GNDGND
      30I/O/GCK1KPR
      31I/OKPR
      32I/O/GCK2KPR
      33I/OKPR
      34I/OKPR
      35I/OROM_OE
      36GNDGND
      37VCCIOVCC
      38I/O/GCK3KPR
      39I/OD<2>
      40I/OD<9>
      41I/OD<10>
      42VCCINTVCC
      43I/OD<11>
      44I/OD<12>
      45I/OD<13>
      46I/OD<14>
      47GNDGND
      48I/OD<15>
      49I/OA<5>
      50I/OA<4>
      51I/OA<6>
      52I/OA<3>
      53I/OKPR
      54I/OA<2>
      55VCCIOVCC
      56I/OKPR
      57I/OA<1>
      58I/OA<9>
      59I/OA<10>
      60I/OA<11>
      61I/OA<12>
      62GNDGND
      63TDITDI
      64I/OA<13>
      65TMSTMS
      66I/OKPR
      67TCKTCK
      68I/OROM_B<0>
      69I/OROM_B<1>
      70I/OKPR
      71I/OKPR
      72GNDGND
      73VCCIOVCC
      74I/OKPR
      75I/OAUTOBOOT_OFF
      76I/OKPR
      77I/OKPR
      78I/OKPR
      79I/OKPR
      80I/OAS
      81I/OUDS
      82I/OKPR
      83I/ORW
      84VCCINTVCC
      85I/ODTACK
      86I/OA<23>
      87I/OA<22>
      88I/OA<21>
      89GNDGND
      90GNDGND
      91I/OA<20>
      92I/OA<19>
      93I/OKPR
      94I/OA<18>
      95I/OA<17>
      96I/OKPR
      97I/OA<16>
      98I/OBERR
      99GNDGND
      100I/OKPR
      101I/OKPR
      102I/OC3
      103I/OC1
      104I/OKPR
      105I/OKPR
      106I/OKPR
      107I/OKPR
      108GNDGND
      109VCCIOVCC
      110I/OKPR
      111I/OKPR
      112I/OKPR
      113I/OKPR
      114GNDGND
      115I/OKPR
      116I/OKPR
      117I/OKPR
      118I/OKPR
      119I/OKPR
      120I/OKPR
      121I/OKPR
      122TDOTDO
      123GNDGND
      124I/OKPR
      125I/OKPR
      126I/OKPR
      127VCCIOVCC
      128I/OKPR
      129I/OKPR
      130I/OKPR
      131I/OKPR
      132I/OKPR
      133I/OKPR
      134I/OKPR
      135I/OKPR
      136I/OKPR
      137I/OKPR
      138I/OKPR
      139I/OKPR
      140I/OKPR
      141VCCINTVCC
      142I/OKPR
      143I/O/GSRRESET
      144GNDGND
      + + +
      + +
      + + diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/pins.js b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/pins.js new file mode 100644 index 0000000..591e563 --- /dev/null +++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/pins.js @@ -0,0 +1,62 @@ +var specSig = new Array(); +var pins = new Array(); +var pinsAssign = new Array(); +var prohibit = new Array(); +var unusedStr = "WPU"; +var gndStr = "GND"; +var vccStr = "VCC"; +var tdiStr = "TDI"; +var tdoStr = "TDO"; +var tmsStr = "TMS"; +var tckStr = "TCK"; + +function showPin(pin) { parent.leftnav.showAppletPin(pin); } + +function printPage() { window.print(); parent.leftnav.printAppletPkg(); } + +function showEqn(signal) { parent.leftnav.showEqn(signal); } + +function updatePin(type) { + with (document.options) { + switch (type) { + case 0: + if (inp.checked) parent.leftnav.document.options.inOn.value = 1; + else parent.leftnav.document.options.inOn.value = 0; + break; + + case 1: + if (out.checked) parent.leftnav.document.options.outOn.value = 1; + else parent.leftnav.document.options.outOn.value = 0; + break; + + case 2: + if (glb.checked) parent.leftnav.document.options.glbOn.value = 1; + else parent.leftnav.document.options.glbOn.value = 0; + break; + + case 3: + if (isp.checked) parent.leftnav.document.options.ispOn.value = 1; + else parent.leftnav.document.options.ispOn.value = 0; + break; + + case 4: + if (vcc.checked) parent.leftnav.document.options.vccOn.value = 1; + else parent.leftnav.document.options.vccOn.value = 0; + break; + + case 5: + if (gnd.checked) parent.leftnav.document.options.gndOn.value = 1; + else parent.leftnav.document.options.gndOn.value = 0; + break; + + case 6: + if (unuse.checked) parent.leftnav.document.options.unuseOn.value = 1; + else parent.leftnav.document.options.unuseOn.value = 0; + break; + } + } + + parent.leftnav.showPinOut(); +} + +function showLegend(url) { parent.leftnav.showLegend(url, 650, 350); } diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/pinsdoc.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/pinsdoc.htm new file mode 100644 index 0000000..9da2708 --- /dev/null +++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/pinsdoc.htm @@ -0,0 +1,265 @@ + + + + + + + + + + +Pin List + + + + + + + + + + + + + + + + + + + + + + + + +

      Pin List

      + +

      The Pin List + page lists each pin of your design with its pin type and associated signal. +  Check boxes + at the top of the table allow you to select and deselect which pin types + you want displayed in the table (the default view will display all of + them).

      + +

      Note: +  There is + a button below the table.  Click + this button to open a new window describing all of the acronyms used in + the function block table.  You + can select either brief descriptions or more detailed descriptions by + clicking the "Verbose" button at the top of the window.

      + +Clicking + on the underscored pin numbers in the first column of the table will open + a new window displaying the pin layout diagram for the selected pin.  Rolling + your mouse over the colored pin will pop up a tooltip with the signal + name assigned to the pin, the I/O standard,  the + I/O style, the slew rate, and/or any constraints assigned to the pin: + + +

      + +

      Clicking any underscored signal in the + third column of the table will open a new window displaying the equations + for that particular signal.

      + +

      Clicking on the button + at the top of the screen will open a new window with a graphical, top + view of all of the pins:  

      + +

      + +

      They are color-coded as follows:

      + + + +++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
      +

      Color

      		 +

      Signal

      +

      Green

      		 +

      Input

      +

      Aqua

      		 +

      Bidirectional

      +

      Blue

      		 +

      Output

      +

      Magenta

      		 +

      Clock

      +

      Red

      		 +

      VCC

      +

      Black

      		 +

      GND

      +

      Yellow

      		 +

      TDO

      +

      Gray

      		 +

      TDI

      +

      White

      		 +

      Unused Pin

      +

      Black Outline

      		 +

      No available + Pad

      + +

      As with the single pin display, rolling + your mouse over any colored pin will pop up a tooltip with the signal + name assigned to the pin, the I/O standard,  the + I/O style, the slew rate, and/or any constraints assigned to the pin.

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      Summary

      + + + + + + + + + + + + + + + + + + + + + +
       Design Name + LAN_IDE_CP
       Fitting Status + Successful
       Software Version + P.68d
       Device Used + XC95144XL-10-TQ144 +
       Date + 12-15-2016, 7:48PM

      RESOURCES SUMMARY
      + + + + + + + + + + + + + + + +
      Macrocells UsedPterms UsedRegisters UsedPins UsedFunction Block Inputs Used
      51/144  (36%)179/720  (25%)26/144  (19%)54/117  (47%)134/432  (32%)

      PIN RESOURCES
      + + + +
      + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
      Signal TypeRequiredMapped
       Input 26 26
       Output 19 19
       Bidirectional 8 8
       GCK 0 0
       GTS 0 0
       GSR 1 1
      		 + + + + + + + + + + + + + + + + + + + + + + + + + +
      Pin TypeUsedTotal
       I/O  + 52 110
       GCK/IO 0 3
       GTS/IO 1 4
       GSR/IO 1 1

      GLOBAL RESOURCES
      + + + +
       Signal mapped onto global output enable net (GSR) RESET

      POWER DATA
      + + + + + + + + + + + + + +
       Macrocells in high performance mode (MCHP) 51
       Macrocells in low power mode (MCLP) 0
       Total macrocells used (MC) 51
      + + +
      + + diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/summary.js b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/summary.js new file mode 100644 index 0000000..8702822 --- /dev/null +++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/summary.js @@ -0,0 +1,28 @@ +function popWin(url, w, h) { + var win = window.open(url, 'win', + 'toolbar=no,location=no,directories=no,status=no,menubar=no,scrollbars=yes,resizable=yes,width='+w+',height='+h); + win.focus(); +} + +function showTop() { parent.leftnav.showTop(); } + +function showDoc(device) { + var url = docURL; + + if ((device.indexOf("XC2") != -1) && (device.indexOf("S") != -1)) + url = docCr2sURL; + else if (device.indexOf("XC2") != -1) url = docXbrURL; + else if (device.indexOf("XA2") != -1) url = docAcr2URL; + else if (device.indexOf("XCR3") != -1) url = docXpla3URL; + else if (device.indexOf("XV") != -1) url = doc95xvURL; + else if (device.indexOf("XL") != -1) url = doc95xlURL; + else if (device.indexOf("XA") != -1) url = doc95xaURL; + else url = doc95URL; + + popWin(url); +} + +function priceDev(device) { + var url = "http://toolbox.xilinx.com/cgi-bin/xilinx.storefront/1816638537/Catalog"; + popWin(url); +} diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/summarydoc.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/summarydoc.htm new file mode 100644 index 0000000..607f637 --- /dev/null +++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/summarydoc.htm @@ -0,0 +1,205 @@ + + + + + + + + + + + + + + + Summary + + + + + + + + +

      +Summary

      + +
      The +Summary section of the HTML report contains several tables summarizing +the fitting results for your design. +
       
      +The Header +table contains the following:  +
        +
      • +The Design +Name
        • + +
      • +The Fitting +Status, which is one of  the following:
        • + +
          +
        • +Successful
          • + +
        • +Design Rule Checking Failed
          • + +
        • +Placement Failed
          • + +
        • +Routing Failed
          • +
        + +
      • +The Software +Version 
        • + +
      • +The Device +Used, with a link to a PDF version of the device documentation
        • + +
      • +The Date +and time of completion
        • +
      +The Resources +Summary table includes: +
        +
      • +The number +and percentage of macrocells used vs total in device 
        • + +
      • +The number +and percentage of product terms used vs total in device 
        • + +
      • +The number +and percentage of registers used vs total in device 
        • + +
      • +The number +and percentage of pins used vs total in device 
        • + +
      • +The number +and percentage of function block inputs used vs total in device 
        • +
      +The Pin +Resources table includes two tables: +
        +
      • +The first +table indicates the requirements of the design, broken up by Signal Type. +The number required and the number mapped onto the device are indicated +for each signal type.
        • + +
      • +The second +table gives the total number of each pin type available in the device, +alongwith the number used.
        • +
      +XPLA3 +only - The Local Control Term Resources table lists the local +control term mapping for each function block: +
        +
      • +Each row +lists the local control term mapping for each of the eight control terms, +LCT0-LCT7, in a function block.
        • + +
      • +The control +term mapping can be:
        • + +
          +
        • +ce - clock +enable
          • + +
        • +clk - clock
          • + +
        • +ee - output +enable
          • + +
        • +sr - set/reset
          • + +
        • +uct1 - universal +control term clock
          • + +
        • +uct2 - universal +control term output enable
          • + +
        • +uct3 - universal +control term set
          • + +
        • +uct4 - universal +control term reset
          • +
        + +
      • +Each LCT +can have some subset of the signals above mapped onto them:
        • + +
          +
        • +LCT0 - sr, +oe
          • + +
        • +LCT1 - sr, +oe
          • + +
        • +LCT2 - sr, +oe
          • + +
        • +LCT3 - sr
          • + +
        • +LCT4 - ce, +clk, sr
          • + +
        • +LCT5 - clk, +sr
          • + +
        • +LCT6 - clk, +oe
          • + +
        • +LCT7 - clk, +uct1/uct2/uct3/uct4
          • +
        +
      +The Global +Resources table indicates the signals used as global signals in the +device. +

      XC9500/XL/XV +only - The Power Data table indicates the number of macrocells +in standard and low power mode. +

      XPLA3 +only - The Block Resources table indicates the number of function +block control terms used vs available and the number of foldback NANDs +used vs available. + + diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/support.gif b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/support.gif new file mode 100644 index 0000000000000000000000000000000000000000..a154620eb23ea85665f2a9d925132d1cb474dbdb GIT binary patch literal 760 zcmVr;Hg@0hXyRRA=8o0Qvv9YC1O-({V zLLeX@C@3g2G&ECFQ&?D7P*6~4W?$66WbxT$te;|XZeJxOC46^akB4EQp_JXoWHB)@ zz_4SJlY_mzvK}5DiHUimm|~faVWgy&oSck$dTi&>Wy-i?si~VwOG`aHJvur%v$LnP zw5df!MM+6XFE1~yuA#Q4Vn9GZR#sM8T2Q&UtzltTXlPrxxvqbIaZyo7baZDJu-SE}PHjv>IXKwhTUld`_?1@A$mF&RTpHfPsR8goTEOh=VK^j1~-!kdcy;l$Dm3 zkSs8p8ygLuprN9pq@|{(4I42ltSTxq3bC@Yw6(UkxVSSaF)j)&E-xtw#Kp$P$jQpf z%PB7?&M7?*4g=QL*xB0K+}+&{5GW7{)HDwP=;`X~?CtLF?+-L6;ML~<`1$(#{Qds_ z{{lQ1QE$LKfCv*R>?bfo!Gi!U5XcvSKm>dQDpVwp5#Pp+`Yu$U$dTj4k|p&CB=Il+ zfCv%<2$+BY0099L0SKUQQ>Fm_4mN%M#3y2cOcNJ^`kZh|RJ3!SrCR ze>qSHaq{Qxi;9UNz8QkRVG(fUzJ3t9vP%jRL=fO`6~F`u1Z;~%4Va<{4H$~P-M%xq zWF2-Ra4-rUABLD3LiEMhJ>P{BGtc&&pc%4qs3q97(0~N`BT#_O6{z5X0`VZ=f)Fay q;DZrXXy5}sP-x+X`3Qs+gN7V#D9{ZchFGCMHI!%~gaYjl1OPiZ2uK$I literal 0 HcmV?d00001 diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/time.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/time.htm new file mode 100644 index 0000000..2856558 --- /dev/null +++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/time.htm @@ -0,0 +1,4 @@ + +

      +
      + diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/tooltips.js b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/tooltips.js new file mode 100644 index 0000000..790ce27 --- /dev/null +++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/tooltips.js @@ -0,0 +1,143 @@ +/* Your are permitted to reuse this code as long as the following copyright + notice is not removed: + + This HTML tip handling is copyright 1998 by insideDHTML.com, LLC. More information about this + code can be found at Inside Dynamic HTML: HTTP://www.insideDHTML.com +*/ + + +// Support for all collection +var allSupport = document.all!=null; + +function setupEventObject(e) { + // Map NS event object to IEs + if (e==null) return; // IE returns + window.event = e; + window.event.fromElement = e.target; + window.event.toElement = e.target; + window.event.srcElement = e.target; + window.event.x = e.x; + window.event.y = e.y; + // Route the event to the original element + // Necessary to make sure _tip is set. + window.event.srcElement.handleEvent(e); +} + +function checkName(src) { + // Look for tooltip in IE + while ((src!=null) && (src._tip==null)) + src = src.parentElement; + return src; +} + +function getElement(elName) { + // Get an element from its ID + if (allSupport) return document.all[elName]; + else return document.layers[elName]; +} + +function writeContents(el, tip) { + // Replace the contents of the tooltip + if (allSupport) + el.innerHTML = tip; + else { + // In NS, insert a table to work around + // stylesheet rendering bug. + // NS fails to apply style sheets when writing + // contents into a positioned element. + el.document.open(); + el.document.write("
      "); + el.document.write(tip); + el.document.write("
      "); + el.document.close(); + } +} + +function getOffset(el, which) { + // Function for IE to calculate position + // of an element. + var amount = el["offset"+which]; + if (which=="Top") amount+=el.offsetHeight; + el = el.offsetParent; + while (el!=null) { + amount+=el["offset"+which]; + el = el.offsetParent; + } + return amount; +} + + +function setPosition(el) { + // Set the position of an element + + src = window.event.srcElement + if (allSupport) { + el.style.pixelTop = getOffset(src, "Top"); + el.style.pixelLeft = getOffset(src, "Left"); + } + else { + el.top = src.y + 20; //window.event.y + 15 + el.left = src.x; //window.event.x + } +} + +function setVisibility(el, bDisplay) { + // Hide or show to tip + if (bDisplay) { + if (allSupport) el.style.visibility = "visible"; + else el.visibility = "show"; + } + else { + if (allSupport) el.style.visibility = "hidden"; + else el.visibility = "hidden"; + } +} + + +function displayContents(tip) { + // Display the tooltip. + var el = getElement("tipBox"); + writeContents(el, tip); + setPosition(el); + setVisibility(el, true); +} + + +function doMouseOver(e) { + // Mouse moves over an element + setupEventObject(e); + var el, tip; + if ((el = checkName(window.event.srcElement))!=null) { + if (!el._display) { + displayContents(el._tip); + el._display = true; + } + } +} + +function doMouseOut(e) { + // Mouse leaves an element + setupEventObject(e); + el = checkName(window.event.srcElement); + var el, tip; + if ((el = checkName(window.event.srcElement))!=null) { + if (el._display) { + if ((el.contains==null) || (!el.contains(window.event.toElement))) { + setVisibility(getElement("tipBox"), false); + el._display = false; + } + } + } +} + +function doLoad() { + // Do Loading + if ((window.document.captureEvents==null) && (!allSupport)) + return; // Not IE4 or NS4 + if (window.document.captureEvents!=null) // NS - capture events + window.document.captureEvents(Event.MOUSEOVER | Event.MOUSEOUT) + window.document.onmouseover = doMouseOver; + window.document.onmouseout = doMouseOut; +} + +window.onload = doLoad; diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/topnav.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/topnav.htm new file mode 100644 index 0000000..ac2b452 --- /dev/null +++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/topnav.htm @@ -0,0 +1,10 @@ + + + + + + + + +
      + diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/topnav.js b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/topnav.js new file mode 100644 index 0000000..9e3bb9a --- /dev/null +++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/topnav.js @@ -0,0 +1,30 @@ +function popWin(url) { + var win = window.open(url, 'win', + 'location=yes,directories=yes,menubar=yes,toolbar=yes,status=yes,scrollbars=yes,resizable=yes,width=800,height=600'); + win.focus(); +} + +function openTab(type, device) { + var url = rootURL; + switch (type) { + case 0: url = rootURL; break; + case 1: + if (device.indexOf('XC2') != -1) url += prodURL + xbrURL; + else if (device.indexOf('XA2') != -1) url += prodURL + acr2URL; + else if (device.indexOf('XCR3') != -1) url += prodURL + xpla3URL; + else if (device.indexOf('XV') != -1) url += prodURL + xc9500xvURL; + else if (device.indexOf('XL') != -1) url += prodURL + xc9500xlURL; + else if (device.indexOf('XA') != -1) url += prodURL + xa9500xlURL; + else url += prodURL + xc9500URL; + break; + case 2: url += marketURL; break; + case 3: url = supportURL; break; + case 4: url += educationURL; break; + case 5: url = buyURL; break; + case 6: url += contactURL; break; + case 7: url += searchURL; break; + default: url = rootURL; + } + + popWin(url); +} diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/unmapinputdoc.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/unmapinputdoc.htm new file mode 100644 index 0000000..fe242d6 --- /dev/null +++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/unmapinputdoc.htm @@ -0,0 +1,65 @@ + + + + + + + + + + +unmapinputdoc + + + + + + + + + + + + + + + + + + + + + + + + +

      Unmapped Inputs

      + +

      This page shows + input signals which were either not mapped or not + routed.

      + + + + diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/unmaplogicdoc.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/unmaplogicdoc.htm new file mode 100644 index 0000000..6371313 --- /dev/null +++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/unmaplogicdoc.htm @@ -0,0 +1,68 @@ + + + + + + + + + + +unmaplogicdoc + + + + + + + + + + + + + + + + + + + + + + + + +

      Unmapped Logic

      + +

      This page shows those equations whose + logic was either not placed or not completely + placed in the specified device.

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      Processing...

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      Introduction

      + +

      This report is the result of a static timing analysis of your design + after it has been fit in the device that you selected. The timing values + given represent the worst-case values over the recommended operating conditions + for the part.

      + +

      Overview

      + +

      The timing report consists of a series of sections:

      + +

      Summary

      + +

      This table summarizes the external timing parameters for your device, + including tPD, + tCO, + tSU, + tCYC, + and fSYSTEM. +  For a more + detailed description of the timing model for your device, please refer + to the application notes linked below.

      + +

      Timing Constraints

      + +

      This section reports on any timing constraints that you created for + your design. Timing constraints can be entered using the Constraints Editor + tool, or by editing an Implementation Constraints File directly. For more + information on creating timing constraints, see the Constraints Guide. +

      + +

      Note that if you + did not define any constraints for your design, then the timing analysis + software will automatically create a default set of constraints for you. + These include pad-to-pad, register-to-register, pad-to-register, and period + constraints. A constraint value of 0 ns + will be used for all of these automatically generated constraints. As + a result, all paths listed under each constraint will violate the constraint, + and will have a negative value for slack.

      + +

      Note also that to + limit the size of the report, each path endpoint involved in a timing + path will only be listed once, under a single constraint.  

      + +

      For each timing path listed under a constraint, there is a hyperlink + that can be used to open a window listing the individual internal delay + elements traversed in the path. To understand these delay elements, consult + the Definitions section below, or the following + application notes and white papers:

      + +

      XAPP375: Understanding + the CoolRunner-II + Timing Model

      + +

      WP122: + Using the CoolRunner + XPLA3 Timing Model

      + +

      XAPP071: Using + the XC9500 Timing Model

      + +

      XAPP111: Using + the XC9500XL Timing Model

      + +

      XAPP + 362: Using the XC9500XV Timing Model

      + +

      available in the literature section of www.xilinx.com. +

      + +

      Data Sheet Report

      + +

      This section of the report lists the external timing parameters for + your design. This includes; maximum external clock speed for each clock, + setup and hold times for each registered input, clock-to-output pad timing + for each registered output, clock to setup time for each register-to-register + timing path, and pad-to-pad time for each combinatorial path through your + design.

      + +

      Going Further

      + +

      To do more advanced timing analysis of your design, select the process + Analyze Post-Fit Static Timing + in iSE. This + will run Xilinx's + Timing Analyzer tool interactively.  The + Timing Analyzer provides a powerful, flexible, and easy way to perform + static timing analysis on FPGA + and CPLD designs. + With Timing Analyzer, analysis can be performed immediately after mapping, + placing or routing an FPGA + design, and after fitting and routing a CPLD + design.

      + +

      Timing Analyzer verifies that the delay along a given path or paths + meets specified timing requirements. It organizes and displays data that + allows you to analyze critical paths in a circuit, the cycle time of the + circuit, the delay along any specified path(s), + and the path with the greatest delay. It also provides a quick analysis + of the effect different speed grades have on the same design.  

      + +

      Timing Analyzer performs setup and hold checks (skew analysis). It works + with synchronous systems composed of synchronous elements and combinatorial + logic. In synchronous design, Timing Analyzer takes into account all path + delays, including clock-to-out and setup requirements, while calculating + the worst-case timing of the design.

      + +

      Timing Analyzer creates timing analysis reports based on existing timing + constraints or user specified paths within the program. Timing reports + have a hierarchical browser to quickly jump to different sections of the + reports. Timing paths in reports can be cross probed to synthesis tools + (Exemplar and Synplicity) + and Floorplanner. +

      + +

      There are several ways to issue commands in Timing Analyzer. Timing + Analyzer can be controlled through GUI + features (menu commands) or its comprehensive macro command language facility. + You can select from menus, click toolbar buttons, type keyboard commands + in the console window, and run macros.

      + +

      Definitions

      + +

      Pad to Pad (tPD) +

      + +

      Reports pad to pad paths that start at input pads and end at output + pads. The maximum external pad to pad delay.  Combinatorial + pad-to-pad paths begin at input pads, propagate through one or more levels + of combinatorial logic and end at output pads. Combinatorial paths also + trace through the enable inputs of 3-state controlled pads. Combinatorial + paths are not traced through clock, and asynchronous set and reset inputs + of registers. These paths are also broken at bidirectional pins

      + +

      Clock Pad to Output Pad (tCO) +

      + +

      The maximum external clock pad to output pad delay.  Reports + paths that start at input  pads + trace through clock inputs of  registers + and end at output pads. Paths are not traced through PRE/CLR +  inputs + of registers.  You + can directly specify tCO + for all registered output paths in your design using the Pad-to-Pad timespec. + Clock-Pad-to-Pad paths for global clocks begin at global clock pads, propagate + through global clock buffers, and propagate through the flip-flop Q + output and any number of levels of combinatorial logic and end at the + output pad. Clock-Pad-to-Pad paths for product term clock paths begin + at input pads, propagate through any number of logic levels feeding into + a clock product term, propagate through the flip-flop Q + output and any number of levels of combinatorial logic and end at the + output pad. Clock-Pad-to-Pad paths also trace through the enable inputs + of 3-state controlled pads.

      + +

      Setup to Clock at Pad (tSU + or tSUF)

      + +

      Reports external setup time of data  to + clock at pad. Data path starts at an input pad and ends at register  (Fast + Input Register for tSUF) + D/T  input. + Clock path starts at input pad and ends at the register clock input.  Paths + are not traced through registers. Pin-to-pin setup requirement is not + reported or guaranteed for product-term clocks derived from macrocell + feedback signals.

      + +

      The minimum required setup time for flip-flops.  You + can specify the tSU + (setup-to-clock) for all inputs in your design relative to a global clock + or product term clock. Each tSU + OFFSET timespec involves an input path and a clock path. Input paths start + at input pads, propagate through input buffers and any number of combinatorial + logic levels before ending at a flip-flop D/T input, including the receiving + flip-flop's tSU.  Input + paths are not traced through flip-flop clock pins, asynchronous set/reset + inputs or bidirectional I/O pins. Global clock paths start at global clock + pads, propagate through global clock buffers and end at the flip-flop + clock pin. Product term clock paths start at input pads, propagate through + a single level of logic implemented in a clock product term and end at + the flip-flop clock pin.

      + +

      Clock to Setup (tCYC)

      + +

      Register to register cycle time. Includes source register tCO and destination + register tSU.

      + +

      Note that when the + computed Maximum Clock Speed is limited by tCYC, it is computed assuming + that all registers are rising-edge sensitive.

      + +

      fSYSTEM

      + +

      Maximum clock operating frequency.  You + can specify the fSYSTEM (clock frequency or period) for all registered + paths in your design using a Register-to-Register timespec. Register-to-Register + paths begin at flip-flop clock inputs, propagate through the flip-flop + Q output and any number of levels of combinatorial logic and end at the + receiving flip-flop D/T input, including the receiving flip-flop's tSU. + When these flip-flops are clocked by the same clock, the delay on this + path is equivalent to the cycle time of the clock. Registered paths do + not propagate through clock, and asynchronous set and reset inputs of + registers as shown below. These paths are also broken at bidirectional + pins.

      + +

       

      + + + + diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/tim/cpldta_style.css b/Logic/LAN_IDE/LAN_IDE_CP_html/tim/cpldta_style.css new file mode 100644 index 0000000..4b82019 --- /dev/null +++ b/Logic/LAN_IDE/LAN_IDE_CP_html/tim/cpldta_style.css @@ -0,0 +1,144 @@ + + + + +.cpldta_text_report_header { + font-style: normal; + font-weight: bold; + font-size: 25pt; + font-family: Arial, Helvetica, sans-serif; + text-align: center;} + +.cpldta_text_section_header { + font-style: normal; + font-weight: bold; + font-size: 15pt; + font-family: Arial, Helvetica, sans-serif; + text-align: center;} + +.cpldta_text_subsection_header { + font-style: normal; + font-weight: bold; + font-size: 10pt; + font-family: Arial, Helvetica, sans-serif; + text-align: left;} + + +.cpldta_warnings_header { + font-style: normal; + font-weight: normal; + font-size: 10pt; + font-family: Arial, Helvetica, sans-serif; + text-align: center; + background-color: #FFFFCC; } + + +.cpldta_text_normal { + font-style: normal; + font-weight: normal; + font-size: 10pt; + font-family: Arial, Helvetica, sans-serif; + text-align: left;} + + +.cpldta_text_normal_bold { + font-style: normal; + font-weight: bold; + font-size: 10pt; + font-family: Arial, Helvetica, sans-serif; + text-align: left;} + + +.cpldta_constraint_description_normal { + font-style: normal; + font-weight: normal; + font-size: 10pt; + font-family: Arial, Helvetica, sans-serif; + text-align: left;} +.cpldta_constraint_description_bold { + font-style: normal; + font-weight: bold; + font-size: 10pt; + font-family: Arial, Helvetica, sans-serif; + text-align: left;} + + +.cpldta_constraint_name { + font-style: normal; + font-weight: normal; + font-size: 10pt; + font-family: Arial, Helvetica, sans-serif; + text-align: left;} + + +.cpldta_constraint_name_error { + font-style: normal; + font-weight: normal; + font-size: 10pt; + font-family: Arial, Helvetica, sans-serif; + text-align: left; + background-color: #FFCCCC; } + + +.cpldta_time_value { + font-style: normal; + font-weight: normal; + font-size: 10pt; + font-family: Arial, Helvetica, sans-serif; + text-align: center;} + + +.cpldta_time_value_error { + font-style: normal; + font-weight: normal; + font-size: 10pt; + font-family: Arial, Helvetica, sans-serif; + text-align: center; + background-color: #FFCCCC; } + + +.cpldta_delaytable_header { + font-style: normal; + font-weight: bold; + font-size: 12pt; + font-family: Arial, Helvetica, sans-serif; + text-align: center; + background-color: #FFFFCC; } +.cpldta_constraint_header { + font-style: normal; + font-weight: bold; + font-size: 10pt; + font-family: Arial, Helvetica, sans-serif; + text-align: left; + background-color: #FFFFCC; } +.cpldta_time_header { + font-style: normal; + font-weight: bold; + font-size: 10pt; + font-family: Arial, Helvetica, sans-serif; + text-align: center; + background-color: #FFFFCC; } +.cpldta_text_caption { + font-style: normal; + font-weight: Bold; + font-size: 10pt; + font-family: Arial, Helvetica, sans-serif; + text-align: center;} + + +.cpldta_datasheet_pathname { + font-style: normal; + font-weight: normal; + font-size: 10pt; + font-family: Arial, Helvetica, sans-serif; + text-align: left;} +.cpldta_datasheet_time_value { + font-style: normal; + font-weight: normal; + font-size: 10pt; + font-family: Arial, Helvetica, sans-serif; + text-align: center;} + + + + diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/tim/genreport.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/tim/genreport.htm new file mode 100644 index 0000000..43aca47 --- /dev/null +++ b/Logic/LAN_IDE/LAN_IDE_CP_html/tim/genreport.htm @@ -0,0 +1,17 @@ + + +Reports + + +; + + + + + + + +<body bgcolor="#FFFFFF" text="#000000"> +</body> + + diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/tim/leftnav.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/tim/leftnav.htm new file mode 100644 index 0000000..e72761d --- /dev/null +++ b/Logic/LAN_IDE/LAN_IDE_CP_html/tim/leftnav.htm @@ -0,0 +1,37 @@ + + +Timing Navigation + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
      +
      Timing Report
      +
       Description
       Summary
       Constraints
       Definitions
        
      + + diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/tim/report.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/tim/report.htm new file mode 100644 index 0000000..43aca47 --- /dev/null +++ b/Logic/LAN_IDE/LAN_IDE_CP_html/tim/report.htm @@ -0,0 +1,17 @@ + + +Reports + + +; + + + + + + + +<body bgcolor="#FFFFFF" text="#000000"> +</body> + + diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/tim/timing_report.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/tim/timing_report.htm new file mode 100644 index 0000000..5039cfd --- /dev/null +++ b/Logic/LAN_IDE/LAN_IDE_CP_html/tim/timing_report.htm @@ -0,0 +1,1534 @@ + + + + + + + +Timing report for LAN_IDE_CP + + + +

      Timing Report

      +
      Need help reading this report?

      + + + + + + + + + + + + + + + + + + +
      Design NameLAN_IDE_CP
      Device, Speed (SpeedFile Version)XC95144XL, -10 (3.0)
      Date Created Thu Dec 15 19:17:49 2016 +
      Created By Timing Report Generator: version P.68d
      Copyright Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
      +

      Summary

      + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
      Notes and Warnings
      Note: This design contains no timing constraints.
      Note: A default set of constraints using a delay of 0.000ns will be used for analysis.
      Possible asynchronous logic: Clock pin 'AUTO_CONFIG_DONE_CYCLE<1>.CLKF' has multiple original clock nets 'C1' 'C3'.
      Possible asynchronous logic: Clock pin 'IDE_BASEADR<0>.CLKF' has multiple original clock nets 'C1' 'C3'.
      Possible asynchronous logic: Clock pin 'IDE_BASEADR<4>.CLKF' has multiple original clock nets 'C1' 'C3'.
      Possible asynchronous logic: Clock pin 'IDE_BASEADR<5>.CLKF' has multiple original clock nets 'C1' 'C3'.
      Possible asynchronous logic: Clock pin 'IDE_ENABLE.CLKF' has multiple original clock nets 'C1' 'C3'.
      Possible asynchronous logic: Clock pin 'IDE_BASEADR<1>.CLKF' has multiple original clock nets 'C1' 'C3'.
      Possible asynchronous logic: Clock pin 'IDE_BASEADR<2>.CLKF' has multiple original clock nets 'C1' 'C3'.
      Possible asynchronous logic: Clock pin 'IDE_BASEADR<3>.CLKF' has multiple original clock nets 'C1' 'C3'.
      Possible asynchronous logic: Clock pin 'IDE_BASEADR<6>.CLKF' has multiple original clock nets 'C1' 'C3'.
      Possible asynchronous logic: Clock pin 'IDE_BASEADR<7>.CLKF' has multiple original clock nets 'C1' 'C3'.
      Possible asynchronous logic: Clock pin 'SHUT_UP<1>.CLKF' has multiple original clock nets 'C1' 'C3'.
      Possible asynchronous logic: Clock pin 'ide.CLKF' has multiple original clock nets 'C1' 'C3'.
      Possible asynchronous logic: Clock pin 'autoconfig.CLKF' has multiple original clock nets 'C1' 'C3'.
      Possible asynchronous logic: Clock pin 'IDE_R.CLKF' has multiple original clock nets 'C1' 'C3'.
      Possible asynchronous logic: Clock pin 'IDE_W.CLKF' has multiple original clock nets 'C1' 'C3'.
      Possible asynchronous logic: Clock pin 'ROM_OE.CLKF' has multiple original clock nets 'C1' 'C3'.

      + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
      Performance Summary
      Min. Clock Period14.000 ns.
      Max. Clock Frequency (fSYSTEM)71.429 MHz.
      Limited by Clock Pulse Width for C1
      Clock to Setup (tCYC)11.400 ns.
      Pad to Pad Delay (tPD)10.000 ns.
      Setup to Clock at the Pad (tSU)-4.200 ns.
      Clock Pad to Output Pad Delay (tCO)17.900 ns.
      +
      +

      Timing Constraints

      + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
      Constraint NameRequirement (ns)Delay (ns)PathsPaths Failing
      TS10000.00.000
      TS10010.00.000
      TS10020.00.000
      AUTO_TS_F2F0.011.45959
      AUTO_TS_P2P0.017.91111
      AUTO_TS_P2F0.013.9171171
      AUTO_TS_F2P0.04.033
      +
      +
      + +

      Constraint: TS1000

      + + + + + + + + +
      Description: PERIOD:PERIOD_C1:0.000 nS
      PathRequirement (ns)Delay (ns)Slack (ns)
      +
      +
      +       +

      Constraint: TS1001

      + + + + + + + + +
      Description: PERIOD:PERIOD_C3:0.000 nS
      PathRequirement (ns)Delay (ns)Slack (ns)
      +
      +
      +       +

      Constraint: TS1002

      + + + + + + + + +
      Description: PERIOD:PERIOD_AS:0.000 nS
      PathRequirement (ns)Delay (ns)Slack (ns)
      +
      +
      +       +

      Constraint: AUTO_TS_F2F

      + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
      Description: MAXDELAY:FROM:FFS(*):TO:FFS(*):0.000 nS
      PathRequirement (ns)Delay (ns)Slack (ns)
      IDE_BASEADR<4>.Q to ide.D0.00011.400-11.400
      IDE_BASEADR<5>.Q to ide.D0.00011.400-11.400
      IDE_BASEADR<0>.Q to ide.D0.00011.000-11.000
       +
      +
      + +

      Constraint: AUTO_TS_P2P

      + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
      Description: MAXDELAY:FROM:PADS(*):TO:PADS(*):0.000 nS
      PathRequirement (ns)Delay (ns)Slack (ns)
      C1 to IDE_R0.00017.900-17.900
      C1 to IDE_W0.00017.900-17.900
      C1 to ROM_OE0.00017.900-17.900
       +
      +
      + +

      Constraint: AUTO_TS_P2F

      + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
      Description: MAXDELAY:FROM:PADS(*):TO:FFS(*):0.000 nS
      PathRequirement (ns)Delay (ns)Slack (ns)
      C1 to AUTO_CONFIG_DONE_CYCLE<1>.CLKF0.00013.900-13.900
      C1 to IDE_BASEADR<0>.CLKF0.00013.900-13.900
      C1 to IDE_BASEADR<1>.CLKF0.00013.900-13.900
       +
      +
      + +

      Constraint: AUTO_TS_F2P

      + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
      Description: MAXDELAY:FROM:FFS(*):TO:PADS(*):0.000 nS
      PathRequirement (ns)Delay (ns)Slack (ns)
      IDE_R.Q to IDE_R0.0004.000-4.000
      IDE_W.Q to IDE_W0.0004.000-4.000
      ROM_OE.Q to ROM_OE0.0004.000-4.000
       +
      +
      +
      Number of constraints not met: 4
      +
      + +

      Data Sheet Report

      + +

      Maximum External Clock Speeds

      + + + + + + + + + + + + + + + + + + + + + +
      ClockfEXT (MHz)Reason
      C171.429Limited by Clock Pulse Width for C1
      C371.429Limited by Clock Pulse Width for C3
      AS71.429Limited by Clock Pulse Width for AS
      +
      + +

      Setup/Hold Times for Clocks

      + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
      Setup/Hold Times for Clock C1
      Source PadSetup to clk (edge) Hold to clk (edge)
      A<16>-4.6009.100
      A<17>-4.6009.100
      A<18>-4.6009.100
      A<19>-5.6009.100
      A<1>-5.6009.100
      A<20>-4.2009.100
      A<21>-4.2009.100
      A<22>-4.6009.100
      A<23>-4.6009.100
      A<2>-5.6009.100
      A<3>-5.6009.100
      A<4>-5.6009.100
      A<5>-5.6009.100
      A<6>-5.6009.100
      AS-5.6009.100
      BERR-5.6009.100
      D<10>-5.6009.100
      D<11>-5.6009.100
      D<12>-5.6009.100
      D<13>-5.6009.100
      D<14>-5.6009.100
      D<15>-5.6009.100
      D<8>-5.6009.100
      D<9>-5.6009.100
      RESET-5.6009.100
      RW-5.6009.100
      UDS-5.6009.100

      + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
      Setup/Hold Times for Clock C3
      Source PadSetup to clk (edge) Hold to clk (edge)
      A<16>-4.6009.100
      A<17>-4.6009.100
      A<18>-4.6009.100
      A<19>-5.6009.100
      A<1>-5.6009.100
      A<20>-4.2009.100
      A<21>-4.2009.100
      A<22>-4.6009.100
      A<23>-4.6009.100
      A<2>-5.6009.100
      A<3>-5.6009.100
      A<4>-5.6009.100
      A<5>-5.6009.100
      A<6>-5.6009.100
      AS-5.6009.100
      BERR-5.6009.100
      D<10>-5.6009.100
      D<11>-5.6009.100
      D<12>-5.6009.100
      D<13>-5.6009.100
      D<14>-5.6009.100
      D<15>-5.6009.100
      D<8>-5.6009.100
      D<9>-5.6009.100
      RESET-5.6009.100
      RW-5.6009.100
      UDS-5.6009.100

      +
      + +

      Clock to Pad Timing

      + + + + + + + + + + + + + + + + + + +
      Clock C1 to Pad
      Destination PadClock (edge) to Pad
      IDE_R17.900
      IDE_W17.900
      ROM_OE17.900

      + + + + + + + + + + + + + + + + + + +
      Clock C3 to Pad
      Destination PadClock (edge) to Pad
      IDE_R17.900
      IDE_W17.900
      ROM_OE17.900

      +
      + +

      Clock to Setup Times for Clocks

      + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
      Clock to Setup for clock C1
      SourceDestinationDelay
      IDE_BASEADR<4>.Qide.D11.400
      IDE_BASEADR<5>.Qide.D11.400
      IDE_BASEADR<0>.Qide.D11.000
      IDE_BASEADR<1>.Qide.D11.000
      IDE_BASEADR<2>.Qide.D11.000
      IDE_BASEADR<6>.Qide.D11.000
      IDE_BASEADR<7>.Qide.D11.000
      AUTO_CONFIG_DONE_CYCLE<1>.QAUTO_CONFIG_DONE_CYCLE<1>.D10.000
      IDE_BASEADR<0>.QIDE_BASEADR<0>.D10.000
      IDE_BASEADR<1>.QIDE_BASEADR<1>.D10.000
      IDE_BASEADR<2>.QIDE_BASEADR<2>.D10.000
      IDE_BASEADR<3>.QIDE_BASEADR<3>.D10.000
      IDE_BASEADR<3>.Qide.D10.000
      IDE_BASEADR<4>.QIDE_BASEADR<4>.D10.000
      IDE_BASEADR<5>.QIDE_BASEADR<5>.D10.000
      IDE_BASEADR<6>.QIDE_BASEADR<6>.D10.000
      IDE_BASEADR<7>.QIDE_BASEADR<7>.D10.000
      IDE_ENABLE.QIDE_ENABLE.D10.000
      IDE_ENABLE.QIDE_R.D10.000
      IDE_ENABLE.QROM_OE.D10.000
      SHUT_UP<1>.QSHUT_UP<1>.D10.000
      SHUT_UP<1>.Qide.D10.000
      autoconfig.QAUTO_CONFIG_DONE_CYCLE<1>.D10.000
      autoconfig.QIDE_BASEADR<0>.D10.000
      autoconfig.QIDE_BASEADR<1>.D10.000
      autoconfig.QIDE_BASEADR<2>.D10.000
      autoconfig.QIDE_BASEADR<3>.D10.000
      autoconfig.QIDE_BASEADR<4>.D10.000
      autoconfig.QIDE_BASEADR<5>.D10.000
      autoconfig.QIDE_BASEADR<6>.D10.000
      autoconfig.QIDE_BASEADR<7>.D10.000
      autoconfig.QSHUT_UP<1>.D10.000
      ide.QIDE_ENABLE.D10.000
      ide.QIDE_R.D10.000
      ide.QIDE_W.D10.000
      ide.QROM_OE.D10.000

      + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
      Clock to Setup for clock C3
      SourceDestinationDelay
      IDE_BASEADR<4>.Qide.D11.400
      IDE_BASEADR<5>.Qide.D11.400
      IDE_BASEADR<0>.Qide.D11.000
      IDE_BASEADR<1>.Qide.D11.000
      IDE_BASEADR<2>.Qide.D11.000
      IDE_BASEADR<6>.Qide.D11.000
      IDE_BASEADR<7>.Qide.D11.000
      AUTO_CONFIG_DONE_CYCLE<1>.QAUTO_CONFIG_DONE_CYCLE<1>.D10.000
      IDE_BASEADR<0>.QIDE_BASEADR<0>.D10.000
      IDE_BASEADR<1>.QIDE_BASEADR<1>.D10.000
      IDE_BASEADR<2>.QIDE_BASEADR<2>.D10.000
      IDE_BASEADR<3>.QIDE_BASEADR<3>.D10.000
      IDE_BASEADR<3>.Qide.D10.000
      IDE_BASEADR<4>.QIDE_BASEADR<4>.D10.000
      IDE_BASEADR<5>.QIDE_BASEADR<5>.D10.000
      IDE_BASEADR<6>.QIDE_BASEADR<6>.D10.000
      IDE_BASEADR<7>.QIDE_BASEADR<7>.D10.000
      IDE_ENABLE.QIDE_ENABLE.D10.000
      IDE_ENABLE.QIDE_R.D10.000
      IDE_ENABLE.QROM_OE.D10.000
      SHUT_UP<1>.QSHUT_UP<1>.D10.000
      SHUT_UP<1>.Qide.D10.000
      autoconfig.QAUTO_CONFIG_DONE_CYCLE<1>.D10.000
      autoconfig.QIDE_BASEADR<0>.D10.000
      autoconfig.QIDE_BASEADR<1>.D10.000
      autoconfig.QIDE_BASEADR<2>.D10.000
      autoconfig.QIDE_BASEADR<3>.D10.000
      autoconfig.QIDE_BASEADR<4>.D10.000
      autoconfig.QIDE_BASEADR<5>.D10.000
      autoconfig.QIDE_BASEADR<6>.D10.000
      autoconfig.QIDE_BASEADR<7>.D10.000
      autoconfig.QSHUT_UP<1>.D10.000
      ide.QIDE_ENABLE.D10.000
      ide.QIDE_R.D10.000
      ide.QIDE_W.D10.000
      ide.QROM_OE.D10.000

      +
      + +

      Pad to Pad List

      + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
      Source PadDestination PadDelay
      A<10>IDE_A<1>10.000
      A<11>IDE_A<2>10.000
      A<12>IDE_CS<0>10.000
      A<13>IDE_CS<1>10.000
      A<9>IDE_A<0>10.000
      +
      +
      +
      Number of paths analyzed: +244 +
      Number of Timing errors: +244 +
      Analysis Completed: Thu Dec 15 19:17:49 2016 + +
      + diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/tim/toc.css b/Logic/LAN_IDE/LAN_IDE_CP_html/tim/toc.css new file mode 100644 index 0000000..29af0e1 --- /dev/null +++ b/Logic/LAN_IDE/LAN_IDE_CP_html/tim/toc.css @@ -0,0 +1,36 @@ +.HEADING { + font-size: 15px; + font-family: Arial, Geneva, Verdana, Helvetica; + font-weight: bold; color: #000000; + text-align: normal; + margin-left: 0px; } +.Fitting { + font-size: 11px; + font-family: Arial, Geneva, Verdana, Helvetica; + font-weight: bold; color: #000000; + text-align: normal; + margin-left: 0px; } +.SECONDARY-NAV { + font-size: 11px; + font-family: Arial, Geneva, Verdana, Helvetica; + font-weight: bold; color: #FFFFFF; + margin-left: 0px; + text-decoration: none; ; + list-style-type: disc ; + list-style-position: inside } +.Timing { + font-size: 11px; + font-family: Arial, Geneva, Verdana, Helvetica; + font-weight: bold; color: #333333; + margin-left: 0px; + text-decoration: none; ; + list-style-type: disc ; + list-style-position: inside } +.Timing-Error { + font-size: 11px; + font-family: Arial, Geneva, Verdana, Helvetica; + font-weight: bold; color: #990000; + margin-left: 0px; + text-decoration: none; ; + list-style-type: disc ; + list-style-position: inside } diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/tim/topnav.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/tim/topnav.htm new file mode 100644 index 0000000..00e11b8 --- /dev/null +++ b/Logic/LAN_IDE/LAN_IDE_CP_html/tim/topnav.htm @@ -0,0 +1,31 @@ + + +CPLD Reports Banner + + + + + + + + + + + + + + +
       
      + + + + +   
      + + + + + + + + diff --git a/Logic/LAN_IDE/LAN_IDE_CP_ngdbuild.xrpt b/Logic/LAN_IDE/LAN_IDE_CP_ngdbuild.xrpt new file mode 100644 index 0000000..e8a8d37 --- /dev/null +++ b/Logic/LAN_IDE/LAN_IDE_CP_ngdbuild.xrpt @@ -0,0 +1,113 @@ + + + + + + +
      + + + + + + + + + + + + + + + + + + + + + + + + + + + +
      + + + + + + + + + + + + + + + + +
      +
      + +
      + + + + +
      +       + +
      + + + + + +
      +
      + + + + + + + + + + + + + + + + + +
      +
      + + + + + + + + + + + + + + +
      +
      +
      +
      + + + + diff --git a/Logic/LAN_IDE/LAN_IDE_CP_pad.csv b/Logic/LAN_IDE/LAN_IDE_CP_pad.csv new file mode 100644 index 0000000..853bd5c --- /dev/null +++ b/Logic/LAN_IDE/LAN_IDE_CP_pad.csv @@ -0,0 +1,173 @@ +Release 8.1i - Fit P.68d +Copyright(c) 1995-2003 Xilinx Inc. All rights reserved + +12-15-2016 7:48PM + +NOTE: This file is designed to be imported into a spreadsheet program +such as Microsoft Excel for viewing, printing and sorting. The comma ',' +character is used as the data field separator. +This file is also designed to support parsing. + +Input file: LAN_IDE_CP.ngd +output file: LAN_IDE_CP_pad.csv +Part type: xc95144xl +Speed grade: -10 +Package: tq144 + +Pinout by Pin Number: + +-----,-----,-----,-----,-----,-----,-----,-----,-----,-----, +Pin Number,Signal Name,Pin Usage,Pin Name,Direction,IO Standard,IO Bank Number,{blank},Slew Rate,Termination,{blank},Voltage,Constraint, +P1,VCC,,VCCIO,,,,,,,,,, +P2,D<0>,O,I/O/GTS3,OUTPUT,,,,,,,,, +P3,TIE,,I/O/GTS4,,,,,,,,,, +P4,TIE,,I/O,,,,,,,,,, +P5,TIE,,I/O/GTS1,,,,,,,,,, +P6,TIE,,I/O/GTS2,,,,,,,,,, +P7,TIE,,I/O,,,,,,,,,, +P8,VCC,,VCCINT,,,,,,,,,, +P9,TIE,,I/O,,,,,,,,,, +P10,TIE,,I/O,,,,,,,,,, +P11,TIE,,I/O,,,,,,,,,, +P12,TIE,,I/O,,,,,,,,,, +P13,TIE,,I/O,,,,,,,,,, +P14,D<6>,O,I/O,OUTPUT,,,,,,,,, +P15,D<3>,O,I/O,OUTPUT,,,,,,,,, +P16,D<7>,O,I/O,OUTPUT,,,,,,,,, +P17,D<1>,O,I/O,OUTPUT,,,,,,,,, +P18,GND,,GND,,,,,,,,,, +P19,D<8>,I/O,I/O,BIDIR,,,,,,,,, +P20,D<5>,O,I/O,OUTPUT,,,,,,,,, +P21,D<4>,O,I/O,OUTPUT,,,,,,,,, +P22,IDE_CS<0>,O,I/O,OUTPUT,,,,,,,,, +P23,IDE_CS<1>,O,I/O,OUTPUT,,,,,,,,, +P24,IDE_A<0>,O,I/O,OUTPUT,,,,,,,,, +P25,IDE_A<2>,O,I/O,OUTPUT,,,,,,,,, +P26,IDE_A<1>,O,I/O,OUTPUT,,,,,,,,, +P27,IDE_R,O,I/O,OUTPUT,,,,,,,,, +P28,IDE_W,O,I/O,OUTPUT,,,,,,,,, +P29,GND,,GND,,,,,,,,,, +P30,TIE,,I/O/GCK1,,,,,,,,,, +P31,TIE,,I/O,,,,,,,,,, +P32,TIE,,I/O/GCK2,,,,,,,,,, +P33,TIE,,I/O,,,,,,,,,, +P34,TIE,,I/O,,,,,,,,,, +P35,ROM_OE,O,I/O,OUTPUT,,,,,,,,, +P36,GND,,GND,,,,,,,,,, +P37,VCC,,VCCIO,,,,,,,,,, +P38,TIE,,I/O/GCK3,,,,,,,,,, +P39,D<2>,O,I/O,OUTPUT,,,,,,,,, +P40,D<9>,I/O,I/O,BIDIR,,,,,,,,, +P41,D<10>,I/O,I/O,BIDIR,,,,,,,,, +P42,VCC,,VCCINT,,,,,,,,,, +P43,D<11>,I/O,I/O,BIDIR,,,,,,,,, +P44,D<12>,I/O,I/O,BIDIR,,,,,,,,, +P45,D<13>,I/O,I/O,BIDIR,,,,,,,,, +P46,D<14>,I/O,I/O,BIDIR,,,,,,,,, +P47,GND,,GND,,,,,,,,,, +P48,D<15>,I/O,I/O,BIDIR,,,,,,,,, +P49,A<5>,I,I/O,INPUT,,,,,,,,, +P50,A<4>,I,I/O,INPUT,,,,,,,,, +P51,A<6>,I,I/O,INPUT,,,,,,,,, +P52,A<3>,I,I/O,INPUT,,,,,,,,, +P53,TIE,,I/O,,,,,,,,,, +P54,A<2>,I,I/O,INPUT,,,,,,,,, +P55,VCC,,VCCIO,,,,,,,,,, +P56,TIE,,I/O,,,,,,,,,, +P57,A<1>,I,I/O,INPUT,,,,,,,,, +P58,A<9>,I,I/O,INPUT,,,,,,,,, +P59,A<10>,I,I/O,INPUT,,,,,,,,, +P60,A<11>,I,I/O,INPUT,,,,,,,,, +P61,A<12>,I,I/O,INPUT,,,,,,,,, +P62,GND,,GND,,,,,,,,,, +P63,TDI,,TDI,,,,,,,,,, +P64,A<13>,I,I/O,INPUT,,,,,,,,, +P65,TMS,,TMS,,,,,,,,,, +P66,TIE,,I/O,,,,,,,,,, +P67,TCK,,TCK,,,,,,,,,, +P68,ROM_B<0>,O,I/O,OUTPUT,,,,,,,,, +P69,ROM_B<1>,O,I/O,OUTPUT,,,,,,,,, +P70,TIE,,I/O,,,,,,,,,, +P71,TIE,,I/O,,,,,,,,,, +P72,GND,,GND,,,,,,,,,, +P73,VCC,,VCCIO,,,,,,,,,, +P74,TIE,,I/O,,,,,,,,,, +P75,AUTOBOOT_OFF,I,I/O,INPUT,,,,,,,,, +P76,TIE,,I/O,,,,,,,,,, +P77,TIE,,I/O,,,,,,,,,, +P78,TIE,,I/O,,,,,,,,,, +P79,TIE,,I/O,,,,,,,,,, +P80,AS,I,I/O,INPUT,,,,,,,,, +P81,UDS,I,I/O,INPUT,,,,,,,,, +P82,TIE,,I/O,,,,,,,,,, +P83,RW,I,I/O,INPUT,,,,,,,,, +P84,VCC,,VCCINT,,,,,,,,,, +P85,DTACK,O,I/O,OUTPUT,,,,,,,,, +P86,A<23>,I,I/O,INPUT,,,,,,,,, +P87,A<22>,I,I/O,INPUT,,,,,,,,, +P88,A<21>,I,I/O,INPUT,,,,,,,,, +P89,GND,,GND,,,,,,,,,, +P90,GND,,GND,,,,,,,,,, +P91,A<20>,I,I/O,INPUT,,,,,,,,, +P92,A<19>,I,I/O,INPUT,,,,,,,,, +P93,TIE,,I/O,,,,,,,,,, +P94,A<18>,I,I/O,INPUT,,,,,,,,, +P95,A<17>,I,I/O,INPUT,,,,,,,,, +P96,TIE,,I/O,,,,,,,,,, +P97,A<16>,I,I/O,INPUT,,,,,,,,, +P98,BERR,I,I/O,INPUT,,,,,,,,, +P99,GND,,GND,,,,,,,,,, +P100,TIE,,I/O,,,,,,,,,, +P101,TIE,,I/O,,,,,,,,,, +P102,C3,I,I/O,INPUT,,,,,,,,, +P103,C1,I,I/O,INPUT,,,,,,,,, +P104,TIE,,I/O,,,,,,,,,, +P105,TIE,,I/O,,,,,,,,,, +P106,TIE,,I/O,,,,,,,,,, +P107,TIE,,I/O,,,,,,,,,, +P108,GND,,GND,,,,,,,,,, +P109,VCC,,VCCIO,,,,,,,,,, +P110,TIE,,I/O,,,,,,,,,, +P111,TIE,,I/O,,,,,,,,,, +P112,TIE,,I/O,,,,,,,,,, +P113,TIE,,I/O,,,,,,,,,, +P114,GND,,GND,,,,,,,,,, +P115,TIE,,I/O,,,,,,,,,, +P116,TIE,,I/O,,,,,,,,,, +P117,TIE,,I/O,,,,,,,,,, +P118,TIE,,I/O,,,,,,,,,, +P119,TIE,,I/O,,,,,,,,,, +P120,TIE,,I/O,,,,,,,,,, +P121,TIE,,I/O,,,,,,,,,, +P122,TDO,,TDO,,,,,,,,,, +P123,GND,,GND,,,,,,,,,, +P124,TIE,,I/O,,,,,,,,,, +P125,TIE,,I/O,,,,,,,,,, +P126,TIE,,I/O,,,,,,,,,, +P127,VCC,,VCCIO,,,,,,,,,, +P128,TIE,,I/O,,,,,,,,,, +P129,TIE,,I/O,,,,,,,,,, +P130,TIE,,I/O,,,,,,,,,, +P131,TIE,,I/O,,,,,,,,,, +P132,TIE,,I/O,,,,,,,,,, +P133,TIE,,I/O,,,,,,,,,, +P134,TIE,,I/O,,,,,,,,,, +P135,TIE,,I/O,,,,,,,,,, +P136,TIE,,I/O,,,,,,,,,, +P137,TIE,,I/O,,,,,,,,,, +P138,TIE,,I/O,,,,,,,,,, +P139,TIE,,I/O,,,,,,,,,, +P140,TIE,,I/O,,,,,,,,,, +P141,VCC,,VCCINT,,,,,,,,,, +P142,TIE,,I/O,,,,,,,,,, +P143,RESET,GSR/I,I/O/GSR,,,,,,,,,, +P144,GND,,GND,,,,,,,,,, + +To preserve the pinout above for future design iterations in +Project Navigator simply execute the (Lock Pins) process +located under the (Implement Design) process in a toolbox named +(Optional Implementation Tools) or invoke PIN2UCF from the +command line. The location constraints will be written into your +specified UCF file + + diff --git a/Logic/LAN_IDE/LAN_IDE_CP_summary.html b/Logic/LAN_IDE/LAN_IDE_CP_summary.html index 5a64987..2288606 100644 --- a/Logic/LAN_IDE/LAN_IDE_CP_summary.html +++ b/Logic/LAN_IDE/LAN_IDE_CP_summary.html @@ -2,7 +2,7 @@ - + @@ -13,18 +13,19 @@ - + - + - + @@ -41,7 +42,10 @@ - + @@ -61,9 +65,9 @@ - - - + + +
      LAN_IDE_CP Project Status
      LAN_IDE_CP Project Status (12/15/2016 - 19:48:52)
      Project File: LAN_IDE.xiseModule Name: LAN_IDE_CP Implementation State:NewFitted
      Target Device: xc95144xl-10TQ144
      • Errors:
      		  +No Errors
      Product Version:ISE 14.6
      • Warnings:
      		 72 Warnings (52 new)
      Design Goal:
      Environment:  + +System Settings +
      • Final Timing Score:
      		   
      Detailed Reports [-]
      Report NameStatusGenerated ErrorsWarningsInfos
      Synthesis Report     
      Translation Report     
      CPLD Fitter Report (Text)     
      Synthesis ReportCurrentDo 15. Dez 19:48:23 2016052 Warnings (52 new)0
      Translation ReportCurrentDo 15. Dez 19:48:31 2016020 Warnings (0 new)0
      CPLD Fitter Report (Text)CurrentDo 15. Dez 19:48:44 2016067 Warnings (5 new)1 Info (1 new)
      Power Report     
       
      @@ -73,5 +77,5 @@
      -
      Date Generated: 12/13/2016 - 22:08:30
      +
      Date Generated: 12/15/2016 - 19:48:52
      \ No newline at end of file diff --git a/Logic/LAN_IDE/LAN_IDE_CP_vhdl.prj b/Logic/LAN_IDE/LAN_IDE_CP_vhdl.prj new file mode 100644 index 0000000..80b06c6 --- /dev/null +++ b/Logic/LAN_IDE/LAN_IDE_CP_vhdl.prj @@ -0,0 +1 @@ +vhdl work "C:\Users\Matze\Amiga\Hardwarehacks\Zorro-LAN-IDE\Logic\LAN_IDE\LAN_IDE_CP.vhd" diff --git a/Logic/LAN_IDE/LAN_IDE_CP_xst.xrpt b/Logic/LAN_IDE/LAN_IDE_CP_xst.xrpt new file mode 100644 index 0000000..985d946 --- /dev/null +++ b/Logic/LAN_IDE/LAN_IDE_CP_xst.xrpt @@ -0,0 +1,142 @@ + + + + + + +
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      + + + diff --git a/Logic/LAN_IDE/_ngo/netlist.lst b/Logic/LAN_IDE/_ngo/netlist.lst new file mode 100644 index 0000000..0aeed87 --- /dev/null +++ b/Logic/LAN_IDE/_ngo/netlist.lst @@ -0,0 +1,2 @@ +C:\Users\Matze\Amiga\Hardwarehacks\Zorro-LAN-IDE\Logic\LAN_IDE\LAN_IDE_CP.ngc 1481827703 +OK diff --git a/Logic/LAN_IDE/_pace.ucf b/Logic/LAN_IDE/_pace.ucf new file mode 100644 index 0000000..4253454 --- /dev/null +++ b/Logic/LAN_IDE/_pace.ucf @@ -0,0 +1,68 @@ +#PACE: Start of Constraints generated by PACE + +#PACE: Start of PACE I/O Pin Assignments +NET "A<10>" LOC = "P59" ; +NET "A<11>" LOC = "P60" ; +NET "A<12>" LOC = "P61" ; +NET "A<13>" LOC = "P64" ; +NET "A<14>" LOC = "P66" ; +NET "A<15>" LOC = "P74" ; +NET "A<16>" LOC = "P97" ; +NET "A<17>" LOC = "P95" ; +NET "A<18>" LOC = "P94" ; +NET "A<19>" LOC = "P92" ; +NET "A<1>" LOC = "P57" ; +NET "A<20>" LOC = "P91" ; +NET "A<21>" LOC = "P88" ; +NET "A<22>" LOC = "P87" ; +NET "A<23>" LOC = "P86" ; +NET "A<2>" LOC = "P54" ; +NET "A<3>" LOC = "P52" ; +NET "A<4>" LOC = "P50" ; +NET "A<5>" LOC = "P49" ; +NET "A<6>" LOC = "P51" ; +NET "A<7>" LOC = "P53" ; +NET "A<8>" LOC = "P56" ; +NET "A<9>" LOC = "P58" ; +NET "AS" LOC = "P80" ; +NET "AUTOBOOT_OFF" LOC = "P75" ; +NET "BERR" LOC = "P98" ; +NET "C1" LOC = "P103" ; +NET "C3" LOC = "P102" ; +NET "CFIN" LOC = "P104" ; +NET "CFOUT" LOC = "P105" ; +NET "D<0>" LOC = "P2" ; +NET "D<10>" LOC = "P41" ; +NET "D<11>" LOC = "P43" ; +NET "D<12>" LOC = "P44" ; +NET "D<13>" LOC = "P45" ; +NET "D<14>" LOC = "P46" ; +NET "D<15>" LOC = "P48" ; +NET "D<1>" LOC = "P17" ; +NET "D<2>" LOC = "P39" ; +NET "D<3>" LOC = "P15" ; +NET "D<4>" LOC = "P21" ; +NET "D<5>" LOC = "P20" ; +NET "D<6>" LOC = "P14" ; +NET "D<7>" LOC = "P16" ; +NET "D<8>" LOC = "P19" ; +NET "D<9>" LOC = "P40" ; +NET "DS0" LOC = "P93" ; +NET "DS1" LOC = "P78" ; +NET "DTACK" LOC = "P85" ; +NET "FCS" LOC = "P77" ; +NET "LAN_EN" LOC = "P76" ; +NET "LDS" LOC = "P82" ; +NET "MTACK" LOC = "P96" ; +NET "MTCR" LOC = "P101" ; +NET "OVR" LOC = "P100" ; +NET "OWN" LOC = "P107" ; +NET "SLAVE" LOC = "P106" ; +NET "UDS" LOC = "P81" ; +NET "Z3" LOC = "P79" ; + +#PACE: Start of PACE Area Constraints + +#PACE: Start of PACE Prohibit Constraints + +#PACE: End of Constraints generated by PACE diff --git a/Logic/LAN_IDE/_xmsgs/cpldfit.xmsgs b/Logic/LAN_IDE/_xmsgs/cpldfit.xmsgs new file mode 100644 index 0000000..043fd08 --- /dev/null +++ b/Logic/LAN_IDE/_xmsgs/cpldfit.xmsgs @@ -0,0 +1,213 @@ + + + +Unable to retrieve the path to the iSE Project Repository. Will use the default filename of 'LAN_IDE_CP.ise'. + + +Inferring BUFG constraint for signal 'CLK_EXT' based upon the LOC constraint 'P30'. It is recommended that you declare this BUFG explicitedly in your design. Note that for certain device families the output of a BUFG constraint can not drive a gated clock, and the BUFG constraint will be ignored. + + +The output buffer 'SLAVE_OBUF' is missing an input and will be deleted. + + +The output buffer 'OWN_OBUF' is missing an input and will be deleted. + + +The output buffer 'OVR_OBUF' is missing an input and will be deleted. + + +The output buffer 'MTACK_OBUF' is missing an input and will be deleted. + + +The output buffer 'LAN_WRH_OBUF' is missing an input and will be deleted. + + +The output buffer 'LAN_RD_OBUF' is missing an input and will be deleted. + + +The output buffer 'LAN_EN_OBUF' is missing an input and will be deleted. + + +The output buffer 'LAN_CS_OBUF' is missing an input and will be deleted. + + +The output buffer 'LAN_CFG<4>_OBUF' is missing an input and will be deleted. + + +The output buffer 'LAN_CFG<3>_OBUF' is missing an input and will be deleted. + + +The output buffer 'LAN_CFG<2>_OBUF' is missing an input and will be deleted. + + +The output buffer 'LAN_CFG<1>_OBUF' is missing an input and will be deleted. + + +The output buffer 'INT_OUT_OBUF' is missing an input and will be deleted. + + +The output buffer 'CP_WE_OBUF' is missing an input and will be deleted. + + +The output buffer 'CP_RD_OBUF' is missing an input and will be deleted. + + +The output buffer 'CP_CS_OBUF' is missing an input and will be deleted. + + +The output buffer 'CFOUT_OBUF' is missing an input and will be deleted. + + +The output buffer 'A_LAN<9>_OBUF' is missing an input and will be deleted. + + +The output buffer 'A_LAN<8>_OBUF' is missing an input and will be deleted. + + +The output buffer 'A_LAN<7>_OBUF' is missing an input and will be deleted. + + +The output buffer 'A_LAN<6>_OBUF' is missing an input and will be deleted. + + +The output buffer 'A_LAN<5>_OBUF' is missing an input and will be deleted. + + +The output buffer 'A_LAN<4>_OBUF' is missing an input and will be deleted. + + +The output buffer 'A_LAN<3>_OBUF' is missing an input and will be deleted. + + +The output buffer 'A_LAN<2>_OBUF' is missing an input and will be deleted. + + +The output buffer 'A_LAN<1>_OBUF' is missing an input and will be deleted. + + +The output buffer 'A_LAN<13>_OBUF' is missing an input and will be deleted. + + +The output buffer 'A_LAN<12>_OBUF' is missing an input and will be deleted. + + +The output buffer 'A_LAN<11>_OBUF' is missing an input and will be deleted. + + +The output buffer 'A_LAN<10>_OBUF' is missing an input and will be deleted. + + +The output buffer 'A_LAN<0>_OBUF' is missing an input and will be deleted. + + +Removing unused input(s) 'A<14>'. The input(s) are unused after optimization. Please verify functionality via simulation. + + +Removing unused input(s) 'A<15>'. The input(s) are unused after optimization. Please verify functionality via simulation. + + +Removing unused input(s) 'A<7>'. The input(s) are unused after optimization. Please verify functionality via simulation. + + +Removing unused input(s) 'A<8>'. The input(s) are unused after optimization. Please verify functionality via simulation. + + +Removing unused input(s) 'CFIN'. The input(s) are unused after optimization. Please verify functionality via simulation. + + +Removing unused input(s) 'CLK_EXT'. The input(s) are unused after optimization. Please verify functionality via simulation. + + +Removing unused input(s) 'CP_IRQ'. The input(s) are unused after optimization. Please verify functionality via simulation. + + +Removing unused input(s) 'DQ<0>'. The input(s) are unused after optimization. Please verify functionality via simulation. + + +Removing unused input(s) 'DQ<10>'. The input(s) are unused after optimization. Please verify functionality via simulation. + + +Removing unused input(s) 'DQ<11>'. The input(s) are unused after optimization. Please verify functionality via simulation. + + +Removing unused input(s) 'DQ<12>'. The input(s) are unused after optimization. Please verify functionality via simulation. + + +Removing unused input(s) 'DQ<13>'. The input(s) are unused after optimization. Please verify functionality via simulation. + + +Removing unused input(s) 'DQ<14>'. The input(s) are unused after optimization. Please verify functionality via simulation. + + +Removing unused input(s) 'DQ<15>'. The input(s) are unused after optimization. Please verify functionality via simulation. + + +Removing unused input(s) 'DQ<1>'. The input(s) are unused after optimization. Please verify functionality via simulation. + + +Removing unused input(s) 'DQ<2>'. The input(s) are unused after optimization. Please verify functionality via simulation. + + +Removing unused input(s) 'DQ<3>'. The input(s) are unused after optimization. Please verify functionality via simulation. + + +Removing unused input(s) 'DQ<4>'. The input(s) are unused after optimization. Please verify functionality via simulation. + + +Removing unused input(s) 'DQ<5>'. The input(s) are unused after optimization. Please verify functionality via simulation. + + +Removing unused input(s) 'DQ<6>'. The input(s) are unused after optimization. Please verify functionality via simulation. + + +Removing unused input(s) 'DQ<7>'. The input(s) are unused after optimization. Please verify functionality via simulation. + + +Removing unused input(s) 'DQ<8>'. The input(s) are unused after optimization. Please verify functionality via simulation. + + +Removing unused input(s) 'DQ<9>'. The input(s) are unused after optimization. Please verify functionality via simulation. + + +Removing unused input(s) 'DS0'. The input(s) are unused after optimization. Please verify functionality via simulation. + + +Removing unused input(s) 'DS1'. The input(s) are unused after optimization. Please verify functionality via simulation. + + +Removing unused input(s) 'FCS'. The input(s) are unused after optimization. Please verify functionality via simulation. + + +Removing unused input(s) 'IDE_WAIT'. The input(s) are unused after optimization. Please verify functionality via simulation. + + +Removing unused input(s) 'LAN_INT'. The input(s) are unused after optimization. Please verify functionality via simulation. + + +Removing unused input(s) 'LDS'. The input(s) are unused after optimization. Please verify functionality via simulation. + + +Removing unused input(s) 'MTCR'. The input(s) are unused after optimization. Please verify functionality via simulation. + + +Removing unused input(s) 'Z3'. The input(s) are unused after optimization. Please verify functionality via simulation. + + +Unable to map all desired signals into function block, FB3, because too many function block product terms are required. Buffering output signal D<12> to allow all signals assigned to this function block to be placed. + + +Unable to map all desired signals into function block, FB3, because too many function block product terms are required. Buffering output signal D<14> to allow all signals assigned to this function block to be placed. + + +Unable to map all desired signals into function block, FB3, because too many function block product terms are required. Buffering output signal D<13> to allow all signals assigned to this function block to be placed. + + +Unable to map all desired signals into function block, FB3, because too many function block product terms are required. Buffering output signal D<15> to allow all signals assigned to this function block to be placed. + + + + diff --git a/Logic/LAN_IDE/_xmsgs/hprep6.xmsgs b/Logic/LAN_IDE/_xmsgs/hprep6.xmsgs new file mode 100644 index 0000000..f84336a --- /dev/null +++ b/Logic/LAN_IDE/_xmsgs/hprep6.xmsgs @@ -0,0 +1,9 @@ + + + + + diff --git a/Logic/LAN_IDE/_xmsgs/ngdbuild.xmsgs b/Logic/LAN_IDE/_xmsgs/ngdbuild.xmsgs new file mode 100644 index 0000000..d581cd4 --- /dev/null +++ b/Logic/LAN_IDE/_xmsgs/ngdbuild.xmsgs @@ -0,0 +1,69 @@ + + + +bidirect pad net 'DQ<0>' has no legal driver + + +bidirect pad net 'DQ<1>' has no legal driver + + +bidirect pad net 'DQ<2>' has no legal driver + + +bidirect pad net 'DQ<3>' has no legal driver + + +bidirect pad net 'DQ<4>' has no legal driver + + +bidirect pad net 'DQ<10>' has no legal driver + + +bidirect pad net 'DQ<5>' has no legal driver + + +bidirect pad net 'DQ<11>' has no legal driver + + +bidirect pad net 'DQ<6>' has no legal driver + + +bidirect pad net 'DQ<12>' has no legal driver + + +bidirect pad net 'DQ<7>' has no legal driver + + +bidirect pad net 'DQ<13>' has no legal driver + + +bidirect pad net 'DQ<8>' has no legal driver + + +bidirect pad net 'DQ<14>' has no legal driver + + +bidirect pad net 'DQ<9>' has no legal driver + + +bidirect pad net 'DQ<15>' has no legal driver + + +bidirect pad net 'A<14>' has no legal driver + + +bidirect pad net 'A<15>' has no legal driver + + +bidirect pad net 'A<7>' has no legal driver + + +bidirect pad net 'A<8>' has no legal driver + + + + diff --git a/Logic/LAN_IDE/_xmsgs/taengine.xmsgs b/Logic/LAN_IDE/_xmsgs/taengine.xmsgs new file mode 100644 index 0000000..f84336a --- /dev/null +++ b/Logic/LAN_IDE/_xmsgs/taengine.xmsgs @@ -0,0 +1,9 @@ + + + + + diff --git a/Logic/LAN_IDE/_xmsgs/tsim.xmsgs b/Logic/LAN_IDE/_xmsgs/tsim.xmsgs new file mode 100644 index 0000000..f84336a --- /dev/null +++ b/Logic/LAN_IDE/_xmsgs/tsim.xmsgs @@ -0,0 +1,9 @@ + + + + + diff --git a/Logic/LAN_IDE/_xmsgs/xst.xmsgs b/Logic/LAN_IDE/_xmsgs/xst.xmsgs new file mode 100644 index 0000000..280b83c --- /dev/null +++ b/Logic/LAN_IDE/_xmsgs/xst.xmsgs @@ -0,0 +1,165 @@ + + + +Inout <DQ<0>> is never assigned. + + +Output <SLAVE> is never assigned. + + +Input <IDE_WAIT> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Inout <DQ<1>> is never assigned. + + +Input <LDS> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Output <LAN_CS> is never assigned. + + +Inout <DQ<2>> is never assigned. + + +Output <LAN_EN> is never assigned. + + +Inout <DQ<3>> is never assigned. + + +Inout <DQ<4>> is never assigned. + + +Inout <DQ<10>> is never assigned. + + +Inout <DQ<5>> is never assigned. + + +Inout <DQ<11>> is never assigned. + + +Inout <DQ<6>> is never assigned. + + +Inout <DQ<12>> is never assigned. + + +Output <CFOUT> is never assigned. + + +Inout <DQ<7>> is never assigned. + + +Inout <DQ<13>> is never assigned. + + +Output <LAN_WRH> is never assigned. + + +Input <DS0> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <DS1> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Inout <DQ<8>> is never assigned. + + +Inout <DQ<14>> is never assigned. + + +Input <FCS> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Inout <DQ<9>> is never assigned. + + +Inout <DQ<15>> is never assigned. + + +Output <CP_CS> is never assigned. + + +Output <LAN_CFG> is never assigned. + + +Output <MTACK> is never assigned. + + +Input <LAN_INT> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Output <INT_OUT> is never assigned. + + +Output <LAN_RD> is never assigned. + + +Inout <A<14>> is never assigned. + + +Inout <A<15>> is never assigned. + + +Input <CP_IRQ> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Output <CP_RD> is never assigned. + + +Input <Z3> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Inout <A<7>> is never assigned. + + +Inout <A<8>> is never assigned. + + +Output <CP_WE> is never assigned. + + +Input <CFIN> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <CLK_EXT> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Output <OVR> is never assigned. + + +Output <OWN> is never assigned. + + +Input <MTCR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Output <A_LAN> is never assigned. + + +Signal <SHUT_UP<2>> is assigned but never used. This unconnected signal will be trimmed during the optimization process. + + +Signal <SHUT_UP<0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process. + + +Signal <LAN_BASEADR> is assigned but never used. This unconnected signal will be trimmed during the optimization process. + + +Signal <DTACK_S> is never used or assigned. This unconnected signal will be trimmed during the optimization process. + + +Signal <CP_BASEADR> is assigned but never used. This unconnected signal will be trimmed during the optimization process. + + +Signal <AS_D> is never used or assigned. This unconnected signal will be trimmed during the optimization process. + + + + diff --git a/Logic/LAN_IDE/iseconfig/LAN_IDE_CP.xreport b/Logic/LAN_IDE/iseconfig/LAN_IDE_CP.xreport index fd3309e..bb55510 100644 --- a/Logic/LAN_IDE/iseconfig/LAN_IDE_CP.xreport +++ b/Logic/LAN_IDE/iseconfig/LAN_IDE_CP.xreport @@ -1,11 +1,11 @@
      - 2016-12-13T22:08:30 + 2016-12-15T18:39:52 LAN_IDE_CP Unknown C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/iseconfig/LAN_IDE_CP.xreport - C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE + C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE\ 2016-12-13T22:08:29 false
      diff --git a/Logic/LAN_IDE/pepExtractor.prj b/Logic/LAN_IDE/pepExtractor.prj new file mode 100644 index 0000000..30d69dc --- /dev/null +++ b/Logic/LAN_IDE/pepExtractor.prj @@ -0,0 +1 @@ +work "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.vhd" diff --git a/Logic/LAN_IDE/pinlist.lfp b/Logic/LAN_IDE/pinlist.lfp new file mode 100644 index 0000000..0fdeeb5 --- /dev/null +++ b/Logic/LAN_IDE/pinlist.lfp @@ -0,0 +1,93 @@ +# begin LFP file C:\Users\Matze\Amiga\Hardwarehacks\Zorro-LAN-IDE\Logic\LAN_IDE\pinlist.lfp +designfile LAN_IDE_CP.vhd +parttype xc95144xl-tq144-10 +bus_delimiter 0; +set_busdelim_onsave 1; +IO_GROUP "A" ; +IO_GROUP "D" ; +IO_GROUP "DQ" ; +IO_GROUP "A_LAN" ; +IO_GROUP "ROM_B" ; +IO_GROUP "IDE_A" ; +IO_GROUP "IDE_CS" ; +IO_GROUP "LAN_CFG" ; +NET "A<23>" IO_GROUP="A" ; +NET "A<22>" IO_GROUP="A" ; +NET "A<21>" IO_GROUP="A" ; +NET "A<20>" IO_GROUP="A" ; +NET "A<19>" IO_GROUP="A" ; +NET "A<18>" IO_GROUP="A" ; +NET "A<17>" IO_GROUP="A" ; +NET "A<16>" IO_GROUP="A" ; +NET "A<15>" IO_GROUP="A" ; +NET "A<14>" IO_GROUP="A" ; +NET "A<13>" IO_GROUP="A" ; +NET "A<12>" IO_GROUP="A" ; +NET "A<11>" IO_GROUP="A" ; +NET "A<10>" IO_GROUP="A" ; +NET "A<9>" IO_GROUP="A" ; +NET "A<8>" IO_GROUP="A" ; +NET "A<7>" IO_GROUP="A" ; +NET "A<6>" IO_GROUP="A" ; +NET "A<5>" IO_GROUP="A" ; +NET "A<4>" IO_GROUP="A" ; +NET "A<3>" IO_GROUP="A" ; +NET "A<2>" IO_GROUP="A" ; +NET "A<1>" IO_GROUP="A" ; +NET "D<15>" IO_GROUP="D" ; +NET "D<14>" IO_GROUP="D" ; +NET "D<13>" IO_GROUP="D" ; +NET "D<12>" IO_GROUP="D" ; +NET "D<11>" IO_GROUP="D" ; +NET "D<10>" IO_GROUP="D" ; +NET "D<9>" IO_GROUP="D" ; +NET "D<8>" IO_GROUP="D" ; +NET "D<7>" IO_GROUP="D" ; +NET "D<6>" IO_GROUP="D" ; +NET "D<5>" IO_GROUP="D" ; +NET "D<4>" IO_GROUP="D" ; +NET "D<3>" IO_GROUP="D" ; +NET "D<2>" IO_GROUP="D" ; +NET "D<1>" IO_GROUP="D" ; +NET "D<0>" IO_GROUP="D" ; +NET "DQ<15>" IO_GROUP="DQ" ; +NET "DQ<14>" IO_GROUP="DQ" ; +NET "DQ<13>" IO_GROUP="DQ" ; +NET "DQ<12>" IO_GROUP="DQ" ; +NET "DQ<11>" IO_GROUP="DQ" ; +NET "DQ<10>" IO_GROUP="DQ" ; +NET "DQ<9>" IO_GROUP="DQ" ; +NET "DQ<8>" IO_GROUP="DQ" ; +NET "DQ<7>" IO_GROUP="DQ" ; +NET "DQ<6>" IO_GROUP="DQ" ; +NET "DQ<5>" IO_GROUP="DQ" ; +NET "DQ<4>" IO_GROUP="DQ" ; +NET "DQ<3>" IO_GROUP="DQ" ; +NET "DQ<2>" IO_GROUP="DQ" ; +NET "DQ<1>" IO_GROUP="DQ" ; +NET "DQ<0>" IO_GROUP="DQ" ; +NET "A_LAN<13>" IO_GROUP="A_LAN" ; +NET "A_LAN<12>" IO_GROUP="A_LAN" ; +NET "A_LAN<11>" IO_GROUP="A_LAN" ; +NET "A_LAN<10>" IO_GROUP="A_LAN" ; +NET "A_LAN<9>" IO_GROUP="A_LAN" ; +NET "A_LAN<8>" IO_GROUP="A_LAN" ; +NET "A_LAN<7>" IO_GROUP="A_LAN" ; +NET "A_LAN<6>" IO_GROUP="A_LAN" ; +NET "A_LAN<5>" IO_GROUP="A_LAN" ; +NET "A_LAN<4>" IO_GROUP="A_LAN" ; +NET "A_LAN<3>" IO_GROUP="A_LAN" ; +NET "A_LAN<2>" IO_GROUP="A_LAN" ; +NET "A_LAN<1>" IO_GROUP="A_LAN" ; +NET "A_LAN<0>" IO_GROUP="A_LAN" ; +NET "ROM_B<1>" IO_GROUP="ROM_B" ; +NET "ROM_B<0>" IO_GROUP="ROM_B" ; +NET "IDE_A<2>" IO_GROUP="IDE_A" ; +NET "IDE_A<1>" IO_GROUP="IDE_A" ; +NET "IDE_A<0>" IO_GROUP="IDE_A" ; +NET "IDE_CS<1>" IO_GROUP="IDE_CS" ; +NET "IDE_CS<0>" IO_GROUP="IDE_CS" ; +NET "LAN_CFG<4>" IO_GROUP="LAN_CFG" ; +NET "LAN_CFG<3>" IO_GROUP="LAN_CFG" ; +NET "LAN_CFG<2>" IO_GROUP="LAN_CFG" ; +NET "LAN_CFG<1>" IO_GROUP="LAN_CFG" ; diff --git a/Logic/LAN_IDE/pinlist.ucf b/Logic/LAN_IDE/pinlist.ucf new file mode 100644 index 0000000..92a4910 --- /dev/null +++ b/Logic/LAN_IDE/pinlist.ucf @@ -0,0 +1,125 @@ +#PACE: Start of Constraints generated by PACE + +#PACE: Start of PACE I/O Pin Assignments +NET "A<10>" LOC = "P59" ; +NET "A<11>" LOC = "P60" ; +NET "A<12>" LOC = "P61" ; +NET "A<13>" LOC = "P64" ; +NET "A<14>" LOC = "P66" ; +NET "A<15>" LOC = "P74" ; +NET "A<16>" LOC = "P97" ; +NET "A<17>" LOC = "P95" ; +NET "A<18>" LOC = "P94" ; +NET "A<19>" LOC = "P92" ; +NET "A<1>" LOC = "P57" ; +NET "A<20>" LOC = "P91" ; +NET "A<21>" LOC = "P88" ; +NET "A<22>" LOC = "P87" ; +NET "A<23>" LOC = "P86" ; +NET "A<2>" LOC = "P54" ; +NET "A<3>" LOC = "P52" ; +NET "A<4>" LOC = "P50" ; +NET "A<5>" LOC = "P49" ; +NET "A<6>" LOC = "P51" ; +NET "A<7>" LOC = "P53" ; +NET "A<8>" LOC = "P56" ; +NET "A<9>" LOC = "P58" ; +NET "A_LAN<0>" LOC = "P4" ; +NET "A_LAN<10>" LOC = "P138" ; +NET "A_LAN<11>" LOC = "P139" ; +NET "A_LAN<12>" LOC = "P137" ; +NET "A_LAN<13>" LOC = "P136" ; +NET "A_LAN<1>" LOC = "P3" ; +NET "A_LAN<2>" LOC = "P6" ; +NET "A_LAN<3>" LOC = "P5" ; +NET "A_LAN<4>" LOC = "P9" ; +NET "A_LAN<5>" LOC = "P7" ; +NET "A_LAN<6>" LOC = "P11" ; +NET "A_LAN<7>" LOC = "P10" ; +NET "A_LAN<8>" LOC = "P140" ; +NET "A_LAN<9>" LOC = "P142" ; +NET "AS" LOC = "P80" ; +NET "AUTOBOOT_OFF" LOC = "P75" ; +NET "BERR" LOC = "P98" ; +NET "C1" LOC = "P103" ; +NET "C3" LOC = "P102" ; +NET "CFIN" LOC = "P104" ; +NET "CFOUT" LOC = "P105" ; +NET "CLK_EXT" LOC = "P30" ; +NET "CP_CS" LOC = "P34" ; +NET "CP_IRQ" LOC = "P31" ; +NET "CP_RD" LOC = "P71" ; +NET "CP_WE" LOC = "P70" ; +NET "D<0>" LOC = "P2" ; +NET "D<10>" LOC = "P41" ; +NET "D<11>" LOC = "P43" ; +NET "D<12>" LOC = "P44" ; +NET "D<13>" LOC = "P45" ; +NET "D<14>" LOC = "P46" ; +NET "D<15>" LOC = "P48" ; +NET "D<1>" LOC = "P17" ; +NET "D<2>" LOC = "P39" ; +NET "D<3>" LOC = "P15" ; +NET "D<4>" LOC = "P21" ; +NET "D<5>" LOC = "P20" ; +NET "D<6>" LOC = "P14" ; +NET "D<7>" LOC = "P16" ; +NET "D<8>" LOC = "P19" ; +NET "D<9>" LOC = "P40" ; +NET "DQ<0>" LOC = "P118" ; +NET "DQ<10>" LOC = "P129" ; +NET "DQ<11>" LOC = "P115" ; +NET "DQ<12>" LOC = "P130" ; +NET "DQ<13>" LOC = "P113" ; +NET "DQ<14>" LOC = "P131" ; +NET "DQ<15>" LOC = "P112" ; +NET "DQ<1>" LOC = "P117" ; +NET "DQ<2>" LOC = "P120" ; +NET "DQ<3>" LOC = "P119" ; +NET "DQ<4>" LOC = "P124" ; +NET "DQ<5>" LOC = "P121" ; +NET "DQ<6>" LOC = "P126" ; +NET "DQ<7>" LOC = "P125" ; +NET "DQ<8>" LOC = "P128" ; +NET "DQ<9>" LOC = "P116" ; +NET "DS0" LOC = "P93" ; +NET "DS1" LOC = "P78" ; +NET "DTACK" LOC = "P85" ; +NET "FCS" LOC = "P77" ; +NET "IDE_A<0>" LOC = "P24" ; +NET "IDE_A<1>" LOC = "P26" ; +NET "IDE_A<2>" LOC = "P25" ; +NET "IDE_CS<0>" LOC = "P22" ; +NET "IDE_CS<1>" LOC = "P23" ; +NET "IDE_R" LOC = "P27" ; +NET "IDE_W" LOC = "P28" ; +NET "IDE_WAIT" LOC = "P33" ; +NET "INT_OUT" LOC = "P32" ; +NET "LAN_CFG<1>" LOC = "P12" ; +NET "LAN_CFG<2>" LOC = "P135" ; +NET "LAN_CFG<3>" LOC = "P13" ; +NET "LAN_CFG<4>" LOC = "P110" ; +NET "LAN_CS" LOC = "P133" ; +NET "LAN_EN" LOC = "P76" ; +NET "LAN_INT" LOC = "P111" ; +NET "LAN_RD" LOC = "P134" ; +NET "LAN_WRH" LOC = "P132" ; +NET "LDS" LOC = "P82" ; +NET "MTACK" LOC = "P96" ; +NET "MTCR" LOC = "P101" ; +NET "OVR" LOC = "P100" ; +NET "OWN" LOC = "P107" ; +NET "RESET" LOC = "P143" ; +NET "ROM_B<0>" LOC = "P68" ; +NET "ROM_B<1>" LOC = "P69" ; +NET "ROM_OE" LOC = "P35" ; +NET "RW" LOC = "P83" ; +NET "SLAVE" LOC = "P106" ; +NET "UDS" LOC = "P81" ; +NET "Z3" LOC = "P79" ; + +#PACE: Start of PACE Area Constraints + +#PACE: Start of PACE Prohibit Constraints + +#PACE: End of Constraints generated by PACE diff --git a/Logic/LAN_IDE/tmperr.err b/Logic/LAN_IDE/tmperr.err new file mode 100644 index 0000000..e69de29 diff --git a/Logic/LAN_IDE/webtalk_pn.xml b/Logic/LAN_IDE/webtalk_pn.xml new file mode 100644 index 0000000..a41706b --- /dev/null +++ b/Logic/LAN_IDE/webtalk_pn.xml @@ -0,0 +1,43 @@ + + + + +
      + + + + +
      +
      + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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