diff --git a/Bilder/Aufgebaut.jpg b/Bilder/Aufgebaut.jpg
index b612360..56c237e 100644
Binary files a/Bilder/Aufgebaut.jpg and b/Bilder/Aufgebaut.jpg differ
diff --git a/Bilder/Autoconfig.jpg b/Bilder/Autoconfig.jpg
new file mode 100644
index 0000000..a8c55ed
Binary files /dev/null and b/Bilder/Autoconfig.jpg differ
diff --git a/Bilder/Hardware.jpg b/Bilder/Hardware.jpg
new file mode 100644
index 0000000..9591ed5
Binary files /dev/null and b/Bilder/Hardware.jpg differ
diff --git a/Logic/LAN_IDE/LAN_IDE.gise b/Logic/LAN_IDE/LAN_IDE.gise
index 9973d4b..dbbc078 100644
--- a/Logic/LAN_IDE/LAN_IDE.gise
+++ b/Logic/LAN_IDE/LAN_IDE.gise
@@ -21,8 +21,84 @@
 
   <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="LAN_IDE.xise"/>
 
-  <files xmlns="http://www.xilinx.com/XMLSchema"/>
+  <files xmlns="http://www.xilinx.com/XMLSchema">
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="LAN_IDE_CP.bld"/>
+    <file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="LAN_IDE_CP.cmd_log"/>
+    <file xil_pn:fileType="FILE_LFP" xil_pn:name="LAN_IDE_CP.lfp"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="LAN_IDE_CP.lso"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="LAN_IDE_CP.ngc"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGD" xil_pn:name="LAN_IDE_CP.ngd"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="LAN_IDE_CP.ngr"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="LAN_IDE_CP.prj"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="LAN_IDE_CP.stx"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="LAN_IDE_CP.syr"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="LAN_IDE_CP.xst"/>
+    <file xil_pn:fileType="FILE_XRPT" xil_pn:name="LAN_IDE_CP_ngdbuild.xrpt"/>
+    <file xil_pn:fileType="FILE_HTML" xil_pn:name="LAN_IDE_CP_summary.html"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="LAN_IDE_CP_vhdl.prj"/>
+    <file xil_pn:fileType="FILE_XRPT" xil_pn:name="LAN_IDE_CP_xst.xrpt"/>
+    <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="_ngo"/>
+    <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
+    <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/xst.xmsgs"/>
+    <file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="webtalk_pn.xml"/>
+    <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xlnx_auto_0_xdb"/>
+    <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xst"/>
+  </files>
 
-  <transforms xmlns="http://www.xilinx.com/XMLSchema"/>
+  <transforms xmlns="http://www.xilinx.com/XMLSchema">
+    <transform xil_pn:end_ts="1481823627" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1481823627">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+    </transform>
+    <transform xil_pn:end_ts="1481823627" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="5081391373936803697" xil_pn:start_ts="1481823627">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+    </transform>
+    <transform xil_pn:end_ts="1481823641" xil_pn:in_ck="-2520376148396271922" xil_pn:name="TRANEXT_xstsynthesize_xc9500xl" xil_pn:prop_ck="-3821115760053952169" xil_pn:start_ts="1481823627">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="WarningsGenerated"/>
+      <status xil_pn:value="ReadyToRun"/>
+      <status xil_pn:value="OutOfDateForInputs"/>
+      <status xil_pn:value="InputChanged"/>
+      <outfile xil_pn:name="LAN_IDE_CP.lso"/>
+      <outfile xil_pn:name="LAN_IDE_CP.ngc"/>
+      <outfile xil_pn:name="LAN_IDE_CP.ngr"/>
+      <outfile xil_pn:name="LAN_IDE_CP.prj"/>
+      <outfile xil_pn:name="LAN_IDE_CP.stx"/>
+      <outfile xil_pn:name="LAN_IDE_CP.syr"/>
+      <outfile xil_pn:name="LAN_IDE_CP.xst"/>
+      <outfile xil_pn:name="LAN_IDE_CP_vhdl.prj"/>
+      <outfile xil_pn:name="LAN_IDE_CP_xst.xrpt"/>
+      <outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
+      <outfile xil_pn:name="webtalk_pn.xml"/>
+      <outfile xil_pn:name="xst"/>
+    </transform>
+    <transform xil_pn:end_ts="1481823642" xil_pn:in_ck="176569500195729039" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-8537920303570934858" xil_pn:start_ts="1481823641">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+      <status xil_pn:value="OutOfDateForInputs"/>
+      <status xil_pn:value="InputChanged"/>
+    </transform>
+    <transform xil_pn:end_ts="1481823651" xil_pn:in_ck="-8547647177936735053" xil_pn:name="TRAN_ngdbuild" xil_pn:prop_ck="-1996509353111835880" xil_pn:start_ts="1481823642">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="WarningsGenerated"/>
+      <status xil_pn:value="ReadyToRun"/>
+      <status xil_pn:value="OutOfDateForInputs"/>
+      <status xil_pn:value="OutOfDateForPredecessor"/>
+      <status xil_pn:value="InputChanged"/>
+      <outfile xil_pn:name="LAN_IDE_CP.bld"/>
+      <outfile xil_pn:name="LAN_IDE_CP.ngd"/>
+      <outfile xil_pn:name="LAN_IDE_CP_ngdbuild.xrpt"/>
+      <outfile xil_pn:name="_ngo"/>
+      <outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
+    </transform>
+    <transform xil_pn:end_ts="1481823675" xil_pn:in_ck="-8497105071423008236" xil_pn:name="TRAN_createTimingConstraints" xil_pn:start_ts="1481823675">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+      <status xil_pn:value="OutOfDateForInputs"/>
+      <status xil_pn:value="OutOfDateForPredecessor"/>
+      <status xil_pn:value="InputChanged"/>
+    </transform>
+  </transforms>
 
 </generated_project>
diff --git a/Logic/LAN_IDE/LAN_IDE.xise b/Logic/LAN_IDE/LAN_IDE.xise
index ab3d1e6..fbbe06e 100644
--- a/Logic/LAN_IDE/LAN_IDE.xise
+++ b/Logic/LAN_IDE/LAN_IDE.xise
@@ -19,134 +19,63 @@
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
     </file>
+    <file xil_pn:name="pinlist.ucf" xil_pn:type="FILE_UCF">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
   </files>
 
   <properties>
-    <property xil_pn:name="AES Initial Vector virtex6" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="AES Key (Hex String) virtex6" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
-    <property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Auto Implementation Top" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Autosignature Generation" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="BPI Reads Per Page" xil_pn:value="1" xil_pn:valueState="default"/>
-    <property xil_pn:name="BPI Sync Mode" xil_pn:value="Disable" xil_pn:valueState="default"/>
-    <property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
     <property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
     <property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
     <property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
-    <property xil_pn:name="Change Device Speed To" xil_pn:value="-10" xil_pn:valueState="default"/>
-    <property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-10" xil_pn:valueState="default"/>
     <property xil_pn:name="Clock Enable" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Collapsing Input Limit (2-54)" xil_pn:value="54" xil_pn:valueState="default"/>
     <property xil_pn:name="Collapsing Pterm Limit (1-90)" xil_pn:value="25" xil_pn:valueState="default"/>
-    <property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Compile CPLD Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Compile uni9000 (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Pin Init" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Rate virtex5" xil_pn:value="3" xil_pn:valueState="default"/>
-    <property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Create Programmable GND Pins on Unused I/O" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Cycles for First BPI Page Read" xil_pn:value="1" xil_pn:valueState="default"/>
-    <property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="default"/>
-    <property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
     <property xil_pn:name="Default Powerup Value of Registers" xil_pn:value="Low" xil_pn:valueState="default"/>
     <property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
     <property xil_pn:name="Device" xil_pn:value="xc95144xl" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Device Family" xil_pn:value="XC9500XL CPLDs" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-10" xil_pn:valueState="default"/>
-    <property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Disable JTAG Connection" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Cyclic Redundancy Checking (CRC)" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable External Master Clock" xil_pn:value="Disable" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Multi-Threading par virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Encrypt Bitstream virtex6" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Encrypt Key Select virtex6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
     <property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
-    <property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Exhaustive Fit Mode" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Extra Cost Tables Map virtex6" xil_pn:value="0" xil_pn:valueState="default"/>
-    <property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
-    <property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
     <property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
-    <property xil_pn:name="Fallback Reconfiguration virtex7" xil_pn:value="Disable" xil_pn:valueState="default"/>
     <property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="VHDL" xil_pn:valueState="default"/>
     <property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="VHDL" xil_pn:valueState="default"/>
     <property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="VHDL" xil_pn:valueState="default"/>
     <property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Generate Post-Fit Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
     <property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
-    <property xil_pn:name="Global Optimization map virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
     <property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
     <property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
     <property xil_pn:name="HDL Equations Style" xil_pn:value="Source" xil_pn:valueState="default"/>
-    <property xil_pn:name="HMAC Key (Hex String)" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
     <property xil_pn:name="I/O Pin Termination" xil_pn:value="Keeper" xil_pn:valueState="default"/>
-    <property xil_pn:name="ICAP Select" xil_pn:value="Auto" xil_pn:valueState="default"/>
     <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
-    <property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Implementation Template" xil_pn:value="Optimize Balance" xil_pn:valueState="default"/>
     <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|LAN_IDE_CP|Behavioral" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Implementation Top File" xil_pn:value="LAN_IDE_CP.vhd" xil_pn:valueState="non-default"/>
@@ -158,15 +87,8 @@
     <property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="VHDL" xil_pn:valueState="default"/>
-    <property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="JTAG to XADC Connection" xil_pn:value="Enable" xil_pn:valueState="default"/>
     <property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
     <property xil_pn:name="Keep Hierarchy CPLD" xil_pn:value="Yes" xil_pn:valueState="default"/>
-    <property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
-    <property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
     <property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
     <property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
     <property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
@@ -178,25 +100,14 @@
     <property xil_pn:name="Macro Preserve" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Macrocell Power Setting" xil_pn:value="Std" xil_pn:valueState="default"/>
     <property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
-    <property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
     <property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
-    <property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile virtex7" xil_pn:value="Enable" xil_pn:valueState="default"/>
     <property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
     <property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
-    <property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
-    <property xil_pn:name="Number of Clock Buffers" xil_pn:value="32" xil_pn:valueState="default"/>
-    <property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
-    <property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Number of Clock Buffers" xil_pn:value="4" xil_pn:valueState="default"/>
     <property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/>
-    <property xil_pn:name="Optimization Effort virtex6" xil_pn:value="Normal" xil_pn:valueState="default"/>
     <property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
-    <property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Other CPLD Fitter Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Other Compiler Options Fit" xil_pn:value="" xil_pn:valueState="default"/>
@@ -204,16 +115,11 @@
     <property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Other Programming Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Other Simulator Commands Fit" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Other Timing Report Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
@@ -221,75 +127,35 @@
     <property xil_pn:name="Output File Name" xil_pn:value="LAN_IDE_CP" xil_pn:valueState="default"/>
     <property xil_pn:name="Output Slew Rate" xil_pn:value="Fast" xil_pn:valueState="default"/>
     <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
     <property xil_pn:name="Package" xil_pn:value="TQ144" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
-    <property xil_pn:name="Place And Route Mode" xil_pn:value="Route Only" xil_pn:valueState="default"/>
-    <property xil_pn:name="Place MultiBoot Settings into Bitstream virtex7" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
-    <property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
     <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
     <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="LAN_IDE_CP_map.vhd" xil_pn:valueState="default"/>
     <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="LAN_IDE_CP_timesim.vhd" xil_pn:valueState="default"/>
     <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="LAN_IDE_CP_synthesis.vhd" xil_pn:valueState="default"/>
     <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="LAN_IDE_CP_translate.vhd" xil_pn:valueState="default"/>
-    <property xil_pn:name="Power Down Device if Over Safe Temperature" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Power Reduction Map virtex6" xil_pn:value="Off" xil_pn:valueState="default"/>
-    <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Preserve Unused Inputs" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
-    <property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
     <property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
-    <property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
-    <property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
-    <property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Register Ordering virtex6" xil_pn:value="4" xil_pn:valueState="default"/>
-    <property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
     <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
     <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
     <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="LAN_IDE_CP" xil_pn:valueState="default"/>
     <property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
     <property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Revision Select" xil_pn:value="00" xil_pn:valueState="default"/>
-    <property xil_pn:name="Revision Select Tristate" xil_pn:value="Disable" xil_pn:valueState="default"/>
-    <property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="SPI 32-bit Addressing" xil_pn:value="No" xil_pn:valueState="default"/>
     <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
-    <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
     <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
-    <property xil_pn:name="Set SPI Configuration Bus Width" xil_pn:value="1" xil_pn:valueState="default"/>
-    <property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Shift Register Minimum Size virtex6" xil_pn:value="2" xil_pn:valueState="default"/>
     <property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Signature /User Code" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/>
@@ -298,33 +164,19 @@
     <property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
     <property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
     <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
     <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
     <property xil_pn:name="Specify Top Level Instance Names Fit" xil_pn:value="Default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
     <property xil_pn:name="Speed Grade" xil_pn:value="-10" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Starting Address for Fallback Configuration virtex7" xil_pn:value="None" xil_pn:valueState="default"/>
-    <property xil_pn:name="Starting Placer Cost Table (1-100)" xil_pn:value="1" xil_pn:valueState="default"/>
     <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
     <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
-    <property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
-    <property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
+    <property xil_pn:name="Target UCF File Name" xil_pn:value="pinlist.ucf" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Timing Report Format" xil_pn:value="Summary" xil_pn:valueState="default"/>
-    <property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
-    <property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
-    <property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
     <property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
     <property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Use Custom Project File Fit" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
@@ -334,34 +186,22 @@
     <property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use DSP Block" xil_pn:value="Auto" xil_pn:valueState="default"/>
     <property xil_pn:name="Use Global Clocks" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Use Global Output Enables" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Use Global Set/Reset" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Use Location Constraints" xil_pn:value="Always" xil_pn:valueState="default"/>
     <property xil_pn:name="Use Multi-level Logic Optimization" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use SPI Falling Edge" xil_pn:value="No" xil_pn:valueState="default"/>
     <property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
     <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Use Timing Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="User Access Register Value" xil_pn:value="None" xil_pn:valueState="default"/>
-    <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
+    <property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="VCCIO Reference Voltage" xil_pn:value="LVTTL" xil_pn:valueState="default"/>
     <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
     <property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="WYSIWYG" xil_pn:value="None" xil_pn:valueState="default"/>
-    <property xil_pn:name="Wait for DCI Match (Output Events) virtex5" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Wait for PLL Lock (Output Events) virtex6" xil_pn:value="No Wait" xil_pn:valueState="default"/>
-    <property xil_pn:name="Watchdog Timer Mode 7-series" xil_pn:value="Off" xil_pn:valueState="default"/>
-    <property xil_pn:name="Watchdog Timer Value 7-series" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
     <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="XOR Preserve" xil_pn:value="true" xil_pn:valueState="default"/>
     <!--                                                                                  -->
     <!-- The following properties are for internal use only. These should not be modified.-->
diff --git a/Logic/LAN_IDE/LAN_IDE_CP.bld b/Logic/LAN_IDE/LAN_IDE_CP.bld
new file mode 100644
index 0000000..46b5398
--- /dev/null
+++ b/Logic/LAN_IDE/LAN_IDE_CP.bld
@@ -0,0 +1,58 @@
+Release 14.6 ngdbuild P.68d (nt64)
+Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
+
+Command Line: C:\Xilinx\14.6\ISE_DS\ISE\bin\nt64\unwrapped\ngdbuild.exe
+-intstyle ise -dd _ngo -uc pinlist.ucf -p xc95144xl-TQ144-10 LAN_IDE_CP.ngc
+LAN_IDE_CP.ngd
+
+Reading NGO file
+"C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.ngc"
+...
+Gathering constraint information from source properties...
+Done.
+
+Annotating constraints to design from ucf file "pinlist.ucf" ...
+Resolving constraint associations...
+Checking Constraint Associations...
+Done...
+
+Checking expanded design ...
+WARNING:NgdBuild:470 - bidirect pad net 'DQ<0>' has no legal driver
+WARNING:NgdBuild:470 - bidirect pad net 'DQ<1>' has no legal driver
+WARNING:NgdBuild:470 - bidirect pad net 'DQ<2>' has no legal driver
+WARNING:NgdBuild:470 - bidirect pad net 'DQ<3>' has no legal driver
+WARNING:NgdBuild:470 - bidirect pad net 'DQ<4>' has no legal driver
+WARNING:NgdBuild:470 - bidirect pad net 'DQ<10>' has no legal driver
+WARNING:NgdBuild:470 - bidirect pad net 'DQ<5>' has no legal driver
+WARNING:NgdBuild:470 - bidirect pad net 'DQ<11>' has no legal driver
+WARNING:NgdBuild:470 - bidirect pad net 'DQ<6>' has no legal driver
+WARNING:NgdBuild:470 - bidirect pad net 'DQ<12>' has no legal driver
+WARNING:NgdBuild:470 - bidirect pad net 'DQ<7>' has no legal driver
+WARNING:NgdBuild:470 - bidirect pad net 'DQ<13>' has no legal driver
+WARNING:NgdBuild:470 - bidirect pad net 'DQ<8>' has no legal driver
+WARNING:NgdBuild:470 - bidirect pad net 'DQ<14>' has no legal driver
+WARNING:NgdBuild:470 - bidirect pad net 'DQ<9>' has no legal driver
+WARNING:NgdBuild:470 - bidirect pad net 'DQ<15>' has no legal driver
+WARNING:NgdBuild:470 - bidirect pad net 'A<14>' has no legal driver
+WARNING:NgdBuild:470 - bidirect pad net 'A<15>' has no legal driver
+WARNING:NgdBuild:470 - bidirect pad net 'A<7>' has no legal driver
+WARNING:NgdBuild:470 - bidirect pad net 'A<8>' has no legal driver
+
+Partition Implementation Status
+-------------------------------
+
+  No Partitions were found in this design.
+
+-------------------------------
+
+NGDBUILD Design Results Summary:
+  Number of errors:     0
+  Number of warnings:  20
+
+Total memory usage is 190196 kilobytes
+
+Writing NGD file "LAN_IDE_CP.ngd" ...
+Total REAL time to NGDBUILD completion:  5 sec
+Total CPU time to NGDBUILD completion:   5 sec
+
+Writing NGDBUILD log file "LAN_IDE_CP.bld"...
diff --git a/Logic/LAN_IDE/LAN_IDE_CP.cmd_log b/Logic/LAN_IDE/LAN_IDE_CP.cmd_log
new file mode 100644
index 0000000..10909b3
--- /dev/null
+++ b/Logic/LAN_IDE/LAN_IDE_CP.cmd_log
@@ -0,0 +1,42 @@
+xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr" 
+ngdbuild -intstyle ise -dd _ngo -i -p xc95144xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd  
+xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr" 
+xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr" 
+xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr" 
+xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr" 
+xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr" 
+xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr" 
+xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr" 
+ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95144xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd  
+cpldfit -intstyle ise -p xc95144xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd 
+XSLTProcess LAN_IDE_CP_build.xml 
+tsim -intstyle ise LAN_IDE_CP LAN_IDE_CP.nga 
+taengine -intstyle ise -f LAN_IDE_CP -w --format html1 -l LAN_IDE_CP_html/tim/timing_report.htm 
+hprep6 -s IEEE1149 -n LAN_IDE_CP -i LAN_IDE_CP 
+xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr" 
+xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr" 
+ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95144xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd  
+cpldfit -intstyle ise -p xc95144xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd 
+XSLTProcess LAN_IDE_CP_build.xml 
+tsim -intstyle ise LAN_IDE_CP LAN_IDE_CP.nga 
+hprep6 -s IEEE1149 -n LAN_IDE_CP -i LAN_IDE_CP 
+xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr" 
+ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95144xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd  
+cpldfit -intstyle ise -p xc95144xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd 
+XSLTProcess LAN_IDE_CP_build.xml 
+tsim -intstyle ise LAN_IDE_CP LAN_IDE_CP.nga 
+hprep6 -s IEEE1149 -n LAN_IDE_CP -i LAN_IDE_CP 
+xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr" 
+xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr" 
+ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95144xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd  
+cpldfit -intstyle ise -p xc95144xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd 
+XSLTProcess LAN_IDE_CP_build.xml 
+tsim -intstyle ise LAN_IDE_CP LAN_IDE_CP.nga 
+hprep6 -s IEEE1149 -n LAN_IDE_CP -i LAN_IDE_CP 
+xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr" 
+xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr" 
+ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95144xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd  
+cpldfit -intstyle ise -p xc95144xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd 
+XSLTProcess LAN_IDE_CP_build.xml 
+tsim -intstyle ise LAN_IDE_CP LAN_IDE_CP.nga 
+hprep6 -s IEEE1149 -n LAN_IDE_CP -i LAN_IDE_CP 
diff --git a/Logic/LAN_IDE/LAN_IDE_CP.gyd b/Logic/LAN_IDE/LAN_IDE_CP.gyd
new file mode 100644
index 0000000..788deb2
--- /dev/null
+++ b/Logic/LAN_IDE/LAN_IDE_CP.gyd
@@ -0,0 +1,90 @@
+Pin Freeze File:  version P.68d
+
+95144XL144TQ XC95144XL-10-TQ144
+AS S:PIN80
+AUTOBOOT_OFF S:PIN75
+A<12> S:PIN61
+A<13> S:PIN64
+A<16> S:PIN97
+A<17> S:PIN95
+A<18> S:PIN94
+A<19> S:PIN92
+A<1> S:PIN57
+A<20> S:PIN91
+A<21> S:PIN88
+A<22> S:PIN87
+A<23> S:PIN86
+A<2> S:PIN54
+A<3> S:PIN52
+A<4> S:PIN50
+A<5> S:PIN49
+A<6> S:PIN51
+BERR S:PIN98
+C1 S:PIN103
+C3 S:PIN102
+A<9> S:PIN58
+A<10> S:PIN59
+A<11> S:PIN60
+RESET S:PIN143
+RW S:PIN83
+UDS S:PIN81
+IDE_A<0> S:PIN24
+IDE_A<1> S:PIN26
+IDE_A<2> S:PIN25
+IDE_CS<0> S:PIN22
+IDE_CS<1> S:PIN23
+IDE_R S:PIN27
+IDE_W S:PIN28
+D<9> S:PIN40
+D<8> S:PIN19
+D<7> S:PIN16
+D<0> S:PIN2
+D<6> S:PIN14
+D<5> S:PIN20
+D<4> S:PIN21
+D<3> S:PIN15
+D<2> S:PIN39
+D<1> S:PIN17
+D<11> S:PIN43
+D<10> S:PIN41
+ROM_B<1> S:PIN69
+ROM_B<0> S:PIN68
+DTACK S:PIN85
+ROM_OE S:PIN35
+D<12> S:PIN44
+D<14> S:PIN46
+D<13> S:PIN45
+D<15> S:PIN48
+
+
+;The remaining section of the .gyd file is for documentation purposes only.
+;It shows where your internal equations were placed in the last successful fit.
+
+PARTITION FB1_1 IDE_CS_1_OBUF N1$BUF1 N1$BUF7 IDE_A_2_OBUF$BUF0
+		 N1$BUF0 N1$BUF3 AUTOCONFIG_IN_PROGRESS N1$BUF4
+		 IDE_CS_0_OBUF IDE_ENABLE IDE_A_0_OBUF$BUF0 IDE_A_1_OBUF$BUF0
+		
+PARTITION FB1_14 IDE_R_S IDE_W_S ROM_OE_S EXP14_
+		 D<12>_BUFR.MC
+PARTITION FB2_1 D<14>_BUFR.MC EXP15_ EXP16_
+PARTITION FB2_5 N1$BUF10
+PARTITION FB2_8 AUTO_CONFIG_DONE<2> AUTO_CONFIG_DONE<0> AUTO_CONFIG_DONE_CYCLE<2> AUTO_CONFIG_DONE_CYCLE<0>
+		 IDE_BASEADR<7> IDE_BASEADR<6> EXP17_ D<13>_BUFR.MC
+		 N1$BUF2 N1$BUF5 EXP18_
+PARTITION FB3_1 N1$BUF6
+PARTITION FB3_3 N1$BUF9 _10_
+PARTITION FB3_7 _11_
+PARTITION FB3_9 N1 _13_ N1$BUF8 _12_
+		
+PARTITION FB3_15 AUTO_CONFIG_DONE<1> AUTO_CONFIG_DONE_CYCLE<1> IDE_BASEADR<3> IDE_BASEADR<2>
+		
+PARTITION FB4_1 ide EXP19_ EXP20_
+PARTITION FB4_16 ide/ide_CLKF autoconfig EXP21_
+PARTITION FB5_10 ROM_B_0_OBUF$BUF0
+PARTITION FB5_13 SHUT_UP<1> IDE_BASEADR<5> IDE_BASEADR<4> IDE_BASEADR<1>
+		 ROM_B_0_OBUF IDE_BASEADR<0>
+PARTITION FB6_16 EXP22_ D<15>_BUFR.MC EXP23_
+PARTITION FB7_12 ROM_B_0_OBUF$BUF1
+
+
+
diff --git a/Logic/LAN_IDE/LAN_IDE_CP.jed b/Logic/LAN_IDE/LAN_IDE_CP.jed
new file mode 100644
index 0000000..3c09d1a
--- /dev/null
+++ b/Logic/LAN_IDE/LAN_IDE_CP.jed
@@ -0,0 +1,1750 @@
+Programmer Jedec Bit Map
+Date Extracted: Thu Dec 15 19:48:51 2016
+
+QF93312*
+QP144*
+QV0*
+F0*
+X0*
+J0 0*
+N VERSION P.68d*
+N DEVICE XC95144XL-10-TQ144*
+N PPMAP 12 10*
+N PPMAP 112 100*
+N PPMAP 113 101*
+N PPMAP 114 102*
+N PPMAP 115 103*
+N PPMAP 116 104*
+N PPMAP 117 105*
+N PPMAP 118 106*
+N PPMAP 119 107*
+N PPMAP 13 11*
+N PPMAP 123 110*
+N PPMAP 124 111*
+N PPMAP 125 112*
+N PPMAP 127 113*
+N PPMAP 129 115*
+N PPMAP 130 116*
+N PPMAP 132 117*
+N PPMAP 133 118*
+N PPMAP 134 119*
+N PPMAP 14 12*
+N PPMAP 135 120*
+N PPMAP 136 121*
+N PPMAP 139 124*
+N PPMAP 140 125*
+N PPMAP 141 126*
+N PPMAP 143 128*
+N PPMAP 144 129*
+N PPMAP 15 13*
+N PPMAP 145 130*
+N PPMAP 146 131*
+N PPMAP 147 132*
+N PPMAP 148 133*
+N PPMAP 149 134*
+N PPMAP 152 135*
+N PPMAP 153 136*
+N PPMAP 154 137*
+N PPMAP 155 138*
+N PPMAP 156 139*
+N PPMAP 16 14*
+N PPMAP 157 140*
+N PPMAP 159 142*
+N PPMAP 160 143*
+N PPMAP 17 15*
+N PPMAP 18 16*
+N PPMAP 19 17*
+N PPMAP 21 19*
+N PPMAP 2 2*
+N PPMAP 22 20*
+N PPMAP 23 21*
+N PPMAP 24 22*
+N PPMAP 25 23*
+N PPMAP 26 24*
+N PPMAP 27 25*
+N PPMAP 28 26*
+N PPMAP 29 27*
+N PPMAP 30 28*
+N PPMAP 4 3*
+N PPMAP 33 30*
+N PPMAP 34 31*
+N PPMAP 35 32*
+N PPMAP 36 33*
+N PPMAP 37 34*
+N PPMAP 39 35*
+N PPMAP 42 38*
+N PPMAP 43 39*
+N PPMAP 5 4*
+N PPMAP 44 40*
+N PPMAP 45 41*
+N PPMAP 47 43*
+N PPMAP 48 44*
+N PPMAP 49 45*
+N PPMAP 50 46*
+N PPMAP 52 48*
+N PPMAP 54 49*
+N PPMAP 6 5*
+N PPMAP 56 50*
+N PPMAP 57 51*
+N PPMAP 58 52*
+N PPMAP 59 53*
+N PPMAP 60 54*
+N PPMAP 62 56*
+N PPMAP 63 57*
+N PPMAP 64 58*
+N PPMAP 66 59*
+N PPMAP 8 6*
+N PPMAP 68 60*
+N PPMAP 69 61*
+N PPMAP 72 64*
+N PPMAP 74 66*
+N PPMAP 76 68*
+N PPMAP 77 69*
+N PPMAP 9 7*
+N PPMAP 78 70*
+N PPMAP 79 71*
+N PPMAP 82 74*
+N PPMAP 84 75*
+N PPMAP 86 76*
+N PPMAP 87 77*
+N PPMAP 88 78*
+N PPMAP 89 79*
+N PPMAP 90 80*
+N PPMAP 91 81*
+N PPMAP 92 82*
+N PPMAP 93 83*
+N PPMAP 95 85*
+N PPMAP 96 86*
+N PPMAP 97 87*
+N PPMAP 98 88*
+N PPMAP 11 9*
+N PPMAP 102 91*
+N PPMAP 103 92*
+N PPMAP 104 93*
+N PPMAP 105 94*
+N PPMAP 106 95*
+N PPMAP 107 96*
+N PPMAP 108 97*
+N PPMAP 109 98*
+L0000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
+L0000064 00000000 00001000 00000000 00000000 00000100 00000000 00000000 00000000*
+L0000128 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
+L0000192 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
+L0000256 00000000 00000000 00000000 10000000 00000000 00000000 00000000 00000000*
+L0000320 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
+L0000384 00000000 00000000 00000100 00000000 00001000 00000000 00000000 00000000*
+L0000448 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
+L0000512 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
+L0000576 000000 000000 000000 000000 000000 000000 000000 000000*
+L0000624 000000 000000 000000 000000 000000 000000 000000 000000*
+L0000672 000000 000100 000001 000000 000011 000000 000000 000000*
+L0000720 000000 000000 000000 000000 000000 000000 000000 000000*
+L0000768 000000 000000 000000 000000 000000 000000 000000 000000*
+L0000816 000000 000000 000000 000000 000000 000000 000000 000000*
+L0000864 10000000 00000100 00000000 00000000 00000000 00000100 00000000 00000000*
+L0000928 10010100 10010000 00000100 00000000 00001000 00000100 00000000 00000000*
+L0000992 10010100 10011100 00000100 00000000 00001000 00000100 00000000 00000000*
+L0001056 10000100 10001100 00000000 10000000 00000100 00000100 00000000 00000000*
+L0001120 10000100 10001100 00000000 00000000 00000000 00000000 00000000 00000000*
+L0001184 00000100 10001000 00000000 00000000 00000000 00000000 00000000 00000000*
+L0001248 00001100 10011000 00000000 00000100 00000000 00000100 00000000 00000000*
+L0001312 00000100 10011000 00000000 00000100 00000000 00000100 00000000 00000000*
+L0001376 00000100 10011000 00000100 00000100 00001000 00000100 00000000 00000000*
+L0001440 000001 100010 000000 000000 000000 000001 000000 000000*
+L0001488 000000 100001 000000 000000 000000 000001 000000 000000*
+L0001536 000011 100011 000000 000000 000000 000001 000000 000000*
+L0001584 000011 100011 000000 000000 000000 000001 000000 000000*
+L0001632 000001 000011 000001 000000 000011 000001 000000 000000*
+L0001680 000001 000111 000000 000000 000000 000001 000000 000000*
+L0001728 10000010 00000100 00000000 00000000 00000000 00000000 00000000 00000000*
+L0001792 10100100 10000000 00000000 00000000 00000000 00000100 00000000 00000000*
+L0001856 10010100 10011100 00000100 00000000 00001100 00000100 00000000 00000000*
+L0001920 10000100 10001100 00000000 00000000 00000100 00000100 00000000 00000000*
+L0001984 10000100 10001100 00000000 00000000 00000000 00000000 00000000 00000000*
+L0002048 00000000 10000000 00000000 00000000 00000000 00000000 00000000 00000000*
+L0002112 00001000 10000000 00000000 00000000 00000000 00000000 00000000 00000000*
+L0002176 00000000 10011000 00000100 00000000 00001000 00000000 00000000 00000000*
+L0002240 00000000 10011000 00000100 00000000 00001000 00000000 00000000 00000000*
+L0002304 000001 100010 000000 000000 000000 000001 000000 000000*
+L0002352 000000 100000 000000 000000 000000 000001 000000 000000*
+L0002400 000011 100000 000000 000000 000000 000001 000000 000000*
+L0002448 000011 100100 000001 000000 000011 000001 000000 000000*
+L0002496 000001 000110 000001 000000 000011 000001 000000 000000*
+L0002544 000001 000111 000000 000000 000000 000001 000000 000000*
+L0002592 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
+L0002656 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
+L0002720 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
+L0002784 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
+L0002848 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
+L0002912 00000000 00100000 00000000 00000000 00000000 00000000 00000000 00000000*
+L0002976 00000100 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
+L0003040 00000000 00000000 00000000 00000000 00000000 00000100 00000000 00000000*
+L0003104 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
+L0003168 000000 000000 000000 000000 000000 000000 000000 000000*
+L0003216 000000 001000 000010 000000 000000 000000 000000 000000*
+L0003264 000000 000011 000000 000000 000000 000000 000000 000000*
+L0003312 000000 000000 000000 000000 000000 000000 000000 000000*
+L0003360 000000 000000 000000 000000 000000 000000 000000 000000*
+L0003408 000000 000000 000000 000000 000000 000000 000000 000000*
+L0003456 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
+L0003520 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
+L0003584 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
+L0003648 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
+L0003712 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
+L0003776 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
+L0003840 00000000 00000000 00000000 00000100 00000000 00000000 00000000 00000000*
+L0003904 00000000 00000000 00000000 00000100 00000000 00000000 00000000 00000000*
+L0003968 00000000 00000000 00000000 00000100 00000000 00000000 00000000 00000000*
+L0004032 000000 000000 000000 000000 000000 000000 000000 000000*
+L0004080 000000 000000 000000 000000 000000 000000 000000 000000*
+L0004128 000000 000000 000000 100000 000000 000000 000000 000000*
+L0004176 000000 000000 000000 000000 000000 000000 000000 000000*
+L0004224 000000 000000 000000 000000 000000 000000 000000 000000*
+L0004272 000000 000100 000000 000000 000000 000000 000000 000000*
+L0004320 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
+L0004384 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
+L0004448 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
+L0004512 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
+L0004576 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
+L0004640 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
+L0004704 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
+L0004768 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
+L0004832 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
+L0004896 000000 000000 000000 000000 000000 000000 000000 000000*
+L0004944 000000 000000 000000 000000 000000 000000 000000 000000*
+L0004992 000000 000000 000000 000000 000000 000000 000000 000000*
+L0005040 000000 000000 000000 100000 000000 000000 000000 000000*
+L0005088 000000 000100 000000 000000 000000 000000 000000 000000*
+L0005136 000000 000000 000000 000000 000000 000000 000000 000000*
+L0005184 00000010 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
+L0005248 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
+L0005312 00000011 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
+L0005376 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
+L0005440 00000010 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
+L0005504 00000100 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
+L0005568 00000100 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
+L0005632 00000110 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
+L0005696 00000100 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
+L0005760 000000 000000 000000 000000 000000 000000 000000 000000*
+L0005808 000000 000000 000000 000000 000000 000000 000000 000000*
+L0005856 000000 000000 000000 000000 000000 000000 000000 000000*
+L0005904 000000 000000 000000 000000 000000 000000 000000 000000*
+L0005952 000000 000000 000000 000000 000000 000000 000000 000000*
+L0006000 000000 000000 000000 000000 000000 000000 000000 000000*
+L0006048 00000010 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
+L0006112 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
+L0006176 00000011 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
+L0006240 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
+L0006304 00000010 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
+L0006368 00000010 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
+L0006432 00000011 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
+L0006496 00000011 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
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+CB6CD*
+A17C
diff --git a/Logic/LAN_IDE/LAN_IDE_CP.lfp b/Logic/LAN_IDE/LAN_IDE_CP.lfp
new file mode 100644
index 0000000..e69de29
diff --git a/Logic/LAN_IDE/LAN_IDE_CP.lso b/Logic/LAN_IDE/LAN_IDE_CP.lso
new file mode 100644
index 0000000..b8f99f5
--- /dev/null
+++ b/Logic/LAN_IDE/LAN_IDE_CP.lso
@@ -0,0 +1 @@
+work
diff --git a/Logic/LAN_IDE/LAN_IDE_CP.mfd b/Logic/LAN_IDE/LAN_IDE_CP.mfd
new file mode 100644
index 0000000..32b3f21
--- /dev/null
+++ b/Logic/LAN_IDE/LAN_IDE_CP.mfd
@@ -0,0 +1,1046 @@
+MDF Database:  version 1.0
+MDF_INFO | LAN_IDE_CP | XC95144XL-10-TQ144
+MACROCELL | 1 | 14 | D<13>_BUFR.MC
+ATTRIBUTES | 8520480 | 0
+OUTPUTMC | 1 | 2 | 11
+INPUTS | 17 | RESET  | RW  | AS  | A<5>  | A<1>  | A<6>  | A<3>  | A<2>  | AUTO_CONFIG_DONE<1>  | AUTO_CONFIG_DONE<2>  | autoconfig  | A<4>  | AUTO_CONFIG_DONE<0>  | D<13>  | ide/ide_CLKF  | EXP17_.EXP  | N1$BUF2.EXP
+INPUTMC | 8 | 2 | 14 | 1 | 7 | 3 | 16 | 1 | 8 | 2 | 11 | 3 | 15 | 1 | 13 | 1 | 15
+INPUTP | 9 | 160 | 93 | 90 | 54 | 63 | 57 | 58 | 60 | 56
+IMPORTS | 2 | 1 | 13 | 1 | 15
+EQ | 39 | 
+   !D<13>_BUFR.D = RESET & !D<13> & AS
+	# RESET & !D<13> & !autoconfig
+	# RESET & RW & !AS & !A<5> & A<4> & !A<6> & A<3> & 
+	A<2> & AUTO_CONFIG_DONE<0> & !AUTO_CONFIG_DONE<1> & 
+	autoconfig
+	# RESET & RW & !AS & !A<5> & A<1> & !A<6> & !A<3> & 
+	!A<2> & AUTO_CONFIG_DONE<1> & !AUTO_CONFIG_DONE<2> & 
+	autoconfig
+;Imported pterms FB2_14
+	# RESET & !D<13> & !RW
+	# RESET & !D<13> & AUTO_CONFIG_DONE<0> & 
+	AUTO_CONFIG_DONE<1> & AUTO_CONFIG_DONE<2>
+	# RESET & RW & !AS & !A<5> & !A<4> & !A<6> & !A<3> & 
+	!AUTO_CONFIG_DONE<0> & autoconfig
+	# RESET & RW & !AS & !A<5> & !A<4> & !A<3> & !A<2> & 
+	!AUTO_CONFIG_DONE<0> & autoconfig
+	# RESET & RW & !AS & !A<5> & !A<4> & !A<3> & !A<2> & 
+	!AUTO_CONFIG_DONE<1> & autoconfig
+;Imported pterms FB2_13
+	# RESET & RW & !AS & !A<5> & A<4> & !A<1> & !A<6> & 
+	A<3> & AUTO_CONFIG_DONE<0> & !AUTO_CONFIG_DONE<1> & 
+	autoconfig
+	# RESET & RW & !AS & !A<5> & !A<4> & !A<1> & !A<6> & 
+	!A<3> & AUTO_CONFIG_DONE<1> & !AUTO_CONFIG_DONE<2> & 
+	autoconfig
+	# RESET & RW & !AS & A<5> & !A<4> & !A<1> & !A<6> & 
+	!A<3> & A<2> & AUTO_CONFIG_DONE<0> & !AUTO_CONFIG_DONE<1> & 
+	autoconfig
+;Imported pterms FB2_16
+	# RESET & RW & !AS & !A<5> & !A<4> & !A<3> & !A<2> & 
+	!AUTO_CONFIG_DONE<2> & autoconfig
+	# RESET & RW & !AS & !A<5> & !A<4> & A<1> & !A<6> & 
+	!A<3> & !AUTO_CONFIG_DONE<1> & autoconfig
+	# RESET & RW & !AS & !A<5> & A<1> & !A<6> & !A<3> & 
+	!A<2> & !AUTO_CONFIG_DONE<0> & autoconfig
+	# RESET & RW & !AS & !A<5> & A<4> & !A<1> & !A<6> & 
+	A<2> & AUTO_CONFIG_DONE<0> & !AUTO_CONFIG_DONE<1> & 
+	autoconfig;
+   D<13>_BUFR.CLK = ide/ide_CLKF;
+
+MACROCELL | 0 | 17 | D<12>_BUFR.MC
+ATTRIBUTES | 8520480 | 0
+OUTPUTMC | 1 | 2 | 3
+INPUTS | 17 | RESET  | RW  | AS  | A<5>  | A<4>  | A<1>  | A<3>  | A<2>  | AUTO_CONFIG_DONE<1>  | AUTO_CONFIG_DONE<2>  | autoconfig  | A<6>  | AUTO_CONFIG_DONE<0>  | AUTOBOOT_OFF  | IDE_CS_1_OBUF.EXP  | ide/ide_CLKF  | EXP14_.EXP
+INPUTMC | 7 | 2 | 14 | 1 | 7 | 3 | 16 | 1 | 8 | 0 | 0 | 3 | 15 | 0 | 16
+INPUTP | 10 | 160 | 93 | 90 | 54 | 56 | 63 | 58 | 60 | 57 | 84
+IMPORTS | 2 | 0 | 0 | 0 | 16
+EQ | 43 | 
+   !D<12>_BUFR.D = RESET & RW & !AS & !A<4> & A<1> & !A<6> & !A<3> & 
+	A<2> & !AUTO_CONFIG_DONE<0> & autoconfig
+	# RESET & RW & !AS & !A<5> & A<4> & !A<6> & A<3> & 
+	!A<2> & AUTO_CONFIG_DONE<0> & !AUTO_CONFIG_DONE<1> & 
+	autoconfig
+	# RESET & RW & !AS & !A<5> & !A<4> & !A<1> & !A<3> & 
+	!A<2> & AUTO_CONFIG_DONE<1> & !AUTO_CONFIG_DONE<2> & 
+	autoconfig
+	# RESET & RW & !AS & !A<5> & !A<4> & !A<1> & !A<3> & 
+	!A<2> & !AUTO_CONFIG_DONE<1> & AUTOBOOT_OFF & autoconfig
+;Imported pterms FB1_1
+	# RESET & RW & !AS & !A<5> & !A<4> & A<6> & !A<3> & 
+	!A<2> & !AUTO_CONFIG_DONE<0> & autoconfig
+	# RESET & RW & !AS & !A<5> & !A<4> & A<6> & !A<3> & 
+	!A<2> & !AUTO_CONFIG_DONE<1> & autoconfig
+	# RESET & RW & !AS & !A<5> & !A<4> & A<6> & !A<3> & 
+	!A<2> & !AUTO_CONFIG_DONE<2> & autoconfig
+	# RESET & RW & !AS & !A<5> & !A<1> & !A<6> & !A<3> & 
+	A<2> & !AUTO_CONFIG_DONE<0> & autoconfig
+	# RESET & RW & !AS & A<5> & !A<4> & A<1> & !A<6> & 
+	A<2> & AUTO_CONFIG_DONE<0> & !AUTO_CONFIG_DONE<1> & 
+	autoconfig
+;Imported pterms FB1_17
+	# RESET & !D<12> & !RW
+	# RESET & !D<12> & AS
+	# RESET & !D<12> & !autoconfig
+	# RESET & !D<12> & AUTO_CONFIG_DONE<0> & 
+	AUTO_CONFIG_DONE<1> & AUTO_CONFIG_DONE<2>
+	# RESET & RW & !AS & !A<5> & !A<4> & !A<1> & !A<3> & 
+	!A<2> & !AUTO_CONFIG_DONE<0> & autoconfig
+;Imported pterms FB1_16
+	# RESET & RW & !AS & A<5> & !A<4> & A<1> & !A<6> & 
+	!A<3> & A<2> & !AUTO_CONFIG_DONE<2> & autoconfig
+	# RESET & RW & !AS & A<5> & !A<4> & !A<6> & !A<3> & 
+	A<2> & AUTO_CONFIG_DONE<0> & !AUTO_CONFIG_DONE<1> & 
+	autoconfig
+	# RESET & RW & !AS & !A<5> & A<4> & A<1> & !A<6> & 
+	A<3> & AUTO_CONFIG_DONE<0> & !AUTO_CONFIG_DONE<1> & 
+	autoconfig
+	# RESET & RW & !AS & !A<5> & !A<1> & !A<6> & !A<3> & 
+	A<2> & AUTO_CONFIG_DONE<1> & !AUTO_CONFIG_DONE<2> & 
+	autoconfig;
+   D<12>_BUFR.CLK = ide/ide_CLKF;
+
+MACROCELL | 1 | 0 | D<14>_BUFR.MC
+ATTRIBUTES | 8520480 | 0
+OUTPUTMC | 1 | 2 | 6
+INPUTS | 16 | RESET  | RW  | AS  | A<5>  | A<4>  | A<6>  | A<3>  | A<2>  | AUTO_CONFIG_DONE<0>  | AUTO_CONFIG_DONE<1>  | AUTO_CONFIG_DONE<2>  | autoconfig  | A<1>  | EXP15_.EXP  | ide/ide_CLKF  | EXP18_.EXP
+INPUTMC | 7 | 1 | 8 | 2 | 14 | 1 | 7 | 3 | 16 | 1 | 1 | 3 | 15 | 1 | 17
+INPUTP | 9 | 160 | 93 | 90 | 54 | 56 | 57 | 58 | 60 | 63
+IMPORTS | 2 | 1 | 1 | 1 | 17
+EQ | 40 | 
+   !D<14>_BUFR.D = RESET & RW & !AS & !A<5> & !A<4> & A<1> & !A<3> & 
+	!A<2> & !AUTO_CONFIG_DONE<1> & autoconfig
+	# RESET & RW & !AS & !A<5> & !A<4> & A<1> & !A<3> & 
+	!A<2> & !AUTO_CONFIG_DONE<2> & autoconfig
+	# RESET & RW & !AS & !A<5> & A<1> & !A<6> & !A<3> & 
+	A<2> & AUTO_CONFIG_DONE<0> & !AUTO_CONFIG_DONE<1> & 
+	autoconfig
+	# RESET & RW & !AS & !A<5> & !A<4> & !A<6> & !A<3> & 
+	A<2> & AUTO_CONFIG_DONE<0> & AUTO_CONFIG_DONE<1> & 
+	!AUTO_CONFIG_DONE<2> & autoconfig
+;Imported pterms FB2_2
+	# RESET & RW & !AS & !A<5> & !A<4> & A<1> & !A<3> & 
+	!A<2> & !AUTO_CONFIG_DONE<0> & autoconfig
+	# RESET & RW & !AS & !A<5> & !A<4> & A<6> & !A<3> & 
+	!A<2> & !AUTO_CONFIG_DONE<0> & autoconfig
+	# RESET & RW & !AS & !A<5> & !A<4> & A<6> & !A<3> & 
+	!A<2> & !AUTO_CONFIG_DONE<1> & autoconfig
+	# RESET & RW & !AS & !A<5> & !A<4> & A<6> & !A<3> & 
+	!A<2> & !AUTO_CONFIG_DONE<2> & autoconfig
+	# RESET & RW & !AS & !A<4> & A<1> & !A<6> & !A<3> & 
+	A<2> & AUTO_CONFIG_DONE<0> & !AUTO_CONFIG_DONE<1> & 
+	autoconfig
+;Imported pterms FB2_3
+	# RESET & RW & !AS & !A<5> & A<4> & A<1> & !A<6> & 
+	!A<3> & A<2> & !AUTO_CONFIG_DONE<0> & autoconfig
+	# RESET & RW & !AS & !A<5> & !A<4> & !A<1> & !A<6> & 
+	!A<3> & A<2> & !AUTO_CONFIG_DONE<0> & autoconfig
+	# RESET & RW & !AS & !A<5> & A<4> & !A<1> & !A<6> & 
+	A<3> & A<2> & AUTO_CONFIG_DONE<0> & !AUTO_CONFIG_DONE<1> & 
+	autoconfig
+;Imported pterms FB2_18
+	# RESET & !D<14> & !RW
+	# RESET & !D<14> & AS
+	# RESET & !D<14> & !autoconfig
+	# RESET & !D<14> & AUTO_CONFIG_DONE<0> & 
+	AUTO_CONFIG_DONE<1> & AUTO_CONFIG_DONE<2>
+	# RESET & RW & !AS & !A<5> & A<1> & !A<6> & !A<3> & 
+	A<2> & AUTO_CONFIG_DONE<0> & !AUTO_CONFIG_DONE<2> & 
+	autoconfig;
+   D<14>_BUFR.CLK = ide/ide_CLKF;
+
+MACROCELL | 5 | 16 | D<15>_BUFR.MC
+ATTRIBUTES | 8520480 | 0
+OUTPUTMC | 1 | 2 | 9
+INPUTS | 14 | RESET  | RW  | AS  | A<5>  | A<1>  | A<6>  | A<3>  | A<2>  | AUTO_CONFIG_DONE<1>  | autoconfig  | D<15>  | EXP22_.EXP  | EXP23_.EXP  | ide/ide_CLKF
+INPUTMC | 6 | 2 | 14 | 3 | 16 | 2 | 9 | 5 | 15 | 5 | 17 | 3 | 15
+INPUTP | 8 | 160 | 93 | 90 | 54 | 63 | 57 | 58 | 60
+IMPORTS | 2 | 5 | 15 | 5 | 17
+EQ | 29 | 
+   !D<15>_BUFR.D = RESET & !D<15> & !RW
+	# RESET & !D<15> & AS
+	# RESET & !D<15> & !autoconfig
+	# RESET & RW & !AS & !A<5> & A<1> & !A<6> & !A<3> & 
+	!A<2> & !AUTO_CONFIG_DONE<1> & autoconfig
+;Imported pterms FB6_16
+	# RESET & !D<15> & AUTO_CONFIG_DONE<0> & 
+	AUTO_CONFIG_DONE<1> & AUTO_CONFIG_DONE<2>
+	# RESET & RW & !AS & !A<5> & A<1> & !A<6> & !A<3> & 
+	!AUTO_CONFIG_DONE<0> & autoconfig
+	# RESET & RW & !AS & !A<5> & !A<4> & A<6> & !A<3> & 
+	!A<2> & !AUTO_CONFIG_DONE<0> & autoconfig
+	# RESET & RW & !AS & !A<5> & !A<4> & A<6> & !A<3> & 
+	!A<2> & !AUTO_CONFIG_DONE<1> & autoconfig
+;Imported pterms FB6_18
+	# RESET & RW & !AS & !A<5> & !A<4> & A<6> & !A<3> & 
+	!A<2> & !AUTO_CONFIG_DONE<2> & autoconfig
+	# RESET & RW & !AS & !A<5> & A<1> & !A<6> & !A<3> & 
+	AUTO_CONFIG_DONE<1> & !AUTO_CONFIG_DONE<2> & autoconfig
+	# RESET & RW & !AS & !A<5> & A<4> & A<1> & !A<6> & 
+	A<2> & AUTO_CONFIG_DONE<0> & !AUTO_CONFIG_DONE<1> & 
+	autoconfig
+	# RESET & RW & !AS & A<5> & !A<4> & !A<1> & !A<6> & 
+	!A<3> & A<2> & AUTO_CONFIG_DONE<0> & !AUTO_CONFIG_DONE<1> & 
+	autoconfig
+	# RESET & RW & !AS & !A<5> & A<4> & !A<1> & !A<6> & 
+	A<3> & !A<2> & AUTO_CONFIG_DONE<0> & !AUTO_CONFIG_DONE<1> & 
+	autoconfig;
+   D<15>_BUFR.CLK = ide/ide_CLKF;
+
+MACROCELL | 1 | 8 | AUTO_CONFIG_DONE<0>
+ATTRIBUTES | 8528672 | 0
+OUTPUTMC | 26 | 1 | 14 | 0 | 17 | 1 | 0 | 5 | 15 | 1 | 10 | 2 | 15 | 1 | 9 | 4 | 17 | 4 | 14 | 4 | 13 | 4 | 15 | 2 | 17 | 2 | 16 | 1 | 2 | 1 | 11 | 4 | 12 | 3 | 16 | 0 | 0 | 0 | 15 | 0 | 16 | 1 | 1 | 1 | 12 | 1 | 13 | 1 | 15 | 1 | 17 | 5 | 17
+INPUTS | 2 | AUTO_CONFIG_DONE_CYCLE<0>  | AS
+INPUTMC | 1 | 1 | 10
+INPUTP | 1 | 90
+EQ | 3 | 
+   AUTO_CONFIG_DONE<0>.D = AUTO_CONFIG_DONE_CYCLE<0>;
+   AUTO_CONFIG_DONE<0>.CLK = AS;
+   !AUTO_CONFIG_DONE<0>.AR = RESET;	// GSR
+GLOBALS | 1 | 4 | RESET
+
+MACROCELL | 2 | 14 | AUTO_CONFIG_DONE<1>
+ATTRIBUTES | 8528672 | 0
+OUTPUTMC | 27 | 1 | 14 | 0 | 17 | 1 | 0 | 5 | 16 | 2 | 15 | 1 | 9 | 4 | 17 | 4 | 14 | 4 | 13 | 4 | 15 | 2 | 17 | 2 | 16 | 1 | 10 | 1 | 11 | 4 | 12 | 3 | 16 | 0 | 0 | 0 | 15 | 0 | 16 | 1 | 1 | 1 | 2 | 1 | 12 | 1 | 13 | 1 | 15 | 1 | 17 | 5 | 15 | 5 | 17
+INPUTS | 2 | AUTO_CONFIG_DONE_CYCLE<1>  | AS
+INPUTMC | 1 | 2 | 15
+INPUTP | 1 | 90
+EQ | 3 | 
+   AUTO_CONFIG_DONE<1>.D = AUTO_CONFIG_DONE_CYCLE<1>;
+   AUTO_CONFIG_DONE<1>.CLK = AS;
+   !AUTO_CONFIG_DONE<1>.AR = RESET;	// GSR
+GLOBALS | 1 | 4 | RESET
+
+MACROCELL | 1 | 7 | AUTO_CONFIG_DONE<2>
+ATTRIBUTES | 8528672 | 0
+OUTPUTMC | 15 | 1 | 14 | 0 | 17 | 1 | 0 | 5 | 15 | 1 | 9 | 3 | 16 | 0 | 0 | 0 | 15 | 0 | 16 | 1 | 1 | 1 | 12 | 1 | 13 | 1 | 15 | 1 | 17 | 5 | 17
+INPUTS | 2 | AUTO_CONFIG_DONE_CYCLE<2>  | AS
+INPUTMC | 1 | 1 | 9
+INPUTP | 1 | 90
+EQ | 3 | 
+   AUTO_CONFIG_DONE<2>.D = AUTO_CONFIG_DONE_CYCLE<2>;
+   AUTO_CONFIG_DONE<2>.CLK = AS;
+   !AUTO_CONFIG_DONE<2>.AR = RESET;	// GSR
+GLOBALS | 1 | 4 | RESET
+
+MACROCELL | 1 | 10 | AUTO_CONFIG_DONE_CYCLE<0>
+ATTRIBUTES | 8520480 | 0
+OUTPUTMC | 3 | 1 | 8 | 1 | 10 | 1 | 11
+INPUTS | 17 | RESET  | AUTO_CONFIG_DONE_CYCLE<0>  | UDS  | RW  | AS  | A<5>  | A<4>  | A<1>  | A<6>  | A<3>  | AUTO_CONFIG_DONE<0>  | autoconfig  | ide/ide_CLKF  | A<2>  | AUTO_CONFIG_DONE<1>  | IDE_BASEADR<7>  | D<15>.PIN
+INPUTMC | 6 | 1 | 10 | 1 | 8 | 3 | 16 | 3 | 15 | 2 | 14 | 1 | 11
+INPUTP | 11 | 160 | 91 | 93 | 90 | 54 | 56 | 63 | 57 | 58 | 60 | 52
+EXPORTS | 1 | 1 | 11
+EQ | 7 | 
+   AUTO_CONFIG_DONE_CYCLE<0>.D = RESET & AUTO_CONFIG_DONE_CYCLE<0>
+	# RESET & !UDS & !RW & !AS & !A<5> & !A<4> & !A<1> & 
+	A<6> & A<3> & !AUTO_CONFIG_DONE<0> & autoconfig;
+   AUTO_CONFIG_DONE_CYCLE<0>.CLK = ide/ide_CLKF;
+    AUTO_CONFIG_DONE_CYCLE<0>.EXP  =  RESET & !UDS & !RW & !AS & !A<5> & !A<4> & !A<1> & 
+	A<6> & A<3> & !A<2> & AUTO_CONFIG_DONE<0> & 
+	!AUTO_CONFIG_DONE<1> & IDE_BASEADR<7> & autoconfig & !D<15>.PIN
+
+MACROCELL | 2 | 15 | AUTO_CONFIG_DONE_CYCLE<1>
+ATTRIBUTES | 8520480 | 0
+OUTPUTMC | 2 | 2 | 14 | 2 | 15
+INPUTS | 14 | RESET  | AUTO_CONFIG_DONE_CYCLE<1>  | UDS  | RW  | AS  | A<5>  | A<4>  | A<1>  | A<6>  | A<3>  | AUTO_CONFIG_DONE<0>  | AUTO_CONFIG_DONE<1>  | autoconfig  | ide/ide_CLKF
+INPUTMC | 5 | 2 | 15 | 1 | 8 | 2 | 14 | 3 | 16 | 3 | 15
+INPUTP | 9 | 160 | 91 | 93 | 90 | 54 | 56 | 63 | 57 | 58
+EQ | 5 | 
+   AUTO_CONFIG_DONE_CYCLE<1>.D = RESET & AUTO_CONFIG_DONE_CYCLE<1>
+	# RESET & !UDS & !RW & !AS & !A<5> & !A<4> & !A<1> & 
+	A<6> & A<3> & AUTO_CONFIG_DONE<0> & !AUTO_CONFIG_DONE<1> & 
+	autoconfig;
+   AUTO_CONFIG_DONE_CYCLE<1>.CLK = ide/ide_CLKF;
+
+MACROCELL | 1 | 9 | AUTO_CONFIG_DONE_CYCLE<2>
+ATTRIBUTES | 8520480 | 0
+OUTPUTMC | 2 | 1 | 7 | 1 | 9
+INPUTS | 15 | RESET  | AUTO_CONFIG_DONE_CYCLE<2>  | UDS  | RW  | AS  | A<5>  | A<4>  | A<1>  | A<6>  | A<3>  | AUTO_CONFIG_DONE<0>  | AUTO_CONFIG_DONE<1>  | AUTO_CONFIG_DONE<2>  | autoconfig  | ide/ide_CLKF
+INPUTMC | 6 | 1 | 9 | 1 | 8 | 2 | 14 | 1 | 7 | 3 | 16 | 3 | 15
+INPUTP | 9 | 160 | 91 | 93 | 90 | 54 | 56 | 63 | 57 | 58
+EQ | 5 | 
+   AUTO_CONFIG_DONE_CYCLE<2>.D = RESET & AUTO_CONFIG_DONE_CYCLE<2>
+	# RESET & !UDS & !RW & !AS & !A<5> & !A<4> & !A<1> & 
+	A<6> & A<3> & AUTO_CONFIG_DONE<0> & AUTO_CONFIG_DONE<1> & 
+	!AUTO_CONFIG_DONE<2> & autoconfig;
+   AUTO_CONFIG_DONE_CYCLE<2>.CLK = ide/ide_CLKF;
+
+MACROCELL | 4 | 17 | IDE_BASEADR<0>
+ATTRIBUTES | 4326176 | 0
+OUTPUTMC | 2 | 4 | 17 | 3 | 17
+INPUTS | 16 | RESET  | IDE_BASEADR<0>  | UDS  | RW  | AS  | A<5>  | A<4>  | A<1>  | A<6>  | A<3>  | A<2>  | AUTO_CONFIG_DONE<0>  | AUTO_CONFIG_DONE<1>  | autoconfig  | D<8>.PIN  | ide/ide_CLKF
+INPUTMC | 5 | 4 | 17 | 1 | 8 | 2 | 14 | 3 | 16 | 3 | 15
+INPUTP | 11 | 160 | 91 | 93 | 90 | 54 | 56 | 63 | 57 | 58 | 60 | 21
+EQ | 8 | 
+   IDE_BASEADR<0>.T = !RESET & !IDE_BASEADR<0>
+	# !UDS & !RW & !AS & !A<5> & !A<4> & !A<1> & A<6> & 
+	A<3> & !A<2> & AUTO_CONFIG_DONE<0> & !AUTO_CONFIG_DONE<1> & 
+	!IDE_BASEADR<0> & autoconfig & D<8>.PIN
+	# RESET & !UDS & !RW & !AS & !A<5> & !A<4> & !A<1> & 
+	A<6> & A<3> & !A<2> & AUTO_CONFIG_DONE<0> & 
+	!AUTO_CONFIG_DONE<1> & IDE_BASEADR<0> & autoconfig & !D<8>.PIN;
+   IDE_BASEADR<0>.CLK = ide/ide_CLKF;
+
+MACROCELL | 4 | 14 | IDE_BASEADR<4>
+ATTRIBUTES | 4326176 | 0
+OUTPUTMC | 2 | 4 | 14 | 3 | 2
+INPUTS | 16 | RESET  | IDE_BASEADR<4>  | UDS  | RW  | AS  | A<5>  | A<4>  | A<1>  | A<6>  | A<3>  | A<2>  | AUTO_CONFIG_DONE<0>  | AUTO_CONFIG_DONE<1>  | autoconfig  | D<12>.PIN  | ide/ide_CLKF
+INPUTMC | 5 | 4 | 14 | 1 | 8 | 2 | 14 | 3 | 16 | 3 | 15
+INPUTP | 11 | 160 | 91 | 93 | 90 | 54 | 56 | 63 | 57 | 58 | 60 | 48
+EQ | 8 | 
+   IDE_BASEADR<4>.T = !RESET & !IDE_BASEADR<4>
+	# !UDS & !RW & !AS & !A<5> & !A<4> & !A<1> & A<6> & 
+	A<3> & !A<2> & AUTO_CONFIG_DONE<0> & !AUTO_CONFIG_DONE<1> & 
+	!IDE_BASEADR<4> & autoconfig & D<12>.PIN
+	# RESET & !UDS & !RW & !AS & !A<5> & !A<4> & !A<1> & 
+	A<6> & A<3> & !A<2> & AUTO_CONFIG_DONE<0> & 
+	!AUTO_CONFIG_DONE<1> & IDE_BASEADR<4> & autoconfig & !D<12>.PIN;
+   IDE_BASEADR<4>.CLK = ide/ide_CLKF;
+
+MACROCELL | 4 | 13 | IDE_BASEADR<5>
+ATTRIBUTES | 4326176 | 0
+OUTPUTMC | 3 | 4 | 13 | 3 | 2 | 3 | 16
+INPUTS | 16 | RESET  | IDE_BASEADR<5>  | UDS  | RW  | AS  | A<5>  | A<4>  | A<1>  | A<6>  | A<3>  | A<2>  | AUTO_CONFIG_DONE<0>  | AUTO_CONFIG_DONE<1>  | autoconfig  | D<13>.PIN  | ide/ide_CLKF
+INPUTMC | 5 | 4 | 13 | 1 | 8 | 2 | 14 | 3 | 16 | 3 | 15
+INPUTP | 11 | 160 | 91 | 93 | 90 | 54 | 56 | 63 | 57 | 58 | 60 | 49
+EQ | 8 | 
+   IDE_BASEADR<5>.T = !RESET & !IDE_BASEADR<5>
+	# !UDS & !RW & !AS & !A<5> & !A<4> & !A<1> & A<6> & 
+	A<3> & !A<2> & AUTO_CONFIG_DONE<0> & !AUTO_CONFIG_DONE<1> & 
+	!IDE_BASEADR<5> & autoconfig & D<13>.PIN
+	# RESET & !UDS & !RW & !AS & !A<5> & !A<4> & !A<1> & 
+	A<6> & A<3> & !A<2> & AUTO_CONFIG_DONE<0> & 
+	!AUTO_CONFIG_DONE<1> & IDE_BASEADR<5> & autoconfig & !D<13>.PIN;
+   IDE_BASEADR<5>.CLK = ide/ide_CLKF;
+
+MACROCELL | 0 | 9 | IDE_ENABLE
+ATTRIBUTES | 8520480 | 0
+OUTPUTMC | 3 | 0 | 9 | 0 | 13 | 0 | 14
+INPUTS | 6 | RESET  | IDE_ENABLE  | RW  | AS  | ide  | ide/ide_CLKF
+INPUTMC | 3 | 0 | 9 | 3 | 0 | 3 | 15
+INPUTP | 3 | 160 | 93 | 90
+EQ | 3 | 
+   !IDE_ENABLE.D = RESET & !IDE_ENABLE
+	# RESET & !RW & !AS & ide;
+   IDE_ENABLE.CLK = ide/ide_CLKF;
+
+MACROCELL | 4 | 15 | IDE_BASEADR<1>
+ATTRIBUTES | 4326176 | 0
+OUTPUTMC | 3 | 4 | 15 | 3 | 1 | 3 | 17
+INPUTS | 16 | RESET  | IDE_BASEADR<1>  | UDS  | RW  | AS  | A<5>  | A<4>  | A<1>  | A<6>  | A<3>  | A<2>  | AUTO_CONFIG_DONE<0>  | AUTO_CONFIG_DONE<1>  | autoconfig  | D<9>.PIN  | ide/ide_CLKF
+INPUTMC | 5 | 4 | 15 | 1 | 8 | 2 | 14 | 3 | 16 | 3 | 15
+INPUTP | 11 | 160 | 91 | 93 | 90 | 54 | 56 | 63 | 57 | 58 | 60 | 44
+EQ | 8 | 
+   IDE_BASEADR<1>.T = !RESET & !IDE_BASEADR<1>
+	# !UDS & !RW & !AS & !A<5> & !A<4> & !A<1> & A<6> & 
+	A<3> & !A<2> & AUTO_CONFIG_DONE<0> & !AUTO_CONFIG_DONE<1> & 
+	!IDE_BASEADR<1> & autoconfig & D<9>.PIN
+	# RESET & !UDS & !RW & !AS & !A<5> & !A<4> & !A<1> & 
+	A<6> & A<3> & !A<2> & AUTO_CONFIG_DONE<0> & 
+	!AUTO_CONFIG_DONE<1> & IDE_BASEADR<1> & autoconfig & !D<9>.PIN;
+   IDE_BASEADR<1>.CLK = ide/ide_CLKF;
+
+MACROCELL | 2 | 17 | IDE_BASEADR<2>
+ATTRIBUTES | 4326176 | 0
+OUTPUTMC | 2 | 2 | 17 | 3 | 17
+INPUTS | 16 | RESET  | IDE_BASEADR<2>  | UDS  | RW  | AS  | A<5>  | A<4>  | A<1>  | A<6>  | A<3>  | A<2>  | AUTO_CONFIG_DONE<0>  | AUTO_CONFIG_DONE<1>  | autoconfig  | D<10>.PIN  | ide/ide_CLKF
+INPUTMC | 5 | 2 | 17 | 1 | 8 | 2 | 14 | 3 | 16 | 3 | 15
+INPUTP | 11 | 160 | 91 | 93 | 90 | 54 | 56 | 63 | 57 | 58 | 60 | 45
+EQ | 8 | 
+   IDE_BASEADR<2>.T = !RESET & !IDE_BASEADR<2>
+	# !UDS & !RW & !AS & !A<5> & !A<4> & !A<1> & A<6> & 
+	A<3> & !A<2> & AUTO_CONFIG_DONE<0> & !AUTO_CONFIG_DONE<1> & 
+	!IDE_BASEADR<2> & autoconfig & D<10>.PIN
+	# RESET & !UDS & !RW & !AS & !A<5> & !A<4> & !A<1> & 
+	A<6> & A<3> & !A<2> & AUTO_CONFIG_DONE<0> & 
+	!AUTO_CONFIG_DONE<1> & IDE_BASEADR<2> & autoconfig & !D<10>.PIN;
+   IDE_BASEADR<2>.CLK = ide/ide_CLKF;
+
+MACROCELL | 2 | 16 | IDE_BASEADR<3>
+ATTRIBUTES | 4326176 | 0
+OUTPUTMC | 2 | 2 | 16 | 3 | 0
+INPUTS | 16 | RESET  | IDE_BASEADR<3>  | UDS  | RW  | AS  | A<5>  | A<4>  | A<1>  | A<6>  | A<3>  | A<2>  | AUTO_CONFIG_DONE<0>  | AUTO_CONFIG_DONE<1>  | autoconfig  | D<11>.PIN  | ide/ide_CLKF
+INPUTMC | 5 | 2 | 16 | 1 | 8 | 2 | 14 | 3 | 16 | 3 | 15
+INPUTP | 11 | 160 | 91 | 93 | 90 | 54 | 56 | 63 | 57 | 58 | 60 | 47
+EQ | 8 | 
+   IDE_BASEADR<3>.T = !RESET & !IDE_BASEADR<3>
+	# !UDS & !RW & !AS & !A<5> & !A<4> & !A<1> & A<6> & 
+	A<3> & !A<2> & AUTO_CONFIG_DONE<0> & !AUTO_CONFIG_DONE<1> & 
+	!IDE_BASEADR<3> & autoconfig & D<11>.PIN
+	# RESET & !UDS & !RW & !AS & !A<5> & !A<4> & !A<1> & 
+	A<6> & A<3> & !A<2> & AUTO_CONFIG_DONE<0> & 
+	!AUTO_CONFIG_DONE<1> & IDE_BASEADR<3> & autoconfig & !D<11>.PIN;
+   IDE_BASEADR<3>.CLK = ide/ide_CLKF;
+
+MACROCELL | 1 | 12 | IDE_BASEADR<6>
+ATTRIBUTES | 4326176 | 0
+OUTPUTMC | 4 | 1 | 12 | 1 | 11 | 3 | 1 | 1 | 13
+INPUTS | 16 | RESET  | IDE_BASEADR<6>  | RW  | AS  | A<5>  | A<4>  | A<1>  | A<6>  | A<3>  | AUTO_CONFIG_DONE<0>  | AUTO_CONFIG_DONE<1>  | autoconfig  | AUTO_CONFIG_DONE<2>  | A<2>  | IDE_BASEADR<7>.EXP  | ide/ide_CLKF
+INPUTMC | 7 | 1 | 12 | 1 | 8 | 2 | 14 | 3 | 16 | 1 | 7 | 1 | 11 | 3 | 15
+INPUTP | 9 | 160 | 93 | 90 | 54 | 56 | 63 | 57 | 58 | 60
+EXPORTS | 1 | 1 | 13
+IMPORTS | 1 | 1 | 11
+EQ | 18 | 
+   IDE_BASEADR<6>.T = !RESET & !IDE_BASEADR<6>
+;Imported pterms FB2_12
+	# !UDS & !RW & !AS & !A<5> & !A<4> & !A<1> & A<6> & 
+	A<3> & !A<2> & AUTO_CONFIG_DONE<0> & !AUTO_CONFIG_DONE<1> & 
+	!IDE_BASEADR<6> & autoconfig & D<14>.PIN
+	# RESET & !UDS & !RW & !AS & !A<5> & !A<4> & !A<1> & 
+	A<6> & A<3> & !A<2> & AUTO_CONFIG_DONE<0> & 
+	!AUTO_CONFIG_DONE<1> & IDE_BASEADR<6> & autoconfig & !D<14>.PIN;
+   IDE_BASEADR<6>.CLK = ide/ide_CLKF;
+    IDE_BASEADR<6>.EXP  =  RESET & RW & !AS & !A<5> & A<4> & !A<1> & !A<6> & 
+	A<3> & AUTO_CONFIG_DONE<0> & !AUTO_CONFIG_DONE<1> & 
+	autoconfig
+	# RESET & RW & !AS & !A<5> & !A<4> & !A<1> & !A<6> & 
+	!A<3> & AUTO_CONFIG_DONE<1> & !AUTO_CONFIG_DONE<2> & 
+	autoconfig
+	# RESET & RW & !AS & A<5> & !A<4> & !A<1> & !A<6> & 
+	!A<3> & A<2> & AUTO_CONFIG_DONE<0> & !AUTO_CONFIG_DONE<1> & 
+	autoconfig
+
+MACROCELL | 1 | 11 | IDE_BASEADR<7>
+ATTRIBUTES | 4326176 | 0
+OUTPUTMC | 4 | 1 | 11 | 1 | 10 | 3 | 1 | 1 | 12
+INPUTS | 19 | RESET  | IDE_BASEADR<7>  | UDS  | RW  | AS  | A<5>  | A<4>  | A<1>  | A<6>  | A<3>  | A<2>  | AUTO_CONFIG_DONE<0>  | AUTO_CONFIG_DONE<1>  | autoconfig  | D<15>.PIN  | ide/ide_CLKF  | IDE_BASEADR<6>  | D<14>.PIN  | AUTO_CONFIG_DONE_CYCLE<0>.EXP
+INPUTMC | 7 | 1 | 11 | 1 | 8 | 2 | 14 | 3 | 16 | 3 | 15 | 1 | 12 | 1 | 10
+INPUTP | 12 | 160 | 91 | 93 | 90 | 54 | 56 | 63 | 57 | 58 | 60 | 52 | 50
+EXPORTS | 1 | 1 | 12
+IMPORTS | 1 | 1 | 10
+EQ | 15 | 
+   IDE_BASEADR<7>.T = !RESET & !IDE_BASEADR<7>
+	# !UDS & !RW & !AS & !A<5> & !A<4> & !A<1> & A<6> & 
+	A<3> & !A<2> & AUTO_CONFIG_DONE<0> & !AUTO_CONFIG_DONE<1> & 
+	!IDE_BASEADR<7> & autoconfig & D<15>.PIN
+;Imported pterms FB2_11
+	# RESET & !UDS & !RW & !AS & !A<5> & !A<4> & !A<1> & 
+	A<6> & A<3> & !A<2> & AUTO_CONFIG_DONE<0> & 
+	!AUTO_CONFIG_DONE<1> & IDE_BASEADR<7> & autoconfig & !D<15>.PIN;
+   IDE_BASEADR<7>.CLK = ide/ide_CLKF;
+    IDE_BASEADR<7>.EXP  =  !UDS & !RW & !AS & !A<5> & !A<4> & !A<1> & A<6> & 
+	A<3> & !A<2> & AUTO_CONFIG_DONE<0> & !AUTO_CONFIG_DONE<1> & 
+	!IDE_BASEADR<6> & autoconfig & D<14>.PIN
+	# RESET & !UDS & !RW & !AS & !A<5> & !A<4> & !A<1> & 
+	A<6> & A<3> & !A<2> & AUTO_CONFIG_DONE<0> & 
+	!AUTO_CONFIG_DONE<1> & IDE_BASEADR<6> & autoconfig & !D<14>.PIN
+
+MACROCELL | 4 | 12 | SHUT_UP<1>
+ATTRIBUTES | 8520480 | 0
+OUTPUTMC | 2 | 4 | 12 | 3 | 0
+INPUTS | 15 | RESET  | SHUT_UP<1>  | UDS  | RW  | AS  | A<5>  | A<4>  | A<1>  | A<6>  | A<3>  | A<2>  | AUTO_CONFIG_DONE<0>  | AUTO_CONFIG_DONE<1>  | autoconfig  | ide/ide_CLKF
+INPUTMC | 5 | 4 | 12 | 1 | 8 | 2 | 14 | 3 | 16 | 3 | 15
+INPUTP | 10 | 160 | 91 | 93 | 90 | 54 | 56 | 63 | 57 | 58 | 60
+EQ | 5 | 
+   !SHUT_UP<1>.D = RESET & !SHUT_UP<1>
+	# RESET & !UDS & !RW & !AS & !A<5> & !A<4> & !A<1> & 
+	A<6> & A<3> & !A<2> & AUTO_CONFIG_DONE<0> & 
+	!AUTO_CONFIG_DONE<1> & autoconfig;
+   SHUT_UP<1>.CLK = ide/ide_CLKF;
+
+MACROCELL | 3 | 16 | autoconfig
+ATTRIBUTES | 8520480 | 0
+OUTPUTMC | 28 | 1 | 14 | 0 | 17 | 1 | 0 | 5 | 16 | 1 | 10 | 2 | 15 | 1 | 9 | 4 | 17 | 4 | 14 | 4 | 13 | 4 | 15 | 2 | 17 | 2 | 16 | 1 | 2 | 1 | 11 | 4 | 12 | 0 | 6 | 0 | 0 | 0 | 15 | 0 | 16 | 1 | 1 | 1 | 12 | 1 | 13 | 1 | 15 | 1 | 17 | 5 | 15 | 5 | 17 | 3 | 17
+INPUTS | 14 | A<23>  | A<22>  | A<21>  | A<19>  | AUTO_CONFIG_DONE<0>  | BERR  | A<17>  | A<16>  | A<20>  | A<18>  | AUTO_CONFIG_DONE<1>  | AUTO_CONFIG_DONE<2>  | ide/ide_CLKF  | IDE_BASEADR<5>
+INPUTMC | 5 | 1 | 8 | 2 | 14 | 1 | 7 | 3 | 15 | 4 | 13
+INPUTP | 9 | 96 | 97 | 98 | 103 | 109 | 106 | 108 | 102 | 105
+EXPORTS | 1 | 3 | 17
+EQ | 8 | 
+   autoconfig.D = A<23> & A<22> & A<21> & A<19> & 
+	!AUTO_CONFIG_DONE<0> & BERR & !A<17> & !A<16> & !A<20> & !A<18>
+	# A<23> & A<22> & A<21> & A<19> & 
+	!AUTO_CONFIG_DONE<1> & BERR & !A<17> & !A<16> & !A<20> & !A<18>
+	# A<23> & A<22> & A<21> & A<19> & 
+	!AUTO_CONFIG_DONE<2> & BERR & !A<17> & !A<16> & !A<20> & !A<18>;
+   autoconfig.CLK = ide/ide_CLKF;
+    autoconfig.EXP  =  A<21> & !IDE_BASEADR<5>
+
+MACROCELL | 3 | 0 | ide
+ATTRIBUTES | 8520480 | 0
+OUTPUTMC | 3 | 0 | 9 | 0 | 13 | 0 | 14
+INPUTS | 7 | BERR  | SHUT_UP<1>  | A<19>  | IDE_BASEADR<3>  | EXP19_.EXP  | EXP21_.EXP  | ide/ide_CLKF
+INPUTMC | 5 | 4 | 12 | 2 | 16 | 3 | 1 | 3 | 17 | 3 | 15
+INPUTP | 2 | 109 | 103
+IMPORTS | 2 | 3 | 1 | 3 | 17
+EQ | 23 | 
+   !ide.D = SHUT_UP<1>
+	# !BERR
+	# A<19> & !IDE_BASEADR<3>
+	# !A<19> & IDE_BASEADR<3>
+;Imported pterms FB4_2
+	# A<23> & !IDE_BASEADR<7>
+	# !A<23> & IDE_BASEADR<7>
+	# A<22> & !IDE_BASEADR<6>
+	# !A<22> & IDE_BASEADR<6>
+	# IDE_BASEADR<1> & !A<17>
+;Imported pterms FB4_3
+	# !A<21> & IDE_BASEADR<5>
+	# IDE_BASEADR<4> & !A<20>
+	# !IDE_BASEADR<4> & A<20>
+;Imported pterms FB4_18
+	# IDE_BASEADR<0> & !A<16>
+	# !IDE_BASEADR<0> & A<16>
+	# !IDE_BASEADR<1> & A<17>
+	# IDE_BASEADR<2> & !A<18>
+	# !IDE_BASEADR<2> & A<18>
+;Imported pterms FB4_17
+	# A<21> & !IDE_BASEADR<5>;
+   ide.CLK = ide/ide_CLKF;
+
+MACROCELL | 0 | 6 | AUTOCONFIG_IN_PROGRESS
+ATTRIBUTES | 8520480 | 0
+OUTPUTMC | 16 | 2 | 11 | 2 | 3 | 2 | 6 | 2 | 9 | 2 | 8 | 0 | 4 | 0 | 1 | 1 | 4 | 1 | 15 | 0 | 5 | 0 | 7 | 1 | 16 | 2 | 0 | 0 | 2 | 2 | 10 | 2 | 2
+INPUTS | 3 | AS  | autoconfig  | ide/ide_CLKF
+INPUTMC | 2 | 3 | 16 | 3 | 15
+INPUTP | 1 | 90
+EQ | 2 | 
+   AUTOCONFIG_IN_PROGRESS.D = !AS & autoconfig;
+   AUTOCONFIG_IN_PROGRESS.CLK = ide/ide_CLKF;
+
+MACROCELL | 0 | 13 | IDE_R_S
+ATTRIBUTES | 8651558 | 0
+INPUTS | 6 | RESET  | RW  | AS  | IDE_ENABLE  | ide  | ide/ide_CLKF
+INPUTMC | 3 | 0 | 9 | 3 | 0 | 3 | 15
+INPUTP | 3 | 160 | 93 | 90
+EQ | 2 | 
+   !IDE_R.D = RESET & RW & !AS & !IDE_ENABLE & ide;
+   IDE_R.CLK = ide/ide_CLKF;
+
+MACROCELL | 0 | 14 | IDE_W_S
+ATTRIBUTES | 8651558 | 0
+OUTPUTMC | 1 | 0 | 15
+INPUTS | 6 | RESET  | RW  | AS  | ide  | ide/ide_CLKF  | IDE_ENABLE
+INPUTMC | 3 | 3 | 0 | 3 | 15 | 0 | 9
+INPUTP | 3 | 160 | 93 | 90
+EXPORTS | 1 | 0 | 15
+EQ | 3 | 
+   !IDE_W.D = RESET & !RW & !AS & ide;
+   IDE_W.CLK = ide/ide_CLKF;
+    IDE_W_S.EXP  =  RESET & RW & !AS & IDE_ENABLE & ide
+
+MACROCELL | 0 | 15 | ROM_OE_S
+ATTRIBUTES | 8651558 | 0
+OUTPUTMC | 1 | 0 | 16
+INPUTS | 15 | RESET  | RW  | AS  | A<5>  | A<4>  | ide/ide_CLKF  | A<1>  | A<6>  | A<3>  | A<2>  | AUTO_CONFIG_DONE<2>  | autoconfig  | AUTO_CONFIG_DONE<0>  | AUTO_CONFIG_DONE<1>  | IDE_W_S.EXP
+INPUTMC | 6 | 3 | 15 | 1 | 7 | 3 | 16 | 1 | 8 | 2 | 14 | 0 | 14
+INPUTP | 9 | 160 | 93 | 90 | 54 | 56 | 63 | 57 | 58 | 60
+EXPORTS | 1 | 0 | 16
+IMPORTS | 1 | 0 | 14
+EQ | 14 | 
+   !ROM_OE.D = ;Imported pterms FB1_15
+	  RESET & RW & !AS & IDE_ENABLE & ide;
+   ROM_OE.CLK = ide/ide_CLKF;
+    ROM_OE_S.EXP  =  RESET & RW & !AS & A<5> & !A<4> & A<1> & !A<6> & 
+	!A<3> & A<2> & !AUTO_CONFIG_DONE<2> & autoconfig
+	# RESET & RW & !AS & A<5> & !A<4> & !A<6> & !A<3> & 
+	A<2> & AUTO_CONFIG_DONE<0> & !AUTO_CONFIG_DONE<1> & 
+	autoconfig
+	# RESET & RW & !AS & !A<5> & A<4> & A<1> & !A<6> & 
+	A<3> & AUTO_CONFIG_DONE<0> & !AUTO_CONFIG_DONE<1> & 
+	autoconfig
+	# RESET & RW & !AS & !A<5> & !A<1> & !A<6> & !A<3> & 
+	A<2> & AUTO_CONFIG_DONE<1> & !AUTO_CONFIG_DONE<2> & 
+	autoconfig
+
+MACROCELL | 2 | 8 | N1
+ATTRIBUTES | 265986 | 0
+INPUTS | 2 | RW  | AUTOCONFIG_IN_PROGRESS
+INPUTMC | 1 | 0 | 6
+INPUTP | 1 | 93
+EQ | 2 | 
+   D<9> = Vcc;
+   D<9>.OE = RW & AUTOCONFIG_IN_PROGRESS;
+
+MACROCELL | 0 | 4 | N1$BUF0
+ATTRIBUTES | 265986 | 0
+INPUTS | 2 | RW  | AUTOCONFIG_IN_PROGRESS
+INPUTMC | 1 | 0 | 6
+INPUTP | 1 | 93
+EQ | 2 | 
+   D<8> = Vcc;
+   D<8>.OE = RW & AUTOCONFIG_IN_PROGRESS;
+
+MACROCELL | 0 | 1 | N1$BUF1
+ATTRIBUTES | 265986 | 0
+OUTPUTMC | 1 | 0 | 0
+INPUTS | 3 | RW  | AUTOCONFIG_IN_PROGRESS  | A<13>
+INPUTMC | 1 | 0 | 6
+INPUTP | 2 | 93 | 72
+EXPORTS | 1 | 0 | 0
+EQ | 3 | 
+   D<7> = Vcc;
+   D<7>.OE = RW & AUTOCONFIG_IN_PROGRESS;
+    N1$BUF1.EXP  =  !A<13>
+
+MACROCELL | 1 | 4 | N1$BUF10
+ATTRIBUTES | 265986 | 0
+INPUTS | 2 | RW  | AUTOCONFIG_IN_PROGRESS
+INPUTMC | 1 | 0 | 6
+INPUTP | 1 | 93
+EQ | 2 | 
+   D<0> = Vcc;
+   D<0>.OE = RW & AUTOCONFIG_IN_PROGRESS;
+
+MACROCELL | 1 | 15 | N1$BUF2
+ATTRIBUTES | 265986 | 0
+OUTPUTMC | 1 | 1 | 14
+INPUTS | 14 | RW  | AUTOCONFIG_IN_PROGRESS  | RESET  | AS  | A<5>  | A<4>  | A<3>  | A<2>  | AUTO_CONFIG_DONE<2>  | autoconfig  | A<1>  | A<6>  | AUTO_CONFIG_DONE<1>  | AUTO_CONFIG_DONE<0>
+INPUTMC | 5 | 0 | 6 | 1 | 7 | 3 | 16 | 2 | 14 | 1 | 8
+INPUTP | 9 | 93 | 160 | 90 | 54 | 56 | 58 | 60 | 63 | 57
+EXPORTS | 1 | 1 | 14
+EQ | 11 | 
+   D<6> = Vcc;
+   D<6>.OE = RW & AUTOCONFIG_IN_PROGRESS;
+    N1$BUF2.EXP  =  RESET & RW & !AS & !A<5> & !A<4> & !A<3> & !A<2> & 
+	!AUTO_CONFIG_DONE<2> & autoconfig
+	# RESET & RW & !AS & !A<5> & !A<4> & A<1> & !A<6> & 
+	!A<3> & !AUTO_CONFIG_DONE<1> & autoconfig
+	# RESET & RW & !AS & !A<5> & A<1> & !A<6> & !A<3> & 
+	!A<2> & !AUTO_CONFIG_DONE<0> & autoconfig
+	# RESET & RW & !AS & !A<5> & A<4> & !A<1> & !A<6> & 
+	A<2> & AUTO_CONFIG_DONE<0> & !AUTO_CONFIG_DONE<1> & 
+	autoconfig
+
+MACROCELL | 0 | 5 | N1$BUF3
+ATTRIBUTES | 265986 | 0
+INPUTS | 2 | RW  | AUTOCONFIG_IN_PROGRESS
+INPUTMC | 1 | 0 | 6
+INPUTP | 1 | 93
+EQ | 2 | 
+   D<5> = Vcc;
+   D<5>.OE = RW & AUTOCONFIG_IN_PROGRESS;
+
+MACROCELL | 0 | 7 | N1$BUF4
+ATTRIBUTES | 265986 | 0
+INPUTS | 2 | RW  | AUTOCONFIG_IN_PROGRESS
+INPUTMC | 1 | 0 | 6
+INPUTP | 1 | 93
+EQ | 2 | 
+   D<4> = Vcc;
+   D<4>.OE = RW & AUTOCONFIG_IN_PROGRESS;
+
+MACROCELL | 1 | 16 | N1$BUF5
+ATTRIBUTES | 265986 | 0
+INPUTS | 2 | RW  | AUTOCONFIG_IN_PROGRESS
+INPUTMC | 1 | 0 | 6
+INPUTP | 1 | 93
+EQ | 2 | 
+   D<3> = Vcc;
+   D<3>.OE = RW & AUTOCONFIG_IN_PROGRESS;
+
+MACROCELL | 2 | 0 | N1$BUF6
+ATTRIBUTES | 265986 | 0
+INPUTS | 2 | RW  | AUTOCONFIG_IN_PROGRESS
+INPUTMC | 1 | 0 | 6
+INPUTP | 1 | 93
+EQ | 2 | 
+   D<2> = Vcc;
+   D<2>.OE = RW & AUTOCONFIG_IN_PROGRESS;
+
+MACROCELL | 0 | 2 | N1$BUF7
+ATTRIBUTES | 265986 | 0
+INPUTS | 2 | RW  | AUTOCONFIG_IN_PROGRESS
+INPUTMC | 1 | 0 | 6
+INPUTP | 1 | 93
+EQ | 2 | 
+   D<1> = Vcc;
+   D<1>.OE = RW & AUTOCONFIG_IN_PROGRESS;
+
+MACROCELL | 2 | 10 | N1$BUF8
+ATTRIBUTES | 265986 | 0
+INPUTS | 2 | RW  | AUTOCONFIG_IN_PROGRESS
+INPUTMC | 1 | 0 | 6
+INPUTP | 1 | 93
+EQ | 2 | 
+   D<11> = Vcc;
+   D<11>.OE = RW & AUTOCONFIG_IN_PROGRESS;
+
+MACROCELL | 2 | 2 | N1$BUF9
+ATTRIBUTES | 265986 | 0
+INPUTS | 2 | RW  | AUTOCONFIG_IN_PROGRESS
+INPUTMC | 1 | 0 | 6
+INPUTP | 1 | 93
+EQ | 2 | 
+   D<10> = Vcc;
+   D<10>.OE = RW & AUTOCONFIG_IN_PROGRESS;
+
+MACROCELL | 0 | 10 | IDE_A_0_OBUF$BUF0
+ATTRIBUTES | 264962 | 0
+INPUTS | 1 | A<9>
+INPUTP | 1 | 64
+EQ | 1 | 
+   IDE_A<0> = A<9>;
+
+MACROCELL | 0 | 11 | IDE_A_1_OBUF$BUF0
+ATTRIBUTES | 264962 | 0
+INPUTS | 1 | A<10>
+INPUTP | 1 | 66
+EQ | 1 | 
+   IDE_A<1> = A<10>;
+
+MACROCELL | 0 | 3 | IDE_A_2_OBUF$BUF0
+ATTRIBUTES | 264962 | 0
+INPUTS | 1 | A<11>
+INPUTP | 1 | 68
+EQ | 1 | 
+   IDE_A<2> = A<11>;
+
+MACROCELL | 0 | 8 | IDE_CS_0_OBUF
+ATTRIBUTES | 264962 | 0
+INPUTS | 1 | A<12>
+INPUTP | 1 | 69
+EQ | 1 | 
+   IDE_CS<0> = !A<12>;
+
+MACROCELL | 0 | 0 | IDE_CS_1_OBUF
+ATTRIBUTES | 264962 | 0
+OUTPUTMC | 1 | 0 | 17
+INPUTS | 14 | RESET  | RW  | AS  | A<5>  | A<4>  | A<6>  | A<3>  | A<2>  | AUTO_CONFIG_DONE<0>  | autoconfig  | AUTO_CONFIG_DONE<1>  | AUTO_CONFIG_DONE<2>  | A<1>  | N1$BUF1.EXP
+INPUTMC | 5 | 1 | 8 | 3 | 16 | 2 | 14 | 1 | 7 | 0 | 1
+INPUTP | 9 | 160 | 93 | 90 | 54 | 56 | 57 | 58 | 60 | 63
+EXPORTS | 1 | 0 | 17
+IMPORTS | 1 | 0 | 1
+EQ | 13 | 
+   IDE_CS<1> = ;Imported pterms FB1_2
+	  !A<13>;
+    IDE_CS_1_OBUF.EXP  =  RESET & RW & !AS & !A<5> & !A<4> & A<6> & !A<3> & 
+	!A<2> & !AUTO_CONFIG_DONE<0> & autoconfig
+	# RESET & RW & !AS & !A<5> & !A<4> & A<6> & !A<3> & 
+	!A<2> & !AUTO_CONFIG_DONE<1> & autoconfig
+	# RESET & RW & !AS & !A<5> & !A<4> & A<6> & !A<3> & 
+	!A<2> & !AUTO_CONFIG_DONE<2> & autoconfig
+	# RESET & RW & !AS & !A<5> & !A<1> & !A<6> & !A<3> & 
+	A<2> & !AUTO_CONFIG_DONE<0> & autoconfig
+	# RESET & RW & !AS & A<5> & !A<4> & A<1> & !A<6> & 
+	A<2> & AUTO_CONFIG_DONE<0> & !AUTO_CONFIG_DONE<1> & 
+	autoconfig
+
+MACROCELL | 6 | 11 | ROM_B_0_OBUF$BUF1
+ATTRIBUTES | 265986 | 0
+INPUTS | 0
+EQ | 2 | 
+   DTACK = Gnd;
+   DTACK.OE = Gnd;
+
+MACROCELL | 4 | 16 | ROM_B_0_OBUF
+ATTRIBUTES | 264962 | 0
+INPUTS | 0
+EQ | 1 | 
+   ROM_B<1> = Gnd;
+
+MACROCELL | 4 | 9 | ROM_B_0_OBUF$BUF0
+ATTRIBUTES | 264962 | 0
+INPUTS | 0
+EQ | 1 | 
+   ROM_B<0> = Gnd;
+
+MACROCELL | 3 | 15 | ide/ide_CLKF
+ATTRIBUTES | 133888 | 0
+OUTPUTMC | 23 | 1 | 14 | 0 | 17 | 1 | 0 | 5 | 16 | 1 | 10 | 2 | 15 | 1 | 9 | 4 | 17 | 4 | 14 | 4 | 13 | 0 | 9 | 4 | 15 | 2 | 17 | 2 | 16 | 1 | 12 | 1 | 11 | 4 | 12 | 3 | 16 | 3 | 0 | 0 | 6 | 0 | 13 | 0 | 14 | 0 | 15
+INPUTS | 2 | C3  | C1
+INPUTP | 2 | 114 | 115
+EQ | 2 | 
+   !ide/ide_CLKF = C3
+	$ C1;
+
+MACROCELL | 2 | 3 | _10_
+ATTRIBUTES | 397058 | 0
+OUTPUTMC | 1 | 0 | 16
+INPUTS | 3 | RW  | AUTOCONFIG_IN_PROGRESS  | D<12>_BUFR
+INPUTMC | 2 | 0 | 6 | 0 | 17
+INPUTP | 1 | 93
+EQ | 2 | 
+   D<12> = D<12>_BUFR;
+   D<12>.OE = RW & AUTOCONFIG_IN_PROGRESS;
+
+MACROCELL | 2 | 6 | _11_
+ATTRIBUTES | 397058 | 0
+OUTPUTMC | 1 | 1 | 17
+INPUTS | 3 | RW  | AUTOCONFIG_IN_PROGRESS  | D<14>_BUFR
+INPUTMC | 2 | 0 | 6 | 1 | 0
+INPUTP | 1 | 93
+EQ | 2 | 
+   D<14> = D<14>_BUFR;
+   D<14>.OE = RW & AUTOCONFIG_IN_PROGRESS;
+
+MACROCELL | 2 | 11 | _12_
+ATTRIBUTES | 397058 | 0
+OUTPUTMC | 2 | 1 | 14 | 1 | 13
+INPUTS | 3 | RW  | AUTOCONFIG_IN_PROGRESS  | D<13>_BUFR
+INPUTMC | 2 | 0 | 6 | 1 | 14
+INPUTP | 1 | 93
+EQ | 2 | 
+   D<13> = D<13>_BUFR;
+   D<13>.OE = RW & AUTOCONFIG_IN_PROGRESS;
+
+MACROCELL | 2 | 9 | _13_
+ATTRIBUTES | 397058 | 0
+OUTPUTMC | 2 | 5 | 16 | 5 | 15
+INPUTS | 3 | RW  | AUTOCONFIG_IN_PROGRESS  | D<15>_BUFR
+INPUTMC | 2 | 0 | 6 | 5 | 16
+INPUTP | 1 | 93
+EQ | 2 | 
+   D<15> = D<15>_BUFR;
+   D<15>.OE = RW & AUTOCONFIG_IN_PROGRESS;
+
+MACROCELL | 0 | 16 | EXP14_
+ATTRIBUTES | 2048 | 0
+OUTPUTMC | 1 | 0 | 17
+INPUTS | 14 | RESET  | D<12>  | RW  | AS  | autoconfig  | AUTO_CONFIG_DONE<0>  | AUTO_CONFIG_DONE<1>  | AUTO_CONFIG_DONE<2>  | A<5>  | A<4>  | A<1>  | A<3>  | A<2>  | ROM_OE_S.EXP
+INPUTMC | 6 | 2 | 3 | 3 | 16 | 1 | 8 | 2 | 14 | 1 | 7 | 0 | 15
+INPUTP | 8 | 160 | 93 | 90 | 54 | 56 | 63 | 58 | 60
+EXPORTS | 1 | 0 | 17
+IMPORTS | 1 | 0 | 15
+EQ | 19 | 
+       EXP14_.EXP  =  RESET & !D<12> & !RW
+	# RESET & !D<12> & AS
+	# RESET & !D<12> & !autoconfig
+	# RESET & !D<12> & AUTO_CONFIG_DONE<0> & 
+	AUTO_CONFIG_DONE<1> & AUTO_CONFIG_DONE<2>
+	# RESET & RW & !AS & !A<5> & !A<4> & !A<1> & !A<3> & 
+	!A<2> & !AUTO_CONFIG_DONE<0> & autoconfig
+;Imported pterms FB1_16
+	# RESET & RW & !AS & A<5> & !A<4> & A<1> & !A<6> & 
+	!A<3> & A<2> & !AUTO_CONFIG_DONE<2> & autoconfig
+	# RESET & RW & !AS & A<5> & !A<4> & !A<6> & !A<3> & 
+	A<2> & AUTO_CONFIG_DONE<0> & !AUTO_CONFIG_DONE<1> & 
+	autoconfig
+	# RESET & RW & !AS & !A<5> & A<4> & A<1> & !A<6> & 
+	A<3> & AUTO_CONFIG_DONE<0> & !AUTO_CONFIG_DONE<1> & 
+	autoconfig
+	# RESET & RW & !AS & !A<5> & !A<1> & !A<6> & !A<3> & 
+	A<2> & AUTO_CONFIG_DONE<1> & !AUTO_CONFIG_DONE<2> & 
+	autoconfig
+
+MACROCELL | 1 | 1 | EXP15_
+ATTRIBUTES | 2048 | 0
+OUTPUTMC | 1 | 1 | 0
+INPUTS | 14 | RESET  | RW  | AS  | A<5>  | A<4>  | A<1>  | A<3>  | A<2>  | AUTO_CONFIG_DONE<0>  | autoconfig  | A<6>  | AUTO_CONFIG_DONE<1>  | AUTO_CONFIG_DONE<2>  | EXP16_.EXP
+INPUTMC | 5 | 1 | 8 | 3 | 16 | 2 | 14 | 1 | 7 | 1 | 2
+INPUTP | 9 | 160 | 93 | 90 | 54 | 56 | 63 | 58 | 60 | 57
+EXPORTS | 1 | 1 | 0
+IMPORTS | 1 | 1 | 2
+EQ | 19 | 
+       EXP15_.EXP  =  RESET & RW & !AS & !A<5> & !A<4> & A<1> & !A<3> & 
+	!A<2> & !AUTO_CONFIG_DONE<0> & autoconfig
+	# RESET & RW & !AS & !A<5> & !A<4> & A<6> & !A<3> & 
+	!A<2> & !AUTO_CONFIG_DONE<0> & autoconfig
+	# RESET & RW & !AS & !A<5> & !A<4> & A<6> & !A<3> & 
+	!A<2> & !AUTO_CONFIG_DONE<1> & autoconfig
+	# RESET & RW & !AS & !A<5> & !A<4> & A<6> & !A<3> & 
+	!A<2> & !AUTO_CONFIG_DONE<2> & autoconfig
+	# RESET & RW & !AS & !A<4> & A<1> & !A<6> & !A<3> & 
+	A<2> & AUTO_CONFIG_DONE<0> & !AUTO_CONFIG_DONE<1> & 
+	autoconfig
+;Imported pterms FB2_3
+	# RESET & RW & !AS & !A<5> & A<4> & A<1> & !A<6> & 
+	!A<3> & A<2> & !AUTO_CONFIG_DONE<0> & autoconfig
+	# RESET & RW & !AS & !A<5> & !A<4> & !A<1> & !A<6> & 
+	!A<3> & A<2> & !AUTO_CONFIG_DONE<0> & autoconfig
+	# RESET & RW & !AS & !A<5> & A<4> & !A<1> & !A<6> & 
+	A<3> & A<2> & AUTO_CONFIG_DONE<0> & !AUTO_CONFIG_DONE<1> & 
+	autoconfig
+
+MACROCELL | 1 | 2 | EXP16_
+ATTRIBUTES | 2048 | 0
+OUTPUTMC | 1 | 1 | 1
+INPUTS | 12 | RESET  | RW  | AS  | A<5>  | A<4>  | A<1>  | A<6>  | A<3>  | A<2>  | AUTO_CONFIG_DONE<0>  | autoconfig  | AUTO_CONFIG_DONE<1>
+INPUTMC | 3 | 1 | 8 | 3 | 16 | 2 | 14
+INPUTP | 9 | 160 | 93 | 90 | 54 | 56 | 63 | 57 | 58 | 60
+EXPORTS | 1 | 1 | 1
+EQ | 7 | 
+       EXP16_.EXP  =  RESET & RW & !AS & !A<5> & A<4> & A<1> & !A<6> & 
+	!A<3> & A<2> & !AUTO_CONFIG_DONE<0> & autoconfig
+	# RESET & RW & !AS & !A<5> & !A<4> & !A<1> & !A<6> & 
+	!A<3> & A<2> & !AUTO_CONFIG_DONE<0> & autoconfig
+	# RESET & RW & !AS & !A<5> & A<4> & !A<1> & !A<6> & 
+	A<3> & A<2> & AUTO_CONFIG_DONE<0> & !AUTO_CONFIG_DONE<1> & 
+	autoconfig
+
+MACROCELL | 1 | 13 | EXP17_
+ATTRIBUTES | 2048 | 0
+OUTPUTMC | 1 | 1 | 14
+INPUTS | 14 | RESET  | D<13>  | RW  | AUTO_CONFIG_DONE<0>  | AUTO_CONFIG_DONE<1>  | AUTO_CONFIG_DONE<2>  | AS  | A<5>  | A<4>  | A<6>  | A<3>  | autoconfig  | A<2>  | IDE_BASEADR<6>.EXP
+INPUTMC | 6 | 2 | 11 | 1 | 8 | 2 | 14 | 1 | 7 | 3 | 16 | 1 | 12
+INPUTP | 8 | 160 | 93 | 90 | 54 | 56 | 57 | 58 | 60
+EXPORTS | 1 | 1 | 14
+IMPORTS | 1 | 1 | 12
+EQ | 19 | 
+       EXP17_.EXP  =  RESET & !D<13> & !RW
+	# RESET & !D<13> & AUTO_CONFIG_DONE<0> & 
+	AUTO_CONFIG_DONE<1> & AUTO_CONFIG_DONE<2>
+	# RESET & RW & !AS & !A<5> & !A<4> & !A<6> & !A<3> & 
+	!AUTO_CONFIG_DONE<0> & autoconfig
+	# RESET & RW & !AS & !A<5> & !A<4> & !A<3> & !A<2> & 
+	!AUTO_CONFIG_DONE<0> & autoconfig
+	# RESET & RW & !AS & !A<5> & !A<4> & !A<3> & !A<2> & 
+	!AUTO_CONFIG_DONE<1> & autoconfig
+;Imported pterms FB2_13
+	# RESET & RW & !AS & !A<5> & A<4> & !A<1> & !A<6> & 
+	A<3> & AUTO_CONFIG_DONE<0> & !AUTO_CONFIG_DONE<1> & 
+	autoconfig
+	# RESET & RW & !AS & !A<5> & !A<4> & !A<1> & !A<6> & 
+	!A<3> & AUTO_CONFIG_DONE<1> & !AUTO_CONFIG_DONE<2> & 
+	autoconfig
+	# RESET & RW & !AS & A<5> & !A<4> & !A<1> & !A<6> & 
+	!A<3> & A<2> & AUTO_CONFIG_DONE<0> & !AUTO_CONFIG_DONE<1> & 
+	autoconfig
+
+MACROCELL | 1 | 17 | EXP18_
+ATTRIBUTES | 2048 | 0
+OUTPUTMC | 1 | 1 | 0
+INPUTS | 13 | RESET  | D<14>  | RW  | AS  | autoconfig  | AUTO_CONFIG_DONE<0>  | AUTO_CONFIG_DONE<1>  | AUTO_CONFIG_DONE<2>  | A<5>  | A<1>  | A<6>  | A<3>  | A<2>
+INPUTMC | 5 | 2 | 6 | 3 | 16 | 1 | 8 | 2 | 14 | 1 | 7
+INPUTP | 8 | 160 | 93 | 90 | 54 | 63 | 57 | 58 | 60
+EXPORTS | 1 | 1 | 0
+EQ | 8 | 
+       EXP18_.EXP  =  RESET & !D<14> & !RW
+	# RESET & !D<14> & AS
+	# RESET & !D<14> & !autoconfig
+	# RESET & !D<14> & AUTO_CONFIG_DONE<0> & 
+	AUTO_CONFIG_DONE<1> & AUTO_CONFIG_DONE<2>
+	# RESET & RW & !AS & !A<5> & A<1> & !A<6> & !A<3> & 
+	A<2> & AUTO_CONFIG_DONE<0> & !AUTO_CONFIG_DONE<2> & 
+	autoconfig
+
+MACROCELL | 3 | 1 | EXP19_
+ATTRIBUTES | 2048 | 0
+OUTPUTMC | 1 | 3 | 0
+INPUTS | 7 | A<23>  | IDE_BASEADR<7>  | A<22>  | IDE_BASEADR<6>  | IDE_BASEADR<1>  | A<17>  | EXP20_.EXP
+INPUTMC | 4 | 1 | 11 | 1 | 12 | 4 | 15 | 3 | 2
+INPUTP | 3 | 96 | 97 | 106
+EXPORTS | 1 | 3 | 0
+IMPORTS | 1 | 3 | 2
+EQ | 9 | 
+       EXP19_.EXP  =  A<23> & !IDE_BASEADR<7>
+	# !A<23> & IDE_BASEADR<7>
+	# A<22> & !IDE_BASEADR<6>
+	# !A<22> & IDE_BASEADR<6>
+	# IDE_BASEADR<1> & !A<17>
+;Imported pterms FB4_3
+	# !A<21> & IDE_BASEADR<5>
+	# IDE_BASEADR<4> & !A<20>
+	# !IDE_BASEADR<4> & A<20>
+
+MACROCELL | 3 | 2 | EXP20_
+ATTRIBUTES | 2048 | 0
+OUTPUTMC | 1 | 3 | 1
+INPUTS | 4 | A<21>  | IDE_BASEADR<5>  | IDE_BASEADR<4>  | A<20>
+INPUTMC | 2 | 4 | 13 | 4 | 14
+INPUTP | 2 | 98 | 102
+EXPORTS | 1 | 3 | 1
+EQ | 3 | 
+       EXP20_.EXP  =  !A<21> & IDE_BASEADR<5>
+	# IDE_BASEADR<4> & !A<20>
+	# !IDE_BASEADR<4> & A<20>
+
+MACROCELL | 3 | 17 | EXP21_
+ATTRIBUTES | 2048 | 0
+OUTPUTMC | 1 | 3 | 0
+INPUTS | 7 | IDE_BASEADR<0>  | A<16>  | IDE_BASEADR<1>  | A<17>  | IDE_BASEADR<2>  | A<18>  | autoconfig.EXP
+INPUTMC | 4 | 4 | 17 | 4 | 15 | 2 | 17 | 3 | 16
+INPUTP | 3 | 108 | 106 | 105
+EXPORTS | 1 | 3 | 0
+IMPORTS | 1 | 3 | 16
+EQ | 7 | 
+       EXP21_.EXP  =  IDE_BASEADR<0> & !A<16>
+	# !IDE_BASEADR<0> & A<16>
+	# !IDE_BASEADR<1> & A<17>
+	# IDE_BASEADR<2> & !A<18>
+	# !IDE_BASEADR<2> & A<18>
+;Imported pterms FB4_17
+	# A<21> & !IDE_BASEADR<5>
+
+MACROCELL | 5 | 15 | EXP22_
+ATTRIBUTES | 2048 | 0
+OUTPUTMC | 1 | 5 | 16
+INPUTS | 14 | RESET  | D<15>  | AUTO_CONFIG_DONE<0>  | AUTO_CONFIG_DONE<1>  | AUTO_CONFIG_DONE<2>  | RW  | AS  | A<5>  | A<1>  | A<6>  | A<3>  | autoconfig  | A<4>  | A<2>
+INPUTMC | 5 | 2 | 9 | 1 | 8 | 2 | 14 | 1 | 7 | 3 | 16
+INPUTP | 9 | 160 | 93 | 90 | 54 | 63 | 57 | 58 | 56 | 60
+EXPORTS | 1 | 5 | 16
+EQ | 8 | 
+       EXP22_.EXP  =  RESET & !D<15> & AUTO_CONFIG_DONE<0> & 
+	AUTO_CONFIG_DONE<1> & AUTO_CONFIG_DONE<2>
+	# RESET & RW & !AS & !A<5> & A<1> & !A<6> & !A<3> & 
+	!AUTO_CONFIG_DONE<0> & autoconfig
+	# RESET & RW & !AS & !A<5> & !A<4> & A<6> & !A<3> & 
+	!A<2> & !AUTO_CONFIG_DONE<0> & autoconfig
+	# RESET & RW & !AS & !A<5> & !A<4> & A<6> & !A<3> & 
+	!A<2> & !AUTO_CONFIG_DONE<1> & autoconfig
+
+MACROCELL | 5 | 17 | EXP23_
+ATTRIBUTES | 2048 | 0
+OUTPUTMC | 1 | 5 | 16
+INPUTS | 13 | RESET  | RW  | AS  | A<5>  | A<4>  | A<6>  | A<3>  | A<2>  | AUTO_CONFIG_DONE<2>  | autoconfig  | A<1>  | AUTO_CONFIG_DONE<1>  | AUTO_CONFIG_DONE<0>
+INPUTMC | 4 | 1 | 7 | 3 | 16 | 2 | 14 | 1 | 8
+INPUTP | 9 | 160 | 93 | 90 | 54 | 56 | 57 | 58 | 60 | 63
+EXPORTS | 1 | 5 | 16
+EQ | 13 | 
+       EXP23_.EXP  =  RESET & RW & !AS & !A<5> & !A<4> & A<6> & !A<3> & 
+	!A<2> & !AUTO_CONFIG_DONE<2> & autoconfig
+	# RESET & RW & !AS & !A<5> & A<1> & !A<6> & !A<3> & 
+	AUTO_CONFIG_DONE<1> & !AUTO_CONFIG_DONE<2> & autoconfig
+	# RESET & RW & !AS & !A<5> & A<4> & A<1> & !A<6> & 
+	A<2> & AUTO_CONFIG_DONE<0> & !AUTO_CONFIG_DONE<1> & 
+	autoconfig
+	# RESET & RW & !AS & A<5> & !A<4> & !A<1> & !A<6> & 
+	!A<3> & A<2> & AUTO_CONFIG_DONE<0> & !AUTO_CONFIG_DONE<1> & 
+	autoconfig
+	# RESET & RW & !AS & !A<5> & A<4> & !A<1> & !A<6> & 
+	A<3> & !A<2> & AUTO_CONFIG_DONE<0> & !AUTO_CONFIG_DONE<1> & 
+	autoconfig
+
+PIN | RESET | 65600 | 0 | N/A | 160 | 32 | 1 | 14 | 0 | 17 | 1 | 0 | 5 | 16 | 1 | 10 | 2 | 15 | 1 | 9 | 4 | 17 | 4 | 14 | 4 | 13 | 0 | 9 | 4 | 15 | 2 | 17 | 2 | 16 | 1 | 12 | 1 | 11 | 4 | 12 | 0 | 13 | 0 | 14 | 0 | 0 | 0 | 15 | 0 | 16 | 1 | 1 | 1 | 2 | 1 | 13 | 1 | 15 | 1 | 17 | 5 | 15 | 5 | 17 | 1 | 8 | 2 | 14 | 1 | 7
+PIN | RW | 64 | 0 | N/A | 93 | 44 | 1 | 14 | 0 | 17 | 1 | 0 | 5 | 16 | 1 | 10 | 2 | 15 | 1 | 9 | 4 | 17 | 4 | 14 | 4 | 13 | 0 | 9 | 4 | 15 | 2 | 17 | 2 | 16 | 1 | 2 | 1 | 11 | 4 | 12 | 0 | 13 | 0 | 14 | 0 | 0 | 2 | 8 | 0 | 4 | 0 | 1 | 1 | 4 | 1 | 15 | 0 | 5 | 0 | 7 | 1 | 16 | 2 | 0 | 0 | 2 | 2 | 10 | 2 | 2 | 2 | 3 | 2 | 6 | 2 | 11 | 2 | 9 | 0 | 15 | 0 | 16 | 1 | 1 | 1 | 12 | 1 | 13 | 1 | 17 | 5 | 15 | 5 | 17
+PIN | A<1> | 64 | 0 | N/A | 63 | 25 | 1 | 14 | 0 | 17 | 1 | 0 | 5 | 16 | 1 | 10 | 2 | 15 | 1 | 9 | 4 | 17 | 4 | 14 | 4 | 13 | 4 | 15 | 2 | 17 | 2 | 16 | 1 | 2 | 1 | 11 | 4 | 12 | 0 | 0 | 0 | 15 | 0 | 16 | 1 | 1 | 1 | 12 | 1 | 15 | 1 | 17 | 5 | 15 | 5 | 17
+PIN | A<2> | 64 | 0 | N/A | 60 | 24 | 1 | 14 | 0 | 17 | 1 | 0 | 5 | 16 | 4 | 17 | 4 | 14 | 4 | 13 | 4 | 15 | 2 | 17 | 2 | 16 | 1 | 10 | 1 | 11 | 4 | 12 | 0 | 0 | 0 | 15 | 0 | 16 | 1 | 1 | 1 | 2 | 1 | 12 | 1 | 13 | 1 | 15 | 1 | 17 | 5 | 15 | 5 | 17
+PIN | A<5> | 64 | 0 | N/A | 54 | 26 | 1 | 14 | 0 | 17 | 1 | 0 | 5 | 16 | 1 | 10 | 2 | 15 | 1 | 9 | 4 | 17 | 4 | 14 | 4 | 13 | 4 | 15 | 2 | 17 | 2 | 16 | 1 | 2 | 1 | 11 | 4 | 12 | 0 | 0 | 0 | 15 | 0 | 16 | 1 | 1 | 1 | 12 | 1 | 13 | 1 | 15 | 1 | 17 | 5 | 15 | 5 | 17
+PIN | A<6> | 64 | 0 | N/A | 57 | 25 | 1 | 14 | 0 | 17 | 1 | 0 | 5 | 16 | 1 | 10 | 2 | 15 | 1 | 9 | 4 | 17 | 4 | 14 | 4 | 13 | 4 | 15 | 2 | 17 | 2 | 16 | 1 | 2 | 1 | 11 | 4 | 12 | 0 | 0 | 0 | 15 | 1 | 1 | 1 | 12 | 1 | 13 | 1 | 15 | 1 | 17 | 5 | 15 | 5 | 17
+PIN | A<3> | 64 | 0 | N/A | 58 | 26 | 1 | 14 | 0 | 17 | 1 | 0 | 5 | 16 | 1 | 10 | 2 | 15 | 1 | 9 | 4 | 17 | 4 | 14 | 4 | 13 | 4 | 15 | 2 | 17 | 2 | 16 | 1 | 2 | 1 | 11 | 4 | 12 | 0 | 0 | 0 | 15 | 0 | 16 | 1 | 1 | 1 | 12 | 1 | 13 | 1 | 15 | 1 | 17 | 5 | 15 | 5 | 17
+PIN | AS | 64 | 0 | N/A | 90 | 33 | 1 | 14 | 0 | 17 | 1 | 0 | 5 | 16 | 1 | 8 | 2 | 14 | 1 | 7 | 1 | 10 | 2 | 15 | 1 | 9 | 4 | 17 | 4 | 14 | 4 | 13 | 0 | 9 | 4 | 15 | 2 | 17 | 2 | 16 | 1 | 2 | 1 | 11 | 4 | 12 | 0 | 6 | 0 | 13 | 0 | 14 | 0 | 0 | 0 | 15 | 0 | 16 | 1 | 1 | 1 | 12 | 1 | 13 | 1 | 15 | 1 | 17 | 5 | 15 | 5 | 17
+PIN | A<4> | 64 | 0 | N/A | 56 | 24 | 1 | 14 | 0 | 17 | 1 | 0 | 5 | 15 | 1 | 10 | 2 | 15 | 1 | 9 | 4 | 17 | 4 | 14 | 4 | 13 | 4 | 15 | 2 | 17 | 2 | 16 | 1 | 2 | 1 | 11 | 4 | 12 | 0 | 0 | 0 | 15 | 0 | 16 | 1 | 1 | 1 | 12 | 1 | 13 | 1 | 15 | 5 | 17
+PIN | AUTOBOOT_OFF | 64 | 0 | N/A | 84 | 1 | 0 | 17
+PIN | UDS | 64 | 0 | N/A | 91 | 11 | 1 | 10 | 2 | 15 | 1 | 9 | 4 | 17 | 4 | 14 | 4 | 13 | 4 | 15 | 2 | 17 | 2 | 16 | 4 | 12 | 1 | 11
+PIN | A<23> | 64 | 0 | N/A | 96 | 2 | 3 | 16 | 3 | 1
+PIN | A<22> | 64 | 0 | N/A | 97 | 2 | 3 | 16 | 3 | 1
+PIN | A<21> | 64 | 0 | N/A | 98 | 2 | 3 | 16 | 3 | 2
+PIN | A<19> | 64 | 0 | N/A | 103 | 2 | 3 | 16 | 3 | 0
+PIN | BERR | 64 | 0 | N/A | 109 | 2 | 3 | 16 | 3 | 0
+PIN | C1 | 64 | 0 | N/A | 115 | 1 | 3 | 15
+PIN | C3 | 64 | 0 | N/A | 114 | 1 | 3 | 15
+PIN | A<16> | 64 | 0 | N/A | 108 | 2 | 3 | 16 | 3 | 17
+PIN | A<20> | 64 | 0 | N/A | 102 | 2 | 3 | 16 | 3 | 2
+PIN | A<17> | 64 | 0 | N/A | 106 | 3 | 3 | 16 | 3 | 1 | 3 | 17
+PIN | A<18> | 64 | 0 | N/A | 105 | 2 | 3 | 16 | 3 | 17
+PIN | A<9> | 64 | 0 | N/A | 64 | 1 | 0 | 10
+PIN | A<10> | 64 | 0 | N/A | 66 | 1 | 0 | 11
+PIN | A<11> | 64 | 0 | N/A | 68 | 1 | 0 | 3
+PIN | A<12> | 64 | 0 | N/A | 69 | 1 | 0 | 8
+PIN | A<13> | 64 | 0 | N/A | 72 | 1 | 0 | 1
+PIN | IDE_R | 536871040 | 0 | N/A | 29
+PIN | IDE_W | 536871040 | 0 | N/A | 30
+PIN | ROM_OE | 536871040 | 0 | N/A | 39
+PIN | D<7> | 536871040 | 0 | N/A | 18
+PIN | D<0> | 536871040 | 0 | N/A | 2
+PIN | D<6> | 536871040 | 0 | N/A | 16
+PIN | D<5> | 536871040 | 0 | N/A | 22
+PIN | D<4> | 536871040 | 0 | N/A | 23
+PIN | D<3> | 536871040 | 0 | N/A | 17
+PIN | D<2> | 536871040 | 0 | N/A | 43
+PIN | D<1> | 536871040 | 0 | N/A | 19
+PIN | IDE_A<0> | 536871040 | 0 | N/A | 26
+PIN | IDE_A<1> | 536871040 | 0 | N/A | 28
+PIN | IDE_A<2> | 536871040 | 0 | N/A | 27
+PIN | IDE_CS<0> | 536871040 | 0 | N/A | 24
+PIN | IDE_CS<1> | 536871040 | 0 | N/A | 25
+PIN | DTACK | 536871040 | 0 | N/A | 95
+PIN | ROM_B<1> | 536871040 | 0 | N/A | 77
+PIN | ROM_B<0> | 536871040 | 0 | N/A | 76
+PIN | D<13> | 536870976 | 0 | N/A | 49 | 1 | 4 | 13
+PIN | D<12> | 536870976 | 0 | N/A | 48 | 1 | 4 | 14
+PIN | D<14> | 536870976 | 0 | N/A | 50 | 1 | 1 | 11
+PIN | D<15> | 536870976 | 0 | N/A | 52 | 2 | 1 | 11 | 1 | 10
+PIN | D<9> | 536870976 | 0 | N/A | 44 | 1 | 4 | 15
+PIN | D<8> | 536870976 | 0 | N/A | 21 | 1 | 4 | 17
+PIN | D<11> | 536870976 | 0 | N/A | 47 | 1 | 2 | 16
+PIN | D<10> | 536870976 | 0 | N/A | 45 | 1 | 2 | 17
diff --git a/Logic/LAN_IDE/LAN_IDE_CP.nga b/Logic/LAN_IDE/LAN_IDE_CP.nga
new file mode 100644
index 0000000..b09b633
--- /dev/null
+++ b/Logic/LAN_IDE/LAN_IDE_CP.nga
@@ -0,0 +1,3 @@
+XILINX-XDB 0.1 STUB 0.1 ASCII
+XILINX-XDM V1.6e
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\ No newline at end of file
diff --git a/Logic/LAN_IDE/LAN_IDE_CP.ngc b/Logic/LAN_IDE/LAN_IDE_CP.ngc
new file mode 100644
index 0000000..e337966
--- /dev/null
+++ b/Logic/LAN_IDE/LAN_IDE_CP.ngc
@@ -0,0 +1,3 @@
+XILINX-XDB 0.1 STUB 0.1 ASCII
+XILINX-XDM V1.6e
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\ No newline at end of file
diff --git a/Logic/LAN_IDE/LAN_IDE_CP.ngd b/Logic/LAN_IDE/LAN_IDE_CP.ngd
new file mode 100644
index 0000000..19ee67f
--- /dev/null
+++ b/Logic/LAN_IDE/LAN_IDE_CP.ngd
@@ -0,0 +1,3 @@
+XILINX-XDB 0.1 STUB 0.1 ASCII
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diff --git a/Logic/LAN_IDE/LAN_IDE_CP.ngr b/Logic/LAN_IDE/LAN_IDE_CP.ngr
new file mode 100644
index 0000000..99d9952
--- /dev/null
+++ b/Logic/LAN_IDE/LAN_IDE_CP.ngr
@@ -0,0 +1,3 @@
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\ No newline at end of file
diff --git a/Logic/LAN_IDE/LAN_IDE_CP.pad b/Logic/LAN_IDE/LAN_IDE_CP.pad
new file mode 100644
index 0000000..f028475
--- /dev/null
+++ b/Logic/LAN_IDE/LAN_IDE_CP.pad
@@ -0,0 +1,173 @@
+Release 8.1i - Fit P.68d
+Copyright(c) 1995-2003 Xilinx Inc. All rights reserved
+
+12-15-2016  7:48PM
+
+NOTE: This file is designed to be imported into a spreadsheet program
+such as Microsoft Excel for viewing, printing and sorting. The pipe '|'
+character is used as the data field separator.
+This file is also designed to support parsing.
+
+Input file:  LAN_IDE_CP.ngd
+output file: LAN_IDE_CP.pad
+Part type:   xc95144xl
+Speed grade: -10
+Package:     tq144
+
+Pinout by Pin Number:
+
+-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|
+Pin Number|Signal Name|Pin Usage|Pin Name|Direction|IO Standard|IO Bank Number|{blank}|Slew Rate|Termination|{blank}|Voltage|Constraint|
+P1|VCC||VCCIO||||||||||
+P2|D<0>|O|I/O/GTS3|OUTPUT|||||||||
+P3|TIE||I/O/GTS4||||||||||
+P4|TIE||I/O||||||||||
+P5|TIE||I/O/GTS1||||||||||
+P6|TIE||I/O/GTS2||||||||||
+P7|TIE||I/O||||||||||
+P8|VCC||VCCINT||||||||||
+P9|TIE||I/O||||||||||
+P10|TIE||I/O||||||||||
+P11|TIE||I/O||||||||||
+P12|TIE||I/O||||||||||
+P13|TIE||I/O||||||||||
+P14|D<6>|O|I/O|OUTPUT|||||||||
+P15|D<3>|O|I/O|OUTPUT|||||||||
+P16|D<7>|O|I/O|OUTPUT|||||||||
+P17|D<1>|O|I/O|OUTPUT|||||||||
+P18|GND||GND||||||||||
+P19|D<8>|I/O|I/O|BIDIR|||||||||
+P20|D<5>|O|I/O|OUTPUT|||||||||
+P21|D<4>|O|I/O|OUTPUT|||||||||
+P22|IDE_CS<0>|O|I/O|OUTPUT|||||||||
+P23|IDE_CS<1>|O|I/O|OUTPUT|||||||||
+P24|IDE_A<0>|O|I/O|OUTPUT|||||||||
+P25|IDE_A<2>|O|I/O|OUTPUT|||||||||
+P26|IDE_A<1>|O|I/O|OUTPUT|||||||||
+P27|IDE_R|O|I/O|OUTPUT|||||||||
+P28|IDE_W|O|I/O|OUTPUT|||||||||
+P29|GND||GND||||||||||
+P30|TIE||I/O/GCK1||||||||||
+P31|TIE||I/O||||||||||
+P32|TIE||I/O/GCK2||||||||||
+P33|TIE||I/O||||||||||
+P34|TIE||I/O||||||||||
+P35|ROM_OE|O|I/O|OUTPUT|||||||||
+P36|GND||GND||||||||||
+P37|VCC||VCCIO||||||||||
+P38|TIE||I/O/GCK3||||||||||
+P39|D<2>|O|I/O|OUTPUT|||||||||
+P40|D<9>|I/O|I/O|BIDIR|||||||||
+P41|D<10>|I/O|I/O|BIDIR|||||||||
+P42|VCC||VCCINT||||||||||
+P43|D<11>|I/O|I/O|BIDIR|||||||||
+P44|D<12>|I/O|I/O|BIDIR|||||||||
+P45|D<13>|I/O|I/O|BIDIR|||||||||
+P46|D<14>|I/O|I/O|BIDIR|||||||||
+P47|GND||GND||||||||||
+P48|D<15>|I/O|I/O|BIDIR|||||||||
+P49|A<5>|I|I/O|INPUT|||||||||
+P50|A<4>|I|I/O|INPUT|||||||||
+P51|A<6>|I|I/O|INPUT|||||||||
+P52|A<3>|I|I/O|INPUT|||||||||
+P53|TIE||I/O||||||||||
+P54|A<2>|I|I/O|INPUT|||||||||
+P55|VCC||VCCIO||||||||||
+P56|TIE||I/O||||||||||
+P57|A<1>|I|I/O|INPUT|||||||||
+P58|A<9>|I|I/O|INPUT|||||||||
+P59|A<10>|I|I/O|INPUT|||||||||
+P60|A<11>|I|I/O|INPUT|||||||||
+P61|A<12>|I|I/O|INPUT|||||||||
+P62|GND||GND||||||||||
+P63|TDI||TDI||||||||||
+P64|A<13>|I|I/O|INPUT|||||||||
+P65|TMS||TMS||||||||||
+P66|TIE||I/O||||||||||
+P67|TCK||TCK||||||||||
+P68|ROM_B<0>|O|I/O|OUTPUT|||||||||
+P69|ROM_B<1>|O|I/O|OUTPUT|||||||||
+P70|TIE||I/O||||||||||
+P71|TIE||I/O||||||||||
+P72|GND||GND||||||||||
+P73|VCC||VCCIO||||||||||
+P74|TIE||I/O||||||||||
+P75|AUTOBOOT_OFF|I|I/O|INPUT|||||||||
+P76|TIE||I/O||||||||||
+P77|TIE||I/O||||||||||
+P78|TIE||I/O||||||||||
+P79|TIE||I/O||||||||||
+P80|AS|I|I/O|INPUT|||||||||
+P81|UDS|I|I/O|INPUT|||||||||
+P82|TIE||I/O||||||||||
+P83|RW|I|I/O|INPUT|||||||||
+P84|VCC||VCCINT||||||||||
+P85|DTACK|O|I/O|OUTPUT|||||||||
+P86|A<23>|I|I/O|INPUT|||||||||
+P87|A<22>|I|I/O|INPUT|||||||||
+P88|A<21>|I|I/O|INPUT|||||||||
+P89|GND||GND||||||||||
+P90|GND||GND||||||||||
+P91|A<20>|I|I/O|INPUT|||||||||
+P92|A<19>|I|I/O|INPUT|||||||||
+P93|TIE||I/O||||||||||
+P94|A<18>|I|I/O|INPUT|||||||||
+P95|A<17>|I|I/O|INPUT|||||||||
+P96|TIE||I/O||||||||||
+P97|A<16>|I|I/O|INPUT|||||||||
+P98|BERR|I|I/O|INPUT|||||||||
+P99|GND||GND||||||||||
+P100|TIE||I/O||||||||||
+P101|TIE||I/O||||||||||
+P102|C3|I|I/O|INPUT|||||||||
+P103|C1|I|I/O|INPUT|||||||||
+P104|TIE||I/O||||||||||
+P105|TIE||I/O||||||||||
+P106|TIE||I/O||||||||||
+P107|TIE||I/O||||||||||
+P108|GND||GND||||||||||
+P109|VCC||VCCIO||||||||||
+P110|TIE||I/O||||||||||
+P111|TIE||I/O||||||||||
+P112|TIE||I/O||||||||||
+P113|TIE||I/O||||||||||
+P114|GND||GND||||||||||
+P115|TIE||I/O||||||||||
+P116|TIE||I/O||||||||||
+P117|TIE||I/O||||||||||
+P118|TIE||I/O||||||||||
+P119|TIE||I/O||||||||||
+P120|TIE||I/O||||||||||
+P121|TIE||I/O||||||||||
+P122|TDO||TDO||||||||||
+P123|GND||GND||||||||||
+P124|TIE||I/O||||||||||
+P125|TIE||I/O||||||||||
+P126|TIE||I/O||||||||||
+P127|VCC||VCCIO||||||||||
+P128|TIE||I/O||||||||||
+P129|TIE||I/O||||||||||
+P130|TIE||I/O||||||||||
+P131|TIE||I/O||||||||||
+P132|TIE||I/O||||||||||
+P133|TIE||I/O||||||||||
+P134|TIE||I/O||||||||||
+P135|TIE||I/O||||||||||
+P136|TIE||I/O||||||||||
+P137|TIE||I/O||||||||||
+P138|TIE||I/O||||||||||
+P139|TIE||I/O||||||||||
+P140|TIE||I/O||||||||||
+P141|VCC||VCCINT||||||||||
+P142|TIE||I/O||||||||||
+P143|RESET|GSR/I|I/O/GSR||||||||||
+P144|GND||GND||||||||||
+
+To preserve the pinout above for future design iterations in
+Project Navigator simply execute the (Lock Pins) process
+located under the (Implement Design) process in a toolbox named
+(Optional Implementation Tools) or invoke PIN2UCF from the
+command line. The location constraints will be written into your
+specified UCF file
+
+
diff --git a/Logic/LAN_IDE/LAN_IDE_CP.pnx b/Logic/LAN_IDE/LAN_IDE_CP.pnx
new file mode 100644
index 0000000..08cda4f
--- /dev/null
+++ b/Logic/LAN_IDE/LAN_IDE_CP.pnx
@@ -0,0 +1,18 @@
+<?xml version='1.0' encoding='utf-8' ?>
+<!DOCTYPE ibis [
+<!ELEMENT ibis (part, pin+)>
+<!ELEMENT part EMPTY>
+<!ELEMENT pin EMPTY>
+<!ATTLIST part
+  arch   CDATA #REQUIRED
+  device CDATA #REQUIRED
+  spg    CDATA #REQUIRED
+  pkg    CDATA #REQUIRED>
+<!ATTLIST pin
+  nm     CDATA #REQUIRED
+  no     CDATA #REQUIRED
+  iostd  (TTL|LVTTL|LVCMOS2|NA) "NA"
+  sr     (SLOW|FAST|slow|fast) "SLOW"
+  dir    (BIDIR|bidir|INPUT|input|OUTPUT|output) "BIDIR">
+]>
+<ibis><part arch="xc9500xl" device="XC95144XL" pkg="TQ144" spg="-10"/><pin dir="input" nm="RESET" no="143"/><pin dir="input" nm="RW" no="83"/><pin dir="input" nm="A&lt;1&gt;" no="57"/><pin dir="input" nm="A&lt;2&gt;" no="54"/><pin dir="input" nm="A&lt;5&gt;" no="49"/><pin dir="input" nm="A&lt;6&gt;" no="51"/><pin dir="input" nm="A&lt;3&gt;" no="52"/><pin dir="input" nm="AS" no="80"/><pin dir="input" nm="A&lt;4&gt;" no="50"/><pin dir="input" nm="AUTOBOOT_OFF" no="75"/><pin dir="input" nm="UDS" no="81"/><pin dir="input" nm="A&lt;23&gt;" no="86"/><pin dir="input" nm="A&lt;22&gt;" no="87"/><pin dir="input" nm="A&lt;21&gt;" no="88"/><pin dir="input" nm="A&lt;19&gt;" no="92"/><pin dir="input" nm="BERR" no="98"/><pin dir="input" nm="C1" no="103"/><pin dir="input" nm="C3" no="102"/><pin dir="input" nm="A&lt;16&gt;" no="97"/><pin dir="input" nm="A&lt;20&gt;" no="91"/><pin dir="input" nm="A&lt;17&gt;" no="95"/><pin dir="input" nm="A&lt;18&gt;" no="94"/><pin dir="input" nm="A&lt;9&gt;" no="58"/><pin dir="input" nm="A&lt;10&gt;" no="59"/><pin dir="input" nm="A&lt;11&gt;" no="60"/><pin dir="input" nm="A&lt;12&gt;" no="61"/><pin dir="input" nm="A&lt;13&gt;" no="64"/><pin dir="output" nm="IDE_R" no="27" sr="fast"/><pin dir="output" nm="IDE_W" no="28" sr="fast"/><pin dir="output" nm="ROM_OE" no="35" sr="fast"/><pin dir="output" nm="D&lt;7&gt;" no="16" sr="fast"/><pin dir="output" nm="D&lt;0&gt;" no="2" sr="fast"/><pin dir="output" nm="D&lt;6&gt;" no="14" sr="fast"/><pin dir="output" nm="D&lt;5&gt;" no="20" sr="fast"/><pin dir="output" nm="D&lt;4&gt;" no="21" sr="fast"/><pin dir="output" nm="D&lt;3&gt;" no="15" sr="fast"/><pin dir="output" nm="D&lt;2&gt;" no="39" sr="fast"/><pin dir="output" nm="D&lt;1&gt;" no="17" sr="fast"/><pin dir="output" nm="IDE_A&lt;0&gt;" no="24" sr="fast"/><pin dir="output" nm="IDE_A&lt;1&gt;" no="26" sr="fast"/><pin dir="output" nm="IDE_A&lt;2&gt;" no="25" sr="fast"/><pin dir="output" nm="IDE_CS&lt;0&gt;" no="22" sr="fast"/><pin dir="output" nm="IDE_CS&lt;1&gt;" no="23" sr="fast"/><pin dir="output" nm="DTACK" no="85" sr="fast"/><pin dir="output" nm="ROM_B&lt;1&gt;" no="69" sr="fast"/><pin dir="output" nm="ROM_B&lt;0&gt;" no="68" sr="fast"/><pin dir="bidir" nm="D&lt;13&gt;" no="45" sr="fast"/><pin dir="bidir" nm="D&lt;12&gt;" no="44" sr="fast"/><pin dir="bidir" nm="D&lt;14&gt;" no="46" sr="fast"/><pin dir="bidir" nm="D&lt;15&gt;" no="48" sr="fast"/><pin dir="bidir" nm="D&lt;9&gt;" no="40" sr="fast"/><pin dir="bidir" nm="D&lt;8&gt;" no="19" sr="fast"/><pin dir="bidir" nm="D&lt;11&gt;" no="43" sr="fast"/><pin dir="bidir" nm="D&lt;10&gt;" no="41" sr="fast"/></ibis>
diff --git a/Logic/LAN_IDE/LAN_IDE_CP.prj b/Logic/LAN_IDE/LAN_IDE_CP.prj
new file mode 100644
index 0000000..3370765
--- /dev/null
+++ b/Logic/LAN_IDE/LAN_IDE_CP.prj
@@ -0,0 +1 @@
+vhdl work "LAN_IDE_CP.vhd"
diff --git a/Logic/LAN_IDE/LAN_IDE_CP.rpt b/Logic/LAN_IDE/LAN_IDE_CP.rpt
new file mode 100644
index 0000000..159d140
--- /dev/null
+++ b/Logic/LAN_IDE/LAN_IDE_CP.rpt
@@ -0,0 +1,1167 @@
+ 
+cpldfit:  version P.68d                             Xilinx Inc.
+                                  Fitter Report
+Design Name: LAN_IDE_CP                          Date: 12-15-2016,  7:48PM
+Device Used: XC95144XL-10-TQ144
+Fitting Status: Successful
+
+*************************  Mapped Resource Summary  **************************
+
+Macrocells     Product Terms    Function Block   Registers      Pins           
+Used/Tot       Used/Tot         Inps Used/Tot    Used/Tot       Used/Tot       
+51 /144 ( 35%) 179 /720  ( 25%) 134/432 ( 31%)   26 /144 ( 18%) 54 /117 ( 46%)
+
+** Function Block Resources **
+
+Function    Mcells      FB Inps     Pterms      IO          
+Block       Used/Tot    Used/Tot    Used/Tot    Used/Tot    
+FB1          16/18       24/54       40/90      13/15
+FB2          11/18       24/54       56/90       4/15
+FB3          12/18       24/54       25/90      11/15
+FB4           3/18       24/54       25/90       0/15
+FB5           7/18       23/54       19/90      10/14
+FB6           1/18       15/54       14/90       0/13
+FB7           1/18        0/54        0/90       8/15
+FB8           0/18        0/54        0/90       8/15
+             -----       -----       -----      -----    
+             51/144     134/432     179/720     54/117
+
+* - Resource is exhausted
+
+** Global Control Resources **
+
+Global clock net(s) unused.
+Global output enable net(s) unused.
+Signal 'RESET' mapped onto global set/reset net GSR.
+
+** Pin Resources **
+
+Signal Type    Required     Mapped  |  Pin Type            Used    Total 
+------------------------------------|------------------------------------
+Input         :   26          26    |  I/O              :    52     109
+Output        :   19          19    |  GCK/IO           :     0       3
+Bidirectional :    8           8    |  GTS/IO           :     1       4
+GCK           :    0           0    |  GSR/IO           :     1       1
+GTS           :    0           0    |
+GSR           :    1           1    |
+                 ----        ----
+        Total     54          54
+
+** Power Data **
+
+There are 51 macrocells in high performance mode (MCHP).
+There are 0 macrocells in low power mode (MCLP).
+End of Mapped Resource Summary
+**************************  Errors and Warnings  ***************************
+
+WARNING:Cpld - Unable to retrieve the path to the iSE Project Repository. Will
+   use the default filename of 'LAN_IDE_CP.ise'.
+INFO:Cpld - Inferring BUFG constraint for signal 'CLK_EXT' based upon the LOC
+   constraint 'P30'. It is recommended that you declare this BUFG explicitedly
+   in your design. Note that for certain device families the output of a BUFG
+   constraint can not drive a gated clock, and the BUFG constraint will be
+   ignored.
+WARNING:Cpld:936 - The output buffer 'SLAVE_OBUF' is missing an input and will
+   be deleted.
+WARNING:Cpld:936 - The output buffer 'OWN_OBUF' is missing an input and will be
+   deleted.
+WARNING:Cpld:936 - The output buffer 'OVR_OBUF' is missing an input and will be
+   deleted.
+WARNING:Cpld:936 - The output buffer 'MTACK_OBUF' is missing an input and will
+   be deleted.
+WARNING:Cpld:936 - The output buffer 'LAN_WRH_OBUF' is missing an input and will
+   be deleted.
+WARNING:Cpld:936 - The output buffer 'LAN_RD_OBUF' is missing an input and will
+   be deleted.
+WARNING:Cpld:936 - The output buffer 'LAN_EN_OBUF' is missing an input and will
+   be deleted.
+WARNING:Cpld:936 - The output buffer 'LAN_CS_OBUF' is missing an input and will
+   be deleted.
+WARNING:Cpld:936 - The output buffer 'LAN_CFG<4>_OBUF' is missing an input and
+   will be deleted.
+WARNING:Cpld:936 - The output buffer 'LAN_CFG<3>_OBUF' is missing an input and
+   will be deleted.
+WARNING:Cpld:936 - The output buffer 'LAN_CFG<2>_OBUF' is missing an input and
+   will be deleted.
+WARNING:Cpld:936 - The output buffer 'LAN_CFG<1>_OBUF' is missing an input and
+   will be deleted.
+WARNING:Cpld:936 - The output buffer 'INT_OUT_OBUF' is missing an input and will
+   be deleted.
+WARNING:Cpld:936 - The output buffer 'CP_WE_OBUF' is missing an input and will
+   be deleted.
+WARNING:Cpld:936 - The output buffer 'CP_RD_OBUF' is missing an input and will
+   be deleted.
+WARNING:Cpld:936 - The output buffer 'CP_CS_OBUF' is missing an input and will
+   be deleted.
+WARNING:Cpld:936 - The output buffer 'CFOUT_OBUF' is missing an input and will
+   be deleted.
+WARNING:Cpld:936 - The output buffer 'A_LAN<9>_OBUF' is missing an input and
+   will be deleted.
+WARNING:Cpld:936 - The output buffer 'A_LAN<8>_OBUF' is missing an input and
+   will be deleted.
+WARNING:Cpld:936 - The output buffer 'A_LAN<7>_OBUF' is missing an input and
+   will be deleted.
+WARNING:Cpld:936 - The output buffer 'A_LAN<6>_OBUF' is missing an input and
+   will be deleted.
+WARNING:Cpld:936 - The output buffer 'A_LAN<5>_OBUF' is missing an input and
+   will be deleted.
+WARNING:Cpld:936 - The output buffer 'A_LAN<4>_OBUF' is missing an input and
+   will be deleted.
+WARNING:Cpld:936 - The output buffer 'A_LAN<3>_OBUF' is missing an input and
+   will be deleted.
+WARNING:Cpld:936 - The output buffer 'A_LAN<2>_OBUF' is missing an input and
+   will be deleted.
+WARNING:Cpld:936 - The output buffer 'A_LAN<1>_OBUF' is missing an input and
+   will be deleted.
+WARNING:Cpld:936 - The output buffer 'A_LAN<13>_OBUF' is missing an input and
+   will be deleted.
+WARNING:Cpld:936 - The output buffer 'A_LAN<12>_OBUF' is missing an input and
+   will be deleted.
+WARNING:Cpld:936 - The output buffer 'A_LAN<11>_OBUF' is missing an input and
+   will be deleted.
+WARNING:Cpld:936 - The output buffer 'A_LAN<10>_OBUF' is missing an input and
+   will be deleted.
+WARNING:Cpld:936 - The output buffer 'A_LAN<0>_OBUF' is missing an input and
+   will be deleted.
+WARNING:Cpld:1007 - Removing unused input(s) 'A<14>'.  The input(s) are unused
+   after optimization. Please verify functionality via simulation.
+WARNING:Cpld:1007 - Removing unused input(s) 'A<15>'.  The input(s) are unused
+   after optimization. Please verify functionality via simulation.
+WARNING:Cpld:1007 - Removing unused input(s) 'A<7>'.  The input(s) are unused
+   after optimization. Please verify functionality via simulation.
+WARNING:Cpld:1007 - Removing unused input(s) 'A<8>'.  The input(s) are unused
+   after optimization. Please verify functionality via simulation.
+WARNING:Cpld:1007 - Removing unused input(s) 'CFIN'.  The input(s) are unused
+   after optimization. Please verify functionality via simulation.
+WARNING:Cpld:1007 - Removing unused input(s) 'CLK_EXT'.  The input(s) are unused
+   after optimization. Please verify functionality via simulation.
+WARNING:Cpld:1007 - Removing unused input(s) 'CP_IRQ'.  The input(s) are unused
+   after optimization. Please verify functionality via simulation.
+WARNING:Cpld:1007 - Removing unused input(s) 'DQ<0>'.  The input(s) are unused
+   after optimization. Please verify functionality via simulation.
+WARNING:Cpld:1007 - Removing unused input(s) 'DQ<10>'.  The input(s) are unused
+   after optimization. Please verify functionality via simulation.
+WARNING:Cpld:1007 - Removing unused input(s) 'DQ<11>'.  The input(s) are unused
+   after optimization. Please verify functionality via simulation.
+WARNING:Cpld:1007 - Removing unused input(s) 'DQ<12>'.  The input(s) are unused
+   after optimization. Please verify functionality via simulation.
+WARNING:Cpld:1007 - Removing unused input(s) 'DQ<13>'.  The input(s) are unused
+   after optimization. Please verify functionality via simulation.
+WARNING:Cpld:1007 - Removing unused input(s) 'DQ<14>'.  The input(s) are unused
+   after optimization. Please verify functionality via simulation.
+WARNING:Cpld:1007 - Removing unused input(s) 'DQ<15>'.  The input(s) are unused
+   after optimization. Please verify functionality via simulation.
+WARNING:Cpld:1007 - Removing unused input(s) 'DQ<1>'.  The input(s) are unused
+   after optimization. Please verify functionality via simulation.
+WARNING:Cpld:1007 - Removing unused input(s) 'DQ<2>'.  The input(s) are unused
+   after optimization. Please verify functionality via simulation.
+WARNING:Cpld:1007 - Removing unused input(s) 'DQ<3>'.  The input(s) are unused
+   after optimization. Please verify functionality via simulation.
+WARNING:Cpld:1007 - Removing unused input(s) 'DQ<4>'.  The input(s) are unused
+   after optimization. Please verify functionality via simulation.
+WARNING:Cpld:1007 - Removing unused input(s) 'DQ<5>'.  The input(s) are unused
+   after optimization. Please verify functionality via simulation.
+WARNING:Cpld:1007 - Removing unused input(s) 'DQ<6>'.  The input(s) are unused
+   after optimization. Please verify functionality via simulation.
+WARNING:Cpld:1007 - Removing unused input(s) 'DQ<7>'.  The input(s) are unused
+   after optimization. Please verify functionality via simulation.
+WARNING:Cpld:1007 - Removing unused input(s) 'DQ<8>'.  The input(s) are unused
+   after optimization. Please verify functionality via simulation.
+WARNING:Cpld:1007 - Removing unused input(s) 'DQ<9>'.  The input(s) are unused
+   after optimization. Please verify functionality via simulation.
+WARNING:Cpld:1007 - Removing unused input(s) 'DS0'.  The input(s) are unused
+   after optimization. Please verify functionality via simulation.
+WARNING:Cpld:1007 - Removing unused input(s) 'DS1'.  The input(s) are unused
+   after optimization. Please verify functionality via simulation.
+WARNING:Cpld:1007 - Removing unused input(s) 'FCS'.  The input(s) are unused
+   after optimization. Please verify functionality via simulation.
+WARNING:Cpld:1007 - Removing unused input(s) 'IDE_WAIT'.  The input(s) are
+   unused after optimization. Please verify functionality via simulation.
+WARNING:Cpld:1007 - Removing unused input(s) 'LAN_INT'.  The input(s) are unused
+   after optimization. Please verify functionality via simulation.
+WARNING:Cpld:1007 - Removing unused input(s) 'LDS'.  The input(s) are unused
+   after optimization. Please verify functionality via simulation.
+WARNING:Cpld:1007 - Removing unused input(s) 'MTCR'.  The input(s) are unused
+   after optimization. Please verify functionality via simulation.
+WARNING:Cpld:1007 - Removing unused input(s) 'Z3'.  The input(s) are unused
+   after optimization. Please verify functionality via simulation.
+WARNING:Cpld:896 - Unable to map all desired signals into function block, FB3,
+   because too many function block product terms are required. Buffering output
+   signal D<12> to allow all signals assigned to this function block to be
+   placed.
+WARNING:Cpld:896 - Unable to map all desired signals into function block, FB3,
+   because too many function block product terms are required. Buffering output
+   signal D<14> to allow all signals assigned to this function block to be
+   placed.
+WARNING:Cpld:896 - Unable to map all desired signals into function block, FB3,
+   because too many function block product terms are required. Buffering output
+   signal D<13> to allow all signals assigned to this function block to be
+   placed.
+WARNING:Cpld:896 - Unable to map all desired signals into function block, FB3,
+   because too many function block product terms are required. Buffering output
+   signal D<15> to allow all signals assigned to this function block to be
+   placed.
+*************************  Summary of Mapped Logic  ************************
+
+** 27 Outputs **
+
+Signal                     Total Total Loc     Pin  Pin     Pin     Pwr  Slew Reg Init
+Name                       Pts   Inps          No.  Type    Use     Mode Rate State
+IDE_CS<1>                  1     1     FB1_1   23   I/O     O       STD  FAST 
+D<7>                       1     2     FB1_2   16   I/O     O       STD  FAST 
+D<1>                       1     2     FB1_3   17   I/O     O       STD  FAST 
+IDE_A<2>                   1     1     FB1_4   25   I/O     O       STD  FAST 
+D<8>                       1     2     FB1_5   19   I/O     I/O     STD  FAST 
+D<5>                       1     2     FB1_6   20   I/O     O       STD  FAST 
+D<4>                       1     2     FB1_8   21   I/O     O       STD  FAST 
+IDE_CS<0>                  1     1     FB1_9   22   I/O     O       STD  FAST 
+IDE_A<0>                   1     1     FB1_11  24   I/O     O       STD  FAST 
+IDE_A<1>                   1     1     FB1_12  26   I/O     O       STD  FAST 
+IDE_R                      2     6     FB1_14  27   I/O     O       STD  FAST SET
+IDE_W                      2     5     FB1_15  28   I/O     O       STD  FAST SET
+ROM_OE                     2     6     FB1_16  35   I/O     O       STD  FAST SET
+D<0>                       1     2     FB2_5   2    GTS/I/O O       STD  FAST 
+D<6>                       1     2     FB2_16  14   I/O     O       STD  FAST 
+D<3>                       1     2     FB2_17  15   I/O     O       STD  FAST 
+D<2>                       1     2     FB3_1   39   I/O     O       STD  FAST 
+D<10>                      1     2     FB3_3   41   I/O     I/O     STD  FAST 
+D<12>                      2     3     FB3_4   44   I/O     I/O     STD  FAST 
+D<14>                      2     3     FB3_7   46   I/O     I/O     STD  FAST 
+D<9>                       1     2     FB3_9   40   I/O     I/O     STD  FAST 
+D<15>                      2     3     FB3_10  48   I/O     I/O     STD  FAST 
+D<11>                      1     2     FB3_11  43   I/O     I/O     STD  FAST 
+D<13>                      2     3     FB3_12  45   I/O     I/O     STD  FAST 
+ROM_B<0>                   0     0     FB5_10  68   I/O     O       STD  FAST 
+ROM_B<1>                   0     0     FB5_17  69   I/O     O       STD  FAST 
+DTACK                      0     0     FB7_12  85   I/O     O       STD  FAST 
+
+** 24 Buried Nodes **
+
+Signal                     Total Total Loc     Pwr  Reg Init
+Name                       Pts   Inps          Mode State
+AUTOCONFIG_IN_PROGRESS     2     3     FB1_7   STD  RESET
+IDE_ENABLE                 3     6     FB1_10  STD  RESET
+D<12>_BUFR                 19    16    FB1_18  STD  RESET
+D<14>_BUFR                 18    15    FB2_1   STD  RESET
+AUTO_CONFIG_DONE<2>        2     2     FB2_8   STD  RESET
+AUTO_CONFIG_DONE<0>        2     2     FB2_9   STD  RESET
+AUTO_CONFIG_DONE_CYCLE<2>  3     15    FB2_10  STD  RESET
+AUTO_CONFIG_DONE_CYCLE<0>  3     13    FB2_11  STD  RESET
+IDE_BASEADR<7>             4     16    FB2_12  STD  RESET
+IDE_BASEADR<6>             4     16    FB2_13  STD  RESET
+D<13>_BUFR                 17    15    FB2_15  STD  RESET
+AUTO_CONFIG_DONE<1>        2     2     FB3_15  STD  RESET
+AUTO_CONFIG_DONE_CYCLE<1>  3     14    FB3_16  STD  RESET
+IDE_BASEADR<3>             4     16    FB3_17  STD  RESET
+IDE_BASEADR<2>             4     16    FB3_18  STD  RESET
+ide                        19    19    FB4_1   STD  RESET
+ide/ide_CLKF               2     2     FB4_16  STD  
+autoconfig                 4     13    FB4_17  STD  RESET
+SHUT_UP<1>                 3     15    FB5_13  STD  RESET
+IDE_BASEADR<5>             4     16    FB5_14  STD  RESET
+IDE_BASEADR<4>             4     16    FB5_15  STD  RESET
+IDE_BASEADR<1>             4     16    FB5_16  STD  RESET
+IDE_BASEADR<0>             4     16    FB5_18  STD  RESET
+D<15>_BUFR                 14    15    FB6_17  STD  RESET
+
+** 27 Inputs **
+
+Signal                     Loc     Pin  Pin     Pin     
+Name                               No.  Type    Use     
+RESET                      FB2_2   143  GSR/I/O GSR/I
+A<5>                       FB3_14  49   I/O     I
+A<4>                       FB3_15  50   I/O     I
+A<6>                       FB3_17  51   I/O     I
+A<3>                       FB5_2   52   I/O     I
+A<10>                      FB5_3   59   I/O     I
+A<2>                       FB5_6   54   I/O     I
+A<1>                       FB5_9   57   I/O     I
+A<9>                       FB5_11  58   I/O     I
+A<11>                      FB5_12  60   I/O     I
+A<12>                      FB5_14  61   I/O     I
+A<13>                      FB5_15  64   I/O     I
+AUTOBOOT_OFF               FB7_3   75   I/O     I
+AS                         FB7_9   80   I/O     I
+UDS                        FB7_13  81   I/O     I
+A<23>                      FB7_14  86   I/O     I
+A<22>                      FB7_15  87   I/O     I
+RW                         FB7_16  83   I/O     I
+A<21>                      FB7_17  88   I/O     I
+A<20>                      FB8_2   91   I/O     I
+A<17>                      FB8_3   95   I/O     I
+A<16>                      FB8_4   97   I/O     I
+A<19>                      FB8_5   92   I/O     I
+A<18>                      FB8_8   94   I/O     I
+BERR                       FB8_11  98   I/O     I
+C1                         FB8_13  103  I/O     I
+C3                         FB8_14  102  I/O     I
+
+Legend:
+Pin No. - ~ - User Assigned
+**************************  Function Block Details  ************************
+Legend:
+Total Pt     - Total product terms used by the macrocell signal
+Imp Pt       - Product terms imported from other macrocells
+Exp Pt       - Product terms exported to other macrocells
+               in direction shown
+Unused Pt    - Unused local product terms remaining in macrocell
+Loc          - Location where logic was mapped in device
+Pin Type/Use - I  - Input             GCK - Global Clock
+               O  - Output            GTS - Global Output Enable
+              (b) - Buried macrocell  GSR - Global Set/Reset
+X            - Signal used as input to the macrocell logic.
+Pin No.      - ~  - User Assigned
+*********************************** FB1  ***********************************
+Number of function block inputs used/remaining:               24/30
+Number of signals used by logic mapping into function block:  24
+Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
+Name                Pt      Pt    Pt  Pt               #    Type    Use
+IDE_CS<1>             1       1<- /\5   0     FB1_1   23    I/O     O
+D<7>                  1       0   /\1   3     FB1_2   16    I/O     O
+D<1>                  1       0     0   4     FB1_3   17    I/O     O
+IDE_A<2>              1       0     0   4     FB1_4   25    I/O     O
+D<8>                  1       0     0   4     FB1_5   19    I/O     I/O
+D<5>                  1       0     0   4     FB1_6   20    I/O     O
+AUTOCONFIG_IN_PROGRESS
+                      2       0     0   3     FB1_7         (b)     (b)
+D<4>                  1       0     0   4     FB1_8   21    I/O     O
+IDE_CS<0>             1       0     0   4     FB1_9   22    I/O     O
+IDE_ENABLE            3       0     0   2     FB1_10  31    I/O     (b)
+IDE_A<0>              1       0     0   4     FB1_11  24    I/O     O
+IDE_A<1>              1       0     0   4     FB1_12  26    I/O     O
+(unused)              0       0     0   5     FB1_13        (b)     
+IDE_R                 2       0     0   3     FB1_14  27    I/O     O
+IDE_W                 2       0   \/1   2     FB1_15  28    I/O     O
+ROM_OE                2       1<- \/4   0     FB1_16  35    I/O     O
+(unused)              0       0   \/5   0     FB1_17  30    GCK/I/O (b)
+D<12>_BUFR           19      14<-   0   0     FB1_18        (b)     (b)
+
+Signals Used by Logic in Function Block
+  1: AS                       9: A<1>              17: A<10> 
+  2: AUTOBOOT_OFF            10: A<2>              18: A<11> 
+  3: AUTOCONFIG_IN_PROGRESS  11: A<3>              19: IDE_ENABLE 
+  4: AUTO_CONFIG_DONE<0>     12: A<4>              20: RESET 
+  5: AUTO_CONFIG_DONE<1>     13: A<5>              21: RW 
+  6: AUTO_CONFIG_DONE<2>     14: A<6>              22: autoconfig 
+  7: A<12>                   15: D<12>             23: ide 
+  8: A<13>                   16: A<9>              24: ide/ide_CLKF 
+
+Signal                        1         2         3         4 FB
+Name                0----+----0----+----0----+----0----+----0 Inputs
+IDE_CS<1>            .......X................................ 1
+D<7>                 ..X.................X................... 2
+D<1>                 ..X.................X................... 2
+IDE_A<2>             .................X...................... 1
+D<8>                 ..X.................X................... 2
+D<5>                 ..X.................X................... 2
+AUTOCONFIG_IN_PROGRESS 
+                     X....................X.X................ 3
+D<4>                 ..X.................X................... 2
+IDE_CS<0>            ......X................................. 1
+IDE_ENABLE           X.................XXX.XX................ 6
+IDE_A<0>             ...............X........................ 1
+IDE_A<1>             ................X....................... 1
+IDE_R                X.................XXX.XX................ 6
+IDE_W                X..................XX.XX................ 5
+ROM_OE               X.................XXX.XX................ 6
+D<12>_BUFR           XX.XXX..XXXXXXX....XXX.X................ 16
+                    0----+----1----+----2----+----3----+----4
+                              0         0         0         0
+*********************************** FB2  ***********************************
+Number of function block inputs used/remaining:               24/30
+Number of signals used by logic mapping into function block:  24
+Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
+Name                Pt      Pt    Pt  Pt               #    Type    Use
+D<14>_BUFR           18      13<-   0   0     FB2_1   142   I/O     (b)
+(unused)              0       0   /\5   0     FB2_2   143   GSR/I/O GSR/I
+(unused)              0       0   /\3   2     FB2_3         (b)     (b)
+(unused)              0       0     0   5     FB2_4   4     I/O     
+D<0>                  1       0     0   4     FB2_5   2     GTS/I/O O
+(unused)              0       0     0   5     FB2_6   3     GTS/I/O 
+(unused)              0       0     0   5     FB2_7         (b)     
+AUTO_CONFIG_DONE<2>   2       0     0   3     FB2_8   5     GTS/I/O (b)
+AUTO_CONFIG_DONE<0>   2       0     0   3     FB2_9   6     GTS/I/O (b)
+AUTO_CONFIG_DONE_CYCLE<2>
+                      3       0     0   2     FB2_10  7     I/O     (b)
+AUTO_CONFIG_DONE_CYCLE<0>
+                      3       0   \/1   1     FB2_11  9     I/O     (b)
+IDE_BASEADR<7>        4       1<- \/2   0     FB2_12  10    I/O     (b)
+IDE_BASEADR<6>        4       2<- \/3   0     FB2_13  12    I/O     (b)
+(unused)              0       0   \/5   0     FB2_14  11    I/O     (b)
+D<13>_BUFR           17      12<-   0   0     FB2_15  13    I/O     (b)
+D<6>                  1       0   /\4   0     FB2_16  14    I/O     O
+D<3>                  1       0     0   4     FB2_17  15    I/O     O
+(unused)              0       0   \/5   0     FB2_18        (b)     (b)
+
+Signals Used by Logic in Function Block
+  1: AS                          9: A<2>              17: IDE_BASEADR<7> 
+  2: AUTOCONFIG_IN_PROGRESS     10: A<3>              18: D<14>.PIN 
+  3: AUTO_CONFIG_DONE<0>        11: A<4>              19: D<15>.PIN 
+  4: AUTO_CONFIG_DONE<1>        12: A<5>              20: RESET 
+  5: AUTO_CONFIG_DONE<2>        13: A<6>              21: RW 
+  6: AUTO_CONFIG_DONE_CYCLE<0>  14: D<13>             22: UDS 
+  7: AUTO_CONFIG_DONE_CYCLE<2>  15: D<14>             23: autoconfig 
+  8: A<1>                       16: IDE_BASEADR<6>    24: ide/ide_CLKF 
+
+Signal                        1         2         3         4 FB
+Name                0----+----0----+----0----+----0----+----0 Inputs
+D<14>_BUFR           X.XXX..XXXXXX.X....XX.XX................ 15
+D<0>                 .X..................X................... 2
+AUTO_CONFIG_DONE<2>  X.....X................................. 2
+AUTO_CONFIG_DONE<0>  X....X.................................. 2
+AUTO_CONFIG_DONE_CYCLE<2> 
+                     X.XXX.XX.XXXX......XXXXX................ 15
+AUTO_CONFIG_DONE_CYCLE<0> 
+                     X.X..X.X.XXXX......XXXXX................ 13
+IDE_BASEADR<7>       X.XX...XXXXXX...X.XXXXXX................ 16
+IDE_BASEADR<6>       X.XX...XXXXXX..X.X.XXXXX................ 16
+D<13>_BUFR           X.XXX..XXXXXXX.....XX.XX................ 15
+D<6>                 .X..................X................... 2
+D<3>                 .X..................X................... 2
+                    0----+----1----+----2----+----3----+----4
+                              0         0         0         0
+*********************************** FB3  ***********************************
+Number of function block inputs used/remaining:               24/30
+Number of signals used by logic mapping into function block:  24
+Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
+Name                Pt      Pt    Pt  Pt               #    Type    Use
+D<2>                  1       0     0   4     FB3_1   39    I/O     O
+(unused)              0       0     0   5     FB3_2   32    GCK/I/O 
+D<10>                 1       0     0   4     FB3_3   41    I/O     I/O
+D<12>                 2       0     0   3     FB3_4   44    I/O     I/O
+(unused)              0       0     0   5     FB3_5   33    I/O     
+(unused)              0       0     0   5     FB3_6   34    I/O     
+D<14>                 2       0     0   3     FB3_7   46    I/O     I/O
+(unused)              0       0     0   5     FB3_8   38    GCK/I/O 
+D<9>                  1       0     0   4     FB3_9   40    I/O     I/O
+D<15>                 2       0     0   3     FB3_10  48    I/O     I/O
+D<11>                 1       0     0   4     FB3_11  43    I/O     I/O
+D<13>                 2       0     0   3     FB3_12  45    I/O     I/O
+(unused)              0       0     0   5     FB3_13        (b)     
+(unused)              0       0     0   5     FB3_14  49    I/O     I
+AUTO_CONFIG_DONE<1>   2       0     0   3     FB3_15  50    I/O     I
+AUTO_CONFIG_DONE_CYCLE<1>
+                      3       0     0   2     FB3_16        (b)     (b)
+IDE_BASEADR<3>        4       0     0   1     FB3_17  51    I/O     I
+IDE_BASEADR<2>        4       0     0   1     FB3_18        (b)     (b)
+
+Signals Used by Logic in Function Block
+  1: AS                          9: A<4>              17: IDE_BASEADR<3> 
+  2: AUTOCONFIG_IN_PROGRESS     10: A<5>              18: D<11>.PIN 
+  3: AUTO_CONFIG_DONE<0>        11: A<6>              19: D<10>.PIN 
+  4: AUTO_CONFIG_DONE<1>        12: D<12>_BUFR        20: RESET 
+  5: AUTO_CONFIG_DONE_CYCLE<1>  13: D<13>_BUFR        21: RW 
+  6: A<1>                       14: D<14>_BUFR        22: UDS 
+  7: A<2>                       15: D<15>_BUFR        23: autoconfig 
+  8: A<3>                       16: IDE_BASEADR<2>    24: ide/ide_CLKF 
+
+Signal                        1         2         3         4 FB
+Name                0----+----0----+----0----+----0----+----0 Inputs
+D<2>                 .X..................X................... 2
+D<10>                .X..................X................... 2
+D<12>                .X.........X........X................... 3
+D<14>                .X...........X......X................... 3
+D<9>                 .X..................X................... 2
+D<15>                .X............X.....X................... 3
+D<11>                .X..................X................... 2
+D<13>                .X..........X.......X................... 3
+AUTO_CONFIG_DONE<1>  X...X................................... 2
+AUTO_CONFIG_DONE_CYCLE<1> 
+                     X.XXXX.XXXX........XXXXX................ 14
+IDE_BASEADR<3>       X.XX.XXXXXX.....XX.XXXXX................ 16
+IDE_BASEADR<2>       X.XX.XXXXXX....X..XXXXXX................ 16
+                    0----+----1----+----2----+----3----+----4
+                              0         0         0         0
+*********************************** FB4  ***********************************
+Number of function block inputs used/remaining:               24/30
+Number of signals used by logic mapping into function block:  24
+Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
+Name                Pt      Pt    Pt  Pt               #    Type    Use
+ide                  19      14<-   0   0     FB4_1   118   I/O     (b)
+(unused)              0       0   /\5   0     FB4_2   126   I/O     (b)
+(unused)              0       0   /\3   2     FB4_3   133   I/O     (b)
+(unused)              0       0     0   5     FB4_4         (b)     
+(unused)              0       0     0   5     FB4_5   128   I/O     
+(unused)              0       0     0   5     FB4_6   129   I/O     
+(unused)              0       0     0   5     FB4_7         (b)     
+(unused)              0       0     0   5     FB4_8   130   I/O     
+(unused)              0       0     0   5     FB4_9   131   I/O     
+(unused)              0       0     0   5     FB4_10  135   I/O     
+(unused)              0       0     0   5     FB4_11  132   I/O     
+(unused)              0       0     0   5     FB4_12  134   I/O     
+(unused)              0       0     0   5     FB4_13  137   I/O     
+(unused)              0       0     0   5     FB4_14  136   I/O     
+(unused)              0       0     0   5     FB4_15  138   I/O     
+ide/ide_CLKF          2       0     0   3     FB4_16  139   I/O     (b)
+autoconfig            4       0   \/1   0     FB4_17  140   I/O     (b)
+(unused)              0       0   \/5   0     FB4_18        (b)     (b)
+
+Signals Used by Logic in Function Block
+  1: AUTO_CONFIG_DONE<0>   9: A<21>             17: IDE_BASEADR<2> 
+  2: AUTO_CONFIG_DONE<1>  10: A<22>             18: IDE_BASEADR<3> 
+  3: AUTO_CONFIG_DONE<2>  11: A<23>             19: IDE_BASEADR<4> 
+  4: A<16>                12: BERR              20: IDE_BASEADR<5> 
+  5: A<17>                13: C1                21: IDE_BASEADR<6> 
+  6: A<18>                14: C3                22: IDE_BASEADR<7> 
+  7: A<19>                15: IDE_BASEADR<0>    23: SHUT_UP<1> 
+  8: A<20>                16: IDE_BASEADR<1>    24: ide/ide_CLKF 
+
+Signal                        1         2         3         4 FB
+Name                0----+----0----+----0----+----0----+----0 Inputs
+ide                  ...XXXXXXXXX..XXXXXXXXXX................ 19
+ide/ide_CLKF         ............XX.......................... 2
+autoconfig           XXXXXXXXXXXX...........X................ 13
+                    0----+----1----+----2----+----3----+----4
+                              0         0         0         0
+*********************************** FB5  ***********************************
+Number of function block inputs used/remaining:               23/31
+Number of signals used by logic mapping into function block:  23
+Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
+Name                Pt      Pt    Pt  Pt               #    Type    Use
+(unused)              0       0     0   5     FB5_1         (b)     
+(unused)              0       0     0   5     FB5_2   52    I/O     I
+(unused)              0       0     0   5     FB5_3   59    I/O     I
+(unused)              0       0     0   5     FB5_4         (b)     
+(unused)              0       0     0   5     FB5_5   53    I/O     
+(unused)              0       0     0   5     FB5_6   54    I/O     I
+(unused)              0       0     0   5     FB5_7   66    I/O     
+(unused)              0       0     0   5     FB5_8   56    I/O     
+(unused)              0       0     0   5     FB5_9   57    I/O     I
+ROM_B<0>              0       0     0   5     FB5_10  68    I/O     O
+(unused)              0       0     0   5     FB5_11  58    I/O     I
+(unused)              0       0     0   5     FB5_12  60    I/O     I
+SHUT_UP<1>            3       0     0   2     FB5_13  70    I/O     (b)
+IDE_BASEADR<5>        4       0     0   1     FB5_14  61    I/O     I
+IDE_BASEADR<4>        4       0     0   1     FB5_15  64    I/O     I
+IDE_BASEADR<1>        4       0     0   1     FB5_16        (b)     (b)
+ROM_B<1>              0       0     0   5     FB5_17  69    I/O     O
+IDE_BASEADR<0>        4       0     0   1     FB5_18        (b)     (b)
+
+Signals Used by Logic in Function Block
+  1: AS                    9: A<6>              17: D<9>.PIN 
+  2: AUTO_CONFIG_DONE<0>  10: IDE_BASEADR<0>    18: RESET 
+  3: AUTO_CONFIG_DONE<1>  11: IDE_BASEADR<1>    19: RW 
+  4: A<1>                 12: IDE_BASEADR<4>    20: SHUT_UP<1> 
+  5: A<2>                 13: IDE_BASEADR<5>    21: UDS 
+  6: A<3>                 14: D<12>.PIN         22: autoconfig 
+  7: A<4>                 15: D<13>.PIN         23: ide/ide_CLKF 
+  8: A<5>                 16: D<8>.PIN         
+
+Signal                        1         2         3         4 FB
+Name                0----+----0----+----0----+----0----+----0 Inputs
+ROM_B<0>             ........................................ 0
+SHUT_UP<1>           XXXXXXXXX........XXXXXX................. 15
+IDE_BASEADR<5>       XXXXXXXXX...X.X..XX.XXX................. 16
+IDE_BASEADR<4>       XXXXXXXXX..X.X...XX.XXX................. 16
+IDE_BASEADR<1>       XXXXXXXXX.X.....XXX.XXX................. 16
+ROM_B<1>             ........................................ 0
+IDE_BASEADR<0>       XXXXXXXXXX.....X.XX.XXX................. 16
+                    0----+----1----+----2----+----3----+----4
+                              0         0         0         0
+*********************************** FB6  ***********************************
+Number of function block inputs used/remaining:               15/39
+Number of signals used by logic mapping into function block:  15
+Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
+Name                Pt      Pt    Pt  Pt               #    Type    Use
+(unused)              0       0     0   5     FB6_1         (b)     
+(unused)              0       0     0   5     FB6_2   106   I/O     
+(unused)              0       0     0   5     FB6_3         (b)     
+(unused)              0       0     0   5     FB6_4   111   I/O     
+(unused)              0       0     0   5     FB6_5   110   I/O     
+(unused)              0       0     0   5     FB6_6   112   I/O     
+(unused)              0       0     0   5     FB6_7         (b)     
+(unused)              0       0     0   5     FB6_8   113   I/O     
+(unused)              0       0     0   5     FB6_9   116   I/O     
+(unused)              0       0     0   5     FB6_10  115   I/O     
+(unused)              0       0     0   5     FB6_11  119   I/O     
+(unused)              0       0     0   5     FB6_12  120   I/O     
+(unused)              0       0     0   5     FB6_13        (b)     
+(unused)              0       0     0   5     FB6_14  121   I/O     
+(unused)              0       0     0   5     FB6_15  124   I/O     
+(unused)              0       0   \/4   1     FB6_16  117   I/O     (b)
+D<15>_BUFR           14       9<-   0   0     FB6_17  125   I/O     (b)
+(unused)              0       0   /\5   0     FB6_18        (b)     (b)
+
+Signals Used by Logic in Function Block
+  1: AS                    6: A<2>              11: D<15> 
+  2: AUTO_CONFIG_DONE<0>   7: A<3>              12: RESET 
+  3: AUTO_CONFIG_DONE<1>   8: A<4>              13: RW 
+  4: AUTO_CONFIG_DONE<2>   9: A<5>              14: autoconfig 
+  5: A<1>                 10: A<6>              15: ide/ide_CLKF 
+
+Signal                        1         2         3         4 FB
+Name                0----+----0----+----0----+----0----+----0 Inputs
+D<15>_BUFR           XXXXXXXXXXXXXXX......................... 15
+                    0----+----1----+----2----+----3----+----4
+                              0         0         0         0
+*********************************** FB7  ***********************************
+Number of function block inputs used/remaining:               0/54
+Number of signals used by logic mapping into function block:  0
+Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
+Name                Pt      Pt    Pt  Pt               #    Type    Use
+(unused)              0       0     0   5     FB7_1         (b)     
+(unused)              0       0     0   5     FB7_2   71    I/O     
+(unused)              0       0     0   5     FB7_3   75    I/O     I
+(unused)              0       0     0   5     FB7_4         (b)     
+(unused)              0       0     0   5     FB7_5   74    I/O     
+(unused)              0       0     0   5     FB7_6   76    I/O     
+(unused)              0       0     0   5     FB7_7   77    I/O     
+(unused)              0       0     0   5     FB7_8   78    I/O     
+(unused)              0       0     0   5     FB7_9   80    I/O     I
+(unused)              0       0     0   5     FB7_10  79    I/O     
+(unused)              0       0     0   5     FB7_11  82    I/O     
+DTACK                 0       0     0   5     FB7_12  85    I/O     O
+(unused)              0       0     0   5     FB7_13  81    I/O     I
+(unused)              0       0     0   5     FB7_14  86    I/O     I
+(unused)              0       0     0   5     FB7_15  87    I/O     I
+(unused)              0       0     0   5     FB7_16  83    I/O     I
+(unused)              0       0     0   5     FB7_17  88    I/O     I
+(unused)              0       0     0   5     FB7_18        (b)     
+
+Signals Used by Logic in Function Block
+
+Signal                        1         2         3         4 FB
+Name                0----+----0----+----0----+----0----+----0 Inputs
+DTACK                ........................................ 0
+                    0----+----1----+----2----+----3----+----4
+                              0         0         0         0
+*********************************** FB8  ***********************************
+Number of function block inputs used/remaining:               0/54
+Number of signals used by logic mapping into function block:  0
+Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
+Name                Pt      Pt    Pt  Pt               #    Type    Use
+(unused)              0       0     0   5     FB8_1         (b)     
+(unused)              0       0     0   5     FB8_2   91    I/O     I
+(unused)              0       0     0   5     FB8_3   95    I/O     I
+(unused)              0       0     0   5     FB8_4   97    I/O     I
+(unused)              0       0     0   5     FB8_5   92    I/O     I
+(unused)              0       0     0   5     FB8_6   93    I/O     
+(unused)              0       0     0   5     FB8_7         (b)     
+(unused)              0       0     0   5     FB8_8   94    I/O     I
+(unused)              0       0     0   5     FB8_9   96    I/O     
+(unused)              0       0     0   5     FB8_10  101   I/O     
+(unused)              0       0     0   5     FB8_11  98    I/O     I
+(unused)              0       0     0   5     FB8_12  100   I/O     
+(unused)              0       0     0   5     FB8_13  103   I/O     I
+(unused)              0       0     0   5     FB8_14  102   I/O     I
+(unused)              0       0     0   5     FB8_15  104   I/O     
+(unused)              0       0     0   5     FB8_16  107   I/O     
+(unused)              0       0     0   5     FB8_17  105   I/O     
+(unused)              0       0     0   5     FB8_18        (b)     
+*******************************  Equations  ********************************
+
+********** Mapped Logic **********
+
+FDCPE_AUTOCONFIG_IN_PROGRESS: FDCPE port map (AUTOCONFIG_IN_PROGRESS,AUTOCONFIG_IN_PROGRESS_D,ide/ide_CLKF,'0','0');
+AUTOCONFIG_IN_PROGRESS_D <= (NOT AS AND autoconfig);
+
+FDCPE_AUTO_CONFIG_DONE0: FDCPE port map (AUTO_CONFIG_DONE(0),AUTO_CONFIG_DONE_CYCLE(0),AS,NOT RESET,'0');
+
+FDCPE_AUTO_CONFIG_DONE1: FDCPE port map (AUTO_CONFIG_DONE(1),AUTO_CONFIG_DONE_CYCLE(1),AS,NOT RESET,'0');
+
+FDCPE_AUTO_CONFIG_DONE2: FDCPE port map (AUTO_CONFIG_DONE(2),AUTO_CONFIG_DONE_CYCLE(2),AS,NOT RESET,'0');
+
+FDCPE_AUTO_CONFIG_DONE_CYCLE0: FDCPE port map (AUTO_CONFIG_DONE_CYCLE(0),AUTO_CONFIG_DONE_CYCLE_D(0),ide/ide_CLKF,'0','0');
+AUTO_CONFIG_DONE_CYCLE_D(0) <= ((RESET AND AUTO_CONFIG_DONE_CYCLE(0))
+	OR (RESET AND NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND 
+	A(6) AND A(3) AND NOT AUTO_CONFIG_DONE(0) AND autoconfig));
+
+FDCPE_AUTO_CONFIG_DONE_CYCLE1: FDCPE port map (AUTO_CONFIG_DONE_CYCLE(1),AUTO_CONFIG_DONE_CYCLE_D(1),ide/ide_CLKF,'0','0');
+AUTO_CONFIG_DONE_CYCLE_D(1) <= ((RESET AND AUTO_CONFIG_DONE_CYCLE(1))
+	OR (RESET AND NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND 
+	A(6) AND A(3) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND 
+	autoconfig));
+
+FDCPE_AUTO_CONFIG_DONE_CYCLE2: FDCPE port map (AUTO_CONFIG_DONE_CYCLE(2),AUTO_CONFIG_DONE_CYCLE_D(2),ide/ide_CLKF,'0','0');
+AUTO_CONFIG_DONE_CYCLE_D(2) <= ((RESET AND AUTO_CONFIG_DONE_CYCLE(2))
+	OR (RESET AND NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND 
+	A(6) AND A(3) AND AUTO_CONFIG_DONE(0) AND AUTO_CONFIG_DONE(1) AND 
+	NOT AUTO_CONFIG_DONE(2) AND autoconfig));
+
+
+D_I(0) <= '1';
+D(0) <= D_I(0) when D_OE(0) = '1' else 'Z';
+D_OE(0) <= (RW AND AUTOCONFIG_IN_PROGRESS);
+
+
+D_I(1) <= '1';
+D(1) <= D_I(1) when D_OE(1) = '1' else 'Z';
+D_OE(1) <= (RW AND AUTOCONFIG_IN_PROGRESS);
+
+
+D_I(2) <= '1';
+D(2) <= D_I(2) when D_OE(2) = '1' else 'Z';
+D_OE(2) <= (RW AND AUTOCONFIG_IN_PROGRESS);
+
+
+D_I(3) <= '1';
+D(3) <= D_I(3) when D_OE(3) = '1' else 'Z';
+D_OE(3) <= (RW AND AUTOCONFIG_IN_PROGRESS);
+
+
+D_I(4) <= '1';
+D(4) <= D_I(4) when D_OE(4) = '1' else 'Z';
+D_OE(4) <= (RW AND AUTOCONFIG_IN_PROGRESS);
+
+
+D_I(5) <= '1';
+D(5) <= D_I(5) when D_OE(5) = '1' else 'Z';
+D_OE(5) <= (RW AND AUTOCONFIG_IN_PROGRESS);
+
+
+D_I(6) <= '1';
+D(6) <= D_I(6) when D_OE(6) = '1' else 'Z';
+D_OE(6) <= (RW AND AUTOCONFIG_IN_PROGRESS);
+
+
+D_I(7) <= '1';
+D(7) <= D_I(7) when D_OE(7) = '1' else 'Z';
+D_OE(7) <= (RW AND AUTOCONFIG_IN_PROGRESS);
+
+
+D_I(8) <= '1';
+D(8) <= D_I(8) when D_OE(8) = '1' else 'Z';
+D_OE(8) <= (RW AND AUTOCONFIG_IN_PROGRESS);
+
+
+D_I(9) <= '1';
+D(9) <= D_I(9) when D_OE(9) = '1' else 'Z';
+D_OE(9) <= (RW AND AUTOCONFIG_IN_PROGRESS);
+
+
+D_I(10) <= '1';
+D(10) <= D_I(10) when D_OE(10) = '1' else 'Z';
+D_OE(10) <= (RW AND AUTOCONFIG_IN_PROGRESS);
+
+
+D_I(11) <= '1';
+D(11) <= D_I(11) when D_OE(11) = '1' else 'Z';
+D_OE(11) <= (RW AND AUTOCONFIG_IN_PROGRESS);
+
+FDCPE_D12_BUFR: FDCPE port map (D(12)_BUFR,D_D(12)_BUFR,ide/ide_CLKF,'0','0');
+D_D(12)_BUFR <= ((RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND A(6) AND NOT A(3) AND 
+	NOT A(2) AND NOT AUTO_CONFIG_DONE(0) AND autoconfig)
+	OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND A(6) AND NOT A(3) AND 
+	NOT A(2) AND NOT AUTO_CONFIG_DONE(1) AND autoconfig)
+	OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND A(6) AND NOT A(3) AND 
+	NOT A(2) AND NOT AUTO_CONFIG_DONE(2) AND autoconfig)
+	OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(1) AND NOT A(6) AND NOT A(3) AND 
+	A(2) AND NOT AUTO_CONFIG_DONE(0) AND autoconfig)
+	OR (RESET AND RW AND NOT AS AND A(5) AND NOT A(4) AND A(1) AND NOT A(6) AND 
+	A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND 
+	autoconfig)
+	OR (ROM_OE_S.EXP)
+	OR (RESET AND NOT D(12) AND NOT RW)
+	OR (RESET AND NOT D(12) AND AS)
+	OR (RESET AND NOT D(12) AND NOT autoconfig)
+	OR (RESET AND NOT D(12) AND AUTO_CONFIG_DONE(0) AND 
+	AUTO_CONFIG_DONE(1) AND AUTO_CONFIG_DONE(2))
+	OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND NOT A(3) AND 
+	NOT A(2) AND NOT AUTO_CONFIG_DONE(0) AND autoconfig)
+	OR (RESET AND RW AND NOT AS AND NOT A(4) AND A(1) AND NOT A(6) AND NOT A(3) AND 
+	A(2) AND NOT AUTO_CONFIG_DONE(0) AND autoconfig)
+	OR (RESET AND RW AND NOT AS AND NOT A(5) AND A(4) AND NOT A(6) AND A(3) AND 
+	NOT A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND 
+	autoconfig)
+	OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND NOT A(3) AND 
+	NOT A(2) AND AUTO_CONFIG_DONE(1) AND NOT AUTO_CONFIG_DONE(2) AND 
+	autoconfig)
+	OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND NOT A(3) AND 
+	NOT A(2) AND NOT AUTO_CONFIG_DONE(1) AND AUTOBOOT_OFF AND autoconfig));
+
+
+D_I(12) <= D(12)_BUFR;
+D(12) <= D_I(12) when D_OE(12) = '1' else 'Z';
+D_OE(12) <= (RW AND AUTOCONFIG_IN_PROGRESS);
+
+FDCPE_D13_BUFR: FDCPE port map (D(13)_BUFR,D_D(13)_BUFR,ide/ide_CLKF,'0','0');
+D_D(13)_BUFR <= ((IDE_BASEADR(6).EXP)
+	OR (RESET AND NOT D(13) AND NOT RW)
+	OR (RESET AND NOT D(13) AND AUTO_CONFIG_DONE(0) AND 
+	AUTO_CONFIG_DONE(1) AND AUTO_CONFIG_DONE(2))
+	OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(6) AND NOT A(3) AND 
+	NOT AUTO_CONFIG_DONE(0) AND autoconfig)
+	OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(3) AND NOT A(2) AND 
+	NOT AUTO_CONFIG_DONE(0) AND autoconfig)
+	OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(3) AND NOT A(2) AND 
+	NOT AUTO_CONFIG_DONE(1) AND autoconfig)
+	OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(3) AND NOT A(2) AND 
+	NOT AUTO_CONFIG_DONE(2) AND autoconfig)
+	OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND A(1) AND NOT A(6) AND 
+	NOT A(3) AND NOT AUTO_CONFIG_DONE(1) AND autoconfig)
+	OR (RESET AND RW AND NOT AS AND NOT A(5) AND A(1) AND NOT A(6) AND NOT A(3) AND 
+	NOT A(2) AND NOT AUTO_CONFIG_DONE(0) AND autoconfig)
+	OR (RESET AND RW AND NOT AS AND NOT A(5) AND A(4) AND NOT A(1) AND NOT A(6) AND 
+	A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND 
+	autoconfig)
+	OR (RESET AND NOT D(13) AND AS)
+	OR (RESET AND NOT D(13) AND NOT autoconfig)
+	OR (RESET AND RW AND NOT AS AND NOT A(5) AND A(4) AND NOT A(6) AND A(3) AND 
+	A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND 
+	autoconfig)
+	OR (RESET AND RW AND NOT AS AND NOT A(5) AND A(1) AND NOT A(6) AND NOT A(3) AND 
+	NOT A(2) AND AUTO_CONFIG_DONE(1) AND NOT AUTO_CONFIG_DONE(2) AND 
+	autoconfig));
+
+
+D_I(13) <= D(13)_BUFR;
+D(13) <= D_I(13) when D_OE(13) = '1' else 'Z';
+D_OE(13) <= (RW AND AUTOCONFIG_IN_PROGRESS);
+
+
+D_I(14) <= D(14)_BUFR;
+D(14) <= D_I(14) when D_OE(14) = '1' else 'Z';
+D_OE(14) <= (RW AND AUTOCONFIG_IN_PROGRESS);
+
+FDCPE_D14_BUFR: FDCPE port map (D(14)_BUFR,D_D(14)_BUFR,ide/ide_CLKF,'0','0');
+D_D(14)_BUFR <= ((EXP16_.EXP)
+	OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND A(1) AND NOT A(3) AND 
+	NOT A(2) AND NOT AUTO_CONFIG_DONE(0) AND autoconfig)
+	OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND A(6) AND NOT A(3) AND 
+	NOT A(2) AND NOT AUTO_CONFIG_DONE(0) AND autoconfig)
+	OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND A(6) AND NOT A(3) AND 
+	NOT A(2) AND NOT AUTO_CONFIG_DONE(1) AND autoconfig)
+	OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND A(6) AND NOT A(3) AND 
+	NOT A(2) AND NOT AUTO_CONFIG_DONE(2) AND autoconfig)
+	OR (RESET AND RW AND NOT AS AND NOT A(4) AND A(1) AND NOT A(6) AND NOT A(3) AND 
+	A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND 
+	autoconfig)
+	OR (RESET AND NOT D(14) AND NOT RW)
+	OR (RESET AND NOT D(14) AND AS)
+	OR (RESET AND NOT D(14) AND NOT autoconfig)
+	OR (RESET AND NOT D(14) AND AUTO_CONFIG_DONE(0) AND 
+	AUTO_CONFIG_DONE(1) AND AUTO_CONFIG_DONE(2))
+	OR (RESET AND RW AND NOT AS AND NOT A(5) AND A(1) AND NOT A(6) AND NOT A(3) AND 
+	A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(2) AND 
+	autoconfig)
+	OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND A(1) AND NOT A(3) AND 
+	NOT A(2) AND NOT AUTO_CONFIG_DONE(1) AND autoconfig)
+	OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND A(1) AND NOT A(3) AND 
+	NOT A(2) AND NOT AUTO_CONFIG_DONE(2) AND autoconfig)
+	OR (RESET AND RW AND NOT AS AND NOT A(5) AND A(1) AND NOT A(6) AND NOT A(3) AND 
+	A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND 
+	autoconfig)
+	OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(6) AND NOT A(3) AND 
+	A(2) AND AUTO_CONFIG_DONE(0) AND AUTO_CONFIG_DONE(1) AND 
+	NOT AUTO_CONFIG_DONE(2) AND autoconfig));
+
+
+D_I(15) <= D(15)_BUFR;
+D(15) <= D_I(15) when D_OE(15) = '1' else 'Z';
+D_OE(15) <= (RW AND AUTOCONFIG_IN_PROGRESS);
+
+FDCPE_D15_BUFR: FDCPE port map (D(15)_BUFR,D_D(15)_BUFR,ide/ide_CLKF,'0','0');
+D_D(15)_BUFR <= ((RESET AND NOT D(15) AND AUTO_CONFIG_DONE(0) AND 
+	AUTO_CONFIG_DONE(1) AND AUTO_CONFIG_DONE(2))
+	OR (RESET AND RW AND NOT AS AND NOT A(5) AND A(1) AND NOT A(6) AND NOT A(3) AND 
+	NOT AUTO_CONFIG_DONE(0) AND autoconfig)
+	OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND A(6) AND NOT A(3) AND 
+	NOT A(2) AND NOT AUTO_CONFIG_DONE(0) AND autoconfig)
+	OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND A(6) AND NOT A(3) AND 
+	NOT A(2) AND NOT AUTO_CONFIG_DONE(1) AND autoconfig)
+	OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND A(6) AND NOT A(3) AND 
+	NOT A(2) AND NOT AUTO_CONFIG_DONE(2) AND autoconfig)
+	OR (RESET AND RW AND NOT AS AND NOT A(5) AND A(1) AND NOT A(6) AND NOT A(3) AND 
+	AUTO_CONFIG_DONE(1) AND NOT AUTO_CONFIG_DONE(2) AND autoconfig)
+	OR (RESET AND RW AND NOT AS AND NOT A(5) AND A(4) AND A(1) AND NOT A(6) AND 
+	A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND 
+	autoconfig)
+	OR (RESET AND RW AND NOT AS AND A(5) AND NOT A(4) AND NOT A(1) AND NOT A(6) AND 
+	NOT A(3) AND A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND 
+	autoconfig)
+	OR (RESET AND RW AND NOT AS AND NOT A(5) AND A(4) AND NOT A(1) AND NOT A(6) AND 
+	A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND 
+	autoconfig)
+	OR (RESET AND NOT D(15) AND NOT RW)
+	OR (RESET AND NOT D(15) AND AS)
+	OR (RESET AND NOT D(15) AND NOT autoconfig)
+	OR (RESET AND RW AND NOT AS AND NOT A(5) AND A(1) AND NOT A(6) AND NOT A(3) AND 
+	NOT A(2) AND NOT AUTO_CONFIG_DONE(1) AND autoconfig));
+
+
+DTACK_I <= '0';
+DTACK <= DTACK_I when DTACK_OE = '1' else 'Z';
+DTACK_OE <= '0';
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+IDE_A(0) <= A(9);
+
+
+IDE_A(1) <= A(10);
+
+
+IDE_A(2) <= A(11);
+
+FTCPE_IDE_BASEADR0: FTCPE port map (IDE_BASEADR(0),IDE_BASEADR_T(0),ide/ide_CLKF,'0','0');
+IDE_BASEADR_T(0) <= ((NOT RESET AND NOT IDE_BASEADR(0))
+	OR (NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND A(6) AND 
+	A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND 
+	NOT IDE_BASEADR(0) AND autoconfig AND D(8).PIN)
+	OR (RESET AND NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND 
+	A(6) AND A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND 
+	NOT AUTO_CONFIG_DONE(1) AND IDE_BASEADR(0) AND autoconfig AND NOT D(8).PIN));
+
+FTCPE_IDE_BASEADR1: FTCPE port map (IDE_BASEADR(1),IDE_BASEADR_T(1),ide/ide_CLKF,'0','0');
+IDE_BASEADR_T(1) <= ((NOT RESET AND NOT IDE_BASEADR(1))
+	OR (NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND A(6) AND 
+	A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND 
+	NOT IDE_BASEADR(1) AND autoconfig AND D(9).PIN)
+	OR (RESET AND NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND 
+	A(6) AND A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND 
+	NOT AUTO_CONFIG_DONE(1) AND IDE_BASEADR(1) AND autoconfig AND NOT D(9).PIN));
+
+FTCPE_IDE_BASEADR2: FTCPE port map (IDE_BASEADR(2),IDE_BASEADR_T(2),ide/ide_CLKF,'0','0');
+IDE_BASEADR_T(2) <= ((NOT RESET AND NOT IDE_BASEADR(2))
+	OR (NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND A(6) AND 
+	A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND 
+	NOT IDE_BASEADR(2) AND autoconfig AND D(10).PIN)
+	OR (RESET AND NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND 
+	A(6) AND A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND 
+	NOT AUTO_CONFIG_DONE(1) AND IDE_BASEADR(2) AND autoconfig AND NOT D(10).PIN));
+
+FTCPE_IDE_BASEADR3: FTCPE port map (IDE_BASEADR(3),IDE_BASEADR_T(3),ide/ide_CLKF,'0','0');
+IDE_BASEADR_T(3) <= ((NOT RESET AND NOT IDE_BASEADR(3))
+	OR (NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND A(6) AND 
+	A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND 
+	NOT IDE_BASEADR(3) AND autoconfig AND D(11).PIN)
+	OR (RESET AND NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND 
+	A(6) AND A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND 
+	NOT AUTO_CONFIG_DONE(1) AND IDE_BASEADR(3) AND autoconfig AND NOT D(11).PIN));
+
+FTCPE_IDE_BASEADR4: FTCPE port map (IDE_BASEADR(4),IDE_BASEADR_T(4),ide/ide_CLKF,'0','0');
+IDE_BASEADR_T(4) <= ((NOT RESET AND NOT IDE_BASEADR(4))
+	OR (NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND A(6) AND 
+	A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND 
+	NOT IDE_BASEADR(4) AND autoconfig AND D(12).PIN)
+	OR (RESET AND NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND 
+	A(6) AND A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND 
+	NOT AUTO_CONFIG_DONE(1) AND IDE_BASEADR(4) AND autoconfig AND NOT D(12).PIN));
+
+FTCPE_IDE_BASEADR5: FTCPE port map (IDE_BASEADR(5),IDE_BASEADR_T(5),ide/ide_CLKF,'0','0');
+IDE_BASEADR_T(5) <= ((NOT RESET AND NOT IDE_BASEADR(5))
+	OR (NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND A(6) AND 
+	A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND 
+	NOT IDE_BASEADR(5) AND autoconfig AND D(13).PIN)
+	OR (RESET AND NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND 
+	A(6) AND A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND 
+	NOT AUTO_CONFIG_DONE(1) AND IDE_BASEADR(5) AND autoconfig AND NOT D(13).PIN));
+
+FTCPE_IDE_BASEADR6: FTCPE port map (IDE_BASEADR(6),IDE_BASEADR_T(6),ide/ide_CLKF,'0','0');
+IDE_BASEADR_T(6) <= ((NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND A(6) AND 
+	A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND 
+	NOT IDE_BASEADR(6) AND autoconfig AND D(14).PIN)
+	OR (RESET AND NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND 
+	A(6) AND A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND 
+	NOT AUTO_CONFIG_DONE(1) AND IDE_BASEADR(6) AND autoconfig AND NOT D(14).PIN)
+	OR (NOT RESET AND NOT IDE_BASEADR(6)));
+
+FTCPE_IDE_BASEADR7: FTCPE port map (IDE_BASEADR(7),IDE_BASEADR_T(7),ide/ide_CLKF,'0','0');
+IDE_BASEADR_T(7) <= ((RESET AND NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND 
+	A(6) AND A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND 
+	NOT AUTO_CONFIG_DONE(1) AND IDE_BASEADR(7) AND autoconfig AND NOT D(15).PIN)
+	OR (NOT RESET AND NOT IDE_BASEADR(7))
+	OR (NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND A(6) AND 
+	A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND 
+	NOT IDE_BASEADR(7) AND autoconfig AND D(15).PIN));
+
+
+IDE_CS(0) <= NOT A(12);
+
+
+IDE_CS(1) <= NOT A(13);
+
+FDCPE_IDE_ENABLE: FDCPE port map (IDE_ENABLE,IDE_ENABLE_D,ide/ide_CLKF,'0','0');
+IDE_ENABLE_D <= ((RESET AND NOT IDE_ENABLE)
+	OR (RESET AND NOT RW AND NOT AS AND ide));
+
+FDCPE_IDE_R: FDCPE port map (IDE_R,IDE_R_D,ide/ide_CLKF,'0','0');
+IDE_R_D <= (RESET AND RW AND NOT AS AND NOT IDE_ENABLE AND ide);
+
+FDCPE_IDE_W: FDCPE port map (IDE_W,IDE_W_D,ide/ide_CLKF,'0','0');
+IDE_W_D <= (RESET AND NOT RW AND NOT AS AND ide);
+
+
+ROM_B(0) <= '0';
+
+
+ROM_B(1) <= '0';
+
+FDCPE_ROM_OE: FDCPE port map (ROM_OE,ROM_OE_D,ide/ide_CLKF,'0','0');
+ROM_OE_D <= (RESET AND RW AND NOT AS AND IDE_ENABLE AND ide);
+
+FDCPE_SHUT_UP1: FDCPE port map (SHUT_UP(1),SHUT_UP_D(1),ide/ide_CLKF,'0','0');
+SHUT_UP_D(1) <= ((RESET AND NOT SHUT_UP(1))
+	OR (RESET AND NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND 
+	A(6) AND A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND 
+	NOT AUTO_CONFIG_DONE(1) AND autoconfig));
+
+FDCPE_autoconfig: FDCPE port map (autoconfig,autoconfig_D,ide/ide_CLKF,'0','0');
+autoconfig_D <= ((A(23) AND A(22) AND A(21) AND A(19) AND 
+	NOT AUTO_CONFIG_DONE(0) AND BERR AND NOT A(17) AND NOT A(16) AND NOT A(20) AND NOT A(18))
+	OR (A(23) AND A(22) AND A(21) AND A(19) AND 
+	NOT AUTO_CONFIG_DONE(1) AND BERR AND NOT A(17) AND NOT A(16) AND NOT A(20) AND NOT A(18))
+	OR (A(23) AND A(22) AND A(21) AND A(19) AND 
+	NOT AUTO_CONFIG_DONE(2) AND BERR AND NOT A(17) AND NOT A(16) AND NOT A(20) AND NOT A(18)));
+
+FDCPE_ide: FDCPE port map (ide,ide_D,ide/ide_CLKF,'0','0');
+ide_D <= ((SHUT_UP(1))
+	OR (NOT BERR)
+	OR (EXP20_.EXP)
+	OR (A(23) AND NOT IDE_BASEADR(7))
+	OR (NOT A(23) AND IDE_BASEADR(7))
+	OR (A(22) AND NOT IDE_BASEADR(6))
+	OR (NOT A(22) AND IDE_BASEADR(6))
+	OR (IDE_BASEADR(1) AND NOT A(17))
+	OR (autoconfig.EXP)
+	OR (IDE_BASEADR(0) AND NOT A(16))
+	OR (NOT IDE_BASEADR(0) AND A(16))
+	OR (NOT IDE_BASEADR(1) AND A(17))
+	OR (IDE_BASEADR(2) AND NOT A(18))
+	OR (NOT IDE_BASEADR(2) AND A(18))
+	OR (A(19) AND NOT IDE_BASEADR(3))
+	OR (NOT A(19) AND IDE_BASEADR(3)));
+
+
+ide/ide_CLKF <= NOT (C3
+	 XOR 
+ide/ide_CLKF <= NOT (C1);
+
+Register Legend:
+ FDCPE (Q,D,C,CLR,PRE,CE); 
+ FTCPE (Q,D,C,CLR,PRE,CE); 
+ LDCP  (Q,D,G,CLR,PRE); 
+
+******************************  Device Pin Out *****************************
+
+Device : XC95144XL-10-TQ144
+
+
+Pin Signal                         Pin Signal                        
+No. Name                           No. Name                          
+  1 VCC                              73 VCC                           
+  2 D<0>                             74 KPR                           
+  3 KPR                              75 AUTOBOOT_OFF                  
+  4 KPR                              76 KPR                           
+  5 KPR                              77 KPR                           
+  6 KPR                              78 KPR                           
+  7 KPR                              79 KPR                           
+  8 VCC                              80 AS                            
+  9 KPR                              81 UDS                           
+ 10 KPR                              82 KPR                           
+ 11 KPR                              83 RW                            
+ 12 KPR                              84 VCC                           
+ 13 KPR                              85 DTACK                         
+ 14 D<6>                             86 A<23>                         
+ 15 D<3>                             87 A<22>                         
+ 16 D<7>                             88 A<21>                         
+ 17 D<1>                             89 GND                           
+ 18 GND                              90 GND                           
+ 19 D<8>                             91 A<20>                         
+ 20 D<5>                             92 A<19>                         
+ 21 D<4>                             93 KPR                           
+ 22 IDE_CS<0>                        94 A<18>                         
+ 23 IDE_CS<1>                        95 A<17>                         
+ 24 IDE_A<0>                         96 KPR                           
+ 25 IDE_A<2>                         97 A<16>                         
+ 26 IDE_A<1>                         98 BERR                          
+ 27 IDE_R                            99 GND                           
+ 28 IDE_W                           100 KPR                           
+ 29 GND                             101 KPR                           
+ 30 KPR                             102 C3                            
+ 31 KPR                             103 C1                            
+ 32 KPR                             104 KPR                           
+ 33 KPR                             105 KPR                           
+ 34 KPR                             106 KPR                           
+ 35 ROM_OE                          107 KPR                           
+ 36 GND                             108 GND                           
+ 37 VCC                             109 VCC                           
+ 38 KPR                             110 KPR                           
+ 39 D<2>                            111 KPR                           
+ 40 D<9>                            112 KPR                           
+ 41 D<10>                           113 KPR                           
+ 42 VCC                             114 GND                           
+ 43 D<11>                           115 KPR                           
+ 44 D<12>                           116 KPR                           
+ 45 D<13>                           117 KPR                           
+ 46 D<14>                           118 KPR                           
+ 47 GND                             119 KPR                           
+ 48 D<15>                           120 KPR                           
+ 49 A<5>                            121 KPR                           
+ 50 A<4>                            122 TDO                           
+ 51 A<6>                            123 GND                           
+ 52 A<3>                            124 KPR                           
+ 53 KPR                             125 KPR                           
+ 54 A<2>                            126 KPR                           
+ 55 VCC                             127 VCC                           
+ 56 KPR                             128 KPR                           
+ 57 A<1>                            129 KPR                           
+ 58 A<9>                            130 KPR                           
+ 59 A<10>                           131 KPR                           
+ 60 A<11>                           132 KPR                           
+ 61 A<12>                           133 KPR                           
+ 62 GND                             134 KPR                           
+ 63 TDI                             135 KPR                           
+ 64 A<13>                           136 KPR                           
+ 65 TMS                             137 KPR                           
+ 66 KPR                             138 KPR                           
+ 67 TCK                             139 KPR                           
+ 68 ROM_B<0>                        140 KPR                           
+ 69 ROM_B<1>                        141 VCC                           
+ 70 KPR                             142 KPR                           
+ 71 KPR                             143 RESET                         
+ 72 GND                             144 GND                           
+
+
+Legend :  NC  = Not Connected, unbonded pin
+         PGND = Unused I/O configured as additional Ground pin
+         TIE  = Unused I/O floating -- must tie to VCC, GND or other signal
+         KPR  = Unused I/O with weak keeper (leave unconnected)
+         VCC  = Dedicated Power Pin
+         GND  = Dedicated Ground Pin
+         TDI  = Test Data In, JTAG pin
+         TDO  = Test Data Out, JTAG pin
+         TCK  = Test Clock, JTAG pin
+         TMS  = Test Mode Select, JTAG pin
+  PROHIBITED  = User reserved pin
+****************************  Compiler Options  ****************************
+
+Following is a list of all global compiler options used by the fitter run.
+
+Device(s) Specified                         : xc95144xl-10-TQ144
+Optimization Method                         : SPEED
+Multi-Level Logic Optimization              : ON
+Ignore Timing Specifications                : OFF
+Default Register Power Up Value             : LOW
+Keep User Location Constraints              : ON
+What-You-See-Is-What-You-Get                : OFF
+Exhaustive Fitting                          : OFF
+Keep Unused Inputs                          : OFF
+Slew Rate                                   : FAST
+Power Mode                                  : STD
+Ground on Unused IOs                        : OFF
+Set I/O Pin Termination                     : KEEPER
+Global Clock Optimization                   : ON
+Global Set/Reset Optimization               : ON
+Global Ouput Enable Optimization            : ON
+Input Limit                                 : 54
+Pterm Limit                                 : 25
diff --git a/Logic/LAN_IDE/LAN_IDE_CP.stx b/Logic/LAN_IDE/LAN_IDE_CP.stx
new file mode 100644
index 0000000..e69de29
diff --git a/Logic/LAN_IDE/LAN_IDE_CP.syr b/Logic/LAN_IDE/LAN_IDE_CP.syr
new file mode 100644
index 0000000..4bafe65
--- /dev/null
+++ b/Logic/LAN_IDE/LAN_IDE_CP.syr
@@ -0,0 +1,286 @@
+Release 14.6 - xst P.68d (nt64)
+Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
+--> Parameter TMPDIR set to xst/projnav.tmp
+
+
+Total REAL time to Xst completion: 0.00 secs
+Total CPU time to Xst completion: 0.11 secs
+ 
+--> Parameter xsthdpdir set to xst
+
+
+Total REAL time to Xst completion: 0.00 secs
+Total CPU time to Xst completion: 0.11 secs
+ 
+--> Reading design: LAN_IDE_CP.prj
+
+TABLE OF CONTENTS
+  1) Synthesis Options Summary
+  2) HDL Compilation
+  3) Design Hierarchy Analysis
+  4) HDL Analysis
+  5) HDL Synthesis
+     5.1) HDL Synthesis Report
+  6) Advanced HDL Synthesis
+     6.1) Advanced HDL Synthesis Report
+  7) Low Level Synthesis
+  8) Partition Report
+  9) Final Report
+
+=========================================================================
+*                      Synthesis Options Summary                        *
+=========================================================================
+---- Source Parameters
+Input File Name                    : "LAN_IDE_CP.prj"
+Input Format                       : mixed
+Ignore Synthesis Constraint File   : NO
+
+---- Target Parameters
+Output File Name                   : "LAN_IDE_CP"
+Output Format                      : NGC
+Target Device                      : XC9500XL CPLDs
+
+---- Source Options
+Top Module Name                    : LAN_IDE_CP
+Automatic FSM Extraction           : YES
+FSM Encoding Algorithm             : Auto
+Safe Implementation                : No
+Mux Extraction                     : Yes
+Resource Sharing                   : YES
+
+---- Target Options
+Add IO Buffers                     : YES
+MACRO Preserve                     : YES
+XOR Preserve                       : YES
+Equivalent register Removal        : YES
+
+---- General Options
+Optimization Goal                  : Speed
+Optimization Effort                : 1
+Keep Hierarchy                     : Yes
+Netlist Hierarchy                  : As_Optimized
+RTL Output                         : Yes
+Hierarchy Separator                : /
+Bus Delimiter                      : <>
+Case Specifier                     : Maintain
+Verilog 2001                       : YES
+
+---- Other Options
+Clock Enable                       : YES
+wysiwyg                            : NO
+
+=========================================================================
+
+
+=========================================================================
+*                          HDL Compilation                              *
+=========================================================================
+Compiling vhdl file "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.vhd" in Library work.
+Entity <lan_ide_cp> compiled.
+Entity <lan_ide_cp> (Architecture <behavioral>) compiled.
+
+=========================================================================
+*                     Design Hierarchy Analysis                         *
+=========================================================================
+Analyzing hierarchy for entity <LAN_IDE_CP> in library <work> (architecture <behavioral>).
+
+
+=========================================================================
+*                            HDL Analysis                               *
+=========================================================================
+Analyzing Entity <LAN_IDE_CP> in library <work> (Architecture <behavioral>).
+Entity <LAN_IDE_CP> analyzed. Unit <LAN_IDE_CP> generated.
+
+
+=========================================================================
+*                           HDL Synthesis                               *
+=========================================================================
+
+Performing bidirectional port resolution...
+
+Synthesizing Unit <LAN_IDE_CP>.
+    Related source file is "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.vhd".
+WARNING:Xst:2565 - Inout <DQ<0>> is never assigned.
+WARNING:Xst:1306 - Output <SLAVE> is never assigned.
+WARNING:Xst:647 - Input <IDE_WAIT> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+WARNING:Xst:2565 - Inout <DQ<1>> is never assigned.
+WARNING:Xst:647 - Input <LDS> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+WARNING:Xst:1306 - Output <LAN_CS> is never assigned.
+WARNING:Xst:2565 - Inout <DQ<2>> is never assigned.
+WARNING:Xst:1306 - Output <LAN_EN> is never assigned.
+WARNING:Xst:2565 - Inout <DQ<3>> is never assigned.
+WARNING:Xst:2565 - Inout <DQ<4>> is never assigned.
+WARNING:Xst:2565 - Inout <DQ<10>> is never assigned.
+WARNING:Xst:2565 - Inout <DQ<5>> is never assigned.
+WARNING:Xst:2565 - Inout <DQ<11>> is never assigned.
+WARNING:Xst:2565 - Inout <DQ<6>> is never assigned.
+WARNING:Xst:2565 - Inout <DQ<12>> is never assigned.
+WARNING:Xst:1306 - Output <CFOUT> is never assigned.
+WARNING:Xst:2565 - Inout <DQ<7>> is never assigned.
+WARNING:Xst:2565 - Inout <DQ<13>> is never assigned.
+WARNING:Xst:1306 - Output <LAN_WRH> is never assigned.
+WARNING:Xst:647 - Input <DS0> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+WARNING:Xst:647 - Input <DS1> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+WARNING:Xst:2565 - Inout <DQ<8>> is never assigned.
+WARNING:Xst:2565 - Inout <DQ<14>> is never assigned.
+WARNING:Xst:647 - Input <FCS> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+WARNING:Xst:2565 - Inout <DQ<9>> is never assigned.
+WARNING:Xst:2565 - Inout <DQ<15>> is never assigned.
+WARNING:Xst:1306 - Output <CP_CS> is never assigned.
+WARNING:Xst:1306 - Output <LAN_CFG> is never assigned.
+WARNING:Xst:1306 - Output <MTACK> is never assigned.
+WARNING:Xst:647 - Input <LAN_INT> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+WARNING:Xst:1306 - Output <INT_OUT> is never assigned.
+WARNING:Xst:1306 - Output <LAN_RD> is never assigned.
+WARNING:Xst:2565 - Inout <A<14>> is never assigned.
+WARNING:Xst:2565 - Inout <A<15>> is never assigned.
+WARNING:Xst:647 - Input <CP_IRQ> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+WARNING:Xst:1306 - Output <CP_RD> is never assigned.
+WARNING:Xst:647 - Input <Z3> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+WARNING:Xst:2565 - Inout <A<7>> is never assigned.
+WARNING:Xst:2565 - Inout <A<8>> is never assigned.
+WARNING:Xst:1306 - Output <CP_WE> is never assigned.
+WARNING:Xst:647 - Input <CFIN> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+WARNING:Xst:647 - Input <CLK_EXT> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+WARNING:Xst:1306 - Output <OVR> is never assigned.
+WARNING:Xst:1306 - Output <OWN> is never assigned.
+WARNING:Xst:647 - Input <MTCR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+WARNING:Xst:1306 - Output <A_LAN> is never assigned.
+WARNING:Xst:646 - Signal <SHUT_UP<2>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <SHUT_UP<0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <LAN_BASEADR> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:1780 - Signal <DTACK_S> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <CP_BASEADR> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:1780 - Signal <AS_D> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+    Found 1-bit tristate buffer for signal <DTACK>.
+    Found 16-bit tristate buffer for signal <$mux0000>.
+    Found 1-bit xor2 for signal <AMIGA_CLK$xor0000> created at line 108.
+    Found 3-bit register for signal <AUTO_CONFIG_DONE>.
+    Found 3-bit register for signal <AUTO_CONFIG_DONE_CYCLE>.
+    Found 1-bit register for signal <autoconfig>.
+    Found 1-bit register for signal <AUTOCONFIG_IN_PROGRESS>.
+    Found 4-bit register for signal <Dout1>.
+    Found 1-bit register for signal <ide>.
+    Found 8-bit comparator not equal for signal <ide$cmp_ne0000> created at line 126.
+    Found 8-bit register for signal <IDE_BASEADR>.
+    Found 1-bit register for signal <IDE_ENABLE>.
+    Found 1-bit register for signal <IDE_R_S>.
+    Found 1-bit register for signal <IDE_W_S>.
+    Found 1-bit register for signal <ROM_OE_S>.
+    Found 1-bit register for signal <SHUT_UP<1>>.
+    Summary:
+	inferred   1 Comparator(s).
+	inferred   1 Xor(s).
+	inferred  17 Tristate(s).
+Unit <LAN_IDE_CP> synthesized.
+
+
+=========================================================================
+HDL Synthesis Report
+
+Macro Statistics
+# Registers                                            : 14
+ 1-bit register                                        : 11
+ 3-bit register                                        : 1
+ 4-bit register                                        : 1
+ 8-bit register                                        : 1
+# Comparators                                          : 1
+ 8-bit comparator not equal                            : 1
+# Tristates                                            : 2
+ 1-bit tristate buffer                                 : 1
+ 16-bit tristate buffer                                : 1
+# Xors                                                 : 1
+ 1-bit xor2                                            : 1
+
+=========================================================================
+
+=========================================================================
+*                       Advanced HDL Synthesis                          *
+=========================================================================
+
+
+=========================================================================
+Advanced HDL Synthesis Report
+
+Found no macro
+=========================================================================
+
+=========================================================================
+*                         Low Level Synthesis                           *
+=========================================================================
+
+Optimizing unit <LAN_IDE_CP> ...
+  implementation constraint: INIT=r	 : IDE_ENABLE
+  implementation constraint: INIT=r	 : ide
+  implementation constraint: INIT=r	 : autoconfig
+  implementation constraint: INIT=s	 : IDE_R_S
+  implementation constraint: INIT=s	 : IDE_W_S
+  implementation constraint: INIT=s	 : ROM_OE_S
+  implementation constraint: INIT=r	 : AUTOCONFIG_IN_PROGRESS
+
+=========================================================================
+*                           Partition Report                            *
+=========================================================================
+
+Partition Implementation Status
+-------------------------------
+
+  No Partitions were found in this design.
+
+-------------------------------
+
+=========================================================================
+*                            Final Report                               *
+=========================================================================
+Final Results
+RTL Top Level Output File Name     : LAN_IDE_CP.ngr
+Top Level Output File Name         : LAN_IDE_CP
+Output Format                      : NGC
+Optimization Goal                  : Speed
+Keep Hierarchy                     : Yes
+Target Technology                  : XC9500XL CPLDs
+Macro Preserve                     : YES
+XOR Preserve                       : YES
+Clock Enable                       : YES
+wysiwyg                            : NO
+
+Design Statistics
+# IOs                              : 116
+
+Cell Usage :
+# BELS                             : 322
+#      AND2                        : 75
+#      AND3                        : 16
+#      AND4                        : 5
+#      AND5                        : 1
+#      GND                         : 1
+#      INV                         : 138
+#      OR2                         : 63
+#      OR3                         : 13
+#      OR4                         : 2
+#      OR5                         : 1
+#      VCC                         : 1
+#      XOR2                        : 6
+# FlipFlops/Latches                : 26
+#      FD                          : 6
+#      FDC                         : 3
+#      FDCE                        : 17
+# IO Buffers                       : 54
+#      IBUF                        : 27
+#      IOBUFE                      : 8
+#      OBUF                        : 10
+#      OBUFE                       : 9
+=========================================================================
+
+
+Total REAL time to Xst completion: 7.00 secs
+Total CPU time to Xst completion: 7.69 secs
+ 
+--> 
+
+Total memory usage is 290044 kilobytes
+
+Number of errors   :    0 (   0 filtered)
+Number of warnings :   52 (   0 filtered)
+Number of infos    :    0 (   0 filtered)
+
diff --git a/Logic/LAN_IDE/LAN_IDE_CP.tim b/Logic/LAN_IDE/LAN_IDE_CP.tim
new file mode 100644
index 0000000..e69de29
diff --git a/Logic/LAN_IDE/LAN_IDE_CP.tspec b/Logic/LAN_IDE/LAN_IDE_CP.tspec
new file mode 100644
index 0000000..6b5d04c
--- /dev/null
+++ b/Logic/LAN_IDE/LAN_IDE_CP.tspec
@@ -0,0 +1,278 @@
+AUTO_TS_P2P:FROM:C3:TO:IDE_R:1
+AUTO_TS_P2P:FROM:C1:TO:IDE_R:1
+AUTO_TS_F2P:FROM:IDE_R_S.Q:TO:IDE_R:1
+AUTO_TS_P2P:FROM:C3:TO:IDE_W:1
+AUTO_TS_P2P:FROM:C1:TO:IDE_W:1
+AUTO_TS_F2P:FROM:IDE_W_S.Q:TO:IDE_W:1
+AUTO_TS_P2P:FROM:C3:TO:ROM_OE:1
+AUTO_TS_P2P:FROM:C1:TO:ROM_OE:1
+AUTO_TS_F2P:FROM:ROM_OE_S.Q:TO:ROM_OE:1
+AUTO_TS_P2P:FROM:A<9>:TO:IDE_A<0>:1
+AUTO_TS_P2P:FROM:A<10>:TO:IDE_A<1>:1
+AUTO_TS_P2P:FROM:A<11>:TO:IDE_A<2>:1
+AUTO_TS_P2P:FROM:A<12>:TO:IDE_CS<0>:1
+AUTO_TS_P2P:FROM:A<13>:TO:IDE_CS<1>:1
+AUTO_TS_F2F:FROM:AUTO_CONFIG_DONE_CYCLE<1>.Q:TO:AUTO_CONFIG_DONE_CYCLE<1>.D:1
+AUTO_TS_F2F:FROM:autoconfig.Q:TO:AUTO_CONFIG_DONE_CYCLE<1>.D:1
+AUTO_TS_F2F:FROM:AUTO_CONFIG_DONE<1>.Q:TO:AUTO_CONFIG_DONE_CYCLE<1>.D:1
+AUTO_TS_F2F:FROM:AUTO_CONFIG_DONE<0>.Q:TO:AUTO_CONFIG_DONE_CYCLE<1>.D:1
+AUTO_TS_P2F:FROM:RESET:TO:AUTO_CONFIG_DONE_CYCLE<1>.D:1
+AUTO_TS_P2F:FROM:C3:TO:AUTO_CONFIG_DONE_CYCLE<1>.D:1
+AUTO_TS_P2F:FROM:C1:TO:AUTO_CONFIG_DONE_CYCLE<1>.D:1
+AUTO_TS_P2F:FROM:AS:TO:AUTO_CONFIG_DONE_CYCLE<1>.D:1
+AUTO_TS_P2F:FROM:RW:TO:AUTO_CONFIG_DONE_CYCLE<1>.D:1
+AUTO_TS_P2F:FROM:A<1>:TO:AUTO_CONFIG_DONE_CYCLE<1>.D:1
+AUTO_TS_P2F:FROM:A<3>:TO:AUTO_CONFIG_DONE_CYCLE<1>.D:1
+AUTO_TS_P2F:FROM:A<4>:TO:AUTO_CONFIG_DONE_CYCLE<1>.D:1
+AUTO_TS_P2F:FROM:A<5>:TO:AUTO_CONFIG_DONE_CYCLE<1>.D:1
+AUTO_TS_P2F:FROM:A<6>:TO:AUTO_CONFIG_DONE_CYCLE<1>.D:1
+AUTO_TS_P2F:FROM:UDS:TO:AUTO_CONFIG_DONE_CYCLE<1>.D:1
+AUTO_TS_F2F:FROM:IDE_BASEADR<0>.Q:TO:IDE_BASEADR<0>.D:1
+AUTO_TS_F2F:FROM:autoconfig.Q:TO:IDE_BASEADR<0>.D:1
+AUTO_TS_F2F:FROM:AUTO_CONFIG_DONE<1>.Q:TO:IDE_BASEADR<0>.D:1
+AUTO_TS_F2F:FROM:AUTO_CONFIG_DONE<0>.Q:TO:IDE_BASEADR<0>.D:1
+AUTO_TS_P2F:FROM:RESET:TO:IDE_BASEADR<0>.D:1
+AUTO_TS_P2F:FROM:C3:TO:IDE_BASEADR<0>.D:1
+AUTO_TS_P2F:FROM:C1:TO:IDE_BASEADR<0>.D:1
+AUTO_TS_P2F:FROM:AS:TO:IDE_BASEADR<0>.D:1
+AUTO_TS_P2F:FROM:RW:TO:IDE_BASEADR<0>.D:1
+AUTO_TS_P2F:FROM:A<1>:TO:IDE_BASEADR<0>.D:1
+AUTO_TS_P2F:FROM:A<3>:TO:IDE_BASEADR<0>.D:1
+AUTO_TS_P2F:FROM:A<4>:TO:IDE_BASEADR<0>.D:1
+AUTO_TS_P2F:FROM:A<5>:TO:IDE_BASEADR<0>.D:1
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+AUTO_TS_P2F:FROM:RESET:TO:IDE_BASEADR<4>.D:1
+AUTO_TS_P2F:FROM:C3:TO:IDE_BASEADR<4>.D:1
+AUTO_TS_P2F:FROM:C1:TO:IDE_BASEADR<4>.D:1
+AUTO_TS_P2F:FROM:AS:TO:IDE_BASEADR<4>.D:1
+AUTO_TS_P2F:FROM:RW:TO:IDE_BASEADR<4>.D:1
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+AUTO_TS_P2F:FROM:C3:TO:IDE_BASEADR<5>.D:1
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+AUTO_TS_P2F:FROM:RESET:TO:SHUT_UP<1>.D:1
+AUTO_TS_P2F:FROM:C3:TO:SHUT_UP<1>.D:1
+AUTO_TS_P2F:FROM:C1:TO:SHUT_UP<1>.D:1
+AUTO_TS_P2F:FROM:AS:TO:SHUT_UP<1>.D:1
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+AUTO_TS_P2F:FROM:A<2>:TO:SHUT_UP<1>.D:1
+AUTO_TS_F2F:FROM:SHUT_UP<1>.Q:TO:ide.D:1
+AUTO_TS_F2F:FROM:IDE_BASEADR<5>.Q:TO:ide.D:1
+AUTO_TS_F2F:FROM:IDE_BASEADR<4>.Q:TO:ide.D:1
+AUTO_TS_F2F:FROM:IDE_BASEADR<0>.Q:TO:ide.D:1
+AUTO_TS_F2F:FROM:IDE_BASEADR<1>.Q:TO:ide.D:1
+AUTO_TS_F2F:FROM:IDE_BASEADR<2>.Q:TO:ide.D:1
+AUTO_TS_F2F:FROM:IDE_BASEADR<7>.Q:TO:ide.D:1
+AUTO_TS_F2F:FROM:IDE_BASEADR<6>.Q:TO:ide.D:1
+AUTO_TS_F2F:FROM:IDE_BASEADR<3>.Q:TO:ide.D:1
+AUTO_TS_P2F:FROM:C3:TO:ide.D:1
+AUTO_TS_P2F:FROM:C1:TO:ide.D:1
+AUTO_TS_P2F:FROM:BERR:TO:ide.D:1
+AUTO_TS_P2F:FROM:A<21>:TO:ide.D:1
+AUTO_TS_P2F:FROM:A<20>:TO:ide.D:1
+AUTO_TS_P2F:FROM:A<16>:TO:ide.D:1
+AUTO_TS_P2F:FROM:A<17>:TO:ide.D:1
+AUTO_TS_P2F:FROM:A<18>:TO:ide.D:1
+AUTO_TS_P2F:FROM:A<23>:TO:ide.D:1
+AUTO_TS_P2F:FROM:A<22>:TO:ide.D:1
+AUTO_TS_P2F:FROM:A<19>:TO:ide.D:1
+AUTO_TS_F2F:FROM:IDE_ENABLE.Q:TO:IDE_R_S.D:1
+AUTO_TS_F2F:FROM:ide.Q:TO:IDE_R_S.D:1
+AUTO_TS_P2F:FROM:AS:TO:IDE_R_S.D:1
+AUTO_TS_P2F:FROM:RESET:TO:IDE_R_S.D:1
+AUTO_TS_P2F:FROM:RW:TO:IDE_R_S.D:1
+AUTO_TS_P2F:FROM:C3:TO:IDE_R_S.D:1
+AUTO_TS_P2F:FROM:C1:TO:IDE_R_S.D:1
+AUTO_TS_F2F:FROM:ide.Q:TO:IDE_W_S.D:1
+AUTO_TS_P2F:FROM:AS:TO:IDE_W_S.D:1
+AUTO_TS_P2F:FROM:RESET:TO:IDE_W_S.D:1
+AUTO_TS_P2F:FROM:RW:TO:IDE_W_S.D:1
+AUTO_TS_P2F:FROM:C3:TO:IDE_W_S.D:1
+AUTO_TS_P2F:FROM:C1:TO:IDE_W_S.D:1
+AUTO_TS_F2F:FROM:IDE_ENABLE.Q:TO:ROM_OE_S.D:1
+AUTO_TS_F2F:FROM:ide.Q:TO:ROM_OE_S.D:1
+AUTO_TS_P2F:FROM:AS:TO:ROM_OE_S.D:1
+AUTO_TS_P2F:FROM:RESET:TO:ROM_OE_S.D:1
+AUTO_TS_P2F:FROM:RW:TO:ROM_OE_S.D:1
+AUTO_TS_P2F:FROM:C3:TO:ROM_OE_S.D:1
+AUTO_TS_P2F:FROM:C1:TO:ROM_OE_S.D:1
+AUTO_TS_F2F:FROM:AUTO_CONFIG_DONE_CYCLE<1>.Q:TO:AUTO_CONFIG_DONE<1>.D:1
+AUTO_TS_P2F:FROM:C3:TO:AUTO_CONFIG_DONE<1>.D:1
+AUTO_TS_P2F:FROM:C1:TO:AUTO_CONFIG_DONE<1>.D:1
+AUTO_TS_F2F:FROM:AUTO_CONFIG_DONE<1>.Q:TO:autoconfig.D:1
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+AUTO_TS_P2F:FROM:AS:TO:autoconfig.D:1
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+AUTO_TS_P2F:FROM:A<17>:TO:autoconfig.D:1
+AUTO_TS_P2F:FROM:A<20>:TO:autoconfig.D:1
+AUTO_TS_P2F:FROM:AS:TO:AUTO_CONFIG_DONE<1>.CLKF:1
+AUTO_TS_P2F:FROM:RESET:TO:FSR-IO_0:1
+AUTO_TS_P2F:FROM:C3:TO:AUTO_CONFIG_DONE_CYCLE<1>.CLKF:1
+AUTO_TS_P2F:FROM:C1:TO:AUTO_CONFIG_DONE_CYCLE<1>.CLKF:1
+AUTO_TS_P2F:FROM:C3:TO:IDE_BASEADR<0>.CLKF:1
+AUTO_TS_P2F:FROM:C1:TO:IDE_BASEADR<0>.CLKF:1
+AUTO_TS_P2F:FROM:C3:TO:IDE_BASEADR<4>.CLKF:1
+AUTO_TS_P2F:FROM:C1:TO:IDE_BASEADR<4>.CLKF:1
+AUTO_TS_P2F:FROM:C3:TO:IDE_BASEADR<5>.CLKF:1
+AUTO_TS_P2F:FROM:C1:TO:IDE_BASEADR<5>.CLKF:1
+AUTO_TS_P2F:FROM:C3:TO:IDE_ENABLE.CLKF:1
+AUTO_TS_P2F:FROM:C1:TO:IDE_ENABLE.CLKF:1
+AUTO_TS_P2F:FROM:C3:TO:IDE_BASEADR<1>.CLKF:1
+AUTO_TS_P2F:FROM:C1:TO:IDE_BASEADR<1>.CLKF:1
+AUTO_TS_P2F:FROM:C3:TO:IDE_BASEADR<2>.CLKF:1
+AUTO_TS_P2F:FROM:C1:TO:IDE_BASEADR<2>.CLKF:1
+AUTO_TS_P2F:FROM:C3:TO:IDE_BASEADR<3>.CLKF:1
+AUTO_TS_P2F:FROM:C1:TO:IDE_BASEADR<3>.CLKF:1
+AUTO_TS_P2F:FROM:C3:TO:IDE_BASEADR<6>.CLKF:1
+AUTO_TS_P2F:FROM:C1:TO:IDE_BASEADR<6>.CLKF:1
+AUTO_TS_P2F:FROM:C3:TO:IDE_BASEADR<7>.CLKF:1
+AUTO_TS_P2F:FROM:C1:TO:IDE_BASEADR<7>.CLKF:1
+AUTO_TS_P2F:FROM:C3:TO:SHUT_UP<1>.CLKF:1
+AUTO_TS_P2F:FROM:C1:TO:SHUT_UP<1>.CLKF:1
+AUTO_TS_P2F:FROM:AS:TO:AUTO_CONFIG_DONE<0>.CLKF:1
+AUTO_TS_P2F:FROM:C3:TO:ide.CLKF:1
+AUTO_TS_P2F:FROM:C1:TO:ide.CLKF:1
+AUTO_TS_P2F:FROM:C3:TO:autoconfig.CLKF:1
+AUTO_TS_P2F:FROM:C1:TO:autoconfig.CLKF:1
+AUTO_TS_P2F:FROM:C3:TO:IDE_R_S.CLKF:1
+AUTO_TS_P2F:FROM:C1:TO:IDE_R_S.CLKF:1
+AUTO_TS_P2F:FROM:C3:TO:IDE_W_S.CLKF:1
+AUTO_TS_P2F:FROM:C1:TO:IDE_W_S.CLKF:1
+AUTO_TS_P2F:FROM:C3:TO:ROM_OE_S.CLKF:1
+AUTO_TS_P2F:FROM:C1:TO:ROM_OE_S.CLKF:1
diff --git a/Logic/LAN_IDE/LAN_IDE_CP.vhd b/Logic/LAN_IDE/LAN_IDE_CP.vhd
index 642e7ea..998a2fb 100644
--- a/Logic/LAN_IDE/LAN_IDE_CP.vhd
+++ b/Logic/LAN_IDE/LAN_IDE_CP.vhd
@@ -30,7 +30,7 @@ use IEEE.STD_LOGIC_1164.ALL;
 --use UNISIM.VComponents.all;
 
 entity LAN_IDE_CP is
-    Port ( A : inout  STD_LOGIC_VECTOR (23 downto 0);
+    Port ( A : inout  STD_LOGIC_VECTOR (23 downto 1);
            D : inout  STD_LOGIC_VECTOR (15 downto 0);
            DQ : inout  STD_LOGIC_VECTOR (15 downto 0);
            A_LAN : out  STD_LOGIC_VECTOR (13 downto 0);
@@ -49,6 +49,7 @@ entity LAN_IDE_CP is
            UDS : in  STD_LOGIC;
            LDS : in  STD_LOGIC;
            AS : in  STD_LOGIC;
+           RW : in  STD_LOGIC;
            Z3 : in  STD_LOGIC;
            DS1 : in  STD_LOGIC;
            FCS : in  STD_LOGIC;
@@ -77,8 +78,271 @@ end LAN_IDE_CP;
 
 architecture Behavioral of LAN_IDE_CP is
 
-begin
+	SIGNAL ide: STD_LOGIC:= '0';
+	SIGNAL autoconfig: STD_LOGIC:= '0';
+	SIGNAL AUTOCONFIG_IN_PROGRESS: STD_LOGIC:= '0';
+	signal Dout1:STD_LOGIC_VECTOR(3 downto 0);
+	signal AUTO_CONFIG_DONE:STD_LOGIC_VECTOR(2 downto 0);
+	signal AUTO_CONFIG_DONE_CYCLE:STD_LOGIC_VECTOR(2 downto 0);
+	signal SHUT_UP:STD_LOGIC_VECTOR(2 downto 0);
+	signal IDE_BASEADR:STD_LOGIC_VECTOR(7 downto 0);
+	signal LAN_BASEADR:STD_LOGIC_VECTOR(7 downto 0);
+	signal CP_BASEADR:STD_LOGIC_VECTOR(7 downto 0);
+	signal IDE_ENABLE:STD_LOGIC:= '0';
+	signal ROM_OE_S:STD_LOGIC:= '1';
+	signal IDE_R_S:STD_LOGIC:= '1';
+	signal IDE_W_S:STD_LOGIC:= '1';
+	signal DTACK_S:STD_LOGIC:= '1';
+   signal AS_D: std_logic:= '1';
+	signal AMIGA_CLK: std_logic:= '1';
 
+   Function to_std_logic(X: in Boolean) return Std_Logic is
+   variable ret : std_logic;
+   begin
+   if x then ret := '1';  else ret := '0'; end if;
+   return ret;
+   end to_std_logic;
+	
+begin
+	
+	AMIGA_CLK <= not (C1 xor C3);
+	
+	ADDRESS_DECODE: process(AMIGA_CLK)
+	begin
+		if(rising_edge(AMIGA_CLK))then
+			if(AS='0')then
+				AUTOCONFIG_IN_PROGRESS<= autoconfig;
+			else
+				AUTOCONFIG_IN_PROGRESS<= '0';
+			end if;
+				
+			if(BERR='1') then
+				if(A(23 downto 16) = x"E8" and not(AUTO_CONFIG_DONE ="111"))then
+					autoconfig <='1';
+				else
+					autoconfig <='0';
+				end if;
+
+				if(A(23 downto 16) = IDE_BASEADR and SHUT_UP(1) = '0')then					
+					ide <='1';					
+				else
+					ide <='0';
+				end if;				
+			else
+				autoconfig <='0';
+				ide <='0';
+			end if;					
+		end if;				
+	end process ADDRESS_DECODE;
+	
+	--ide
+		-- this is the clocked process
+	ide_rw_gen: process (AMIGA_CLK)
+	begin
+	
+		if rising_edge(AMIGA_CLK) then
+			if	(reset = '0') then
+				IDE_R_S		<= '1';
+				IDE_W_S		<= '1';
+				ROM_OE_S		<= '1';
+				IDE_ENABLE 	<= '1';
+			elsif(AS='0' and ide='1')then
+				if(RW='0')then
+					--the write goes to the hdd!
+					IDE_ENABLE  <= '0'; -- enable IDE on first read
+					IDE_W_S		<= '0';	
+					IDE_R_S		<= '1';
+					ROM_OE_S		<=	'1';
+				else
+					IDE_W_S		<= '1';						
+					IDE_R_S		<= IDE_ENABLE; --read from IDE instead from ROM
+					ROM_OE_S		<=	not IDE_ENABLE;						
+				end if;	
+			else
+				IDE_R_S		<= '1';
+				IDE_W_S		<= '1';
+				ROM_OE_S		<= '1';					
+			end if;
+				
+		end if;
+	end process ide_rw_gen;
+		
+	
+	--autoconfig
+	
+	autoconfig_done: process (reset, AS)
+	begin
+		if	reset = '0' then
+			-- reset active ...
+			AUTO_CONFIG_DONE	<="000";
+		elsif rising_edge(AS) then -- no reset, so wait for rising edge of the nAS		
+			AUTO_CONFIG_DONE <= AUTO_CONFIG_DONE_CYCLE;
+		end if;
+	end process autoconfig_done;
+
+
+	autoconfig_proc: process (reset, AMIGA_CLK)
+	begin
+		if rising_edge(AMIGA_CLK) then -- no reset, so wait for rising edge of the clock		
+			if	reset = '0' then
+				-- reset active ...
+				AUTO_CONFIG_DONE_CYCLE	<="000";
+				Dout1<="1111";
+				--Dout2<="1111";
+				SHUT_UP	<="111";
+				IDE_BASEADR<=x"FF";
+				LAN_BASEADR<=x"FF";
+				CP_BASEADR<=x"FF";
+			elsif(autoconfig= '1' and AS='0') then
+				if(RW='1') then
+					if(AUTO_CONFIG_DONE(0)='0')then
+						case A(6 downto 1) is
+							when "000000"	=> 
+								Dout1 <= 	"1100" ; --ZII, System-Memory, no ROM
+							when "000001"	=> Dout1 <=	"0001" ; --one Card, 64KB =001
+							when "000010"	=> Dout1 <=	"1000" ; --ProductID high nibble : E->0001
+							when "000011"	=> Dout1 <=	"0100" ; --ProductID low nibble: F->0000
+							--when "0001000"	=> Dout1 <=	"1111" ; --Config HIGH: 0x20 and no shut down
+							--when "0001010"	=> Dout1 <=	"1111" ; --Config LOW
+							--when "0010000"	=> Dout1 <=	"1111" ; --Ventor ID 0
+							when "001001"	=> Dout1 <=	"0101" ; --Ventor ID 1
+							when "001010"	=> Dout1 <=	"1110" ; --Ventor ID 2
+							when "001011"	=> Dout1 <=	"0011" ; --Ventor ID 3 : $0A1C: A1K.org
+							--when "0011000"	=> Dout1 <=	"1111" ; --Serial byte 0 (msb) high nibble
+							--when "0011010"	=> Dout1 <=	"1111" ; --Serial byte 0 (msb) low  nibble
+							--when "0011100"	=> Dout1 <=	"1111" ; --Serial byte 1       high nibble
+							--when "0011110"	=> Dout1 <=	"1111" ; --Serial byte 1       low  nibble
+							--when "0100000"	=> Dout1 <=	"1111" ; --Serial byte 2       high nibble
+							--when "0100010"	=> Dout1 <=	"1111" ; --Serial byte 2       low  nibble
+							--when "0100100"	=> Dout1 <=	"1111" ; --Serial byte 3 (lsb) high nibble
+							--when "010001"	=> Dout1 <=	"1000" ; --Serial byte 2       low  nibble
+							when "010011"	=> Dout1 <=	"1110" ; --Serial byte 3 (lsb) low  nibble
+							when "100000"	=> Dout1 <=	"0000" ; --Interrupt config: all zero
+							when "100001"	=> Dout1 <=	"0000" ; --Interrupt config: all zero
+							when others	=> Dout1 <=	"1111" ;
+						end case;	
+					elsif(AUTO_CONFIG_DONE(1)='0')then
+						case A(6 downto 1) is
+							when "000000"	=> 
+								if(AUTOBOOT_OFF ='0') then
+									Dout1 <= 	"1101" ; --ZII, no System-Memory, ROM
+								else
+									Dout1 <= 	"1100" ; --ZII, no System-Memory, no ROM
+								end if;
+							when "000001"	=> Dout1 <=	"0001" ; --one Card, 64kb = 001
+							--when "0000100"	=> Dout2 <=	"1111" ; --ProductID high nibble : F->0000=0
+							when "000011"	=> Dout1 <=	"1001" ; --ProductID low nibble: 9->0110=6
+							--when "0001000"	=>                                                                                                                                                                                                                                                                                                                        Dout <=	"1111" ; --Config HIGH: 0x20 and no shut down
+							--when "0001010"	=> Dout2 <=	"1111" ; --Config LOW
+							--when "0010000"	=> Dout2 <=	"1111" ; --Ventor ID 0
+							when "001001"	=> Dout1 <=	"0111" ; --Ventor ID 1
+							when "001010"	=> Dout1 <=	"1101" ; --Ventor ID 2
+							when "001011"	=> Dout1 <=	"0011" ; --Ventor ID 3 : $082C: BSC
+							when "001100"	=> Dout1 <=	"0100" ; --Serial byte 0 (msb) high nibble
+							when "001101"	=> Dout1 <=	"1110" ; --Serial byte 0 (msb) low  nibble
+							when "001110"	=> Dout1 <=	"1001" ; --Serial byte 1       high nibble
+							when "001111"	=> Dout1 <=	"0100" ; --Serial byte 1       low  nibble
+							--when "0100000"	=> Dout2 <=	"1111" ; --Serial byte 2       high nibble
+							--when "0100010"	=> Dout2 <=	"1111" ; --Serial byte 2       low  nibble
+							when "010010"	=> Dout1 <=	"0100" ; --Serial byte 3 (lsb) high nibble
+							when "010011"	=> Dout1 <=	"1010" ; --Serial byte 3 (lsb) low  nibble: B16B00B5
+							--when "0101000"	=> Dout2 <=	"1111" ; --Rom vector high byte high nibble 
+							--when "0101010"	=> Dout2 <=	"1111" ; --Rom vector high byte low  nibble 
+							--when "0101100"	=> Dout2 <=	"1111" ; --Rom vector low byte high nibble
+							when "010111"	=> Dout1 <=	"1110" ; --Rom vector low byte low  nibble
+							when "100000"	=> Dout1 <=	"0000" ; --Interrupt config: all zero
+							when "100001"	=> Dout1 <=	"0000" ; --Interrupt config: all zero
+							when others	=> Dout1 <=	"1111" ;
+						end case;	
+					elsif(AUTO_CONFIG_DONE(2)='0')then
+						case A(6 downto 1) is
+							when "000000"	=> 
+								Dout1 <= 	"1100" ; --ZII, System-Memory, no ROM
+							when "000001"	=> Dout1 <=	"0001" ; --one Card, 64KB =001
+							when "000010"	=> Dout1 <=	"1000" ; --ProductID high nibble : E->0001
+							when "000011"	=> Dout1 <=	"0011" ; --ProductID low nibble: F->0000
+							--when "0001000"	=> Dout1 <=	"1111" ; --Config HIGH: 0x20 and no shut down
+							--when "0001010"	=> Dout1 <=	"1111" ; --Config LOW
+							--when "0010000"	=> Dout1 <=	"1111" ; --Ventor ID 0
+							when "001001"	=> Dout1 <=	"0101" ; --Ventor ID 1
+							when "001010"	=> Dout1 <=	"1110" ; --Ventor ID 2
+							when "001011"	=> Dout1 <=	"0011" ; --Ventor ID 3 : $0A1C: A1K.org
+							--when "0011000"	=> Dout1 <=	"1111" ; --Serial byte 0 (msb) high nibble
+							--when "0011010"	=> Dout1 <=	"1111" ; --Serial byte 0 (msb) low  nibble
+							--when "0011100"	=> Dout1 <=	"1111" ; --Serial byte 1       high nibble
+							--when "0011110"	=> Dout1 <=	"1111" ; --Serial byte 1       low  nibble
+							--when "0100000"	=> Dout1 <=	"1111" ; --Serial byte 2       high nibble
+							--when "0100010"	=> Dout1 <=	"1111" ; --Serial byte 2       low  nibble
+							--when "0100100"	=> Dout1 <=	"1111" ; --Serial byte 3 (lsb) high nibble
+							--when "010001"	=> Dout1 <=	"1000" ; --Serial byte 2       low  nibble
+							when "010011"	=> Dout1 <=	"1110" ; --Serial byte 3 (lsb) low  nibble
+							when "100000"	=> Dout1 <=	"0000" ; --Interrupt config: all zero
+							when "100001"	=> Dout1 <=	"0000" ; --Interrupt config: all zero
+							when others	=> Dout1 <=	"1111" ;
+						end case;	
+					elsif(AUTO_CONFIG_DONE(1)='0')then
+					end if;
+				else --write
+					if( UDS='0' )then
+						if(AUTO_CONFIG_DONE(0)='0')then
+							if(A (6 downto 1)="100100")then								
+								LAN_BASEADR(7 downto 0)	<= D(15 downto 8); --Base adress
+								AUTO_CONFIG_DONE_CYCLE(0)	<='1'; --done here
+								SHUT_UP(0)				<='0'; --enable board
+							elsif(A (6 downto 1)="100110")then
+								AUTO_CONFIG_DONE_CYCLE(0)	<='1'; --done here
+							end if;
+						elsif(AUTO_CONFIG_DONE(1)='0')then
+	--						if(AUTO_CONFIG_DONE(1)='0')then
+							if(A (6 downto 1)="100100")then
+								IDE_BASEADR(7 downto 0)	<= D(15 downto 8); --Base adress
+								SHUT_UP(1) <= '0'; --enable board
+								AUTO_CONFIG_DONE_CYCLE(1)	<='1'; --done here
+							elsif(A (6 downto 1)="100110")then
+								AUTO_CONFIG_DONE_CYCLE(1)	<='1'; --done here
+							end if;
+						elsif(AUTO_CONFIG_DONE(2)='0')then
+	--						if(AUTO_CONFIG_DONE(1)='0')then
+							if(A (6 downto 1)="100100")then
+								CP_BASEADR(7 downto 0)	<= D(15 downto 8); --Base adress
+								SHUT_UP(2) <= '0'; --enable board
+								AUTO_CONFIG_DONE_CYCLE(2)	<='1'; --done here
+							elsif(A (6 downto 1)="100110")then
+								AUTO_CONFIG_DONE_CYCLE(2)	<='1'; --done here
+							end if;
+						end if;
+					end if;
+				end if;
+			end if;
+		end if;
+	end process autoconfig_proc; --- that's all
+
+
+
+	--signal assignment
+	D	<=	--RAM_D 						when RW='1' and TRANSFER_IN_PROGRES ='1' else
+			Dout1	& "111111111111" 	when RW='1' and AUTOCONFIG_IN_PROGRESS ='1' else
+			"ZZZZZZZZZZZZZZZZ";
+--
+--	DRAM <= 	D when RW='0' and AS ='0' else
+--				"ZZZZZZZZZZZZZZZZ";
+								
+	IDE_W <=	IDE_W_S;
+	IDE_R <=	IDE_R_S;
+	IDE_CS(0)<= not(A(12));			
+	IDE_CS(1)<= not(A(13));
+	IDE_A(0)	<= A(9);
+	IDE_A(1)	<= A(10);
+	IDE_A(2)	<= A(11);
+	ROM_B	<= "00";
+	ROM_OE	<= ROM_OE_S;				
+
+	
+--	DTACK <= DTACK_S when --TRANSFER_IN_PROGRES ='1' or 
+--								AUTOCONFIG_IN_PROGRES ='1' 
+--						  else 'Z';
+	
+	DTACK <= 'Z';
 
 end Behavioral;
 
diff --git a/Logic/LAN_IDE/LAN_IDE_CP.vm6 b/Logic/LAN_IDE/LAN_IDE_CP.vm6
new file mode 100644
index 0000000..9147c94
--- /dev/null
+++ b/Logic/LAN_IDE/LAN_IDE_CP.vm6
@@ -0,0 +1,4110 @@
+NDS Database:  version P.68d
+
+NDS_INFO | xc9500xl | 95144XL144TQ | XC95144XL-10-TQ144
+
+DEVICE | 95144XL | 95144XL144TQ | 
+
+NETWORK | LAN_IDE_CP | 0 | 0 | 16391
+
+INPUT_INSTANCE | 0 | 0 | NULL | RESET_IBUF | LAN_IDE_CP_COPY_0_COPY_0 | 16 | 1 | 2
+INPUT_NODE_TYPE | 0 | 5 | II_IN
+NODE | RESET | 5041 | PI | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE
+OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX
+NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX
+OUTPUT_NODE_TYPE | 9 | 5 | II_FSRINV
+NODE | FSR-IO_0 | 4911 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 9 | 5 | II_FSRINV
+
+INPUT_INSTANCE | 0 | 0 | NULL | RW_IBUF | LAN_IDE_CP_COPY_0_COPY_0 | 16 | 1 | 1
+INPUT_NODE_TYPE | 0 | 5 | II_IN
+NODE | RW | 5043 | PI | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE
+OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX
+NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX
+
+INPUT_INSTANCE | 0 | 0 | NULL | A_1_IBUF | LAN_IDE_CP_COPY_0_COPY_0 | 16 | 1 | 1
+INPUT_NODE_TYPE | 0 | 5 | II_IN
+NODE | A<1> | 5047 | PI | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE
+OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX
+NODE | A_1_IBUF | 4929 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_1_IBUF | 0 | 5 | II_IMUX
+
+INPUT_INSTANCE | 0 | 0 | NULL | A_2_IBUF | LAN_IDE_CP_COPY_0_COPY_0 | 16 | 1 | 1
+INPUT_NODE_TYPE | 0 | 5 | II_IN
+NODE | A<2> | 5050 | PI | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE
+OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX
+NODE | A_2_IBUF | 4932 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX
+
+INPUT_INSTANCE | 0 | 0 | NULL | A_5_IBUF | LAN_IDE_CP_COPY_0_COPY_0 | 16 | 1 | 1
+INPUT_NODE_TYPE | 0 | 5 | II_IN
+NODE | A<5> | 5045 | PI | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE
+OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX
+NODE | A_5_IBUF | 4927 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX
+
+INPUT_INSTANCE | 0 | 0 | NULL | A_6_IBUF | LAN_IDE_CP_COPY_0_COPY_0 | 16 | 1 | 1
+INPUT_NODE_TYPE | 0 | 5 | II_IN
+NODE | A<6> | 5048 | PI | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE
+OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX
+NODE | A_6_IBUF | 4930 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_6_IBUF | 0 | 5 | II_IMUX
+
+INPUT_INSTANCE | 0 | 0 | NULL | A_3_IBUF | LAN_IDE_CP_COPY_0_COPY_0 | 16 | 1 | 1
+INPUT_NODE_TYPE | 0 | 5 | II_IN
+NODE | A<3> | 5049 | PI | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE
+OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX
+NODE | A_3_IBUF | 4931 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX
+
+INPUT_INSTANCE | 0 | 0 | NULL | AS_IBUF | LAN_IDE_CP_COPY_0_COPY_0 | 16 | 1 | 1
+INPUT_NODE_TYPE | 0 | 5 | II_IN
+NODE | AS | 5044 | PI | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE
+OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX
+NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX
+
+INPUT_INSTANCE | 0 | 0 | NULL | A_4_IBUF | LAN_IDE_CP_COPY_0_COPY_0 | 16 | 1 | 1
+INPUT_NODE_TYPE | 0 | 5 | II_IN
+NODE | A<4> | 5046 | PI | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE
+OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX
+NODE | A_4_IBUF | 4928 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_4_IBUF | 0 | 5 | II_IMUX
+
+MACROCELL_INSTANCE | NoOpt+Inv+PrldLow+PinTrst+OptxMapped | D<13>_BUFR.MC | LAN_IDE_CP_COPY_0_COPY_0 | 2155889936 | 17 | 1
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_5_IBUF | 4927 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_1_IBUF | 4929 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_1_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_6_IBUF | 4930 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_6_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_3_IBUF | 4931 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_2_IBUF | 4932 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<1> | 4938 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<1>.Q | AUTO_CONFIG_DONE<1> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<2> | 4939 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<2>.Q | AUTO_CONFIG_DONE<2> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | autoconfig | 4957 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.Q | autoconfig | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_4_IBUF | 4928 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_4_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<0> | 4937 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<0>.Q | AUTO_CONFIG_DONE<0> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | Dout1<1>.UIM | 4913 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | HPART_CREATED_2.Q | _12_ | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | ide/ide_CLKF.UIM | 5040 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ide/ide_CLKF.Q | ide/ide_CLKF | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | EXP17_.EXP | 5371 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | EXP17_.EXP | EXP17_ | 4 | 0 | MC_EXPORT
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | N1$BUF2.EXP | 5372 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | N1$BUF2.EXP | N1$BUF2 | 4 | 0 | MC_EXPORT
+OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
+NODE | D<13>_BUFR | 5335 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | Dout1<1>.Q | D<13>_BUFR.MC | 1 | 0 | MC_UIM
+
+SIGNAL_INSTANCE | Dout1<1>.SI | D<13>_BUFR.MC | 0 | 17 | 3
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_5_IBUF | 4927 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_1_IBUF | 4929 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_1_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_6_IBUF | 4930 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_6_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_3_IBUF | 4931 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_2_IBUF | 4932 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<1> | 4938 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<1>.Q | AUTO_CONFIG_DONE<1> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<2> | 4939 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<2>.Q | AUTO_CONFIG_DONE<2> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | autoconfig | 4957 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.Q | autoconfig | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_4_IBUF | 4928 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_4_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<0> | 4937 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<0>.Q | AUTO_CONFIG_DONE<0> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | Dout1<1>.UIM | 4913 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | HPART_CREATED_2.Q | _12_ | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | ide/ide_CLKF.UIM | 5040 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ide/ide_CLKF.Q | ide/ide_CLKF | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | EXP17_.EXP | 5371 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | EXP17_.EXP | EXP17_ | 4 | 0 | MC_EXPORT
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | N1$BUF2.EXP | 5372 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | N1$BUF2.EXP | N1$BUF2 | 4 | 0 | MC_EXPORT
+OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
+SIGNAL | NODE | Dout1<1>.D1 | 5069 | ? | 0 | 4096 | D<13>_BUFR.MC | NULL | NULL | Dout1<1>.SI | 1 | 9 | MC_SI_D1
+SPPTERM | 0 | IV_ZERO
+OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
+SIGNAL | NODE | Dout1<1>.D2 | 5070 | ? | 0 | 4096 | D<13>_BUFR.MC | NULL | NULL | Dout1<1>.SI | 2 | 9 | MC_SI_D2
+SPPTERM | 1 | IV_TRUE | EXP17_.EXP
+SPPTERM | 1 | IV_TRUE | N1$BUF2.EXP
+SPPTERM | 3 | IV_TRUE | RESET_IBUF | IV_FALSE | Dout1<1>.UIM | IV_TRUE | AS_IBUF
+SPPTERM | 3 | IV_TRUE | RESET_IBUF | IV_FALSE | Dout1<1>.UIM | IV_FALSE | autoconfig
+SPPTERM | 11 | IV_TRUE | RESET_IBUF | IV_TRUE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_TRUE | A_4_IBUF | IV_FALSE | A_6_IBUF | IV_TRUE | A_3_IBUF | IV_TRUE | A_2_IBUF | IV_TRUE | AUTO_CONFIG_DONE<0> | IV_FALSE | AUTO_CONFIG_DONE<1> | IV_TRUE | autoconfig
+SPPTERM | 11 | IV_TRUE | RESET_IBUF | IV_TRUE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_TRUE | A_1_IBUF | IV_FALSE | A_6_IBUF | IV_FALSE | A_3_IBUF | IV_FALSE | A_2_IBUF | IV_TRUE | AUTO_CONFIG_DONE<1> | IV_FALSE | AUTO_CONFIG_DONE<2> | IV_TRUE | autoconfig
+OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF
+SIGNAL | NODE | Dout1<1>.CLKF | 5071 | ? | 0 | 4096 | D<13>_BUFR.MC | NULL | NULL | Dout1<1>.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_TRUE | ide/ide_CLKF.UIM
+
+SRFF_INSTANCE | Dout1<1>.REG | D<13>_BUFR.MC | 0 | 2 | 1
+INPUT_NODE_TYPE | 0 | 8 | SRFF_D
+NODE | Dout1<1>.D | 5068 | ? | 0 | 0 | D<13>_BUFR.MC | NULL | NULL | Dout1<1>.XOR | 0 | 7 | ALU_F
+INPUT_NODE_TYPE | 1 | 8 | SRFF_C
+SIGNAL | NODE | Dout1<1>.CLKF | 5071 | ? | 0 | 4096 | D<13>_BUFR.MC | NULL | NULL | Dout1<1>.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_TRUE | ide/ide_CLKF.UIM
+OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
+NODE | Dout1<1>.Q | 5074 | ? | 0 | 0 | D<13>_BUFR.MC | NULL | NULL | Dout1<1>.REG | 0 | 8 | SRFF_Q
+
+INPUT_INSTANCE | 0 | 0 | NULL | AUTOBOOT_OFF_IBUF | LAN_IDE_CP_COPY_0_COPY_0 | 16 | 1 | 1
+INPUT_NODE_TYPE | 0 | 5 | II_IN
+NODE | AUTOBOOT_OFF | 5055 | PI | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE
+OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX
+NODE | AUTOBOOT_OFF_IBUF | 4953 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AUTOBOOT_OFF_IBUF | 0 | 5 | II_IMUX
+
+MACROCELL_INSTANCE | NoOpt+Inv+PrldLow+PinTrst+OptxMapped | D<12>_BUFR.MC | LAN_IDE_CP_COPY_0_COPY_0 | 2155889936 | 17 | 1
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_5_IBUF | 4927 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_4_IBUF | 4928 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_4_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_1_IBUF | 4929 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_1_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_3_IBUF | 4931 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_2_IBUF | 4932 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<1> | 4938 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<1>.Q | AUTO_CONFIG_DONE<1> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<2> | 4939 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<2>.Q | AUTO_CONFIG_DONE<2> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | autoconfig | 4957 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.Q | autoconfig | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_6_IBUF | 4930 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_6_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<0> | 4937 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<0>.Q | AUTO_CONFIG_DONE<0> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTOBOOT_OFF_IBUF | 4953 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AUTOBOOT_OFF_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | IDE_CS_1_OBUF.EXP | 5353 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_CS_1_OBUF.EXP | IDE_CS_1_OBUF | 4 | 0 | MC_EXPORT
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | ide/ide_CLKF.UIM | 5040 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ide/ide_CLKF.Q | ide/ide_CLKF | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | EXP14_.EXP | 5357 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | EXP14_.EXP | EXP14_ | 4 | 0 | MC_EXPORT
+OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
+NODE | D<12>_BUFR | 5319 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | Dout1<0>.Q | D<12>_BUFR.MC | 1 | 0 | MC_UIM
+
+SIGNAL_INSTANCE | Dout1<0>.SI | D<12>_BUFR.MC | 0 | 17 | 3
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_5_IBUF | 4927 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_4_IBUF | 4928 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_4_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_1_IBUF | 4929 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_1_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_3_IBUF | 4931 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_2_IBUF | 4932 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<1> | 4938 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<1>.Q | AUTO_CONFIG_DONE<1> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<2> | 4939 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<2>.Q | AUTO_CONFIG_DONE<2> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | autoconfig | 4957 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.Q | autoconfig | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_6_IBUF | 4930 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_6_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<0> | 4937 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<0>.Q | AUTO_CONFIG_DONE<0> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTOBOOT_OFF_IBUF | 4953 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AUTOBOOT_OFF_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | IDE_CS_1_OBUF.EXP | 5353 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_CS_1_OBUF.EXP | IDE_CS_1_OBUF | 4 | 0 | MC_EXPORT
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | ide/ide_CLKF.UIM | 5040 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ide/ide_CLKF.Q | ide/ide_CLKF | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | EXP14_.EXP | 5357 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | EXP14_.EXP | EXP14_ | 4 | 0 | MC_EXPORT
+OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
+SIGNAL | NODE | Dout1<0>.D1 | 5076 | ? | 0 | 4096 | D<12>_BUFR.MC | NULL | NULL | Dout1<0>.SI | 1 | 9 | MC_SI_D1
+SPPTERM | 0 | IV_ZERO
+OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
+SIGNAL | NODE | Dout1<0>.D2 | 5077 | ? | 0 | 4096 | D<12>_BUFR.MC | NULL | NULL | Dout1<0>.SI | 2 | 9 | MC_SI_D2
+SPPTERM | 1 | IV_TRUE | IDE_CS_1_OBUF.EXP
+SPPTERM | 1 | IV_TRUE | EXP14_.EXP
+SPPTERM | 10 | IV_TRUE | RESET_IBUF | IV_TRUE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_4_IBUF | IV_TRUE | A_1_IBUF | IV_FALSE | A_6_IBUF | IV_FALSE | A_3_IBUF | IV_TRUE | A_2_IBUF | IV_FALSE | AUTO_CONFIG_DONE<0> | IV_TRUE | autoconfig
+SPPTERM | 11 | IV_TRUE | RESET_IBUF | IV_TRUE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_TRUE | A_4_IBUF | IV_FALSE | A_6_IBUF | IV_TRUE | A_3_IBUF | IV_FALSE | A_2_IBUF | IV_TRUE | AUTO_CONFIG_DONE<0> | IV_FALSE | AUTO_CONFIG_DONE<1> | IV_TRUE | autoconfig
+SPPTERM | 11 | IV_TRUE | RESET_IBUF | IV_TRUE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_FALSE | A_4_IBUF | IV_FALSE | A_1_IBUF | IV_FALSE | A_3_IBUF | IV_FALSE | A_2_IBUF | IV_TRUE | AUTO_CONFIG_DONE<1> | IV_FALSE | AUTO_CONFIG_DONE<2> | IV_TRUE | autoconfig
+SPPTERM | 11 | IV_TRUE | RESET_IBUF | IV_TRUE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_FALSE | A_4_IBUF | IV_FALSE | A_1_IBUF | IV_FALSE | A_3_IBUF | IV_FALSE | A_2_IBUF | IV_FALSE | AUTO_CONFIG_DONE<1> | IV_TRUE | AUTOBOOT_OFF_IBUF | IV_TRUE | autoconfig
+OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF
+SIGNAL | NODE | Dout1<0>.CLKF | 5078 | ? | 0 | 4096 | D<12>_BUFR.MC | NULL | NULL | Dout1<0>.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_TRUE | ide/ide_CLKF.UIM
+
+SRFF_INSTANCE | Dout1<0>.REG | D<12>_BUFR.MC | 0 | 2 | 1
+INPUT_NODE_TYPE | 0 | 8 | SRFF_D
+NODE | Dout1<0>.D | 5075 | ? | 0 | 0 | D<12>_BUFR.MC | NULL | NULL | Dout1<0>.XOR | 0 | 7 | ALU_F
+INPUT_NODE_TYPE | 1 | 8 | SRFF_C
+SIGNAL | NODE | Dout1<0>.CLKF | 5078 | ? | 0 | 4096 | D<12>_BUFR.MC | NULL | NULL | Dout1<0>.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_TRUE | ide/ide_CLKF.UIM
+OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
+NODE | Dout1<0>.Q | 5081 | ? | 0 | 0 | D<12>_BUFR.MC | NULL | NULL | Dout1<0>.REG | 0 | 8 | SRFF_Q
+
+MACROCELL_INSTANCE | NoOpt+Inv+PrldLow+PinTrst+OptxMapped | D<14>_BUFR.MC | LAN_IDE_CP_COPY_0_COPY_0 | 2155889936 | 16 | 1
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_5_IBUF | 4927 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_4_IBUF | 4928 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_4_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_6_IBUF | 4930 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_6_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_3_IBUF | 4931 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_2_IBUF | 4932 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<0> | 4937 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<0>.Q | AUTO_CONFIG_DONE<0> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<1> | 4938 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<1>.Q | AUTO_CONFIG_DONE<1> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<2> | 4939 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<2>.Q | AUTO_CONFIG_DONE<2> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | autoconfig | 4957 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.Q | autoconfig | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_1_IBUF | 4929 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_1_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | EXP15_.EXP | 5366 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | EXP15_.EXP | EXP15_ | 4 | 0 | MC_EXPORT
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | ide/ide_CLKF.UIM | 5040 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ide/ide_CLKF.Q | ide/ide_CLKF | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | EXP18_.EXP | 5373 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | EXP18_.EXP | EXP18_ | 4 | 0 | MC_EXPORT
+OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
+NODE | D<14>_BUFR | 5327 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | Dout1<2>.Q | D<14>_BUFR.MC | 1 | 0 | MC_UIM
+
+SIGNAL_INSTANCE | Dout1<2>.SI | D<14>_BUFR.MC | 0 | 16 | 3
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_5_IBUF | 4927 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_4_IBUF | 4928 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_4_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_6_IBUF | 4930 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_6_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_3_IBUF | 4931 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_2_IBUF | 4932 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<0> | 4937 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<0>.Q | AUTO_CONFIG_DONE<0> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<1> | 4938 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<1>.Q | AUTO_CONFIG_DONE<1> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<2> | 4939 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<2>.Q | AUTO_CONFIG_DONE<2> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | autoconfig | 4957 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.Q | autoconfig | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_1_IBUF | 4929 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_1_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | EXP15_.EXP | 5366 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | EXP15_.EXP | EXP15_ | 4 | 0 | MC_EXPORT
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | ide/ide_CLKF.UIM | 5040 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ide/ide_CLKF.Q | ide/ide_CLKF | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | EXP18_.EXP | 5373 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | EXP18_.EXP | EXP18_ | 4 | 0 | MC_EXPORT
+OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
+SIGNAL | NODE | Dout1<2>.D1 | 5083 | ? | 0 | 4096 | D<14>_BUFR.MC | NULL | NULL | Dout1<2>.SI | 1 | 9 | MC_SI_D1
+SPPTERM | 0 | IV_ZERO
+OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
+SIGNAL | NODE | Dout1<2>.D2 | 5084 | ? | 0 | 4096 | D<14>_BUFR.MC | NULL | NULL | Dout1<2>.SI | 2 | 9 | MC_SI_D2
+SPPTERM | 1 | IV_TRUE | EXP15_.EXP
+SPPTERM | 1 | IV_TRUE | EXP18_.EXP
+SPPTERM | 10 | IV_TRUE | RESET_IBUF | IV_TRUE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_FALSE | A_4_IBUF | IV_TRUE | A_1_IBUF | IV_FALSE | A_3_IBUF | IV_FALSE | A_2_IBUF | IV_FALSE | AUTO_CONFIG_DONE<1> | IV_TRUE | autoconfig
+SPPTERM | 10 | IV_TRUE | RESET_IBUF | IV_TRUE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_FALSE | A_4_IBUF | IV_TRUE | A_1_IBUF | IV_FALSE | A_3_IBUF | IV_FALSE | A_2_IBUF | IV_FALSE | AUTO_CONFIG_DONE<2> | IV_TRUE | autoconfig
+SPPTERM | 11 | IV_TRUE | RESET_IBUF | IV_TRUE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_TRUE | A_1_IBUF | IV_FALSE | A_6_IBUF | IV_FALSE | A_3_IBUF | IV_TRUE | A_2_IBUF | IV_TRUE | AUTO_CONFIG_DONE<0> | IV_FALSE | AUTO_CONFIG_DONE<1> | IV_TRUE | autoconfig
+SPPTERM | 12 | IV_TRUE | RESET_IBUF | IV_TRUE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_FALSE | A_4_IBUF | IV_FALSE | A_6_IBUF | IV_FALSE | A_3_IBUF | IV_TRUE | A_2_IBUF | IV_TRUE | AUTO_CONFIG_DONE<0> | IV_TRUE | AUTO_CONFIG_DONE<1> | IV_FALSE | AUTO_CONFIG_DONE<2> | IV_TRUE | autoconfig
+OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF
+SIGNAL | NODE | Dout1<2>.CLKF | 5085 | ? | 0 | 4096 | D<14>_BUFR.MC | NULL | NULL | Dout1<2>.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_TRUE | ide/ide_CLKF.UIM
+
+SRFF_INSTANCE | Dout1<2>.REG | D<14>_BUFR.MC | 0 | 2 | 1
+INPUT_NODE_TYPE | 0 | 8 | SRFF_D
+NODE | Dout1<2>.D | 5082 | ? | 0 | 0 | D<14>_BUFR.MC | NULL | NULL | Dout1<2>.XOR | 0 | 7 | ALU_F
+INPUT_NODE_TYPE | 1 | 8 | SRFF_C
+SIGNAL | NODE | Dout1<2>.CLKF | 5085 | ? | 0 | 4096 | D<14>_BUFR.MC | NULL | NULL | Dout1<2>.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_TRUE | ide/ide_CLKF.UIM
+OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
+NODE | Dout1<2>.Q | 5088 | ? | 0 | 0 | D<14>_BUFR.MC | NULL | NULL | Dout1<2>.REG | 0 | 8 | SRFF_Q
+
+MACROCELL_INSTANCE | NoOpt+Inv+PrldLow+PinTrst+OptxMapped | D<15>_BUFR.MC | LAN_IDE_CP_COPY_0_COPY_0 | 2155889936 | 14 | 1
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_5_IBUF | 4927 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_1_IBUF | 4929 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_1_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_6_IBUF | 4930 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_6_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_3_IBUF | 4931 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_2_IBUF | 4932 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<1> | 4938 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<1>.Q | AUTO_CONFIG_DONE<1> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | autoconfig | 4957 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.Q | autoconfig | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | Dout1<3>.UIM | 4922 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | HPART_CREATED_3.Q | _13_ | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | EXP22_.EXP | 5384 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | EXP22_.EXP | EXP22_ | 4 | 0 | MC_EXPORT
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | EXP23_.EXP | 5385 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | EXP23_.EXP | EXP23_ | 4 | 0 | MC_EXPORT
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | ide/ide_CLKF.UIM | 5040 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ide/ide_CLKF.Q | ide/ide_CLKF | 1 | 0 | MC_UIM
+OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
+NODE | D<15>_BUFR | 5343 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | Dout1<3>.Q | D<15>_BUFR.MC | 1 | 0 | MC_UIM
+
+SIGNAL_INSTANCE | Dout1<3>.SI | D<15>_BUFR.MC | 0 | 14 | 3
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_5_IBUF | 4927 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_1_IBUF | 4929 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_1_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_6_IBUF | 4930 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_6_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_3_IBUF | 4931 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_2_IBUF | 4932 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<1> | 4938 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<1>.Q | AUTO_CONFIG_DONE<1> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | autoconfig | 4957 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.Q | autoconfig | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | Dout1<3>.UIM | 4922 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | HPART_CREATED_3.Q | _13_ | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | EXP22_.EXP | 5384 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | EXP22_.EXP | EXP22_ | 4 | 0 | MC_EXPORT
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | EXP23_.EXP | 5385 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | EXP23_.EXP | EXP23_ | 4 | 0 | MC_EXPORT
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | ide/ide_CLKF.UIM | 5040 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ide/ide_CLKF.Q | ide/ide_CLKF | 1 | 0 | MC_UIM
+OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
+SIGNAL | NODE | Dout1<3>.D1 | 5090 | ? | 0 | 4096 | D<15>_BUFR.MC | NULL | NULL | Dout1<3>.SI | 1 | 9 | MC_SI_D1
+SPPTERM | 0 | IV_ZERO
+OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
+SIGNAL | NODE | Dout1<3>.D2 | 5091 | ? | 0 | 4096 | D<15>_BUFR.MC | NULL | NULL | Dout1<3>.SI | 2 | 9 | MC_SI_D2
+SPPTERM | 1 | IV_TRUE | EXP22_.EXP
+SPPTERM | 1 | IV_TRUE | EXP23_.EXP
+SPPTERM | 3 | IV_TRUE | RESET_IBUF | IV_FALSE | Dout1<3>.UIM | IV_FALSE | RW_IBUF
+SPPTERM | 3 | IV_TRUE | RESET_IBUF | IV_FALSE | Dout1<3>.UIM | IV_TRUE | AS_IBUF
+SPPTERM | 3 | IV_TRUE | RESET_IBUF | IV_FALSE | Dout1<3>.UIM | IV_FALSE | autoconfig
+SPPTERM | 10 | IV_TRUE | RESET_IBUF | IV_TRUE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_TRUE | A_1_IBUF | IV_FALSE | A_6_IBUF | IV_FALSE | A_3_IBUF | IV_FALSE | A_2_IBUF | IV_FALSE | AUTO_CONFIG_DONE<1> | IV_TRUE | autoconfig
+OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF
+SIGNAL | NODE | Dout1<3>.CLKF | 5092 | ? | 0 | 4096 | D<15>_BUFR.MC | NULL | NULL | Dout1<3>.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_TRUE | ide/ide_CLKF.UIM
+
+SRFF_INSTANCE | Dout1<3>.REG | D<15>_BUFR.MC | 0 | 2 | 1
+INPUT_NODE_TYPE | 0 | 8 | SRFF_D
+NODE | Dout1<3>.D | 5089 | ? | 0 | 0 | D<15>_BUFR.MC | NULL | NULL | Dout1<3>.XOR | 0 | 7 | ALU_F
+INPUT_NODE_TYPE | 1 | 8 | SRFF_C
+SIGNAL | NODE | Dout1<3>.CLKF | 5092 | ? | 0 | 4096 | D<15>_BUFR.MC | NULL | NULL | Dout1<3>.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_TRUE | ide/ide_CLKF.UIM
+OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
+NODE | Dout1<3>.Q | 5095 | ? | 0 | 0 | D<15>_BUFR.MC | NULL | NULL | Dout1<3>.REG | 0 | 8 | SRFF_Q
+
+INPUT_INSTANCE | 0 | 0 | NULL | UDS_IBUF | LAN_IDE_CP_COPY_0_COPY_0 | 16 | 1 | 1
+INPUT_NODE_TYPE | 0 | 5 | II_IN
+NODE | UDS | 5042 | PI | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE
+OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX
+NODE | UDS_IBUF | 4924 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | UDS_IBUF | 0 | 5 | II_IMUX
+
+INPUT_INSTANCE | 0 | 0 | NULL | A_23_IBUF | LAN_IDE_CP_COPY_0_COPY_0 | 16 | 1 | 1
+INPUT_NODE_TYPE | 0 | 5 | II_IN
+NODE | A<23> | 5051 | PI | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE
+OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX
+NODE | A_23_IBUF | 4933 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_23_IBUF | 0 | 5 | II_IMUX
+
+INPUT_INSTANCE | 0 | 0 | NULL | A_22_IBUF | LAN_IDE_CP_COPY_0_COPY_0 | 16 | 1 | 1
+INPUT_NODE_TYPE | 0 | 5 | II_IN
+NODE | A<22> | 5052 | PI | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE
+OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX
+NODE | A_22_IBUF | 4934 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_22_IBUF | 0 | 5 | II_IMUX
+
+INPUT_INSTANCE | 0 | 0 | NULL | A_21_IBUF | LAN_IDE_CP_COPY_0_COPY_0 | 16 | 1 | 1
+INPUT_NODE_TYPE | 0 | 5 | II_IN
+NODE | A<21> | 5053 | PI | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE
+OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX
+NODE | A_21_IBUF | 4935 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_21_IBUF | 0 | 5 | II_IMUX
+
+INPUT_INSTANCE | 0 | 0 | NULL | A_19_IBUF | LAN_IDE_CP_COPY_0_COPY_0 | 16 | 1 | 1
+INPUT_NODE_TYPE | 0 | 5 | II_IN
+NODE | A<19> | 5054 | PI | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE
+OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX
+NODE | A_19_IBUF | 4936 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_19_IBUF | 0 | 5 | II_IMUX
+
+MACROCELL_INSTANCE | PrldLow+OptxMapped | AUTO_CONFIG_DONE<0> | LAN_IDE_CP_COPY_0_COPY_0 | 2155873280 | 3 | 1
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE_CYCLE<0> | 4940 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE_CYCLE<0>.Q | AUTO_CONFIG_DONE_CYCLE<0> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | FSR-IO_0 | 4911 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 9 | 5 | II_FSRINV
+OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
+NODE | AUTO_CONFIG_DONE<0> | 4937 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<0>.Q | AUTO_CONFIG_DONE<0> | 1 | 0 | MC_UIM
+
+SIGNAL_INSTANCE | AUTO_CONFIG_DONE<0>.SI | AUTO_CONFIG_DONE<0> | 0 | 2 | 3
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE_CYCLE<0> | 4940 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE_CYCLE<0>.Q | AUTO_CONFIG_DONE_CYCLE<0> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX
+OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
+SIGNAL | NODE | AUTO_CONFIG_DONE<0>.D1 | 5097 | ? | 0 | 4096 | AUTO_CONFIG_DONE<0> | NULL | NULL | AUTO_CONFIG_DONE<0>.SI | 1 | 9 | MC_SI_D1
+SPPTERM | 0 | IV_ZERO
+OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
+SIGNAL | NODE | AUTO_CONFIG_DONE<0>.D2 | 5098 | ? | 0 | 4096 | AUTO_CONFIG_DONE<0> | NULL | NULL | AUTO_CONFIG_DONE<0>.SI | 2 | 9 | MC_SI_D2
+SPPTERM | 1 | IV_TRUE | AUTO_CONFIG_DONE_CYCLE<0>
+OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF
+SIGNAL | NODE | AUTO_CONFIG_DONE<0>.CLKF | 5099 | ? | 0 | 4096 | AUTO_CONFIG_DONE<0> | NULL | NULL | AUTO_CONFIG_DONE<0>.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_TRUE | AS_IBUF
+
+SRFF_INSTANCE | AUTO_CONFIG_DONE<0>.REG | AUTO_CONFIG_DONE<0> | 0 | 3 | 1
+INPUT_NODE_TYPE | 0 | 8 | SRFF_D
+NODE | AUTO_CONFIG_DONE<0>.D | 5096 | ? | 0 | 0 | AUTO_CONFIG_DONE<0> | NULL | NULL | AUTO_CONFIG_DONE<0>.XOR | 0 | 7 | ALU_F
+INPUT_NODE_TYPE | 1 | 8 | SRFF_C
+SIGNAL | NODE | AUTO_CONFIG_DONE<0>.CLKF | 5099 | ? | 0 | 4096 | AUTO_CONFIG_DONE<0> | NULL | NULL | AUTO_CONFIG_DONE<0>.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_TRUE | AS_IBUF
+INPUT_NODE_TYPE | 3 | 8 | SRFF_R
+NODE | FSR-IO_0 | 4911 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 9 | 5 | II_FSRINV
+OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
+NODE | AUTO_CONFIG_DONE<0>.Q | 5100 | ? | 0 | 0 | AUTO_CONFIG_DONE<0> | NULL | NULL | AUTO_CONFIG_DONE<0>.REG | 0 | 8 | SRFF_Q
+
+MACROCELL_INSTANCE | PrldLow+OptxMapped | AUTO_CONFIG_DONE<1> | LAN_IDE_CP_COPY_0_COPY_0 | 2155873280 | 3 | 1
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE_CYCLE<1> | 4941 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE_CYCLE<1>.Q | AUTO_CONFIG_DONE_CYCLE<1> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | FSR-IO_0 | 4911 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 9 | 5 | II_FSRINV
+OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
+NODE | AUTO_CONFIG_DONE<1> | 4938 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<1>.Q | AUTO_CONFIG_DONE<1> | 1 | 0 | MC_UIM
+
+SIGNAL_INSTANCE | AUTO_CONFIG_DONE<1>.SI | AUTO_CONFIG_DONE<1> | 0 | 2 | 3
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE_CYCLE<1> | 4941 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE_CYCLE<1>.Q | AUTO_CONFIG_DONE_CYCLE<1> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX
+OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
+SIGNAL | NODE | AUTO_CONFIG_DONE<1>.D1 | 5102 | ? | 0 | 4096 | AUTO_CONFIG_DONE<1> | NULL | NULL | AUTO_CONFIG_DONE<1>.SI | 1 | 9 | MC_SI_D1
+SPPTERM | 0 | IV_ZERO
+OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
+SIGNAL | NODE | AUTO_CONFIG_DONE<1>.D2 | 5103 | ? | 0 | 4096 | AUTO_CONFIG_DONE<1> | NULL | NULL | AUTO_CONFIG_DONE<1>.SI | 2 | 9 | MC_SI_D2
+SPPTERM | 1 | IV_TRUE | AUTO_CONFIG_DONE_CYCLE<1>
+OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF
+SIGNAL | NODE | AUTO_CONFIG_DONE<1>.CLKF | 5104 | ? | 0 | 4096 | AUTO_CONFIG_DONE<1> | NULL | NULL | AUTO_CONFIG_DONE<1>.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_TRUE | AS_IBUF
+
+SRFF_INSTANCE | AUTO_CONFIG_DONE<1>.REG | AUTO_CONFIG_DONE<1> | 0 | 3 | 1
+INPUT_NODE_TYPE | 0 | 8 | SRFF_D
+NODE | AUTO_CONFIG_DONE<1>.D | 5101 | ? | 0 | 0 | AUTO_CONFIG_DONE<1> | NULL | NULL | AUTO_CONFIG_DONE<1>.XOR | 0 | 7 | ALU_F
+INPUT_NODE_TYPE | 1 | 8 | SRFF_C
+SIGNAL | NODE | AUTO_CONFIG_DONE<1>.CLKF | 5104 | ? | 0 | 4096 | AUTO_CONFIG_DONE<1> | NULL | NULL | AUTO_CONFIG_DONE<1>.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_TRUE | AS_IBUF
+INPUT_NODE_TYPE | 3 | 8 | SRFF_R
+NODE | FSR-IO_0 | 4911 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 9 | 5 | II_FSRINV
+OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
+NODE | AUTO_CONFIG_DONE<1>.Q | 5105 | ? | 0 | 0 | AUTO_CONFIG_DONE<1> | NULL | NULL | AUTO_CONFIG_DONE<1>.REG | 0 | 8 | SRFF_Q
+
+MACROCELL_INSTANCE | PrldLow+OptxMapped | AUTO_CONFIG_DONE<2> | LAN_IDE_CP_COPY_0_COPY_0 | 2155873280 | 3 | 1
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE_CYCLE<2> | 4942 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE_CYCLE<2>.Q | AUTO_CONFIG_DONE_CYCLE<2> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | FSR-IO_0 | 4911 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 9 | 5 | II_FSRINV
+OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
+NODE | AUTO_CONFIG_DONE<2> | 4939 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<2>.Q | AUTO_CONFIG_DONE<2> | 1 | 0 | MC_UIM
+
+SIGNAL_INSTANCE | AUTO_CONFIG_DONE<2>.SI | AUTO_CONFIG_DONE<2> | 0 | 2 | 3
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE_CYCLE<2> | 4942 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE_CYCLE<2>.Q | AUTO_CONFIG_DONE_CYCLE<2> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX
+OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
+SIGNAL | NODE | AUTO_CONFIG_DONE<2>.D1 | 5107 | ? | 0 | 4096 | AUTO_CONFIG_DONE<2> | NULL | NULL | AUTO_CONFIG_DONE<2>.SI | 1 | 9 | MC_SI_D1
+SPPTERM | 0 | IV_ZERO
+OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
+SIGNAL | NODE | AUTO_CONFIG_DONE<2>.D2 | 5108 | ? | 0 | 4096 | AUTO_CONFIG_DONE<2> | NULL | NULL | AUTO_CONFIG_DONE<2>.SI | 2 | 9 | MC_SI_D2
+SPPTERM | 1 | IV_TRUE | AUTO_CONFIG_DONE_CYCLE<2>
+OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF
+SIGNAL | NODE | AUTO_CONFIG_DONE<2>.CLKF | 5109 | ? | 0 | 4096 | AUTO_CONFIG_DONE<2> | NULL | NULL | AUTO_CONFIG_DONE<2>.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_TRUE | AS_IBUF
+
+SRFF_INSTANCE | AUTO_CONFIG_DONE<2>.REG | AUTO_CONFIG_DONE<2> | 0 | 3 | 1
+INPUT_NODE_TYPE | 0 | 8 | SRFF_D
+NODE | AUTO_CONFIG_DONE<2>.D | 5106 | ? | 0 | 0 | AUTO_CONFIG_DONE<2> | NULL | NULL | AUTO_CONFIG_DONE<2>.XOR | 0 | 7 | ALU_F
+INPUT_NODE_TYPE | 1 | 8 | SRFF_C
+SIGNAL | NODE | AUTO_CONFIG_DONE<2>.CLKF | 5109 | ? | 0 | 4096 | AUTO_CONFIG_DONE<2> | NULL | NULL | AUTO_CONFIG_DONE<2>.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_TRUE | AS_IBUF
+INPUT_NODE_TYPE | 3 | 8 | SRFF_R
+NODE | FSR-IO_0 | 4911 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 9 | 5 | II_FSRINV
+OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
+NODE | AUTO_CONFIG_DONE<2>.Q | 5110 | ? | 0 | 0 | AUTO_CONFIG_DONE<2> | NULL | NULL | AUTO_CONFIG_DONE<2>.REG | 0 | 8 | SRFF_Q
+
+MACROCELL_INSTANCE | PrldLow+OptxMapped | AUTO_CONFIG_DONE_CYCLE<0> | LAN_IDE_CP_COPY_0_COPY_0 | 2155873280 | 17 | 2
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE_CYCLE<0> | 4940 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE_CYCLE<0>.Q | AUTO_CONFIG_DONE_CYCLE<0> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | UDS_IBUF | 4924 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | UDS_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_5_IBUF | 4927 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_4_IBUF | 4928 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_4_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_1_IBUF | 4929 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_1_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_6_IBUF | 4930 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_6_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_3_IBUF | 4931 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<0> | 4937 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<0>.Q | AUTO_CONFIG_DONE<0> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | autoconfig | 4957 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.Q | autoconfig | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | ide/ide_CLKF.UIM | 5040 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ide/ide_CLKF.Q | ide/ide_CLKF | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_2_IBUF | 4932 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<1> | 4938 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<1>.Q | AUTO_CONFIG_DONE<1> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | IDE_BASEADR<7> | 4951 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_BASEADR<7>.Q | IDE_BASEADR<7> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | N4 | 4967 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | N4 | 0 | 5 | II_IMUX
+OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
+NODE | AUTO_CONFIG_DONE_CYCLE<0> | 4940 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE_CYCLE<0>.Q | AUTO_CONFIG_DONE_CYCLE<0> | 1 | 0 | MC_UIM
+OUTPUT_NODE_TYPE | 4 | 0 | MC_EXPORT
+NODE | AUTO_CONFIG_DONE_CYCLE<0>.EXP | 5368 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE_CYCLE<0>.EXP | AUTO_CONFIG_DONE_CYCLE<0> | 4 | 0 | MC_EXPORT
+
+SIGNAL_INSTANCE | AUTO_CONFIG_DONE_CYCLE<0>.SI | AUTO_CONFIG_DONE_CYCLE<0> | 0 | 17 | 4
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE_CYCLE<0> | 4940 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE_CYCLE<0>.Q | AUTO_CONFIG_DONE_CYCLE<0> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | UDS_IBUF | 4924 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | UDS_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_5_IBUF | 4927 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_4_IBUF | 4928 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_4_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_1_IBUF | 4929 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_1_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_6_IBUF | 4930 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_6_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_3_IBUF | 4931 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<0> | 4937 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<0>.Q | AUTO_CONFIG_DONE<0> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | autoconfig | 4957 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.Q | autoconfig | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | ide/ide_CLKF.UIM | 5040 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ide/ide_CLKF.Q | ide/ide_CLKF | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_2_IBUF | 4932 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<1> | 4938 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<1>.Q | AUTO_CONFIG_DONE<1> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | IDE_BASEADR<7> | 4951 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_BASEADR<7>.Q | IDE_BASEADR<7> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | N4 | 4967 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | N4 | 0 | 5 | II_IMUX
+OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
+SIGNAL | NODE | AUTO_CONFIG_DONE_CYCLE<0>.D1 | 5112 | ? | 0 | 4096 | AUTO_CONFIG_DONE_CYCLE<0> | NULL | NULL | AUTO_CONFIG_DONE_CYCLE<0>.SI | 1 | 9 | MC_SI_D1
+SPPTERM | 0 | IV_ZERO
+OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
+SIGNAL | NODE | AUTO_CONFIG_DONE_CYCLE<0>.D2 | 5113 | ? | 0 | 4096 | AUTO_CONFIG_DONE_CYCLE<0> | NULL | NULL | AUTO_CONFIG_DONE_CYCLE<0>.SI | 2 | 9 | MC_SI_D2
+SPPTERM | 2 | IV_TRUE | RESET_IBUF | IV_TRUE | AUTO_CONFIG_DONE_CYCLE<0>
+SPPTERM | 11 | IV_TRUE | RESET_IBUF | IV_FALSE | UDS_IBUF | IV_FALSE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_FALSE | A_4_IBUF | IV_FALSE | A_1_IBUF | IV_TRUE | A_6_IBUF | IV_TRUE | A_3_IBUF | IV_FALSE | AUTO_CONFIG_DONE<0> | IV_TRUE | autoconfig
+OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF
+SIGNAL | NODE | AUTO_CONFIG_DONE_CYCLE<0>.CLKF | 5114 | ? | 0 | 4096 | AUTO_CONFIG_DONE_CYCLE<0> | NULL | NULL | AUTO_CONFIG_DONE_CYCLE<0>.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_TRUE | ide/ide_CLKF.UIM
+OUTPUT_NODE_TYPE | 7 | 9 | MC_SI_EXPORT
+SIGNAL | NODE | AUTO_CONFIG_DONE_CYCLE<0>.EXP | 5360 | ? | 0 | 0 | AUTO_CONFIG_DONE_CYCLE<0> | NULL | NULL | AUTO_CONFIG_DONE_CYCLE<0>.SI | 7 | 9 | MC_SI_EXPORT
+SPPTERM | 15 | IV_TRUE | RESET_IBUF | IV_FALSE | UDS_IBUF | IV_FALSE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_FALSE | A_4_IBUF | IV_FALSE | A_1_IBUF | IV_TRUE | A_6_IBUF | IV_TRUE | A_3_IBUF | IV_FALSE | A_2_IBUF | IV_TRUE | AUTO_CONFIG_DONE<0> | IV_FALSE | AUTO_CONFIG_DONE<1> | IV_TRUE | IDE_BASEADR<7> | IV_TRUE | autoconfig | IV_FALSE | N4
+
+SRFF_INSTANCE | AUTO_CONFIG_DONE_CYCLE<0>.REG | AUTO_CONFIG_DONE_CYCLE<0> | 0 | 2 | 1
+INPUT_NODE_TYPE | 0 | 8 | SRFF_D
+NODE | AUTO_CONFIG_DONE_CYCLE<0>.D | 5111 | ? | 0 | 0 | AUTO_CONFIG_DONE_CYCLE<0> | NULL | NULL | AUTO_CONFIG_DONE_CYCLE<0>.XOR | 0 | 7 | ALU_F
+INPUT_NODE_TYPE | 1 | 8 | SRFF_C
+SIGNAL | NODE | AUTO_CONFIG_DONE_CYCLE<0>.CLKF | 5114 | ? | 0 | 4096 | AUTO_CONFIG_DONE_CYCLE<0> | NULL | NULL | AUTO_CONFIG_DONE_CYCLE<0>.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_TRUE | ide/ide_CLKF.UIM
+OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
+NODE | AUTO_CONFIG_DONE_CYCLE<0>.Q | 5115 | ? | 0 | 0 | AUTO_CONFIG_DONE_CYCLE<0> | NULL | NULL | AUTO_CONFIG_DONE_CYCLE<0>.REG | 0 | 8 | SRFF_Q
+
+MACROCELL_INSTANCE | PrldLow+OptxMapped | AUTO_CONFIG_DONE_CYCLE<1> | LAN_IDE_CP_COPY_0_COPY_0 | 2155873280 | 14 | 1
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE_CYCLE<1> | 4941 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE_CYCLE<1>.Q | AUTO_CONFIG_DONE_CYCLE<1> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | UDS_IBUF | 4924 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | UDS_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_5_IBUF | 4927 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_4_IBUF | 4928 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_4_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_1_IBUF | 4929 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_1_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_6_IBUF | 4930 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_6_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_3_IBUF | 4931 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<0> | 4937 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<0>.Q | AUTO_CONFIG_DONE<0> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<1> | 4938 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<1>.Q | AUTO_CONFIG_DONE<1> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | autoconfig | 4957 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.Q | autoconfig | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | ide/ide_CLKF.UIM | 5040 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ide/ide_CLKF.Q | ide/ide_CLKF | 1 | 0 | MC_UIM
+OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
+NODE | AUTO_CONFIG_DONE_CYCLE<1> | 4941 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE_CYCLE<1>.Q | AUTO_CONFIG_DONE_CYCLE<1> | 1 | 0 | MC_UIM
+
+SIGNAL_INSTANCE | AUTO_CONFIG_DONE_CYCLE<1>.SI | AUTO_CONFIG_DONE_CYCLE<1> | 0 | 14 | 3
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE_CYCLE<1> | 4941 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE_CYCLE<1>.Q | AUTO_CONFIG_DONE_CYCLE<1> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | UDS_IBUF | 4924 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | UDS_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_5_IBUF | 4927 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_4_IBUF | 4928 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_4_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_1_IBUF | 4929 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_1_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_6_IBUF | 4930 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_6_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_3_IBUF | 4931 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<0> | 4937 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<0>.Q | AUTO_CONFIG_DONE<0> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<1> | 4938 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<1>.Q | AUTO_CONFIG_DONE<1> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | autoconfig | 4957 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.Q | autoconfig | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | ide/ide_CLKF.UIM | 5040 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ide/ide_CLKF.Q | ide/ide_CLKF | 1 | 0 | MC_UIM
+OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
+SIGNAL | NODE | AUTO_CONFIG_DONE_CYCLE<1>.D1 | 5117 | ? | 0 | 4096 | AUTO_CONFIG_DONE_CYCLE<1> | NULL | NULL | AUTO_CONFIG_DONE_CYCLE<1>.SI | 1 | 9 | MC_SI_D1
+SPPTERM | 0 | IV_ZERO
+OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
+SIGNAL | NODE | AUTO_CONFIG_DONE_CYCLE<1>.D2 | 5118 | ? | 0 | 4096 | AUTO_CONFIG_DONE_CYCLE<1> | NULL | NULL | AUTO_CONFIG_DONE_CYCLE<1>.SI | 2 | 9 | MC_SI_D2
+SPPTERM | 2 | IV_TRUE | RESET_IBUF | IV_TRUE | AUTO_CONFIG_DONE_CYCLE<1>
+SPPTERM | 12 | IV_TRUE | RESET_IBUF | IV_FALSE | UDS_IBUF | IV_FALSE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_FALSE | A_4_IBUF | IV_FALSE | A_1_IBUF | IV_TRUE | A_6_IBUF | IV_TRUE | A_3_IBUF | IV_TRUE | AUTO_CONFIG_DONE<0> | IV_FALSE | AUTO_CONFIG_DONE<1> | IV_TRUE | autoconfig
+OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF
+SIGNAL | NODE | AUTO_CONFIG_DONE_CYCLE<1>.CLKF | 5119 | ? | 0 | 4096 | AUTO_CONFIG_DONE_CYCLE<1> | NULL | NULL | AUTO_CONFIG_DONE_CYCLE<1>.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_TRUE | ide/ide_CLKF.UIM
+
+SRFF_INSTANCE | AUTO_CONFIG_DONE_CYCLE<1>.REG | AUTO_CONFIG_DONE_CYCLE<1> | 0 | 2 | 1
+INPUT_NODE_TYPE | 0 | 8 | SRFF_D
+NODE | AUTO_CONFIG_DONE_CYCLE<1>.D | 5116 | ? | 0 | 0 | AUTO_CONFIG_DONE_CYCLE<1> | NULL | NULL | AUTO_CONFIG_DONE_CYCLE<1>.XOR | 0 | 7 | ALU_F
+INPUT_NODE_TYPE | 1 | 8 | SRFF_C
+SIGNAL | NODE | AUTO_CONFIG_DONE_CYCLE<1>.CLKF | 5119 | ? | 0 | 4096 | AUTO_CONFIG_DONE_CYCLE<1> | NULL | NULL | AUTO_CONFIG_DONE_CYCLE<1>.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_TRUE | ide/ide_CLKF.UIM
+OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
+NODE | AUTO_CONFIG_DONE_CYCLE<1>.Q | 5120 | ? | 0 | 0 | AUTO_CONFIG_DONE_CYCLE<1> | NULL | NULL | AUTO_CONFIG_DONE_CYCLE<1>.REG | 0 | 8 | SRFF_Q
+
+MACROCELL_INSTANCE | PrldLow+OptxMapped | AUTO_CONFIG_DONE_CYCLE<2> | LAN_IDE_CP_COPY_0_COPY_0 | 2155873280 | 15 | 1
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE_CYCLE<2> | 4942 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE_CYCLE<2>.Q | AUTO_CONFIG_DONE_CYCLE<2> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | UDS_IBUF | 4924 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | UDS_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_5_IBUF | 4927 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_4_IBUF | 4928 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_4_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_1_IBUF | 4929 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_1_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_6_IBUF | 4930 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_6_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_3_IBUF | 4931 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<0> | 4937 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<0>.Q | AUTO_CONFIG_DONE<0> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<1> | 4938 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<1>.Q | AUTO_CONFIG_DONE<1> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<2> | 4939 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<2>.Q | AUTO_CONFIG_DONE<2> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | autoconfig | 4957 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.Q | autoconfig | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | ide/ide_CLKF.UIM | 5040 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ide/ide_CLKF.Q | ide/ide_CLKF | 1 | 0 | MC_UIM
+OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
+NODE | AUTO_CONFIG_DONE_CYCLE<2> | 4942 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE_CYCLE<2>.Q | AUTO_CONFIG_DONE_CYCLE<2> | 1 | 0 | MC_UIM
+
+SIGNAL_INSTANCE | AUTO_CONFIG_DONE_CYCLE<2>.SI | AUTO_CONFIG_DONE_CYCLE<2> | 0 | 15 | 3
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE_CYCLE<2> | 4942 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE_CYCLE<2>.Q | AUTO_CONFIG_DONE_CYCLE<2> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | UDS_IBUF | 4924 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | UDS_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_5_IBUF | 4927 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_4_IBUF | 4928 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_4_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_1_IBUF | 4929 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_1_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_6_IBUF | 4930 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_6_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_3_IBUF | 4931 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<0> | 4937 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<0>.Q | AUTO_CONFIG_DONE<0> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<1> | 4938 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<1>.Q | AUTO_CONFIG_DONE<1> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<2> | 4939 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<2>.Q | AUTO_CONFIG_DONE<2> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | autoconfig | 4957 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.Q | autoconfig | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | ide/ide_CLKF.UIM | 5040 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ide/ide_CLKF.Q | ide/ide_CLKF | 1 | 0 | MC_UIM
+OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
+SIGNAL | NODE | AUTO_CONFIG_DONE_CYCLE<2>.D1 | 5122 | ? | 0 | 4096 | AUTO_CONFIG_DONE_CYCLE<2> | NULL | NULL | AUTO_CONFIG_DONE_CYCLE<2>.SI | 1 | 9 | MC_SI_D1
+SPPTERM | 0 | IV_ZERO
+OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
+SIGNAL | NODE | AUTO_CONFIG_DONE_CYCLE<2>.D2 | 5123 | ? | 0 | 4096 | AUTO_CONFIG_DONE_CYCLE<2> | NULL | NULL | AUTO_CONFIG_DONE_CYCLE<2>.SI | 2 | 9 | MC_SI_D2
+SPPTERM | 2 | IV_TRUE | RESET_IBUF | IV_TRUE | AUTO_CONFIG_DONE_CYCLE<2>
+SPPTERM | 13 | IV_TRUE | RESET_IBUF | IV_FALSE | UDS_IBUF | IV_FALSE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_FALSE | A_4_IBUF | IV_FALSE | A_1_IBUF | IV_TRUE | A_6_IBUF | IV_TRUE | A_3_IBUF | IV_TRUE | AUTO_CONFIG_DONE<0> | IV_TRUE | AUTO_CONFIG_DONE<1> | IV_FALSE | AUTO_CONFIG_DONE<2> | IV_TRUE | autoconfig
+OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF
+SIGNAL | NODE | AUTO_CONFIG_DONE_CYCLE<2>.CLKF | 5124 | ? | 0 | 4096 | AUTO_CONFIG_DONE_CYCLE<2> | NULL | NULL | AUTO_CONFIG_DONE_CYCLE<2>.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_TRUE | ide/ide_CLKF.UIM
+
+SRFF_INSTANCE | AUTO_CONFIG_DONE_CYCLE<2>.REG | AUTO_CONFIG_DONE_CYCLE<2> | 0 | 2 | 1
+INPUT_NODE_TYPE | 0 | 8 | SRFF_D
+NODE | AUTO_CONFIG_DONE_CYCLE<2>.D | 5121 | ? | 0 | 0 | AUTO_CONFIG_DONE_CYCLE<2> | NULL | NULL | AUTO_CONFIG_DONE_CYCLE<2>.XOR | 0 | 7 | ALU_F
+INPUT_NODE_TYPE | 1 | 8 | SRFF_C
+SIGNAL | NODE | AUTO_CONFIG_DONE_CYCLE<2>.CLKF | 5124 | ? | 0 | 4096 | AUTO_CONFIG_DONE_CYCLE<2> | NULL | NULL | AUTO_CONFIG_DONE_CYCLE<2>.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_TRUE | ide/ide_CLKF.UIM
+OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
+NODE | AUTO_CONFIG_DONE_CYCLE<2>.Q | 5125 | ? | 0 | 0 | AUTO_CONFIG_DONE_CYCLE<2> | NULL | NULL | AUTO_CONFIG_DONE_CYCLE<2>.REG | 0 | 8 | SRFF_Q
+
+INPUT_INSTANCE | 0 | 0 | NULL | N5 | LAN_IDE_CP_COPY_0_COPY_0 | 16 | 1 | 1
+INPUT_NODE_TYPE | 0 | 5 | II_IN
+NODE | D<8> | 5021 | PIPO | 0 | 64 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | D<8> | 0 | 6 | OI_OUT
+OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX
+NODE | N5 | 4960 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | N5 | 0 | 5 | II_IMUX
+
+MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped | IDE_BASEADR<0> | LAN_IDE_CP_COPY_0_COPY_0 | 2155877376 | 16 | 1
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | IDE_BASEADR<0> | 4943 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_BASEADR<0>.Q | IDE_BASEADR<0> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | UDS_IBUF | 4924 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | UDS_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_5_IBUF | 4927 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_4_IBUF | 4928 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_4_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_1_IBUF | 4929 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_1_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_6_IBUF | 4930 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_6_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_3_IBUF | 4931 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_2_IBUF | 4932 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<0> | 4937 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<0>.Q | AUTO_CONFIG_DONE<0> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<1> | 4938 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<1>.Q | AUTO_CONFIG_DONE<1> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | autoconfig | 4957 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.Q | autoconfig | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | N5 | 4960 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | N5 | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | ide/ide_CLKF.UIM | 5040 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ide/ide_CLKF.Q | ide/ide_CLKF | 1 | 0 | MC_UIM
+OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
+NODE | IDE_BASEADR<0> | 4943 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_BASEADR<0>.Q | IDE_BASEADR<0> | 1 | 0 | MC_UIM
+
+SIGNAL_INSTANCE | IDE_BASEADR<0>.SI | IDE_BASEADR<0> | 0 | 16 | 3
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | IDE_BASEADR<0> | 4943 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_BASEADR<0>.Q | IDE_BASEADR<0> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | UDS_IBUF | 4924 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | UDS_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_5_IBUF | 4927 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_4_IBUF | 4928 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_4_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_1_IBUF | 4929 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_1_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_6_IBUF | 4930 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_6_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_3_IBUF | 4931 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_2_IBUF | 4932 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<0> | 4937 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<0>.Q | AUTO_CONFIG_DONE<0> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<1> | 4938 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<1>.Q | AUTO_CONFIG_DONE<1> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | autoconfig | 4957 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.Q | autoconfig | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | N5 | 4960 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | N5 | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | ide/ide_CLKF.UIM | 5040 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ide/ide_CLKF.Q | ide/ide_CLKF | 1 | 0 | MC_UIM
+OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
+SIGNAL | NODE | IDE_BASEADR<0>.D1 | 5127 | ? | 0 | 4096 | IDE_BASEADR<0> | NULL | NULL | IDE_BASEADR<0>.SI | 1 | 9 | MC_SI_D1
+SPPTERM | 0 | IV_ZERO
+OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
+SIGNAL | NODE | IDE_BASEADR<0>.D2 | 5128 | ? | 0 | 4096 | IDE_BASEADR<0> | NULL | NULL | IDE_BASEADR<0>.SI | 2 | 9 | MC_SI_D2
+SPPTERM | 2 | IV_FALSE | RESET_IBUF | IV_FALSE | IDE_BASEADR<0>
+SPPTERM | 14 | IV_FALSE | UDS_IBUF | IV_FALSE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_FALSE | A_4_IBUF | IV_FALSE | A_1_IBUF | IV_TRUE | A_6_IBUF | IV_TRUE | A_3_IBUF | IV_FALSE | A_2_IBUF | IV_TRUE | AUTO_CONFIG_DONE<0> | IV_FALSE | AUTO_CONFIG_DONE<1> | IV_FALSE | IDE_BASEADR<0> | IV_TRUE | autoconfig | IV_TRUE | N5
+SPPTERM | 15 | IV_TRUE | RESET_IBUF | IV_FALSE | UDS_IBUF | IV_FALSE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_FALSE | A_4_IBUF | IV_FALSE | A_1_IBUF | IV_TRUE | A_6_IBUF | IV_TRUE | A_3_IBUF | IV_FALSE | A_2_IBUF | IV_TRUE | AUTO_CONFIG_DONE<0> | IV_FALSE | AUTO_CONFIG_DONE<1> | IV_TRUE | IDE_BASEADR<0> | IV_TRUE | autoconfig | IV_FALSE | N5
+OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF
+SIGNAL | NODE | IDE_BASEADR<0>.CLKF | 5129 | ? | 0 | 4096 | IDE_BASEADR<0> | NULL | NULL | IDE_BASEADR<0>.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_TRUE | ide/ide_CLKF.UIM
+
+SRFF_INSTANCE | IDE_BASEADR<0>.REG | IDE_BASEADR<0> | 0 | 2 | 1
+INPUT_NODE_TYPE | 0 | 8 | SRFF_D
+NODE | IDE_BASEADR<0>.D | 5126 | ? | 0 | 0 | IDE_BASEADR<0> | NULL | NULL | IDE_BASEADR<0>.XOR | 0 | 7 | ALU_F
+INPUT_NODE_TYPE | 1 | 8 | SRFF_C
+SIGNAL | NODE | IDE_BASEADR<0>.CLKF | 5129 | ? | 0 | 4096 | IDE_BASEADR<0> | NULL | NULL | IDE_BASEADR<0>.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_TRUE | ide/ide_CLKF.UIM
+OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
+NODE | IDE_BASEADR<0>.Q | 5130 | ? | 0 | 0 | IDE_BASEADR<0> | NULL | NULL | IDE_BASEADR<0>.REG | 0 | 8 | SRFF_Q
+
+INPUT_INSTANCE | 0 | 0 | NULL | N11 | LAN_IDE_CP_COPY_0_COPY_0 | 16 | 1 | 1
+INPUT_NODE_TYPE | 0 | 5 | II_IN
+NODE | D<12> | 5014 | PIPO | 0 | 64 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | D<12> | 0 | 6 | OI_OUT
+OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX
+NODE | N11 | 4964 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | N11 | 0 | 5 | II_IMUX
+
+MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped | IDE_BASEADR<4> | LAN_IDE_CP_COPY_0_COPY_0 | 2155877376 | 16 | 1
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | IDE_BASEADR<4> | 4944 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_BASEADR<4>.Q | IDE_BASEADR<4> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | UDS_IBUF | 4924 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | UDS_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_5_IBUF | 4927 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_4_IBUF | 4928 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_4_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_1_IBUF | 4929 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_1_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_6_IBUF | 4930 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_6_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_3_IBUF | 4931 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_2_IBUF | 4932 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<0> | 4937 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<0>.Q | AUTO_CONFIG_DONE<0> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<1> | 4938 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<1>.Q | AUTO_CONFIG_DONE<1> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | autoconfig | 4957 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.Q | autoconfig | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | N11 | 4964 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | N11 | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | ide/ide_CLKF.UIM | 5040 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ide/ide_CLKF.Q | ide/ide_CLKF | 1 | 0 | MC_UIM
+OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
+NODE | IDE_BASEADR<4> | 4944 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_BASEADR<4>.Q | IDE_BASEADR<4> | 1 | 0 | MC_UIM
+
+SIGNAL_INSTANCE | IDE_BASEADR<4>.SI | IDE_BASEADR<4> | 0 | 16 | 3
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | IDE_BASEADR<4> | 4944 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_BASEADR<4>.Q | IDE_BASEADR<4> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | UDS_IBUF | 4924 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | UDS_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_5_IBUF | 4927 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_4_IBUF | 4928 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_4_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_1_IBUF | 4929 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_1_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_6_IBUF | 4930 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_6_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_3_IBUF | 4931 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_2_IBUF | 4932 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<0> | 4937 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<0>.Q | AUTO_CONFIG_DONE<0> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<1> | 4938 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<1>.Q | AUTO_CONFIG_DONE<1> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | autoconfig | 4957 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.Q | autoconfig | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | N11 | 4964 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | N11 | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | ide/ide_CLKF.UIM | 5040 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ide/ide_CLKF.Q | ide/ide_CLKF | 1 | 0 | MC_UIM
+OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
+SIGNAL | NODE | IDE_BASEADR<4>.D1 | 5132 | ? | 0 | 4096 | IDE_BASEADR<4> | NULL | NULL | IDE_BASEADR<4>.SI | 1 | 9 | MC_SI_D1
+SPPTERM | 0 | IV_ZERO
+OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
+SIGNAL | NODE | IDE_BASEADR<4>.D2 | 5133 | ? | 0 | 4096 | IDE_BASEADR<4> | NULL | NULL | IDE_BASEADR<4>.SI | 2 | 9 | MC_SI_D2
+SPPTERM | 2 | IV_FALSE | RESET_IBUF | IV_FALSE | IDE_BASEADR<4>
+SPPTERM | 14 | IV_FALSE | UDS_IBUF | IV_FALSE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_FALSE | A_4_IBUF | IV_FALSE | A_1_IBUF | IV_TRUE | A_6_IBUF | IV_TRUE | A_3_IBUF | IV_FALSE | A_2_IBUF | IV_TRUE | AUTO_CONFIG_DONE<0> | IV_FALSE | AUTO_CONFIG_DONE<1> | IV_FALSE | IDE_BASEADR<4> | IV_TRUE | autoconfig | IV_TRUE | N11
+SPPTERM | 15 | IV_TRUE | RESET_IBUF | IV_FALSE | UDS_IBUF | IV_FALSE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_FALSE | A_4_IBUF | IV_FALSE | A_1_IBUF | IV_TRUE | A_6_IBUF | IV_TRUE | A_3_IBUF | IV_FALSE | A_2_IBUF | IV_TRUE | AUTO_CONFIG_DONE<0> | IV_FALSE | AUTO_CONFIG_DONE<1> | IV_TRUE | IDE_BASEADR<4> | IV_TRUE | autoconfig | IV_FALSE | N11
+OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF
+SIGNAL | NODE | IDE_BASEADR<4>.CLKF | 5134 | ? | 0 | 4096 | IDE_BASEADR<4> | NULL | NULL | IDE_BASEADR<4>.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_TRUE | ide/ide_CLKF.UIM
+
+SRFF_INSTANCE | IDE_BASEADR<4>.REG | IDE_BASEADR<4> | 0 | 2 | 1
+INPUT_NODE_TYPE | 0 | 8 | SRFF_D
+NODE | IDE_BASEADR<4>.D | 5131 | ? | 0 | 0 | IDE_BASEADR<4> | NULL | NULL | IDE_BASEADR<4>.XOR | 0 | 7 | ALU_F
+INPUT_NODE_TYPE | 1 | 8 | SRFF_C
+SIGNAL | NODE | IDE_BASEADR<4>.CLKF | 5134 | ? | 0 | 4096 | IDE_BASEADR<4> | NULL | NULL | IDE_BASEADR<4>.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_TRUE | ide/ide_CLKF.UIM
+OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
+NODE | IDE_BASEADR<4>.Q | 5135 | ? | 0 | 0 | IDE_BASEADR<4> | NULL | NULL | IDE_BASEADR<4>.REG | 0 | 8 | SRFF_Q
+
+INPUT_INSTANCE | 0 | 0 | NULL | N2 | LAN_IDE_CP_COPY_0_COPY_0 | 16 | 1 | 1
+INPUT_NODE_TYPE | 0 | 5 | II_IN
+NODE | D<13> | 5013 | PIPO | 0 | 64 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | D<13> | 0 | 6 | OI_OUT
+OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX
+NODE | N2 | 4965 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | N2 | 0 | 5 | II_IMUX
+
+MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped | IDE_BASEADR<5> | LAN_IDE_CP_COPY_0_COPY_0 | 2155877376 | 16 | 1
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | IDE_BASEADR<5> | 4945 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_BASEADR<5>.Q | IDE_BASEADR<5> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | UDS_IBUF | 4924 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | UDS_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_5_IBUF | 4927 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_4_IBUF | 4928 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_4_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_1_IBUF | 4929 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_1_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_6_IBUF | 4930 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_6_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_3_IBUF | 4931 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_2_IBUF | 4932 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<0> | 4937 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<0>.Q | AUTO_CONFIG_DONE<0> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<1> | 4938 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<1>.Q | AUTO_CONFIG_DONE<1> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | autoconfig | 4957 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.Q | autoconfig | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | N2 | 4965 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | N2 | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | ide/ide_CLKF.UIM | 5040 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ide/ide_CLKF.Q | ide/ide_CLKF | 1 | 0 | MC_UIM
+OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
+NODE | IDE_BASEADR<5> | 4945 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_BASEADR<5>.Q | IDE_BASEADR<5> | 1 | 0 | MC_UIM
+
+SIGNAL_INSTANCE | IDE_BASEADR<5>.SI | IDE_BASEADR<5> | 0 | 16 | 3
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | IDE_BASEADR<5> | 4945 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_BASEADR<5>.Q | IDE_BASEADR<5> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | UDS_IBUF | 4924 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | UDS_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_5_IBUF | 4927 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_4_IBUF | 4928 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_4_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_1_IBUF | 4929 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_1_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_6_IBUF | 4930 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_6_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_3_IBUF | 4931 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_2_IBUF | 4932 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<0> | 4937 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<0>.Q | AUTO_CONFIG_DONE<0> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<1> | 4938 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<1>.Q | AUTO_CONFIG_DONE<1> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | autoconfig | 4957 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.Q | autoconfig | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | N2 | 4965 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | N2 | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | ide/ide_CLKF.UIM | 5040 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ide/ide_CLKF.Q | ide/ide_CLKF | 1 | 0 | MC_UIM
+OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
+SIGNAL | NODE | IDE_BASEADR<5>.D1 | 5137 | ? | 0 | 4096 | IDE_BASEADR<5> | NULL | NULL | IDE_BASEADR<5>.SI | 1 | 9 | MC_SI_D1
+SPPTERM | 0 | IV_ZERO
+OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
+SIGNAL | NODE | IDE_BASEADR<5>.D2 | 5138 | ? | 0 | 4096 | IDE_BASEADR<5> | NULL | NULL | IDE_BASEADR<5>.SI | 2 | 9 | MC_SI_D2
+SPPTERM | 2 | IV_FALSE | RESET_IBUF | IV_FALSE | IDE_BASEADR<5>
+SPPTERM | 14 | IV_FALSE | UDS_IBUF | IV_FALSE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_FALSE | A_4_IBUF | IV_FALSE | A_1_IBUF | IV_TRUE | A_6_IBUF | IV_TRUE | A_3_IBUF | IV_FALSE | A_2_IBUF | IV_TRUE | AUTO_CONFIG_DONE<0> | IV_FALSE | AUTO_CONFIG_DONE<1> | IV_FALSE | IDE_BASEADR<5> | IV_TRUE | autoconfig | IV_TRUE | N2
+SPPTERM | 15 | IV_TRUE | RESET_IBUF | IV_FALSE | UDS_IBUF | IV_FALSE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_FALSE | A_4_IBUF | IV_FALSE | A_1_IBUF | IV_TRUE | A_6_IBUF | IV_TRUE | A_3_IBUF | IV_FALSE | A_2_IBUF | IV_TRUE | AUTO_CONFIG_DONE<0> | IV_FALSE | AUTO_CONFIG_DONE<1> | IV_TRUE | IDE_BASEADR<5> | IV_TRUE | autoconfig | IV_FALSE | N2
+OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF
+SIGNAL | NODE | IDE_BASEADR<5>.CLKF | 5139 | ? | 0 | 4096 | IDE_BASEADR<5> | NULL | NULL | IDE_BASEADR<5>.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_TRUE | ide/ide_CLKF.UIM
+
+SRFF_INSTANCE | IDE_BASEADR<5>.REG | IDE_BASEADR<5> | 0 | 2 | 1
+INPUT_NODE_TYPE | 0 | 8 | SRFF_D
+NODE | IDE_BASEADR<5>.D | 5136 | ? | 0 | 0 | IDE_BASEADR<5> | NULL | NULL | IDE_BASEADR<5>.XOR | 0 | 7 | ALU_F
+INPUT_NODE_TYPE | 1 | 8 | SRFF_C
+SIGNAL | NODE | IDE_BASEADR<5>.CLKF | 5139 | ? | 0 | 4096 | IDE_BASEADR<5> | NULL | NULL | IDE_BASEADR<5>.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_TRUE | ide/ide_CLKF.UIM
+OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
+NODE | IDE_BASEADR<5>.Q | 5140 | ? | 0 | 0 | IDE_BASEADR<5> | NULL | NULL | IDE_BASEADR<5>.REG | 0 | 8 | SRFF_Q
+
+MACROCELL_INSTANCE | Inv+PrldLow+OptxMapped | IDE_ENABLE | LAN_IDE_CP_COPY_0_COPY_0 | 2155873536 | 6 | 1
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | IDE_ENABLE | 4946 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_ENABLE.Q | IDE_ENABLE | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | ide | 4958 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ide.Q | ide | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | ide/ide_CLKF.UIM | 5040 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ide/ide_CLKF.Q | ide/ide_CLKF | 1 | 0 | MC_UIM
+OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
+NODE | IDE_ENABLE | 4946 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_ENABLE.Q | IDE_ENABLE | 1 | 0 | MC_UIM
+
+SIGNAL_INSTANCE | IDE_ENABLE.SI | IDE_ENABLE | 0 | 6 | 3
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | IDE_ENABLE | 4946 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_ENABLE.Q | IDE_ENABLE | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | ide | 4958 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ide.Q | ide | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | ide/ide_CLKF.UIM | 5040 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ide/ide_CLKF.Q | ide/ide_CLKF | 1 | 0 | MC_UIM
+OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
+SIGNAL | NODE | IDE_ENABLE.D1 | 5142 | ? | 0 | 4096 | IDE_ENABLE | NULL | NULL | IDE_ENABLE.SI | 1 | 9 | MC_SI_D1
+SPPTERM | 0 | IV_ZERO
+OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
+SIGNAL | NODE | IDE_ENABLE.D2 | 5143 | ? | 0 | 4096 | IDE_ENABLE | NULL | NULL | IDE_ENABLE.SI | 2 | 9 | MC_SI_D2
+SPPTERM | 2 | IV_TRUE | RESET_IBUF | IV_FALSE | IDE_ENABLE
+SPPTERM | 4 | IV_TRUE | RESET_IBUF | IV_FALSE | RW_IBUF | IV_FALSE | AS_IBUF | IV_TRUE | ide
+OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF
+SIGNAL | NODE | IDE_ENABLE.CLKF | 5144 | ? | 0 | 4096 | IDE_ENABLE | NULL | NULL | IDE_ENABLE.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_TRUE | ide/ide_CLKF.UIM
+
+SRFF_INSTANCE | IDE_ENABLE.REG | IDE_ENABLE | 0 | 2 | 1
+INPUT_NODE_TYPE | 0 | 8 | SRFF_D
+NODE | IDE_ENABLE.D | 5141 | ? | 0 | 0 | IDE_ENABLE | NULL | NULL | IDE_ENABLE.XOR | 0 | 7 | ALU_F
+INPUT_NODE_TYPE | 1 | 8 | SRFF_C
+SIGNAL | NODE | IDE_ENABLE.CLKF | 5144 | ? | 0 | 4096 | IDE_ENABLE | NULL | NULL | IDE_ENABLE.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_TRUE | ide/ide_CLKF.UIM
+OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
+NODE | IDE_ENABLE.Q | 5145 | ? | 0 | 0 | IDE_ENABLE | NULL | NULL | IDE_ENABLE.REG | 0 | 8 | SRFF_Q
+
+INPUT_INSTANCE | 0 | 0 | NULL | N6 | LAN_IDE_CP_COPY_0_COPY_0 | 16 | 1 | 1
+INPUT_NODE_TYPE | 0 | 5 | II_IN
+NODE | D<9> | 5020 | PIPO | 0 | 64 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | D<9> | 0 | 6 | OI_OUT
+OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX
+NODE | N6 | 4961 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | N6 | 0 | 5 | II_IMUX
+
+MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped | IDE_BASEADR<1> | LAN_IDE_CP_COPY_0_COPY_0 | 2155877376 | 16 | 1
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | IDE_BASEADR<1> | 4947 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_BASEADR<1>.Q | IDE_BASEADR<1> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | UDS_IBUF | 4924 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | UDS_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_5_IBUF | 4927 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_4_IBUF | 4928 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_4_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_1_IBUF | 4929 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_1_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_6_IBUF | 4930 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_6_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_3_IBUF | 4931 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_2_IBUF | 4932 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<0> | 4937 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<0>.Q | AUTO_CONFIG_DONE<0> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<1> | 4938 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<1>.Q | AUTO_CONFIG_DONE<1> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | autoconfig | 4957 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.Q | autoconfig | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | N6 | 4961 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | N6 | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | ide/ide_CLKF.UIM | 5040 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ide/ide_CLKF.Q | ide/ide_CLKF | 1 | 0 | MC_UIM
+OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
+NODE | IDE_BASEADR<1> | 4947 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_BASEADR<1>.Q | IDE_BASEADR<1> | 1 | 0 | MC_UIM
+
+SIGNAL_INSTANCE | IDE_BASEADR<1>.SI | IDE_BASEADR<1> | 0 | 16 | 3
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | IDE_BASEADR<1> | 4947 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_BASEADR<1>.Q | IDE_BASEADR<1> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | UDS_IBUF | 4924 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | UDS_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_5_IBUF | 4927 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_4_IBUF | 4928 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_4_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_1_IBUF | 4929 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_1_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_6_IBUF | 4930 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_6_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_3_IBUF | 4931 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_2_IBUF | 4932 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<0> | 4937 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<0>.Q | AUTO_CONFIG_DONE<0> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<1> | 4938 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<1>.Q | AUTO_CONFIG_DONE<1> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | autoconfig | 4957 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.Q | autoconfig | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | N6 | 4961 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | N6 | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | ide/ide_CLKF.UIM | 5040 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ide/ide_CLKF.Q | ide/ide_CLKF | 1 | 0 | MC_UIM
+OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
+SIGNAL | NODE | IDE_BASEADR<1>.D1 | 5147 | ? | 0 | 4096 | IDE_BASEADR<1> | NULL | NULL | IDE_BASEADR<1>.SI | 1 | 9 | MC_SI_D1
+SPPTERM | 0 | IV_ZERO
+OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
+SIGNAL | NODE | IDE_BASEADR<1>.D2 | 5148 | ? | 0 | 4096 | IDE_BASEADR<1> | NULL | NULL | IDE_BASEADR<1>.SI | 2 | 9 | MC_SI_D2
+SPPTERM | 2 | IV_FALSE | RESET_IBUF | IV_FALSE | IDE_BASEADR<1>
+SPPTERM | 14 | IV_FALSE | UDS_IBUF | IV_FALSE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_FALSE | A_4_IBUF | IV_FALSE | A_1_IBUF | IV_TRUE | A_6_IBUF | IV_TRUE | A_3_IBUF | IV_FALSE | A_2_IBUF | IV_TRUE | AUTO_CONFIG_DONE<0> | IV_FALSE | AUTO_CONFIG_DONE<1> | IV_FALSE | IDE_BASEADR<1> | IV_TRUE | autoconfig | IV_TRUE | N6
+SPPTERM | 15 | IV_TRUE | RESET_IBUF | IV_FALSE | UDS_IBUF | IV_FALSE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_FALSE | A_4_IBUF | IV_FALSE | A_1_IBUF | IV_TRUE | A_6_IBUF | IV_TRUE | A_3_IBUF | IV_FALSE | A_2_IBUF | IV_TRUE | AUTO_CONFIG_DONE<0> | IV_FALSE | AUTO_CONFIG_DONE<1> | IV_TRUE | IDE_BASEADR<1> | IV_TRUE | autoconfig | IV_FALSE | N6
+OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF
+SIGNAL | NODE | IDE_BASEADR<1>.CLKF | 5149 | ? | 0 | 4096 | IDE_BASEADR<1> | NULL | NULL | IDE_BASEADR<1>.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_TRUE | ide/ide_CLKF.UIM
+
+SRFF_INSTANCE | IDE_BASEADR<1>.REG | IDE_BASEADR<1> | 0 | 2 | 1
+INPUT_NODE_TYPE | 0 | 8 | SRFF_D
+NODE | IDE_BASEADR<1>.D | 5146 | ? | 0 | 0 | IDE_BASEADR<1> | NULL | NULL | IDE_BASEADR<1>.XOR | 0 | 7 | ALU_F
+INPUT_NODE_TYPE | 1 | 8 | SRFF_C
+SIGNAL | NODE | IDE_BASEADR<1>.CLKF | 5149 | ? | 0 | 4096 | IDE_BASEADR<1> | NULL | NULL | IDE_BASEADR<1>.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_TRUE | ide/ide_CLKF.UIM
+OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
+NODE | IDE_BASEADR<1>.Q | 5150 | ? | 0 | 0 | IDE_BASEADR<1> | NULL | NULL | IDE_BASEADR<1>.REG | 0 | 8 | SRFF_Q
+
+INPUT_INSTANCE | 0 | 0 | NULL | N7 | LAN_IDE_CP_COPY_0_COPY_0 | 16 | 1 | 1
+INPUT_NODE_TYPE | 0 | 5 | II_IN
+NODE | D<10> | 5031 | PIPO | 0 | 64 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | D<10> | 0 | 6 | OI_OUT
+OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX
+NODE | N7 | 4962 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | N7 | 0 | 5 | II_IMUX
+
+MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped | IDE_BASEADR<2> | LAN_IDE_CP_COPY_0_COPY_0 | 2155877376 | 16 | 1
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | IDE_BASEADR<2> | 4948 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_BASEADR<2>.Q | IDE_BASEADR<2> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | UDS_IBUF | 4924 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | UDS_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_5_IBUF | 4927 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_4_IBUF | 4928 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_4_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_1_IBUF | 4929 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_1_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_6_IBUF | 4930 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_6_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_3_IBUF | 4931 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_2_IBUF | 4932 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<0> | 4937 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<0>.Q | AUTO_CONFIG_DONE<0> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<1> | 4938 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<1>.Q | AUTO_CONFIG_DONE<1> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | autoconfig | 4957 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.Q | autoconfig | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | N7 | 4962 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | N7 | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | ide/ide_CLKF.UIM | 5040 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ide/ide_CLKF.Q | ide/ide_CLKF | 1 | 0 | MC_UIM
+OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
+NODE | IDE_BASEADR<2> | 4948 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_BASEADR<2>.Q | IDE_BASEADR<2> | 1 | 0 | MC_UIM
+
+SIGNAL_INSTANCE | IDE_BASEADR<2>.SI | IDE_BASEADR<2> | 0 | 16 | 3
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | IDE_BASEADR<2> | 4948 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_BASEADR<2>.Q | IDE_BASEADR<2> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | UDS_IBUF | 4924 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | UDS_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_5_IBUF | 4927 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_4_IBUF | 4928 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_4_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_1_IBUF | 4929 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_1_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_6_IBUF | 4930 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_6_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_3_IBUF | 4931 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_2_IBUF | 4932 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<0> | 4937 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<0>.Q | AUTO_CONFIG_DONE<0> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<1> | 4938 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<1>.Q | AUTO_CONFIG_DONE<1> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | autoconfig | 4957 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.Q | autoconfig | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | N7 | 4962 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | N7 | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | ide/ide_CLKF.UIM | 5040 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ide/ide_CLKF.Q | ide/ide_CLKF | 1 | 0 | MC_UIM
+OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
+SIGNAL | NODE | IDE_BASEADR<2>.D1 | 5152 | ? | 0 | 4096 | IDE_BASEADR<2> | NULL | NULL | IDE_BASEADR<2>.SI | 1 | 9 | MC_SI_D1
+SPPTERM | 0 | IV_ZERO
+OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
+SIGNAL | NODE | IDE_BASEADR<2>.D2 | 5153 | ? | 0 | 4096 | IDE_BASEADR<2> | NULL | NULL | IDE_BASEADR<2>.SI | 2 | 9 | MC_SI_D2
+SPPTERM | 2 | IV_FALSE | RESET_IBUF | IV_FALSE | IDE_BASEADR<2>
+SPPTERM | 14 | IV_FALSE | UDS_IBUF | IV_FALSE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_FALSE | A_4_IBUF | IV_FALSE | A_1_IBUF | IV_TRUE | A_6_IBUF | IV_TRUE | A_3_IBUF | IV_FALSE | A_2_IBUF | IV_TRUE | AUTO_CONFIG_DONE<0> | IV_FALSE | AUTO_CONFIG_DONE<1> | IV_FALSE | IDE_BASEADR<2> | IV_TRUE | autoconfig | IV_TRUE | N7
+SPPTERM | 15 | IV_TRUE | RESET_IBUF | IV_FALSE | UDS_IBUF | IV_FALSE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_FALSE | A_4_IBUF | IV_FALSE | A_1_IBUF | IV_TRUE | A_6_IBUF | IV_TRUE | A_3_IBUF | IV_FALSE | A_2_IBUF | IV_TRUE | AUTO_CONFIG_DONE<0> | IV_FALSE | AUTO_CONFIG_DONE<1> | IV_TRUE | IDE_BASEADR<2> | IV_TRUE | autoconfig | IV_FALSE | N7
+OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF
+SIGNAL | NODE | IDE_BASEADR<2>.CLKF | 5154 | ? | 0 | 4096 | IDE_BASEADR<2> | NULL | NULL | IDE_BASEADR<2>.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_TRUE | ide/ide_CLKF.UIM
+
+SRFF_INSTANCE | IDE_BASEADR<2>.REG | IDE_BASEADR<2> | 0 | 2 | 1
+INPUT_NODE_TYPE | 0 | 8 | SRFF_D
+NODE | IDE_BASEADR<2>.D | 5151 | ? | 0 | 0 | IDE_BASEADR<2> | NULL | NULL | IDE_BASEADR<2>.XOR | 0 | 7 | ALU_F
+INPUT_NODE_TYPE | 1 | 8 | SRFF_C
+SIGNAL | NODE | IDE_BASEADR<2>.CLKF | 5154 | ? | 0 | 4096 | IDE_BASEADR<2> | NULL | NULL | IDE_BASEADR<2>.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_TRUE | ide/ide_CLKF.UIM
+OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
+NODE | IDE_BASEADR<2>.Q | 5155 | ? | 0 | 0 | IDE_BASEADR<2> | NULL | NULL | IDE_BASEADR<2>.REG | 0 | 8 | SRFF_Q
+
+INPUT_INSTANCE | 0 | 0 | NULL | N0 | LAN_IDE_CP_COPY_0_COPY_0 | 16 | 1 | 1
+INPUT_NODE_TYPE | 0 | 5 | II_IN
+NODE | D<11> | 5030 | PIPO | 0 | 64 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | D<11> | 0 | 6 | OI_OUT
+OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX
+NODE | N0 | 4963 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | N0 | 0 | 5 | II_IMUX
+
+MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped | IDE_BASEADR<3> | LAN_IDE_CP_COPY_0_COPY_0 | 2155877376 | 16 | 1
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | IDE_BASEADR<3> | 4949 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_BASEADR<3>.Q | IDE_BASEADR<3> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | UDS_IBUF | 4924 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | UDS_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_5_IBUF | 4927 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_4_IBUF | 4928 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_4_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_1_IBUF | 4929 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_1_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_6_IBUF | 4930 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_6_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_3_IBUF | 4931 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_2_IBUF | 4932 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<0> | 4937 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<0>.Q | AUTO_CONFIG_DONE<0> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<1> | 4938 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<1>.Q | AUTO_CONFIG_DONE<1> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | autoconfig | 4957 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.Q | autoconfig | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | N0 | 4963 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | N0 | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | ide/ide_CLKF.UIM | 5040 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ide/ide_CLKF.Q | ide/ide_CLKF | 1 | 0 | MC_UIM
+OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
+NODE | IDE_BASEADR<3> | 4949 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_BASEADR<3>.Q | IDE_BASEADR<3> | 1 | 0 | MC_UIM
+
+SIGNAL_INSTANCE | IDE_BASEADR<3>.SI | IDE_BASEADR<3> | 0 | 16 | 3
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | IDE_BASEADR<3> | 4949 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_BASEADR<3>.Q | IDE_BASEADR<3> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | UDS_IBUF | 4924 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | UDS_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_5_IBUF | 4927 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_4_IBUF | 4928 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_4_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_1_IBUF | 4929 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_1_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_6_IBUF | 4930 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_6_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_3_IBUF | 4931 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_2_IBUF | 4932 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<0> | 4937 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<0>.Q | AUTO_CONFIG_DONE<0> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<1> | 4938 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<1>.Q | AUTO_CONFIG_DONE<1> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | autoconfig | 4957 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.Q | autoconfig | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | N0 | 4963 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | N0 | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | ide/ide_CLKF.UIM | 5040 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ide/ide_CLKF.Q | ide/ide_CLKF | 1 | 0 | MC_UIM
+OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
+SIGNAL | NODE | IDE_BASEADR<3>.D1 | 5157 | ? | 0 | 4096 | IDE_BASEADR<3> | NULL | NULL | IDE_BASEADR<3>.SI | 1 | 9 | MC_SI_D1
+SPPTERM | 0 | IV_ZERO
+OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
+SIGNAL | NODE | IDE_BASEADR<3>.D2 | 5158 | ? | 0 | 4096 | IDE_BASEADR<3> | NULL | NULL | IDE_BASEADR<3>.SI | 2 | 9 | MC_SI_D2
+SPPTERM | 2 | IV_FALSE | RESET_IBUF | IV_FALSE | IDE_BASEADR<3>
+SPPTERM | 14 | IV_FALSE | UDS_IBUF | IV_FALSE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_FALSE | A_4_IBUF | IV_FALSE | A_1_IBUF | IV_TRUE | A_6_IBUF | IV_TRUE | A_3_IBUF | IV_FALSE | A_2_IBUF | IV_TRUE | AUTO_CONFIG_DONE<0> | IV_FALSE | AUTO_CONFIG_DONE<1> | IV_FALSE | IDE_BASEADR<3> | IV_TRUE | autoconfig | IV_TRUE | N0
+SPPTERM | 15 | IV_TRUE | RESET_IBUF | IV_FALSE | UDS_IBUF | IV_FALSE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_FALSE | A_4_IBUF | IV_FALSE | A_1_IBUF | IV_TRUE | A_6_IBUF | IV_TRUE | A_3_IBUF | IV_FALSE | A_2_IBUF | IV_TRUE | AUTO_CONFIG_DONE<0> | IV_FALSE | AUTO_CONFIG_DONE<1> | IV_TRUE | IDE_BASEADR<3> | IV_TRUE | autoconfig | IV_FALSE | N0
+OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF
+SIGNAL | NODE | IDE_BASEADR<3>.CLKF | 5159 | ? | 0 | 4096 | IDE_BASEADR<3> | NULL | NULL | IDE_BASEADR<3>.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_TRUE | ide/ide_CLKF.UIM
+
+SRFF_INSTANCE | IDE_BASEADR<3>.REG | IDE_BASEADR<3> | 0 | 2 | 1
+INPUT_NODE_TYPE | 0 | 8 | SRFF_D
+NODE | IDE_BASEADR<3>.D | 5156 | ? | 0 | 0 | IDE_BASEADR<3> | NULL | NULL | IDE_BASEADR<3>.XOR | 0 | 7 | ALU_F
+INPUT_NODE_TYPE | 1 | 8 | SRFF_C
+SIGNAL | NODE | IDE_BASEADR<3>.CLKF | 5159 | ? | 0 | 4096 | IDE_BASEADR<3> | NULL | NULL | IDE_BASEADR<3>.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_TRUE | ide/ide_CLKF.UIM
+OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
+NODE | IDE_BASEADR<3>.Q | 5160 | ? | 0 | 0 | IDE_BASEADR<3> | NULL | NULL | IDE_BASEADR<3>.REG | 0 | 8 | SRFF_Q
+
+INPUT_INSTANCE | 0 | 0 | NULL | N3 | LAN_IDE_CP_COPY_0_COPY_0 | 16 | 1 | 1
+INPUT_NODE_TYPE | 0 | 5 | II_IN
+NODE | D<14> | 5015 | PIPO | 0 | 64 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | D<14> | 0 | 6 | OI_OUT
+OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX
+NODE | N3 | 4966 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | N3 | 0 | 5 | II_IMUX
+
+MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped | IDE_BASEADR<6> | LAN_IDE_CP_COPY_0_COPY_0 | 2155877376 | 16 | 2
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | IDE_BASEADR<6> | 4950 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_BASEADR<6>.Q | IDE_BASEADR<6> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_5_IBUF | 4927 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_4_IBUF | 4928 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_4_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_1_IBUF | 4929 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_1_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_6_IBUF | 4930 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_6_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_3_IBUF | 4931 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<0> | 4937 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<0>.Q | AUTO_CONFIG_DONE<0> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<1> | 4938 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<1>.Q | AUTO_CONFIG_DONE<1> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | autoconfig | 4957 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.Q | autoconfig | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<2> | 4939 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<2>.Q | AUTO_CONFIG_DONE<2> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_2_IBUF | 4932 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | IDE_BASEADR<7>.EXP | 5369 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_BASEADR<7>.EXP | IDE_BASEADR<7> | 4 | 0 | MC_EXPORT
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | ide/ide_CLKF.UIM | 5040 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ide/ide_CLKF.Q | ide/ide_CLKF | 1 | 0 | MC_UIM
+OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
+NODE | IDE_BASEADR<6> | 4950 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_BASEADR<6>.Q | IDE_BASEADR<6> | 1 | 0 | MC_UIM
+OUTPUT_NODE_TYPE | 4 | 0 | MC_EXPORT
+NODE | IDE_BASEADR<6>.EXP | 5370 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_BASEADR<6>.EXP | IDE_BASEADR<6> | 4 | 0 | MC_EXPORT
+
+SIGNAL_INSTANCE | IDE_BASEADR<6>.SI | IDE_BASEADR<6> | 0 | 16 | 4
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | IDE_BASEADR<6> | 4950 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_BASEADR<6>.Q | IDE_BASEADR<6> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_5_IBUF | 4927 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_4_IBUF | 4928 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_4_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_1_IBUF | 4929 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_1_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_6_IBUF | 4930 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_6_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_3_IBUF | 4931 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<0> | 4937 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<0>.Q | AUTO_CONFIG_DONE<0> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<1> | 4938 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<1>.Q | AUTO_CONFIG_DONE<1> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | autoconfig | 4957 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.Q | autoconfig | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<2> | 4939 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<2>.Q | AUTO_CONFIG_DONE<2> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_2_IBUF | 4932 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | IDE_BASEADR<7>.EXP | 5369 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_BASEADR<7>.EXP | IDE_BASEADR<7> | 4 | 0 | MC_EXPORT
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | ide/ide_CLKF.UIM | 5040 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ide/ide_CLKF.Q | ide/ide_CLKF | 1 | 0 | MC_UIM
+OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
+SIGNAL | NODE | IDE_BASEADR<6>.D1 | 5162 | ? | 0 | 4096 | IDE_BASEADR<6> | NULL | NULL | IDE_BASEADR<6>.SI | 1 | 9 | MC_SI_D1
+SPPTERM | 0 | IV_ZERO
+OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
+SIGNAL | NODE | IDE_BASEADR<6>.D2 | 5163 | ? | 0 | 4096 | IDE_BASEADR<6> | NULL | NULL | IDE_BASEADR<6>.SI | 2 | 9 | MC_SI_D2
+SPPTERM | 1 | IV_TRUE | IDE_BASEADR<7>.EXP
+SPPTERM | 2 | IV_FALSE | RESET_IBUF | IV_FALSE | IDE_BASEADR<6>
+OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF
+SIGNAL | NODE | IDE_BASEADR<6>.CLKF | 5164 | ? | 0 | 4096 | IDE_BASEADR<6> | NULL | NULL | IDE_BASEADR<6>.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_TRUE | ide/ide_CLKF.UIM
+OUTPUT_NODE_TYPE | 7 | 9 | MC_SI_EXPORT
+SIGNAL | NODE | IDE_BASEADR<6>.EXP | 5362 | ? | 0 | 0 | IDE_BASEADR<6> | NULL | NULL | IDE_BASEADR<6>.SI | 7 | 9 | MC_SI_EXPORT
+SPPTERM | 11 | IV_TRUE | RESET_IBUF | IV_TRUE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_TRUE | A_4_IBUF | IV_FALSE | A_1_IBUF | IV_FALSE | A_6_IBUF | IV_TRUE | A_3_IBUF | IV_TRUE | AUTO_CONFIG_DONE<0> | IV_FALSE | AUTO_CONFIG_DONE<1> | IV_TRUE | autoconfig
+SPPTERM | 11 | IV_TRUE | RESET_IBUF | IV_TRUE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_FALSE | A_4_IBUF | IV_FALSE | A_1_IBUF | IV_FALSE | A_6_IBUF | IV_FALSE | A_3_IBUF | IV_TRUE | AUTO_CONFIG_DONE<1> | IV_FALSE | AUTO_CONFIG_DONE<2> | IV_TRUE | autoconfig
+SPPTERM | 12 | IV_TRUE | RESET_IBUF | IV_TRUE | RW_IBUF | IV_FALSE | AS_IBUF | IV_TRUE | A_5_IBUF | IV_FALSE | A_4_IBUF | IV_FALSE | A_1_IBUF | IV_FALSE | A_6_IBUF | IV_FALSE | A_3_IBUF | IV_TRUE | A_2_IBUF | IV_TRUE | AUTO_CONFIG_DONE<0> | IV_FALSE | AUTO_CONFIG_DONE<1> | IV_TRUE | autoconfig
+
+SRFF_INSTANCE | IDE_BASEADR<6>.REG | IDE_BASEADR<6> | 0 | 2 | 1
+INPUT_NODE_TYPE | 0 | 8 | SRFF_D
+NODE | IDE_BASEADR<6>.D | 5161 | ? | 0 | 0 | IDE_BASEADR<6> | NULL | NULL | IDE_BASEADR<6>.XOR | 0 | 7 | ALU_F
+INPUT_NODE_TYPE | 1 | 8 | SRFF_C
+SIGNAL | NODE | IDE_BASEADR<6>.CLKF | 5164 | ? | 0 | 4096 | IDE_BASEADR<6> | NULL | NULL | IDE_BASEADR<6>.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_TRUE | ide/ide_CLKF.UIM
+OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
+NODE | IDE_BASEADR<6>.Q | 5165 | ? | 0 | 0 | IDE_BASEADR<6> | NULL | NULL | IDE_BASEADR<6>.REG | 0 | 8 | SRFF_Q
+
+INPUT_INSTANCE | 0 | 0 | NULL | N4 | LAN_IDE_CP_COPY_0_COPY_0 | 16 | 1 | 1
+INPUT_NODE_TYPE | 0 | 5 | II_IN
+NODE | D<15> | 5016 | PIPO | 0 | 64 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | D<15> | 0 | 6 | OI_OUT
+OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX
+NODE | N4 | 4967 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | N4 | 0 | 5 | II_IMUX
+
+MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped | IDE_BASEADR<7> | LAN_IDE_CP_COPY_0_COPY_0 | 2155877376 | 19 | 2
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | IDE_BASEADR<7> | 4951 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_BASEADR<7>.Q | IDE_BASEADR<7> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | UDS_IBUF | 4924 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | UDS_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_5_IBUF | 4927 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_4_IBUF | 4928 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_4_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_1_IBUF | 4929 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_1_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_6_IBUF | 4930 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_6_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_3_IBUF | 4931 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_2_IBUF | 4932 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<0> | 4937 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<0>.Q | AUTO_CONFIG_DONE<0> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<1> | 4938 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<1>.Q | AUTO_CONFIG_DONE<1> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | autoconfig | 4957 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.Q | autoconfig | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | N4 | 4967 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | N4 | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | ide/ide_CLKF.UIM | 5040 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ide/ide_CLKF.Q | ide/ide_CLKF | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | IDE_BASEADR<6> | 4950 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_BASEADR<6>.Q | IDE_BASEADR<6> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | N3 | 4966 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | N3 | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE_CYCLE<0>.EXP | 5368 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE_CYCLE<0>.EXP | AUTO_CONFIG_DONE_CYCLE<0> | 4 | 0 | MC_EXPORT
+OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
+NODE | IDE_BASEADR<7> | 4951 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_BASEADR<7>.Q | IDE_BASEADR<7> | 1 | 0 | MC_UIM
+OUTPUT_NODE_TYPE | 4 | 0 | MC_EXPORT
+NODE | IDE_BASEADR<7>.EXP | 5369 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_BASEADR<7>.EXP | IDE_BASEADR<7> | 4 | 0 | MC_EXPORT
+
+SIGNAL_INSTANCE | IDE_BASEADR<7>.SI | IDE_BASEADR<7> | 0 | 19 | 4
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | IDE_BASEADR<7> | 4951 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_BASEADR<7>.Q | IDE_BASEADR<7> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | UDS_IBUF | 4924 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | UDS_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_5_IBUF | 4927 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_4_IBUF | 4928 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_4_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_1_IBUF | 4929 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_1_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_6_IBUF | 4930 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_6_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_3_IBUF | 4931 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_2_IBUF | 4932 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<0> | 4937 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<0>.Q | AUTO_CONFIG_DONE<0> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<1> | 4938 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<1>.Q | AUTO_CONFIG_DONE<1> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | autoconfig | 4957 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.Q | autoconfig | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | N4 | 4967 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | N4 | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | ide/ide_CLKF.UIM | 5040 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ide/ide_CLKF.Q | ide/ide_CLKF | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | IDE_BASEADR<6> | 4950 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_BASEADR<6>.Q | IDE_BASEADR<6> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | N3 | 4966 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | N3 | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE_CYCLE<0>.EXP | 5368 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE_CYCLE<0>.EXP | AUTO_CONFIG_DONE_CYCLE<0> | 4 | 0 | MC_EXPORT
+OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
+SIGNAL | NODE | IDE_BASEADR<7>.D1 | 5167 | ? | 0 | 4096 | IDE_BASEADR<7> | NULL | NULL | IDE_BASEADR<7>.SI | 1 | 9 | MC_SI_D1
+SPPTERM | 0 | IV_ZERO
+OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
+SIGNAL | NODE | IDE_BASEADR<7>.D2 | 5168 | ? | 0 | 4096 | IDE_BASEADR<7> | NULL | NULL | IDE_BASEADR<7>.SI | 2 | 9 | MC_SI_D2
+SPPTERM | 1 | IV_TRUE | AUTO_CONFIG_DONE_CYCLE<0>.EXP
+SPPTERM | 2 | IV_FALSE | RESET_IBUF | IV_FALSE | IDE_BASEADR<7>
+SPPTERM | 14 | IV_FALSE | UDS_IBUF | IV_FALSE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_FALSE | A_4_IBUF | IV_FALSE | A_1_IBUF | IV_TRUE | A_6_IBUF | IV_TRUE | A_3_IBUF | IV_FALSE | A_2_IBUF | IV_TRUE | AUTO_CONFIG_DONE<0> | IV_FALSE | AUTO_CONFIG_DONE<1> | IV_FALSE | IDE_BASEADR<7> | IV_TRUE | autoconfig | IV_TRUE | N4
+OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF
+SIGNAL | NODE | IDE_BASEADR<7>.CLKF | 5169 | ? | 0 | 4096 | IDE_BASEADR<7> | NULL | NULL | IDE_BASEADR<7>.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_TRUE | ide/ide_CLKF.UIM
+OUTPUT_NODE_TYPE | 7 | 9 | MC_SI_EXPORT
+SIGNAL | NODE | IDE_BASEADR<7>.EXP | 5361 | ? | 0 | 0 | IDE_BASEADR<7> | NULL | NULL | IDE_BASEADR<7>.SI | 7 | 9 | MC_SI_EXPORT
+SPPTERM | 14 | IV_FALSE | UDS_IBUF | IV_FALSE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_FALSE | A_4_IBUF | IV_FALSE | A_1_IBUF | IV_TRUE | A_6_IBUF | IV_TRUE | A_3_IBUF | IV_FALSE | A_2_IBUF | IV_TRUE | AUTO_CONFIG_DONE<0> | IV_FALSE | AUTO_CONFIG_DONE<1> | IV_FALSE | IDE_BASEADR<6> | IV_TRUE | autoconfig | IV_TRUE | N3
+SPPTERM | 15 | IV_TRUE | RESET_IBUF | IV_FALSE | UDS_IBUF | IV_FALSE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_FALSE | A_4_IBUF | IV_FALSE | A_1_IBUF | IV_TRUE | A_6_IBUF | IV_TRUE | A_3_IBUF | IV_FALSE | A_2_IBUF | IV_TRUE | AUTO_CONFIG_DONE<0> | IV_FALSE | AUTO_CONFIG_DONE<1> | IV_TRUE | IDE_BASEADR<6> | IV_TRUE | autoconfig | IV_FALSE | N3
+
+SRFF_INSTANCE | IDE_BASEADR<7>.REG | IDE_BASEADR<7> | 0 | 2 | 1
+INPUT_NODE_TYPE | 0 | 8 | SRFF_D
+NODE | IDE_BASEADR<7>.D | 5166 | ? | 0 | 0 | IDE_BASEADR<7> | NULL | NULL | IDE_BASEADR<7>.XOR | 0 | 7 | ALU_F
+INPUT_NODE_TYPE | 1 | 8 | SRFF_C
+SIGNAL | NODE | IDE_BASEADR<7>.CLKF | 5169 | ? | 0 | 4096 | IDE_BASEADR<7> | NULL | NULL | IDE_BASEADR<7>.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_TRUE | ide/ide_CLKF.UIM
+OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
+NODE | IDE_BASEADR<7>.Q | 5170 | ? | 0 | 0 | IDE_BASEADR<7> | NULL | NULL | IDE_BASEADR<7>.REG | 0 | 8 | SRFF_Q
+
+MACROCELL_INSTANCE | Inv+PrldLow+OptxMapped | SHUT_UP<1> | LAN_IDE_CP_COPY_0_COPY_0 | 2155873536 | 15 | 1
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | SHUT_UP<1> | 4952 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | SHUT_UP<1>.Q | SHUT_UP<1> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | UDS_IBUF | 4924 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | UDS_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_5_IBUF | 4927 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_4_IBUF | 4928 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_4_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_1_IBUF | 4929 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_1_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_6_IBUF | 4930 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_6_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_3_IBUF | 4931 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_2_IBUF | 4932 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<0> | 4937 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<0>.Q | AUTO_CONFIG_DONE<0> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<1> | 4938 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<1>.Q | AUTO_CONFIG_DONE<1> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | autoconfig | 4957 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.Q | autoconfig | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | ide/ide_CLKF.UIM | 5040 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ide/ide_CLKF.Q | ide/ide_CLKF | 1 | 0 | MC_UIM
+OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
+NODE | SHUT_UP<1> | 4952 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | SHUT_UP<1>.Q | SHUT_UP<1> | 1 | 0 | MC_UIM
+
+SIGNAL_INSTANCE | SHUT_UP<1>.SI | SHUT_UP<1> | 0 | 15 | 3
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | SHUT_UP<1> | 4952 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | SHUT_UP<1>.Q | SHUT_UP<1> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | UDS_IBUF | 4924 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | UDS_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_5_IBUF | 4927 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_4_IBUF | 4928 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_4_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_1_IBUF | 4929 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_1_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_6_IBUF | 4930 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_6_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_3_IBUF | 4931 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_2_IBUF | 4932 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<0> | 4937 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<0>.Q | AUTO_CONFIG_DONE<0> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<1> | 4938 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<1>.Q | AUTO_CONFIG_DONE<1> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | autoconfig | 4957 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.Q | autoconfig | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | ide/ide_CLKF.UIM | 5040 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ide/ide_CLKF.Q | ide/ide_CLKF | 1 | 0 | MC_UIM
+OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
+SIGNAL | NODE | SHUT_UP<1>.D1 | 5172 | ? | 0 | 4096 | SHUT_UP<1> | NULL | NULL | SHUT_UP<1>.SI | 1 | 9 | MC_SI_D1
+SPPTERM | 0 | IV_ZERO
+OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
+SIGNAL | NODE | SHUT_UP<1>.D2 | 5173 | ? | 0 | 4096 | SHUT_UP<1> | NULL | NULL | SHUT_UP<1>.SI | 2 | 9 | MC_SI_D2
+SPPTERM | 2 | IV_TRUE | RESET_IBUF | IV_FALSE | SHUT_UP<1>
+SPPTERM | 13 | IV_TRUE | RESET_IBUF | IV_FALSE | UDS_IBUF | IV_FALSE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_FALSE | A_4_IBUF | IV_FALSE | A_1_IBUF | IV_TRUE | A_6_IBUF | IV_TRUE | A_3_IBUF | IV_FALSE | A_2_IBUF | IV_TRUE | AUTO_CONFIG_DONE<0> | IV_FALSE | AUTO_CONFIG_DONE<1> | IV_TRUE | autoconfig
+OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF
+SIGNAL | NODE | SHUT_UP<1>.CLKF | 5174 | ? | 0 | 4096 | SHUT_UP<1> | NULL | NULL | SHUT_UP<1>.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_TRUE | ide/ide_CLKF.UIM
+
+SRFF_INSTANCE | SHUT_UP<1>.REG | SHUT_UP<1> | 0 | 2 | 1
+INPUT_NODE_TYPE | 0 | 8 | SRFF_D
+NODE | SHUT_UP<1>.D | 5171 | ? | 0 | 0 | SHUT_UP<1> | NULL | NULL | SHUT_UP<1>.XOR | 0 | 7 | ALU_F
+INPUT_NODE_TYPE | 1 | 8 | SRFF_C
+SIGNAL | NODE | SHUT_UP<1>.CLKF | 5174 | ? | 0 | 4096 | SHUT_UP<1> | NULL | NULL | SHUT_UP<1>.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_TRUE | ide/ide_CLKF.UIM
+OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
+NODE | SHUT_UP<1>.Q | 5175 | ? | 0 | 0 | SHUT_UP<1> | NULL | NULL | SHUT_UP<1>.REG | 0 | 8 | SRFF_Q
+
+INPUT_INSTANCE | 0 | 0 | NULL | BERR_IBUF | LAN_IDE_CP_COPY_0_COPY_0 | 16 | 1 | 1
+INPUT_NODE_TYPE | 0 | 5 | II_IN
+NODE | BERR | 5056 | PI | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE
+OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX
+NODE | BERR_IBUF | 4954 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | BERR_IBUF | 0 | 5 | II_IMUX
+
+INPUT_INSTANCE | 0 | 0 | NULL | C1_IBUF | LAN_IDE_CP_COPY_0_COPY_0 | 16 | 1 | 1
+INPUT_NODE_TYPE | 0 | 5 | II_IN
+NODE | C1 | 5057 | PI | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE
+OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX
+NODE | C1_IBUF | 4955 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | C1_IBUF | 0 | 5 | II_IMUX
+
+INPUT_INSTANCE | 0 | 0 | NULL | C3_IBUF | LAN_IDE_CP_COPY_0_COPY_0 | 16 | 1 | 1
+INPUT_NODE_TYPE | 0 | 5 | II_IN
+NODE | C3 | 5058 | PI | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE
+OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX
+NODE | C3_IBUF | 4956 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | C3_IBUF | 0 | 5 | II_IMUX
+
+INPUT_INSTANCE | 0 | 0 | NULL | A_16_IBUF | LAN_IDE_CP_COPY_0_COPY_0 | 16 | 1 | 1
+INPUT_NODE_TYPE | 0 | 5 | II_IN
+NODE | A<16> | 5060 | PI | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE
+OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX
+NODE | A_16_IBUF | 4969 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_16_IBUF | 0 | 5 | II_IMUX
+
+INPUT_INSTANCE | 0 | 0 | NULL | A_20_IBUF | LAN_IDE_CP_COPY_0_COPY_0 | 16 | 1 | 1
+INPUT_NODE_TYPE | 0 | 5 | II_IN
+NODE | A<20> | 5061 | PI | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE
+OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX
+NODE | A_20_IBUF | 4970 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_20_IBUF | 0 | 5 | II_IMUX
+
+INPUT_INSTANCE | 0 | 0 | NULL | A_17_IBUF | LAN_IDE_CP_COPY_0_COPY_0 | 16 | 1 | 1
+INPUT_NODE_TYPE | 0 | 5 | II_IN
+NODE | A<17> | 5059 | PI | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE
+OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX
+NODE | A_17_IBUF | 4968 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_17_IBUF | 0 | 5 | II_IMUX
+
+INPUT_INSTANCE | 0 | 0 | NULL | A_18_IBUF | LAN_IDE_CP_COPY_0_COPY_0 | 16 | 1 | 1
+INPUT_NODE_TYPE | 0 | 5 | II_IN
+NODE | A<18> | 5062 | PI | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE
+OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX
+NODE | A_18_IBUF | 4971 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_18_IBUF | 0 | 5 | II_IMUX
+
+MACROCELL_INSTANCE | PrldLow+OptxMapped | autoconfig | LAN_IDE_CP_COPY_0_COPY_0 | 2155873280 | 14 | 2
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_23_IBUF | 4933 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_23_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_22_IBUF | 4934 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_22_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_21_IBUF | 4935 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_21_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_19_IBUF | 4936 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_19_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<0> | 4937 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<0>.Q | AUTO_CONFIG_DONE<0> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | BERR_IBUF | 4954 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | BERR_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_17_IBUF | 4968 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_17_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_16_IBUF | 4969 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_16_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_20_IBUF | 4970 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_20_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_18_IBUF | 4971 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_18_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<1> | 4938 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<1>.Q | AUTO_CONFIG_DONE<1> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<2> | 4939 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<2>.Q | AUTO_CONFIG_DONE<2> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | ide/ide_CLKF.UIM | 5040 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ide/ide_CLKF.Q | ide/ide_CLKF | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | IDE_BASEADR<5> | 4945 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_BASEADR<5>.Q | IDE_BASEADR<5> | 1 | 0 | MC_UIM
+OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
+NODE | autoconfig | 4957 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.Q | autoconfig | 1 | 0 | MC_UIM
+OUTPUT_NODE_TYPE | 4 | 0 | MC_EXPORT
+NODE | autoconfig.EXP | 5380 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.EXP | autoconfig | 4 | 0 | MC_EXPORT
+
+SIGNAL_INSTANCE | autoconfig.SI | autoconfig | 0 | 14 | 4
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_23_IBUF | 4933 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_23_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_22_IBUF | 4934 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_22_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_21_IBUF | 4935 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_21_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_19_IBUF | 4936 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_19_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<0> | 4937 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<0>.Q | AUTO_CONFIG_DONE<0> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | BERR_IBUF | 4954 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | BERR_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_17_IBUF | 4968 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_17_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_16_IBUF | 4969 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_16_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_20_IBUF | 4970 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_20_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_18_IBUF | 4971 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_18_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<1> | 4938 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<1>.Q | AUTO_CONFIG_DONE<1> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<2> | 4939 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<2>.Q | AUTO_CONFIG_DONE<2> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | ide/ide_CLKF.UIM | 5040 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ide/ide_CLKF.Q | ide/ide_CLKF | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | IDE_BASEADR<5> | 4945 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_BASEADR<5>.Q | IDE_BASEADR<5> | 1 | 0 | MC_UIM
+OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
+SIGNAL | NODE | autoconfig.D1 | 5177 | ? | 0 | 4096 | autoconfig | NULL | NULL | autoconfig.SI | 1 | 9 | MC_SI_D1
+SPPTERM | 0 | IV_ZERO
+OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
+SIGNAL | NODE | autoconfig.D2 | 5178 | ? | 0 | 4096 | autoconfig | NULL | NULL | autoconfig.SI | 2 | 9 | MC_SI_D2
+SPPTERM | 10 | IV_TRUE | A_23_IBUF | IV_TRUE | A_22_IBUF | IV_TRUE | A_21_IBUF | IV_TRUE | A_19_IBUF | IV_FALSE | AUTO_CONFIG_DONE<0> | IV_TRUE | BERR_IBUF | IV_FALSE | A_17_IBUF | IV_FALSE | A_16_IBUF | IV_FALSE | A_20_IBUF | IV_FALSE | A_18_IBUF
+SPPTERM | 10 | IV_TRUE | A_23_IBUF | IV_TRUE | A_22_IBUF | IV_TRUE | A_21_IBUF | IV_TRUE | A_19_IBUF | IV_FALSE | AUTO_CONFIG_DONE<1> | IV_TRUE | BERR_IBUF | IV_FALSE | A_17_IBUF | IV_FALSE | A_16_IBUF | IV_FALSE | A_20_IBUF | IV_FALSE | A_18_IBUF
+SPPTERM | 10 | IV_TRUE | A_23_IBUF | IV_TRUE | A_22_IBUF | IV_TRUE | A_21_IBUF | IV_TRUE | A_19_IBUF | IV_FALSE | AUTO_CONFIG_DONE<2> | IV_TRUE | BERR_IBUF | IV_FALSE | A_17_IBUF | IV_FALSE | A_16_IBUF | IV_FALSE | A_20_IBUF | IV_FALSE | A_18_IBUF
+OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF
+SIGNAL | NODE | autoconfig.CLKF | 5179 | ? | 0 | 4096 | autoconfig | NULL | NULL | autoconfig.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_TRUE | ide/ide_CLKF.UIM
+OUTPUT_NODE_TYPE | 7 | 9 | MC_SI_EXPORT
+SIGNAL | NODE | autoconfig.EXP | 5376 | ? | 0 | 0 | autoconfig | NULL | NULL | autoconfig.SI | 7 | 9 | MC_SI_EXPORT
+SPPTERM | 2 | IV_TRUE | A_21_IBUF | IV_FALSE | IDE_BASEADR<5>
+
+SRFF_INSTANCE | autoconfig.REG | autoconfig | 0 | 2 | 1
+INPUT_NODE_TYPE | 0 | 8 | SRFF_D
+NODE | autoconfig.D | 5176 | ? | 0 | 0 | autoconfig | NULL | NULL | autoconfig.XOR | 0 | 7 | ALU_F
+INPUT_NODE_TYPE | 1 | 8 | SRFF_C
+SIGNAL | NODE | autoconfig.CLKF | 5179 | ? | 0 | 4096 | autoconfig | NULL | NULL | autoconfig.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_TRUE | ide/ide_CLKF.UIM
+OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
+NODE | autoconfig.Q | 5180 | ? | 0 | 0 | autoconfig | NULL | NULL | autoconfig.REG | 0 | 8 | SRFF_Q
+
+MACROCELL_INSTANCE | Inv+PrldLow+OptxMapped | ide | LAN_IDE_CP_COPY_0_COPY_0 | 2155873536 | 7 | 1
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | BERR_IBUF | 4954 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | BERR_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | SHUT_UP<1> | 4952 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | SHUT_UP<1>.Q | SHUT_UP<1> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_19_IBUF | 4936 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_19_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | IDE_BASEADR<3> | 4949 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_BASEADR<3>.Q | IDE_BASEADR<3> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | EXP19_.EXP | 5378 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | EXP19_.EXP | EXP19_ | 4 | 0 | MC_EXPORT
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | EXP21_.EXP | 5381 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | EXP21_.EXP | EXP21_ | 4 | 0 | MC_EXPORT
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | ide/ide_CLKF.UIM | 5040 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ide/ide_CLKF.Q | ide/ide_CLKF | 1 | 0 | MC_UIM
+OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
+NODE | ide | 4958 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ide.Q | ide | 1 | 0 | MC_UIM
+
+SIGNAL_INSTANCE | ide.SI | ide | 0 | 7 | 3
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | BERR_IBUF | 4954 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | BERR_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | SHUT_UP<1> | 4952 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | SHUT_UP<1>.Q | SHUT_UP<1> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_19_IBUF | 4936 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_19_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | IDE_BASEADR<3> | 4949 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_BASEADR<3>.Q | IDE_BASEADR<3> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | EXP19_.EXP | 5378 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | EXP19_.EXP | EXP19_ | 4 | 0 | MC_EXPORT
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | EXP21_.EXP | 5381 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | EXP21_.EXP | EXP21_ | 4 | 0 | MC_EXPORT
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | ide/ide_CLKF.UIM | 5040 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ide/ide_CLKF.Q | ide/ide_CLKF | 1 | 0 | MC_UIM
+OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
+SIGNAL | NODE | ide.D1 | 5182 | ? | 0 | 4096 | ide | NULL | NULL | ide.SI | 1 | 9 | MC_SI_D1
+SPPTERM | 0 | IV_ZERO
+OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
+SIGNAL | NODE | ide.D2 | 5183 | ? | 0 | 4096 | ide | NULL | NULL | ide.SI | 2 | 9 | MC_SI_D2
+SPPTERM | 1 | IV_TRUE | SHUT_UP<1>
+SPPTERM | 1 | IV_FALSE | BERR_IBUF
+SPPTERM | 1 | IV_TRUE | EXP19_.EXP
+SPPTERM | 1 | IV_TRUE | EXP21_.EXP
+SPPTERM | 2 | IV_TRUE | A_19_IBUF | IV_FALSE | IDE_BASEADR<3>
+SPPTERM | 2 | IV_FALSE | A_19_IBUF | IV_TRUE | IDE_BASEADR<3>
+OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF
+SIGNAL | NODE | ide.CLKF | 5184 | ? | 0 | 4096 | ide | NULL | NULL | ide.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_TRUE | ide/ide_CLKF.UIM
+
+SRFF_INSTANCE | ide.REG | ide | 0 | 2 | 1
+INPUT_NODE_TYPE | 0 | 8 | SRFF_D
+NODE | ide.D | 5181 | ? | 0 | 0 | ide | NULL | NULL | ide.XOR | 0 | 7 | ALU_F
+INPUT_NODE_TYPE | 1 | 8 | SRFF_C
+SIGNAL | NODE | ide.CLKF | 5184 | ? | 0 | 4096 | ide | NULL | NULL | ide.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_TRUE | ide/ide_CLKF.UIM
+OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
+NODE | ide.Q | 5185 | ? | 0 | 0 | ide | NULL | NULL | ide.REG | 0 | 8 | SRFF_Q
+
+MACROCELL_INSTANCE | PrldLow+OptxMapped | AUTOCONFIG_IN_PROGRESS | LAN_IDE_CP_COPY_0_COPY_0 | 2155873280 | 3 | 1
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | autoconfig | 4957 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.Q | autoconfig | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | ide/ide_CLKF.UIM | 5040 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ide/ide_CLKF.Q | ide/ide_CLKF | 1 | 0 | MC_UIM
+OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
+NODE | AUTOCONFIG_IN_PROGRESS | 4959 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTOCONFIG_IN_PROGRESS.Q | AUTOCONFIG_IN_PROGRESS | 1 | 0 | MC_UIM
+
+SIGNAL_INSTANCE | AUTOCONFIG_IN_PROGRESS.SI | AUTOCONFIG_IN_PROGRESS | 0 | 3 | 3
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | autoconfig | 4957 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.Q | autoconfig | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | ide/ide_CLKF.UIM | 5040 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ide/ide_CLKF.Q | ide/ide_CLKF | 1 | 0 | MC_UIM
+OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
+SIGNAL | NODE | AUTOCONFIG_IN_PROGRESS.D1 | 5187 | ? | 0 | 4096 | AUTOCONFIG_IN_PROGRESS | NULL | NULL | AUTOCONFIG_IN_PROGRESS.SI | 1 | 9 | MC_SI_D1
+SPPTERM | 0 | IV_ZERO
+OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
+SIGNAL | NODE | AUTOCONFIG_IN_PROGRESS.D2 | 5188 | ? | 0 | 4096 | AUTOCONFIG_IN_PROGRESS | NULL | NULL | AUTOCONFIG_IN_PROGRESS.SI | 2 | 9 | MC_SI_D2
+SPPTERM | 2 | IV_FALSE | AS_IBUF | IV_TRUE | autoconfig
+OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF
+SIGNAL | NODE | AUTOCONFIG_IN_PROGRESS.CLKF | 5189 | ? | 0 | 4096 | AUTOCONFIG_IN_PROGRESS | NULL | NULL | AUTOCONFIG_IN_PROGRESS.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_TRUE | ide/ide_CLKF.UIM
+
+SRFF_INSTANCE | AUTOCONFIG_IN_PROGRESS.REG | AUTOCONFIG_IN_PROGRESS | 0 | 2 | 1
+INPUT_NODE_TYPE | 0 | 8 | SRFF_D
+NODE | AUTOCONFIG_IN_PROGRESS.D | 5186 | ? | 0 | 0 | AUTOCONFIG_IN_PROGRESS | NULL | NULL | AUTOCONFIG_IN_PROGRESS.XOR | 0 | 7 | ALU_F
+INPUT_NODE_TYPE | 1 | 8 | SRFF_C
+SIGNAL | NODE | AUTOCONFIG_IN_PROGRESS.CLKF | 5189 | ? | 0 | 4096 | AUTOCONFIG_IN_PROGRESS | NULL | NULL | AUTOCONFIG_IN_PROGRESS.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_TRUE | ide/ide_CLKF.UIM
+OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
+NODE | AUTOCONFIG_IN_PROGRESS.Q | 5190 | ? | 0 | 0 | AUTOCONFIG_IN_PROGRESS | NULL | NULL | AUTOCONFIG_IN_PROGRESS.REG | 0 | 8 | SRFF_Q
+
+MACROCELL_INSTANCE | Inv+PrldHigh+OptxMapped | IDE_R_S | LAN_IDE_CP_COPY_0_COPY_0 | 2155873024 | 6 | 1
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | IDE_ENABLE | 4946 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_ENABLE.Q | IDE_ENABLE | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | ide | 4958 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ide.Q | ide | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | ide/ide_CLKF.UIM | 5040 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ide/ide_CLKF.Q | ide/ide_CLKF | 1 | 0 | MC_UIM
+OUTPUT_NODE_TYPE | 0 | 0 | MC_Q
+NODE | IDE_R_S | 4972 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_R_S.Q | IDE_R_S | 0 | 0 | MC_Q
+
+SIGNAL_INSTANCE | IDE_R_S.SI | IDE_R_S | 0 | 6 | 3
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | IDE_ENABLE | 4946 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_ENABLE.Q | IDE_ENABLE | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | ide | 4958 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ide.Q | ide | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | ide/ide_CLKF.UIM | 5040 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ide/ide_CLKF.Q | ide/ide_CLKF | 1 | 0 | MC_UIM
+OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
+SIGNAL | NODE | IDE_R_S.D1 | 5192 | ? | 0 | 4096 | IDE_R_S | NULL | NULL | IDE_R_S.SI | 1 | 9 | MC_SI_D1
+SPPTERM | 0 | IV_ZERO
+OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
+SIGNAL | NODE | IDE_R_S.D2 | 5193 | ? | 0 | 4096 | IDE_R_S | NULL | NULL | IDE_R_S.SI | 2 | 9 | MC_SI_D2
+SPPTERM | 5 | IV_TRUE | RESET_IBUF | IV_TRUE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | IDE_ENABLE | IV_TRUE | ide
+OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF
+SIGNAL | NODE | IDE_R_S.CLKF | 5194 | ? | 0 | 4096 | IDE_R_S | NULL | NULL | IDE_R_S.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_TRUE | ide/ide_CLKF.UIM
+
+SRFF_INSTANCE | IDE_R_S.REG | IDE_R_S | 0 | 2 | 1
+INPUT_NODE_TYPE | 0 | 8 | SRFF_D
+NODE | IDE_R_S.D | 5191 | ? | 0 | 0 | IDE_R_S | NULL | NULL | IDE_R_S.XOR | 0 | 7 | ALU_F
+INPUT_NODE_TYPE | 1 | 8 | SRFF_C
+SIGNAL | NODE | IDE_R_S.CLKF | 5194 | ? | 0 | 4096 | IDE_R_S | NULL | NULL | IDE_R_S.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_TRUE | ide/ide_CLKF.UIM
+OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
+NODE | IDE_R_S.Q | 5195 | ? | 0 | 0 | IDE_R_S | NULL | NULL | IDE_R_S.REG | 0 | 8 | SRFF_Q
+
+MACROCELL_INSTANCE | Inv+PrldHigh+OptxMapped | IDE_W_S | LAN_IDE_CP_COPY_0_COPY_0 | 2155873024 | 6 | 2
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | ide | 4958 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ide.Q | ide | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | ide/ide_CLKF.UIM | 5040 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ide/ide_CLKF.Q | ide/ide_CLKF | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | IDE_ENABLE | 4946 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_ENABLE.Q | IDE_ENABLE | 1 | 0 | MC_UIM
+OUTPUT_NODE_TYPE | 0 | 0 | MC_Q
+NODE | IDE_W_S | 4973 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_W_S.Q | IDE_W_S | 0 | 0 | MC_Q
+OUTPUT_NODE_TYPE | 4 | 0 | MC_EXPORT
+NODE | IDE_W_S.EXP | 5355 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_W_S.EXP | IDE_W_S | 4 | 0 | MC_EXPORT
+
+SIGNAL_INSTANCE | IDE_W_S.SI | IDE_W_S | 0 | 6 | 4
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | ide | 4958 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ide.Q | ide | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | ide/ide_CLKF.UIM | 5040 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ide/ide_CLKF.Q | ide/ide_CLKF | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | IDE_ENABLE | 4946 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_ENABLE.Q | IDE_ENABLE | 1 | 0 | MC_UIM
+OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
+SIGNAL | NODE | IDE_W_S.D1 | 5197 | ? | 0 | 4096 | IDE_W_S | NULL | NULL | IDE_W_S.SI | 1 | 9 | MC_SI_D1
+SPPTERM | 0 | IV_ZERO
+OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
+SIGNAL | NODE | IDE_W_S.D2 | 5198 | ? | 0 | 4096 | IDE_W_S | NULL | NULL | IDE_W_S.SI | 2 | 9 | MC_SI_D2
+SPPTERM | 4 | IV_TRUE | RESET_IBUF | IV_FALSE | RW_IBUF | IV_FALSE | AS_IBUF | IV_TRUE | ide
+OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF
+SIGNAL | NODE | IDE_W_S.CLKF | 5199 | ? | 0 | 4096 | IDE_W_S | NULL | NULL | IDE_W_S.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_TRUE | ide/ide_CLKF.UIM
+OUTPUT_NODE_TYPE | 7 | 9 | MC_SI_EXPORT
+SIGNAL | NODE | IDE_W_S.EXP | 5350 | ? | 0 | 0 | IDE_W_S | NULL | NULL | IDE_W_S.SI | 7 | 9 | MC_SI_EXPORT
+SPPTERM | 5 | IV_TRUE | RESET_IBUF | IV_TRUE | RW_IBUF | IV_FALSE | AS_IBUF | IV_TRUE | IDE_ENABLE | IV_TRUE | ide
+
+SRFF_INSTANCE | IDE_W_S.REG | IDE_W_S | 0 | 2 | 1
+INPUT_NODE_TYPE | 0 | 8 | SRFF_D
+NODE | IDE_W_S.D | 5196 | ? | 0 | 0 | IDE_W_S | NULL | NULL | IDE_W_S.XOR | 0 | 7 | ALU_F
+INPUT_NODE_TYPE | 1 | 8 | SRFF_C
+SIGNAL | NODE | IDE_W_S.CLKF | 5199 | ? | 0 | 4096 | IDE_W_S | NULL | NULL | IDE_W_S.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_TRUE | ide/ide_CLKF.UIM
+OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
+NODE | IDE_W_S.Q | 5200 | ? | 0 | 0 | IDE_W_S | NULL | NULL | IDE_W_S.REG | 0 | 8 | SRFF_Q
+
+MACROCELL_INSTANCE | Inv+PrldHigh+OptxMapped | ROM_OE_S | LAN_IDE_CP_COPY_0_COPY_0 | 2155873024 | 15 | 2
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_5_IBUF | 4927 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_4_IBUF | 4928 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_4_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | ide/ide_CLKF.UIM | 5040 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ide/ide_CLKF.Q | ide/ide_CLKF | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_1_IBUF | 4929 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_1_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_6_IBUF | 4930 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_6_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_3_IBUF | 4931 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_2_IBUF | 4932 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<2> | 4939 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<2>.Q | AUTO_CONFIG_DONE<2> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | autoconfig | 4957 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.Q | autoconfig | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<0> | 4937 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<0>.Q | AUTO_CONFIG_DONE<0> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<1> | 4938 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<1>.Q | AUTO_CONFIG_DONE<1> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | IDE_W_S.EXP | 5355 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_W_S.EXP | IDE_W_S | 4 | 0 | MC_EXPORT
+OUTPUT_NODE_TYPE | 0 | 0 | MC_Q
+NODE | ROM_OE_S | 4974 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ROM_OE_S.Q | ROM_OE_S | 0 | 0 | MC_Q
+OUTPUT_NODE_TYPE | 4 | 0 | MC_EXPORT
+NODE | ROM_OE_S.EXP | 5356 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ROM_OE_S.EXP | ROM_OE_S | 4 | 0 | MC_EXPORT
+
+SIGNAL_INSTANCE | ROM_OE_S.SI | ROM_OE_S | 0 | 15 | 4
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_5_IBUF | 4927 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_4_IBUF | 4928 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_4_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | ide/ide_CLKF.UIM | 5040 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ide/ide_CLKF.Q | ide/ide_CLKF | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_1_IBUF | 4929 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_1_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_6_IBUF | 4930 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_6_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_3_IBUF | 4931 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_2_IBUF | 4932 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<2> | 4939 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<2>.Q | AUTO_CONFIG_DONE<2> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | autoconfig | 4957 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.Q | autoconfig | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<0> | 4937 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<0>.Q | AUTO_CONFIG_DONE<0> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<1> | 4938 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<1>.Q | AUTO_CONFIG_DONE<1> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | IDE_W_S.EXP | 5355 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_W_S.EXP | IDE_W_S | 4 | 0 | MC_EXPORT
+OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
+SIGNAL | NODE | ROM_OE_S.D1 | 5202 | ? | 0 | 4096 | ROM_OE_S | NULL | NULL | ROM_OE_S.SI | 1 | 9 | MC_SI_D1
+SPPTERM | 0 | IV_ZERO
+OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
+SIGNAL | NODE | ROM_OE_S.D2 | 5203 | ? | 0 | 4096 | ROM_OE_S | NULL | NULL | ROM_OE_S.SI | 2 | 9 | MC_SI_D2
+SPPTERM | 1 | IV_TRUE | IDE_W_S.EXP
+OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF
+SIGNAL | NODE | ROM_OE_S.CLKF | 5204 | ? | 0 | 4096 | ROM_OE_S | NULL | NULL | ROM_OE_S.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_TRUE | ide/ide_CLKF.UIM
+OUTPUT_NODE_TYPE | 7 | 9 | MC_SI_EXPORT
+SIGNAL | NODE | ROM_OE_S.EXP | 5351 | ? | 0 | 0 | ROM_OE_S | NULL | NULL | ROM_OE_S.SI | 7 | 9 | MC_SI_EXPORT
+SPPTERM | 11 | IV_TRUE | RESET_IBUF | IV_TRUE | RW_IBUF | IV_FALSE | AS_IBUF | IV_TRUE | A_5_IBUF | IV_FALSE | A_4_IBUF | IV_TRUE | A_1_IBUF | IV_FALSE | A_6_IBUF | IV_FALSE | A_3_IBUF | IV_TRUE | A_2_IBUF | IV_FALSE | AUTO_CONFIG_DONE<2> | IV_TRUE | autoconfig
+SPPTERM | 11 | IV_TRUE | RESET_IBUF | IV_TRUE | RW_IBUF | IV_FALSE | AS_IBUF | IV_TRUE | A_5_IBUF | IV_FALSE | A_4_IBUF | IV_FALSE | A_6_IBUF | IV_FALSE | A_3_IBUF | IV_TRUE | A_2_IBUF | IV_TRUE | AUTO_CONFIG_DONE<0> | IV_FALSE | AUTO_CONFIG_DONE<1> | IV_TRUE | autoconfig
+SPPTERM | 11 | IV_TRUE | RESET_IBUF | IV_TRUE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_TRUE | A_4_IBUF | IV_TRUE | A_1_IBUF | IV_FALSE | A_6_IBUF | IV_TRUE | A_3_IBUF | IV_TRUE | AUTO_CONFIG_DONE<0> | IV_FALSE | AUTO_CONFIG_DONE<1> | IV_TRUE | autoconfig
+SPPTERM | 11 | IV_TRUE | RESET_IBUF | IV_TRUE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_FALSE | A_1_IBUF | IV_FALSE | A_6_IBUF | IV_FALSE | A_3_IBUF | IV_TRUE | A_2_IBUF | IV_TRUE | AUTO_CONFIG_DONE<1> | IV_FALSE | AUTO_CONFIG_DONE<2> | IV_TRUE | autoconfig
+
+SRFF_INSTANCE | ROM_OE_S.REG | ROM_OE_S | 0 | 2 | 1
+INPUT_NODE_TYPE | 0 | 8 | SRFF_D
+NODE | ROM_OE_S.D | 5201 | ? | 0 | 0 | ROM_OE_S | NULL | NULL | ROM_OE_S.XOR | 0 | 7 | ALU_F
+INPUT_NODE_TYPE | 1 | 8 | SRFF_C
+SIGNAL | NODE | ROM_OE_S.CLKF | 5204 | ? | 0 | 4096 | ROM_OE_S | NULL | NULL | ROM_OE_S.SI | 3 | 9 | MC_SI_CLKF
+SPPTERM | 1 | IV_TRUE | ide/ide_CLKF.UIM
+OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
+NODE | ROM_OE_S.Q | 5205 | ? | 0 | 0 | ROM_OE_S | NULL | NULL | ROM_OE_S.REG | 0 | 8 | SRFF_Q
+
+MACROCELL_INSTANCE | FbkInv+PinTrst+Merge+OptxMapped | N1 | LAN_IDE_CP_COPY_0_COPY_0 | 2155923456 | 2 | 2
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTOCONFIG_IN_PROGRESS | 4959 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTOCONFIG_IN_PROGRESS.Q | AUTOCONFIG_IN_PROGRESS | 1 | 0 | MC_UIM
+OUTPUT_NODE_TYPE | 0 | 0 | MC_Q
+NODE | N1$Q | 4975 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | N1.Q | N1 | 0 | 0 | MC_Q
+OUTPUT_NODE_TYPE | 2 | 0 | MC_OE
+NODE | N1$OE | 4976 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | N1.BUFOE.OUT | N1 | 2 | 0 | MC_OE
+
+SIGNAL_INSTANCE | N1.SI | N1 | 0 | 2 | 3
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTOCONFIG_IN_PROGRESS | 4959 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTOCONFIG_IN_PROGRESS.Q | AUTOCONFIG_IN_PROGRESS | 1 | 0 | MC_UIM
+OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
+SIGNAL | NODE | N1.D1 | 5207 | ? | 0 | 4096 | N1 | NULL | NULL | N1.SI | 1 | 9 | MC_SI_D1
+SPPTERM | 0 | IV_ZERO
+OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
+SIGNAL | NODE | N1.D2 | 5208 | ? | 0 | 4096 | N1 | NULL | NULL | N1.SI | 2 | 9 | MC_SI_D2
+SPPTERM | 0 | IV_DC
+OUTPUT_NODE_TYPE | 4 | 9 | MC_SI_TRST
+SIGNAL | NODE | N1.TRST | 5210 | ? | 0 | 4096 | N1 | NULL | NULL | N1.SI | 4 | 9 | MC_SI_TRST
+SPPTERM | 2 | IV_TRUE | RW_IBUF | IV_TRUE | AUTOCONFIG_IN_PROGRESS
+
+SRFF_INSTANCE | N1.REG | N1 | 0 | 1 | 1
+INPUT_NODE_TYPE | 0 | 8 | SRFF_D
+NODE | N1.D | 5206 | ? | 0 | 0 | N1 | NULL | NULL | N1.XOR | 0 | 7 | ALU_F
+OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
+NODE | N1.Q | 5211 | ? | 0 | 0 | N1 | NULL | NULL | N1.REG | 0 | 8 | SRFF_Q
+
+BUF_INSTANCE | N1.BUFOE | N1 | 0 | 1 | 1
+INPUT_NODE_TYPE | 0 | 10 | CTOR_UNKNOWN
+SIGNAL | NODE | N1.TRST | 5210 | ? | 0 | 4096 | N1 | NULL | NULL | N1.SI | 4 | 9 | MC_SI_TRST
+SPPTERM | 2 | IV_TRUE | RW_IBUF | IV_TRUE | AUTOCONFIG_IN_PROGRESS
+OUTPUT_NODE_TYPE | 0 | 10 | BUF_OUT
+NODE | N1.BUFOE.OUT | 5209 | ? | 0 | 0 | N1 | NULL | NULL | N1.BUFOE | 0 | 10 | BUF_OUT
+
+MACROCELL_INSTANCE | PinTrst+OptxMapped | N1$BUF0 | LAN_IDE_CP_COPY_0_COPY_0 | 2155888640 | 2 | 2
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTOCONFIG_IN_PROGRESS | 4959 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTOCONFIG_IN_PROGRESS.Q | AUTOCONFIG_IN_PROGRESS | 1 | 0 | MC_UIM
+OUTPUT_NODE_TYPE | 0 | 0 | MC_Q
+NODE | N1$BUF0 | 4977 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | N1$BUF0.Q | N1$BUF0 | 0 | 0 | MC_Q
+OUTPUT_NODE_TYPE | 2 | 0 | MC_OE
+NODE | N1$BUF0$OE | 4978 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | N1$BUF0.BUFOE.OUT | N1$BUF0 | 2 | 0 | MC_OE
+
+SIGNAL_INSTANCE | N1$BUF0.SI | N1$BUF0 | 0 | 2 | 3
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTOCONFIG_IN_PROGRESS | 4959 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTOCONFIG_IN_PROGRESS.Q | AUTOCONFIG_IN_PROGRESS | 1 | 0 | MC_UIM
+OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
+SIGNAL | NODE | N1$BUF0.D1 | 5213 | ? | 0 | 4096 | N1$BUF0 | NULL | NULL | N1$BUF0.SI | 1 | 9 | MC_SI_D1
+SPPTERM | 0 | IV_ZERO
+OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
+SIGNAL | NODE | N1$BUF0.D2 | 5214 | ? | 0 | 6144 | N1$BUF0 | NULL | NULL | N1$BUF0.SI | 2 | 9 | MC_SI_D2
+SPPTERM | 0 | IV_DC
+OUTPUT_NODE_TYPE | 4 | 9 | MC_SI_TRST
+SIGNAL | NODE | N1$BUF0.TRST | 5216 | ? | 0 | 4096 | N1$BUF0 | NULL | NULL | N1$BUF0.SI | 4 | 9 | MC_SI_TRST
+SPPTERM | 2 | IV_TRUE | RW_IBUF | IV_TRUE | AUTOCONFIG_IN_PROGRESS
+
+SRFF_INSTANCE | N1$BUF0.REG | N1$BUF0 | 0 | 1 | 1
+INPUT_NODE_TYPE | 0 | 8 | SRFF_D
+NODE | N1$BUF0.D | 5212 | ? | 0 | 0 | N1$BUF0 | NULL | NULL | N1$BUF0.XOR | 0 | 7 | ALU_F
+OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
+NODE | N1$BUF0.Q | 5217 | ? | 0 | 0 | N1$BUF0 | NULL | NULL | N1$BUF0.REG | 0 | 8 | SRFF_Q
+
+BUF_INSTANCE | N1$BUF0.BUFOE | N1$BUF0 | 0 | 1 | 1
+INPUT_NODE_TYPE | 0 | 10 | CTOR_UNKNOWN
+SIGNAL | NODE | N1$BUF0.TRST | 5216 | ? | 0 | 4096 | N1$BUF0 | NULL | NULL | N1$BUF0.SI | 4 | 9 | MC_SI_TRST
+SPPTERM | 2 | IV_TRUE | RW_IBUF | IV_TRUE | AUTOCONFIG_IN_PROGRESS
+OUTPUT_NODE_TYPE | 0 | 10 | BUF_OUT
+NODE | N1$BUF0.BUFOE.OUT | 5215 | ? | 0 | 0 | N1$BUF0 | NULL | NULL | N1$BUF0.BUFOE | 0 | 10 | BUF_OUT
+
+MACROCELL_INSTANCE | PinTrst+OptxMapped | N1$BUF1 | LAN_IDE_CP_COPY_0_COPY_0 | 2155888640 | 3 | 3
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTOCONFIG_IN_PROGRESS | 4959 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTOCONFIG_IN_PROGRESS.Q | AUTOCONFIG_IN_PROGRESS | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_13_IBUF | 5007 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_13_IBUF | 0 | 5 | II_IMUX
+OUTPUT_NODE_TYPE | 0 | 0 | MC_Q
+NODE | N1$BUF1 | 4979 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | N1$BUF1.Q | N1$BUF1 | 0 | 0 | MC_Q
+OUTPUT_NODE_TYPE | 4 | 0 | MC_EXPORT
+NODE | N1$BUF1.EXP | 5354 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | N1$BUF1.EXP | N1$BUF1 | 4 | 0 | MC_EXPORT
+OUTPUT_NODE_TYPE | 2 | 0 | MC_OE
+NODE | N1$BUF1$OE | 4980 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | N1$BUF1.BUFOE.OUT | N1$BUF1 | 2 | 0 | MC_OE
+
+SIGNAL_INSTANCE | N1$BUF1.SI | N1$BUF1 | 0 | 3 | 4
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTOCONFIG_IN_PROGRESS | 4959 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTOCONFIG_IN_PROGRESS.Q | AUTOCONFIG_IN_PROGRESS | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_13_IBUF | 5007 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_13_IBUF | 0 | 5 | II_IMUX
+OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
+SIGNAL | NODE | N1$BUF1.D1 | 5219 | ? | 0 | 4096 | N1$BUF1 | NULL | NULL | N1$BUF1.SI | 1 | 9 | MC_SI_D1
+SPPTERM | 0 | IV_ZERO
+OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
+SIGNAL | NODE | N1$BUF1.D2 | 5220 | ? | 0 | 6144 | N1$BUF1 | NULL | NULL | N1$BUF1.SI | 2 | 9 | MC_SI_D2
+SPPTERM | 0 | IV_DC
+OUTPUT_NODE_TYPE | 4 | 9 | MC_SI_TRST
+SIGNAL | NODE | N1$BUF1.TRST | 5222 | ? | 0 | 4096 | N1$BUF1 | NULL | NULL | N1$BUF1.SI | 4 | 9 | MC_SI_TRST
+SPPTERM | 2 | IV_TRUE | RW_IBUF | IV_TRUE | AUTOCONFIG_IN_PROGRESS
+OUTPUT_NODE_TYPE | 7 | 9 | MC_SI_EXPORT
+SIGNAL | NODE | N1$BUF1.EXP | 5349 | ? | 0 | 0 | N1$BUF1 | NULL | NULL | N1$BUF1.SI | 7 | 9 | MC_SI_EXPORT
+SPPTERM | 1 | IV_FALSE | A_13_IBUF
+
+SRFF_INSTANCE | N1$BUF1.REG | N1$BUF1 | 0 | 1 | 1
+INPUT_NODE_TYPE | 0 | 8 | SRFF_D
+NODE | N1$BUF1.D | 5218 | ? | 0 | 0 | N1$BUF1 | NULL | NULL | N1$BUF1.XOR | 0 | 7 | ALU_F
+OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
+NODE | N1$BUF1.Q | 5223 | ? | 0 | 0 | N1$BUF1 | NULL | NULL | N1$BUF1.REG | 0 | 8 | SRFF_Q
+
+BUF_INSTANCE | N1$BUF1.BUFOE | N1$BUF1 | 0 | 1 | 1
+INPUT_NODE_TYPE | 0 | 10 | CTOR_UNKNOWN
+SIGNAL | NODE | N1$BUF1.TRST | 5222 | ? | 0 | 4096 | N1$BUF1 | NULL | NULL | N1$BUF1.SI | 4 | 9 | MC_SI_TRST
+SPPTERM | 2 | IV_TRUE | RW_IBUF | IV_TRUE | AUTOCONFIG_IN_PROGRESS
+OUTPUT_NODE_TYPE | 0 | 10 | BUF_OUT
+NODE | N1$BUF1.BUFOE.OUT | 5221 | ? | 0 | 0 | N1$BUF1 | NULL | NULL | N1$BUF1.BUFOE | 0 | 10 | BUF_OUT
+
+MACROCELL_INSTANCE | PinTrst+OptxMapped | N1$BUF10 | LAN_IDE_CP_COPY_0_COPY_0 | 2155888640 | 2 | 2
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTOCONFIG_IN_PROGRESS | 4959 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTOCONFIG_IN_PROGRESS.Q | AUTOCONFIG_IN_PROGRESS | 1 | 0 | MC_UIM
+OUTPUT_NODE_TYPE | 0 | 0 | MC_Q
+NODE | N1$BUF10 | 4981 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | N1$BUF10.Q | N1$BUF10 | 0 | 0 | MC_Q
+OUTPUT_NODE_TYPE | 2 | 0 | MC_OE
+NODE | N1$BUF10$OE | 4982 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | N1$BUF10.BUFOE.OUT | N1$BUF10 | 2 | 0 | MC_OE
+
+SIGNAL_INSTANCE | N1$BUF10.SI | N1$BUF10 | 0 | 2 | 3
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTOCONFIG_IN_PROGRESS | 4959 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTOCONFIG_IN_PROGRESS.Q | AUTOCONFIG_IN_PROGRESS | 1 | 0 | MC_UIM
+OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
+SIGNAL | NODE | N1$BUF10.D1 | 5225 | ? | 0 | 4096 | N1$BUF10 | NULL | NULL | N1$BUF10.SI | 1 | 9 | MC_SI_D1
+SPPTERM | 0 | IV_ZERO
+OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
+SIGNAL | NODE | N1$BUF10.D2 | 5226 | ? | 0 | 6144 | N1$BUF10 | NULL | NULL | N1$BUF10.SI | 2 | 9 | MC_SI_D2
+SPPTERM | 0 | IV_DC
+OUTPUT_NODE_TYPE | 4 | 9 | MC_SI_TRST
+SIGNAL | NODE | N1$BUF10.TRST | 5228 | ? | 0 | 4096 | N1$BUF10 | NULL | NULL | N1$BUF10.SI | 4 | 9 | MC_SI_TRST
+SPPTERM | 2 | IV_TRUE | RW_IBUF | IV_TRUE | AUTOCONFIG_IN_PROGRESS
+
+SRFF_INSTANCE | N1$BUF10.REG | N1$BUF10 | 0 | 1 | 1
+INPUT_NODE_TYPE | 0 | 8 | SRFF_D
+NODE | N1$BUF10.D | 5224 | ? | 0 | 0 | N1$BUF10 | NULL | NULL | N1$BUF10.XOR | 0 | 7 | ALU_F
+OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
+NODE | N1$BUF10.Q | 5229 | ? | 0 | 0 | N1$BUF10 | NULL | NULL | N1$BUF10.REG | 0 | 8 | SRFF_Q
+
+BUF_INSTANCE | N1$BUF10.BUFOE | N1$BUF10 | 0 | 1 | 1
+INPUT_NODE_TYPE | 0 | 10 | CTOR_UNKNOWN
+SIGNAL | NODE | N1$BUF10.TRST | 5228 | ? | 0 | 4096 | N1$BUF10 | NULL | NULL | N1$BUF10.SI | 4 | 9 | MC_SI_TRST
+SPPTERM | 2 | IV_TRUE | RW_IBUF | IV_TRUE | AUTOCONFIG_IN_PROGRESS
+OUTPUT_NODE_TYPE | 0 | 10 | BUF_OUT
+NODE | N1$BUF10.BUFOE.OUT | 5227 | ? | 0 | 0 | N1$BUF10 | NULL | NULL | N1$BUF10.BUFOE | 0 | 10 | BUF_OUT
+
+MACROCELL_INSTANCE | PinTrst+OptxMapped | N1$BUF2 | LAN_IDE_CP_COPY_0_COPY_0 | 2155888640 | 14 | 3
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTOCONFIG_IN_PROGRESS | 4959 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTOCONFIG_IN_PROGRESS.Q | AUTOCONFIG_IN_PROGRESS | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_5_IBUF | 4927 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_4_IBUF | 4928 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_4_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_3_IBUF | 4931 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_2_IBUF | 4932 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<2> | 4939 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<2>.Q | AUTO_CONFIG_DONE<2> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | autoconfig | 4957 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.Q | autoconfig | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_1_IBUF | 4929 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_1_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_6_IBUF | 4930 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_6_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<1> | 4938 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<1>.Q | AUTO_CONFIG_DONE<1> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<0> | 4937 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<0>.Q | AUTO_CONFIG_DONE<0> | 1 | 0 | MC_UIM
+OUTPUT_NODE_TYPE | 0 | 0 | MC_Q
+NODE | N1$BUF2 | 4983 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | N1$BUF2.Q | N1$BUF2 | 0 | 0 | MC_Q
+OUTPUT_NODE_TYPE | 4 | 0 | MC_EXPORT
+NODE | N1$BUF2.EXP | 5372 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | N1$BUF2.EXP | N1$BUF2 | 4 | 0 | MC_EXPORT
+OUTPUT_NODE_TYPE | 2 | 0 | MC_OE
+NODE | N1$BUF2$OE | 4984 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | N1$BUF2.BUFOE.OUT | N1$BUF2 | 2 | 0 | MC_OE
+
+SIGNAL_INSTANCE | N1$BUF2.SI | N1$BUF2 | 0 | 14 | 4
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTOCONFIG_IN_PROGRESS | 4959 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTOCONFIG_IN_PROGRESS.Q | AUTOCONFIG_IN_PROGRESS | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_5_IBUF | 4927 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_4_IBUF | 4928 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_4_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_3_IBUF | 4931 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_2_IBUF | 4932 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<2> | 4939 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<2>.Q | AUTO_CONFIG_DONE<2> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | autoconfig | 4957 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.Q | autoconfig | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_1_IBUF | 4929 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_1_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_6_IBUF | 4930 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_6_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<1> | 4938 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<1>.Q | AUTO_CONFIG_DONE<1> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<0> | 4937 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<0>.Q | AUTO_CONFIG_DONE<0> | 1 | 0 | MC_UIM
+OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
+SIGNAL | NODE | N1$BUF2.D1 | 5231 | ? | 0 | 4096 | N1$BUF2 | NULL | NULL | N1$BUF2.SI | 1 | 9 | MC_SI_D1
+SPPTERM | 0 | IV_ZERO
+OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
+SIGNAL | NODE | N1$BUF2.D2 | 5232 | ? | 0 | 6144 | N1$BUF2 | NULL | NULL | N1$BUF2.SI | 2 | 9 | MC_SI_D2
+SPPTERM | 0 | IV_DC
+OUTPUT_NODE_TYPE | 4 | 9 | MC_SI_TRST
+SIGNAL | NODE | N1$BUF2.TRST | 5234 | ? | 0 | 4096 | N1$BUF2 | NULL | NULL | N1$BUF2.SI | 4 | 9 | MC_SI_TRST
+SPPTERM | 2 | IV_TRUE | RW_IBUF | IV_TRUE | AUTOCONFIG_IN_PROGRESS
+OUTPUT_NODE_TYPE | 7 | 9 | MC_SI_EXPORT
+SIGNAL | NODE | N1$BUF2.EXP | 5364 | ? | 0 | 0 | N1$BUF2 | NULL | NULL | N1$BUF2.SI | 7 | 9 | MC_SI_EXPORT
+SPPTERM | 9 | IV_TRUE | RESET_IBUF | IV_TRUE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_FALSE | A_4_IBUF | IV_FALSE | A_3_IBUF | IV_FALSE | A_2_IBUF | IV_FALSE | AUTO_CONFIG_DONE<2> | IV_TRUE | autoconfig
+SPPTERM | 10 | IV_TRUE | RESET_IBUF | IV_TRUE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_FALSE | A_4_IBUF | IV_TRUE | A_1_IBUF | IV_FALSE | A_6_IBUF | IV_FALSE | A_3_IBUF | IV_FALSE | AUTO_CONFIG_DONE<1> | IV_TRUE | autoconfig
+SPPTERM | 10 | IV_TRUE | RESET_IBUF | IV_TRUE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_TRUE | A_1_IBUF | IV_FALSE | A_6_IBUF | IV_FALSE | A_3_IBUF | IV_FALSE | A_2_IBUF | IV_FALSE | AUTO_CONFIG_DONE<0> | IV_TRUE | autoconfig
+SPPTERM | 11 | IV_TRUE | RESET_IBUF | IV_TRUE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_TRUE | A_4_IBUF | IV_FALSE | A_1_IBUF | IV_FALSE | A_6_IBUF | IV_TRUE | A_2_IBUF | IV_TRUE | AUTO_CONFIG_DONE<0> | IV_FALSE | AUTO_CONFIG_DONE<1> | IV_TRUE | autoconfig
+
+SRFF_INSTANCE | N1$BUF2.REG | N1$BUF2 | 0 | 1 | 1
+INPUT_NODE_TYPE | 0 | 8 | SRFF_D
+NODE | N1$BUF2.D | 5230 | ? | 0 | 0 | N1$BUF2 | NULL | NULL | N1$BUF2.XOR | 0 | 7 | ALU_F
+OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
+NODE | N1$BUF2.Q | 5235 | ? | 0 | 0 | N1$BUF2 | NULL | NULL | N1$BUF2.REG | 0 | 8 | SRFF_Q
+
+BUF_INSTANCE | N1$BUF2.BUFOE | N1$BUF2 | 0 | 1 | 1
+INPUT_NODE_TYPE | 0 | 10 | CTOR_UNKNOWN
+SIGNAL | NODE | N1$BUF2.TRST | 5234 | ? | 0 | 4096 | N1$BUF2 | NULL | NULL | N1$BUF2.SI | 4 | 9 | MC_SI_TRST
+SPPTERM | 2 | IV_TRUE | RW_IBUF | IV_TRUE | AUTOCONFIG_IN_PROGRESS
+OUTPUT_NODE_TYPE | 0 | 10 | BUF_OUT
+NODE | N1$BUF2.BUFOE.OUT | 5233 | ? | 0 | 0 | N1$BUF2 | NULL | NULL | N1$BUF2.BUFOE | 0 | 10 | BUF_OUT
+
+MACROCELL_INSTANCE | PinTrst+OptxMapped | N1$BUF3 | LAN_IDE_CP_COPY_0_COPY_0 | 2155888640 | 2 | 2
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTOCONFIG_IN_PROGRESS | 4959 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTOCONFIG_IN_PROGRESS.Q | AUTOCONFIG_IN_PROGRESS | 1 | 0 | MC_UIM
+OUTPUT_NODE_TYPE | 0 | 0 | MC_Q
+NODE | N1$BUF3 | 4985 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | N1$BUF3.Q | N1$BUF3 | 0 | 0 | MC_Q
+OUTPUT_NODE_TYPE | 2 | 0 | MC_OE
+NODE | N1$BUF3$OE | 4986 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | N1$BUF3.BUFOE.OUT | N1$BUF3 | 2 | 0 | MC_OE
+
+SIGNAL_INSTANCE | N1$BUF3.SI | N1$BUF3 | 0 | 2 | 3
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTOCONFIG_IN_PROGRESS | 4959 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTOCONFIG_IN_PROGRESS.Q | AUTOCONFIG_IN_PROGRESS | 1 | 0 | MC_UIM
+OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
+SIGNAL | NODE | N1$BUF3.D1 | 5237 | ? | 0 | 4096 | N1$BUF3 | NULL | NULL | N1$BUF3.SI | 1 | 9 | MC_SI_D1
+SPPTERM | 0 | IV_ZERO
+OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
+SIGNAL | NODE | N1$BUF3.D2 | 5238 | ? | 0 | 6144 | N1$BUF3 | NULL | NULL | N1$BUF3.SI | 2 | 9 | MC_SI_D2
+SPPTERM | 0 | IV_DC
+OUTPUT_NODE_TYPE | 4 | 9 | MC_SI_TRST
+SIGNAL | NODE | N1$BUF3.TRST | 5240 | ? | 0 | 4096 | N1$BUF3 | NULL | NULL | N1$BUF3.SI | 4 | 9 | MC_SI_TRST
+SPPTERM | 2 | IV_TRUE | RW_IBUF | IV_TRUE | AUTOCONFIG_IN_PROGRESS
+
+SRFF_INSTANCE | N1$BUF3.REG | N1$BUF3 | 0 | 1 | 1
+INPUT_NODE_TYPE | 0 | 8 | SRFF_D
+NODE | N1$BUF3.D | 5236 | ? | 0 | 0 | N1$BUF3 | NULL | NULL | N1$BUF3.XOR | 0 | 7 | ALU_F
+OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
+NODE | N1$BUF3.Q | 5241 | ? | 0 | 0 | N1$BUF3 | NULL | NULL | N1$BUF3.REG | 0 | 8 | SRFF_Q
+
+BUF_INSTANCE | N1$BUF3.BUFOE | N1$BUF3 | 0 | 1 | 1
+INPUT_NODE_TYPE | 0 | 10 | CTOR_UNKNOWN
+SIGNAL | NODE | N1$BUF3.TRST | 5240 | ? | 0 | 4096 | N1$BUF3 | NULL | NULL | N1$BUF3.SI | 4 | 9 | MC_SI_TRST
+SPPTERM | 2 | IV_TRUE | RW_IBUF | IV_TRUE | AUTOCONFIG_IN_PROGRESS
+OUTPUT_NODE_TYPE | 0 | 10 | BUF_OUT
+NODE | N1$BUF3.BUFOE.OUT | 5239 | ? | 0 | 0 | N1$BUF3 | NULL | NULL | N1$BUF3.BUFOE | 0 | 10 | BUF_OUT
+
+MACROCELL_INSTANCE | PinTrst+OptxMapped | N1$BUF4 | LAN_IDE_CP_COPY_0_COPY_0 | 2155888640 | 2 | 2
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTOCONFIG_IN_PROGRESS | 4959 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTOCONFIG_IN_PROGRESS.Q | AUTOCONFIG_IN_PROGRESS | 1 | 0 | MC_UIM
+OUTPUT_NODE_TYPE | 0 | 0 | MC_Q
+NODE | N1$BUF4 | 4987 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | N1$BUF4.Q | N1$BUF4 | 0 | 0 | MC_Q
+OUTPUT_NODE_TYPE | 2 | 0 | MC_OE
+NODE | N1$BUF4$OE | 4988 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | N1$BUF4.BUFOE.OUT | N1$BUF4 | 2 | 0 | MC_OE
+
+SIGNAL_INSTANCE | N1$BUF4.SI | N1$BUF4 | 0 | 2 | 3
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTOCONFIG_IN_PROGRESS | 4959 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTOCONFIG_IN_PROGRESS.Q | AUTOCONFIG_IN_PROGRESS | 1 | 0 | MC_UIM
+OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
+SIGNAL | NODE | N1$BUF4.D1 | 5243 | ? | 0 | 4096 | N1$BUF4 | NULL | NULL | N1$BUF4.SI | 1 | 9 | MC_SI_D1
+SPPTERM | 0 | IV_ZERO
+OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
+SIGNAL | NODE | N1$BUF4.D2 | 5244 | ? | 0 | 6144 | N1$BUF4 | NULL | NULL | N1$BUF4.SI | 2 | 9 | MC_SI_D2
+SPPTERM | 0 | IV_DC
+OUTPUT_NODE_TYPE | 4 | 9 | MC_SI_TRST
+SIGNAL | NODE | N1$BUF4.TRST | 5246 | ? | 0 | 4096 | N1$BUF4 | NULL | NULL | N1$BUF4.SI | 4 | 9 | MC_SI_TRST
+SPPTERM | 2 | IV_TRUE | RW_IBUF | IV_TRUE | AUTOCONFIG_IN_PROGRESS
+
+SRFF_INSTANCE | N1$BUF4.REG | N1$BUF4 | 0 | 1 | 1
+INPUT_NODE_TYPE | 0 | 8 | SRFF_D
+NODE | N1$BUF4.D | 5242 | ? | 0 | 0 | N1$BUF4 | NULL | NULL | N1$BUF4.XOR | 0 | 7 | ALU_F
+OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
+NODE | N1$BUF4.Q | 5247 | ? | 0 | 0 | N1$BUF4 | NULL | NULL | N1$BUF4.REG | 0 | 8 | SRFF_Q
+
+BUF_INSTANCE | N1$BUF4.BUFOE | N1$BUF4 | 0 | 1 | 1
+INPUT_NODE_TYPE | 0 | 10 | CTOR_UNKNOWN
+SIGNAL | NODE | N1$BUF4.TRST | 5246 | ? | 0 | 4096 | N1$BUF4 | NULL | NULL | N1$BUF4.SI | 4 | 9 | MC_SI_TRST
+SPPTERM | 2 | IV_TRUE | RW_IBUF | IV_TRUE | AUTOCONFIG_IN_PROGRESS
+OUTPUT_NODE_TYPE | 0 | 10 | BUF_OUT
+NODE | N1$BUF4.BUFOE.OUT | 5245 | ? | 0 | 0 | N1$BUF4 | NULL | NULL | N1$BUF4.BUFOE | 0 | 10 | BUF_OUT
+
+MACROCELL_INSTANCE | PinTrst+OptxMapped | N1$BUF5 | LAN_IDE_CP_COPY_0_COPY_0 | 2155888640 | 2 | 2
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTOCONFIG_IN_PROGRESS | 4959 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTOCONFIG_IN_PROGRESS.Q | AUTOCONFIG_IN_PROGRESS | 1 | 0 | MC_UIM
+OUTPUT_NODE_TYPE | 0 | 0 | MC_Q
+NODE | N1$BUF5 | 4989 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | N1$BUF5.Q | N1$BUF5 | 0 | 0 | MC_Q
+OUTPUT_NODE_TYPE | 2 | 0 | MC_OE
+NODE | N1$BUF5$OE | 4990 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | N1$BUF5.BUFOE.OUT | N1$BUF5 | 2 | 0 | MC_OE
+
+SIGNAL_INSTANCE | N1$BUF5.SI | N1$BUF5 | 0 | 2 | 3
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTOCONFIG_IN_PROGRESS | 4959 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTOCONFIG_IN_PROGRESS.Q | AUTOCONFIG_IN_PROGRESS | 1 | 0 | MC_UIM
+OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
+SIGNAL | NODE | N1$BUF5.D1 | 5249 | ? | 0 | 4096 | N1$BUF5 | NULL | NULL | N1$BUF5.SI | 1 | 9 | MC_SI_D1
+SPPTERM | 0 | IV_ZERO
+OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
+SIGNAL | NODE | N1$BUF5.D2 | 5250 | ? | 0 | 6144 | N1$BUF5 | NULL | NULL | N1$BUF5.SI | 2 | 9 | MC_SI_D2
+SPPTERM | 0 | IV_DC
+OUTPUT_NODE_TYPE | 4 | 9 | MC_SI_TRST
+SIGNAL | NODE | N1$BUF5.TRST | 5252 | ? | 0 | 4096 | N1$BUF5 | NULL | NULL | N1$BUF5.SI | 4 | 9 | MC_SI_TRST
+SPPTERM | 2 | IV_TRUE | RW_IBUF | IV_TRUE | AUTOCONFIG_IN_PROGRESS
+
+SRFF_INSTANCE | N1$BUF5.REG | N1$BUF5 | 0 | 1 | 1
+INPUT_NODE_TYPE | 0 | 8 | SRFF_D
+NODE | N1$BUF5.D | 5248 | ? | 0 | 0 | N1$BUF5 | NULL | NULL | N1$BUF5.XOR | 0 | 7 | ALU_F
+OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
+NODE | N1$BUF5.Q | 5253 | ? | 0 | 0 | N1$BUF5 | NULL | NULL | N1$BUF5.REG | 0 | 8 | SRFF_Q
+
+BUF_INSTANCE | N1$BUF5.BUFOE | N1$BUF5 | 0 | 1 | 1
+INPUT_NODE_TYPE | 0 | 10 | CTOR_UNKNOWN
+SIGNAL | NODE | N1$BUF5.TRST | 5252 | ? | 0 | 4096 | N1$BUF5 | NULL | NULL | N1$BUF5.SI | 4 | 9 | MC_SI_TRST
+SPPTERM | 2 | IV_TRUE | RW_IBUF | IV_TRUE | AUTOCONFIG_IN_PROGRESS
+OUTPUT_NODE_TYPE | 0 | 10 | BUF_OUT
+NODE | N1$BUF5.BUFOE.OUT | 5251 | ? | 0 | 0 | N1$BUF5 | NULL | NULL | N1$BUF5.BUFOE | 0 | 10 | BUF_OUT
+
+MACROCELL_INSTANCE | PinTrst+OptxMapped | N1$BUF6 | LAN_IDE_CP_COPY_0_COPY_0 | 2155888640 | 2 | 2
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTOCONFIG_IN_PROGRESS | 4959 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTOCONFIG_IN_PROGRESS.Q | AUTOCONFIG_IN_PROGRESS | 1 | 0 | MC_UIM
+OUTPUT_NODE_TYPE | 0 | 0 | MC_Q
+NODE | N1$BUF6 | 4991 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | N1$BUF6.Q | N1$BUF6 | 0 | 0 | MC_Q
+OUTPUT_NODE_TYPE | 2 | 0 | MC_OE
+NODE | N1$BUF6$OE | 4992 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | N1$BUF6.BUFOE.OUT | N1$BUF6 | 2 | 0 | MC_OE
+
+SIGNAL_INSTANCE | N1$BUF6.SI | N1$BUF6 | 0 | 2 | 3
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTOCONFIG_IN_PROGRESS | 4959 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTOCONFIG_IN_PROGRESS.Q | AUTOCONFIG_IN_PROGRESS | 1 | 0 | MC_UIM
+OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
+SIGNAL | NODE | N1$BUF6.D1 | 5255 | ? | 0 | 4096 | N1$BUF6 | NULL | NULL | N1$BUF6.SI | 1 | 9 | MC_SI_D1
+SPPTERM | 0 | IV_ZERO
+OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
+SIGNAL | NODE | N1$BUF6.D2 | 5256 | ? | 0 | 6144 | N1$BUF6 | NULL | NULL | N1$BUF6.SI | 2 | 9 | MC_SI_D2
+SPPTERM | 0 | IV_DC
+OUTPUT_NODE_TYPE | 4 | 9 | MC_SI_TRST
+SIGNAL | NODE | N1$BUF6.TRST | 5258 | ? | 0 | 4096 | N1$BUF6 | NULL | NULL | N1$BUF6.SI | 4 | 9 | MC_SI_TRST
+SPPTERM | 2 | IV_TRUE | RW_IBUF | IV_TRUE | AUTOCONFIG_IN_PROGRESS
+
+SRFF_INSTANCE | N1$BUF6.REG | N1$BUF6 | 0 | 1 | 1
+INPUT_NODE_TYPE | 0 | 8 | SRFF_D
+NODE | N1$BUF6.D | 5254 | ? | 0 | 0 | N1$BUF6 | NULL | NULL | N1$BUF6.XOR | 0 | 7 | ALU_F
+OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
+NODE | N1$BUF6.Q | 5259 | ? | 0 | 0 | N1$BUF6 | NULL | NULL | N1$BUF6.REG | 0 | 8 | SRFF_Q
+
+BUF_INSTANCE | N1$BUF6.BUFOE | N1$BUF6 | 0 | 1 | 1
+INPUT_NODE_TYPE | 0 | 10 | CTOR_UNKNOWN
+SIGNAL | NODE | N1$BUF6.TRST | 5258 | ? | 0 | 4096 | N1$BUF6 | NULL | NULL | N1$BUF6.SI | 4 | 9 | MC_SI_TRST
+SPPTERM | 2 | IV_TRUE | RW_IBUF | IV_TRUE | AUTOCONFIG_IN_PROGRESS
+OUTPUT_NODE_TYPE | 0 | 10 | BUF_OUT
+NODE | N1$BUF6.BUFOE.OUT | 5257 | ? | 0 | 0 | N1$BUF6 | NULL | NULL | N1$BUF6.BUFOE | 0 | 10 | BUF_OUT
+
+MACROCELL_INSTANCE | PinTrst+OptxMapped | N1$BUF7 | LAN_IDE_CP_COPY_0_COPY_0 | 2155888640 | 2 | 2
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTOCONFIG_IN_PROGRESS | 4959 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTOCONFIG_IN_PROGRESS.Q | AUTOCONFIG_IN_PROGRESS | 1 | 0 | MC_UIM
+OUTPUT_NODE_TYPE | 0 | 0 | MC_Q
+NODE | N1$BUF7 | 4993 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | N1$BUF7.Q | N1$BUF7 | 0 | 0 | MC_Q
+OUTPUT_NODE_TYPE | 2 | 0 | MC_OE
+NODE | N1$BUF7$OE | 4994 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | N1$BUF7.BUFOE.OUT | N1$BUF7 | 2 | 0 | MC_OE
+
+SIGNAL_INSTANCE | N1$BUF7.SI | N1$BUF7 | 0 | 2 | 3
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTOCONFIG_IN_PROGRESS | 4959 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTOCONFIG_IN_PROGRESS.Q | AUTOCONFIG_IN_PROGRESS | 1 | 0 | MC_UIM
+OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
+SIGNAL | NODE | N1$BUF7.D1 | 5261 | ? | 0 | 4096 | N1$BUF7 | NULL | NULL | N1$BUF7.SI | 1 | 9 | MC_SI_D1
+SPPTERM | 0 | IV_ZERO
+OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
+SIGNAL | NODE | N1$BUF7.D2 | 5262 | ? | 0 | 6144 | N1$BUF7 | NULL | NULL | N1$BUF7.SI | 2 | 9 | MC_SI_D2
+SPPTERM | 0 | IV_DC
+OUTPUT_NODE_TYPE | 4 | 9 | MC_SI_TRST
+SIGNAL | NODE | N1$BUF7.TRST | 5264 | ? | 0 | 4096 | N1$BUF7 | NULL | NULL | N1$BUF7.SI | 4 | 9 | MC_SI_TRST
+SPPTERM | 2 | IV_TRUE | RW_IBUF | IV_TRUE | AUTOCONFIG_IN_PROGRESS
+
+SRFF_INSTANCE | N1$BUF7.REG | N1$BUF7 | 0 | 1 | 1
+INPUT_NODE_TYPE | 0 | 8 | SRFF_D
+NODE | N1$BUF7.D | 5260 | ? | 0 | 0 | N1$BUF7 | NULL | NULL | N1$BUF7.XOR | 0 | 7 | ALU_F
+OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
+NODE | N1$BUF7.Q | 5265 | ? | 0 | 0 | N1$BUF7 | NULL | NULL | N1$BUF7.REG | 0 | 8 | SRFF_Q
+
+BUF_INSTANCE | N1$BUF7.BUFOE | N1$BUF7 | 0 | 1 | 1
+INPUT_NODE_TYPE | 0 | 10 | CTOR_UNKNOWN
+SIGNAL | NODE | N1$BUF7.TRST | 5264 | ? | 0 | 4096 | N1$BUF7 | NULL | NULL | N1$BUF7.SI | 4 | 9 | MC_SI_TRST
+SPPTERM | 2 | IV_TRUE | RW_IBUF | IV_TRUE | AUTOCONFIG_IN_PROGRESS
+OUTPUT_NODE_TYPE | 0 | 10 | BUF_OUT
+NODE | N1$BUF7.BUFOE.OUT | 5263 | ? | 0 | 0 | N1$BUF7 | NULL | NULL | N1$BUF7.BUFOE | 0 | 10 | BUF_OUT
+
+MACROCELL_INSTANCE | PinTrst+OptxMapped | N1$BUF8 | LAN_IDE_CP_COPY_0_COPY_0 | 2155888640 | 2 | 2
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTOCONFIG_IN_PROGRESS | 4959 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTOCONFIG_IN_PROGRESS.Q | AUTOCONFIG_IN_PROGRESS | 1 | 0 | MC_UIM
+OUTPUT_NODE_TYPE | 0 | 0 | MC_Q
+NODE | N1$BUF8 | 4995 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | N1$BUF8.Q | N1$BUF8 | 0 | 0 | MC_Q
+OUTPUT_NODE_TYPE | 2 | 0 | MC_OE
+NODE | N1$BUF8$OE | 4996 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | N1$BUF8.BUFOE.OUT | N1$BUF8 | 2 | 0 | MC_OE
+
+SIGNAL_INSTANCE | N1$BUF8.SI | N1$BUF8 | 0 | 2 | 3
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTOCONFIG_IN_PROGRESS | 4959 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTOCONFIG_IN_PROGRESS.Q | AUTOCONFIG_IN_PROGRESS | 1 | 0 | MC_UIM
+OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
+SIGNAL | NODE | N1$BUF8.D1 | 5267 | ? | 0 | 4096 | N1$BUF8 | NULL | NULL | N1$BUF8.SI | 1 | 9 | MC_SI_D1
+SPPTERM | 0 | IV_ZERO
+OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
+SIGNAL | NODE | N1$BUF8.D2 | 5268 | ? | 0 | 6144 | N1$BUF8 | NULL | NULL | N1$BUF8.SI | 2 | 9 | MC_SI_D2
+SPPTERM | 0 | IV_DC
+OUTPUT_NODE_TYPE | 4 | 9 | MC_SI_TRST
+SIGNAL | NODE | N1$BUF8.TRST | 5270 | ? | 0 | 4096 | N1$BUF8 | NULL | NULL | N1$BUF8.SI | 4 | 9 | MC_SI_TRST
+SPPTERM | 2 | IV_TRUE | RW_IBUF | IV_TRUE | AUTOCONFIG_IN_PROGRESS
+
+SRFF_INSTANCE | N1$BUF8.REG | N1$BUF8 | 0 | 1 | 1
+INPUT_NODE_TYPE | 0 | 8 | SRFF_D
+NODE | N1$BUF8.D | 5266 | ? | 0 | 0 | N1$BUF8 | NULL | NULL | N1$BUF8.XOR | 0 | 7 | ALU_F
+OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
+NODE | N1$BUF8.Q | 5271 | ? | 0 | 0 | N1$BUF8 | NULL | NULL | N1$BUF8.REG | 0 | 8 | SRFF_Q
+
+BUF_INSTANCE | N1$BUF8.BUFOE | N1$BUF8 | 0 | 1 | 1
+INPUT_NODE_TYPE | 0 | 10 | CTOR_UNKNOWN
+SIGNAL | NODE | N1$BUF8.TRST | 5270 | ? | 0 | 4096 | N1$BUF8 | NULL | NULL | N1$BUF8.SI | 4 | 9 | MC_SI_TRST
+SPPTERM | 2 | IV_TRUE | RW_IBUF | IV_TRUE | AUTOCONFIG_IN_PROGRESS
+OUTPUT_NODE_TYPE | 0 | 10 | BUF_OUT
+NODE | N1$BUF8.BUFOE.OUT | 5269 | ? | 0 | 0 | N1$BUF8 | NULL | NULL | N1$BUF8.BUFOE | 0 | 10 | BUF_OUT
+
+MACROCELL_INSTANCE | PinTrst+OptxMapped | N1$BUF9 | LAN_IDE_CP_COPY_0_COPY_0 | 2155888640 | 2 | 2
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTOCONFIG_IN_PROGRESS | 4959 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTOCONFIG_IN_PROGRESS.Q | AUTOCONFIG_IN_PROGRESS | 1 | 0 | MC_UIM
+OUTPUT_NODE_TYPE | 0 | 0 | MC_Q
+NODE | N1$BUF9 | 4997 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | N1$BUF9.Q | N1$BUF9 | 0 | 0 | MC_Q
+OUTPUT_NODE_TYPE | 2 | 0 | MC_OE
+NODE | N1$BUF9$OE | 4998 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | N1$BUF9.BUFOE.OUT | N1$BUF9 | 2 | 0 | MC_OE
+
+SIGNAL_INSTANCE | N1$BUF9.SI | N1$BUF9 | 0 | 2 | 3
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTOCONFIG_IN_PROGRESS | 4959 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTOCONFIG_IN_PROGRESS.Q | AUTOCONFIG_IN_PROGRESS | 1 | 0 | MC_UIM
+OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
+SIGNAL | NODE | N1$BUF9.D1 | 5273 | ? | 0 | 4096 | N1$BUF9 | NULL | NULL | N1$BUF9.SI | 1 | 9 | MC_SI_D1
+SPPTERM | 0 | IV_ZERO
+OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
+SIGNAL | NODE | N1$BUF9.D2 | 5274 | ? | 0 | 6144 | N1$BUF9 | NULL | NULL | N1$BUF9.SI | 2 | 9 | MC_SI_D2
+SPPTERM | 0 | IV_DC
+OUTPUT_NODE_TYPE | 4 | 9 | MC_SI_TRST
+SIGNAL | NODE | N1$BUF9.TRST | 5276 | ? | 0 | 4096 | N1$BUF9 | NULL | NULL | N1$BUF9.SI | 4 | 9 | MC_SI_TRST
+SPPTERM | 2 | IV_TRUE | RW_IBUF | IV_TRUE | AUTOCONFIG_IN_PROGRESS
+
+SRFF_INSTANCE | N1$BUF9.REG | N1$BUF9 | 0 | 1 | 1
+INPUT_NODE_TYPE | 0 | 8 | SRFF_D
+NODE | N1$BUF9.D | 5272 | ? | 0 | 0 | N1$BUF9 | NULL | NULL | N1$BUF9.XOR | 0 | 7 | ALU_F
+OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
+NODE | N1$BUF9.Q | 5277 | ? | 0 | 0 | N1$BUF9 | NULL | NULL | N1$BUF9.REG | 0 | 8 | SRFF_Q
+
+BUF_INSTANCE | N1$BUF9.BUFOE | N1$BUF9 | 0 | 1 | 1
+INPUT_NODE_TYPE | 0 | 10 | CTOR_UNKNOWN
+SIGNAL | NODE | N1$BUF9.TRST | 5276 | ? | 0 | 4096 | N1$BUF9 | NULL | NULL | N1$BUF9.SI | 4 | 9 | MC_SI_TRST
+SPPTERM | 2 | IV_TRUE | RW_IBUF | IV_TRUE | AUTOCONFIG_IN_PROGRESS
+OUTPUT_NODE_TYPE | 0 | 10 | BUF_OUT
+NODE | N1$BUF9.BUFOE.OUT | 5275 | ? | 0 | 0 | N1$BUF9 | NULL | NULL | N1$BUF9.BUFOE | 0 | 10 | BUF_OUT
+
+INPUT_INSTANCE | 0 | 0 | NULL | IDE_A_0_OBUF | LAN_IDE_CP_COPY_0_COPY_0 | 16 | 1 | 1
+INPUT_NODE_TYPE | 0 | 5 | II_IN
+NODE | A<9> | 5063 | PI | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE
+OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX
+NODE | IDE_A_0_OBUF | 4999 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | IDE_A_0_OBUF | 0 | 5 | II_IMUX
+
+MACROCELL_INSTANCE | OptxMapped | IDE_A_0_OBUF$BUF0 | LAN_IDE_CP_COPY_0_COPY_0 | 2155872256 | 1 | 1
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | IDE_A_0_OBUF | 4999 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | IDE_A_0_OBUF | 0 | 5 | II_IMUX
+OUTPUT_NODE_TYPE | 0 | 0 | MC_Q
+NODE | IDE_A_0_OBUF$BUF0 | 5000 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_A_0_OBUF$BUF0.Q | IDE_A_0_OBUF$BUF0 | 0 | 0 | MC_Q
+
+SIGNAL_INSTANCE | IDE_A_0_OBUF$BUF0.SI | IDE_A_0_OBUF$BUF0 | 0 | 1 | 2
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | IDE_A_0_OBUF | 4999 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | IDE_A_0_OBUF | 0 | 5 | II_IMUX
+OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
+SIGNAL | NODE | IDE_A_0_OBUF$BUF0.D1 | 5279 | ? | 0 | 4096 | IDE_A_0_OBUF$BUF0 | NULL | NULL | IDE_A_0_OBUF$BUF0.SI | 1 | 9 | MC_SI_D1
+SPPTERM | 0 | IV_ZERO
+OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
+SIGNAL | NODE | IDE_A_0_OBUF$BUF0.D2 | 5280 | ? | 0 | 4096 | IDE_A_0_OBUF$BUF0 | NULL | NULL | IDE_A_0_OBUF$BUF0.SI | 2 | 9 | MC_SI_D2
+SPPTERM | 1 | IV_TRUE | IDE_A_0_OBUF
+
+SRFF_INSTANCE | IDE_A_0_OBUF$BUF0.REG | IDE_A_0_OBUF$BUF0 | 0 | 1 | 1
+INPUT_NODE_TYPE | 0 | 8 | SRFF_D
+NODE | IDE_A_0_OBUF$BUF0.D | 5278 | ? | 0 | 0 | IDE_A_0_OBUF$BUF0 | NULL | NULL | IDE_A_0_OBUF$BUF0.XOR | 0 | 7 | ALU_F
+OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
+NODE | IDE_A_0_OBUF$BUF0.Q | 5281 | ? | 0 | 0 | IDE_A_0_OBUF$BUF0 | NULL | NULL | IDE_A_0_OBUF$BUF0.REG | 0 | 8 | SRFF_Q
+
+INPUT_INSTANCE | 0 | 0 | NULL | IDE_A_1_OBUF | LAN_IDE_CP_COPY_0_COPY_0 | 16 | 1 | 1
+INPUT_NODE_TYPE | 0 | 5 | II_IN
+NODE | A<10> | 5064 | PI | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE
+OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX
+NODE | IDE_A_1_OBUF | 5001 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | IDE_A_1_OBUF | 0 | 5 | II_IMUX
+
+MACROCELL_INSTANCE | OptxMapped | IDE_A_1_OBUF$BUF0 | LAN_IDE_CP_COPY_0_COPY_0 | 2155872256 | 1 | 1
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | IDE_A_1_OBUF | 5001 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | IDE_A_1_OBUF | 0 | 5 | II_IMUX
+OUTPUT_NODE_TYPE | 0 | 0 | MC_Q
+NODE | IDE_A_1_OBUF$BUF0 | 5002 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_A_1_OBUF$BUF0.Q | IDE_A_1_OBUF$BUF0 | 0 | 0 | MC_Q
+
+SIGNAL_INSTANCE | IDE_A_1_OBUF$BUF0.SI | IDE_A_1_OBUF$BUF0 | 0 | 1 | 2
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | IDE_A_1_OBUF | 5001 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | IDE_A_1_OBUF | 0 | 5 | II_IMUX
+OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
+SIGNAL | NODE | IDE_A_1_OBUF$BUF0.D1 | 5283 | ? | 0 | 4096 | IDE_A_1_OBUF$BUF0 | NULL | NULL | IDE_A_1_OBUF$BUF0.SI | 1 | 9 | MC_SI_D1
+SPPTERM | 0 | IV_ZERO
+OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
+SIGNAL | NODE | IDE_A_1_OBUF$BUF0.D2 | 5284 | ? | 0 | 4096 | IDE_A_1_OBUF$BUF0 | NULL | NULL | IDE_A_1_OBUF$BUF0.SI | 2 | 9 | MC_SI_D2
+SPPTERM | 1 | IV_TRUE | IDE_A_1_OBUF
+
+SRFF_INSTANCE | IDE_A_1_OBUF$BUF0.REG | IDE_A_1_OBUF$BUF0 | 0 | 1 | 1
+INPUT_NODE_TYPE | 0 | 8 | SRFF_D
+NODE | IDE_A_1_OBUF$BUF0.D | 5282 | ? | 0 | 0 | IDE_A_1_OBUF$BUF0 | NULL | NULL | IDE_A_1_OBUF$BUF0.XOR | 0 | 7 | ALU_F
+OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
+NODE | IDE_A_1_OBUF$BUF0.Q | 5285 | ? | 0 | 0 | IDE_A_1_OBUF$BUF0 | NULL | NULL | IDE_A_1_OBUF$BUF0.REG | 0 | 8 | SRFF_Q
+
+INPUT_INSTANCE | 0 | 0 | NULL | IDE_A_2_OBUF | LAN_IDE_CP_COPY_0_COPY_0 | 16 | 1 | 1
+INPUT_NODE_TYPE | 0 | 5 | II_IN
+NODE | A<11> | 5065 | PI | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE
+OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX
+NODE | IDE_A_2_OBUF | 5003 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | IDE_A_2_OBUF | 0 | 5 | II_IMUX
+
+MACROCELL_INSTANCE | OptxMapped | IDE_A_2_OBUF$BUF0 | LAN_IDE_CP_COPY_0_COPY_0 | 2155872256 | 1 | 1
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | IDE_A_2_OBUF | 5003 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | IDE_A_2_OBUF | 0 | 5 | II_IMUX
+OUTPUT_NODE_TYPE | 0 | 0 | MC_Q
+NODE | IDE_A_2_OBUF$BUF0 | 5004 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_A_2_OBUF$BUF0.Q | IDE_A_2_OBUF$BUF0 | 0 | 0 | MC_Q
+
+SIGNAL_INSTANCE | IDE_A_2_OBUF$BUF0.SI | IDE_A_2_OBUF$BUF0 | 0 | 1 | 2
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | IDE_A_2_OBUF | 5003 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | IDE_A_2_OBUF | 0 | 5 | II_IMUX
+OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
+SIGNAL | NODE | IDE_A_2_OBUF$BUF0.D1 | 5287 | ? | 0 | 4096 | IDE_A_2_OBUF$BUF0 | NULL | NULL | IDE_A_2_OBUF$BUF0.SI | 1 | 9 | MC_SI_D1
+SPPTERM | 0 | IV_ZERO
+OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
+SIGNAL | NODE | IDE_A_2_OBUF$BUF0.D2 | 5288 | ? | 0 | 4096 | IDE_A_2_OBUF$BUF0 | NULL | NULL | IDE_A_2_OBUF$BUF0.SI | 2 | 9 | MC_SI_D2
+SPPTERM | 1 | IV_TRUE | IDE_A_2_OBUF
+
+SRFF_INSTANCE | IDE_A_2_OBUF$BUF0.REG | IDE_A_2_OBUF$BUF0 | 0 | 1 | 1
+INPUT_NODE_TYPE | 0 | 8 | SRFF_D
+NODE | IDE_A_2_OBUF$BUF0.D | 5286 | ? | 0 | 0 | IDE_A_2_OBUF$BUF0 | NULL | NULL | IDE_A_2_OBUF$BUF0.XOR | 0 | 7 | ALU_F
+OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
+NODE | IDE_A_2_OBUF$BUF0.Q | 5289 | ? | 0 | 0 | IDE_A_2_OBUF$BUF0 | NULL | NULL | IDE_A_2_OBUF$BUF0.REG | 0 | 8 | SRFF_Q
+
+INPUT_INSTANCE | 0 | 0 | NULL | A_12_IBUF | LAN_IDE_CP_COPY_0_COPY_0 | 16 | 1 | 1
+INPUT_NODE_TYPE | 0 | 5 | II_IN
+NODE | A<12> | 5066 | PI | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE
+OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX
+NODE | A_12_IBUF | 5005 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_12_IBUF | 0 | 5 | II_IMUX
+
+MACROCELL_INSTANCE | OptxMapped | IDE_CS_0_OBUF | LAN_IDE_CP_COPY_0_COPY_0 | 2155872256 | 1 | 1
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_12_IBUF | 5005 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_12_IBUF | 0 | 5 | II_IMUX
+OUTPUT_NODE_TYPE | 0 | 0 | MC_Q
+NODE | IDE_CS_0_OBUF | 5006 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_CS_0_OBUF.Q | IDE_CS_0_OBUF | 0 | 0 | MC_Q
+
+SIGNAL_INSTANCE | IDE_CS_0_OBUF.SI | IDE_CS_0_OBUF | 0 | 1 | 2
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_12_IBUF | 5005 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_12_IBUF | 0 | 5 | II_IMUX
+OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
+SIGNAL | NODE | IDE_CS_0_OBUF.D1 | 5291 | ? | 0 | 4096 | IDE_CS_0_OBUF | NULL | NULL | IDE_CS_0_OBUF.SI | 1 | 9 | MC_SI_D1
+SPPTERM | 0 | IV_ZERO
+OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
+SIGNAL | NODE | IDE_CS_0_OBUF.D2 | 5292 | ? | 0 | 4096 | IDE_CS_0_OBUF | NULL | NULL | IDE_CS_0_OBUF.SI | 2 | 9 | MC_SI_D2
+SPPTERM | 1 | IV_FALSE | A_12_IBUF
+
+SRFF_INSTANCE | IDE_CS_0_OBUF.REG | IDE_CS_0_OBUF | 0 | 1 | 1
+INPUT_NODE_TYPE | 0 | 8 | SRFF_D
+NODE | IDE_CS_0_OBUF.D | 5290 | ? | 0 | 0 | IDE_CS_0_OBUF | NULL | NULL | IDE_CS_0_OBUF.XOR | 0 | 7 | ALU_F
+OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
+NODE | IDE_CS_0_OBUF.Q | 5293 | ? | 0 | 0 | IDE_CS_0_OBUF | NULL | NULL | IDE_CS_0_OBUF.REG | 0 | 8 | SRFF_Q
+
+INPUT_INSTANCE | 0 | 0 | NULL | A_13_IBUF | LAN_IDE_CP_COPY_0_COPY_0 | 16 | 1 | 1
+INPUT_NODE_TYPE | 0 | 5 | II_IN
+NODE | A<13> | 5067 | PI | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE
+OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX
+NODE | A_13_IBUF | 5007 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_13_IBUF | 0 | 5 | II_IMUX
+
+MACROCELL_INSTANCE | OptxMapped | IDE_CS_1_OBUF | LAN_IDE_CP_COPY_0_COPY_0 | 2155872256 | 14 | 2
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_5_IBUF | 4927 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_4_IBUF | 4928 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_4_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_6_IBUF | 4930 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_6_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_3_IBUF | 4931 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_2_IBUF | 4932 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<0> | 4937 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<0>.Q | AUTO_CONFIG_DONE<0> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | autoconfig | 4957 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.Q | autoconfig | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<1> | 4938 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<1>.Q | AUTO_CONFIG_DONE<1> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<2> | 4939 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<2>.Q | AUTO_CONFIG_DONE<2> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_1_IBUF | 4929 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_1_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | N1$BUF1.EXP | 5354 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | N1$BUF1.EXP | N1$BUF1 | 4 | 0 | MC_EXPORT
+OUTPUT_NODE_TYPE | 0 | 0 | MC_Q
+NODE | IDE_CS_1_OBUF | 5008 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_CS_1_OBUF.Q | IDE_CS_1_OBUF | 0 | 0 | MC_Q
+OUTPUT_NODE_TYPE | 4 | 0 | MC_EXPORT
+NODE | IDE_CS_1_OBUF.EXP | 5353 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_CS_1_OBUF.EXP | IDE_CS_1_OBUF | 4 | 0 | MC_EXPORT
+
+SIGNAL_INSTANCE | IDE_CS_1_OBUF.SI | IDE_CS_1_OBUF | 0 | 14 | 3
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_5_IBUF | 4927 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_4_IBUF | 4928 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_4_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_6_IBUF | 4930 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_6_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_3_IBUF | 4931 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_2_IBUF | 4932 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<0> | 4937 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<0>.Q | AUTO_CONFIG_DONE<0> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | autoconfig | 4957 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.Q | autoconfig | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<1> | 4938 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<1>.Q | AUTO_CONFIG_DONE<1> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<2> | 4939 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<2>.Q | AUTO_CONFIG_DONE<2> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_1_IBUF | 4929 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_1_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | N1$BUF1.EXP | 5354 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | N1$BUF1.EXP | N1$BUF1 | 4 | 0 | MC_EXPORT
+OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
+SIGNAL | NODE | IDE_CS_1_OBUF.D1 | 5295 | ? | 0 | 4096 | IDE_CS_1_OBUF | NULL | NULL | IDE_CS_1_OBUF.SI | 1 | 9 | MC_SI_D1
+SPPTERM | 0 | IV_ZERO
+OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
+SIGNAL | NODE | IDE_CS_1_OBUF.D2 | 5296 | ? | 0 | 4096 | IDE_CS_1_OBUF | NULL | NULL | IDE_CS_1_OBUF.SI | 2 | 9 | MC_SI_D2
+SPPTERM | 1 | IV_TRUE | N1$BUF1.EXP
+OUTPUT_NODE_TYPE | 7 | 9 | MC_SI_EXPORT
+SIGNAL | NODE | IDE_CS_1_OBUF.EXP | 5348 | ? | 0 | 0 | IDE_CS_1_OBUF | NULL | NULL | IDE_CS_1_OBUF.SI | 7 | 9 | MC_SI_EXPORT
+SPPTERM | 10 | IV_TRUE | RESET_IBUF | IV_TRUE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_FALSE | A_4_IBUF | IV_TRUE | A_6_IBUF | IV_FALSE | A_3_IBUF | IV_FALSE | A_2_IBUF | IV_FALSE | AUTO_CONFIG_DONE<0> | IV_TRUE | autoconfig
+SPPTERM | 10 | IV_TRUE | RESET_IBUF | IV_TRUE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_FALSE | A_4_IBUF | IV_TRUE | A_6_IBUF | IV_FALSE | A_3_IBUF | IV_FALSE | A_2_IBUF | IV_FALSE | AUTO_CONFIG_DONE<1> | IV_TRUE | autoconfig
+SPPTERM | 10 | IV_TRUE | RESET_IBUF | IV_TRUE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_FALSE | A_4_IBUF | IV_TRUE | A_6_IBUF | IV_FALSE | A_3_IBUF | IV_FALSE | A_2_IBUF | IV_FALSE | AUTO_CONFIG_DONE<2> | IV_TRUE | autoconfig
+SPPTERM | 10 | IV_TRUE | RESET_IBUF | IV_TRUE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_FALSE | A_1_IBUF | IV_FALSE | A_6_IBUF | IV_FALSE | A_3_IBUF | IV_TRUE | A_2_IBUF | IV_FALSE | AUTO_CONFIG_DONE<0> | IV_TRUE | autoconfig
+SPPTERM | 11 | IV_TRUE | RESET_IBUF | IV_TRUE | RW_IBUF | IV_FALSE | AS_IBUF | IV_TRUE | A_5_IBUF | IV_FALSE | A_4_IBUF | IV_TRUE | A_1_IBUF | IV_FALSE | A_6_IBUF | IV_TRUE | A_2_IBUF | IV_TRUE | AUTO_CONFIG_DONE<0> | IV_FALSE | AUTO_CONFIG_DONE<1> | IV_TRUE | autoconfig
+
+SRFF_INSTANCE | IDE_CS_1_OBUF.REG | IDE_CS_1_OBUF | 0 | 1 | 1
+INPUT_NODE_TYPE | 0 | 8 | SRFF_D
+NODE | IDE_CS_1_OBUF.D | 5294 | ? | 0 | 0 | IDE_CS_1_OBUF | NULL | NULL | IDE_CS_1_OBUF.XOR | 0 | 7 | ALU_F
+OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
+NODE | IDE_CS_1_OBUF.Q | 5297 | ? | 0 | 0 | IDE_CS_1_OBUF | NULL | NULL | IDE_CS_1_OBUF.REG | 0 | 8 | SRFF_Q
+
+MACROCELL_INSTANCE | PinTrst+OptxMapped | ROM_B_0_OBUF$BUF1 | LAN_IDE_CP_COPY_0_COPY_0 | 2155888640 | 0 | 2
+OUTPUT_NODE_TYPE | 0 | 0 | MC_Q
+NODE | ROM_B_0_OBUF$BUF1 | 5009 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ROM_B_0_OBUF$BUF1.Q | ROM_B_0_OBUF$BUF1 | 0 | 0 | MC_Q
+OUTPUT_NODE_TYPE | 2 | 0 | MC_OE
+NODE | ROM_B_0_OBUF$BUF1$OE | 5010 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ROM_B_0_OBUF$BUF1.BUFOE.OUT | ROM_B_0_OBUF$BUF1 | 2 | 0 | MC_OE
+
+SIGNAL_INSTANCE | ROM_B_0_OBUF$BUF1.SI | ROM_B_0_OBUF$BUF1 | 0 | 0 | 3
+OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
+SIGNAL | NODE | ROM_B_0_OBUF$BUF1.D1 | 5299 | ? | 0 | 4096 | ROM_B_0_OBUF$BUF1 | NULL | NULL | ROM_B_0_OBUF$BUF1.SI | 1 | 9 | MC_SI_D1
+SPPTERM | 0 | IV_ZERO
+OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
+SIGNAL | NODE | ROM_B_0_OBUF$BUF1.D2 | 5300 | ? | 0 | 6144 | ROM_B_0_OBUF$BUF1 | NULL | NULL | ROM_B_0_OBUF$BUF1.SI | 2 | 9 | MC_SI_D2
+SPPTERM | 0 | IV_ZERO
+OUTPUT_NODE_TYPE | 4 | 9 | MC_SI_TRST
+SIGNAL | NODE | ROM_B_0_OBUF$BUF1.TRST | 5302 | ? | 0 | 6144 | ROM_B_0_OBUF$BUF1 | NULL | NULL | ROM_B_0_OBUF$BUF1.SI | 4 | 9 | MC_SI_TRST
+SPPTERM | 0 | IV_ZERO
+
+SRFF_INSTANCE | ROM_B_0_OBUF$BUF1.REG | ROM_B_0_OBUF$BUF1 | 0 | 1 | 1
+INPUT_NODE_TYPE | 0 | 8 | SRFF_D
+NODE | ROM_B_0_OBUF$BUF1.D | 5298 | ? | 0 | 0 | ROM_B_0_OBUF$BUF1 | NULL | NULL | ROM_B_0_OBUF$BUF1.XOR | 0 | 7 | ALU_F
+OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
+NODE | ROM_B_0_OBUF$BUF1.Q | 5303 | ? | 0 | 0 | ROM_B_0_OBUF$BUF1 | NULL | NULL | ROM_B_0_OBUF$BUF1.REG | 0 | 8 | SRFF_Q
+
+BUF_INSTANCE | ROM_B_0_OBUF$BUF1.BUFOE | ROM_B_0_OBUF$BUF1 | 0 | 1 | 1
+INPUT_NODE_TYPE | 0 | 10 | CTOR_UNKNOWN
+SIGNAL | NODE | ROM_B_0_OBUF$BUF1.TRST | 5302 | ? | 0 | 6144 | ROM_B_0_OBUF$BUF1 | NULL | NULL | ROM_B_0_OBUF$BUF1.SI | 4 | 9 | MC_SI_TRST
+SPPTERM | 0 | IV_ZERO
+OUTPUT_NODE_TYPE | 0 | 10 | BUF_OUT
+NODE | ROM_B_0_OBUF$BUF1.BUFOE.OUT | 5301 | ? | 0 | 0 | ROM_B_0_OBUF$BUF1 | NULL | NULL | ROM_B_0_OBUF$BUF1.BUFOE | 0 | 10 | BUF_OUT
+
+MACROCELL_INSTANCE | FbkInv+Merge+OptxMapped | ROM_B_0_OBUF | LAN_IDE_CP_COPY_0_COPY_0 | 2155907072 | 0 | 1
+OUTPUT_NODE_TYPE | 0 | 0 | MC_Q
+NODE | ROM_B_0_OBUF$Q | 5011 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ROM_B_0_OBUF.Q | ROM_B_0_OBUF | 0 | 0 | MC_Q
+
+SIGNAL_INSTANCE | ROM_B_0_OBUF.SI | ROM_B_0_OBUF | 0 | 0 | 2
+OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
+SIGNAL | NODE | ROM_B_0_OBUF.D1 | 5305 | ? | 0 | 4096 | ROM_B_0_OBUF | NULL | NULL | ROM_B_0_OBUF.SI | 1 | 9 | MC_SI_D1
+SPPTERM | 0 | IV_ZERO
+OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
+SIGNAL | NODE | ROM_B_0_OBUF.D2 | 5306 | ? | 0 | 4096 | ROM_B_0_OBUF | NULL | NULL | ROM_B_0_OBUF.SI | 2 | 9 | MC_SI_D2
+SPPTERM | 0 | IV_ZERO
+
+SRFF_INSTANCE | ROM_B_0_OBUF.REG | ROM_B_0_OBUF | 0 | 1 | 1
+INPUT_NODE_TYPE | 0 | 8 | SRFF_D
+NODE | ROM_B_0_OBUF.D | 5304 | ? | 0 | 0 | ROM_B_0_OBUF | NULL | NULL | ROM_B_0_OBUF.XOR | 0 | 7 | ALU_F
+OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
+NODE | ROM_B_0_OBUF.Q | 5307 | ? | 0 | 0 | ROM_B_0_OBUF | NULL | NULL | ROM_B_0_OBUF.REG | 0 | 8 | SRFF_Q
+
+MACROCELL_INSTANCE | OptxMapped | ROM_B_0_OBUF$BUF0 | LAN_IDE_CP_COPY_0_COPY_0 | 2155872256 | 0 | 1
+OUTPUT_NODE_TYPE | 0 | 0 | MC_Q
+NODE | ROM_B_0_OBUF$BUF0 | 5012 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ROM_B_0_OBUF$BUF0.Q | ROM_B_0_OBUF$BUF0 | 0 | 0 | MC_Q
+
+SIGNAL_INSTANCE | ROM_B_0_OBUF$BUF0.SI | ROM_B_0_OBUF$BUF0 | 0 | 0 | 2
+OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
+SIGNAL | NODE | ROM_B_0_OBUF$BUF0.D1 | 5309 | ? | 0 | 4096 | ROM_B_0_OBUF$BUF0 | NULL | NULL | ROM_B_0_OBUF$BUF0.SI | 1 | 9 | MC_SI_D1
+SPPTERM | 0 | IV_ZERO
+OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
+SIGNAL | NODE | ROM_B_0_OBUF$BUF0.D2 | 5310 | ? | 0 | 6144 | ROM_B_0_OBUF$BUF0 | NULL | NULL | ROM_B_0_OBUF$BUF0.SI | 2 | 9 | MC_SI_D2
+SPPTERM | 0 | IV_ZERO
+
+SRFF_INSTANCE | ROM_B_0_OBUF$BUF0.REG | ROM_B_0_OBUF$BUF0 | 0 | 1 | 1
+INPUT_NODE_TYPE | 0 | 8 | SRFF_D
+NODE | ROM_B_0_OBUF$BUF0.D | 5308 | ? | 0 | 0 | ROM_B_0_OBUF$BUF0 | NULL | NULL | ROM_B_0_OBUF$BUF0.XOR | 0 | 7 | ALU_F
+OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
+NODE | ROM_B_0_OBUF$BUF0.Q | 5311 | ? | 0 | 0 | ROM_B_0_OBUF$BUF0 | NULL | NULL | ROM_B_0_OBUF$BUF0.REG | 0 | 8 | SRFF_Q
+
+OUTPUT_INSTANCE | 0 | D<13> | LAN_IDE_CP_COPY_0_COPY_0 | 7 | 2 | 1
+INPUT_NODE_TYPE | 0 | 6 | OI_IN
+NODE | Dout1<1> | 5339 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | HPART_CREATED_2.Q | _12_ | 0 | 0 | MC_Q
+INPUT_NODE_TYPE | 2 | 6 | OI_OE
+NODE | Dout1<1>$OE | 4914 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | HPART_CREATED_2.BUFOE.OUT | _12_ | 2 | 0 | MC_OE
+OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT
+NODE | D<13> | 5013 | PIPO | 0 | 64 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | D<13> | 0 | 6 | OI_OUT
+
+OUTPUT_INSTANCE | 0 | D<12> | LAN_IDE_CP_COPY_0_COPY_0 | 7 | 2 | 1
+INPUT_NODE_TYPE | 0 | 6 | OI_IN
+NODE | Dout1<0> | 5323 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | HPART_CREATED_0.Q | _10_ | 0 | 0 | MC_Q
+INPUT_NODE_TYPE | 2 | 6 | OI_OE
+NODE | Dout1<0>$OE | 4917 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | HPART_CREATED_0.BUFOE.OUT | _10_ | 2 | 0 | MC_OE
+OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT
+NODE | D<12> | 5014 | PIPO | 0 | 64 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | D<12> | 0 | 6 | OI_OUT
+
+OUTPUT_INSTANCE | 0 | D<14> | LAN_IDE_CP_COPY_0_COPY_0 | 7 | 2 | 1
+INPUT_NODE_TYPE | 0 | 6 | OI_IN
+NODE | Dout1<2> | 5331 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | HPART_CREATED_1.Q | _11_ | 0 | 0 | MC_Q
+INPUT_NODE_TYPE | 2 | 6 | OI_OE
+NODE | Dout1<2>$OE | 4920 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | HPART_CREATED_1.BUFOE.OUT | _11_ | 2 | 0 | MC_OE
+OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT
+NODE | D<14> | 5015 | PIPO | 0 | 64 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | D<14> | 0 | 6 | OI_OUT
+
+OUTPUT_INSTANCE | 0 | D<15> | LAN_IDE_CP_COPY_0_COPY_0 | 7 | 2 | 1
+INPUT_NODE_TYPE | 0 | 6 | OI_IN
+NODE | Dout1<3> | 5347 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | HPART_CREATED_3.Q | _13_ | 0 | 0 | MC_Q
+INPUT_NODE_TYPE | 2 | 6 | OI_OE
+NODE | Dout1<3>$OE | 4923 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | HPART_CREATED_3.BUFOE.OUT | _13_ | 2 | 0 | MC_OE
+OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT
+NODE | D<15> | 5016 | PIPO | 0 | 64 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | D<15> | 0 | 6 | OI_OUT
+
+OUTPUT_INSTANCE | 0 | IDE_R | LAN_IDE_CP_COPY_0_COPY_0 | 7 | 1 | 1
+INPUT_NODE_TYPE | 0 | 6 | OI_IN
+NODE | IDE_R_S | 4972 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_R_S.Q | IDE_R_S | 0 | 0 | MC_Q
+OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT
+NODE | IDE_R | 5017 | PO | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | IDE_R | 0 | 6 | OI_OUT
+
+OUTPUT_INSTANCE | 0 | IDE_W | LAN_IDE_CP_COPY_0_COPY_0 | 7 | 1 | 1
+INPUT_NODE_TYPE | 0 | 6 | OI_IN
+NODE | IDE_W_S | 4973 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_W_S.Q | IDE_W_S | 0 | 0 | MC_Q
+OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT
+NODE | IDE_W | 5018 | PO | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | IDE_W | 0 | 6 | OI_OUT
+
+OUTPUT_INSTANCE | 0 | ROM_OE | LAN_IDE_CP_COPY_0_COPY_0 | 7 | 1 | 1
+INPUT_NODE_TYPE | 0 | 6 | OI_IN
+NODE | ROM_OE_S | 4974 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ROM_OE_S.Q | ROM_OE_S | 0 | 0 | MC_Q
+OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT
+NODE | ROM_OE | 5019 | PO | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | ROM_OE | 0 | 6 | OI_OUT
+
+OUTPUT_INSTANCE | 0 | D<9> | LAN_IDE_CP_COPY_0_COPY_0 | 7 | 2 | 1
+INPUT_NODE_TYPE | 0 | 6 | OI_IN
+NODE | N1$Q | 4975 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | N1.Q | N1 | 0 | 0 | MC_Q
+INPUT_NODE_TYPE | 2 | 6 | OI_OE
+NODE | N1$OE | 4976 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | N1.BUFOE.OUT | N1 | 2 | 0 | MC_OE
+OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT
+NODE | D<9> | 5020 | PIPO | 0 | 64 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | D<9> | 0 | 6 | OI_OUT
+
+OUTPUT_INSTANCE | 0 | D<8> | LAN_IDE_CP_COPY_0_COPY_0 | 7 | 2 | 1
+INPUT_NODE_TYPE | 0 | 6 | OI_IN
+NODE | N1$BUF0 | 4977 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | N1$BUF0.Q | N1$BUF0 | 0 | 0 | MC_Q
+INPUT_NODE_TYPE | 2 | 6 | OI_OE
+NODE | N1$BUF0$OE | 4978 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | N1$BUF0.BUFOE.OUT | N1$BUF0 | 2 | 0 | MC_OE
+OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT
+NODE | D<8> | 5021 | PIPO | 0 | 64 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | D<8> | 0 | 6 | OI_OUT
+
+OUTPUT_INSTANCE | 0 | D<7> | LAN_IDE_CP_COPY_0_COPY_0 | 7 | 2 | 1
+INPUT_NODE_TYPE | 0 | 6 | OI_IN
+NODE | N1$BUF1 | 4979 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | N1$BUF1.Q | N1$BUF1 | 0 | 0 | MC_Q
+INPUT_NODE_TYPE | 2 | 6 | OI_OE
+NODE | N1$BUF1$OE | 4980 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | N1$BUF1.BUFOE.OUT | N1$BUF1 | 2 | 0 | MC_OE
+OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT
+NODE | D<7> | 5022 | PO | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | D<7> | 0 | 6 | OI_OUT
+
+OUTPUT_INSTANCE | 0 | D<0> | LAN_IDE_CP_COPY_0_COPY_0 | 7 | 2 | 1
+INPUT_NODE_TYPE | 0 | 6 | OI_IN
+NODE | N1$BUF10 | 4981 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | N1$BUF10.Q | N1$BUF10 | 0 | 0 | MC_Q
+INPUT_NODE_TYPE | 2 | 6 | OI_OE
+NODE | N1$BUF10$OE | 4982 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | N1$BUF10.BUFOE.OUT | N1$BUF10 | 2 | 0 | MC_OE
+OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT
+NODE | D<0> | 5023 | PO | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | D<0> | 0 | 6 | OI_OUT
+
+OUTPUT_INSTANCE | 0 | D<6> | LAN_IDE_CP_COPY_0_COPY_0 | 7 | 2 | 1
+INPUT_NODE_TYPE | 0 | 6 | OI_IN
+NODE | N1$BUF2 | 4983 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | N1$BUF2.Q | N1$BUF2 | 0 | 0 | MC_Q
+INPUT_NODE_TYPE | 2 | 6 | OI_OE
+NODE | N1$BUF2$OE | 4984 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | N1$BUF2.BUFOE.OUT | N1$BUF2 | 2 | 0 | MC_OE
+OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT
+NODE | D<6> | 5024 | PO | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | D<6> | 0 | 6 | OI_OUT
+
+OUTPUT_INSTANCE | 0 | D<5> | LAN_IDE_CP_COPY_0_COPY_0 | 7 | 2 | 1
+INPUT_NODE_TYPE | 0 | 6 | OI_IN
+NODE | N1$BUF3 | 4985 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | N1$BUF3.Q | N1$BUF3 | 0 | 0 | MC_Q
+INPUT_NODE_TYPE | 2 | 6 | OI_OE
+NODE | N1$BUF3$OE | 4986 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | N1$BUF3.BUFOE.OUT | N1$BUF3 | 2 | 0 | MC_OE
+OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT
+NODE | D<5> | 5025 | PO | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | D<5> | 0 | 6 | OI_OUT
+
+OUTPUT_INSTANCE | 0 | D<4> | LAN_IDE_CP_COPY_0_COPY_0 | 7 | 2 | 1
+INPUT_NODE_TYPE | 0 | 6 | OI_IN
+NODE | N1$BUF4 | 4987 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | N1$BUF4.Q | N1$BUF4 | 0 | 0 | MC_Q
+INPUT_NODE_TYPE | 2 | 6 | OI_OE
+NODE | N1$BUF4$OE | 4988 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | N1$BUF4.BUFOE.OUT | N1$BUF4 | 2 | 0 | MC_OE
+OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT
+NODE | D<4> | 5026 | PO | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | D<4> | 0 | 6 | OI_OUT
+
+OUTPUT_INSTANCE | 0 | D<3> | LAN_IDE_CP_COPY_0_COPY_0 | 7 | 2 | 1
+INPUT_NODE_TYPE | 0 | 6 | OI_IN
+NODE | N1$BUF5 | 4989 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | N1$BUF5.Q | N1$BUF5 | 0 | 0 | MC_Q
+INPUT_NODE_TYPE | 2 | 6 | OI_OE
+NODE | N1$BUF5$OE | 4990 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | N1$BUF5.BUFOE.OUT | N1$BUF5 | 2 | 0 | MC_OE
+OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT
+NODE | D<3> | 5027 | PO | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | D<3> | 0 | 6 | OI_OUT
+
+OUTPUT_INSTANCE | 0 | D<2> | LAN_IDE_CP_COPY_0_COPY_0 | 7 | 2 | 1
+INPUT_NODE_TYPE | 0 | 6 | OI_IN
+NODE | N1$BUF6 | 4991 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | N1$BUF6.Q | N1$BUF6 | 0 | 0 | MC_Q
+INPUT_NODE_TYPE | 2 | 6 | OI_OE
+NODE | N1$BUF6$OE | 4992 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | N1$BUF6.BUFOE.OUT | N1$BUF6 | 2 | 0 | MC_OE
+OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT
+NODE | D<2> | 5028 | PO | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | D<2> | 0 | 6 | OI_OUT
+
+OUTPUT_INSTANCE | 0 | D<1> | LAN_IDE_CP_COPY_0_COPY_0 | 7 | 2 | 1
+INPUT_NODE_TYPE | 0 | 6 | OI_IN
+NODE | N1$BUF7 | 4993 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | N1$BUF7.Q | N1$BUF7 | 0 | 0 | MC_Q
+INPUT_NODE_TYPE | 2 | 6 | OI_OE
+NODE | N1$BUF7$OE | 4994 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | N1$BUF7.BUFOE.OUT | N1$BUF7 | 2 | 0 | MC_OE
+OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT
+NODE | D<1> | 5029 | PO | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | D<1> | 0 | 6 | OI_OUT
+
+OUTPUT_INSTANCE | 0 | D<11> | LAN_IDE_CP_COPY_0_COPY_0 | 7 | 2 | 1
+INPUT_NODE_TYPE | 0 | 6 | OI_IN
+NODE | N1$BUF8 | 4995 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | N1$BUF8.Q | N1$BUF8 | 0 | 0 | MC_Q
+INPUT_NODE_TYPE | 2 | 6 | OI_OE
+NODE | N1$BUF8$OE | 4996 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | N1$BUF8.BUFOE.OUT | N1$BUF8 | 2 | 0 | MC_OE
+OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT
+NODE | D<11> | 5030 | PIPO | 0 | 64 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | D<11> | 0 | 6 | OI_OUT
+
+OUTPUT_INSTANCE | 0 | D<10> | LAN_IDE_CP_COPY_0_COPY_0 | 7 | 2 | 1
+INPUT_NODE_TYPE | 0 | 6 | OI_IN
+NODE | N1$BUF9 | 4997 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | N1$BUF9.Q | N1$BUF9 | 0 | 0 | MC_Q
+INPUT_NODE_TYPE | 2 | 6 | OI_OE
+NODE | N1$BUF9$OE | 4998 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | N1$BUF9.BUFOE.OUT | N1$BUF9 | 2 | 0 | MC_OE
+OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT
+NODE | D<10> | 5031 | PIPO | 0 | 64 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | D<10> | 0 | 6 | OI_OUT
+
+OUTPUT_INSTANCE | 0 | IDE_A<0> | LAN_IDE_CP_COPY_0_COPY_0 | 7 | 1 | 1
+INPUT_NODE_TYPE | 0 | 6 | OI_IN
+NODE | IDE_A_0_OBUF$BUF0 | 5000 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_A_0_OBUF$BUF0.Q | IDE_A_0_OBUF$BUF0 | 0 | 0 | MC_Q
+OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT
+NODE | IDE_A<0> | 5032 | PO | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | IDE_A<0> | 0 | 6 | OI_OUT
+
+OUTPUT_INSTANCE | 0 | IDE_A<1> | LAN_IDE_CP_COPY_0_COPY_0 | 7 | 1 | 1
+INPUT_NODE_TYPE | 0 | 6 | OI_IN
+NODE | IDE_A_1_OBUF$BUF0 | 5002 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_A_1_OBUF$BUF0.Q | IDE_A_1_OBUF$BUF0 | 0 | 0 | MC_Q
+OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT
+NODE | IDE_A<1> | 5033 | PO | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | IDE_A<1> | 0 | 6 | OI_OUT
+
+OUTPUT_INSTANCE | 0 | IDE_A<2> | LAN_IDE_CP_COPY_0_COPY_0 | 7 | 1 | 1
+INPUT_NODE_TYPE | 0 | 6 | OI_IN
+NODE | IDE_A_2_OBUF$BUF0 | 5004 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_A_2_OBUF$BUF0.Q | IDE_A_2_OBUF$BUF0 | 0 | 0 | MC_Q
+OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT
+NODE | IDE_A<2> | 5034 | PO | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | IDE_A<2> | 0 | 6 | OI_OUT
+
+OUTPUT_INSTANCE | 0 | IDE_CS<0> | LAN_IDE_CP_COPY_0_COPY_0 | 7 | 1 | 1
+INPUT_NODE_TYPE | 0 | 6 | OI_IN
+NODE | IDE_CS_0_OBUF | 5006 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_CS_0_OBUF.Q | IDE_CS_0_OBUF | 0 | 0 | MC_Q
+OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT
+NODE | IDE_CS<0> | 5035 | PO | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | IDE_CS<0> | 0 | 6 | OI_OUT
+
+OUTPUT_INSTANCE | 0 | IDE_CS<1> | LAN_IDE_CP_COPY_0_COPY_0 | 7 | 1 | 1
+INPUT_NODE_TYPE | 0 | 6 | OI_IN
+NODE | IDE_CS_1_OBUF | 5008 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_CS_1_OBUF.Q | IDE_CS_1_OBUF | 0 | 0 | MC_Q
+OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT
+NODE | IDE_CS<1> | 5036 | PO | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | IDE_CS<1> | 0 | 6 | OI_OUT
+
+OUTPUT_INSTANCE | 0 | DTACK | LAN_IDE_CP_COPY_0_COPY_0 | 7 | 2 | 1
+INPUT_NODE_TYPE | 0 | 6 | OI_IN
+NODE | ROM_B_0_OBUF$BUF1 | 5009 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ROM_B_0_OBUF$BUF1.Q | ROM_B_0_OBUF$BUF1 | 0 | 0 | MC_Q
+INPUT_NODE_TYPE | 2 | 6 | OI_OE
+NODE | ROM_B_0_OBUF$BUF1$OE | 5010 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ROM_B_0_OBUF$BUF1.BUFOE.OUT | ROM_B_0_OBUF$BUF1 | 2 | 0 | MC_OE
+OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT
+NODE | DTACK | 5037 | PO | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | DTACK | 0 | 6 | OI_OUT
+
+OUTPUT_INSTANCE | 0 | ROM_B<1> | LAN_IDE_CP_COPY_0_COPY_0 | 7 | 1 | 1
+INPUT_NODE_TYPE | 0 | 6 | OI_IN
+NODE | ROM_B_0_OBUF$Q | 5011 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ROM_B_0_OBUF.Q | ROM_B_0_OBUF | 0 | 0 | MC_Q
+OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT
+NODE | ROM_B<1> | 5038 | PO | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | ROM_B<1> | 0 | 6 | OI_OUT
+
+OUTPUT_INSTANCE | 0 | ROM_B<0> | LAN_IDE_CP_COPY_0_COPY_0 | 7 | 1 | 1
+INPUT_NODE_TYPE | 0 | 6 | OI_IN
+NODE | ROM_B_0_OBUF$BUF0 | 5012 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ROM_B_0_OBUF$BUF0.Q | ROM_B_0_OBUF$BUF0 | 0 | 0 | MC_Q
+OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT
+NODE | ROM_B<0> | 5039 | PO | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | ROM_B<0> | 0 | 6 | OI_OUT
+
+MACROCELL_INSTANCE | Inv+SoftPfbk | ide/ide_CLKF | LAN_IDE_CP_COPY_0_COPY_0 | 2181038336 | 2 | 1
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | C3_IBUF | 4956 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | C3_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | C1_IBUF | 4955 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | C1_IBUF | 0 | 5 | II_IMUX
+OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
+NODE | ide/ide_CLKF.UIM | 5040 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ide/ide_CLKF.Q | ide/ide_CLKF | 1 | 0 | MC_UIM
+
+SIGNAL_INSTANCE | ide/ide_CLKF.SI | ide/ide_CLKF | 0 | 2 | 2
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | C3_IBUF | 4956 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | C3_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | C1_IBUF | 4955 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | C1_IBUF | 0 | 5 | II_IMUX
+OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
+SIGNAL | NODE | ide/ide_CLKF.D1 | 5313 | ? | 0 | 4096 | ide/ide_CLKF | NULL | NULL | ide/ide_CLKF.SI | 1 | 9 | MC_SI_D1
+SPPTERM | 1 | IV_TRUE | C3_IBUF
+OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
+SIGNAL | NODE | ide/ide_CLKF.D2 | 5314 | ? | 0 | 4096 | ide/ide_CLKF | NULL | NULL | ide/ide_CLKF.SI | 2 | 9 | MC_SI_D2
+SPPTERM | 1 | IV_TRUE | C1_IBUF
+
+SRFF_INSTANCE | ide/ide_CLKF.REG | ide/ide_CLKF | 0 | 1 | 1
+INPUT_NODE_TYPE | 0 | 8 | SRFF_D
+NODE | ide/ide_CLKF.D | 5312 | ? | 0 | 0 | ide/ide_CLKF | NULL | NULL | ide/ide_CLKF.XOR | 0 | 7 | ALU_F
+OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
+NODE | ide/ide_CLKF.Q | 5315 | ? | 0 | 0 | ide/ide_CLKF | NULL | NULL | ide/ide_CLKF.REG | 0 | 8 | SRFF_Q
+
+MACROCELL_INSTANCE | PinTrst+OptxMapped | _10_ | LAN_IDE_CP_COPY_0_COPY_0 | 2155888640 | 3 | 3
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTOCONFIG_IN_PROGRESS | 4959 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTOCONFIG_IN_PROGRESS.Q | AUTOCONFIG_IN_PROGRESS | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | D<12>_BUFR | 5319 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | Dout1<0>.Q | D<12>_BUFR.MC | 1 | 0 | MC_UIM
+OUTPUT_NODE_TYPE | 0 | 0 | MC_Q
+NODE | Dout1<0> | 5323 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | HPART_CREATED_0.Q | _10_ | 0 | 0 | MC_Q
+OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
+NODE | Dout1<0>.UIM | 4916 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | HPART_CREATED_0.Q | _10_ | 1 | 0 | MC_UIM
+OUTPUT_NODE_TYPE | 2 | 0 | MC_OE
+NODE | Dout1<0>$OE | 4917 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | HPART_CREATED_0.BUFOE.OUT | _10_ | 2 | 0 | MC_OE
+
+SIGNAL_INSTANCE | HPART_CREATED_0.SI | _10_ | 0 | 3 | 3
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTOCONFIG_IN_PROGRESS | 4959 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTOCONFIG_IN_PROGRESS.Q | AUTOCONFIG_IN_PROGRESS | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | D<12>_BUFR | 5319 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | Dout1<0>.Q | D<12>_BUFR.MC | 1 | 0 | MC_UIM
+OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
+SIGNAL | NODE | HPART_CREATED_0.D1 | 5322 | ? | 0 | 0 | _10_ | NULL | NULL | HPART_CREATED_0.SI | 1 | 9 | MC_SI_D1
+SPPTERM | 0 | IV_ZERO
+OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
+SIGNAL | NODE | HPART_CREATED_0.D2 | 5321 | ? | 0 | 0 | _10_ | NULL | NULL | HPART_CREATED_0.SI | 2 | 9 | MC_SI_D2
+SPPTERM | 1 | IV_TRUE | D<12>_BUFR
+OUTPUT_NODE_TYPE | 4 | 9 | MC_SI_TRST
+SIGNAL | NODE | HPART_CREATED_0.TRST | 5317 | ? | 0 | 0 | _10_ | NULL | NULL | HPART_CREATED_0.SI | 4 | 9 | MC_SI_TRST
+SPPTERM | 2 | IV_TRUE | RW_IBUF | IV_TRUE | AUTOCONFIG_IN_PROGRESS
+
+SRFF_INSTANCE | HPART_CREATED_0.REG | _10_ | 0 | 1 | 1
+INPUT_NODE_TYPE | 0 | 8 | SRFF_D
+NODE | HPART_CREATED_0.D | 5320 | ? | 0 | 0 | _10_ | NULL | NULL | HPART_CREATED_0.XOR | 0 | 7 | ALU_F
+OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
+NODE | HPART_CREATED_0.Q | 5318 | ? | 0 | 0 | _10_ | NULL | NULL | HPART_CREATED_0.REG | 0 | 8 | SRFF_Q
+
+BUF_INSTANCE | HPART_CREATED_0.BUFOE | _10_ | 0 | 1 | 1
+INPUT_NODE_TYPE | 0 | 10 | CTOR_UNKNOWN
+SIGNAL | NODE | HPART_CREATED_0.TRST | 5317 | ? | 0 | 0 | _10_ | NULL | NULL | HPART_CREATED_0.SI | 4 | 9 | MC_SI_TRST
+SPPTERM | 2 | IV_TRUE | RW_IBUF | IV_TRUE | AUTOCONFIG_IN_PROGRESS
+OUTPUT_NODE_TYPE | 0 | 10 | BUF_OUT
+NODE | HPART_CREATED_0.BUFOE.OUT | 5316 | ? | 0 | 0 | _10_ | NULL | NULL | HPART_CREATED_0.BUFOE | 0 | 10 | BUF_OUT
+
+MACROCELL_INSTANCE | PinTrst+OptxMapped | _11_ | LAN_IDE_CP_COPY_0_COPY_0 | 2155888640 | 3 | 3
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTOCONFIG_IN_PROGRESS | 4959 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTOCONFIG_IN_PROGRESS.Q | AUTOCONFIG_IN_PROGRESS | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | D<14>_BUFR | 5327 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | Dout1<2>.Q | D<14>_BUFR.MC | 1 | 0 | MC_UIM
+OUTPUT_NODE_TYPE | 0 | 0 | MC_Q
+NODE | Dout1<2> | 5331 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | HPART_CREATED_1.Q | _11_ | 0 | 0 | MC_Q
+OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
+NODE | Dout1<2>.UIM | 4919 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | HPART_CREATED_1.Q | _11_ | 1 | 0 | MC_UIM
+OUTPUT_NODE_TYPE | 2 | 0 | MC_OE
+NODE | Dout1<2>$OE | 4920 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | HPART_CREATED_1.BUFOE.OUT | _11_ | 2 | 0 | MC_OE
+
+SIGNAL_INSTANCE | HPART_CREATED_1.SI | _11_ | 0 | 3 | 3
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTOCONFIG_IN_PROGRESS | 4959 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTOCONFIG_IN_PROGRESS.Q | AUTOCONFIG_IN_PROGRESS | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | D<14>_BUFR | 5327 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | Dout1<2>.Q | D<14>_BUFR.MC | 1 | 0 | MC_UIM
+OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
+SIGNAL | NODE | HPART_CREATED_1.D1 | 5330 | ? | 0 | 0 | _11_ | NULL | NULL | HPART_CREATED_1.SI | 1 | 9 | MC_SI_D1
+SPPTERM | 0 | IV_ZERO
+OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
+SIGNAL | NODE | HPART_CREATED_1.D2 | 5329 | ? | 0 | 0 | _11_ | NULL | NULL | HPART_CREATED_1.SI | 2 | 9 | MC_SI_D2
+SPPTERM | 1 | IV_TRUE | D<14>_BUFR
+OUTPUT_NODE_TYPE | 4 | 9 | MC_SI_TRST
+SIGNAL | NODE | HPART_CREATED_1.TRST | 5325 | ? | 0 | 0 | _11_ | NULL | NULL | HPART_CREATED_1.SI | 4 | 9 | MC_SI_TRST
+SPPTERM | 2 | IV_TRUE | RW_IBUF | IV_TRUE | AUTOCONFIG_IN_PROGRESS
+
+SRFF_INSTANCE | HPART_CREATED_1.REG | _11_ | 0 | 1 | 1
+INPUT_NODE_TYPE | 0 | 8 | SRFF_D
+NODE | HPART_CREATED_1.D | 5328 | ? | 0 | 0 | _11_ | NULL | NULL | HPART_CREATED_1.XOR | 0 | 7 | ALU_F
+OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
+NODE | HPART_CREATED_1.Q | 5326 | ? | 0 | 0 | _11_ | NULL | NULL | HPART_CREATED_1.REG | 0 | 8 | SRFF_Q
+
+BUF_INSTANCE | HPART_CREATED_1.BUFOE | _11_ | 0 | 1 | 1
+INPUT_NODE_TYPE | 0 | 10 | CTOR_UNKNOWN
+SIGNAL | NODE | HPART_CREATED_1.TRST | 5325 | ? | 0 | 0 | _11_ | NULL | NULL | HPART_CREATED_1.SI | 4 | 9 | MC_SI_TRST
+SPPTERM | 2 | IV_TRUE | RW_IBUF | IV_TRUE | AUTOCONFIG_IN_PROGRESS
+OUTPUT_NODE_TYPE | 0 | 10 | BUF_OUT
+NODE | HPART_CREATED_1.BUFOE.OUT | 5324 | ? | 0 | 0 | _11_ | NULL | NULL | HPART_CREATED_1.BUFOE | 0 | 10 | BUF_OUT
+
+MACROCELL_INSTANCE | PinTrst+OptxMapped | _12_ | LAN_IDE_CP_COPY_0_COPY_0 | 2155888640 | 3 | 3
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTOCONFIG_IN_PROGRESS | 4959 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTOCONFIG_IN_PROGRESS.Q | AUTOCONFIG_IN_PROGRESS | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | D<13>_BUFR | 5335 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | Dout1<1>.Q | D<13>_BUFR.MC | 1 | 0 | MC_UIM
+OUTPUT_NODE_TYPE | 0 | 0 | MC_Q
+NODE | Dout1<1> | 5339 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | HPART_CREATED_2.Q | _12_ | 0 | 0 | MC_Q
+OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
+NODE | Dout1<1>.UIM | 4913 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | HPART_CREATED_2.Q | _12_ | 1 | 0 | MC_UIM
+OUTPUT_NODE_TYPE | 2 | 0 | MC_OE
+NODE | Dout1<1>$OE | 4914 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | HPART_CREATED_2.BUFOE.OUT | _12_ | 2 | 0 | MC_OE
+
+SIGNAL_INSTANCE | HPART_CREATED_2.SI | _12_ | 0 | 3 | 3
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTOCONFIG_IN_PROGRESS | 4959 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTOCONFIG_IN_PROGRESS.Q | AUTOCONFIG_IN_PROGRESS | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | D<13>_BUFR | 5335 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | Dout1<1>.Q | D<13>_BUFR.MC | 1 | 0 | MC_UIM
+OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
+SIGNAL | NODE | HPART_CREATED_2.D1 | 5338 | ? | 0 | 0 | _12_ | NULL | NULL | HPART_CREATED_2.SI | 1 | 9 | MC_SI_D1
+SPPTERM | 0 | IV_ZERO
+OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
+SIGNAL | NODE | HPART_CREATED_2.D2 | 5337 | ? | 0 | 0 | _12_ | NULL | NULL | HPART_CREATED_2.SI | 2 | 9 | MC_SI_D2
+SPPTERM | 1 | IV_TRUE | D<13>_BUFR
+OUTPUT_NODE_TYPE | 4 | 9 | MC_SI_TRST
+SIGNAL | NODE | HPART_CREATED_2.TRST | 5333 | ? | 0 | 0 | _12_ | NULL | NULL | HPART_CREATED_2.SI | 4 | 9 | MC_SI_TRST
+SPPTERM | 2 | IV_TRUE | RW_IBUF | IV_TRUE | AUTOCONFIG_IN_PROGRESS
+
+SRFF_INSTANCE | HPART_CREATED_2.REG | _12_ | 0 | 1 | 1
+INPUT_NODE_TYPE | 0 | 8 | SRFF_D
+NODE | HPART_CREATED_2.D | 5336 | ? | 0 | 0 | _12_ | NULL | NULL | HPART_CREATED_2.XOR | 0 | 7 | ALU_F
+OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
+NODE | HPART_CREATED_2.Q | 5334 | ? | 0 | 0 | _12_ | NULL | NULL | HPART_CREATED_2.REG | 0 | 8 | SRFF_Q
+
+BUF_INSTANCE | HPART_CREATED_2.BUFOE | _12_ | 0 | 1 | 1
+INPUT_NODE_TYPE | 0 | 10 | CTOR_UNKNOWN
+SIGNAL | NODE | HPART_CREATED_2.TRST | 5333 | ? | 0 | 0 | _12_ | NULL | NULL | HPART_CREATED_2.SI | 4 | 9 | MC_SI_TRST
+SPPTERM | 2 | IV_TRUE | RW_IBUF | IV_TRUE | AUTOCONFIG_IN_PROGRESS
+OUTPUT_NODE_TYPE | 0 | 10 | BUF_OUT
+NODE | HPART_CREATED_2.BUFOE.OUT | 5332 | ? | 0 | 0 | _12_ | NULL | NULL | HPART_CREATED_2.BUFOE | 0 | 10 | BUF_OUT
+
+MACROCELL_INSTANCE | PinTrst+OptxMapped | _13_ | LAN_IDE_CP_COPY_0_COPY_0 | 2155888640 | 3 | 3
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTOCONFIG_IN_PROGRESS | 4959 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTOCONFIG_IN_PROGRESS.Q | AUTOCONFIG_IN_PROGRESS | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | D<15>_BUFR | 5343 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | Dout1<3>.Q | D<15>_BUFR.MC | 1 | 0 | MC_UIM
+OUTPUT_NODE_TYPE | 0 | 0 | MC_Q
+NODE | Dout1<3> | 5347 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | HPART_CREATED_3.Q | _13_ | 0 | 0 | MC_Q
+OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
+NODE | Dout1<3>.UIM | 4922 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | HPART_CREATED_3.Q | _13_ | 1 | 0 | MC_UIM
+OUTPUT_NODE_TYPE | 2 | 0 | MC_OE
+NODE | Dout1<3>$OE | 4923 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | HPART_CREATED_3.BUFOE.OUT | _13_ | 2 | 0 | MC_OE
+
+SIGNAL_INSTANCE | HPART_CREATED_3.SI | _13_ | 0 | 3 | 3
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTOCONFIG_IN_PROGRESS | 4959 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTOCONFIG_IN_PROGRESS.Q | AUTOCONFIG_IN_PROGRESS | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | D<15>_BUFR | 5343 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | Dout1<3>.Q | D<15>_BUFR.MC | 1 | 0 | MC_UIM
+OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
+SIGNAL | NODE | HPART_CREATED_3.D1 | 5346 | ? | 0 | 0 | _13_ | NULL | NULL | HPART_CREATED_3.SI | 1 | 9 | MC_SI_D1
+SPPTERM | 0 | IV_ZERO
+OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
+SIGNAL | NODE | HPART_CREATED_3.D2 | 5345 | ? | 0 | 0 | _13_ | NULL | NULL | HPART_CREATED_3.SI | 2 | 9 | MC_SI_D2
+SPPTERM | 1 | IV_TRUE | D<15>_BUFR
+OUTPUT_NODE_TYPE | 4 | 9 | MC_SI_TRST
+SIGNAL | NODE | HPART_CREATED_3.TRST | 5341 | ? | 0 | 0 | _13_ | NULL | NULL | HPART_CREATED_3.SI | 4 | 9 | MC_SI_TRST
+SPPTERM | 2 | IV_TRUE | RW_IBUF | IV_TRUE | AUTOCONFIG_IN_PROGRESS
+
+SRFF_INSTANCE | HPART_CREATED_3.REG | _13_ | 0 | 1 | 1
+INPUT_NODE_TYPE | 0 | 8 | SRFF_D
+NODE | HPART_CREATED_3.D | 5344 | ? | 0 | 0 | _13_ | NULL | NULL | HPART_CREATED_3.XOR | 0 | 7 | ALU_F
+OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
+NODE | HPART_CREATED_3.Q | 5342 | ? | 0 | 0 | _13_ | NULL | NULL | HPART_CREATED_3.REG | 0 | 8 | SRFF_Q
+
+BUF_INSTANCE | HPART_CREATED_3.BUFOE | _13_ | 0 | 1 | 1
+INPUT_NODE_TYPE | 0 | 10 | CTOR_UNKNOWN
+SIGNAL | NODE | HPART_CREATED_3.TRST | 5341 | ? | 0 | 0 | _13_ | NULL | NULL | HPART_CREATED_3.SI | 4 | 9 | MC_SI_TRST
+SPPTERM | 2 | IV_TRUE | RW_IBUF | IV_TRUE | AUTOCONFIG_IN_PROGRESS
+OUTPUT_NODE_TYPE | 0 | 10 | BUF_OUT
+NODE | HPART_CREATED_3.BUFOE.OUT | 5340 | ? | 0 | 0 | _13_ | NULL | NULL | HPART_CREATED_3.BUFOE | 0 | 10 | BUF_OUT
+
+MACROCELL_INSTANCE | NULL | EXP14_ | LAN_IDE_CP_COPY_0_COPY_0 | 2147483648 | 14 | 1
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | Dout1<0>.UIM | 4916 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | HPART_CREATED_0.Q | _10_ | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | autoconfig | 4957 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.Q | autoconfig | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<0> | 4937 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<0>.Q | AUTO_CONFIG_DONE<0> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<1> | 4938 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<1>.Q | AUTO_CONFIG_DONE<1> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<2> | 4939 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<2>.Q | AUTO_CONFIG_DONE<2> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_5_IBUF | 4927 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_4_IBUF | 4928 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_4_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_1_IBUF | 4929 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_1_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_3_IBUF | 4931 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_2_IBUF | 4932 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | ROM_OE_S.EXP | 5356 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ROM_OE_S.EXP | ROM_OE_S | 4 | 0 | MC_EXPORT
+OUTPUT_NODE_TYPE | 4 | 0 | MC_EXPORT
+NODE | EXP14_.EXP | 5357 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | EXP14_.EXP | EXP14_ | 4 | 0 | MC_EXPORT
+
+SIGNAL_INSTANCE | EXP14_.SI | EXP14_ | 0 | 14 | 1
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | Dout1<0>.UIM | 4916 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | HPART_CREATED_0.Q | _10_ | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | autoconfig | 4957 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.Q | autoconfig | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<0> | 4937 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<0>.Q | AUTO_CONFIG_DONE<0> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<1> | 4938 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<1>.Q | AUTO_CONFIG_DONE<1> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<2> | 4939 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<2>.Q | AUTO_CONFIG_DONE<2> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_5_IBUF | 4927 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_4_IBUF | 4928 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_4_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_1_IBUF | 4929 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_1_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_3_IBUF | 4931 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_2_IBUF | 4932 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | ROM_OE_S.EXP | 5356 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | ROM_OE_S.EXP | ROM_OE_S | 4 | 0 | MC_EXPORT
+OUTPUT_NODE_TYPE | 7 | 9 | MC_SI_EXPORT
+SIGNAL | NODE | EXP14_.EXP | 5352 | ? | 0 | 0 | EXP14_ | NULL | NULL | EXP14_.SI | 7 | 9 | MC_SI_EXPORT
+SPPTERM | 1 | IV_TRUE | ROM_OE_S.EXP
+SPPTERM | 3 | IV_TRUE | RESET_IBUF | IV_FALSE | Dout1<0>.UIM | IV_FALSE | RW_IBUF
+SPPTERM | 3 | IV_TRUE | RESET_IBUF | IV_FALSE | Dout1<0>.UIM | IV_TRUE | AS_IBUF
+SPPTERM | 3 | IV_TRUE | RESET_IBUF | IV_FALSE | Dout1<0>.UIM | IV_FALSE | autoconfig
+SPPTERM | 5 | IV_TRUE | RESET_IBUF | IV_FALSE | Dout1<0>.UIM | IV_TRUE | AUTO_CONFIG_DONE<0> | IV_TRUE | AUTO_CONFIG_DONE<1> | IV_TRUE | AUTO_CONFIG_DONE<2>
+SPPTERM | 10 | IV_TRUE | RESET_IBUF | IV_TRUE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_FALSE | A_4_IBUF | IV_FALSE | A_1_IBUF | IV_FALSE | A_3_IBUF | IV_FALSE | A_2_IBUF | IV_FALSE | AUTO_CONFIG_DONE<0> | IV_TRUE | autoconfig
+
+MACROCELL_INSTANCE | NULL | EXP15_ | LAN_IDE_CP_COPY_0_COPY_0 | 2147483648 | 14 | 1
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_5_IBUF | 4927 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_4_IBUF | 4928 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_4_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_1_IBUF | 4929 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_1_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_3_IBUF | 4931 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_2_IBUF | 4932 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<0> | 4937 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<0>.Q | AUTO_CONFIG_DONE<0> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | autoconfig | 4957 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.Q | autoconfig | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_6_IBUF | 4930 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_6_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<1> | 4938 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<1>.Q | AUTO_CONFIG_DONE<1> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<2> | 4939 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<2>.Q | AUTO_CONFIG_DONE<2> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | EXP16_.EXP | 5367 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | EXP16_.EXP | EXP16_ | 4 | 0 | MC_EXPORT
+OUTPUT_NODE_TYPE | 4 | 0 | MC_EXPORT
+NODE | EXP15_.EXP | 5366 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | EXP15_.EXP | EXP15_ | 4 | 0 | MC_EXPORT
+
+SIGNAL_INSTANCE | EXP15_.SI | EXP15_ | 0 | 14 | 1
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_5_IBUF | 4927 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_4_IBUF | 4928 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_4_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_1_IBUF | 4929 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_1_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_3_IBUF | 4931 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_2_IBUF | 4932 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<0> | 4937 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<0>.Q | AUTO_CONFIG_DONE<0> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | autoconfig | 4957 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.Q | autoconfig | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_6_IBUF | 4930 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_6_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<1> | 4938 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<1>.Q | AUTO_CONFIG_DONE<1> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<2> | 4939 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<2>.Q | AUTO_CONFIG_DONE<2> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | EXP16_.EXP | 5367 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | EXP16_.EXP | EXP16_ | 4 | 0 | MC_EXPORT
+OUTPUT_NODE_TYPE | 7 | 9 | MC_SI_EXPORT
+SIGNAL | NODE | EXP15_.EXP | 5358 | ? | 0 | 0 | EXP15_ | NULL | NULL | EXP15_.SI | 7 | 9 | MC_SI_EXPORT
+SPPTERM | 1 | IV_TRUE | EXP16_.EXP
+SPPTERM | 10 | IV_TRUE | RESET_IBUF | IV_TRUE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_FALSE | A_4_IBUF | IV_TRUE | A_1_IBUF | IV_FALSE | A_3_IBUF | IV_FALSE | A_2_IBUF | IV_FALSE | AUTO_CONFIG_DONE<0> | IV_TRUE | autoconfig
+SPPTERM | 10 | IV_TRUE | RESET_IBUF | IV_TRUE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_FALSE | A_4_IBUF | IV_TRUE | A_6_IBUF | IV_FALSE | A_3_IBUF | IV_FALSE | A_2_IBUF | IV_FALSE | AUTO_CONFIG_DONE<0> | IV_TRUE | autoconfig
+SPPTERM | 10 | IV_TRUE | RESET_IBUF | IV_TRUE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_FALSE | A_4_IBUF | IV_TRUE | A_6_IBUF | IV_FALSE | A_3_IBUF | IV_FALSE | A_2_IBUF | IV_FALSE | AUTO_CONFIG_DONE<1> | IV_TRUE | autoconfig
+SPPTERM | 10 | IV_TRUE | RESET_IBUF | IV_TRUE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_FALSE | A_4_IBUF | IV_TRUE | A_6_IBUF | IV_FALSE | A_3_IBUF | IV_FALSE | A_2_IBUF | IV_FALSE | AUTO_CONFIG_DONE<2> | IV_TRUE | autoconfig
+SPPTERM | 11 | IV_TRUE | RESET_IBUF | IV_TRUE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_4_IBUF | IV_TRUE | A_1_IBUF | IV_FALSE | A_6_IBUF | IV_FALSE | A_3_IBUF | IV_TRUE | A_2_IBUF | IV_TRUE | AUTO_CONFIG_DONE<0> | IV_FALSE | AUTO_CONFIG_DONE<1> | IV_TRUE | autoconfig
+
+MACROCELL_INSTANCE | NULL | EXP16_ | LAN_IDE_CP_COPY_0_COPY_0 | 2147483648 | 12 | 1
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_5_IBUF | 4927 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_4_IBUF | 4928 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_4_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_1_IBUF | 4929 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_1_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_6_IBUF | 4930 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_6_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_3_IBUF | 4931 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_2_IBUF | 4932 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<0> | 4937 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<0>.Q | AUTO_CONFIG_DONE<0> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | autoconfig | 4957 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.Q | autoconfig | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<1> | 4938 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<1>.Q | AUTO_CONFIG_DONE<1> | 1 | 0 | MC_UIM
+OUTPUT_NODE_TYPE | 4 | 0 | MC_EXPORT
+NODE | EXP16_.EXP | 5367 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | EXP16_.EXP | EXP16_ | 4 | 0 | MC_EXPORT
+
+SIGNAL_INSTANCE | EXP16_.SI | EXP16_ | 0 | 12 | 1
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_5_IBUF | 4927 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_4_IBUF | 4928 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_4_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_1_IBUF | 4929 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_1_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_6_IBUF | 4930 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_6_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_3_IBUF | 4931 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_2_IBUF | 4932 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<0> | 4937 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<0>.Q | AUTO_CONFIG_DONE<0> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | autoconfig | 4957 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.Q | autoconfig | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<1> | 4938 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<1>.Q | AUTO_CONFIG_DONE<1> | 1 | 0 | MC_UIM
+OUTPUT_NODE_TYPE | 7 | 9 | MC_SI_EXPORT
+SIGNAL | NODE | EXP16_.EXP | 5359 | ? | 0 | 0 | EXP16_ | NULL | NULL | EXP16_.SI | 7 | 9 | MC_SI_EXPORT
+SPPTERM | 11 | IV_TRUE | RESET_IBUF | IV_TRUE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_TRUE | A_4_IBUF | IV_TRUE | A_1_IBUF | IV_FALSE | A_6_IBUF | IV_FALSE | A_3_IBUF | IV_TRUE | A_2_IBUF | IV_FALSE | AUTO_CONFIG_DONE<0> | IV_TRUE | autoconfig
+SPPTERM | 11 | IV_TRUE | RESET_IBUF | IV_TRUE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_FALSE | A_4_IBUF | IV_FALSE | A_1_IBUF | IV_FALSE | A_6_IBUF | IV_FALSE | A_3_IBUF | IV_TRUE | A_2_IBUF | IV_FALSE | AUTO_CONFIG_DONE<0> | IV_TRUE | autoconfig
+SPPTERM | 12 | IV_TRUE | RESET_IBUF | IV_TRUE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_TRUE | A_4_IBUF | IV_FALSE | A_1_IBUF | IV_FALSE | A_6_IBUF | IV_TRUE | A_3_IBUF | IV_TRUE | A_2_IBUF | IV_TRUE | AUTO_CONFIG_DONE<0> | IV_FALSE | AUTO_CONFIG_DONE<1> | IV_TRUE | autoconfig
+
+MACROCELL_INSTANCE | NULL | EXP17_ | LAN_IDE_CP_COPY_0_COPY_0 | 2147483648 | 14 | 1
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | Dout1<1>.UIM | 4913 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | HPART_CREATED_2.Q | _12_ | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<0> | 4937 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<0>.Q | AUTO_CONFIG_DONE<0> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<1> | 4938 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<1>.Q | AUTO_CONFIG_DONE<1> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<2> | 4939 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<2>.Q | AUTO_CONFIG_DONE<2> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_5_IBUF | 4927 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_4_IBUF | 4928 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_4_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_6_IBUF | 4930 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_6_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_3_IBUF | 4931 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | autoconfig | 4957 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.Q | autoconfig | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_2_IBUF | 4932 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | IDE_BASEADR<6>.EXP | 5370 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_BASEADR<6>.EXP | IDE_BASEADR<6> | 4 | 0 | MC_EXPORT
+OUTPUT_NODE_TYPE | 4 | 0 | MC_EXPORT
+NODE | EXP17_.EXP | 5371 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | EXP17_.EXP | EXP17_ | 4 | 0 | MC_EXPORT
+
+SIGNAL_INSTANCE | EXP17_.SI | EXP17_ | 0 | 14 | 1
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | Dout1<1>.UIM | 4913 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | HPART_CREATED_2.Q | _12_ | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<0> | 4937 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<0>.Q | AUTO_CONFIG_DONE<0> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<1> | 4938 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<1>.Q | AUTO_CONFIG_DONE<1> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<2> | 4939 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<2>.Q | AUTO_CONFIG_DONE<2> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_5_IBUF | 4927 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_4_IBUF | 4928 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_4_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_6_IBUF | 4930 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_6_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_3_IBUF | 4931 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | autoconfig | 4957 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.Q | autoconfig | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_2_IBUF | 4932 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | IDE_BASEADR<6>.EXP | 5370 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_BASEADR<6>.EXP | IDE_BASEADR<6> | 4 | 0 | MC_EXPORT
+OUTPUT_NODE_TYPE | 7 | 9 | MC_SI_EXPORT
+SIGNAL | NODE | EXP17_.EXP | 5363 | ? | 0 | 0 | EXP17_ | NULL | NULL | EXP17_.SI | 7 | 9 | MC_SI_EXPORT
+SPPTERM | 1 | IV_TRUE | IDE_BASEADR<6>.EXP
+SPPTERM | 3 | IV_TRUE | RESET_IBUF | IV_FALSE | Dout1<1>.UIM | IV_FALSE | RW_IBUF
+SPPTERM | 5 | IV_TRUE | RESET_IBUF | IV_FALSE | Dout1<1>.UIM | IV_TRUE | AUTO_CONFIG_DONE<0> | IV_TRUE | AUTO_CONFIG_DONE<1> | IV_TRUE | AUTO_CONFIG_DONE<2>
+SPPTERM | 9 | IV_TRUE | RESET_IBUF | IV_TRUE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_FALSE | A_4_IBUF | IV_FALSE | A_6_IBUF | IV_FALSE | A_3_IBUF | IV_FALSE | AUTO_CONFIG_DONE<0> | IV_TRUE | autoconfig
+SPPTERM | 9 | IV_TRUE | RESET_IBUF | IV_TRUE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_FALSE | A_4_IBUF | IV_FALSE | A_3_IBUF | IV_FALSE | A_2_IBUF | IV_FALSE | AUTO_CONFIG_DONE<0> | IV_TRUE | autoconfig
+SPPTERM | 9 | IV_TRUE | RESET_IBUF | IV_TRUE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_FALSE | A_4_IBUF | IV_FALSE | A_3_IBUF | IV_FALSE | A_2_IBUF | IV_FALSE | AUTO_CONFIG_DONE<1> | IV_TRUE | autoconfig
+
+MACROCELL_INSTANCE | NULL | EXP18_ | LAN_IDE_CP_COPY_0_COPY_0 | 2147483648 | 13 | 1
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | Dout1<2>.UIM | 4919 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | HPART_CREATED_1.Q | _11_ | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | autoconfig | 4957 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.Q | autoconfig | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<0> | 4937 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<0>.Q | AUTO_CONFIG_DONE<0> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<1> | 4938 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<1>.Q | AUTO_CONFIG_DONE<1> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<2> | 4939 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<2>.Q | AUTO_CONFIG_DONE<2> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_5_IBUF | 4927 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_1_IBUF | 4929 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_1_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_6_IBUF | 4930 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_6_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_3_IBUF | 4931 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_2_IBUF | 4932 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX
+OUTPUT_NODE_TYPE | 4 | 0 | MC_EXPORT
+NODE | EXP18_.EXP | 5373 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | EXP18_.EXP | EXP18_ | 4 | 0 | MC_EXPORT
+
+SIGNAL_INSTANCE | EXP18_.SI | EXP18_ | 0 | 13 | 1
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | Dout1<2>.UIM | 4919 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | HPART_CREATED_1.Q | _11_ | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | autoconfig | 4957 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.Q | autoconfig | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<0> | 4937 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<0>.Q | AUTO_CONFIG_DONE<0> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<1> | 4938 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<1>.Q | AUTO_CONFIG_DONE<1> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<2> | 4939 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<2>.Q | AUTO_CONFIG_DONE<2> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_5_IBUF | 4927 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_1_IBUF | 4929 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_1_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_6_IBUF | 4930 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_6_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_3_IBUF | 4931 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_2_IBUF | 4932 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX
+OUTPUT_NODE_TYPE | 7 | 9 | MC_SI_EXPORT
+SIGNAL | NODE | EXP18_.EXP | 5365 | ? | 0 | 0 | EXP18_ | NULL | NULL | EXP18_.SI | 7 | 9 | MC_SI_EXPORT
+SPPTERM | 3 | IV_TRUE | RESET_IBUF | IV_FALSE | Dout1<2>.UIM | IV_FALSE | RW_IBUF
+SPPTERM | 3 | IV_TRUE | RESET_IBUF | IV_FALSE | Dout1<2>.UIM | IV_TRUE | AS_IBUF
+SPPTERM | 3 | IV_TRUE | RESET_IBUF | IV_FALSE | Dout1<2>.UIM | IV_FALSE | autoconfig
+SPPTERM | 5 | IV_TRUE | RESET_IBUF | IV_FALSE | Dout1<2>.UIM | IV_TRUE | AUTO_CONFIG_DONE<0> | IV_TRUE | AUTO_CONFIG_DONE<1> | IV_TRUE | AUTO_CONFIG_DONE<2>
+SPPTERM | 11 | IV_TRUE | RESET_IBUF | IV_TRUE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_TRUE | A_1_IBUF | IV_FALSE | A_6_IBUF | IV_FALSE | A_3_IBUF | IV_TRUE | A_2_IBUF | IV_TRUE | AUTO_CONFIG_DONE<0> | IV_FALSE | AUTO_CONFIG_DONE<2> | IV_TRUE | autoconfig
+
+MACROCELL_INSTANCE | NULL | EXP19_ | LAN_IDE_CP_COPY_0_COPY_0 | 2147483648 | 7 | 1
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_23_IBUF | 4933 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_23_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | IDE_BASEADR<7> | 4951 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_BASEADR<7>.Q | IDE_BASEADR<7> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_22_IBUF | 4934 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_22_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | IDE_BASEADR<6> | 4950 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_BASEADR<6>.Q | IDE_BASEADR<6> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | IDE_BASEADR<1> | 4947 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_BASEADR<1>.Q | IDE_BASEADR<1> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_17_IBUF | 4968 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_17_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | EXP20_.EXP | 5379 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | EXP20_.EXP | EXP20_ | 4 | 0 | MC_EXPORT
+OUTPUT_NODE_TYPE | 4 | 0 | MC_EXPORT
+NODE | EXP19_.EXP | 5378 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | EXP19_.EXP | EXP19_ | 4 | 0 | MC_EXPORT
+
+SIGNAL_INSTANCE | EXP19_.SI | EXP19_ | 0 | 7 | 1
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_23_IBUF | 4933 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_23_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | IDE_BASEADR<7> | 4951 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_BASEADR<7>.Q | IDE_BASEADR<7> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_22_IBUF | 4934 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_22_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | IDE_BASEADR<6> | 4950 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_BASEADR<6>.Q | IDE_BASEADR<6> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | IDE_BASEADR<1> | 4947 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_BASEADR<1>.Q | IDE_BASEADR<1> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_17_IBUF | 4968 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_17_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | EXP20_.EXP | 5379 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | EXP20_.EXP | EXP20_ | 4 | 0 | MC_EXPORT
+OUTPUT_NODE_TYPE | 7 | 9 | MC_SI_EXPORT
+SIGNAL | NODE | EXP19_.EXP | 5374 | ? | 0 | 0 | EXP19_ | NULL | NULL | EXP19_.SI | 7 | 9 | MC_SI_EXPORT
+SPPTERM | 1 | IV_TRUE | EXP20_.EXP
+SPPTERM | 2 | IV_TRUE | A_23_IBUF | IV_FALSE | IDE_BASEADR<7>
+SPPTERM | 2 | IV_FALSE | A_23_IBUF | IV_TRUE | IDE_BASEADR<7>
+SPPTERM | 2 | IV_TRUE | A_22_IBUF | IV_FALSE | IDE_BASEADR<6>
+SPPTERM | 2 | IV_FALSE | A_22_IBUF | IV_TRUE | IDE_BASEADR<6>
+SPPTERM | 2 | IV_TRUE | IDE_BASEADR<1> | IV_FALSE | A_17_IBUF
+
+MACROCELL_INSTANCE | NULL | EXP20_ | LAN_IDE_CP_COPY_0_COPY_0 | 2147483648 | 4 | 1
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_21_IBUF | 4935 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_21_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | IDE_BASEADR<5> | 4945 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_BASEADR<5>.Q | IDE_BASEADR<5> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | IDE_BASEADR<4> | 4944 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_BASEADR<4>.Q | IDE_BASEADR<4> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_20_IBUF | 4970 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_20_IBUF | 0 | 5 | II_IMUX
+OUTPUT_NODE_TYPE | 4 | 0 | MC_EXPORT
+NODE | EXP20_.EXP | 5379 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | EXP20_.EXP | EXP20_ | 4 | 0 | MC_EXPORT
+
+SIGNAL_INSTANCE | EXP20_.SI | EXP20_ | 0 | 4 | 1
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_21_IBUF | 4935 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_21_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | IDE_BASEADR<5> | 4945 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_BASEADR<5>.Q | IDE_BASEADR<5> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | IDE_BASEADR<4> | 4944 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_BASEADR<4>.Q | IDE_BASEADR<4> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_20_IBUF | 4970 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_20_IBUF | 0 | 5 | II_IMUX
+OUTPUT_NODE_TYPE | 7 | 9 | MC_SI_EXPORT
+SIGNAL | NODE | EXP20_.EXP | 5375 | ? | 0 | 0 | EXP20_ | NULL | NULL | EXP20_.SI | 7 | 9 | MC_SI_EXPORT
+SPPTERM | 2 | IV_FALSE | A_21_IBUF | IV_TRUE | IDE_BASEADR<5>
+SPPTERM | 2 | IV_TRUE | IDE_BASEADR<4> | IV_FALSE | A_20_IBUF
+SPPTERM | 2 | IV_FALSE | IDE_BASEADR<4> | IV_TRUE | A_20_IBUF
+
+MACROCELL_INSTANCE | NULL | EXP21_ | LAN_IDE_CP_COPY_0_COPY_0 | 2147483648 | 7 | 1
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | IDE_BASEADR<0> | 4943 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_BASEADR<0>.Q | IDE_BASEADR<0> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_16_IBUF | 4969 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_16_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | IDE_BASEADR<1> | 4947 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_BASEADR<1>.Q | IDE_BASEADR<1> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_17_IBUF | 4968 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_17_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | IDE_BASEADR<2> | 4948 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_BASEADR<2>.Q | IDE_BASEADR<2> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_18_IBUF | 4971 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_18_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | autoconfig.EXP | 5380 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.EXP | autoconfig | 4 | 0 | MC_EXPORT
+OUTPUT_NODE_TYPE | 4 | 0 | MC_EXPORT
+NODE | EXP21_.EXP | 5381 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | EXP21_.EXP | EXP21_ | 4 | 0 | MC_EXPORT
+
+SIGNAL_INSTANCE | EXP21_.SI | EXP21_ | 0 | 7 | 1
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | IDE_BASEADR<0> | 4943 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_BASEADR<0>.Q | IDE_BASEADR<0> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_16_IBUF | 4969 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_16_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | IDE_BASEADR<1> | 4947 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_BASEADR<1>.Q | IDE_BASEADR<1> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_17_IBUF | 4968 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_17_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | IDE_BASEADR<2> | 4948 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | IDE_BASEADR<2>.Q | IDE_BASEADR<2> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_18_IBUF | 4971 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_18_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | autoconfig.EXP | 5380 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.EXP | autoconfig | 4 | 0 | MC_EXPORT
+OUTPUT_NODE_TYPE | 7 | 9 | MC_SI_EXPORT
+SIGNAL | NODE | EXP21_.EXP | 5377 | ? | 0 | 0 | EXP21_ | NULL | NULL | EXP21_.SI | 7 | 9 | MC_SI_EXPORT
+SPPTERM | 1 | IV_TRUE | autoconfig.EXP
+SPPTERM | 2 | IV_TRUE | IDE_BASEADR<0> | IV_FALSE | A_16_IBUF
+SPPTERM | 2 | IV_FALSE | IDE_BASEADR<0> | IV_TRUE | A_16_IBUF
+SPPTERM | 2 | IV_FALSE | IDE_BASEADR<1> | IV_TRUE | A_17_IBUF
+SPPTERM | 2 | IV_TRUE | IDE_BASEADR<2> | IV_FALSE | A_18_IBUF
+SPPTERM | 2 | IV_FALSE | IDE_BASEADR<2> | IV_TRUE | A_18_IBUF
+
+MACROCELL_INSTANCE | NULL | EXP22_ | LAN_IDE_CP_COPY_0_COPY_0 | 2147483648 | 14 | 1
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | Dout1<3>.UIM | 4922 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | HPART_CREATED_3.Q | _13_ | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<0> | 4937 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<0>.Q | AUTO_CONFIG_DONE<0> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<1> | 4938 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<1>.Q | AUTO_CONFIG_DONE<1> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<2> | 4939 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<2>.Q | AUTO_CONFIG_DONE<2> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_5_IBUF | 4927 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_1_IBUF | 4929 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_1_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_6_IBUF | 4930 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_6_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_3_IBUF | 4931 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | autoconfig | 4957 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.Q | autoconfig | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_4_IBUF | 4928 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_4_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_2_IBUF | 4932 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX
+OUTPUT_NODE_TYPE | 4 | 0 | MC_EXPORT
+NODE | EXP22_.EXP | 5384 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | EXP22_.EXP | EXP22_ | 4 | 0 | MC_EXPORT
+
+SIGNAL_INSTANCE | EXP22_.SI | EXP22_ | 0 | 14 | 1
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | Dout1<3>.UIM | 4922 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | HPART_CREATED_3.Q | _13_ | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<0> | 4937 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<0>.Q | AUTO_CONFIG_DONE<0> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<1> | 4938 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<1>.Q | AUTO_CONFIG_DONE<1> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<2> | 4939 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<2>.Q | AUTO_CONFIG_DONE<2> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_5_IBUF | 4927 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_1_IBUF | 4929 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_1_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_6_IBUF | 4930 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_6_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_3_IBUF | 4931 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | autoconfig | 4957 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.Q | autoconfig | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_4_IBUF | 4928 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_4_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_2_IBUF | 4932 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX
+OUTPUT_NODE_TYPE | 7 | 9 | MC_SI_EXPORT
+SIGNAL | NODE | EXP22_.EXP | 5382 | ? | 0 | 0 | EXP22_ | NULL | NULL | EXP22_.SI | 7 | 9 | MC_SI_EXPORT
+SPPTERM | 5 | IV_TRUE | RESET_IBUF | IV_FALSE | Dout1<3>.UIM | IV_TRUE | AUTO_CONFIG_DONE<0> | IV_TRUE | AUTO_CONFIG_DONE<1> | IV_TRUE | AUTO_CONFIG_DONE<2>
+SPPTERM | 9 | IV_TRUE | RESET_IBUF | IV_TRUE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_TRUE | A_1_IBUF | IV_FALSE | A_6_IBUF | IV_FALSE | A_3_IBUF | IV_FALSE | AUTO_CONFIG_DONE<0> | IV_TRUE | autoconfig
+SPPTERM | 10 | IV_TRUE | RESET_IBUF | IV_TRUE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_FALSE | A_4_IBUF | IV_TRUE | A_6_IBUF | IV_FALSE | A_3_IBUF | IV_FALSE | A_2_IBUF | IV_FALSE | AUTO_CONFIG_DONE<0> | IV_TRUE | autoconfig
+SPPTERM | 10 | IV_TRUE | RESET_IBUF | IV_TRUE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_FALSE | A_4_IBUF | IV_TRUE | A_6_IBUF | IV_FALSE | A_3_IBUF | IV_FALSE | A_2_IBUF | IV_FALSE | AUTO_CONFIG_DONE<1> | IV_TRUE | autoconfig
+
+MACROCELL_INSTANCE | NULL | EXP23_ | LAN_IDE_CP_COPY_0_COPY_0 | 2147483648 | 13 | 1
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_5_IBUF | 4927 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_4_IBUF | 4928 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_4_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_6_IBUF | 4930 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_6_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_3_IBUF | 4931 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_2_IBUF | 4932 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<2> | 4939 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<2>.Q | AUTO_CONFIG_DONE<2> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | autoconfig | 4957 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.Q | autoconfig | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_1_IBUF | 4929 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_1_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<1> | 4938 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<1>.Q | AUTO_CONFIG_DONE<1> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<0> | 4937 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<0>.Q | AUTO_CONFIG_DONE<0> | 1 | 0 | MC_UIM
+OUTPUT_NODE_TYPE | 4 | 0 | MC_EXPORT
+NODE | EXP23_.EXP | 5385 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | EXP23_.EXP | EXP23_ | 4 | 0 | MC_EXPORT
+
+SIGNAL_INSTANCE | EXP23_.SI | EXP23_ | 0 | 13 | 1
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RESET_IBUF | 4910 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RESET_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | RW_IBUF | 4925 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | RW_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AS_IBUF | 4926 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | AS_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_5_IBUF | 4927 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_4_IBUF | 4928 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_4_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_6_IBUF | 4930 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_6_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_3_IBUF | 4931 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_2_IBUF | 4932 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<2> | 4939 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<2>.Q | AUTO_CONFIG_DONE<2> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | autoconfig | 4957 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | autoconfig.Q | autoconfig | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | A_1_IBUF | 4929 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | NULL | A_1_IBUF | 0 | 5 | II_IMUX
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<1> | 4938 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<1>.Q | AUTO_CONFIG_DONE<1> | 1 | 0 | MC_UIM
+INPUT_NODE_TYPE | 1 | 100 | NOTYPE
+NODE | AUTO_CONFIG_DONE<0> | 4937 | ? | 0 | 0 | LAN_IDE_CP_COPY_0_COPY_0 | NULL | AUTO_CONFIG_DONE<0>.Q | AUTO_CONFIG_DONE<0> | 1 | 0 | MC_UIM
+OUTPUT_NODE_TYPE | 7 | 9 | MC_SI_EXPORT
+SIGNAL | NODE | EXP23_.EXP | 5383 | ? | 0 | 0 | EXP23_ | NULL | NULL | EXP23_.SI | 7 | 9 | MC_SI_EXPORT
+SPPTERM | 10 | IV_TRUE | RESET_IBUF | IV_TRUE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_FALSE | A_4_IBUF | IV_TRUE | A_6_IBUF | IV_FALSE | A_3_IBUF | IV_FALSE | A_2_IBUF | IV_FALSE | AUTO_CONFIG_DONE<2> | IV_TRUE | autoconfig
+SPPTERM | 10 | IV_TRUE | RESET_IBUF | IV_TRUE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_TRUE | A_1_IBUF | IV_FALSE | A_6_IBUF | IV_FALSE | A_3_IBUF | IV_TRUE | AUTO_CONFIG_DONE<1> | IV_FALSE | AUTO_CONFIG_DONE<2> | IV_TRUE | autoconfig
+SPPTERM | 11 | IV_TRUE | RESET_IBUF | IV_TRUE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_TRUE | A_4_IBUF | IV_TRUE | A_1_IBUF | IV_FALSE | A_6_IBUF | IV_TRUE | A_2_IBUF | IV_TRUE | AUTO_CONFIG_DONE<0> | IV_FALSE | AUTO_CONFIG_DONE<1> | IV_TRUE | autoconfig
+SPPTERM | 12 | IV_TRUE | RESET_IBUF | IV_TRUE | RW_IBUF | IV_FALSE | AS_IBUF | IV_TRUE | A_5_IBUF | IV_FALSE | A_4_IBUF | IV_FALSE | A_1_IBUF | IV_FALSE | A_6_IBUF | IV_FALSE | A_3_IBUF | IV_TRUE | A_2_IBUF | IV_TRUE | AUTO_CONFIG_DONE<0> | IV_FALSE | AUTO_CONFIG_DONE<1> | IV_TRUE | autoconfig
+SPPTERM | 12 | IV_TRUE | RESET_IBUF | IV_TRUE | RW_IBUF | IV_FALSE | AS_IBUF | IV_FALSE | A_5_IBUF | IV_TRUE | A_4_IBUF | IV_FALSE | A_1_IBUF | IV_FALSE | A_6_IBUF | IV_TRUE | A_3_IBUF | IV_FALSE | A_2_IBUF | IV_TRUE | AUTO_CONFIG_DONE<0> | IV_FALSE | AUTO_CONFIG_DONE<1> | IV_TRUE | autoconfig
+
+FB_INSTANCE | FOOBAR1_ | LAN_IDE_CP_COPY_0_COPY_0 | 0 | 0 | 0
+FBPIN | 1 | IDE_CS_1_OBUF | 1 | NULL | 0 | IDE_CS<1> | 1 | 23 | 49152
+FBPIN | 2 | N1$BUF1 | 1 | NULL | 0 | D<7> | 1 | 16 | 49152
+FBPIN | 3 | N1$BUF7 | 1 | NULL | 0 | D<1> | 1 | 17 | 49152
+FBPIN | 4 | IDE_A_2_OBUF$BUF0 | 1 | NULL | 0 | IDE_A<2> | 1 | 25 | 49152
+FBPIN | 5 | N1$BUF0 | 1 | N5 | 1 | D<8> | 1 | 19 | 49152
+FBPIN | 6 | N1$BUF3 | 1 | NULL | 0 | D<5> | 1 | 20 | 49152
+FBPIN | 7 | AUTOCONFIG_IN_PROGRESS | 1 | NULL | 0 | NULL | 0
+FBPIN | 8 | N1$BUF4 | 1 | NULL | 0 | D<4> | 1 | 21 | 49152
+FBPIN | 9 | IDE_CS_0_OBUF | 1 | NULL | 0 | IDE_CS<0> | 1 | 22 | 49152
+FBPIN | 10 | IDE_ENABLE | 1 | NULL | 0 | NULL | 0 | 31 | 49152
+FBPIN | 11 | IDE_A_0_OBUF$BUF0 | 1 | NULL | 0 | IDE_A<0> | 1 | 24 | 49152
+FBPIN | 12 | IDE_A_1_OBUF$BUF0 | 1 | NULL | 0 | IDE_A<1> | 1 | 26 | 49152
+FBPIN | 14 | IDE_R_S | 1 | NULL | 0 | IDE_R | 1 | 27 | 49152
+FBPIN | 15 | IDE_W_S | 1 | NULL | 0 | IDE_W | 1 | 28 | 49152
+FBPIN | 16 | ROM_OE_S | 1 | NULL | 0 | ROM_OE | 1 | 35 | 49152
+FBPIN | 17 | EXP14_ | 1 | NULL | 0 | NULL | 0 | 30 | 57344
+FBPIN | 18 | D<12>_BUFR.MC | 1 | NULL | 0 | NULL | 0
+
+FB_INSTANCE | FOOBAR2_ | LAN_IDE_CP_COPY_0_COPY_0 | 0 | 0 | 0
+FBPIN | 1 | D<14>_BUFR.MC | 1 | NULL | 0 | NULL | 0 | 142 | 49152
+FBPIN | 2 | EXP15_ | 1 | RESET_IBUF | 1 | NULL | 0 | 143 | 51200
+FBPIN | 3 | EXP16_ | 1 | NULL | 0 | NULL | 0
+FBPIN | 5 | N1$BUF10 | 1 | NULL | 0 | D<0> | 1 | 2 | 53248
+FBPIN | 8 | AUTO_CONFIG_DONE<2> | 1 | NULL | 0 | NULL | 0 | 5 | 53248
+FBPIN | 9 | AUTO_CONFIG_DONE<0> | 1 | NULL | 0 | NULL | 0 | 6 | 53248
+FBPIN | 10 | AUTO_CONFIG_DONE_CYCLE<2> | 1 | NULL | 0 | NULL | 0 | 7 | 49152
+FBPIN | 11 | AUTO_CONFIG_DONE_CYCLE<0> | 1 | NULL | 0 | NULL | 0 | 9 | 49152
+FBPIN | 12 | IDE_BASEADR<7> | 1 | NULL | 0 | NULL | 0 | 10 | 49152
+FBPIN | 13 | IDE_BASEADR<6> | 1 | NULL | 0 | NULL | 0 | 12 | 49152
+FBPIN | 14 | EXP17_ | 1 | NULL | 0 | NULL | 0 | 11 | 49152
+FBPIN | 15 | D<13>_BUFR.MC | 1 | NULL | 0 | NULL | 0 | 13 | 49152
+FBPIN | 16 | N1$BUF2 | 1 | NULL | 0 | D<6> | 1 | 14 | 49152
+FBPIN | 17 | N1$BUF5 | 1 | NULL | 0 | D<3> | 1 | 15 | 49152
+FBPIN | 18 | EXP18_ | 1 | NULL | 0 | NULL | 0
+
+FB_INSTANCE | FOOBAR3_ | LAN_IDE_CP_COPY_0_COPY_0 | 0 | 0 | 0
+FBPIN | 1 | N1$BUF6 | 1 | NULL | 0 | D<2> | 1 | 39 | 49152
+FBPIN | 3 | N1$BUF9 | 1 | N7 | 1 | D<10> | 1 | 41 | 49152
+FBPIN | 4 | _10_ | 1 | N11 | 1 | D<12> | 1 | 44 | 49152
+FBPIN | 7 | _11_ | 1 | N3 | 1 | D<14> | 1 | 46 | 49152
+FBPIN | 9 | N1 | 1 | N6 | 1 | D<9> | 1 | 40 | 49152
+FBPIN | 10 | _13_ | 1 | N4 | 1 | D<15> | 1 | 48 | 49152
+FBPIN | 11 | N1$BUF8 | 1 | N0 | 1 | D<11> | 1 | 43 | 49152
+FBPIN | 12 | _12_ | 1 | N2 | 1 | D<13> | 1 | 45 | 49152
+FBPIN | 14 | NULL | 0 | A_5_IBUF | 1 | NULL | 0 | 49 | 49152
+FBPIN | 15 | AUTO_CONFIG_DONE<1> | 1 | A_4_IBUF | 1 | NULL | 0 | 50 | 49152
+FBPIN | 16 | AUTO_CONFIG_DONE_CYCLE<1> | 1 | NULL | 0 | NULL | 0
+FBPIN | 17 | IDE_BASEADR<3> | 1 | A_6_IBUF | 1 | NULL | 0 | 51 | 49152
+FBPIN | 18 | IDE_BASEADR<2> | 1 | NULL | 0 | NULL | 0
+
+FB_INSTANCE | FOOBAR4_ | LAN_IDE_CP_COPY_0_COPY_0 | 0 | 0 | 0
+FBPIN | 1 | ide | 1 | NULL | 0 | NULL | 0 | 118 | 49152
+FBPIN | 2 | EXP19_ | 1 | NULL | 0 | NULL | 0 | 126 | 49152
+FBPIN | 3 | EXP20_ | 1 | NULL | 0 | NULL | 0 | 133 | 49152
+FBPIN | 16 | ide/ide_CLKF | 1 | NULL | 0 | NULL | 0 | 139 | 49152
+FBPIN | 17 | autoconfig | 1 | NULL | 0 | NULL | 0 | 140 | 49152
+FBPIN | 18 | EXP21_ | 1 | NULL | 0 | NULL | 0
+
+FB_INSTANCE | FOOBAR5_ | LAN_IDE_CP_COPY_0_COPY_0 | 0 | 0 | 0
+FBPIN | 2 | NULL | 0 | A_3_IBUF | 1 | NULL | 0 | 52 | 49152
+FBPIN | 3 | NULL | 0 | IDE_A_1_OBUF | 1 | NULL | 0 | 59 | 49152
+FBPIN | 6 | NULL | 0 | A_2_IBUF | 1 | NULL | 0 | 54 | 49152
+FBPIN | 9 | NULL | 0 | A_1_IBUF | 1 | NULL | 0 | 57 | 49152
+FBPIN | 10 | ROM_B_0_OBUF$BUF0 | 1 | NULL | 0 | ROM_B<0> | 1 | 68 | 49152
+FBPIN | 11 | NULL | 0 | IDE_A_0_OBUF | 1 | NULL | 0 | 58 | 49152
+FBPIN | 12 | NULL | 0 | IDE_A_2_OBUF | 1 | NULL | 0 | 60 | 49152
+FBPIN | 13 | SHUT_UP<1> | 1 | NULL | 0 | NULL | 0 | 70 | 49152
+FBPIN | 14 | IDE_BASEADR<5> | 1 | A_12_IBUF | 1 | NULL | 0 | 61 | 49152
+FBPIN | 15 | IDE_BASEADR<4> | 1 | A_13_IBUF | 1 | NULL | 0 | 64 | 49152
+FBPIN | 16 | IDE_BASEADR<1> | 1 | NULL | 0 | NULL | 0
+FBPIN | 17 | ROM_B_0_OBUF | 1 | NULL | 0 | ROM_B<1> | 1 | 69 | 49152
+FBPIN | 18 | IDE_BASEADR<0> | 1 | NULL | 0 | NULL | 0
+
+FB_INSTANCE | FOOBAR6_ | LAN_IDE_CP_COPY_0_COPY_0 | 0 | 0 | 0
+FBPIN | 16 | EXP22_ | 1 | NULL | 0 | NULL | 0 | 117 | 49152
+FBPIN | 17 | D<15>_BUFR.MC | 1 | NULL | 0 | NULL | 0 | 125 | 49152
+FBPIN | 18 | EXP23_ | 1 | NULL | 0 | NULL | 0
+
+FB_INSTANCE | FOOBAR7_ | LAN_IDE_CP_COPY_0_COPY_0 | 0 | 0 | 0
+FBPIN | 3 | NULL | 0 | AUTOBOOT_OFF_IBUF | 1 | NULL | 0 | 75 | 49152
+FBPIN | 9 | NULL | 0 | AS_IBUF | 1 | NULL | 0 | 80 | 49152
+FBPIN | 12 | ROM_B_0_OBUF$BUF1 | 1 | NULL | 0 | DTACK | 1 | 85 | 49152
+FBPIN | 13 | NULL | 0 | UDS_IBUF | 1 | NULL | 0 | 81 | 49152
+FBPIN | 14 | NULL | 0 | A_23_IBUF | 1 | NULL | 0 | 86 | 49152
+FBPIN | 15 | NULL | 0 | A_22_IBUF | 1 | NULL | 0 | 87 | 49152
+FBPIN | 16 | NULL | 0 | RW_IBUF | 1 | NULL | 0 | 83 | 49152
+FBPIN | 17 | NULL | 0 | A_21_IBUF | 1 | NULL | 0 | 88 | 49152
+
+FB_INSTANCE | FOOBAR8_ | LAN_IDE_CP_COPY_0_COPY_0 | 0 | 0 | 0
+FBPIN | 2 | NULL | 0 | A_20_IBUF | 1 | NULL | 0 | 91 | 49152
+FBPIN | 3 | NULL | 0 | A_17_IBUF | 1 | NULL | 0 | 95 | 49152
+FBPIN | 4 | NULL | 0 | A_16_IBUF | 1 | NULL | 0 | 97 | 49152
+FBPIN | 5 | NULL | 0 | A_19_IBUF | 1 | NULL | 0 | 92 | 49152
+FBPIN | 8 | NULL | 0 | A_18_IBUF | 1 | NULL | 0 | 94 | 49152
+FBPIN | 11 | NULL | 0 | BERR_IBUF | 1 | NULL | 0 | 98 | 49152
+FBPIN | 13 | NULL | 0 | C1_IBUF | 1 | NULL | 0 | 103 | 49152
+FBPIN | 14 | NULL | 0 | C3_IBUF | 1 | NULL | 0 | 102 | 49152
+
+FB_INSTANCE | INPUTPINS_FOOBAR9_ | LAN_IDE_CP_COPY_0_COPY_0 | 0 | 0 | 0
+
+BUSINFO | A<23:1> | 23 | 0 | 0 | A<10> | 13 | A<11> | 12 | A<12> | 11 | A<13> | 10 | A<14> | 9 | A<15> | 8 | A<16> | 7 | A<17> | 6 | A<18> | 5 | A<19> | 4 | A<1> | 22 | A<20> | 3 | A<21> | 2 | A<22> | 1 | A<23> | 0 | A<2> | 21 | A<3> | 20 | A<4> | 19 | A<5> | 18 | A<6> | 17 | A<7> | 16 | A<8> | 15 | A<9> | 14
+BUSINFO | D<15:0> | 16 | 0 | 2 | D<0> | 15 | D<10> | 5 | D<11> | 4 | D<12> | 3 | D<13> | 2 | D<14> | 1 | D<15> | 0 | D<1> | 14 | D<2> | 13 | D<3> | 12 | D<4> | 11 | D<5> | 10 | D<6> | 9 | D<7> | 8 | D<8> | 7 | D<9> | 6
+BUSINFO | DQ<15:0> | 16 | 0 | 0 | DQ<0> | 15 | DQ<10> | 5 | DQ<11> | 4 | DQ<12> | 3 | DQ<13> | 2 | DQ<14> | 1 | DQ<15> | 0 | DQ<1> | 14 | DQ<2> | 13 | DQ<3> | 12 | DQ<4> | 11 | DQ<5> | 10 | DQ<6> | 9 | DQ<7> | 8 | DQ<8> | 7 | DQ<9> | 6
+BUSINFO | IDE_A<2:0> | 3 | 0 | 1 | IDE_A<0> | 2 | IDE_A<1> | 1 | IDE_A<2> | 0
+BUSINFO | IDE_CS<1:0> | 2 | 0 | 1 | IDE_CS<0> | 1 | IDE_CS<1> | 0
+BUSINFO | ROM_B<1:0> | 2 | 0 | 1 | ROM_B<0> | 1 | ROM_B<1> | 0
+
+FB_ORDER_OF_INPUTS | FOOBAR1_ | 0 | RESET | 143 | 1 | AS | 80 | 3 | Dout1<0>.UIM | NULL | 6 | AUTOCONFIG_IN_PROGRESS | NULL | 7 | AUTO_CONFIG_DONE<2> | NULL
+FB_ORDER_OF_INPUTS | FOOBAR1_ | 12 | RW | 83 | 13 | AUTOBOOT_OFF | 75 | 14 | A<12> | 61 | 19 | A<10> | 59 | 20 | ide | NULL
+FB_ORDER_OF_INPUTS | FOOBAR1_ | 21 | AUTO_CONFIG_DONE<0> | NULL | 22 | A<6> | 51 | 24 | A<2> | 54 | 27 | A<4> | 50 | 28 | autoconfig | NULL
+FB_ORDER_OF_INPUTS | FOOBAR1_ | 32 | A<9> | 58 | 35 | AUTO_CONFIG_DONE<1> | NULL | 36 | A<5> | 49 | 38 | A<1> | 57 | 40 | A<13> | 64
+FB_ORDER_OF_INPUTS | FOOBAR1_ | 47 | A<3> | 52 | 50 | ide/ide_CLKF.UIM | NULL | 51 | IDE_ENABLE | NULL | 53 | A<11> | 60
+
+FB_IMUX_INDEX | FOOBAR1_ | 176 | 227 | -1 | 39 | -1 | -1 | 6 | 25 | -1 | -1 | -1 | -1 | 221 | 239 | 257 | -1 | -1 | -1 | -1 | 263 | 54 | 26 | 274 | -1 | 273 | -1 | -1 | 272 | 70 | -1 | -1 | -1 | 267 | -1 | -1 | 50 | 268 | -1 | 269 | -1 | 255 | -1 | -1 | -1 | -1 | -1 | -1 | 276 | -1 | -1 | 69 | 9 | -1 | 259
+
+
+FB_ORDER_OF_INPUTS | FOOBAR2_ | 0 | RESET | 143 | 1 | AS | 80 | 2 | D<14> | 46 | 4 | D<15> | 48 | 6 | AUTOCONFIG_IN_PROGRESS | NULL
+FB_ORDER_OF_INPUTS | FOOBAR2_ | 7 | AUTO_CONFIG_DONE<2> | NULL | 9 | AUTO_CONFIG_DONE_CYCLE<2> | NULL | 10 | AUTO_CONFIG_DONE_CYCLE<0> | NULL | 11 | IDE_BASEADR<7> | NULL | 12 | RW | 83
+FB_ORDER_OF_INPUTS | FOOBAR2_ | 16 | UDS | 81 | 21 | AUTO_CONFIG_DONE<0> | NULL | 22 | A<6> | 51 | 23 | Dout1<2>.UIM | NULL | 24 | A<2> | 54
+FB_ORDER_OF_INPUTS | FOOBAR2_ | 27 | A<4> | 50 | 28 | autoconfig | NULL | 34 | Dout1<1>.UIM | NULL | 35 | AUTO_CONFIG_DONE<1> | NULL | 36 | A<5> | 49
+FB_ORDER_OF_INPUTS | FOOBAR2_ | 38 | A<1> | 57 | 45 | IDE_BASEADR<6> | NULL | 47 | A<3> | 52 | 50 | ide/ide_CLKF.UIM | NULL
+
+FB_IMUX_INDEX | FOOBAR2_ | 176 | 227 | 262 | -1 | 264 | -1 | 6 | 25 | -1 | 27 | 28 | 29 | 221 | -1 | -1 | -1 | 225 | -1 | -1 | -1 | -1 | 26 | 274 | 42 | 273 | -1 | -1 | 272 | 70 | -1 | -1 | -1 | -1 | -1 | 47 | 50 | 268 | -1 | 269 | -1 | -1 | -1 | -1 | -1 | -1 | 30 | -1 | 276 | -1 | -1 | 69 | -1 | -1 | -1
+
+
+FB_ORDER_OF_INPUTS | FOOBAR3_ | 0 | RESET | 143 | 1 | AS | 80 | 6 | AUTOCONFIG_IN_PROGRESS | NULL | 11 | D<10> | 41 | 12 | RW | 83
+FB_ORDER_OF_INPUTS | FOOBAR3_ | 16 | UDS | 81 | 17 | IDE_BASEADR<2> | NULL | 18 | D<11> | 43 | 21 | AUTO_CONFIG_DONE<0> | NULL | 22 | A<6> | 51
+FB_ORDER_OF_INPUTS | FOOBAR3_ | 24 | A<2> | 54 | 26 | D<12>_BUFR | NULL | 27 | A<4> | 50 | 28 | autoconfig | NULL | 31 | D<15>_BUFR | NULL
+FB_ORDER_OF_INPUTS | FOOBAR3_ | 35 | AUTO_CONFIG_DONE<1> | NULL | 36 | A<5> | 49 | 37 | D<13>_BUFR | NULL | 38 | A<1> | 57 | 47 | A<3> | 52
+FB_ORDER_OF_INPUTS | FOOBAR3_ | 49 | D<14>_BUFR | NULL | 50 | ide/ide_CLKF.UIM | NULL | 52 | AUTO_CONFIG_DONE_CYCLE<1> | NULL | 53 | IDE_BASEADR<3> | NULL
+
+FB_IMUX_INDEX | FOOBAR3_ | 176 | 227 | -1 | -1 | -1 | -1 | 6 | -1 | -1 | -1 | -1 | 254 | 221 | -1 | -1 | -1 | 225 | 53 | 256 | -1 | -1 | 26 | 274 | -1 | 273 | -1 | 17 | 272 | 70 | -1 | -1 | 106 | -1 | -1 | -1 | 50 | 268 | 32 | 269 | -1 | -1 | -1 | -1 | -1 | -1 | -1 | -1 | 276 | -1 | 18 | 69 | -1 | 51 | 52
+
+
+FB_ORDER_OF_INPUTS | FOOBAR4_ | 0 | A<19> | 92 | 2 | A<20> | 91 | 6 | A<22> | 87 | 7 | AUTO_CONFIG_DONE<2> | NULL | 11 | IDE_BASEADR<7> | NULL
+FB_ORDER_OF_INPUTS | FOOBAR4_ | 12 | SHUT_UP<1> | NULL | 13 | IDE_BASEADR<5> | NULL | 16 | IDE_BASEADR<3> | NULL | 17 | A<21> | 88 | 21 | AUTO_CONFIG_DONE<0> | NULL
+FB_ORDER_OF_INPUTS | FOOBAR4_ | 22 | IDE_BASEADR<4> | NULL | 23 | C3 | 102 | 26 | IDE_BASEADR<1> | NULL | 27 | A<23> | 86 | 28 | IDE_BASEADR<2> | NULL
+FB_ORDER_OF_INPUTS | FOOBAR4_ | 29 | A<18> | 94 | 34 | BERR | 98 | 35 | AUTO_CONFIG_DONE<1> | NULL | 36 | A<16> | 97 | 44 | IDE_BASEADR<0> | NULL
+FB_ORDER_OF_INPUTS | FOOBAR4_ | 47 | IDE_BASEADR<6> | NULL | 50 | ide/ide_CLKF.UIM | NULL | 51 | A<17> | 95 | 53 | C1 | 103
+
+FB_IMUX_INDEX | FOOBAR4_ | 209 | -1 | 211 | -1 | -1 | -1 | 215 | 25 | -1 | -1 | -1 | 29 | 84 | 85 | -1 | -1 | 52 | 213 | -1 | -1 | -1 | 26 | 86 | 189 | -1 | -1 | 87 | 217 | 53 | 205 | -1 | -1 | -1 | -1 | 197 | 50 | 199 | -1 | -1 | -1 | -1 | -1 | -1 | -1 | 89 | -1 | -1 | 30 | -1 | -1 | 69 | 203 | -1 | 187
+
+
+FB_ORDER_OF_INPUTS | FOOBAR5_ | 0 | RESET | 143 | 1 | AS | 80 | 12 | RW | 83 | 13 | IDE_BASEADR<5> | NULL | 14 | IDE_BASEADR<4> | NULL
+FB_ORDER_OF_INPUTS | FOOBAR5_ | 15 | D<12> | 44 | 16 | UDS | 81 | 19 | SHUT_UP<1> | NULL | 21 | AUTO_CONFIG_DONE<0> | NULL | 22 | A<6> | 51
+FB_ORDER_OF_INPUTS | FOOBAR5_ | 24 | A<2> | 54 | 26 | IDE_BASEADR<1> | NULL | 27 | A<4> | 50 | 28 | autoconfig | NULL | 29 | D<13> | 45
+FB_ORDER_OF_INPUTS | FOOBAR5_ | 35 | AUTO_CONFIG_DONE<1> | NULL | 36 | A<5> | 49 | 38 | A<1> | 57 | 44 | IDE_BASEADR<0> | NULL | 46 | D<8> | 19
+FB_ORDER_OF_INPUTS | FOOBAR5_ | 47 | A<3> | 52 | 50 | ide/ide_CLKF.UIM | NULL | 52 | D<9> | 40
+
+FB_IMUX_INDEX | FOOBAR5_ | 176 | 227 | -1 | -1 | -1 | -1 | -1 | -1 | -1 | -1 | -1 | -1 | 221 | 85 | 86 | 258 | 225 | -1 | -1 | 84 | -1 | 26 | 274 | -1 | 273 | -1 | 87 | 272 | 70 | 260 | -1 | -1 | -1 | -1 | -1 | 50 | 268 | -1 | 269 | -1 | -1 | -1 | -1 | -1 | 89 | -1 | 212 | 276 | -1 | -1 | 69 | -1 | 252 | -1
+
+
+FB_ORDER_OF_INPUTS | FOOBAR6_ | 0 | RESET | 143 | 1 | AS | 80 | 7 | AUTO_CONFIG_DONE<2> | NULL | 12 | RW | 83 | 18 | Dout1<3>.UIM | NULL
+FB_ORDER_OF_INPUTS | FOOBAR6_ | 21 | AUTO_CONFIG_DONE<0> | NULL | 22 | A<6> | 51 | 24 | A<2> | 54 | 27 | A<4> | 50 | 28 | autoconfig | NULL
+FB_ORDER_OF_INPUTS | FOOBAR6_ | 35 | AUTO_CONFIG_DONE<1> | NULL | 36 | A<5> | 49 | 38 | A<1> | 57 | 47 | A<3> | 52 | 50 | ide/ide_CLKF.UIM | NULL
+
+FB_IMUX_INDEX | FOOBAR6_ | 176 | 227 | -1 | -1 | -1 | -1 | -1 | 25 | -1 | -1 | -1 | -1 | 221 | -1 | -1 | -1 | -1 | -1 | 45 | -1 | -1 | 26 | 274 | -1 | 273 | -1 | -1 | 272 | 70 | -1 | -1 | -1 | -1 | -1 | -1 | 50 | 268 | -1 | 269 | -1 | -1 | -1 | -1 | -1 | -1 | -1 | -1 | 276 | -1 | -1 | 69 | -1 | -1 | -1
+
+
+GLOBAL_FSR | RESET | 0 | 0
diff --git a/Logic/LAN_IDE/LAN_IDE_CP.xml b/Logic/LAN_IDE/LAN_IDE_CP.xml
new file mode 100644
index 0000000..1b59ec2
--- /dev/null
+++ b/Logic/LAN_IDE/LAN_IDE_CP.xml
@@ -0,0 +1,3 @@
+<?xml version='1.0' encoding='utf-8' ?>
+<!DOCTYPE document SYSTEM "file:///C:/Xilinx/14.6/ISE_DS/ISE/xc9500xl/data/xmlReport9kxl.dtd">
+<document><ascFile>LAN_IDE_CP.rpt</ascFile><devFile>C:/Xilinx/14.6/ISE_DS/ISE/xc9500xl/data/xc95144xl.chp</devFile><mfdFile>LAN_IDE_CP.mfd</mfdFile><htmlFile logic_legend="logiclegend.htm" logo="xc9500xl_logo.jpg" pin_legend="pinlegend.htm"/><header date="12-15-2016" design="LAN_IDE_CP" device="XC95144XL" eqnType="1" pkg="TQ144" speed="-10" status="1" statusStr="Successful" swVersion="P.68d" time="  7:48PM" version="1.0"/><inputs id="RW" userloc="P83"/><inputs id="A1_SPECSIG" userloc="P57"/><inputs id="A2_SPECSIG" userloc="P54"/><inputs id="A5_SPECSIG" userloc="P49"/><inputs id="A6_SPECSIG" userloc="P51"/><inputs id="A3_SPECSIG" userloc="P52"/><inputs id="AS" userloc="P80"/><inputs id="A4_SPECSIG" userloc="P50"/><inputs id="AUTOBOOT_OFF" userloc="P75"/><inputs id="UDS" userloc="P81"/><inputs id="A23_SPECSIG" userloc="P86"/><inputs id="A22_SPECSIG" userloc="P87"/><inputs id="A21_SPECSIG" userloc="P88"/><inputs id="A19_SPECSIG" userloc="P92"/><inputs id="D8PIN_SPECSIG" userloc="P19"/><inputs id="D12PIN_SPECSIG" userloc="P44"/><inputs id="D13PIN_SPECSIG" userloc="P45"/><inputs id="D9PIN_SPECSIG" userloc="P40"/><inputs id="D10PIN_SPECSIG" userloc="P41"/><inputs id="D11PIN_SPECSIG" userloc="P43"/><inputs id="D14PIN_SPECSIG" userloc="P46"/><inputs id="D15PIN_SPECSIG" userloc="P48"/><inputs id="BERR" userloc="P98"/><inputs id="C1" userloc="P103"/><inputs id="C3" userloc="P102"/><inputs id="A16_SPECSIG" userloc="P97"/><inputs id="A20_SPECSIG" userloc="P91"/><inputs id="A17_SPECSIG" userloc="P95"/><inputs id="A18_SPECSIG" userloc="P94"/><inputs id="A9_SPECSIG" userloc="P58"/><inputs id="A10_SPECSIG" userloc="P59"/><inputs id="A11_SPECSIG" userloc="P60"/><inputs id="A12_SPECSIG" userloc="P61"/><inputs id="A13_SPECSIG" userloc="P64"/><global_inputs id="RESET" pinnum="GSR" use="GSR" userloc="P143"/><pin id="FB1_MC1_PIN23" pinnum="23" signal="IDE_CS1_SPECSIG" use="O"/><pin id="FB1_MC2_PIN16" pinnum="16" signal="D7_SPECSIG" use="O"/><pin id="FB1_MC3_PIN17" pinnum="17" signal="D1_SPECSIG" use="O"/><pin id="FB1_MC4_PIN25" pinnum="25" signal="IDE_A2_SPECSIG" use="O"/><pin id="FB1_MC5_PIN19" pinnum="19" signal="D8_SPECSIG" use="IO_SPECSIG"/><pin id="FB1_MC6_PIN20" pinnum="20" signal="D5_SPECSIG" use="O"/><pin id="FB1_MC8_PIN21" pinnum="21" signal="D4_SPECSIG" use="O"/><pin id="FB1_MC9_PIN22" pinnum="22" signal="IDE_CS0_SPECSIG" use="O"/><pin id="FB1_MC10_PIN31" pinnum="31" signal="IDE_ENABLE" use="b_SPECSIG"/><pin id="FB1_MC11_PIN24" pinnum="24" signal="IDE_A0_SPECSIG" use="O"/><pin id="FB1_MC12_PIN26" pinnum="26" signal="IDE_A1_SPECSIG" use="O"/><pin id="FB1_MC14_PIN27" pinnum="27" signal="IDE_R" use="O"/><pin id="FB1_MC15_PIN28" pinnum="28" signal="IDE_W" use="O"/><pin id="FB1_MC16_PIN35" pinnum="35" signal="ROM_OE" use="O"/><pin id="FB1_MC17_PIN30" pinnum="30" use="b_SPECSIG"/><pin id="FB2_MC1_PIN142" pinnum="142" signal="D14_BUFR_SPECSIG" use="b_SPECSIG"/><pin id="FB2_MC2_PIN143" pinnum="143" signal="RESET" use="GSRI_SPECSIG"/><pin id="FB2_MC4_PIN4" pinnum="4"/><pin id="FB2_MC5_PIN2" pinnum="2" signal="D0_SPECSIG" use="O"/><pin id="FB2_MC6_PIN3" pinnum="3"/><pin id="FB2_MC8_PIN5" pinnum="5" signal="AUTO_CONFIG_DONE2_SPECSIG" use="b_SPECSIG"/><pin id="FB2_MC9_PIN6" pinnum="6" signal="AUTO_CONFIG_DONE0_SPECSIG" use="b_SPECSIG"/><pin id="FB2_MC10_PIN7" pinnum="7" signal="AUTO_CONFIG_DONE_CYCLE2_SPECSIG" use="b_SPECSIG"/><pin id="FB2_MC11_PIN9" pinnum="9" signal="AUTO_CONFIG_DONE_CYCLE0_SPECSIG" use="b_SPECSIG"/><pin id="FB2_MC12_PIN10" pinnum="10" signal="IDE_BASEADR7_SPECSIG" use="b_SPECSIG"/><pin id="FB2_MC13_PIN12" pinnum="12" signal="IDE_BASEADR6_SPECSIG" use="b_SPECSIG"/><pin id="FB2_MC14_PIN11" pinnum="11" use="b_SPECSIG"/><pin id="FB2_MC15_PIN13" pinnum="13" signal="D13_BUFR_SPECSIG" use="b_SPECSIG"/><pin id="FB2_MC16_PIN14" pinnum="14" signal="D6_SPECSIG" use="O"/><pin id="FB2_MC17_PIN15" pinnum="15" signal="D3_SPECSIG" use="O"/><pin id="FB3_MC1_PIN39" pinnum="39" signal="D2_SPECSIG" use="O"/><pin id="FB3_MC2_PIN32" pinnum="32"/><pin id="FB3_MC3_PIN41" pinnum="41" signal="D10_SPECSIG" use="IO_SPECSIG"/><pin id="FB3_MC4_PIN44" pinnum="44" signal="D12_SPECSIG" use="IO_SPECSIG"/><pin id="FB3_MC5_PIN33" pinnum="33"/><pin id="FB3_MC6_PIN34" pinnum="34"/><pin id="FB3_MC7_PIN46" pinnum="46" signal="D14_SPECSIG" use="IO_SPECSIG"/><pin id="FB3_MC8_PIN38" pinnum="38"/><pin id="FB3_MC9_PIN40" pinnum="40" signal="D9_SPECSIG" use="IO_SPECSIG"/><pin id="FB3_MC10_PIN48" pinnum="48" signal="D15_SPECSIG" use="IO_SPECSIG"/><pin id="FB3_MC11_PIN43" pinnum="43" signal="D11_SPECSIG" use="IO_SPECSIG"/><pin id="FB3_MC12_PIN45" pinnum="45" signal="D13_SPECSIG" use="IO_SPECSIG"/><pin id="FB3_MC14_PIN49" pinnum="49" signal="A5_SPECSIG" use="I"/><pin id="FB3_MC15_PIN50" pinnum="50" signal="A4_SPECSIG" use="I"/><pin id="FB3_MC17_PIN51" pinnum="51" signal="A6_SPECSIG" use="I"/><pin id="FB4_MC1_PIN118" pinnum="118" signal="ide" use="b_SPECSIG"/><pin id="FB4_MC2_PIN126" pinnum="126" use="b_SPECSIG"/><pin id="FB4_MC3_PIN133" pinnum="133" use="b_SPECSIG"/><pin id="FB4_MC5_PIN128" pinnum="128"/><pin id="FB4_MC6_PIN129" pinnum="129"/><pin id="FB4_MC8_PIN130" pinnum="130"/><pin id="FB4_MC9_PIN131" pinnum="131"/><pin id="FB4_MC10_PIN135" pinnum="135"/><pin id="FB4_MC11_PIN132" pinnum="132"/><pin id="FB4_MC12_PIN134" pinnum="134"/><pin id="FB4_MC13_PIN137" pinnum="137"/><pin id="FB4_MC14_PIN136" pinnum="136"/><pin id="FB4_MC15_PIN138" pinnum="138"/><pin id="FB4_MC16_PIN139" pinnum="139" signal="ideide_CLKF_SPECSIG" use="b_SPECSIG"/><pin id="FB4_MC17_PIN140" pinnum="140" signal="autoconfig" use="b_SPECSIG"/><pin id="FB5_MC2_PIN52" pinnum="52" signal="A3_SPECSIG" use="I"/><pin id="FB5_MC3_PIN59" pinnum="59" signal="A10_SPECSIG" use="I"/><pin id="FB5_MC5_PIN53" pinnum="53"/><pin id="FB5_MC6_PIN54" pinnum="54" signal="A2_SPECSIG" use="I"/><pin id="FB5_MC7_PIN66" pinnum="66"/><pin id="FB5_MC8_PIN56" pinnum="56"/><pin id="FB5_MC9_PIN57" pinnum="57" signal="A1_SPECSIG" use="I"/><pin id="FB5_MC10_PIN68" pinnum="68" signal="ROM_B0_SPECSIG" use="O"/><pin id="FB5_MC11_PIN58" pinnum="58" signal="A9_SPECSIG" use="I"/><pin id="FB5_MC12_PIN60" pinnum="60" signal="A11_SPECSIG" use="I"/><pin id="FB5_MC13_PIN70" pinnum="70" signal="SHUT_UP1_SPECSIG" use="b_SPECSIG"/><pin id="FB5_MC14_PIN61" pinnum="61" signal="A12_SPECSIG" use="I"/><pin id="FB5_MC15_PIN64" pinnum="64" signal="A13_SPECSIG" use="I"/><pin id="FB5_MC17_PIN69" pinnum="69" signal="ROM_B1_SPECSIG" use="O"/><pin id="FB6_MC2_PIN106" pinnum="106"/><pin id="FB6_MC4_PIN111" pinnum="111"/><pin id="FB6_MC5_PIN110" pinnum="110"/><pin id="FB6_MC6_PIN112" pinnum="112"/><pin id="FB6_MC8_PIN113" pinnum="113"/><pin id="FB6_MC9_PIN116" pinnum="116"/><pin id="FB6_MC10_PIN115" pinnum="115"/><pin id="FB6_MC11_PIN119" pinnum="119"/><pin id="FB6_MC12_PIN120" pinnum="120"/><pin id="FB6_MC14_PIN121" pinnum="121"/><pin id="FB6_MC15_PIN124" pinnum="124"/><pin id="FB6_MC16_PIN117" pinnum="117" use="b_SPECSIG"/><pin id="FB6_MC17_PIN125" pinnum="125" signal="D15_BUFR_SPECSIG" use="b_SPECSIG"/><pin id="FB7_MC2_PIN71" pinnum="71"/><pin id="FB7_MC3_PIN75" pinnum="75" signal="AUTOBOOT_OFF" use="I"/><pin id="FB7_MC5_PIN74" pinnum="74"/><pin id="FB7_MC6_PIN76" pinnum="76"/><pin id="FB7_MC7_PIN77" pinnum="77"/><pin id="FB7_MC8_PIN78" pinnum="78"/><pin id="FB7_MC9_PIN80" pinnum="80" signal="AS" use="I"/><pin id="FB7_MC10_PIN79" pinnum="79"/><pin id="FB7_MC11_PIN82" pinnum="82"/><pin id="FB7_MC12_PIN85" pinnum="85" signal="DTACK" use="O"/><pin id="FB7_MC13_PIN81" pinnum="81" signal="UDS" use="I"/><pin id="FB7_MC14_PIN86" pinnum="86" signal="A23_SPECSIG" use="I"/><pin id="FB7_MC15_PIN87" pinnum="87" signal="A22_SPECSIG" use="I"/><pin id="FB7_MC16_PIN83" pinnum="83" signal="RW" use="I"/><pin id="FB7_MC17_PIN88" pinnum="88" signal="A21_SPECSIG" use="I"/><pin id="FB8_MC2_PIN91" pinnum="91" signal="A20_SPECSIG" use="I"/><pin id="FB8_MC3_PIN95" pinnum="95" signal="A17_SPECSIG" use="I"/><pin id="FB8_MC4_PIN97" pinnum="97" signal="A16_SPECSIG" use="I"/><pin id="FB8_MC5_PIN92" pinnum="92" signal="A19_SPECSIG" use="I"/><pin id="FB8_MC6_PIN93" pinnum="93"/><pin id="FB8_MC8_PIN94" pinnum="94" signal="A18_SPECSIG" use="I"/><pin id="FB8_MC9_PIN96" pinnum="96"/><pin id="FB8_MC10_PIN101" pinnum="101"/><pin id="FB8_MC11_PIN98" pinnum="98" signal="BERR" use="I"/><pin id="FB8_MC12_PIN100" pinnum="100"/><pin id="FB8_MC13_PIN103" pinnum="103" signal="C1" use="I"/><pin id="FB8_MC14_PIN102" pinnum="102" signal="C3" use="I"/><pin id="FB8_MC15_PIN104" pinnum="104"/><pin id="FB8_MC16_PIN107" pinnum="107"/><pin id="FB8_MC17_PIN105" pinnum="105"/><fblock id="FB1" inputUse="24" pinUse="13"><macrocell id="FB1_MC1" pin="FB1_MC1_PIN23" sigUse="1" signal="IDE_CS1_SPECSIG"><pterms pt1="FB1_1_1" pt2="FB1_1_2" pt3="FB1_1_3" pt4="FB1_1_4" pt5="FB1_1_5"/></macrocell><macrocell id="FB1_MC2" pin="FB1_MC2_PIN16" sigUse="2" signal="D7_SPECSIG"><pterms pt1="FB1_2_1" pt2="FB1_2_2"/></macrocell><macrocell id="FB1_MC3" pin="FB1_MC3_PIN17" sigUse="2" signal="D1_SPECSIG"><pterms pt1="FB1_3_1"/></macrocell><macrocell id="FB1_MC4" pin="FB1_MC4_PIN25" sigUse="1" signal="IDE_A2_SPECSIG"><pterms pt1="FB1_4_1"/></macrocell><macrocell id="FB1_MC5" pin="FB1_MC5_PIN19" sigUse="2" signal="D8_SPECSIG"><pterms pt1="FB1_5_1"/></macrocell><macrocell id="FB1_MC6" pin="FB1_MC6_PIN20" sigUse="2" signal="D5_SPECSIG"><pterms pt1="FB1_6_1"/></macrocell><macrocell id="FB1_MC7" sigUse="3" signal="AUTOCONFIG_IN_PROGRESS"><pterms pt1="FB1_7_1" pt2="FB1_7_2"/></macrocell><macrocell id="FB1_MC8" pin="FB1_MC8_PIN21" sigUse="2" signal="D4_SPECSIG"><pterms pt1="FB1_8_1"/></macrocell><macrocell id="FB1_MC9" pin="FB1_MC9_PIN22" sigUse="1" signal="IDE_CS0_SPECSIG"><pterms pt1="FB1_9_1"/></macrocell><macrocell id="FB1_MC10" pin="FB1_MC10_PIN31" sigUse="6" signal="IDE_ENABLE"><pterms pt1="FB1_10_1" pt2="FB1_10_2" pt3="FB1_10_3"/></macrocell><macrocell id="FB1_MC11" pin="FB1_MC11_PIN24" sigUse="1" signal="IDE_A0_SPECSIG"><pterms pt1="FB1_11_1"/></macrocell><macrocell id="FB1_MC12" pin="FB1_MC12_PIN26" sigUse="1" signal="IDE_A1_SPECSIG"><pterms pt1="FB1_12_1"/></macrocell><macrocell id="FB1_MC13"/><macrocell id="FB1_MC14" pin="FB1_MC14_PIN27" sigUse="6" signal="IDE_R"><pterms pt1="FB1_14_1" pt2="FB1_14_2"/></macrocell><macrocell id="FB1_MC15" pin="FB1_MC15_PIN28" sigUse="5" signal="IDE_W"><pterms pt1="FB1_15_1" pt2="FB1_15_2" pt3="FB1_15_3"/></macrocell><macrocell id="FB1_MC16" pin="FB1_MC16_PIN35" sigUse="6" signal="ROM_OE"><pterms pt1="FB1_16_1" pt2="FB1_16_2" pt3="FB1_16_3" pt4="FB1_16_4" pt5="FB1_16_5"/></macrocell><macrocell id="FB1_MC17" pin="FB1_MC17_PIN30"><pterms pt1="FB1_17_1" pt2="FB1_17_2" pt3="FB1_17_3" pt4="FB1_17_4" pt5="FB1_17_5"/></macrocell><macrocell id="FB1_MC18" sigUse="16" signal="D12_BUFR_SPECSIG"><pterms pt1="FB1_18_1" pt2="FB1_18_2" pt3="FB1_18_3" pt4="FB1_18_4" pt5="FB1_18_5"/></macrocell><fbinput id="FB1_I1" signal="AS"/><fbinput id="FB1_I2" signal="AUTOBOOT_OFF"/><fbinput id="FB1_I3" signal="AUTOCONFIG_IN_PROGRESS"/><fbinput id="FB1_I4" signal="AUTO_CONFIG_DONE0_SPECSIG"/><fbinput id="FB1_I5" signal="AUTO_CONFIG_DONE1_SPECSIG"/><fbinput id="FB1_I6" signal="AUTO_CONFIG_DONE2_SPECSIG"/><fbinput id="FB1_I7" signal="A12_SPECSIG"/><fbinput id="FB1_I8" signal="A13_SPECSIG"/><fbinput id="FB1_I9" signal="A1_SPECSIG"/><fbinput id="FB1_I10" signal="A2_SPECSIG"/><fbinput id="FB1_I11" signal="A3_SPECSIG"/><fbinput id="FB1_I12" signal="A4_SPECSIG"/><fbinput id="FB1_I13" signal="A5_SPECSIG"/><fbinput id="FB1_I14" signal="A6_SPECSIG"/><fbinput id="FB1_I15" signal="D12_SPECSIG"/><fbinput id="FB1_I16" signal="A9_SPECSIG"/><fbinput id="FB1_I17" signal="A10_SPECSIG"/><fbinput id="FB1_I18" signal="A11_SPECSIG"/><fbinput id="FB1_I19" signal="IDE_ENABLE"/><fbinput id="FB1_I20" signal="RESET"/><fbinput id="FB1_I21" signal="RW"/><fbinput id="FB1_I22" signal="autoconfig"/><fbinput id="FB1_I23" signal="ide"/><fbinput id="FB1_I24" signal="ideide_CLKF_SPECSIG"/><pterm id="FB1_1_1"><signal id="RESET"/><signal id="RW"/><signal id="AS" negated="ON"/><signal id="A5_SPECSIG" negated="ON"/><signal id="A4_SPECSIG" negated="ON"/><signal id="A6_SPECSIG"/><signal id="A3_SPECSIG" negated="ON"/><signal id="A2_SPECSIG" negated="ON"/><signal id="AUTO_CONFIG_DONE0_SPECSIG" negated="ON"/><signal id="autoconfig"/></pterm><pterm id="FB1_1_2"><signal id="RESET"/><signal id="RW"/><signal id="AS" negated="ON"/><signal id="A5_SPECSIG" negated="ON"/><signal id="A4_SPECSIG" negated="ON"/><signal id="A6_SPECSIG"/><signal id="A3_SPECSIG" negated="ON"/><signal id="A2_SPECSIG" negated="ON"/><signal id="AUTO_CONFIG_DONE1_SPECSIG" negated="ON"/><signal id="autoconfig"/></pterm><pterm id="FB1_1_3"><signal id="RESET"/><signal id="RW"/><signal id="AS" negated="ON"/><signal id="A5_SPECSIG" negated="ON"/><signal id="A4_SPECSIG" negated="ON"/><signal id="A6_SPECSIG"/><signal id="A3_SPECSIG" negated="ON"/><signal id="A2_SPECSIG" negated="ON"/><signal id="AUTO_CONFIG_DONE2_SPECSIG" negated="ON"/><signal id="autoconfig"/></pterm><pterm id="FB1_1_4"><signal id="RESET"/><signal id="RW"/><signal id="AS" negated="ON"/><signal id="A5_SPECSIG" negated="ON"/><signal id="A1_SPECSIG" negated="ON"/><signal id="A6_SPECSIG" negated="ON"/><signal id="A3_SPECSIG" negated="ON"/><signal id="A2_SPECSIG"/><signal id="AUTO_CONFIG_DONE0_SPECSIG" negated="ON"/><signal id="autoconfig"/></pterm><pterm id="FB1_1_5"><signal id="RESET"/><signal id="RW"/><signal id="AS" negated="ON"/><signal id="A5_SPECSIG"/><signal id="A4_SPECSIG" negated="ON"/><signal id="A1_SPECSIG"/><signal id="A6_SPECSIG" negated="ON"/><signal id="A2_SPECSIG"/><signal id="AUTO_CONFIG_DONE0_SPECSIG"/><signal id="AUTO_CONFIG_DONE1_SPECSIG" negated="ON"/><signal id="autoconfig"/></pterm><pterm id="FB1_2_1"><signal id="RW"/><signal id="AUTOCONFIG_IN_PROGRESS"/></pterm><pterm id="FB1_2_2"><signal id="A13_SPECSIG" negated="ON"/></pterm><pterm id="FB1_3_1"><signal id="RW"/><signal id="AUTOCONFIG_IN_PROGRESS"/></pterm><pterm id="FB1_4_1"><signal id="A11_SPECSIG"/></pterm><pterm id="FB1_5_1"><signal id="RW"/><signal id="AUTOCONFIG_IN_PROGRESS"/></pterm><pterm id="FB1_6_1"><signal id="RW"/><signal id="AUTOCONFIG_IN_PROGRESS"/></pterm><pterm id="FB1_7_1"><signal id="AS" negated="ON"/><signal id="autoconfig"/></pterm><pterm id="FB1_7_2"><signal id="ideide_CLKF_SPECSIG"/></pterm><pterm id="FB1_8_1"><signal id="RW"/><signal id="AUTOCONFIG_IN_PROGRESS"/></pterm><pterm id="FB1_9_1"><signal id="A12_SPECSIG" negated="ON"/></pterm><pterm id="FB1_10_1"><signal id="RESET"/><signal id="IDE_ENABLE" negated="ON"/></pterm><pterm id="FB1_10_2"><signal id="RESET"/><signal id="RW" negated="ON"/><signal id="AS" negated="ON"/><signal id="ide"/></pterm><pterm id="FB1_10_3"><signal id="ideide_CLKF_SPECSIG"/></pterm><pterm id="FB1_11_1"><signal id="A9_SPECSIG"/></pterm><pterm id="FB1_12_1"><signal id="A10_SPECSIG"/></pterm><pterm id="FB1_14_1"><signal id="RESET"/><signal id="RW"/><signal id="AS" negated="ON"/><signal id="IDE_ENABLE" negated="ON"/><signal id="ide"/></pterm><pterm id="FB1_14_2"><signal id="ideide_CLKF_SPECSIG"/></pterm><pterm id="FB1_15_1"><signal id="RESET"/><signal id="RW" negated="ON"/><signal id="AS" negated="ON"/><signal id="ide"/></pterm><pterm id="FB1_15_2"><signal id="ideide_CLKF_SPECSIG"/></pterm><pterm id="FB1_15_3"><signal id="RESET"/><signal id="RW"/><signal id="AS" negated="ON"/><signal id="IDE_ENABLE"/><signal id="ide"/></pterm><pterm id="FB1_16_1"><signal id="ideide_CLKF_SPECSIG"/></pterm><pterm id="FB1_16_2"><signal id="RESET"/><signal id="RW"/><signal id="AS" negated="ON"/><signal id="A5_SPECSIG"/><signal id="A4_SPECSIG" negated="ON"/><signal id="A1_SPECSIG"/><signal id="A6_SPECSIG" negated="ON"/><signal id="A3_SPECSIG" negated="ON"/><signal id="A2_SPECSIG"/><signal id="AUTO_CONFIG_DONE2_SPECSIG" negated="ON"/><signal id="autoconfig"/></pterm><pterm id="FB1_16_3"><signal id="RESET"/><signal id="RW"/><signal id="AS" negated="ON"/><signal id="A5_SPECSIG"/><signal id="A4_SPECSIG" negated="ON"/><signal id="A6_SPECSIG" negated="ON"/><signal id="A3_SPECSIG" negated="ON"/><signal id="A2_SPECSIG"/><signal id="AUTO_CONFIG_DONE0_SPECSIG"/><signal id="AUTO_CONFIG_DONE1_SPECSIG" negated="ON"/><signal id="autoconfig"/></pterm><pterm id="FB1_16_4"><signal id="RESET"/><signal id="RW"/><signal id="AS" negated="ON"/><signal id="A5_SPECSIG" negated="ON"/><signal id="A4_SPECSIG"/><signal id="A1_SPECSIG"/><signal id="A6_SPECSIG" negated="ON"/><signal id="A3_SPECSIG"/><signal id="AUTO_CONFIG_DONE0_SPECSIG"/><signal id="AUTO_CONFIG_DONE1_SPECSIG" negated="ON"/><signal id="autoconfig"/></pterm><pterm id="FB1_16_5"><signal id="RESET"/><signal id="RW"/><signal id="AS" negated="ON"/><signal id="A5_SPECSIG" negated="ON"/><signal id="A1_SPECSIG" negated="ON"/><signal id="A6_SPECSIG" negated="ON"/><signal id="A3_SPECSIG" negated="ON"/><signal id="A2_SPECSIG"/><signal id="AUTO_CONFIG_DONE1_SPECSIG"/><signal id="AUTO_CONFIG_DONE2_SPECSIG" negated="ON"/><signal id="autoconfig"/></pterm><pterm id="FB1_17_1"><signal id="RESET"/><signal id="D12_SPECSIG" negated="ON"/><signal id="RW" negated="ON"/></pterm><pterm id="FB1_17_2"><signal id="RESET"/><signal id="D12_SPECSIG" negated="ON"/><signal id="AS"/></pterm><pterm id="FB1_17_3"><signal id="RESET"/><signal id="D12_SPECSIG" negated="ON"/><signal id="autoconfig" negated="ON"/></pterm><pterm id="FB1_17_4"><signal id="RESET"/><signal id="D12_SPECSIG" negated="ON"/><signal id="AUTO_CONFIG_DONE0_SPECSIG"/><signal id="AUTO_CONFIG_DONE1_SPECSIG"/><signal id="AUTO_CONFIG_DONE2_SPECSIG"/></pterm><pterm id="FB1_17_5"><signal id="RESET"/><signal id="RW"/><signal id="AS" negated="ON"/><signal id="A5_SPECSIG" negated="ON"/><signal id="A4_SPECSIG" negated="ON"/><signal id="A1_SPECSIG" negated="ON"/><signal id="A3_SPECSIG" negated="ON"/><signal id="A2_SPECSIG" negated="ON"/><signal id="AUTO_CONFIG_DONE0_SPECSIG" negated="ON"/><signal id="autoconfig"/></pterm><pterm id="FB1_18_1"><signal id="RESET"/><signal id="RW"/><signal id="AS" negated="ON"/><signal id="A4_SPECSIG" negated="ON"/><signal id="A1_SPECSIG"/><signal id="A6_SPECSIG" negated="ON"/><signal id="A3_SPECSIG" negated="ON"/><signal id="A2_SPECSIG"/><signal id="AUTO_CONFIG_DONE0_SPECSIG" negated="ON"/><signal id="autoconfig"/></pterm><pterm id="FB1_18_2"><signal id="RESET"/><signal id="RW"/><signal id="AS" negated="ON"/><signal id="A5_SPECSIG" negated="ON"/><signal id="A4_SPECSIG"/><signal id="A6_SPECSIG" negated="ON"/><signal id="A3_SPECSIG"/><signal id="A2_SPECSIG" negated="ON"/><signal id="AUTO_CONFIG_DONE0_SPECSIG"/><signal id="AUTO_CONFIG_DONE1_SPECSIG" negated="ON"/><signal id="autoconfig"/></pterm><pterm id="FB1_18_3"><signal id="RESET"/><signal id="RW"/><signal id="AS" negated="ON"/><signal id="A5_SPECSIG" negated="ON"/><signal id="A4_SPECSIG" negated="ON"/><signal id="A1_SPECSIG" negated="ON"/><signal id="A3_SPECSIG" negated="ON"/><signal id="A2_SPECSIG" negated="ON"/><signal id="AUTO_CONFIG_DONE1_SPECSIG"/><signal id="AUTO_CONFIG_DONE2_SPECSIG" negated="ON"/><signal id="autoconfig"/></pterm><pterm id="FB1_18_4"><signal id="RESET"/><signal id="RW"/><signal id="AS" negated="ON"/><signal id="A5_SPECSIG" negated="ON"/><signal id="A4_SPECSIG" negated="ON"/><signal id="A1_SPECSIG" negated="ON"/><signal id="A3_SPECSIG" negated="ON"/><signal id="A2_SPECSIG" negated="ON"/><signal id="AUTO_CONFIG_DONE1_SPECSIG" negated="ON"/><signal id="AUTOBOOT_OFF"/><signal id="autoconfig"/></pterm><pterm id="FB1_18_5"><signal id="ideide_CLKF_SPECSIG"/></pterm><equation id="IDE_CS1_SPECSIG" userloc="P23"><d2><eq_pterm import="1" ptindx="FB1_2_2"/></d2></equation><equation id="D7_SPECSIG" userloc="P16"><d2><eq_pterm ptindx="VCC"/></d2><oe><eq_pterm ptindx="FB1_2_1"/></oe></equation><equation id="D1_SPECSIG" userloc="P17"><d2><eq_pterm ptindx="VCC"/></d2><oe><eq_pterm ptindx="FB1_3_1"/></oe></equation><equation id="IDE_A2_SPECSIG" userloc="P25"><d2><eq_pterm ptindx="FB1_4_1"/></d2></equation><equation id="D8_SPECSIG" userloc="P19"><d2><eq_pterm ptindx="VCC"/></d2><oe><eq_pterm ptindx="FB1_5_1"/></oe></equation><equation id="D5_SPECSIG" userloc="P20"><d2><eq_pterm ptindx="VCC"/></d2><oe><eq_pterm ptindx="FB1_6_1"/></oe></equation><equation id="AUTOCONFIG_IN_PROGRESS" regUse="D"><d2><eq_pterm ptindx="FB1_7_1"/></d2><clk><eq_pterm ptindx="FB1_7_2"/></clk><prld ptindx="GND"/></equation><equation id="D4_SPECSIG" userloc="P21"><d2><eq_pterm ptindx="VCC"/></d2><oe><eq_pterm ptindx="FB1_8_1"/></oe></equation><equation id="IDE_CS0_SPECSIG" userloc="P22"><d2><eq_pterm ptindx="FB1_9_1"/></d2></equation><equation id="IDE_ENABLE" negated="ON" regUse="D"><d2><eq_pterm ptindx="FB1_10_1"/><eq_pterm ptindx="FB1_10_2"/></d2><clk><eq_pterm ptindx="FB1_10_3"/></clk><prld ptindx="GND"/></equation><equation id="IDE_A0_SPECSIG" userloc="P24"><d2><eq_pterm ptindx="FB1_11_1"/></d2></equation><equation id="IDE_A1_SPECSIG" userloc="P26"><d2><eq_pterm ptindx="FB1_12_1"/></d2></equation><equation id="IDE_R" negated="ON" regUse="D" userloc="P27"><d2><eq_pterm ptindx="FB1_14_1"/></d2><clk><eq_pterm ptindx="FB1_14_2"/></clk><prld ptindx="VCC"/></equation><equation id="IDE_W" negated="ON" regUse="D" userloc="P28"><d2><eq_pterm ptindx="FB1_15_1"/></d2><clk><eq_pterm ptindx="FB1_15_2"/></clk><prld ptindx="VCC"/></equation><equation id="ROM_OE" negated="ON" regUse="D" userloc="P35"><d2><eq_pterm import="1" ptindx="FB1_15_3"/></d2><clk><eq_pterm ptindx="FB1_16_1"/></clk><prld ptindx="VCC"/></equation><equation id="D12_BUFR_SPECSIG" negated="ON" regUse="D"><d2><eq_pterm ptindx="FB1_18_1"/><eq_pterm ptindx="FB1_18_2"/><eq_pterm ptindx="FB1_18_3"/><eq_pterm ptindx="FB1_18_4"/><eq_pterm import="1" ptindx="FB1_1_1"/><eq_pterm import="1" ptindx="FB1_1_2"/><eq_pterm import="1" ptindx="FB1_1_3"/><eq_pterm import="1" ptindx="FB1_1_4"/><eq_pterm import="1" ptindx="FB1_1_5"/><eq_pterm import="1" ptindx="FB1_17_1"/><eq_pterm import="1" ptindx="FB1_17_2"/><eq_pterm import="1" ptindx="FB1_17_3"/><eq_pterm import="1" ptindx="FB1_17_4"/><eq_pterm import="1" ptindx="FB1_17_5"/><eq_pterm import="1" ptindx="FB1_16_2"/><eq_pterm import="1" ptindx="FB1_16_3"/><eq_pterm import="1" ptindx="FB1_16_4"/><eq_pterm import="1" ptindx="FB1_16_5"/></d2><clk><eq_pterm ptindx="FB1_18_5"/></clk><prld ptindx="GND"/></equation></fblock><fblock id="FB2" inputUse="24" pinUse="4"><macrocell id="FB2_MC1" pin="FB2_MC1_PIN142" sigUse="15" signal="D14_BUFR_SPECSIG"><pterms pt1="FB2_1_1" pt2="FB2_1_2" pt3="FB2_1_3" pt4="FB2_1_4" pt5="FB2_1_5"/></macrocell><macrocell id="FB2_MC2" pin="FB2_MC2_PIN143"><pterms pt1="FB2_2_1" pt2="FB2_2_2" pt3="FB2_2_3" pt4="FB2_2_4" pt5="FB2_2_5"/></macrocell><macrocell id="FB2_MC3"><pterms pt1="FB2_3_1" pt2="FB2_3_2" pt3="FB2_3_3"/></macrocell><macrocell id="FB2_MC4" pin="FB2_MC4_PIN4"/><macrocell id="FB2_MC5" pin="FB2_MC5_PIN2" sigUse="2" signal="D0_SPECSIG"><pterms pt1="FB2_5_1"/></macrocell><macrocell id="FB2_MC6" pin="FB2_MC6_PIN3"/><macrocell id="FB2_MC7"/><macrocell id="FB2_MC8" pin="FB2_MC8_PIN5" sigUse="2" signal="AUTO_CONFIG_DONE2_SPECSIG"><pterms pt1="FB2_8_1" pt2="FB2_8_2"/></macrocell><macrocell id="FB2_MC9" pin="FB2_MC9_PIN6" sigUse="2" signal="AUTO_CONFIG_DONE0_SPECSIG"><pterms pt1="FB2_9_1" pt2="FB2_9_2"/></macrocell><macrocell id="FB2_MC10" pin="FB2_MC10_PIN7" sigUse="15" signal="AUTO_CONFIG_DONE_CYCLE2_SPECSIG"><pterms pt1="FB2_10_1" pt2="FB2_10_2" pt3="FB2_10_3"/></macrocell><macrocell id="FB2_MC11" pin="FB2_MC11_PIN9" sigUse="13" signal="AUTO_CONFIG_DONE_CYCLE0_SPECSIG"><pterms pt1="FB2_11_1" pt2="FB2_11_2" pt3="FB2_11_3" pt4="FB2_11_4"/></macrocell><macrocell id="FB2_MC12" pin="FB2_MC12_PIN10" sigUse="16" signal="IDE_BASEADR7_SPECSIG"><pterms pt1="FB2_12_1" pt2="FB2_12_2" pt3="FB2_12_3" pt4="FB2_12_4" pt5="FB2_12_5"/></macrocell><macrocell id="FB2_MC13" pin="FB2_MC13_PIN12" sigUse="16" signal="IDE_BASEADR6_SPECSIG"><pterms pt1="FB2_13_1" pt2="FB2_13_2" pt3="FB2_13_3" pt4="FB2_13_4" pt5="FB2_13_5"/></macrocell><macrocell id="FB2_MC14" pin="FB2_MC14_PIN11"><pterms pt1="FB2_14_1" pt2="FB2_14_2" pt3="FB2_14_3" pt4="FB2_14_4" pt5="FB2_14_5"/></macrocell><macrocell id="FB2_MC15" pin="FB2_MC15_PIN13" sigUse="15" signal="D13_BUFR_SPECSIG"><pterms pt1="FB2_15_1" pt2="FB2_15_2" pt3="FB2_15_3" pt4="FB2_15_4" pt5="FB2_15_5"/></macrocell><macrocell id="FB2_MC16" pin="FB2_MC16_PIN14" sigUse="2" signal="D6_SPECSIG"><pterms pt1="FB2_16_1" pt2="FB2_16_2" pt3="FB2_16_3" pt4="FB2_16_4" pt5="FB2_16_5"/></macrocell><macrocell id="FB2_MC17" pin="FB2_MC17_PIN15" sigUse="2" signal="D3_SPECSIG"><pterms pt1="FB2_17_1"/></macrocell><macrocell id="FB2_MC18"><pterms pt1="FB2_18_1" pt2="FB2_18_2" pt3="FB2_18_3" pt4="FB2_18_4" pt5="FB2_18_5"/></macrocell><fbinput id="FB2_I1" signal="AS"/><fbinput id="FB2_I2" signal="AUTOCONFIG_IN_PROGRESS"/><fbinput id="FB2_I3" signal="AUTO_CONFIG_DONE0_SPECSIG"/><fbinput id="FB2_I4" signal="AUTO_CONFIG_DONE1_SPECSIG"/><fbinput id="FB2_I5" signal="AUTO_CONFIG_DONE2_SPECSIG"/><fbinput id="FB2_I6" signal="AUTO_CONFIG_DONE_CYCLE0_SPECSIG"/><fbinput id="FB2_I7" signal="AUTO_CONFIG_DONE_CYCLE2_SPECSIG"/><fbinput id="FB2_I8" signal="A1_SPECSIG"/><fbinput id="FB2_I9" signal="A2_SPECSIG"/><fbinput id="FB2_I10" signal="A3_SPECSIG"/><fbinput id="FB2_I11" signal="A4_SPECSIG"/><fbinput id="FB2_I12" signal="A5_SPECSIG"/><fbinput id="FB2_I13" signal="A6_SPECSIG"/><fbinput id="FB2_I14" signal="D13_SPECSIG"/><fbinput id="FB2_I15" signal="D14_SPECSIG"/><fbinput id="FB2_I16" signal="IDE_BASEADR6_SPECSIG"/><fbinput id="FB2_I17" signal="IDE_BASEADR7_SPECSIG"/><fbinput fbk="PIN" id="FB2_I18" signal="D14PIN_SPECSIG"/><fbinput fbk="PIN" id="FB2_I19" signal="D15PIN_SPECSIG"/><fbinput id="FB2_I20" signal="RESET"/><fbinput id="FB2_I21" signal="RW"/><fbinput id="FB2_I22" signal="UDS"/><fbinput id="FB2_I23" signal="autoconfig"/><fbinput id="FB2_I24" signal="ideide_CLKF_SPECSIG"/><pterm id="FB2_1_1"><signal id="RESET"/><signal id="RW"/><signal id="AS" negated="ON"/><signal id="A5_SPECSIG" negated="ON"/><signal id="A4_SPECSIG" negated="ON"/><signal id="A1_SPECSIG"/><signal id="A3_SPECSIG" negated="ON"/><signal id="A2_SPECSIG" negated="ON"/><signal id="AUTO_CONFIG_DONE1_SPECSIG" negated="ON"/><signal id="autoconfig"/></pterm><pterm id="FB2_1_2"><signal id="RESET"/><signal id="RW"/><signal id="AS" negated="ON"/><signal id="A5_SPECSIG" negated="ON"/><signal id="A4_SPECSIG" negated="ON"/><signal id="A1_SPECSIG"/><signal id="A3_SPECSIG" negated="ON"/><signal id="A2_SPECSIG" negated="ON"/><signal id="AUTO_CONFIG_DONE2_SPECSIG" negated="ON"/><signal id="autoconfig"/></pterm><pterm id="FB2_1_3"><signal id="RESET"/><signal id="RW"/><signal id="AS" negated="ON"/><signal id="A5_SPECSIG" negated="ON"/><signal id="A1_SPECSIG"/><signal id="A6_SPECSIG" negated="ON"/><signal id="A3_SPECSIG" negated="ON"/><signal id="A2_SPECSIG"/><signal id="AUTO_CONFIG_DONE0_SPECSIG"/><signal id="AUTO_CONFIG_DONE1_SPECSIG" negated="ON"/><signal id="autoconfig"/></pterm><pterm id="FB2_1_4"><signal id="RESET"/><signal id="RW"/><signal id="AS" negated="ON"/><signal id="A5_SPECSIG" negated="ON"/><signal id="A4_SPECSIG" negated="ON"/><signal id="A6_SPECSIG" negated="ON"/><signal id="A3_SPECSIG" negated="ON"/><signal id="A2_SPECSIG"/><signal id="AUTO_CONFIG_DONE0_SPECSIG"/><signal id="AUTO_CONFIG_DONE1_SPECSIG"/><signal id="AUTO_CONFIG_DONE2_SPECSIG" negated="ON"/><signal id="autoconfig"/></pterm><pterm id="FB2_1_5"><signal id="ideide_CLKF_SPECSIG"/></pterm><pterm id="FB2_2_1"><signal id="RESET"/><signal id="RW"/><signal id="AS" negated="ON"/><signal id="A5_SPECSIG" negated="ON"/><signal id="A4_SPECSIG" negated="ON"/><signal id="A1_SPECSIG"/><signal id="A3_SPECSIG" negated="ON"/><signal id="A2_SPECSIG" negated="ON"/><signal id="AUTO_CONFIG_DONE0_SPECSIG" negated="ON"/><signal id="autoconfig"/></pterm><pterm id="FB2_2_2"><signal id="RESET"/><signal id="RW"/><signal id="AS" negated="ON"/><signal id="A5_SPECSIG" negated="ON"/><signal id="A4_SPECSIG" negated="ON"/><signal id="A6_SPECSIG"/><signal id="A3_SPECSIG" negated="ON"/><signal id="A2_SPECSIG" negated="ON"/><signal id="AUTO_CONFIG_DONE0_SPECSIG" negated="ON"/><signal id="autoconfig"/></pterm><pterm id="FB2_2_3"><signal id="RESET"/><signal id="RW"/><signal id="AS" negated="ON"/><signal id="A5_SPECSIG" negated="ON"/><signal id="A4_SPECSIG" negated="ON"/><signal id="A6_SPECSIG"/><signal id="A3_SPECSIG" negated="ON"/><signal id="A2_SPECSIG" negated="ON"/><signal id="AUTO_CONFIG_DONE1_SPECSIG" negated="ON"/><signal id="autoconfig"/></pterm><pterm id="FB2_2_4"><signal id="RESET"/><signal id="RW"/><signal id="AS" negated="ON"/><signal id="A5_SPECSIG" negated="ON"/><signal id="A4_SPECSIG" negated="ON"/><signal id="A6_SPECSIG"/><signal id="A3_SPECSIG" negated="ON"/><signal id="A2_SPECSIG" negated="ON"/><signal id="AUTO_CONFIG_DONE2_SPECSIG" negated="ON"/><signal id="autoconfig"/></pterm><pterm id="FB2_2_5"><signal id="RESET"/><signal id="RW"/><signal id="AS" negated="ON"/><signal id="A4_SPECSIG" negated="ON"/><signal id="A1_SPECSIG"/><signal id="A6_SPECSIG" negated="ON"/><signal id="A3_SPECSIG" negated="ON"/><signal id="A2_SPECSIG"/><signal id="AUTO_CONFIG_DONE0_SPECSIG"/><signal id="AUTO_CONFIG_DONE1_SPECSIG" negated="ON"/><signal id="autoconfig"/></pterm><pterm id="FB2_3_1"><signal id="RESET"/><signal id="RW"/><signal id="AS" negated="ON"/><signal id="A5_SPECSIG" negated="ON"/><signal id="A4_SPECSIG"/><signal id="A1_SPECSIG"/><signal id="A6_SPECSIG" negated="ON"/><signal id="A3_SPECSIG" negated="ON"/><signal id="A2_SPECSIG"/><signal id="AUTO_CONFIG_DONE0_SPECSIG" negated="ON"/><signal id="autoconfig"/></pterm><pterm id="FB2_3_2"><signal id="RESET"/><signal id="RW"/><signal id="AS" negated="ON"/><signal id="A5_SPECSIG" negated="ON"/><signal id="A4_SPECSIG" negated="ON"/><signal id="A1_SPECSIG" negated="ON"/><signal id="A6_SPECSIG" negated="ON"/><signal id="A3_SPECSIG" negated="ON"/><signal id="A2_SPECSIG"/><signal id="AUTO_CONFIG_DONE0_SPECSIG" negated="ON"/><signal id="autoconfig"/></pterm><pterm id="FB2_3_3"><signal id="RESET"/><signal id="RW"/><signal id="AS" negated="ON"/><signal id="A5_SPECSIG" negated="ON"/><signal id="A4_SPECSIG"/><signal id="A1_SPECSIG" negated="ON"/><signal id="A6_SPECSIG" negated="ON"/><signal id="A3_SPECSIG"/><signal id="A2_SPECSIG"/><signal id="AUTO_CONFIG_DONE0_SPECSIG"/><signal id="AUTO_CONFIG_DONE1_SPECSIG" negated="ON"/><signal id="autoconfig"/></pterm><pterm id="FB2_5_1"><signal id="RW"/><signal id="AUTOCONFIG_IN_PROGRESS"/></pterm><pterm id="FB2_8_1"><signal id="AUTO_CONFIG_DONE_CYCLE2_SPECSIG"/></pterm><pterm id="FB2_8_2"><signal id="AS"/></pterm><pterm id="FB2_9_1"><signal id="AUTO_CONFIG_DONE_CYCLE0_SPECSIG"/></pterm><pterm id="FB2_9_2"><signal id="AS"/></pterm><pterm id="FB2_10_1"><signal id="RESET"/><signal id="AUTO_CONFIG_DONE_CYCLE2_SPECSIG"/></pterm><pterm id="FB2_10_2"><signal id="RESET"/><signal id="UDS" negated="ON"/><signal id="RW" negated="ON"/><signal id="AS" negated="ON"/><signal id="A5_SPECSIG" negated="ON"/><signal id="A4_SPECSIG" negated="ON"/><signal id="A1_SPECSIG" negated="ON"/><signal id="A6_SPECSIG"/><signal id="A3_SPECSIG"/><signal id="AUTO_CONFIG_DONE0_SPECSIG"/><signal id="AUTO_CONFIG_DONE1_SPECSIG"/><signal id="AUTO_CONFIG_DONE2_SPECSIG" negated="ON"/><signal id="autoconfig"/></pterm><pterm id="FB2_10_3"><signal id="ideide_CLKF_SPECSIG"/></pterm><pterm id="FB2_11_1"><signal id="RESET"/><signal id="AUTO_CONFIG_DONE_CYCLE0_SPECSIG"/></pterm><pterm id="FB2_11_2"><signal id="RESET"/><signal id="UDS" negated="ON"/><signal id="RW" negated="ON"/><signal id="AS" negated="ON"/><signal id="A5_SPECSIG" negated="ON"/><signal id="A4_SPECSIG" negated="ON"/><signal id="A1_SPECSIG" negated="ON"/><signal id="A6_SPECSIG"/><signal id="A3_SPECSIG"/><signal id="AUTO_CONFIG_DONE0_SPECSIG" negated="ON"/><signal id="autoconfig"/></pterm><pterm id="FB2_11_3"><signal id="ideide_CLKF_SPECSIG"/></pterm><pterm id="FB2_11_4"><signal id="RESET"/><signal id="UDS" negated="ON"/><signal id="RW" negated="ON"/><signal id="AS" negated="ON"/><signal id="A5_SPECSIG" negated="ON"/><signal id="A4_SPECSIG" negated="ON"/><signal id="A1_SPECSIG" negated="ON"/><signal id="A6_SPECSIG"/><signal id="A3_SPECSIG"/><signal id="A2_SPECSIG" negated="ON"/><signal id="AUTO_CONFIG_DONE0_SPECSIG"/><signal id="AUTO_CONFIG_DONE1_SPECSIG" negated="ON"/><signal id="IDE_BASEADR7_SPECSIG"/><signal id="autoconfig"/><signal id="D15PIN_SPECSIG" negated="ON"/></pterm><pterm id="FB2_12_1"><signal id="RESET" negated="ON"/><signal id="IDE_BASEADR7_SPECSIG" negated="ON"/></pterm><pterm id="FB2_12_2"><signal id="UDS" negated="ON"/><signal id="RW" negated="ON"/><signal id="AS" negated="ON"/><signal id="A5_SPECSIG" negated="ON"/><signal id="A4_SPECSIG" negated="ON"/><signal id="A1_SPECSIG" negated="ON"/><signal id="A6_SPECSIG"/><signal id="A3_SPECSIG"/><signal id="A2_SPECSIG" negated="ON"/><signal id="AUTO_CONFIG_DONE0_SPECSIG"/><signal id="AUTO_CONFIG_DONE1_SPECSIG" negated="ON"/><signal id="IDE_BASEADR7_SPECSIG" negated="ON"/><signal id="autoconfig"/><signal id="D15PIN_SPECSIG"/></pterm><pterm id="FB2_12_3"><signal id="ideide_CLKF_SPECSIG"/></pterm><pterm id="FB2_12_4"><signal id="UDS" negated="ON"/><signal id="RW" negated="ON"/><signal id="AS" negated="ON"/><signal id="A5_SPECSIG" negated="ON"/><signal id="A4_SPECSIG" negated="ON"/><signal id="A1_SPECSIG" negated="ON"/><signal id="A6_SPECSIG"/><signal id="A3_SPECSIG"/><signal id="A2_SPECSIG" negated="ON"/><signal id="AUTO_CONFIG_DONE0_SPECSIG"/><signal id="AUTO_CONFIG_DONE1_SPECSIG" negated="ON"/><signal id="IDE_BASEADR6_SPECSIG" negated="ON"/><signal id="autoconfig"/><signal id="D14PIN_SPECSIG"/></pterm><pterm id="FB2_12_5"><signal id="RESET"/><signal id="UDS" negated="ON"/><signal id="RW" negated="ON"/><signal id="AS" negated="ON"/><signal id="A5_SPECSIG" negated="ON"/><signal id="A4_SPECSIG" negated="ON"/><signal id="A1_SPECSIG" negated="ON"/><signal id="A6_SPECSIG"/><signal id="A3_SPECSIG"/><signal id="A2_SPECSIG" negated="ON"/><signal id="AUTO_CONFIG_DONE0_SPECSIG"/><signal id="AUTO_CONFIG_DONE1_SPECSIG" negated="ON"/><signal id="IDE_BASEADR6_SPECSIG"/><signal id="autoconfig"/><signal id="D14PIN_SPECSIG" negated="ON"/></pterm><pterm id="FB2_13_1"><signal id="RESET" negated="ON"/><signal id="IDE_BASEADR6_SPECSIG" negated="ON"/></pterm><pterm id="FB2_13_2"><signal id="ideide_CLKF_SPECSIG"/></pterm><pterm id="FB2_13_3"><signal id="RESET"/><signal id="RW"/><signal id="AS" negated="ON"/><signal id="A5_SPECSIG" negated="ON"/><signal id="A4_SPECSIG"/><signal id="A1_SPECSIG" negated="ON"/><signal id="A6_SPECSIG" negated="ON"/><signal id="A3_SPECSIG"/><signal id="AUTO_CONFIG_DONE0_SPECSIG"/><signal id="AUTO_CONFIG_DONE1_SPECSIG" negated="ON"/><signal id="autoconfig"/></pterm><pterm id="FB2_13_4"><signal id="RESET"/><signal id="RW"/><signal id="AS" negated="ON"/><signal id="A5_SPECSIG" negated="ON"/><signal id="A4_SPECSIG" negated="ON"/><signal id="A1_SPECSIG" negated="ON"/><signal id="A6_SPECSIG" negated="ON"/><signal id="A3_SPECSIG" negated="ON"/><signal id="AUTO_CONFIG_DONE1_SPECSIG"/><signal id="AUTO_CONFIG_DONE2_SPECSIG" negated="ON"/><signal id="autoconfig"/></pterm><pterm id="FB2_13_5"><signal id="RESET"/><signal id="RW"/><signal id="AS" negated="ON"/><signal id="A5_SPECSIG"/><signal id="A4_SPECSIG" negated="ON"/><signal id="A1_SPECSIG" negated="ON"/><signal id="A6_SPECSIG" negated="ON"/><signal id="A3_SPECSIG" negated="ON"/><signal id="A2_SPECSIG"/><signal id="AUTO_CONFIG_DONE0_SPECSIG"/><signal id="AUTO_CONFIG_DONE1_SPECSIG" negated="ON"/><signal id="autoconfig"/></pterm><pterm id="FB2_14_1"><signal id="RESET"/><signal id="D13_SPECSIG" negated="ON"/><signal id="RW" negated="ON"/></pterm><pterm id="FB2_14_2"><signal id="RESET"/><signal id="D13_SPECSIG" negated="ON"/><signal id="AUTO_CONFIG_DONE0_SPECSIG"/><signal id="AUTO_CONFIG_DONE1_SPECSIG"/><signal id="AUTO_CONFIG_DONE2_SPECSIG"/></pterm><pterm id="FB2_14_3"><signal id="RESET"/><signal id="RW"/><signal id="AS" negated="ON"/><signal id="A5_SPECSIG" negated="ON"/><signal id="A4_SPECSIG" negated="ON"/><signal id="A6_SPECSIG" negated="ON"/><signal id="A3_SPECSIG" negated="ON"/><signal id="AUTO_CONFIG_DONE0_SPECSIG" negated="ON"/><signal id="autoconfig"/></pterm><pterm id="FB2_14_4"><signal id="RESET"/><signal id="RW"/><signal id="AS" negated="ON"/><signal id="A5_SPECSIG" negated="ON"/><signal id="A4_SPECSIG" negated="ON"/><signal id="A3_SPECSIG" negated="ON"/><signal id="A2_SPECSIG" negated="ON"/><signal id="AUTO_CONFIG_DONE0_SPECSIG" negated="ON"/><signal id="autoconfig"/></pterm><pterm id="FB2_14_5"><signal id="RESET"/><signal id="RW"/><signal id="AS" negated="ON"/><signal id="A5_SPECSIG" negated="ON"/><signal id="A4_SPECSIG" negated="ON"/><signal id="A3_SPECSIG" negated="ON"/><signal id="A2_SPECSIG" negated="ON"/><signal id="AUTO_CONFIG_DONE1_SPECSIG" negated="ON"/><signal id="autoconfig"/></pterm><pterm id="FB2_15_1"><signal id="RESET"/><signal id="D13_SPECSIG" negated="ON"/><signal id="AS"/></pterm><pterm id="FB2_15_2"><signal id="RESET"/><signal id="D13_SPECSIG" negated="ON"/><signal id="autoconfig" negated="ON"/></pterm><pterm id="FB2_15_3"><signal id="RESET"/><signal id="RW"/><signal id="AS" negated="ON"/><signal id="A5_SPECSIG" negated="ON"/><signal id="A4_SPECSIG"/><signal id="A6_SPECSIG" negated="ON"/><signal id="A3_SPECSIG"/><signal id="A2_SPECSIG"/><signal id="AUTO_CONFIG_DONE0_SPECSIG"/><signal id="AUTO_CONFIG_DONE1_SPECSIG" negated="ON"/><signal id="autoconfig"/></pterm><pterm id="FB2_15_4"><signal id="RESET"/><signal id="RW"/><signal id="AS" negated="ON"/><signal id="A5_SPECSIG" negated="ON"/><signal id="A1_SPECSIG"/><signal id="A6_SPECSIG" negated="ON"/><signal id="A3_SPECSIG" negated="ON"/><signal id="A2_SPECSIG" negated="ON"/><signal id="AUTO_CONFIG_DONE1_SPECSIG"/><signal id="AUTO_CONFIG_DONE2_SPECSIG" negated="ON"/><signal id="autoconfig"/></pterm><pterm id="FB2_15_5"><signal id="ideide_CLKF_SPECSIG"/></pterm><pterm id="FB2_16_1"><signal id="RW"/><signal id="AUTOCONFIG_IN_PROGRESS"/></pterm><pterm id="FB2_16_2"><signal id="RESET"/><signal id="RW"/><signal id="AS" negated="ON"/><signal id="A5_SPECSIG" negated="ON"/><signal id="A4_SPECSIG" negated="ON"/><signal id="A3_SPECSIG" negated="ON"/><signal id="A2_SPECSIG" negated="ON"/><signal id="AUTO_CONFIG_DONE2_SPECSIG" negated="ON"/><signal id="autoconfig"/></pterm><pterm id="FB2_16_3"><signal id="RESET"/><signal id="RW"/><signal id="AS" negated="ON"/><signal id="A5_SPECSIG" negated="ON"/><signal id="A4_SPECSIG" negated="ON"/><signal id="A1_SPECSIG"/><signal id="A6_SPECSIG" negated="ON"/><signal id="A3_SPECSIG" negated="ON"/><signal id="AUTO_CONFIG_DONE1_SPECSIG" negated="ON"/><signal id="autoconfig"/></pterm><pterm id="FB2_16_4"><signal id="RESET"/><signal id="RW"/><signal id="AS" negated="ON"/><signal id="A5_SPECSIG" negated="ON"/><signal id="A1_SPECSIG"/><signal id="A6_SPECSIG" negated="ON"/><signal id="A3_SPECSIG" negated="ON"/><signal id="A2_SPECSIG" negated="ON"/><signal id="AUTO_CONFIG_DONE0_SPECSIG" negated="ON"/><signal id="autoconfig"/></pterm><pterm id="FB2_16_5"><signal id="RESET"/><signal id="RW"/><signal id="AS" negated="ON"/><signal id="A5_SPECSIG" negated="ON"/><signal id="A4_SPECSIG"/><signal id="A1_SPECSIG" negated="ON"/><signal id="A6_SPECSIG" negated="ON"/><signal id="A2_SPECSIG"/><signal id="AUTO_CONFIG_DONE0_SPECSIG"/><signal id="AUTO_CONFIG_DONE1_SPECSIG" negated="ON"/><signal id="autoconfig"/></pterm><pterm id="FB2_17_1"><signal id="RW"/><signal id="AUTOCONFIG_IN_PROGRESS"/></pterm><pterm id="FB2_18_1"><signal id="RESET"/><signal id="D14_SPECSIG" negated="ON"/><signal id="RW" negated="ON"/></pterm><pterm id="FB2_18_2"><signal id="RESET"/><signal id="D14_SPECSIG" negated="ON"/><signal id="AS"/></pterm><pterm id="FB2_18_3"><signal id="RESET"/><signal id="D14_SPECSIG" negated="ON"/><signal id="autoconfig" negated="ON"/></pterm><pterm id="FB2_18_4"><signal id="RESET"/><signal id="D14_SPECSIG" negated="ON"/><signal id="AUTO_CONFIG_DONE0_SPECSIG"/><signal id="AUTO_CONFIG_DONE1_SPECSIG"/><signal id="AUTO_CONFIG_DONE2_SPECSIG"/></pterm><pterm id="FB2_18_5"><signal id="RESET"/><signal id="RW"/><signal id="AS" negated="ON"/><signal id="A5_SPECSIG" negated="ON"/><signal id="A1_SPECSIG"/><signal id="A6_SPECSIG" negated="ON"/><signal id="A3_SPECSIG" negated="ON"/><signal id="A2_SPECSIG"/><signal id="AUTO_CONFIG_DONE0_SPECSIG"/><signal id="AUTO_CONFIG_DONE2_SPECSIG" negated="ON"/><signal id="autoconfig"/></pterm><equation id="D14_BUFR_SPECSIG" negated="ON" regUse="D"><d2><eq_pterm ptindx="FB2_1_1"/><eq_pterm ptindx="FB2_1_2"/><eq_pterm ptindx="FB2_1_3"/><eq_pterm ptindx="FB2_1_4"/><eq_pterm import="1" ptindx="FB2_2_1"/><eq_pterm import="1" ptindx="FB2_2_2"/><eq_pterm import="1" ptindx="FB2_2_3"/><eq_pterm import="1" ptindx="FB2_2_4"/><eq_pterm import="1" ptindx="FB2_2_5"/><eq_pterm import="1" ptindx="FB2_3_1"/><eq_pterm import="1" ptindx="FB2_3_2"/><eq_pterm import="1" ptindx="FB2_3_3"/><eq_pterm import="1" ptindx="FB2_18_1"/><eq_pterm import="1" ptindx="FB2_18_2"/><eq_pterm import="1" ptindx="FB2_18_3"/><eq_pterm import="1" ptindx="FB2_18_4"/><eq_pterm import="1" ptindx="FB2_18_5"/></d2><clk><eq_pterm ptindx="FB2_1_5"/></clk><prld ptindx="GND"/></equation><equation id="D0_SPECSIG" userloc="P2"><d2><eq_pterm ptindx="VCC"/></d2><oe><eq_pterm ptindx="FB2_5_1"/></oe></equation><equation id="AUTO_CONFIG_DONE2_SPECSIG" regUse="D"><d2><eq_pterm ptindx="FB2_8_1"/></d2><clk><eq_pterm ptindx="FB2_8_2"/></clk><reset><fastsig signal="RESET"/></reset><prld ptindx="GND"/></equation><equation id="AUTO_CONFIG_DONE0_SPECSIG" regUse="D"><d2><eq_pterm ptindx="FB2_9_1"/></d2><clk><eq_pterm ptindx="FB2_9_2"/></clk><reset><fastsig signal="RESET"/></reset><prld ptindx="GND"/></equation><equation id="AUTO_CONFIG_DONE_CYCLE2_SPECSIG" regUse="D"><d2><eq_pterm ptindx="FB2_10_1"/><eq_pterm ptindx="FB2_10_2"/></d2><clk><eq_pterm ptindx="FB2_10_3"/></clk><prld ptindx="GND"/></equation><equation id="AUTO_CONFIG_DONE_CYCLE0_SPECSIG" regUse="D"><d2><eq_pterm ptindx="FB2_11_1"/><eq_pterm ptindx="FB2_11_2"/></d2><clk><eq_pterm ptindx="FB2_11_3"/></clk><prld ptindx="GND"/></equation><equation id="IDE_BASEADR7_SPECSIG" regUse="T"><d2><eq_pterm ptindx="FB2_12_1"/><eq_pterm ptindx="FB2_12_2"/><eq_pterm import="1" ptindx="FB2_11_4"/></d2><clk><eq_pterm ptindx="FB2_12_3"/></clk><prld ptindx="GND"/></equation><equation id="IDE_BASEADR6_SPECSIG" regUse="T"><d2><eq_pterm ptindx="FB2_13_1"/><eq_pterm import="1" ptindx="FB2_12_4"/><eq_pterm import="1" ptindx="FB2_12_5"/></d2><clk><eq_pterm ptindx="FB2_13_2"/></clk><prld ptindx="GND"/></equation><equation id="D13_BUFR_SPECSIG" negated="ON" regUse="D"><d2><eq_pterm ptindx="FB2_15_1"/><eq_pterm ptindx="FB2_15_2"/><eq_pterm ptindx="FB2_15_3"/><eq_pterm ptindx="FB2_15_4"/><eq_pterm import="1" ptindx="FB2_14_1"/><eq_pterm import="1" ptindx="FB2_14_2"/><eq_pterm import="1" ptindx="FB2_14_3"/><eq_pterm import="1" ptindx="FB2_14_4"/><eq_pterm import="1" ptindx="FB2_14_5"/><eq_pterm import="1" ptindx="FB2_13_3"/><eq_pterm import="1" ptindx="FB2_13_4"/><eq_pterm import="1" ptindx="FB2_13_5"/><eq_pterm import="1" ptindx="FB2_16_2"/><eq_pterm import="1" ptindx="FB2_16_3"/><eq_pterm import="1" ptindx="FB2_16_4"/><eq_pterm import="1" ptindx="FB2_16_5"/></d2><clk><eq_pterm ptindx="FB2_15_5"/></clk><prld ptindx="GND"/></equation><equation id="D6_SPECSIG" userloc="P14"><d2><eq_pterm ptindx="VCC"/></d2><oe><eq_pterm ptindx="FB2_16_1"/></oe></equation><equation id="D3_SPECSIG" userloc="P15"><d2><eq_pterm ptindx="VCC"/></d2><oe><eq_pterm ptindx="FB2_17_1"/></oe></equation></fblock><fblock id="FB3" inputUse="24" pinUse="11"><macrocell id="FB3_MC1" pin="FB3_MC1_PIN39" sigUse="2" signal="D2_SPECSIG"><pterms pt1="FB3_1_1"/></macrocell><macrocell id="FB3_MC2" pin="FB3_MC2_PIN32"/><macrocell id="FB3_MC3" pin="FB3_MC3_PIN41" sigUse="2" signal="D10_SPECSIG"><pterms pt1="FB3_3_1"/></macrocell><macrocell id="FB3_MC4" pin="FB3_MC4_PIN44" sigUse="3" signal="D12_SPECSIG"><pterms pt1="FB3_4_1" pt2="FB3_4_2"/></macrocell><macrocell id="FB3_MC5" pin="FB3_MC5_PIN33"/><macrocell id="FB3_MC6" pin="FB3_MC6_PIN34"/><macrocell id="FB3_MC7" pin="FB3_MC7_PIN46" sigUse="3" signal="D14_SPECSIG"><pterms pt1="FB3_7_1" pt2="FB3_7_2"/></macrocell><macrocell id="FB3_MC8" pin="FB3_MC8_PIN38"/><macrocell id="FB3_MC9" pin="FB3_MC9_PIN40" sigUse="2" signal="D9_SPECSIG"><pterms pt1="FB3_9_1"/></macrocell><macrocell id="FB3_MC10" pin="FB3_MC10_PIN48" sigUse="3" signal="D15_SPECSIG"><pterms pt1="FB3_10_1" pt2="FB3_10_2"/></macrocell><macrocell id="FB3_MC11" pin="FB3_MC11_PIN43" sigUse="2" signal="D11_SPECSIG"><pterms pt1="FB3_11_1"/></macrocell><macrocell id="FB3_MC12" pin="FB3_MC12_PIN45" sigUse="3" signal="D13_SPECSIG"><pterms pt1="FB3_12_1" pt2="FB3_12_2"/></macrocell><macrocell id="FB3_MC13"/><macrocell id="FB3_MC14" pin="FB3_MC14_PIN49"/><macrocell id="FB3_MC15" pin="FB3_MC15_PIN50" sigUse="2" signal="AUTO_CONFIG_DONE1_SPECSIG"><pterms pt1="FB3_15_1" pt2="FB3_15_2"/></macrocell><macrocell id="FB3_MC16" sigUse="14" signal="AUTO_CONFIG_DONE_CYCLE1_SPECSIG"><pterms pt1="FB3_16_1" pt2="FB3_16_2" pt3="FB3_16_3"/></macrocell><macrocell id="FB3_MC17" pin="FB3_MC17_PIN51" sigUse="16" signal="IDE_BASEADR3_SPECSIG"><pterms pt1="FB3_17_1" pt2="FB3_17_2" pt3="FB3_17_3" pt4="FB3_17_4"/></macrocell><macrocell id="FB3_MC18" sigUse="16" signal="IDE_BASEADR2_SPECSIG"><pterms pt1="FB3_18_1" pt2="FB3_18_2" pt3="FB3_18_3" pt4="FB3_18_4"/></macrocell><fbinput id="FB3_I1" signal="AS"/><fbinput id="FB3_I2" signal="AUTOCONFIG_IN_PROGRESS"/><fbinput id="FB3_I3" signal="AUTO_CONFIG_DONE0_SPECSIG"/><fbinput id="FB3_I4" signal="AUTO_CONFIG_DONE1_SPECSIG"/><fbinput id="FB3_I5" signal="AUTO_CONFIG_DONE_CYCLE1_SPECSIG"/><fbinput id="FB3_I6" signal="A1_SPECSIG"/><fbinput id="FB3_I7" signal="A2_SPECSIG"/><fbinput id="FB3_I8" signal="A3_SPECSIG"/><fbinput id="FB3_I9" signal="A4_SPECSIG"/><fbinput id="FB3_I10" signal="A5_SPECSIG"/><fbinput id="FB3_I11" signal="A6_SPECSIG"/><fbinput id="FB3_I12" signal="D12_BUFR_SPECSIG"/><fbinput id="FB3_I13" signal="D13_BUFR_SPECSIG"/><fbinput id="FB3_I14" signal="D14_BUFR_SPECSIG"/><fbinput id="FB3_I15" signal="D15_BUFR_SPECSIG"/><fbinput id="FB3_I16" signal="IDE_BASEADR2_SPECSIG"/><fbinput id="FB3_I17" signal="IDE_BASEADR3_SPECSIG"/><fbinput fbk="PIN" id="FB3_I18" signal="D11PIN_SPECSIG"/><fbinput fbk="PIN" id="FB3_I19" signal="D10PIN_SPECSIG"/><fbinput id="FB3_I20" signal="RESET"/><fbinput id="FB3_I21" signal="RW"/><fbinput id="FB3_I22" signal="UDS"/><fbinput id="FB3_I23" signal="autoconfig"/><fbinput id="FB3_I24" signal="ideide_CLKF_SPECSIG"/><pterm id="FB3_1_1"><signal id="RW"/><signal id="AUTOCONFIG_IN_PROGRESS"/></pterm><pterm id="FB3_3_1"><signal id="RW"/><signal id="AUTOCONFIG_IN_PROGRESS"/></pterm><pterm id="FB3_4_1"><signal id="D12_BUFR_SPECSIG"/></pterm><pterm id="FB3_4_2"><signal id="RW"/><signal id="AUTOCONFIG_IN_PROGRESS"/></pterm><pterm id="FB3_7_1"><signal id="D14_BUFR_SPECSIG"/></pterm><pterm id="FB3_7_2"><signal id="RW"/><signal id="AUTOCONFIG_IN_PROGRESS"/></pterm><pterm id="FB3_9_1"><signal id="RW"/><signal id="AUTOCONFIG_IN_PROGRESS"/></pterm><pterm id="FB3_10_1"><signal id="D15_BUFR_SPECSIG"/></pterm><pterm id="FB3_10_2"><signal id="RW"/><signal id="AUTOCONFIG_IN_PROGRESS"/></pterm><pterm id="FB3_11_1"><signal id="RW"/><signal id="AUTOCONFIG_IN_PROGRESS"/></pterm><pterm id="FB3_12_1"><signal id="D13_BUFR_SPECSIG"/></pterm><pterm id="FB3_12_2"><signal id="RW"/><signal id="AUTOCONFIG_IN_PROGRESS"/></pterm><pterm id="FB3_15_1"><signal id="AUTO_CONFIG_DONE_CYCLE1_SPECSIG"/></pterm><pterm id="FB3_15_2"><signal id="AS"/></pterm><pterm id="FB3_16_1"><signal id="RESET"/><signal id="AUTO_CONFIG_DONE_CYCLE1_SPECSIG"/></pterm><pterm id="FB3_16_2"><signal id="RESET"/><signal id="UDS" negated="ON"/><signal id="RW" negated="ON"/><signal id="AS" negated="ON"/><signal id="A5_SPECSIG" negated="ON"/><signal id="A4_SPECSIG" negated="ON"/><signal id="A1_SPECSIG" negated="ON"/><signal id="A6_SPECSIG"/><signal id="A3_SPECSIG"/><signal id="AUTO_CONFIG_DONE0_SPECSIG"/><signal id="AUTO_CONFIG_DONE1_SPECSIG" negated="ON"/><signal id="autoconfig"/></pterm><pterm id="FB3_16_3"><signal id="ideide_CLKF_SPECSIG"/></pterm><pterm id="FB3_17_1"><signal id="RESET" negated="ON"/><signal id="IDE_BASEADR3_SPECSIG" negated="ON"/></pterm><pterm id="FB3_17_2"><signal id="UDS" negated="ON"/><signal id="RW" negated="ON"/><signal id="AS" negated="ON"/><signal id="A5_SPECSIG" negated="ON"/><signal id="A4_SPECSIG" negated="ON"/><signal id="A1_SPECSIG" negated="ON"/><signal id="A6_SPECSIG"/><signal id="A3_SPECSIG"/><signal id="A2_SPECSIG" negated="ON"/><signal id="AUTO_CONFIG_DONE0_SPECSIG"/><signal id="AUTO_CONFIG_DONE1_SPECSIG" negated="ON"/><signal id="IDE_BASEADR3_SPECSIG" negated="ON"/><signal id="autoconfig"/><signal id="D11PIN_SPECSIG"/></pterm><pterm id="FB3_17_3"><signal id="RESET"/><signal id="UDS" negated="ON"/><signal id="RW" negated="ON"/><signal id="AS" negated="ON"/><signal id="A5_SPECSIG" negated="ON"/><signal id="A4_SPECSIG" negated="ON"/><signal id="A1_SPECSIG" negated="ON"/><signal id="A6_SPECSIG"/><signal id="A3_SPECSIG"/><signal id="A2_SPECSIG" negated="ON"/><signal id="AUTO_CONFIG_DONE0_SPECSIG"/><signal id="AUTO_CONFIG_DONE1_SPECSIG" negated="ON"/><signal id="IDE_BASEADR3_SPECSIG"/><signal id="autoconfig"/><signal id="D11PIN_SPECSIG" negated="ON"/></pterm><pterm id="FB3_17_4"><signal id="ideide_CLKF_SPECSIG"/></pterm><pterm id="FB3_18_1"><signal id="RESET" negated="ON"/><signal id="IDE_BASEADR2_SPECSIG" negated="ON"/></pterm><pterm id="FB3_18_2"><signal id="UDS" negated="ON"/><signal id="RW" negated="ON"/><signal id="AS" negated="ON"/><signal id="A5_SPECSIG" negated="ON"/><signal id="A4_SPECSIG" negated="ON"/><signal id="A1_SPECSIG" negated="ON"/><signal id="A6_SPECSIG"/><signal id="A3_SPECSIG"/><signal id="A2_SPECSIG" negated="ON"/><signal id="AUTO_CONFIG_DONE0_SPECSIG"/><signal id="AUTO_CONFIG_DONE1_SPECSIG" negated="ON"/><signal id="IDE_BASEADR2_SPECSIG" negated="ON"/><signal id="autoconfig"/><signal id="D10PIN_SPECSIG"/></pterm><pterm id="FB3_18_3"><signal id="RESET"/><signal id="UDS" negated="ON"/><signal id="RW" negated="ON"/><signal id="AS" negated="ON"/><signal id="A5_SPECSIG" negated="ON"/><signal id="A4_SPECSIG" negated="ON"/><signal id="A1_SPECSIG" negated="ON"/><signal id="A6_SPECSIG"/><signal id="A3_SPECSIG"/><signal id="A2_SPECSIG" negated="ON"/><signal id="AUTO_CONFIG_DONE0_SPECSIG"/><signal id="AUTO_CONFIG_DONE1_SPECSIG" negated="ON"/><signal id="IDE_BASEADR2_SPECSIG"/><signal id="autoconfig"/><signal id="D10PIN_SPECSIG" negated="ON"/></pterm><pterm id="FB3_18_4"><signal id="ideide_CLKF_SPECSIG"/></pterm><equation id="D2_SPECSIG" userloc="P39"><d2><eq_pterm ptindx="VCC"/></d2><oe><eq_pterm ptindx="FB3_1_1"/></oe></equation><equation id="D10_SPECSIG" userloc="P41"><d2><eq_pterm ptindx="VCC"/></d2><oe><eq_pterm ptindx="FB3_3_1"/></oe></equation><equation id="D12_SPECSIG" userloc="P44"><d2><eq_pterm ptindx="FB3_4_1"/></d2><oe><eq_pterm ptindx="FB3_4_2"/></oe></equation><equation id="D14_SPECSIG" userloc="P46"><d2><eq_pterm ptindx="FB3_7_1"/></d2><oe><eq_pterm ptindx="FB3_7_2"/></oe></equation><equation id="D9_SPECSIG" userloc="P40"><d2><eq_pterm ptindx="VCC"/></d2><oe><eq_pterm ptindx="FB3_9_1"/></oe></equation><equation id="D15_SPECSIG" userloc="P48"><d2><eq_pterm ptindx="FB3_10_1"/></d2><oe><eq_pterm ptindx="FB3_10_2"/></oe></equation><equation id="D11_SPECSIG" userloc="P43"><d2><eq_pterm ptindx="VCC"/></d2><oe><eq_pterm ptindx="FB3_11_1"/></oe></equation><equation id="D13_SPECSIG" userloc="P45"><d2><eq_pterm ptindx="FB3_12_1"/></d2><oe><eq_pterm ptindx="FB3_12_2"/></oe></equation><equation id="AUTO_CONFIG_DONE1_SPECSIG" regUse="D"><d2><eq_pterm ptindx="FB3_15_1"/></d2><clk><eq_pterm ptindx="FB3_15_2"/></clk><reset><fastsig signal="RESET"/></reset><prld ptindx="GND"/></equation><equation id="AUTO_CONFIG_DONE_CYCLE1_SPECSIG" regUse="D"><d2><eq_pterm ptindx="FB3_16_1"/><eq_pterm ptindx="FB3_16_2"/></d2><clk><eq_pterm ptindx="FB3_16_3"/></clk><prld ptindx="GND"/></equation><equation id="IDE_BASEADR3_SPECSIG" regUse="T"><d2><eq_pterm ptindx="FB3_17_1"/><eq_pterm ptindx="FB3_17_2"/><eq_pterm ptindx="FB3_17_3"/></d2><clk><eq_pterm ptindx="FB3_17_4"/></clk><prld ptindx="GND"/></equation><equation id="IDE_BASEADR2_SPECSIG" regUse="T"><d2><eq_pterm ptindx="FB3_18_1"/><eq_pterm ptindx="FB3_18_2"/><eq_pterm ptindx="FB3_18_3"/></d2><clk><eq_pterm ptindx="FB3_18_4"/></clk><prld ptindx="GND"/></equation></fblock><fblock id="FB4" inputUse="24" pinUse="0"><macrocell id="FB4_MC1" pin="FB4_MC1_PIN118" sigUse="19" signal="ide"><pterms pt1="FB4_1_1" pt2="FB4_1_2" pt3="FB4_1_3" pt4="FB4_1_4" pt5="FB4_1_5"/></macrocell><macrocell id="FB4_MC2" pin="FB4_MC2_PIN126"><pterms pt1="FB4_2_1" pt2="FB4_2_2" pt3="FB4_2_3" pt4="FB4_2_4" pt5="FB4_2_5"/></macrocell><macrocell id="FB4_MC3" pin="FB4_MC3_PIN133"><pterms pt1="FB4_3_1" pt2="FB4_3_2" pt3="FB4_3_3"/></macrocell><macrocell id="FB4_MC4"/><macrocell id="FB4_MC5" pin="FB4_MC5_PIN128"/><macrocell id="FB4_MC6" pin="FB4_MC6_PIN129"/><macrocell id="FB4_MC7"/><macrocell id="FB4_MC8" pin="FB4_MC8_PIN130"/><macrocell id="FB4_MC9" pin="FB4_MC9_PIN131"/><macrocell id="FB4_MC10" pin="FB4_MC10_PIN135"/><macrocell id="FB4_MC11" pin="FB4_MC11_PIN132"/><macrocell id="FB4_MC12" pin="FB4_MC12_PIN134"/><macrocell id="FB4_MC13" pin="FB4_MC13_PIN137"/><macrocell id="FB4_MC14" pin="FB4_MC14_PIN136"/><macrocell id="FB4_MC15" pin="FB4_MC15_PIN138"/><macrocell id="FB4_MC16" pin="FB4_MC16_PIN139" sigUse="2" signal="ideide_CLKF_SPECSIG"><pterms pt1="FB4_16_1" pt2="FB4_16_2"/></macrocell><macrocell id="FB4_MC17" pin="FB4_MC17_PIN140" sigUse="13" signal="autoconfig"><pterms pt1="FB4_17_1" pt2="FB4_17_2" pt3="FB4_17_3" pt4="FB4_17_4" pt5="FB4_17_5"/></macrocell><macrocell id="FB4_MC18"><pterms pt1="FB4_18_1" pt2="FB4_18_2" pt3="FB4_18_3" pt4="FB4_18_4" pt5="FB4_18_5"/></macrocell><fbinput id="FB4_I1" signal="AUTO_CONFIG_DONE0_SPECSIG"/><fbinput id="FB4_I2" signal="AUTO_CONFIG_DONE1_SPECSIG"/><fbinput id="FB4_I3" signal="AUTO_CONFIG_DONE2_SPECSIG"/><fbinput id="FB4_I4" signal="A16_SPECSIG"/><fbinput id="FB4_I5" signal="A17_SPECSIG"/><fbinput id="FB4_I6" signal="A18_SPECSIG"/><fbinput id="FB4_I7" signal="A19_SPECSIG"/><fbinput id="FB4_I8" signal="A20_SPECSIG"/><fbinput id="FB4_I9" signal="A21_SPECSIG"/><fbinput id="FB4_I10" signal="A22_SPECSIG"/><fbinput id="FB4_I11" signal="A23_SPECSIG"/><fbinput id="FB4_I12" signal="BERR"/><fbinput id="FB4_I13" signal="C1"/><fbinput id="FB4_I14" signal="C3"/><fbinput id="FB4_I15" signal="IDE_BASEADR0_SPECSIG"/><fbinput id="FB4_I16" signal="IDE_BASEADR1_SPECSIG"/><fbinput id="FB4_I17" signal="IDE_BASEADR2_SPECSIG"/><fbinput id="FB4_I18" signal="IDE_BASEADR3_SPECSIG"/><fbinput id="FB4_I19" signal="IDE_BASEADR4_SPECSIG"/><fbinput id="FB4_I20" signal="IDE_BASEADR5_SPECSIG"/><fbinput id="FB4_I21" signal="IDE_BASEADR6_SPECSIG"/><fbinput id="FB4_I22" signal="IDE_BASEADR7_SPECSIG"/><fbinput id="FB4_I23" signal="SHUT_UP1_SPECSIG"/><fbinput id="FB4_I24" signal="ideide_CLKF_SPECSIG"/><pterm id="FB4_1_1"><signal id="SHUT_UP1_SPECSIG"/></pterm><pterm id="FB4_1_2"><signal id="BERR" negated="ON"/></pterm><pterm id="FB4_1_3"><signal id="A19_SPECSIG"/><signal id="IDE_BASEADR3_SPECSIG" negated="ON"/></pterm><pterm id="FB4_1_4"><signal id="A19_SPECSIG" negated="ON"/><signal id="IDE_BASEADR3_SPECSIG"/></pterm><pterm id="FB4_1_5"><signal id="ideide_CLKF_SPECSIG"/></pterm><pterm id="FB4_2_1"><signal id="A23_SPECSIG"/><signal id="IDE_BASEADR7_SPECSIG" negated="ON"/></pterm><pterm id="FB4_2_2"><signal id="A23_SPECSIG" negated="ON"/><signal id="IDE_BASEADR7_SPECSIG"/></pterm><pterm id="FB4_2_3"><signal id="A22_SPECSIG"/><signal id="IDE_BASEADR6_SPECSIG" negated="ON"/></pterm><pterm id="FB4_2_4"><signal id="A22_SPECSIG" negated="ON"/><signal id="IDE_BASEADR6_SPECSIG"/></pterm><pterm id="FB4_2_5"><signal id="IDE_BASEADR1_SPECSIG"/><signal id="A17_SPECSIG" negated="ON"/></pterm><pterm id="FB4_3_1"><signal id="A21_SPECSIG" negated="ON"/><signal id="IDE_BASEADR5_SPECSIG"/></pterm><pterm id="FB4_3_2"><signal id="IDE_BASEADR4_SPECSIG"/><signal id="A20_SPECSIG" negated="ON"/></pterm><pterm id="FB4_3_3"><signal id="IDE_BASEADR4_SPECSIG" negated="ON"/><signal id="A20_SPECSIG"/></pterm><pterm id="FB4_16_1"><signal id="C3"/></pterm><pterm id="FB4_16_2"><signal id="C1"/></pterm><pterm id="FB4_17_1"><signal id="A23_SPECSIG"/><signal id="A22_SPECSIG"/><signal id="A21_SPECSIG"/><signal id="A19_SPECSIG"/><signal id="AUTO_CONFIG_DONE0_SPECSIG" negated="ON"/><signal id="BERR"/><signal id="A17_SPECSIG" negated="ON"/><signal id="A16_SPECSIG" negated="ON"/><signal id="A20_SPECSIG" negated="ON"/><signal id="A18_SPECSIG" negated="ON"/></pterm><pterm id="FB4_17_2"><signal id="A23_SPECSIG"/><signal id="A22_SPECSIG"/><signal id="A21_SPECSIG"/><signal id="A19_SPECSIG"/><signal id="AUTO_CONFIG_DONE1_SPECSIG" negated="ON"/><signal id="BERR"/><signal id="A17_SPECSIG" negated="ON"/><signal id="A16_SPECSIG" negated="ON"/><signal id="A20_SPECSIG" negated="ON"/><signal id="A18_SPECSIG" negated="ON"/></pterm><pterm id="FB4_17_3"><signal id="A23_SPECSIG"/><signal id="A22_SPECSIG"/><signal id="A21_SPECSIG"/><signal id="A19_SPECSIG"/><signal id="AUTO_CONFIG_DONE2_SPECSIG" negated="ON"/><signal id="BERR"/><signal id="A17_SPECSIG" negated="ON"/><signal id="A16_SPECSIG" negated="ON"/><signal id="A20_SPECSIG" negated="ON"/><signal id="A18_SPECSIG" negated="ON"/></pterm><pterm id="FB4_17_4"><signal id="ideide_CLKF_SPECSIG"/></pterm><pterm id="FB4_17_5"><signal id="A21_SPECSIG"/><signal id="IDE_BASEADR5_SPECSIG" negated="ON"/></pterm><pterm id="FB4_18_1"><signal id="IDE_BASEADR0_SPECSIG"/><signal id="A16_SPECSIG" negated="ON"/></pterm><pterm id="FB4_18_2"><signal id="IDE_BASEADR0_SPECSIG" negated="ON"/><signal id="A16_SPECSIG"/></pterm><pterm id="FB4_18_3"><signal id="IDE_BASEADR1_SPECSIG" negated="ON"/><signal id="A17_SPECSIG"/></pterm><pterm id="FB4_18_4"><signal id="IDE_BASEADR2_SPECSIG"/><signal id="A18_SPECSIG" negated="ON"/></pterm><pterm id="FB4_18_5"><signal id="IDE_BASEADR2_SPECSIG" negated="ON"/><signal id="A18_SPECSIG"/></pterm><equation id="ide" negated="ON" regUse="D"><d2><eq_pterm ptindx="FB4_1_1"/><eq_pterm ptindx="FB4_1_2"/><eq_pterm ptindx="FB4_1_3"/><eq_pterm ptindx="FB4_1_4"/><eq_pterm import="1" ptindx="FB4_2_1"/><eq_pterm import="1" ptindx="FB4_2_2"/><eq_pterm import="1" ptindx="FB4_2_3"/><eq_pterm import="1" ptindx="FB4_2_4"/><eq_pterm import="1" ptindx="FB4_2_5"/><eq_pterm import="1" ptindx="FB4_3_1"/><eq_pterm import="1" ptindx="FB4_3_2"/><eq_pterm import="1" ptindx="FB4_3_3"/><eq_pterm import="1" ptindx="FB4_18_1"/><eq_pterm import="1" ptindx="FB4_18_2"/><eq_pterm import="1" ptindx="FB4_18_3"/><eq_pterm import="1" ptindx="FB4_18_4"/><eq_pterm import="1" ptindx="FB4_18_5"/><eq_pterm import="1" ptindx="FB4_17_5"/></d2><clk><eq_pterm ptindx="FB4_1_5"/></clk><prld ptindx="GND"/></equation><equation id="ideide_CLKF_SPECSIG" negated="ON"><d1><eq_pterm ptindx="FB4_16_1"/></d1><d2><eq_pterm ptindx="FB4_16_2"/></d2></equation><equation id="autoconfig" regUse="D"><d2><eq_pterm ptindx="FB4_17_1"/><eq_pterm ptindx="FB4_17_2"/><eq_pterm ptindx="FB4_17_3"/></d2><clk><eq_pterm ptindx="FB4_17_4"/></clk><prld ptindx="GND"/></equation></fblock><fblock id="FB5" inputUse="23" pinUse="10"><macrocell id="FB5_MC1"/><macrocell id="FB5_MC2" pin="FB5_MC2_PIN52"/><macrocell id="FB5_MC3" pin="FB5_MC3_PIN59"/><macrocell id="FB5_MC4"/><macrocell id="FB5_MC5" pin="FB5_MC5_PIN53"/><macrocell id="FB5_MC6" pin="FB5_MC6_PIN54"/><macrocell id="FB5_MC7" pin="FB5_MC7_PIN66"/><macrocell id="FB5_MC8" pin="FB5_MC8_PIN56"/><macrocell id="FB5_MC9" pin="FB5_MC9_PIN57"/><macrocell id="FB5_MC10" pin="FB5_MC10_PIN68" sigUse="0" signal="ROM_B0_SPECSIG"/><macrocell id="FB5_MC11" pin="FB5_MC11_PIN58"/><macrocell id="FB5_MC12" pin="FB5_MC12_PIN60"/><macrocell id="FB5_MC13" pin="FB5_MC13_PIN70" sigUse="15" signal="SHUT_UP1_SPECSIG"><pterms pt1="FB5_13_1" pt2="FB5_13_2" pt3="FB5_13_3"/></macrocell><macrocell id="FB5_MC14" pin="FB5_MC14_PIN61" sigUse="16" signal="IDE_BASEADR5_SPECSIG"><pterms pt1="FB5_14_1" pt2="FB5_14_2" pt3="FB5_14_3" pt4="FB5_14_4"/></macrocell><macrocell id="FB5_MC15" pin="FB5_MC15_PIN64" sigUse="16" signal="IDE_BASEADR4_SPECSIG"><pterms pt1="FB5_15_1" pt2="FB5_15_2" pt3="FB5_15_3" pt4="FB5_15_4"/></macrocell><macrocell id="FB5_MC16" sigUse="16" signal="IDE_BASEADR1_SPECSIG"><pterms pt1="FB5_16_1" pt2="FB5_16_2" pt3="FB5_16_3" pt4="FB5_16_4"/></macrocell><macrocell id="FB5_MC17" pin="FB5_MC17_PIN69" sigUse="0" signal="ROM_B1_SPECSIG"/><macrocell id="FB5_MC18" sigUse="16" signal="IDE_BASEADR0_SPECSIG"><pterms pt1="FB5_18_1" pt2="FB5_18_2" pt3="FB5_18_3" pt4="FB5_18_4"/></macrocell><fbinput id="FB5_I1" signal="AS"/><fbinput id="FB5_I2" signal="AUTO_CONFIG_DONE0_SPECSIG"/><fbinput id="FB5_I3" signal="AUTO_CONFIG_DONE1_SPECSIG"/><fbinput id="FB5_I4" signal="A1_SPECSIG"/><fbinput id="FB5_I5" signal="A2_SPECSIG"/><fbinput id="FB5_I6" signal="A3_SPECSIG"/><fbinput id="FB5_I7" signal="A4_SPECSIG"/><fbinput id="FB5_I8" signal="A5_SPECSIG"/><fbinput id="FB5_I9" signal="A6_SPECSIG"/><fbinput id="FB5_I10" signal="IDE_BASEADR0_SPECSIG"/><fbinput id="FB5_I11" signal="IDE_BASEADR1_SPECSIG"/><fbinput id="FB5_I12" signal="IDE_BASEADR4_SPECSIG"/><fbinput id="FB5_I13" signal="IDE_BASEADR5_SPECSIG"/><fbinput fbk="PIN" id="FB5_I14" signal="D12PIN_SPECSIG"/><fbinput fbk="PIN" id="FB5_I15" signal="D13PIN_SPECSIG"/><fbinput fbk="PIN" id="FB5_I16" signal="D8PIN_SPECSIG"/><fbinput fbk="PIN" id="FB5_I17" signal="D9PIN_SPECSIG"/><fbinput id="FB5_I18" signal="RESET"/><fbinput id="FB5_I19" signal="RW"/><fbinput id="FB5_I20" signal="SHUT_UP1_SPECSIG"/><fbinput id="FB5_I21" signal="UDS"/><fbinput id="FB5_I22" signal="autoconfig"/><fbinput id="FB5_I23" signal="ideide_CLKF_SPECSIG"/><pterm id="FB5_13_1"><signal id="RESET"/><signal id="SHUT_UP1_SPECSIG" negated="ON"/></pterm><pterm id="FB5_13_2"><signal id="RESET"/><signal id="UDS" negated="ON"/><signal id="RW" negated="ON"/><signal id="AS" negated="ON"/><signal id="A5_SPECSIG" negated="ON"/><signal id="A4_SPECSIG" negated="ON"/><signal id="A1_SPECSIG" negated="ON"/><signal id="A6_SPECSIG"/><signal id="A3_SPECSIG"/><signal id="A2_SPECSIG" negated="ON"/><signal id="AUTO_CONFIG_DONE0_SPECSIG"/><signal id="AUTO_CONFIG_DONE1_SPECSIG" negated="ON"/><signal id="autoconfig"/></pterm><pterm id="FB5_13_3"><signal id="ideide_CLKF_SPECSIG"/></pterm><pterm id="FB5_14_1"><signal id="RESET" negated="ON"/><signal id="IDE_BASEADR5_SPECSIG" negated="ON"/></pterm><pterm id="FB5_14_2"><signal id="UDS" negated="ON"/><signal id="RW" negated="ON"/><signal id="AS" negated="ON"/><signal id="A5_SPECSIG" negated="ON"/><signal id="A4_SPECSIG" negated="ON"/><signal id="A1_SPECSIG" negated="ON"/><signal id="A6_SPECSIG"/><signal id="A3_SPECSIG"/><signal id="A2_SPECSIG" negated="ON"/><signal id="AUTO_CONFIG_DONE0_SPECSIG"/><signal id="AUTO_CONFIG_DONE1_SPECSIG" negated="ON"/><signal id="IDE_BASEADR5_SPECSIG" negated="ON"/><signal id="autoconfig"/><signal id="D13PIN_SPECSIG"/></pterm><pterm id="FB5_14_3"><signal id="RESET"/><signal id="UDS" negated="ON"/><signal id="RW" negated="ON"/><signal id="AS" negated="ON"/><signal id="A5_SPECSIG" negated="ON"/><signal id="A4_SPECSIG" negated="ON"/><signal id="A1_SPECSIG" negated="ON"/><signal id="A6_SPECSIG"/><signal id="A3_SPECSIG"/><signal id="A2_SPECSIG" negated="ON"/><signal id="AUTO_CONFIG_DONE0_SPECSIG"/><signal id="AUTO_CONFIG_DONE1_SPECSIG" negated="ON"/><signal id="IDE_BASEADR5_SPECSIG"/><signal id="autoconfig"/><signal id="D13PIN_SPECSIG" negated="ON"/></pterm><pterm id="FB5_14_4"><signal id="ideide_CLKF_SPECSIG"/></pterm><pterm id="FB5_15_1"><signal id="RESET" negated="ON"/><signal id="IDE_BASEADR4_SPECSIG" negated="ON"/></pterm><pterm id="FB5_15_2"><signal id="UDS" negated="ON"/><signal id="RW" negated="ON"/><signal id="AS" negated="ON"/><signal id="A5_SPECSIG" negated="ON"/><signal id="A4_SPECSIG" negated="ON"/><signal id="A1_SPECSIG" negated="ON"/><signal id="A6_SPECSIG"/><signal id="A3_SPECSIG"/><signal id="A2_SPECSIG" negated="ON"/><signal id="AUTO_CONFIG_DONE0_SPECSIG"/><signal id="AUTO_CONFIG_DONE1_SPECSIG" negated="ON"/><signal id="IDE_BASEADR4_SPECSIG" negated="ON"/><signal id="autoconfig"/><signal id="D12PIN_SPECSIG"/></pterm><pterm id="FB5_15_3"><signal id="RESET"/><signal id="UDS" negated="ON"/><signal id="RW" negated="ON"/><signal id="AS" negated="ON"/><signal id="A5_SPECSIG" negated="ON"/><signal id="A4_SPECSIG" negated="ON"/><signal id="A1_SPECSIG" negated="ON"/><signal id="A6_SPECSIG"/><signal id="A3_SPECSIG"/><signal id="A2_SPECSIG" negated="ON"/><signal id="AUTO_CONFIG_DONE0_SPECSIG"/><signal id="AUTO_CONFIG_DONE1_SPECSIG" negated="ON"/><signal id="IDE_BASEADR4_SPECSIG"/><signal id="autoconfig"/><signal id="D12PIN_SPECSIG" negated="ON"/></pterm><pterm id="FB5_15_4"><signal id="ideide_CLKF_SPECSIG"/></pterm><pterm id="FB5_16_1"><signal id="RESET" negated="ON"/><signal id="IDE_BASEADR1_SPECSIG" negated="ON"/></pterm><pterm id="FB5_16_2"><signal id="UDS" negated="ON"/><signal id="RW" negated="ON"/><signal id="AS" negated="ON"/><signal id="A5_SPECSIG" negated="ON"/><signal id="A4_SPECSIG" negated="ON"/><signal id="A1_SPECSIG" negated="ON"/><signal id="A6_SPECSIG"/><signal id="A3_SPECSIG"/><signal id="A2_SPECSIG" negated="ON"/><signal id="AUTO_CONFIG_DONE0_SPECSIG"/><signal id="AUTO_CONFIG_DONE1_SPECSIG" negated="ON"/><signal id="IDE_BASEADR1_SPECSIG" negated="ON"/><signal id="autoconfig"/><signal id="D9PIN_SPECSIG"/></pterm><pterm id="FB5_16_3"><signal id="RESET"/><signal id="UDS" negated="ON"/><signal id="RW" negated="ON"/><signal id="AS" negated="ON"/><signal id="A5_SPECSIG" negated="ON"/><signal id="A4_SPECSIG" negated="ON"/><signal id="A1_SPECSIG" negated="ON"/><signal id="A6_SPECSIG"/><signal id="A3_SPECSIG"/><signal id="A2_SPECSIG" negated="ON"/><signal id="AUTO_CONFIG_DONE0_SPECSIG"/><signal id="AUTO_CONFIG_DONE1_SPECSIG" negated="ON"/><signal id="IDE_BASEADR1_SPECSIG"/><signal id="autoconfig"/><signal id="D9PIN_SPECSIG" negated="ON"/></pterm><pterm id="FB5_16_4"><signal id="ideide_CLKF_SPECSIG"/></pterm><pterm id="FB5_18_1"><signal id="RESET" negated="ON"/><signal id="IDE_BASEADR0_SPECSIG" negated="ON"/></pterm><pterm id="FB5_18_2"><signal id="UDS" negated="ON"/><signal id="RW" negated="ON"/><signal id="AS" negated="ON"/><signal id="A5_SPECSIG" negated="ON"/><signal id="A4_SPECSIG" negated="ON"/><signal id="A1_SPECSIG" negated="ON"/><signal id="A6_SPECSIG"/><signal id="A3_SPECSIG"/><signal id="A2_SPECSIG" negated="ON"/><signal id="AUTO_CONFIG_DONE0_SPECSIG"/><signal id="AUTO_CONFIG_DONE1_SPECSIG" negated="ON"/><signal id="IDE_BASEADR0_SPECSIG" negated="ON"/><signal id="autoconfig"/><signal id="D8PIN_SPECSIG"/></pterm><pterm id="FB5_18_3"><signal id="RESET"/><signal id="UDS" negated="ON"/><signal id="RW" negated="ON"/><signal id="AS" negated="ON"/><signal id="A5_SPECSIG" negated="ON"/><signal id="A4_SPECSIG" negated="ON"/><signal id="A1_SPECSIG" negated="ON"/><signal id="A6_SPECSIG"/><signal id="A3_SPECSIG"/><signal id="A2_SPECSIG" negated="ON"/><signal id="AUTO_CONFIG_DONE0_SPECSIG"/><signal id="AUTO_CONFIG_DONE1_SPECSIG" negated="ON"/><signal id="IDE_BASEADR0_SPECSIG"/><signal id="autoconfig"/><signal id="D8PIN_SPECSIG" negated="ON"/></pterm><pterm id="FB5_18_4"><signal id="ideide_CLKF_SPECSIG"/></pterm><equation id="ROM_B0_SPECSIG" userloc="P68"><d2><eq_pterm ptindx="GND"/></d2></equation><equation id="SHUT_UP1_SPECSIG" negated="ON" regUse="D"><d2><eq_pterm ptindx="FB5_13_1"/><eq_pterm ptindx="FB5_13_2"/></d2><clk><eq_pterm ptindx="FB5_13_3"/></clk><prld ptindx="GND"/></equation><equation id="IDE_BASEADR5_SPECSIG" regUse="T"><d2><eq_pterm ptindx="FB5_14_1"/><eq_pterm ptindx="FB5_14_2"/><eq_pterm ptindx="FB5_14_3"/></d2><clk><eq_pterm ptindx="FB5_14_4"/></clk><prld ptindx="GND"/></equation><equation id="IDE_BASEADR4_SPECSIG" regUse="T"><d2><eq_pterm ptindx="FB5_15_1"/><eq_pterm ptindx="FB5_15_2"/><eq_pterm ptindx="FB5_15_3"/></d2><clk><eq_pterm ptindx="FB5_15_4"/></clk><prld ptindx="GND"/></equation><equation id="IDE_BASEADR1_SPECSIG" regUse="T"><d2><eq_pterm ptindx="FB5_16_1"/><eq_pterm ptindx="FB5_16_2"/><eq_pterm ptindx="FB5_16_3"/></d2><clk><eq_pterm ptindx="FB5_16_4"/></clk><prld ptindx="GND"/></equation><equation id="ROM_B1_SPECSIG" userloc="P69"><d2><eq_pterm ptindx="GND"/></d2></equation><equation id="IDE_BASEADR0_SPECSIG" regUse="T"><d2><eq_pterm ptindx="FB5_18_1"/><eq_pterm ptindx="FB5_18_2"/><eq_pterm ptindx="FB5_18_3"/></d2><clk><eq_pterm ptindx="FB5_18_4"/></clk><prld ptindx="GND"/></equation></fblock><fblock id="FB6" inputUse="15" pinUse="0"><macrocell id="FB6_MC1"/><macrocell id="FB6_MC2" pin="FB6_MC2_PIN106"/><macrocell id="FB6_MC3"/><macrocell id="FB6_MC4" pin="FB6_MC4_PIN111"/><macrocell id="FB6_MC5" pin="FB6_MC5_PIN110"/><macrocell id="FB6_MC6" pin="FB6_MC6_PIN112"/><macrocell id="FB6_MC7"/><macrocell id="FB6_MC8" pin="FB6_MC8_PIN113"/><macrocell id="FB6_MC9" pin="FB6_MC9_PIN116"/><macrocell id="FB6_MC10" pin="FB6_MC10_PIN115"/><macrocell id="FB6_MC11" pin="FB6_MC11_PIN119"/><macrocell id="FB6_MC12" pin="FB6_MC12_PIN120"/><macrocell id="FB6_MC13"/><macrocell id="FB6_MC14" pin="FB6_MC14_PIN121"/><macrocell id="FB6_MC15" pin="FB6_MC15_PIN124"/><macrocell id="FB6_MC16" pin="FB6_MC16_PIN117"><pterms pt1="FB6_16_1" pt2="FB6_16_2" pt3="FB6_16_3" pt4="FB6_16_4"/></macrocell><macrocell id="FB6_MC17" pin="FB6_MC17_PIN125" sigUse="15" signal="D15_BUFR_SPECSIG"><pterms pt1="FB6_17_1" pt2="FB6_17_2" pt3="FB6_17_3" pt4="FB6_17_4" pt5="FB6_17_5"/></macrocell><macrocell id="FB6_MC18"><pterms pt1="FB6_18_1" pt2="FB6_18_2" pt3="FB6_18_3" pt4="FB6_18_4" pt5="FB6_18_5"/></macrocell><fbinput id="FB6_I1" signal="AS"/><fbinput id="FB6_I2" signal="AUTO_CONFIG_DONE0_SPECSIG"/><fbinput id="FB6_I3" signal="AUTO_CONFIG_DONE1_SPECSIG"/><fbinput id="FB6_I4" signal="AUTO_CONFIG_DONE2_SPECSIG"/><fbinput id="FB6_I5" signal="A1_SPECSIG"/><fbinput id="FB6_I6" signal="A2_SPECSIG"/><fbinput id="FB6_I7" signal="A3_SPECSIG"/><fbinput id="FB6_I8" signal="A4_SPECSIG"/><fbinput id="FB6_I9" signal="A5_SPECSIG"/><fbinput id="FB6_I10" signal="A6_SPECSIG"/><fbinput id="FB6_I11" signal="D15_SPECSIG"/><fbinput id="FB6_I12" signal="RESET"/><fbinput id="FB6_I13" signal="RW"/><fbinput id="FB6_I14" signal="autoconfig"/><fbinput id="FB6_I15" signal="ideide_CLKF_SPECSIG"/><pterm id="FB6_16_1"><signal id="RESET"/><signal id="D15_SPECSIG" negated="ON"/><signal id="AUTO_CONFIG_DONE0_SPECSIG"/><signal id="AUTO_CONFIG_DONE1_SPECSIG"/><signal id="AUTO_CONFIG_DONE2_SPECSIG"/></pterm><pterm id="FB6_16_2"><signal id="RESET"/><signal id="RW"/><signal id="AS" negated="ON"/><signal id="A5_SPECSIG" negated="ON"/><signal id="A1_SPECSIG"/><signal id="A6_SPECSIG" negated="ON"/><signal id="A3_SPECSIG" negated="ON"/><signal id="AUTO_CONFIG_DONE0_SPECSIG" negated="ON"/><signal id="autoconfig"/></pterm><pterm id="FB6_16_3"><signal id="RESET"/><signal id="RW"/><signal id="AS" negated="ON"/><signal id="A5_SPECSIG" negated="ON"/><signal id="A4_SPECSIG" negated="ON"/><signal id="A6_SPECSIG"/><signal id="A3_SPECSIG" negated="ON"/><signal id="A2_SPECSIG" negated="ON"/><signal id="AUTO_CONFIG_DONE0_SPECSIG" negated="ON"/><signal id="autoconfig"/></pterm><pterm id="FB6_16_4"><signal id="RESET"/><signal id="RW"/><signal id="AS" negated="ON"/><signal id="A5_SPECSIG" negated="ON"/><signal id="A4_SPECSIG" negated="ON"/><signal id="A6_SPECSIG"/><signal id="A3_SPECSIG" negated="ON"/><signal id="A2_SPECSIG" negated="ON"/><signal id="AUTO_CONFIG_DONE1_SPECSIG" negated="ON"/><signal id="autoconfig"/></pterm><pterm id="FB6_17_1"><signal id="RESET"/><signal id="D15_SPECSIG" negated="ON"/><signal id="RW" negated="ON"/></pterm><pterm id="FB6_17_2"><signal id="RESET"/><signal id="D15_SPECSIG" negated="ON"/><signal id="AS"/></pterm><pterm id="FB6_17_3"><signal id="RESET"/><signal id="D15_SPECSIG" negated="ON"/><signal id="autoconfig" negated="ON"/></pterm><pterm id="FB6_17_4"><signal id="RESET"/><signal id="RW"/><signal id="AS" negated="ON"/><signal id="A5_SPECSIG" negated="ON"/><signal id="A1_SPECSIG"/><signal id="A6_SPECSIG" negated="ON"/><signal id="A3_SPECSIG" negated="ON"/><signal id="A2_SPECSIG" negated="ON"/><signal id="AUTO_CONFIG_DONE1_SPECSIG" negated="ON"/><signal id="autoconfig"/></pterm><pterm id="FB6_17_5"><signal id="ideide_CLKF_SPECSIG"/></pterm><pterm id="FB6_18_1"><signal id="RESET"/><signal id="RW"/><signal id="AS" negated="ON"/><signal id="A5_SPECSIG" negated="ON"/><signal id="A4_SPECSIG" negated="ON"/><signal id="A6_SPECSIG"/><signal id="A3_SPECSIG" negated="ON"/><signal id="A2_SPECSIG" negated="ON"/><signal id="AUTO_CONFIG_DONE2_SPECSIG" negated="ON"/><signal id="autoconfig"/></pterm><pterm id="FB6_18_2"><signal id="RESET"/><signal id="RW"/><signal id="AS" negated="ON"/><signal id="A5_SPECSIG" negated="ON"/><signal id="A1_SPECSIG"/><signal id="A6_SPECSIG" negated="ON"/><signal id="A3_SPECSIG" negated="ON"/><signal id="AUTO_CONFIG_DONE1_SPECSIG"/><signal id="AUTO_CONFIG_DONE2_SPECSIG" negated="ON"/><signal id="autoconfig"/></pterm><pterm id="FB6_18_3"><signal id="RESET"/><signal id="RW"/><signal id="AS" negated="ON"/><signal id="A5_SPECSIG" negated="ON"/><signal id="A4_SPECSIG"/><signal id="A1_SPECSIG"/><signal id="A6_SPECSIG" negated="ON"/><signal id="A2_SPECSIG"/><signal id="AUTO_CONFIG_DONE0_SPECSIG"/><signal id="AUTO_CONFIG_DONE1_SPECSIG" negated="ON"/><signal id="autoconfig"/></pterm><pterm id="FB6_18_4"><signal id="RESET"/><signal id="RW"/><signal id="AS" negated="ON"/><signal id="A5_SPECSIG"/><signal id="A4_SPECSIG" negated="ON"/><signal id="A1_SPECSIG" negated="ON"/><signal id="A6_SPECSIG" negated="ON"/><signal id="A3_SPECSIG" negated="ON"/><signal id="A2_SPECSIG"/><signal id="AUTO_CONFIG_DONE0_SPECSIG"/><signal id="AUTO_CONFIG_DONE1_SPECSIG" negated="ON"/><signal id="autoconfig"/></pterm><pterm id="FB6_18_5"><signal id="RESET"/><signal id="RW"/><signal id="AS" negated="ON"/><signal id="A5_SPECSIG" negated="ON"/><signal id="A4_SPECSIG"/><signal id="A1_SPECSIG" negated="ON"/><signal id="A6_SPECSIG" negated="ON"/><signal id="A3_SPECSIG"/><signal id="A2_SPECSIG" negated="ON"/><signal id="AUTO_CONFIG_DONE0_SPECSIG"/><signal id="AUTO_CONFIG_DONE1_SPECSIG" negated="ON"/><signal id="autoconfig"/></pterm><equation id="D15_BUFR_SPECSIG" negated="ON" regUse="D"><d2><eq_pterm ptindx="FB6_17_1"/><eq_pterm ptindx="FB6_17_2"/><eq_pterm ptindx="FB6_17_3"/><eq_pterm ptindx="FB6_17_4"/><eq_pterm import="1" ptindx="FB6_16_1"/><eq_pterm import="1" ptindx="FB6_16_2"/><eq_pterm import="1" ptindx="FB6_16_3"/><eq_pterm import="1" ptindx="FB6_16_4"/><eq_pterm import="1" ptindx="FB6_18_1"/><eq_pterm import="1" ptindx="FB6_18_2"/><eq_pterm import="1" ptindx="FB6_18_3"/><eq_pterm import="1" ptindx="FB6_18_4"/><eq_pterm import="1" ptindx="FB6_18_5"/></d2><clk><eq_pterm ptindx="FB6_17_5"/></clk><prld ptindx="GND"/></equation></fblock><fblock id="FB7" inputUse="0" pinUse="8"><macrocell id="FB7_MC1"/><macrocell id="FB7_MC2" pin="FB7_MC2_PIN71"/><macrocell id="FB7_MC3" pin="FB7_MC3_PIN75"/><macrocell id="FB7_MC4"/><macrocell id="FB7_MC5" pin="FB7_MC5_PIN74"/><macrocell id="FB7_MC6" pin="FB7_MC6_PIN76"/><macrocell id="FB7_MC7" pin="FB7_MC7_PIN77"/><macrocell id="FB7_MC8" pin="FB7_MC8_PIN78"/><macrocell id="FB7_MC9" pin="FB7_MC9_PIN80"/><macrocell id="FB7_MC10" pin="FB7_MC10_PIN79"/><macrocell id="FB7_MC11" pin="FB7_MC11_PIN82"/><macrocell id="FB7_MC12" pin="FB7_MC12_PIN85" sigUse="0" signal="DTACK"/><macrocell id="FB7_MC13" pin="FB7_MC13_PIN81"/><macrocell id="FB7_MC14" pin="FB7_MC14_PIN86"/><macrocell id="FB7_MC15" pin="FB7_MC15_PIN87"/><macrocell id="FB7_MC16" pin="FB7_MC16_PIN83"/><macrocell id="FB7_MC17" pin="FB7_MC17_PIN88"/><macrocell id="FB7_MC18"/><equation id="DTACK" userloc="P85"><d2><eq_pterm ptindx="GND"/></d2><oe><eq_pterm ptindx="GND"/></oe></equation></fblock><fblock id="FB8" inputUse="0" pinUse="8"><macrocell id="FB8_MC1"/><macrocell id="FB8_MC2" pin="FB8_MC2_PIN91"/><macrocell id="FB8_MC3" pin="FB8_MC3_PIN95"/><macrocell id="FB8_MC4" pin="FB8_MC4_PIN97"/><macrocell id="FB8_MC5" pin="FB8_MC5_PIN92"/><macrocell id="FB8_MC6" pin="FB8_MC6_PIN93"/><macrocell id="FB8_MC7"/><macrocell id="FB8_MC8" pin="FB8_MC8_PIN94"/><macrocell id="FB8_MC9" pin="FB8_MC9_PIN96"/><macrocell id="FB8_MC10" pin="FB8_MC10_PIN101"/><macrocell id="FB8_MC11" pin="FB8_MC11_PIN98"/><macrocell id="FB8_MC12" pin="FB8_MC12_PIN100"/><macrocell id="FB8_MC13" pin="FB8_MC13_PIN103"/><macrocell id="FB8_MC14" pin="FB8_MC14_PIN102"/><macrocell id="FB8_MC15" pin="FB8_MC15_PIN104"/><macrocell id="FB8_MC16" pin="FB8_MC16_PIN107"/><macrocell id="FB8_MC17" pin="FB8_MC17_PIN105"/><macrocell id="FB8_MC18"/></fblock><vcc/><gnd/><messages><warning>Cpld - Unable to retrieve the path to the iSE Project Repository. Will   use the default filename of 'LAN_IDE_CP.ise'.INFO:Cpld - Inferring BUFG constraint for signal 'CLK_EXT' based upon the LOC   constraint 'P30'. It is recommended that you declare this BUFG explicitedly   in your design. Note that for certain device families the output of a BUFG   constraint can not drive a gated clock, and the BUFG constraint will be   ignored.</warning><warning>Cpld:936 - The output buffer 'SLAVE_OBUF' is missing an input and will   be deleted.</warning><warning>Cpld:936 - The output buffer 'OWN_OBUF' is missing an input and will be   deleted.</warning><warning>Cpld:936 - The output buffer 'OVR_OBUF' is missing an input and will be   deleted.</warning><warning>Cpld:936 - The output buffer 'MTACK_OBUF' is missing an input and will   be deleted.</warning><warning>Cpld:936 - The output buffer 'LAN_WRH_OBUF' is missing an input and will   be deleted.</warning><warning>Cpld:936 - The output buffer 'LAN_RD_OBUF' is missing an input and will   be deleted.</warning><warning>Cpld:936 - The output buffer 'LAN_EN_OBUF' is missing an input and will   be deleted.</warning><warning>Cpld:936 - The output buffer 'LAN_CS_OBUF' is missing an input and will   be deleted.</warning><warning>Cpld:936 - The output buffer 'LAN_CFG&lt;4&gt;_OBUF' is missing an input and   will be deleted.</warning><warning>Cpld:936 - The output buffer 'LAN_CFG&lt;3&gt;_OBUF' is missing an input and   will be deleted.</warning><warning>Cpld:936 - The output buffer 'LAN_CFG&lt;2&gt;_OBUF' is missing an input and   will be deleted.</warning><warning>Cpld:936 - The output buffer 'LAN_CFG&lt;1&gt;_OBUF' is missing an input and   will be deleted.</warning><warning>Cpld:936 - The output buffer 'INT_OUT_OBUF' is missing an input and will   be deleted.</warning><warning>Cpld:936 - The output buffer 'CP_WE_OBUF' is missing an input and will   be deleted.</warning><warning>Cpld:936 - The output buffer 'CP_RD_OBUF' is missing an input and will   be deleted.</warning><warning>Cpld:936 - The output buffer 'CP_CS_OBUF' is missing an input and will   be deleted.</warning><warning>Cpld:936 - The output buffer 'CFOUT_OBUF' is missing an input and will   be deleted.</warning><warning>Cpld:936 - The output buffer 'A_LAN&lt;9&gt;_OBUF' is missing an input and   will be deleted.</warning><warning>Cpld:936 - The output buffer 'A_LAN&lt;8&gt;_OBUF' is missing an input and   will be deleted.</warning><warning>Cpld:936 - The output buffer 'A_LAN&lt;7&gt;_OBUF' is missing an input and   will be deleted.</warning><warning>Cpld:936 - The output buffer 'A_LAN&lt;6&gt;_OBUF' is missing an input and   will be deleted.</warning><warning>Cpld:936 - The output buffer 'A_LAN&lt;5&gt;_OBUF' is missing an input and   will be deleted.</warning><warning>Cpld:936 - The output buffer 'A_LAN&lt;4&gt;_OBUF' is missing an input and   will be deleted.</warning><warning>Cpld:936 - The output buffer 'A_LAN&lt;3&gt;_OBUF' is missing an input and   will be deleted.</warning><warning>Cpld:936 - The output buffer 'A_LAN&lt;2&gt;_OBUF' is missing an input and   will be deleted.</warning><warning>Cpld:936 - The output buffer 'A_LAN&lt;1&gt;_OBUF' is missing an input and   will be deleted.</warning><warning>Cpld:936 - The output buffer 'A_LAN&lt;13&gt;_OBUF' is missing an input and   will be deleted.</warning><warning>Cpld:936 - The output buffer 'A_LAN&lt;12&gt;_OBUF' is missing an input and   will be deleted.</warning><warning>Cpld:936 - The output buffer 'A_LAN&lt;11&gt;_OBUF' is missing an input and   will be deleted.</warning><warning>Cpld:936 - The output buffer 'A_LAN&lt;10&gt;_OBUF' is missing an input and   will be deleted.</warning><warning>Cpld:936 - The output buffer 'A_LAN&lt;0&gt;_OBUF' is missing an input and   will be deleted.</warning><warning>Cpld:1007 - Removing unused input(s) 'A&lt;14&gt;'.  The input(s) are unused   after optimization. Please verify functionality via simulation.</warning><warning>Cpld:1007 - Removing unused input(s) 'A&lt;15&gt;'.  The input(s) are unused   after optimization. Please verify functionality via simulation.</warning><warning>Cpld:1007 - Removing unused input(s) 'A&lt;7&gt;'.  The input(s) are unused   after optimization. Please verify functionality via simulation.</warning><warning>Cpld:1007 - Removing unused input(s) 'A&lt;8&gt;'.  The input(s) are unused   after optimization. Please verify functionality via simulation.</warning><warning>Cpld:1007 - Removing unused input(s) 'CFIN'.  The input(s) are unused   after optimization. Please verify functionality via simulation.</warning><warning>Cpld:1007 - Removing unused input(s) 'CLK_EXT'.  The input(s) are unused   after optimization. Please verify functionality via simulation.</warning><warning>Cpld:1007 - Removing unused input(s) 'CP_IRQ'.  The input(s) are unused   after optimization. Please verify functionality via simulation.</warning><warning>Cpld:1007 - Removing unused input(s) 'DQ&lt;0&gt;'.  The input(s) are unused   after optimization. Please verify functionality via simulation.</warning><warning>Cpld:1007 - Removing unused input(s) 'DQ&lt;10&gt;'.  The input(s) are unused   after optimization. Please verify functionality via simulation.</warning><warning>Cpld:1007 - Removing unused input(s) 'DQ&lt;11&gt;'.  The input(s) are unused   after optimization. Please verify functionality via simulation.</warning><warning>Cpld:1007 - Removing unused input(s) 'DQ&lt;12&gt;'.  The input(s) are unused   after optimization. Please verify functionality via simulation.</warning><warning>Cpld:1007 - Removing unused input(s) 'DQ&lt;13&gt;'.  The input(s) are unused   after optimization. Please verify functionality via simulation.</warning><warning>Cpld:1007 - Removing unused input(s) 'DQ&lt;14&gt;'.  The input(s) are unused   after optimization. Please verify functionality via simulation.</warning><warning>Cpld:1007 - Removing unused input(s) 'DQ&lt;15&gt;'.  The input(s) are unused   after optimization. Please verify functionality via simulation.</warning><warning>Cpld:1007 - Removing unused input(s) 'DQ&lt;1&gt;'.  The input(s) are unused   after optimization. Please verify functionality via simulation.</warning><warning>Cpld:1007 - Removing unused input(s) 'DQ&lt;2&gt;'.  The input(s) are unused   after optimization. Please verify functionality via simulation.</warning><warning>Cpld:1007 - Removing unused input(s) 'DQ&lt;3&gt;'.  The input(s) are unused   after optimization. Please verify functionality via simulation.</warning><warning>Cpld:1007 - Removing unused input(s) 'DQ&lt;4&gt;'.  The input(s) are unused   after optimization. Please verify functionality via simulation.</warning><warning>Cpld:1007 - Removing unused input(s) 'DQ&lt;5&gt;'.  The input(s) are unused   after optimization. Please verify functionality via simulation.</warning><warning>Cpld:1007 - Removing unused input(s) 'DQ&lt;6&gt;'.  The input(s) are unused   after optimization. Please verify functionality via simulation.</warning><warning>Cpld:1007 - Removing unused input(s) 'DQ&lt;7&gt;'.  The input(s) are unused   after optimization. Please verify functionality via simulation.</warning><warning>Cpld:1007 - Removing unused input(s) 'DQ&lt;8&gt;'.  The input(s) are unused   after optimization. Please verify functionality via simulation.</warning><warning>Cpld:1007 - Removing unused input(s) 'DQ&lt;9&gt;'.  The input(s) are unused   after optimization. Please verify functionality via simulation.</warning><warning>Cpld:1007 - Removing unused input(s) 'DS0'.  The input(s) are unused   after optimization. Please verify functionality via simulation.</warning><warning>Cpld:1007 - Removing unused input(s) 'DS1'.  The input(s) are unused   after optimization. Please verify functionality via simulation.</warning><warning>Cpld:1007 - Removing unused input(s) 'FCS'.  The input(s) are unused   after optimization. Please verify functionality via simulation.</warning><warning>Cpld:1007 - Removing unused input(s) 'IDE_WAIT'.  The input(s) are   unused after optimization. Please verify functionality via simulation.</warning><warning>Cpld:1007 - Removing unused input(s) 'LAN_INT'.  The input(s) are unused   after optimization. Please verify functionality via simulation.</warning><warning>Cpld:1007 - Removing unused input(s) 'LDS'.  The input(s) are unused   after optimization. Please verify functionality via simulation.</warning><warning>Cpld:1007 - Removing unused input(s) 'MTCR'.  The input(s) are unused   after optimization. Please verify functionality via simulation.</warning><warning>Cpld:1007 - Removing unused input(s) 'Z3'.  The input(s) are unused   after optimization. Please verify functionality via simulation.</warning><warning>Cpld:896 - Unable to map all desired signals into function block, FB3,   because too many function block product terms are required. Buffering output   signal D&lt;12&gt; to allow all signals assigned to this function block to be   placed.</warning><warning>Cpld:896 - Unable to map all desired signals into function block, FB3,   because too many function block product terms are required. Buffering output   signal D&lt;14&gt; to allow all signals assigned to this function block to be   placed.</warning><warning>Cpld:896 - Unable to map all desired signals into function block, FB3,   because too many function block product terms are required. Buffering output   signal D&lt;13&gt; to allow all signals assigned to this function block to be   placed.</warning><warning>Cpld:896 - Unable to map all desired signals into function block, FB3,   because too many function block product terms are required. Buffering output   signal D&lt;15&gt; to allow all signals assigned to this function block to be   placed.</warning></messages><compOpts exhaust="OFF" gclkopt="ON" gsropt="ON" gtsopt="ON" ignorets="OFF" inputs="54" keepio="OFF" loc="ON" mlopt="ON" optimize="SPEED" part="xc95144xl-10-TQ144" power="STD" prld="LOW" pterms="25" slew="FAST" terminate="KEEPER" unused="OFF" wysiwyg="OFF"/><specSig signal="A1_SPECSIG" value="A&lt;1&gt;"/><specSig signal="A2_SPECSIG" value="A&lt;2&gt;"/><specSig signal="A5_SPECSIG" value="A&lt;5&gt;"/><specSig signal="A6_SPECSIG" value="A&lt;6&gt;"/><specSig signal="A3_SPECSIG" value="A&lt;3&gt;"/><specSig signal="A4_SPECSIG" value="A&lt;4&gt;"/><specSig signal="A23_SPECSIG" value="A&lt;23&gt;"/><specSig signal="A22_SPECSIG" value="A&lt;22&gt;"/><specSig signal="A21_SPECSIG" value="A&lt;21&gt;"/><specSig signal="A19_SPECSIG" value="A&lt;19&gt;"/><specSig signal="D8PIN_SPECSIG" value="D&lt;8&gt;.PIN"/><specSig signal="D12PIN_SPECSIG" value="D&lt;12&gt;.PIN"/><specSig signal="D13PIN_SPECSIG" value="D&lt;13&gt;.PIN"/><specSig signal="D9PIN_SPECSIG" value="D&lt;9&gt;.PIN"/><specSig signal="D10PIN_SPECSIG" value="D&lt;10&gt;.PIN"/><specSig signal="D11PIN_SPECSIG" value="D&lt;11&gt;.PIN"/><specSig signal="D14PIN_SPECSIG" value="D&lt;14&gt;.PIN"/><specSig signal="D15PIN_SPECSIG" value="D&lt;15&gt;.PIN"/><specSig signal="A16_SPECSIG" value="A&lt;16&gt;"/><specSig signal="A20_SPECSIG" value="A&lt;20&gt;"/><specSig signal="A17_SPECSIG" value="A&lt;17&gt;"/><specSig signal="A18_SPECSIG" value="A&lt;18&gt;"/><specSig signal="A9_SPECSIG" value="A&lt;9&gt;"/><specSig signal="A10_SPECSIG" value="A&lt;10&gt;"/><specSig signal="A11_SPECSIG" value="A&lt;11&gt;"/><specSig signal="A12_SPECSIG" value="A&lt;12&gt;"/><specSig signal="A13_SPECSIG" value="A&lt;13&gt;"/><specSig signal="IDE_CS1_SPECSIG" value="IDE_CS&lt;1&gt;"/><specSig signal="D7_SPECSIG" value="D&lt;7&gt;"/><specSig signal="D1_SPECSIG" value="D&lt;1&gt;"/><specSig signal="IDE_A2_SPECSIG" value="IDE_A&lt;2&gt;"/><specSig signal="IO_SPECSIG" value="I/O"/><specSig signal="D8_SPECSIG" value="D&lt;8&gt;"/><specSig signal="D5_SPECSIG" value="D&lt;5&gt;"/><specSig signal="D4_SPECSIG" value="D&lt;4&gt;"/><specSig signal="IDE_CS0_SPECSIG" value="IDE_CS&lt;0&gt;"/><specSig signal="b_SPECSIG" value="(b)"/><specSig signal="IDE_A0_SPECSIG" value="IDE_A&lt;0&gt;"/><specSig signal="IDE_A1_SPECSIG" value="IDE_A&lt;1&gt;"/><specSig signal="D14_BUFR_SPECSIG" value="D&lt;14&gt;_BUFR"/><specSig signal="GSRI_SPECSIG" value="GSR/I"/><specSig signal="D0_SPECSIG" value="D&lt;0&gt;"/><specSig signal="AUTO_CONFIG_DONE2_SPECSIG" value="AUTO_CONFIG_DONE&lt;2&gt;"/><specSig signal="AUTO_CONFIG_DONE0_SPECSIG" value="AUTO_CONFIG_DONE&lt;0&gt;"/><specSig signal="AUTO_CONFIG_DONE_CYCLE2_SPECSIG" value="AUTO_CONFIG_DONE_CYCLE&lt;2&gt;"/><specSig signal="AUTO_CONFIG_DONE_CYCLE0_SPECSIG" value="AUTO_CONFIG_DONE_CYCLE&lt;0&gt;"/><specSig signal="IDE_BASEADR7_SPECSIG" value="IDE_BASEADR&lt;7&gt;"/><specSig signal="IDE_BASEADR6_SPECSIG" value="IDE_BASEADR&lt;6&gt;"/><specSig signal="D13_BUFR_SPECSIG" value="D&lt;13&gt;_BUFR"/><specSig signal="D6_SPECSIG" value="D&lt;6&gt;"/><specSig signal="D3_SPECSIG" value="D&lt;3&gt;"/><specSig signal="D2_SPECSIG" value="D&lt;2&gt;"/><specSig signal="D10_SPECSIG" value="D&lt;10&gt;"/><specSig signal="D12_SPECSIG" value="D&lt;12&gt;"/><specSig signal="D14_SPECSIG" value="D&lt;14&gt;"/><specSig signal="D9_SPECSIG" value="D&lt;9&gt;"/><specSig signal="D15_SPECSIG" value="D&lt;15&gt;"/><specSig signal="D11_SPECSIG" value="D&lt;11&gt;"/><specSig signal="D13_SPECSIG" value="D&lt;13&gt;"/><specSig signal="ideide_CLKF_SPECSIG" value="ide/ide_CLKF"/><specSig signal="ROM_B0_SPECSIG" value="ROM_B&lt;0&gt;"/><specSig signal="SHUT_UP1_SPECSIG" value="SHUT_UP&lt;1&gt;"/><specSig signal="ROM_B1_SPECSIG" value="ROM_B&lt;1&gt;"/><specSig signal="D15_BUFR_SPECSIG" value="D&lt;15&gt;_BUFR"/><specSig signal="D12_BUFR_SPECSIG" value="D&lt;12&gt;_BUFR"/><specSig signal="AUTO_CONFIG_DONE1_SPECSIG" value="AUTO_CONFIG_DONE&lt;1&gt;"/><specSig signal="AUTO_CONFIG_DONE_CYCLE1_SPECSIG" value="AUTO_CONFIG_DONE_CYCLE&lt;1&gt;"/><specSig signal="IDE_BASEADR3_SPECSIG" value="IDE_BASEADR&lt;3&gt;"/><specSig signal="IDE_BASEADR2_SPECSIG" value="IDE_BASEADR&lt;2&gt;"/><specSig signal="IDE_BASEADR0_SPECSIG" value="IDE_BASEADR&lt;0&gt;"/><specSig signal="IDE_BASEADR1_SPECSIG" value="IDE_BASEADR&lt;1&gt;"/><specSig signal="IDE_BASEADR4_SPECSIG" value="IDE_BASEADR&lt;4&gt;"/><specSig signal="IDE_BASEADR5_SPECSIG" value="IDE_BASEADR&lt;5&gt;"/></document>
diff --git a/Logic/LAN_IDE/LAN_IDE_CP.xst b/Logic/LAN_IDE/LAN_IDE_CP.xst
new file mode 100644
index 0000000..20c79ef
--- /dev/null
+++ b/Logic/LAN_IDE/LAN_IDE_CP.xst
@@ -0,0 +1,29 @@
+set -tmpdir "xst/projnav.tmp"
+set -xsthdpdir "xst"
+run
+-ifn LAN_IDE_CP.prj
+-ifmt mixed
+-ofn LAN_IDE_CP
+-ofmt NGC
+-p xc9500xl
+-top LAN_IDE_CP
+-opt_mode Speed
+-opt_level 1
+-iuc NO
+-keep_hierarchy Yes
+-netlist_hierarchy As_Optimized
+-rtlview Yes
+-hierarchy_separator /
+-bus_delimiter <>
+-case Maintain
+-verilog2001 YES
+-fsm_extract YES -fsm_encoding Auto
+-safe_implementation No
+-mux_extract Yes
+-resource_sharing YES
+-iobuf YES
+-pld_mp YES
+-pld_xp YES
+-pld_ce YES
+-wysiwyg NO
+-equivalent_register_removal YES
diff --git a/Logic/LAN_IDE/LAN_IDE_CP_build.xml b/Logic/LAN_IDE/LAN_IDE_CP_build.xml
new file mode 100644
index 0000000..8123f19
--- /dev/null
+++ b/Logic/LAN_IDE/LAN_IDE_CP_build.xml
@@ -0,0 +1,249 @@
+<?xml version='1.0' encoding='utf-8' ?>
+<!DOCTYPE document SYSTEM 'file:///C:/Xilinx/14.6/ISE_DS/ISE/chipviewer/data/xsl/buildXML.dtd'>
+
+<document>
+<design name='LAN_IDE_CP'/>
+<rptdir name='LAN_IDE_CP'/>
+<xilinx path='C:/Xilinx/14.6/ISE_DS/ISE;'/>
+<projDir path='C:\Users\Matze\Amiga\Hardwarehacks\Zorro-LAN-IDE\Logic\LAN_IDE'/>
+<xslDir path='chipviewer/data/xsl'/>
+<fileDir path='/chipviewer/data/html'/>
+<dataFile file='index.htm'/>
+<dataFile file='report.htm'/>
+<dataFile file='genmsg.htm'/>
+<dataFile file='eqns.js'/>
+<dataFile file='maplogic.js'/>
+<dataFile file='fbs.js'/>
+<dataFile file='pins.js'/>
+<dataFile file='tooltips.js'/>
+<dataFile file='errors.js'/>
+<dataFile file='leftnav.js'/>
+<dataFile file='paths.js'/>
+<dataFile file='summary.js'/>
+<dataFile file='topnav.js'/>
+<dataFile file='applet.js'/>
+<dataFile file='plugin.js'/>
+<dataFile file='ns4plugin.js'/>
+<dataFile file='equations.htm'/>
+<dataFile file='result.htm'/>
+<dataFile file='style.css'/>
+<dataFile file='blank.gif'/>
+<dataFile file='fbview.jpg'/>
+<dataFile file='pinview.jpg'/>
+<dataFile file='xc9500xl_logo.jpg'/>
+<dataFile file='asciidoc.htm'/>
+<dataFile file='equationsdoc.htm'/>
+<dataFile file='errorsdoc.htm'/>
+<dataFile file='failtabledoc.htm'/>
+<dataFile file='fbs_FBdoc.htm'/>
+<dataFile file='fbsdoc.htm'/>
+<dataFile file='inputleftdoc.htm'/>
+<dataFile file='logicleftdoc.htm'/>
+<dataFile file='mapinputdoc.htm'/>
+<dataFile file='maplogicdoc.htm'/>
+<dataFile file='optionsdoc.htm'/>
+<dataFile file='pinsdoc.htm'/>
+<dataFile file='summarydoc.htm'/>
+<dataFile file='check.htm'/>
+<dataFile file='checkNS4.htm'/>
+<dataFile file='appletref.htm'/>
+<dataFile file='newappletref.htm'/>
+<dataFile file='errors1.gif'/>
+<dataFile file='errors2.gif'/>
+<dataFile file='equations.gif'/>
+<dataFile file='functionblock.gif'/>
+<dataFile file='fb1.gif'/>
+<dataFile file='legend.gif'/>
+<dataFile file='macrocell.gif'/>
+<dataFile file='fb.gif'/>
+<dataFile file='pin.gif'/>
+<dataFile file='pindiagram.gif'/>
+<dataFile file='view.gif'/>
+<dataFile file='xml8.jpg'/>
+<dataFile file='xml7.jpg'/>
+<dataFile file='xml6.jpg'/>
+<dataFile file='xml5.jpg'/>
+<xmlFileGroup id='1'>
+<xmlFile file='LAN_IDE_CP.xml'>
+  <xslFile file='topnav.xsl'>
+    <output file='topnav.htm'/>
+  </xslFile>
+  <xslFile file='leftnav.xsl'>
+    <param name='result' value='1'/>
+    <output file='leftnav.htm'/>
+  </xslFile>
+  <xslFile file='print.xsl'>
+    <output file='ascii.tmp'/>
+  </xslFile>
+  <xslFile file='eqns.xsl'>
+    <output file='eqns.htm'/>
+  </xslFile>
+  <xslFile file='summary.xsl'>
+    <param name='sumOn' value='1'/>
+    <param name='optOn' value='0'/>
+    <param name='legendOn' value='0'/>
+    <output file='summary.htm'/>
+  </xslFile>
+</xmlFile>
+</xmlFileGroup>
+<xmlFileGroup id='2'>
+<xmlFile file='LAN_IDE_CP.xml'>
+  <xslFile file='summary.xsl'>
+    <param name='sumOn' value='0'/>
+    <param name='optOn' value='1'/>
+    <param name='legendOn' value='0'/>
+    <output file='options.htm'/>
+  </xslFile>
+  <xslFile file='printErrors.xsl'>
+    <output file='errs.htm'/>
+  </xslFile>
+  <xslFile file='failtable.xsl'>
+    <output file='failtable.htm'/>
+  </xslFile>
+  <xslFile file='logicleft.xsl'>
+    <output file='logicleft.htm'/>
+  </xslFile>
+  <xslFile file='inputleft.xsl'>
+    <output file='inputleft.htm'/>
+  </xslFile>
+  <xslFile file='printPins.xsl'>
+    <param name='appletOn' value='0'/>
+    <output file='pins.htm'/>
+  </xslFile>
+  <xslFile file='wait.xsl'>
+    <output file='wait.htm'/>
+  </xslFile>
+  <xslDebug file='printErrors.xsl'>
+    <output file='errors.htm'/>
+  </xslDebug>
+  <xslDebug file='printPins.xsl'>
+    <output file='pinout.htm'/>
+  </xslDebug>
+  <xslDebug file='printEqns.xsl'>
+    <output file='eqnout.htm'/>
+  </xslDebug>
+  <xslFile file='maplogic.xsl'>
+    <param name='sortType' value='0'/>
+    <param name='mapLog' value='1'/>
+    <param name='mapIn' value='0'/>
+    <param name='unmapLog' value='0'/>
+    <param name='unmapIn' value='0'/>
+    <param name='legendOn' value='1'/>
+    <param name='appletOn' value='0'/>
+    <output file='maplogic_00.htm'/>
+    <param name='sortType' value='1'/>
+    <param name='mapLog' value='1'/>
+    <param name='mapIn' value='0'/>
+    <param name='unmapLog' value='0'/>
+    <param name='unmapIn' value='0'/>
+    <param name='legendOn' value='1'/>
+    <param name='appletOn' value='0'/>
+    <output file='maplogic_01.htm'/>
+    <param name='sortType' value='2'/>
+    <param name='mapLog' value='1'/>
+    <param name='mapIn' value='0'/>
+    <param name='unmapLog' value='0'/>
+    <param name='unmapIn' value='0'/>
+    <param name='legendOn' value='1'/>
+    <param name='appletOn' value='0'/>
+    <output file='maplogic_02.htm'/>
+    <param name='sortType' value='0'/>
+    <param name='mapLog' value='0'/>
+    <param name='mapIn' value='1'/>
+    <param name='unmapLog' value='0'/>
+    <param name='unmapIn' value='0'/>
+    <param name='legendOn' value='1'/>
+    <param name='appletOn' value='0'/>
+    <output file='mapinput_00.htm'/>
+    <param name='sortType' value='1'/>
+    <param name='mapLog' value='0'/>
+    <param name='mapIn' value='1'/>
+    <param name='unmapLog' value='0'/>
+    <param name='unmapIn' value='0'/>
+    <param name='legendOn' value='1'/>
+    <param name='appletOn' value='0'/>
+    <output file='mapinput_01.htm'/>
+    <param name='sortType' value='2'/>
+    <param name='mapLog' value='0'/>
+    <param name='mapIn' value='1'/>
+    <param name='unmapLog' value='0'/>
+    <param name='unmapIn' value='0'/>
+    <param name='legendOn' value='1'/>
+    <param name='appletOn' value='0'/>
+    <output file='mapinput_02.htm'/>
+  </xslFile>
+  <xslFile file='fbsum.xsl'>
+    <param name='legendOn' value='0'/>
+    <output file='fbs.htm'/>
+  </xslFile>
+  <xslFile file='fbs.xsl'>
+    <param name='fb' value='FB1'/>
+    <param name='type' value='1'/>
+    <param name='legendOn' value='1'/>
+    <param name='appletOn' value='0'/>
+    <output file='fbs_FB1.htm'/>
+    <param name='fb' value='FB2'/>
+    <param name='type' value='3'/>
+    <param name='legendOn' value='1'/>
+    <param name='appletOn' value='0'/>
+    <output file='fbs_FB2.htm'/>
+    <param name='fb' value='FB3'/>
+    <param name='type' value='3'/>
+    <param name='legendOn' value='1'/>
+    <param name='appletOn' value='0'/>
+    <output file='fbs_FB3.htm'/>
+    <param name='fb' value='FB4'/>
+    <param name='type' value='3'/>
+    <param name='legendOn' value='1'/>
+    <param name='appletOn' value='0'/>
+    <output file='fbs_FB4.htm'/>
+    <param name='fb' value='FB5'/>
+    <param name='type' value='3'/>
+    <param name='legendOn' value='1'/>
+    <param name='appletOn' value='0'/>
+    <output file='fbs_FB5.htm'/>
+    <param name='fb' value='FB6'/>
+    <param name='type' value='3'/>
+    <param name='legendOn' value='1'/>
+    <param name='appletOn' value='0'/>
+    <output file='fbs_FB6.htm'/>
+    <param name='fb' value='FB7'/>
+    <param name='type' value='3'/>
+    <param name='legendOn' value='1'/>
+    <param name='appletOn' value='0'/>
+    <output file='fbs_FB7.htm'/>
+    <param name='fb' value='FB8'/>
+    <param name='type' value='2'/>
+    <param name='legendOn' value='1'/>
+    <param name='appletOn' value='0'/>
+    <output file='fbs_FB8.htm'/>
+  </xslFile>
+</xmlFile>
+<xmlFile file='C:/Xilinx/14.6/ISE_DS/ISE/chipviewer/data/xsl/pinlegend.xml'>
+  <xslFile file='legend.xsl'>
+    <param name='device' value='XC95144XL-10-TQ144'/>
+    <param name='verOn' value='0'/>
+    <param name='linkName' value='pinlegendV.htm'/>
+    <output file='pinlegend.htm'/>
+    <param name='device' value='XC95144XL-10-TQ144'/>
+    <param name='verOn' value='1'/>
+    <param name='linkName' value='pinlegend.htm'/>
+    <output file='pinlegendV.htm'/>
+  </xslFile>
+</xmlFile>
+<xmlFile file='C:/Xilinx/14.6/ISE_DS/ISE/chipviewer/data/xsl/logiclegend.xml'>
+  <xslFile file='legend.xsl'>
+    <param name='device' value='XC95144XL-10-TQ144'/>
+    <param name='verOn' value='0'/>
+    <param name='linkName' value='logiclegendV.htm'/>
+    <output file='logiclegend.htm'/>
+    <param name='device' value='XC95144XL-10-TQ144'/>
+    <param name='verOn' value='1'/>
+    <param name='linkName' value='logiclegend.htm'/>
+    <output file='logiclegendV.htm'/>
+  </xslFile>
+</xmlFile>
+</xmlFileGroup>
+<rptFile file='LAN_IDE_CP.rpt'/>
+<timFile file='LAN_IDE_CP.tim'/>
+</document>
diff --git a/Logic/LAN_IDE/LAN_IDE_CP_envsettings.html b/Logic/LAN_IDE/LAN_IDE_CP_envsettings.html
new file mode 100644
index 0000000..5c8516f
--- /dev/null
+++ b/Logic/LAN_IDE/LAN_IDE_CP_envsettings.html
@@ -0,0 +1,244 @@
+<HTML><HEAD><TITLE>Xilinx System Settings Report</TITLE></HEAD>
+<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
+<center><big><big><b>System Settings</b></big></big></center><br>
+<A NAME="Environment Settings"></A>
+&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
+<TD ALIGN=CENTER COLSPAN='3'><B> Environment Settings </B></TD>
+</tr>
+<tr bgcolor='#ffff99'>
+<td><b>Environment Variable</b></td>
+<td><b>xst</b></td>
+<td><b>ngdbuild</b></td>
+</tr>
+<tr>
+<td>PATHEXT</td>
+<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC;<br>.PY</td>
+<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC;<br>.PY</td>
+</tr>
+<tr>
+<td>Path</td>
+<td>C:\Xilinx\14.6\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\14.6\ISE_DS\ISE\\bin\nt64;<br>C:\Xilinx\14.6\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\14.6\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\14.6\ISE_DS\ISE\..\..\..\DocNav;<br>C:\Xilinx\14.6\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\14.6\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\14.6\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\14.6\ISE_DS\EDK\gnu\microblaze\nt\bin;<br>C:\Xilinx\14.6\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;<br>C:\Xilinx\14.6\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\14.6\ISE_DS\EDK\gnu\arm\nt\bin;<br>C:\Xilinx\14.6\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;<br>C:\Xilinx\14.6\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;<br>C:\Xilinx\14.6\ISE_DS\common\bin\nt64;<br>C:\Xilinx\14.6\ISE_DS\common\lib\nt64;<br>E:\ispLEVER_Classic2_0\ispcpld\bin;<br>E:\ispLEVER_Classic2_0\ispFPGA\bin\nt;<br>E:\ispLEVER_Classic2_0\active-hdl\BIN;<br>C:\ProgramData\Oracle\Java\javapath;<br>C:\SynaptiCAD\bin\win32;<br>C:\Program Files\Java\jre7\bin;<br>C\Windows\System32;<br>C:\Program Files (x86)\WinAVR\bin;<br>C:\Program Files (x86)\WinAVR\utils\bin;<br>C:\Program Files\Common Files\Microsoft Shared\Windows Live;<br>C:\Program Files (x86)\SSH Communications Security\SSH Secure Shell;<br>C:\Program Files (x86)\UltraEdit;<br>c:\Xilinx\14.6\ISE_DS\ISE\bin\nt64C:\ispLever\ispcpld\bin;<br>C:\ispLever\ispFPGA\bin\nt;<br>C:\ispLever\active-hdl\BIN;<br>C:\Program Files\WinRAR;<br>C:\SynaptiCAD\bin;<br>C:\Program Files (x86)\Windows Kits\8.1\Windows Performance Toolkit\;<br>C:\Program Files\Microsoft SQL Server\110\Tools\Binn\;<br>C:\Program Files (x86)\Microsoft SDKs\TypeScript\1.0\;<br>C:\Program Files\Microsoft SQL Server\120\Tools\Binn\;<br>C:\WINDOWS\system32;<br>C:\WINDOWS;<br>C:\WINDOWS\System32\Wbem;<br>C:\WINDOWS\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files (x86)\ATI Technologies\ATI.ACE\Core-Static;<br>%PATH;<br>C:\Program Files (x86)\IDM Computer Solutions\UltraEdit\;<br>C:\Program Files (x86)\UltraEdit\;<br>C:\Program Files\Java\jdk1.7.0_02\bin;<br>C:\Users\Matze\AppData\Local\Microsoft\WindowsApps</td>
+<td>C:\Xilinx\14.6\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\14.6\ISE_DS\ISE\\bin\nt64;<br>C:\Xilinx\14.6\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\14.6\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\14.6\ISE_DS\ISE\..\..\..\DocNav;<br>C:\Xilinx\14.6\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\14.6\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\14.6\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\14.6\ISE_DS\EDK\gnu\microblaze\nt\bin;<br>C:\Xilinx\14.6\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;<br>C:\Xilinx\14.6\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\14.6\ISE_DS\EDK\gnu\arm\nt\bin;<br>C:\Xilinx\14.6\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;<br>C:\Xilinx\14.6\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;<br>C:\Xilinx\14.6\ISE_DS\common\bin\nt64;<br>C:\Xilinx\14.6\ISE_DS\common\lib\nt64;<br>E:\ispLEVER_Classic2_0\ispcpld\bin;<br>E:\ispLEVER_Classic2_0\ispFPGA\bin\nt;<br>E:\ispLEVER_Classic2_0\active-hdl\BIN;<br>C:\ProgramData\Oracle\Java\javapath;<br>C:\SynaptiCAD\bin\win32;<br>C:\Program Files\Java\jre7\bin;<br>C\Windows\System32;<br>C:\Program Files (x86)\WinAVR\bin;<br>C:\Program Files (x86)\WinAVR\utils\bin;<br>C:\Program Files\Common Files\Microsoft Shared\Windows Live;<br>C:\Program Files (x86)\SSH Communications Security\SSH Secure Shell;<br>C:\Program Files (x86)\UltraEdit;<br>c:\Xilinx\14.6\ISE_DS\ISE\bin\nt64C:\ispLever\ispcpld\bin;<br>C:\ispLever\ispFPGA\bin\nt;<br>C:\ispLever\active-hdl\BIN;<br>C:\Program Files\WinRAR;<br>C:\SynaptiCAD\bin;<br>C:\Program Files (x86)\Windows Kits\8.1\Windows Performance Toolkit\;<br>C:\Program Files\Microsoft SQL Server\110\Tools\Binn\;<br>C:\Program Files (x86)\Microsoft SDKs\TypeScript\1.0\;<br>C:\Program Files\Microsoft SQL Server\120\Tools\Binn\;<br>C:\WINDOWS\system32;<br>C:\WINDOWS;<br>C:\WINDOWS\System32\Wbem;<br>C:\WINDOWS\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files (x86)\ATI Technologies\ATI.ACE\Core-Static;<br>%PATH;<br>C:\Program Files (x86)\IDM Computer Solutions\UltraEdit\;<br>C:\Program Files (x86)\UltraEdit\;<br>C:\Program Files\Java\jdk1.7.0_02\bin;<br>C:\Users\Matze\AppData\Local\Microsoft\WindowsApps</td>
+</tr>
+<tr>
+<td>XILINX</td>
+<td>C:\Xilinx\14.6\ISE_DS\ISE\</td>
+<td>C:\Xilinx\14.6\ISE_DS\ISE\</td>
+</tr>
+<tr>
+<td>XILINX_DSP</td>
+<td>C:\Xilinx\14.6\ISE_DS\ISE</td>
+<td>C:\Xilinx\14.6\ISE_DS\ISE</td>
+</tr>
+<tr>
+<td>XILINX_EDK</td>
+<td>C:\Xilinx\14.6\ISE_DS\EDK</td>
+<td>C:\Xilinx\14.6\ISE_DS\EDK</td>
+</tr>
+<tr>
+<td>XILINX_PLANAHEAD</td>
+<td>C:\Xilinx\14.6\ISE_DS\PlanAhead</td>
+<td>C:\Xilinx\14.6\ISE_DS\PlanAhead</td>
+</tr>
+</TABLE>
+<A NAME="Synthesis Property Settings"></A>
+&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
+<TD ALIGN=CENTER COLSPAN='4'><B>Synthesis Property Settings </B></TD>
+</tr>
+<tr bgcolor='#ffff99'>
+<td><b>Switch Name</b></td>
+<td><b>Property Name</b></td>
+<td><b>Value</b></td>
+<td><b>Default Value</b></td>
+</tr>
+<tr>
+<td>-ifn</td>
+<td>&nbsp;</td>
+<td>LAN_IDE_CP.prj</td>
+<td>&nbsp;</td>
+</tr>
+<tr>
+<td>-ifmt</td>
+<td>&nbsp;</td>
+<td>mixed</td>
+<td>MIXED</td>
+</tr>
+<tr>
+<td>-ofn</td>
+<td>&nbsp;</td>
+<td>LAN_IDE_CP</td>
+<td>&nbsp;</td>
+</tr>
+<tr>
+<td>-ofmt</td>
+<td>&nbsp;</td>
+<td>NGC</td>
+<td>NGC</td>
+</tr>
+<tr>
+<td>-p</td>
+<td>&nbsp;</td>
+<td>xc9500xl</td>
+<td>&nbsp;</td>
+</tr>
+<tr>
+<td>-top</td>
+<td>&nbsp;</td>
+<td>LAN_IDE_CP</td>
+<td>&nbsp;</td>
+</tr>
+<tr>
+<td>-opt_mode</td>
+<td>Optimization Goal</td>
+<td>Speed</td>
+<td>SPEED</td>
+</tr>
+<tr>
+<td>-opt_level</td>
+<td>Optimization Effort</td>
+<td>1</td>
+<td>1</td>
+</tr>
+<tr>
+<td>-iuc</td>
+<td>Use synthesis Constraints File</td>
+<td>NO</td>
+<td>NO</td>
+</tr>
+<tr>
+<td>-keep_hierarchy</td>
+<td>Keep Hierarchy</td>
+<td>Yes</td>
+<td>YES</td>
+</tr>
+<tr>
+<td>-netlist_hierarchy</td>
+<td>Netlist Hierarchy</td>
+<td>As_Optimized</td>
+<td>as_optimized</td>
+</tr>
+<tr>
+<td>-rtlview</td>
+<td>Generate RTL Schematic</td>
+<td>Yes</td>
+<td>NO</td>
+</tr>
+<tr>
+<td>-bus_delimiter</td>
+<td>Bus Delimiter</td>
+<td>&lt;&gt;</td>
+<td>&lt;&gt;</td>
+</tr>
+<tr>
+<td>-verilog2001</td>
+<td>Verilog 2001</td>
+<td>YES</td>
+<td>YES</td>
+</tr>
+<tr>
+<td>-fsm_extract</td>
+<td>&nbsp;</td>
+<td>YES</td>
+<td>YES</td>
+</tr>
+<tr>
+<td>-fsm_encoding</td>
+<td>&nbsp;</td>
+<td>Auto</td>
+<td>AUTO</td>
+</tr>
+<tr>
+<td>-safe_implementation</td>
+<td>&nbsp;</td>
+<td>No</td>
+<td>NO</td>
+</tr>
+<tr>
+<td>-resource_sharing</td>
+<td>&nbsp;</td>
+<td>YES</td>
+<td>YES</td>
+</tr>
+<tr>
+<td>-iobuf</td>
+<td>&nbsp;</td>
+<td>YES</td>
+<td>YES</td>
+</tr>
+<tr>
+<td>-equivalent_register_removal</td>
+<td>&nbsp;</td>
+<td>YES</td>
+<td>YES</td>
+</tr>
+</TABLE>
+<A NAME="Translation Property Settings"></A>
+&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
+<TD ALIGN=CENTER COLSPAN='4'><B>Translation Property Settings </B></TD>
+</tr>
+<tr bgcolor='#ffff99'>
+<td><b>Switch Name</b></td>
+<td><b>Property Name</b></td>
+<td><b>Value</b></td>
+<td><b>Default Value</b></td>
+</tr>
+<tr>
+<td>-intstyle</td>
+<td>&nbsp;</td>
+<td>ise</td>
+<td>None</td>
+</tr>
+<tr>
+<td>-dd</td>
+<td>&nbsp;</td>
+<td>_ngo</td>
+<td>None</td>
+</tr>
+<tr>
+<td>-p</td>
+<td>&nbsp;</td>
+<td>xc95144xl-TQ144-10</td>
+<td>None</td>
+</tr>
+<tr>
+<td>-uc</td>
+<td>&nbsp;</td>
+<td>pinlist.ucf</td>
+<td>None</td>
+</tr>
+</TABLE>
+<A NAME="Operating System Information"></A>
+&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
+<TD ALIGN=CENTER COLSPAN='3'><B> Operating System Information </B></TD>
+</tr>
+<tr bgcolor='#ffff99'>
+<td><b>Operating System Information</b></td>
+<td><b>xst</b></td>
+<td><b>ngdbuild</b></td>
+</tr>
+<tr>
+<td>CPU Architecture/Speed</td>
+<td>AMD Phenom(tm) II X6 1090T Processor/3200 MHz</td>
+<td>AMD Phenom(tm) II X6 1090T Processor/3200 MHz</td>
+</tr>
+<tr>
+<td>Host</td>
+<td>DeepThought</td>
+<td>DeepThought</td>
+</tr>
+<tr>
+<td>OS Name</td>
+<td>Microsoft , 64-bit</td>
+<td>Microsoft , 64-bit</td>
+</tr>
+<tr>
+<td>OS Release</td>
+<td>major release  (build 9200)</td>
+<td>major release  (build 9200)</td>
+</tr>
+</TABLE>
+</BODY> </HTML>
\ No newline at end of file
diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/applet.js b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/applet.js
new file mode 100644
index 0000000..d255dd2
--- /dev/null
+++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/applet.js
@@ -0,0 +1,128 @@
+    var tmpStr = "";
+    var waitWin;
+
+    function openWait() {
+     waitWin = window.open("wait.htm", "wait",
+                          "toolbar=no,location=no,"+
+                             "directories=no,status=no,menubar=no,scrollbars=no,"+
+                             "resizable=no,width=300,height=50" );
+    }
+
+    function closeWait() { if (waitWin) waitWin.close(); }
+
+    function setMsg(msg){
+
+       parent.leftnav.setAppletMsg( msg );
+       // now send it reload forces
+       // call to applet paint
+        location.reload();
+    }
+
+    function getMsg(){
+
+        return( parent.leftnav.getAppletMsg() );
+    }
+
+    function resetMsg(){ parent.leftnav.setAppletMsg(""); }
+
+    function printAppletPkg() {
+        if( isNS() ){
+             setMsg("cmd printPkg ");
+         }
+         else{
+             document.ChipViewerApplet.PrintPkg();
+         }
+    }
+
+    function showAppletGraphicMC(mc) {
+        if( isNS() ){
+             setMsg("cmd showMac " + mc);
+         }
+         else{
+             document.ChipViewerApplet.ShowMac(mc);
+         }
+    }
+
+    function ShowMC() { showAppletGraphicMC(tmpStr); }
+
+    function showAppletGraphicFB(fb) {
+         if( isNS() ){
+            setMsg("cmd showFB " + fb);
+         }
+         else{
+             document.ChipViewerApplet.ShowFB(fb);
+         }
+    }
+
+    function showAppletGraphicPin(pin) { 
+         if( isNS() ){ 
+            setMsg("cmd showPin " + pin); 
+         } 
+         else{ 
+             document.ChipViewerApplet.ShowPin(pin); 
+         } 
+    } 
+
+    function ShowFB() { showAppletGraphicFB(tmpStr); }
+
+    function isNS() {
+      return ((navigator.appName.indexOf("Netscape") >= 0) && (parseFloat(navigator.appVersion) < 5) ) ? true : false;
+    }
+
+    function isIE(){
+        var agt=navigator.userAgent.toLowerCase();
+        return( ( (agt.indexOf("msie") != -1) && (agt.indexOf("opera") == -1) ) ? true: false );
+    }
+
+    function waitUntilOK() {
+      if (!waitWin) openWait();
+      if (isNS()) {
+        if (document.ChipViewerApplet.isActive()) closeWait();
+        else  settimeout("waitUntilOK()",100);
+      }
+      else {
+        if (document.ChipViewerApplet.readyState == 4) closeWait();
+        else  settimeout("waitUntilOK()",100);
+      }
+    }
+
+
+    // check that the applet if file has been generated
+    // this can only be done if the applets been loaded.
+    function fileExists(fileName){
+
+        if( document.ChipViewerApplet.readyState != 4 ) {
+            window.alert("Navigation disabled until the applet is loaded." );
+        }
+        if( isIE() ){
+            if( parent.leftnav.getAppletPermission() == 1 ){
+                if( document.ChipViewerApplet.TestFileExists(fileName) == 1 ){
+                    window.alert("file exist tests true" );
+                    return( true );
+                }
+            }
+            else{
+                window.alert("file exist returns true no permission" );
+                return( true );
+            }
+        }
+        else{
+            return( true );
+        }
+        window.alert("file exist returns false" );
+        return( false );
+    }
+
+
+
+    function setPermission(){
+
+        if( isIE() ){
+            if( document.ChipViewerApplet.granted() ){
+                parent.leftnav.setAppletPermission();     
+            }
+        } 
+        else{ 
+            return( true );
+        }
+    }
diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/appletref.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/appletref.htm
new file mode 100644
index 0000000..2182301
--- /dev/null
+++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/appletref.htm
@@ -0,0 +1,14 @@
+<html>
+  <head>
+    <title></title>
+  </head>
+  <frameset frameborder="NO" framespacing="0" border="0" rows="94,*,0,0" col="*">
+    <frame name="topnav" src="../tim/topnav.htm" scrolling="no" noresize marginwidth="0" marginheight="0">
+    <frameset frameborder="NO" framespacing="0" border="0" cols="125,*">
+      <frame name="leftnav" src="leftnav.htm" noresize marginwidth="0" marginheight="0">
+      <frame name="content" src="summary.htm">
+    </frameset>
+    <frame name="eqns" src="eqns.htm" scrolling="no">
+  </frameset>
+</html>
+
diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/ascii.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/ascii.htm
new file mode 100644
index 0000000..811ab7e
--- /dev/null
+++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/ascii.htm
@@ -0,0 +1,1175 @@
+<html><body>
+<pre>
+ 
+cpldfit:  version P.68d                             Xilinx Inc.
+                                  Fitter Report
+Design Name: LAN_IDE_CP                          Date: 12-15-2016,  7:48PM
+Device Used: XC95144XL-10-TQ144
+Fitting Status: Successful
+
+*************************  Mapped Resource Summary  **************************
+
+Macrocells     Product Terms    Function Block   Registers      Pins           
+Used/Tot       Used/Tot         Inps Used/Tot    Used/Tot       Used/Tot       
+51 /144 ( 35%) 179 /720  ( 25%) 134/432 ( 31%)   26 /144 ( 18%) 54 /117 ( 46%)
+
+** Function Block Resources **
+
+Function    Mcells      FB Inps     Pterms      IO          
+Block       Used/Tot    Used/Tot    Used/Tot    Used/Tot    
+FB1          16/18       24/54       40/90      13/15
+FB2          11/18       24/54       56/90       4/15
+FB3          12/18       24/54       25/90      11/15
+FB4           3/18       24/54       25/90       0/15
+FB5           7/18       23/54       19/90      10/14
+FB6           1/18       15/54       14/90       0/13
+FB7           1/18        0/54        0/90       8/15
+FB8           0/18        0/54        0/90       8/15
+             -----       -----       -----      -----    
+             51/144     134/432     179/720     54/117
+
+* - Resource is exhausted
+
+** Global Control Resources **
+
+Global clock net(s) unused.
+Global output enable net(s) unused.
+Signal 'RESET' mapped onto global set/reset net GSR.
+
+** Pin Resources **
+
+Signal Type    Required     Mapped  |  Pin Type            Used    Total 
+------------------------------------|------------------------------------
+Input         :   26          26    |  I/O              :    52     109
+Output        :   19          19    |  GCK/IO           :     0       3
+Bidirectional :    8           8    |  GTS/IO           :     1       4
+GCK           :    0           0    |  GSR/IO           :     1       1
+GTS           :    0           0    |
+GSR           :    1           1    |
+                 ----        ----
+        Total     54          54
+
+** Power Data **
+
+There are 51 macrocells in high performance mode (MCHP).
+There are 0 macrocells in low power mode (MCLP).
+End of Mapped Resource Summary
+**************************  Errors and Warnings  ***************************
+
+WARNING:Cpld - Unable to retrieve the path to the iSE Project Repository. Will
+   use the default filename of 'LAN_IDE_CP.ise'.
+INFO:Cpld - Inferring BUFG constraint for signal 'CLK_EXT' based upon the LOC
+   constraint 'P30'. It is recommended that you declare this BUFG explicitedly
+   in your design. Note that for certain device families the output of a BUFG
+   constraint can not drive a gated clock, and the BUFG constraint will be
+   ignored.
+WARNING:Cpld:936 - The output buffer 'SLAVE_OBUF' is missing an input and will
+   be deleted.
+WARNING:Cpld:936 - The output buffer 'OWN_OBUF' is missing an input and will be
+   deleted.
+WARNING:Cpld:936 - The output buffer 'OVR_OBUF' is missing an input and will be
+   deleted.
+WARNING:Cpld:936 - The output buffer 'MTACK_OBUF' is missing an input and will
+   be deleted.
+WARNING:Cpld:936 - The output buffer 'LAN_WRH_OBUF' is missing an input and will
+   be deleted.
+WARNING:Cpld:936 - The output buffer 'LAN_RD_OBUF' is missing an input and will
+   be deleted.
+WARNING:Cpld:936 - The output buffer 'LAN_EN_OBUF' is missing an input and will
+   be deleted.
+WARNING:Cpld:936 - The output buffer 'LAN_CS_OBUF' is missing an input and will
+   be deleted.
+WARNING:Cpld:936 - The output buffer 'LAN_CFG<4>_OBUF' is missing an input and
+   will be deleted.
+WARNING:Cpld:936 - The output buffer 'LAN_CFG<3>_OBUF' is missing an input and
+   will be deleted.
+WARNING:Cpld:936 - The output buffer 'LAN_CFG<2>_OBUF' is missing an input and
+   will be deleted.
+WARNING:Cpld:936 - The output buffer 'LAN_CFG<1>_OBUF' is missing an input and
+   will be deleted.
+WARNING:Cpld:936 - The output buffer 'INT_OUT_OBUF' is missing an input and will
+   be deleted.
+WARNING:Cpld:936 - The output buffer 'CP_WE_OBUF' is missing an input and will
+   be deleted.
+WARNING:Cpld:936 - The output buffer 'CP_RD_OBUF' is missing an input and will
+   be deleted.
+WARNING:Cpld:936 - The output buffer 'CP_CS_OBUF' is missing an input and will
+   be deleted.
+WARNING:Cpld:936 - The output buffer 'CFOUT_OBUF' is missing an input and will
+   be deleted.
+WARNING:Cpld:936 - The output buffer 'A_LAN<9>_OBUF' is missing an input and
+   will be deleted.
+WARNING:Cpld:936 - The output buffer 'A_LAN<8>_OBUF' is missing an input and
+   will be deleted.
+WARNING:Cpld:936 - The output buffer 'A_LAN<7>_OBUF' is missing an input and
+   will be deleted.
+WARNING:Cpld:936 - The output buffer 'A_LAN<6>_OBUF' is missing an input and
+   will be deleted.
+WARNING:Cpld:936 - The output buffer 'A_LAN<5>_OBUF' is missing an input and
+   will be deleted.
+WARNING:Cpld:936 - The output buffer 'A_LAN<4>_OBUF' is missing an input and
+   will be deleted.
+WARNING:Cpld:936 - The output buffer 'A_LAN<3>_OBUF' is missing an input and
+   will be deleted.
+WARNING:Cpld:936 - The output buffer 'A_LAN<2>_OBUF' is missing an input and
+   will be deleted.
+WARNING:Cpld:936 - The output buffer 'A_LAN<1>_OBUF' is missing an input and
+   will be deleted.
+WARNING:Cpld:936 - The output buffer 'A_LAN<13>_OBUF' is missing an input and
+   will be deleted.
+WARNING:Cpld:936 - The output buffer 'A_LAN<12>_OBUF' is missing an input and
+   will be deleted.
+WARNING:Cpld:936 - The output buffer 'A_LAN<11>_OBUF' is missing an input and
+   will be deleted.
+WARNING:Cpld:936 - The output buffer 'A_LAN<10>_OBUF' is missing an input and
+   will be deleted.
+WARNING:Cpld:936 - The output buffer 'A_LAN<0>_OBUF' is missing an input and
+   will be deleted.
+WARNING:Cpld:1007 - Removing unused input(s) 'A<14>'.  The input(s) are unused
+   after optimization. Please verify functionality via simulation.
+WARNING:Cpld:1007 - Removing unused input(s) 'A<15>'.  The input(s) are unused
+   after optimization. Please verify functionality via simulation.
+WARNING:Cpld:1007 - Removing unused input(s) 'A<7>'.  The input(s) are unused
+   after optimization. Please verify functionality via simulation.
+WARNING:Cpld:1007 - Removing unused input(s) 'A<8>'.  The input(s) are unused
+   after optimization. Please verify functionality via simulation.
+WARNING:Cpld:1007 - Removing unused input(s) 'CFIN'.  The input(s) are unused
+   after optimization. Please verify functionality via simulation.
+WARNING:Cpld:1007 - Removing unused input(s) 'CLK_EXT'.  The input(s) are unused
+   after optimization. Please verify functionality via simulation.
+WARNING:Cpld:1007 - Removing unused input(s) 'CP_IRQ'.  The input(s) are unused
+   after optimization. Please verify functionality via simulation.
+WARNING:Cpld:1007 - Removing unused input(s) 'DQ<0>'.  The input(s) are unused
+   after optimization. Please verify functionality via simulation.
+WARNING:Cpld:1007 - Removing unused input(s) 'DQ<10>'.  The input(s) are unused
+   after optimization. Please verify functionality via simulation.
+WARNING:Cpld:1007 - Removing unused input(s) 'DQ<11>'.  The input(s) are unused
+   after optimization. Please verify functionality via simulation.
+WARNING:Cpld:1007 - Removing unused input(s) 'DQ<12>'.  The input(s) are unused
+   after optimization. Please verify functionality via simulation.
+WARNING:Cpld:1007 - Removing unused input(s) 'DQ<13>'.  The input(s) are unused
+   after optimization. Please verify functionality via simulation.
+WARNING:Cpld:1007 - Removing unused input(s) 'DQ<14>'.  The input(s) are unused
+   after optimization. Please verify functionality via simulation.
+WARNING:Cpld:1007 - Removing unused input(s) 'DQ<15>'.  The input(s) are unused
+   after optimization. Please verify functionality via simulation.
+WARNING:Cpld:1007 - Removing unused input(s) 'DQ<1>'.  The input(s) are unused
+   after optimization. Please verify functionality via simulation.
+WARNING:Cpld:1007 - Removing unused input(s) 'DQ<2>'.  The input(s) are unused
+   after optimization. Please verify functionality via simulation.
+WARNING:Cpld:1007 - Removing unused input(s) 'DQ<3>'.  The input(s) are unused
+   after optimization. Please verify functionality via simulation.
+WARNING:Cpld:1007 - Removing unused input(s) 'DQ<4>'.  The input(s) are unused
+   after optimization. Please verify functionality via simulation.
+WARNING:Cpld:1007 - Removing unused input(s) 'DQ<5>'.  The input(s) are unused
+   after optimization. Please verify functionality via simulation.
+WARNING:Cpld:1007 - Removing unused input(s) 'DQ<6>'.  The input(s) are unused
+   after optimization. Please verify functionality via simulation.
+WARNING:Cpld:1007 - Removing unused input(s) 'DQ<7>'.  The input(s) are unused
+   after optimization. Please verify functionality via simulation.
+WARNING:Cpld:1007 - Removing unused input(s) 'DQ<8>'.  The input(s) are unused
+   after optimization. Please verify functionality via simulation.
+WARNING:Cpld:1007 - Removing unused input(s) 'DQ<9>'.  The input(s) are unused
+   after optimization. Please verify functionality via simulation.
+WARNING:Cpld:1007 - Removing unused input(s) 'DS0'.  The input(s) are unused
+   after optimization. Please verify functionality via simulation.
+WARNING:Cpld:1007 - Removing unused input(s) 'DS1'.  The input(s) are unused
+   after optimization. Please verify functionality via simulation.
+WARNING:Cpld:1007 - Removing unused input(s) 'FCS'.  The input(s) are unused
+   after optimization. Please verify functionality via simulation.
+WARNING:Cpld:1007 - Removing unused input(s) 'IDE_WAIT'.  The input(s) are
+   unused after optimization. Please verify functionality via simulation.
+WARNING:Cpld:1007 - Removing unused input(s) 'LAN_INT'.  The input(s) are unused
+   after optimization. Please verify functionality via simulation.
+WARNING:Cpld:1007 - Removing unused input(s) 'LDS'.  The input(s) are unused
+   after optimization. Please verify functionality via simulation.
+WARNING:Cpld:1007 - Removing unused input(s) 'MTCR'.  The input(s) are unused
+   after optimization. Please verify functionality via simulation.
+WARNING:Cpld:1007 - Removing unused input(s) 'Z3'.  The input(s) are unused
+   after optimization. Please verify functionality via simulation.
+WARNING:Cpld:896 - Unable to map all desired signals into function block, FB3,
+   because too many function block product terms are required. Buffering output
+   signal D<12> to allow all signals assigned to this function block to be
+   placed.
+WARNING:Cpld:896 - Unable to map all desired signals into function block, FB3,
+   because too many function block product terms are required. Buffering output
+   signal D<14> to allow all signals assigned to this function block to be
+   placed.
+WARNING:Cpld:896 - Unable to map all desired signals into function block, FB3,
+   because too many function block product terms are required. Buffering output
+   signal D<13> to allow all signals assigned to this function block to be
+   placed.
+WARNING:Cpld:896 - Unable to map all desired signals into function block, FB3,
+   because too many function block product terms are required. Buffering output
+   signal D<15> to allow all signals assigned to this function block to be
+   placed.
+*************************  Summary of Mapped Logic  ************************
+
+** 27 Outputs **
+
+Signal                     Total Total Loc     Pin  Pin     Pin     Pwr  Slew Reg Init
+Name                       Pts   Inps          No.  Type    Use     Mode Rate State
+IDE_CS<1>                  1     1     FB1_1   23   I/O     O       STD  FAST 
+D<7>                       1     2     FB1_2   16   I/O     O       STD  FAST 
+D<1>                       1     2     FB1_3   17   I/O     O       STD  FAST 
+IDE_A<2>                   1     1     FB1_4   25   I/O     O       STD  FAST 
+D<8>                       1     2     FB1_5   19   I/O     I/O     STD  FAST 
+D<5>                       1     2     FB1_6   20   I/O     O       STD  FAST 
+D<4>                       1     2     FB1_8   21   I/O     O       STD  FAST 
+IDE_CS<0>                  1     1     FB1_9   22   I/O     O       STD  FAST 
+IDE_A<0>                   1     1     FB1_11  24   I/O     O       STD  FAST 
+IDE_A<1>                   1     1     FB1_12  26   I/O     O       STD  FAST 
+IDE_R                      2     6     FB1_14  27   I/O     O       STD  FAST SET
+IDE_W                      2     5     FB1_15  28   I/O     O       STD  FAST SET
+ROM_OE                     2     6     FB1_16  35   I/O     O       STD  FAST SET
+D<0>                       1     2     FB2_5   2    GTS/I/O O       STD  FAST 
+D<6>                       1     2     FB2_16  14   I/O     O       STD  FAST 
+D<3>                       1     2     FB2_17  15   I/O     O       STD  FAST 
+D<2>                       1     2     FB3_1   39   I/O     O       STD  FAST 
+D<10>                      1     2     FB3_3   41   I/O     I/O     STD  FAST 
+D<12>                      2     3     FB3_4   44   I/O     I/O     STD  FAST 
+D<14>                      2     3     FB3_7   46   I/O     I/O     STD  FAST 
+D<9>                       1     2     FB3_9   40   I/O     I/O     STD  FAST 
+D<15>                      2     3     FB3_10  48   I/O     I/O     STD  FAST 
+D<11>                      1     2     FB3_11  43   I/O     I/O     STD  FAST 
+D<13>                      2     3     FB3_12  45   I/O     I/O     STD  FAST 
+ROM_B<0>                   0     0     FB5_10  68   I/O     O       STD  FAST 
+ROM_B<1>                   0     0     FB5_17  69   I/O     O       STD  FAST 
+DTACK                      0     0     FB7_12  85   I/O     O       STD  FAST 
+
+** 24 Buried Nodes **
+
+Signal                     Total Total Loc     Pwr  Reg Init
+Name                       Pts   Inps          Mode State
+AUTOCONFIG_IN_PROGRESS     2     3     FB1_7   STD  RESET
+IDE_ENABLE                 3     6     FB1_10  STD  RESET
+D<12>_BUFR                 19    16    FB1_18  STD  RESET
+D<14>_BUFR                 18    15    FB2_1   STD  RESET
+AUTO_CONFIG_DONE<2>        2     2     FB2_8   STD  RESET
+AUTO_CONFIG_DONE<0>        2     2     FB2_9   STD  RESET
+AUTO_CONFIG_DONE_CYCLE<2>  3     15    FB2_10  STD  RESET
+AUTO_CONFIG_DONE_CYCLE<0>  3     13    FB2_11  STD  RESET
+IDE_BASEADR<7>             4     16    FB2_12  STD  RESET
+IDE_BASEADR<6>             4     16    FB2_13  STD  RESET
+D<13>_BUFR                 17    15    FB2_15  STD  RESET
+AUTO_CONFIG_DONE<1>        2     2     FB3_15  STD  RESET
+AUTO_CONFIG_DONE_CYCLE<1>  3     14    FB3_16  STD  RESET
+IDE_BASEADR<3>             4     16    FB3_17  STD  RESET
+IDE_BASEADR<2>             4     16    FB3_18  STD  RESET
+ide                        19    19    FB4_1   STD  RESET
+ide/ide_CLKF               2     2     FB4_16  STD  
+autoconfig                 4     13    FB4_17  STD  RESET
+SHUT_UP<1>                 3     15    FB5_13  STD  RESET
+IDE_BASEADR<5>             4     16    FB5_14  STD  RESET
+IDE_BASEADR<4>             4     16    FB5_15  STD  RESET
+IDE_BASEADR<1>             4     16    FB5_16  STD  RESET
+IDE_BASEADR<0>             4     16    FB5_18  STD  RESET
+D<15>_BUFR                 14    15    FB6_17  STD  RESET
+
+** 27 Inputs **
+
+Signal                     Loc     Pin  Pin     Pin     
+Name                               No.  Type    Use     
+RESET                      FB2_2   143  GSR/I/O GSR/I
+A<5>                       FB3_14  49   I/O     I
+A<4>                       FB3_15  50   I/O     I
+A<6>                       FB3_17  51   I/O     I
+A<3>                       FB5_2   52   I/O     I
+A<10>                      FB5_3   59   I/O     I
+A<2>                       FB5_6   54   I/O     I
+A<1>                       FB5_9   57   I/O     I
+A<9>                       FB5_11  58   I/O     I
+A<11>                      FB5_12  60   I/O     I
+A<12>                      FB5_14  61   I/O     I
+A<13>                      FB5_15  64   I/O     I
+AUTOBOOT_OFF               FB7_3   75   I/O     I
+AS                         FB7_9   80   I/O     I
+UDS                        FB7_13  81   I/O     I
+A<23>                      FB7_14  86   I/O     I
+A<22>                      FB7_15  87   I/O     I
+RW                         FB7_16  83   I/O     I
+A<21>                      FB7_17  88   I/O     I
+A<20>                      FB8_2   91   I/O     I
+A<17>                      FB8_3   95   I/O     I
+A<16>                      FB8_4   97   I/O     I
+A<19>                      FB8_5   92   I/O     I
+A<18>                      FB8_8   94   I/O     I
+BERR                       FB8_11  98   I/O     I
+C1                         FB8_13  103  I/O     I
+C3                         FB8_14  102  I/O     I
+
+Legend:
+Pin No. - ~ - User Assigned
+**************************  Function Block Details  ************************
+Legend:
+Total Pt     - Total product terms used by the macrocell signal
+Imp Pt       - Product terms imported from other macrocells
+Exp Pt       - Product terms exported to other macrocells
+               in direction shown
+Unused Pt    - Unused local product terms remaining in macrocell
+Loc          - Location where logic was mapped in device
+Pin Type/Use - I  - Input             GCK - Global Clock
+               O  - Output            GTS - Global Output Enable
+              (b) - Buried macrocell  GSR - Global Set/Reset
+X            - Signal used as input to the macrocell logic.
+Pin No.      - ~  - User Assigned
+*********************************** FB1  ***********************************
+Number of function block inputs used/remaining:               24/30
+Number of signals used by logic mapping into function block:  24
+Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
+Name                Pt      Pt    Pt  Pt               #    Type    Use
+IDE_CS<1>             1       1<- /\5   0     FB1_1   23    I/O     O
+D<7>                  1       0   /\1   3     FB1_2   16    I/O     O
+D<1>                  1       0     0   4     FB1_3   17    I/O     O
+IDE_A<2>              1       0     0   4     FB1_4   25    I/O     O
+D<8>                  1       0     0   4     FB1_5   19    I/O     I/O
+D<5>                  1       0     0   4     FB1_6   20    I/O     O
+AUTOCONFIG_IN_PROGRESS
+                      2       0     0   3     FB1_7         (b)     (b)
+D<4>                  1       0     0   4     FB1_8   21    I/O     O
+IDE_CS<0>             1       0     0   4     FB1_9   22    I/O     O
+IDE_ENABLE            3       0     0   2     FB1_10  31    I/O     (b)
+IDE_A<0>              1       0     0   4     FB1_11  24    I/O     O
+IDE_A<1>              1       0     0   4     FB1_12  26    I/O     O
+(unused)              0       0     0   5     FB1_13        (b)     
+IDE_R                 2       0     0   3     FB1_14  27    I/O     O
+IDE_W                 2       0   \/1   2     FB1_15  28    I/O     O
+ROM_OE                2       1<- \/4   0     FB1_16  35    I/O     O
+(unused)              0       0   \/5   0     FB1_17  30    GCK/I/O (b)
+D<12>_BUFR           19      14<-   0   0     FB1_18        (b)     (b)
+
+Signals Used by Logic in Function Block
+  1: AS                       9: A<1>              17: A<10> 
+  2: AUTOBOOT_OFF            10: A<2>              18: A<11> 
+  3: AUTOCONFIG_IN_PROGRESS  11: A<3>              19: IDE_ENABLE 
+  4: AUTO_CONFIG_DONE<0>     12: A<4>              20: RESET 
+  5: AUTO_CONFIG_DONE<1>     13: A<5>              21: RW 
+  6: AUTO_CONFIG_DONE<2>     14: A<6>              22: autoconfig 
+  7: A<12>                   15: D<12>             23: ide 
+  8: A<13>                   16: A<9>              24: ide/ide_CLKF 
+
+Signal                        1         2         3         4 FB
+Name                0----+----0----+----0----+----0----+----0 Inputs
+IDE_CS<1>            .......X................................ 1
+D<7>                 ..X.................X................... 2
+D<1>                 ..X.................X................... 2
+IDE_A<2>             .................X...................... 1
+D<8>                 ..X.................X................... 2
+D<5>                 ..X.................X................... 2
+AUTOCONFIG_IN_PROGRESS 
+                     X....................X.X................ 3
+D<4>                 ..X.................X................... 2
+IDE_CS<0>            ......X................................. 1
+IDE_ENABLE           X.................XXX.XX................ 6
+IDE_A<0>             ...............X........................ 1
+IDE_A<1>             ................X....................... 1
+IDE_R                X.................XXX.XX................ 6
+IDE_W                X..................XX.XX................ 5
+ROM_OE               X.................XXX.XX................ 6
+D<12>_BUFR           XX.XXX..XXXXXXX....XXX.X................ 16
+                    0----+----1----+----2----+----3----+----4
+                              0         0         0         0
+*********************************** FB2  ***********************************
+Number of function block inputs used/remaining:               24/30
+Number of signals used by logic mapping into function block:  24
+Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
+Name                Pt      Pt    Pt  Pt               #    Type    Use
+D<14>_BUFR           18      13<-   0   0     FB2_1   142   I/O     (b)
+(unused)              0       0   /\5   0     FB2_2   143   GSR/I/O GSR/I
+(unused)              0       0   /\3   2     FB2_3         (b)     (b)
+(unused)              0       0     0   5     FB2_4   4     I/O     
+D<0>                  1       0     0   4     FB2_5   2     GTS/I/O O
+(unused)              0       0     0   5     FB2_6   3     GTS/I/O 
+(unused)              0       0     0   5     FB2_7         (b)     
+AUTO_CONFIG_DONE<2>   2       0     0   3     FB2_8   5     GTS/I/O (b)
+AUTO_CONFIG_DONE<0>   2       0     0   3     FB2_9   6     GTS/I/O (b)
+AUTO_CONFIG_DONE_CYCLE<2>
+                      3       0     0   2     FB2_10  7     I/O     (b)
+AUTO_CONFIG_DONE_CYCLE<0>
+                      3       0   \/1   1     FB2_11  9     I/O     (b)
+IDE_BASEADR<7>        4       1<- \/2   0     FB2_12  10    I/O     (b)
+IDE_BASEADR<6>        4       2<- \/3   0     FB2_13  12    I/O     (b)
+(unused)              0       0   \/5   0     FB2_14  11    I/O     (b)
+D<13>_BUFR           17      12<-   0   0     FB2_15  13    I/O     (b)
+D<6>                  1       0   /\4   0     FB2_16  14    I/O     O
+D<3>                  1       0     0   4     FB2_17  15    I/O     O
+(unused)              0       0   \/5   0     FB2_18        (b)     (b)
+
+Signals Used by Logic in Function Block
+  1: AS                          9: A<2>              17: IDE_BASEADR<7> 
+  2: AUTOCONFIG_IN_PROGRESS     10: A<3>              18: D<14>.PIN 
+  3: AUTO_CONFIG_DONE<0>        11: A<4>              19: D<15>.PIN 
+  4: AUTO_CONFIG_DONE<1>        12: A<5>              20: RESET 
+  5: AUTO_CONFIG_DONE<2>        13: A<6>              21: RW 
+  6: AUTO_CONFIG_DONE_CYCLE<0>  14: D<13>             22: UDS 
+  7: AUTO_CONFIG_DONE_CYCLE<2>  15: D<14>             23: autoconfig 
+  8: A<1>                       16: IDE_BASEADR<6>    24: ide/ide_CLKF 
+
+Signal                        1         2         3         4 FB
+Name                0----+----0----+----0----+----0----+----0 Inputs
+D<14>_BUFR           X.XXX..XXXXXX.X....XX.XX................ 15
+D<0>                 .X..................X................... 2
+AUTO_CONFIG_DONE<2>  X.....X................................. 2
+AUTO_CONFIG_DONE<0>  X....X.................................. 2
+AUTO_CONFIG_DONE_CYCLE<2> 
+                     X.XXX.XX.XXXX......XXXXX................ 15
+AUTO_CONFIG_DONE_CYCLE<0> 
+                     X.X..X.X.XXXX......XXXXX................ 13
+IDE_BASEADR<7>       X.XX...XXXXXX...X.XXXXXX................ 16
+IDE_BASEADR<6>       X.XX...XXXXXX..X.X.XXXXX................ 16
+D<13>_BUFR           X.XXX..XXXXXXX.....XX.XX................ 15
+D<6>                 .X..................X................... 2
+D<3>                 .X..................X................... 2
+                    0----+----1----+----2----+----3----+----4
+                              0         0         0         0
+*********************************** FB3  ***********************************
+Number of function block inputs used/remaining:               24/30
+Number of signals used by logic mapping into function block:  24
+Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
+Name                Pt      Pt    Pt  Pt               #    Type    Use
+D<2>                  1       0     0   4     FB3_1   39    I/O     O
+(unused)              0       0     0   5     FB3_2   32    GCK/I/O 
+D<10>                 1       0     0   4     FB3_3   41    I/O     I/O
+D<12>                 2       0     0   3     FB3_4   44    I/O     I/O
+(unused)              0       0     0   5     FB3_5   33    I/O     
+(unused)              0       0     0   5     FB3_6   34    I/O     
+D<14>                 2       0     0   3     FB3_7   46    I/O     I/O
+(unused)              0       0     0   5     FB3_8   38    GCK/I/O 
+D<9>                  1       0     0   4     FB3_9   40    I/O     I/O
+D<15>                 2       0     0   3     FB3_10  48    I/O     I/O
+D<11>                 1       0     0   4     FB3_11  43    I/O     I/O
+D<13>                 2       0     0   3     FB3_12  45    I/O     I/O
+(unused)              0       0     0   5     FB3_13        (b)     
+(unused)              0       0     0   5     FB3_14  49    I/O     I
+AUTO_CONFIG_DONE<1>   2       0     0   3     FB3_15  50    I/O     I
+AUTO_CONFIG_DONE_CYCLE<1>
+                      3       0     0   2     FB3_16        (b)     (b)
+IDE_BASEADR<3>        4       0     0   1     FB3_17  51    I/O     I
+IDE_BASEADR<2>        4       0     0   1     FB3_18        (b)     (b)
+
+Signals Used by Logic in Function Block
+  1: AS                          9: A<4>              17: IDE_BASEADR<3> 
+  2: AUTOCONFIG_IN_PROGRESS     10: A<5>              18: D<11>.PIN 
+  3: AUTO_CONFIG_DONE<0>        11: A<6>              19: D<10>.PIN 
+  4: AUTO_CONFIG_DONE<1>        12: D<12>_BUFR        20: RESET 
+  5: AUTO_CONFIG_DONE_CYCLE<1>  13: D<13>_BUFR        21: RW 
+  6: A<1>                       14: D<14>_BUFR        22: UDS 
+  7: A<2>                       15: D<15>_BUFR        23: autoconfig 
+  8: A<3>                       16: IDE_BASEADR<2>    24: ide/ide_CLKF 
+
+Signal                        1         2         3         4 FB
+Name                0----+----0----+----0----+----0----+----0 Inputs
+D<2>                 .X..................X................... 2
+D<10>                .X..................X................... 2
+D<12>                .X.........X........X................... 3
+D<14>                .X...........X......X................... 3
+D<9>                 .X..................X................... 2
+D<15>                .X............X.....X................... 3
+D<11>                .X..................X................... 2
+D<13>                .X..........X.......X................... 3
+AUTO_CONFIG_DONE<1>  X...X................................... 2
+AUTO_CONFIG_DONE_CYCLE<1> 
+                     X.XXXX.XXXX........XXXXX................ 14
+IDE_BASEADR<3>       X.XX.XXXXXX.....XX.XXXXX................ 16
+IDE_BASEADR<2>       X.XX.XXXXXX....X..XXXXXX................ 16
+                    0----+----1----+----2----+----3----+----4
+                              0         0         0         0
+*********************************** FB4  ***********************************
+Number of function block inputs used/remaining:               24/30
+Number of signals used by logic mapping into function block:  24
+Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
+Name                Pt      Pt    Pt  Pt               #    Type    Use
+ide                  19      14<-   0   0     FB4_1   118   I/O     (b)
+(unused)              0       0   /\5   0     FB4_2   126   I/O     (b)
+(unused)              0       0   /\3   2     FB4_3   133   I/O     (b)
+(unused)              0       0     0   5     FB4_4         (b)     
+(unused)              0       0     0   5     FB4_5   128   I/O     
+(unused)              0       0     0   5     FB4_6   129   I/O     
+(unused)              0       0     0   5     FB4_7         (b)     
+(unused)              0       0     0   5     FB4_8   130   I/O     
+(unused)              0       0     0   5     FB4_9   131   I/O     
+(unused)              0       0     0   5     FB4_10  135   I/O     
+(unused)              0       0     0   5     FB4_11  132   I/O     
+(unused)              0       0     0   5     FB4_12  134   I/O     
+(unused)              0       0     0   5     FB4_13  137   I/O     
+(unused)              0       0     0   5     FB4_14  136   I/O     
+(unused)              0       0     0   5     FB4_15  138   I/O     
+ide/ide_CLKF          2       0     0   3     FB4_16  139   I/O     (b)
+autoconfig            4       0   \/1   0     FB4_17  140   I/O     (b)
+(unused)              0       0   \/5   0     FB4_18        (b)     (b)
+
+Signals Used by Logic in Function Block
+  1: AUTO_CONFIG_DONE<0>   9: A<21>             17: IDE_BASEADR<2> 
+  2: AUTO_CONFIG_DONE<1>  10: A<22>             18: IDE_BASEADR<3> 
+  3: AUTO_CONFIG_DONE<2>  11: A<23>             19: IDE_BASEADR<4> 
+  4: A<16>                12: BERR              20: IDE_BASEADR<5> 
+  5: A<17>                13: C1                21: IDE_BASEADR<6> 
+  6: A<18>                14: C3                22: IDE_BASEADR<7> 
+  7: A<19>                15: IDE_BASEADR<0>    23: SHUT_UP<1> 
+  8: A<20>                16: IDE_BASEADR<1>    24: ide/ide_CLKF 
+
+Signal                        1         2         3         4 FB
+Name                0----+----0----+----0----+----0----+----0 Inputs
+ide                  ...XXXXXXXXX..XXXXXXXXXX................ 19
+ide/ide_CLKF         ............XX.......................... 2
+autoconfig           XXXXXXXXXXXX...........X................ 13
+                    0----+----1----+----2----+----3----+----4
+                              0         0         0         0
+*********************************** FB5  ***********************************
+Number of function block inputs used/remaining:               23/31
+Number of signals used by logic mapping into function block:  23
+Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
+Name                Pt      Pt    Pt  Pt               #    Type    Use
+(unused)              0       0     0   5     FB5_1         (b)     
+(unused)              0       0     0   5     FB5_2   52    I/O     I
+(unused)              0       0     0   5     FB5_3   59    I/O     I
+(unused)              0       0     0   5     FB5_4         (b)     
+(unused)              0       0     0   5     FB5_5   53    I/O     
+(unused)              0       0     0   5     FB5_6   54    I/O     I
+(unused)              0       0     0   5     FB5_7   66    I/O     
+(unused)              0       0     0   5     FB5_8   56    I/O     
+(unused)              0       0     0   5     FB5_9   57    I/O     I
+ROM_B<0>              0       0     0   5     FB5_10  68    I/O     O
+(unused)              0       0     0   5     FB5_11  58    I/O     I
+(unused)              0       0     0   5     FB5_12  60    I/O     I
+SHUT_UP<1>            3       0     0   2     FB5_13  70    I/O     (b)
+IDE_BASEADR<5>        4       0     0   1     FB5_14  61    I/O     I
+IDE_BASEADR<4>        4       0     0   1     FB5_15  64    I/O     I
+IDE_BASEADR<1>        4       0     0   1     FB5_16        (b)     (b)
+ROM_B<1>              0       0     0   5     FB5_17  69    I/O     O
+IDE_BASEADR<0>        4       0     0   1     FB5_18        (b)     (b)
+
+Signals Used by Logic in Function Block
+  1: AS                    9: A<6>              17: D<9>.PIN 
+  2: AUTO_CONFIG_DONE<0>  10: IDE_BASEADR<0>    18: RESET 
+  3: AUTO_CONFIG_DONE<1>  11: IDE_BASEADR<1>    19: RW 
+  4: A<1>                 12: IDE_BASEADR<4>    20: SHUT_UP<1> 
+  5: A<2>                 13: IDE_BASEADR<5>    21: UDS 
+  6: A<3>                 14: D<12>.PIN         22: autoconfig 
+  7: A<4>                 15: D<13>.PIN         23: ide/ide_CLKF 
+  8: A<5>                 16: D<8>.PIN         
+
+Signal                        1         2         3         4 FB
+Name                0----+----0----+----0----+----0----+----0 Inputs
+ROM_B<0>             ........................................ 0
+SHUT_UP<1>           XXXXXXXXX........XXXXXX................. 15
+IDE_BASEADR<5>       XXXXXXXXX...X.X..XX.XXX................. 16
+IDE_BASEADR<4>       XXXXXXXXX..X.X...XX.XXX................. 16
+IDE_BASEADR<1>       XXXXXXXXX.X.....XXX.XXX................. 16
+ROM_B<1>             ........................................ 0
+IDE_BASEADR<0>       XXXXXXXXXX.....X.XX.XXX................. 16
+                    0----+----1----+----2----+----3----+----4
+                              0         0         0         0
+*********************************** FB6  ***********************************
+Number of function block inputs used/remaining:               15/39
+Number of signals used by logic mapping into function block:  15
+Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
+Name                Pt      Pt    Pt  Pt               #    Type    Use
+(unused)              0       0     0   5     FB6_1         (b)     
+(unused)              0       0     0   5     FB6_2   106   I/O     
+(unused)              0       0     0   5     FB6_3         (b)     
+(unused)              0       0     0   5     FB6_4   111   I/O     
+(unused)              0       0     0   5     FB6_5   110   I/O     
+(unused)              0       0     0   5     FB6_6   112   I/O     
+(unused)              0       0     0   5     FB6_7         (b)     
+(unused)              0       0     0   5     FB6_8   113   I/O     
+(unused)              0       0     0   5     FB6_9   116   I/O     
+(unused)              0       0     0   5     FB6_10  115   I/O     
+(unused)              0       0     0   5     FB6_11  119   I/O     
+(unused)              0       0     0   5     FB6_12  120   I/O     
+(unused)              0       0     0   5     FB6_13        (b)     
+(unused)              0       0     0   5     FB6_14  121   I/O     
+(unused)              0       0     0   5     FB6_15  124   I/O     
+(unused)              0       0   \/4   1     FB6_16  117   I/O     (b)
+D<15>_BUFR           14       9<-   0   0     FB6_17  125   I/O     (b)
+(unused)              0       0   /\5   0     FB6_18        (b)     (b)
+
+Signals Used by Logic in Function Block
+  1: AS                    6: A<2>              11: D<15> 
+  2: AUTO_CONFIG_DONE<0>   7: A<3>              12: RESET 
+  3: AUTO_CONFIG_DONE<1>   8: A<4>              13: RW 
+  4: AUTO_CONFIG_DONE<2>   9: A<5>              14: autoconfig 
+  5: A<1>                 10: A<6>              15: ide/ide_CLKF 
+
+Signal                        1         2         3         4 FB
+Name                0----+----0----+----0----+----0----+----0 Inputs
+D<15>_BUFR           XXXXXXXXXXXXXXX......................... 15
+                    0----+----1----+----2----+----3----+----4
+                              0         0         0         0
+*********************************** FB7  ***********************************
+Number of function block inputs used/remaining:               0/54
+Number of signals used by logic mapping into function block:  0
+Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
+Name                Pt      Pt    Pt  Pt               #    Type    Use
+(unused)              0       0     0   5     FB7_1         (b)     
+(unused)              0       0     0   5     FB7_2   71    I/O     
+(unused)              0       0     0   5     FB7_3   75    I/O     I
+(unused)              0       0     0   5     FB7_4         (b)     
+(unused)              0       0     0   5     FB7_5   74    I/O     
+(unused)              0       0     0   5     FB7_6   76    I/O     
+(unused)              0       0     0   5     FB7_7   77    I/O     
+(unused)              0       0     0   5     FB7_8   78    I/O     
+(unused)              0       0     0   5     FB7_9   80    I/O     I
+(unused)              0       0     0   5     FB7_10  79    I/O     
+(unused)              0       0     0   5     FB7_11  82    I/O     
+DTACK                 0       0     0   5     FB7_12  85    I/O     O
+(unused)              0       0     0   5     FB7_13  81    I/O     I
+(unused)              0       0     0   5     FB7_14  86    I/O     I
+(unused)              0       0     0   5     FB7_15  87    I/O     I
+(unused)              0       0     0   5     FB7_16  83    I/O     I
+(unused)              0       0     0   5     FB7_17  88    I/O     I
+(unused)              0       0     0   5     FB7_18        (b)     
+
+Signals Used by Logic in Function Block
+
+Signal                        1         2         3         4 FB
+Name                0----+----0----+----0----+----0----+----0 Inputs
+DTACK                ........................................ 0
+                    0----+----1----+----2----+----3----+----4
+                              0         0         0         0
+*********************************** FB8  ***********************************
+Number of function block inputs used/remaining:               0/54
+Number of signals used by logic mapping into function block:  0
+Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
+Name                Pt      Pt    Pt  Pt               #    Type    Use
+(unused)              0       0     0   5     FB8_1         (b)     
+(unused)              0       0     0   5     FB8_2   91    I/O     I
+(unused)              0       0     0   5     FB8_3   95    I/O     I
+(unused)              0       0     0   5     FB8_4   97    I/O     I
+(unused)              0       0     0   5     FB8_5   92    I/O     I
+(unused)              0       0     0   5     FB8_6   93    I/O     
+(unused)              0       0     0   5     FB8_7         (b)     
+(unused)              0       0     0   5     FB8_8   94    I/O     I
+(unused)              0       0     0   5     FB8_9   96    I/O     
+(unused)              0       0     0   5     FB8_10  101   I/O     
+(unused)              0       0     0   5     FB8_11  98    I/O     I
+(unused)              0       0     0   5     FB8_12  100   I/O     
+(unused)              0       0     0   5     FB8_13  103   I/O     I
+(unused)              0       0     0   5     FB8_14  102   I/O     I
+(unused)              0       0     0   5     FB8_15  104   I/O     
+(unused)              0       0     0   5     FB8_16  107   I/O     
+(unused)              0       0     0   5     FB8_17  105   I/O     
+(unused)              0       0     0   5     FB8_18        (b)     
+*******************************  Equations  ********************************
+
+********** Mapped Logic **********
+
+FDCPE_AUTOCONFIG_IN_PROGRESS: FDCPE port map (AUTOCONFIG_IN_PROGRESS,AUTOCONFIG_IN_PROGRESS_D,ide/ide_CLKF,'0','0');
+AUTOCONFIG_IN_PROGRESS_D <= (NOT AS AND autoconfig);
+
+FDCPE_AUTO_CONFIG_DONE0: FDCPE port map (AUTO_CONFIG_DONE(0),AUTO_CONFIG_DONE_CYCLE(0),AS,NOT RESET,'0');
+
+FDCPE_AUTO_CONFIG_DONE1: FDCPE port map (AUTO_CONFIG_DONE(1),AUTO_CONFIG_DONE_CYCLE(1),AS,NOT RESET,'0');
+
+FDCPE_AUTO_CONFIG_DONE2: FDCPE port map (AUTO_CONFIG_DONE(2),AUTO_CONFIG_DONE_CYCLE(2),AS,NOT RESET,'0');
+
+FDCPE_AUTO_CONFIG_DONE_CYCLE0: FDCPE port map (AUTO_CONFIG_DONE_CYCLE(0),AUTO_CONFIG_DONE_CYCLE_D(0),ide/ide_CLKF,'0','0');
+AUTO_CONFIG_DONE_CYCLE_D(0) <= ((RESET AND AUTO_CONFIG_DONE_CYCLE(0))
+	OR (RESET AND NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND 
+	A(6) AND A(3) AND NOT AUTO_CONFIG_DONE(0) AND autoconfig));
+
+FDCPE_AUTO_CONFIG_DONE_CYCLE1: FDCPE port map (AUTO_CONFIG_DONE_CYCLE(1),AUTO_CONFIG_DONE_CYCLE_D(1),ide/ide_CLKF,'0','0');
+AUTO_CONFIG_DONE_CYCLE_D(1) <= ((RESET AND AUTO_CONFIG_DONE_CYCLE(1))
+	OR (RESET AND NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND 
+	A(6) AND A(3) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND 
+	autoconfig));
+
+FDCPE_AUTO_CONFIG_DONE_CYCLE2: FDCPE port map (AUTO_CONFIG_DONE_CYCLE(2),AUTO_CONFIG_DONE_CYCLE_D(2),ide/ide_CLKF,'0','0');
+AUTO_CONFIG_DONE_CYCLE_D(2) <= ((RESET AND AUTO_CONFIG_DONE_CYCLE(2))
+	OR (RESET AND NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND 
+	A(6) AND A(3) AND AUTO_CONFIG_DONE(0) AND AUTO_CONFIG_DONE(1) AND 
+	NOT AUTO_CONFIG_DONE(2) AND autoconfig));
+
+
+D_I(0) <= '1';
+D(0) <= D_I(0) when D_OE(0) = '1' else 'Z';
+D_OE(0) <= (RW AND AUTOCONFIG_IN_PROGRESS);
+
+
+D_I(1) <= '1';
+D(1) <= D_I(1) when D_OE(1) = '1' else 'Z';
+D_OE(1) <= (RW AND AUTOCONFIG_IN_PROGRESS);
+
+
+D_I(2) <= '1';
+D(2) <= D_I(2) when D_OE(2) = '1' else 'Z';
+D_OE(2) <= (RW AND AUTOCONFIG_IN_PROGRESS);
+
+
+D_I(3) <= '1';
+D(3) <= D_I(3) when D_OE(3) = '1' else 'Z';
+D_OE(3) <= (RW AND AUTOCONFIG_IN_PROGRESS);
+
+
+D_I(4) <= '1';
+D(4) <= D_I(4) when D_OE(4) = '1' else 'Z';
+D_OE(4) <= (RW AND AUTOCONFIG_IN_PROGRESS);
+
+
+D_I(5) <= '1';
+D(5) <= D_I(5) when D_OE(5) = '1' else 'Z';
+D_OE(5) <= (RW AND AUTOCONFIG_IN_PROGRESS);
+
+
+D_I(6) <= '1';
+D(6) <= D_I(6) when D_OE(6) = '1' else 'Z';
+D_OE(6) <= (RW AND AUTOCONFIG_IN_PROGRESS);
+
+
+D_I(7) <= '1';
+D(7) <= D_I(7) when D_OE(7) = '1' else 'Z';
+D_OE(7) <= (RW AND AUTOCONFIG_IN_PROGRESS);
+
+
+D_I(8) <= '1';
+D(8) <= D_I(8) when D_OE(8) = '1' else 'Z';
+D_OE(8) <= (RW AND AUTOCONFIG_IN_PROGRESS);
+
+
+D_I(9) <= '1';
+D(9) <= D_I(9) when D_OE(9) = '1' else 'Z';
+D_OE(9) <= (RW AND AUTOCONFIG_IN_PROGRESS);
+
+
+D_I(10) <= '1';
+D(10) <= D_I(10) when D_OE(10) = '1' else 'Z';
+D_OE(10) <= (RW AND AUTOCONFIG_IN_PROGRESS);
+
+
+D_I(11) <= '1';
+D(11) <= D_I(11) when D_OE(11) = '1' else 'Z';
+D_OE(11) <= (RW AND AUTOCONFIG_IN_PROGRESS);
+
+FDCPE_D12_BUFR: FDCPE port map (D(12)_BUFR,D_D(12)_BUFR,ide/ide_CLKF,'0','0');
+D_D(12)_BUFR <= ((RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND A(6) AND NOT A(3) AND 
+	NOT A(2) AND NOT AUTO_CONFIG_DONE(0) AND autoconfig)
+	OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND A(6) AND NOT A(3) AND 
+	NOT A(2) AND NOT AUTO_CONFIG_DONE(1) AND autoconfig)
+	OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND A(6) AND NOT A(3) AND 
+	NOT A(2) AND NOT AUTO_CONFIG_DONE(2) AND autoconfig)
+	OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(1) AND NOT A(6) AND NOT A(3) AND 
+	A(2) AND NOT AUTO_CONFIG_DONE(0) AND autoconfig)
+	OR (RESET AND RW AND NOT AS AND A(5) AND NOT A(4) AND A(1) AND NOT A(6) AND 
+	A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND 
+	autoconfig)
+	OR (ROM_OE_S.EXP)
+	OR (RESET AND NOT D(12) AND NOT RW)
+	OR (RESET AND NOT D(12) AND AS)
+	OR (RESET AND NOT D(12) AND NOT autoconfig)
+	OR (RESET AND NOT D(12) AND AUTO_CONFIG_DONE(0) AND 
+	AUTO_CONFIG_DONE(1) AND AUTO_CONFIG_DONE(2))
+	OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND NOT A(3) AND 
+	NOT A(2) AND NOT AUTO_CONFIG_DONE(0) AND autoconfig)
+	OR (RESET AND RW AND NOT AS AND NOT A(4) AND A(1) AND NOT A(6) AND NOT A(3) AND 
+	A(2) AND NOT AUTO_CONFIG_DONE(0) AND autoconfig)
+	OR (RESET AND RW AND NOT AS AND NOT A(5) AND A(4) AND NOT A(6) AND A(3) AND 
+	NOT A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND 
+	autoconfig)
+	OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND NOT A(3) AND 
+	NOT A(2) AND AUTO_CONFIG_DONE(1) AND NOT AUTO_CONFIG_DONE(2) AND 
+	autoconfig)
+	OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND NOT A(3) AND 
+	NOT A(2) AND NOT AUTO_CONFIG_DONE(1) AND AUTOBOOT_OFF AND autoconfig));
+
+
+D_I(12) <= D(12)_BUFR;
+D(12) <= D_I(12) when D_OE(12) = '1' else 'Z';
+D_OE(12) <= (RW AND AUTOCONFIG_IN_PROGRESS);
+
+FDCPE_D13_BUFR: FDCPE port map (D(13)_BUFR,D_D(13)_BUFR,ide/ide_CLKF,'0','0');
+D_D(13)_BUFR <= ((IDE_BASEADR(6).EXP)
+	OR (RESET AND NOT D(13) AND NOT RW)
+	OR (RESET AND NOT D(13) AND AUTO_CONFIG_DONE(0) AND 
+	AUTO_CONFIG_DONE(1) AND AUTO_CONFIG_DONE(2))
+	OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(6) AND NOT A(3) AND 
+	NOT AUTO_CONFIG_DONE(0) AND autoconfig)
+	OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(3) AND NOT A(2) AND 
+	NOT AUTO_CONFIG_DONE(0) AND autoconfig)
+	OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(3) AND NOT A(2) AND 
+	NOT AUTO_CONFIG_DONE(1) AND autoconfig)
+	OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(3) AND NOT A(2) AND 
+	NOT AUTO_CONFIG_DONE(2) AND autoconfig)
+	OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND A(1) AND NOT A(6) AND 
+	NOT A(3) AND NOT AUTO_CONFIG_DONE(1) AND autoconfig)
+	OR (RESET AND RW AND NOT AS AND NOT A(5) AND A(1) AND NOT A(6) AND NOT A(3) AND 
+	NOT A(2) AND NOT AUTO_CONFIG_DONE(0) AND autoconfig)
+	OR (RESET AND RW AND NOT AS AND NOT A(5) AND A(4) AND NOT A(1) AND NOT A(6) AND 
+	A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND 
+	autoconfig)
+	OR (RESET AND NOT D(13) AND AS)
+	OR (RESET AND NOT D(13) AND NOT autoconfig)
+	OR (RESET AND RW AND NOT AS AND NOT A(5) AND A(4) AND NOT A(6) AND A(3) AND 
+	A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND 
+	autoconfig)
+	OR (RESET AND RW AND NOT AS AND NOT A(5) AND A(1) AND NOT A(6) AND NOT A(3) AND 
+	NOT A(2) AND AUTO_CONFIG_DONE(1) AND NOT AUTO_CONFIG_DONE(2) AND 
+	autoconfig));
+
+
+D_I(13) <= D(13)_BUFR;
+D(13) <= D_I(13) when D_OE(13) = '1' else 'Z';
+D_OE(13) <= (RW AND AUTOCONFIG_IN_PROGRESS);
+
+
+D_I(14) <= D(14)_BUFR;
+D(14) <= D_I(14) when D_OE(14) = '1' else 'Z';
+D_OE(14) <= (RW AND AUTOCONFIG_IN_PROGRESS);
+
+FDCPE_D14_BUFR: FDCPE port map (D(14)_BUFR,D_D(14)_BUFR,ide/ide_CLKF,'0','0');
+D_D(14)_BUFR <= ((EXP16_.EXP)
+	OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND A(1) AND NOT A(3) AND 
+	NOT A(2) AND NOT AUTO_CONFIG_DONE(0) AND autoconfig)
+	OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND A(6) AND NOT A(3) AND 
+	NOT A(2) AND NOT AUTO_CONFIG_DONE(0) AND autoconfig)
+	OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND A(6) AND NOT A(3) AND 
+	NOT A(2) AND NOT AUTO_CONFIG_DONE(1) AND autoconfig)
+	OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND A(6) AND NOT A(3) AND 
+	NOT A(2) AND NOT AUTO_CONFIG_DONE(2) AND autoconfig)
+	OR (RESET AND RW AND NOT AS AND NOT A(4) AND A(1) AND NOT A(6) AND NOT A(3) AND 
+	A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND 
+	autoconfig)
+	OR (RESET AND NOT D(14) AND NOT RW)
+	OR (RESET AND NOT D(14) AND AS)
+	OR (RESET AND NOT D(14) AND NOT autoconfig)
+	OR (RESET AND NOT D(14) AND AUTO_CONFIG_DONE(0) AND 
+	AUTO_CONFIG_DONE(1) AND AUTO_CONFIG_DONE(2))
+	OR (RESET AND RW AND NOT AS AND NOT A(5) AND A(1) AND NOT A(6) AND NOT A(3) AND 
+	A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(2) AND 
+	autoconfig)
+	OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND A(1) AND NOT A(3) AND 
+	NOT A(2) AND NOT AUTO_CONFIG_DONE(1) AND autoconfig)
+	OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND A(1) AND NOT A(3) AND 
+	NOT A(2) AND NOT AUTO_CONFIG_DONE(2) AND autoconfig)
+	OR (RESET AND RW AND NOT AS AND NOT A(5) AND A(1) AND NOT A(6) AND NOT A(3) AND 
+	A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND 
+	autoconfig)
+	OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(6) AND NOT A(3) AND 
+	A(2) AND AUTO_CONFIG_DONE(0) AND AUTO_CONFIG_DONE(1) AND 
+	NOT AUTO_CONFIG_DONE(2) AND autoconfig));
+
+
+D_I(15) <= D(15)_BUFR;
+D(15) <= D_I(15) when D_OE(15) = '1' else 'Z';
+D_OE(15) <= (RW AND AUTOCONFIG_IN_PROGRESS);
+
+FDCPE_D15_BUFR: FDCPE port map (D(15)_BUFR,D_D(15)_BUFR,ide/ide_CLKF,'0','0');
+D_D(15)_BUFR <= ((RESET AND NOT D(15) AND AUTO_CONFIG_DONE(0) AND 
+	AUTO_CONFIG_DONE(1) AND AUTO_CONFIG_DONE(2))
+	OR (RESET AND RW AND NOT AS AND NOT A(5) AND A(1) AND NOT A(6) AND NOT A(3) AND 
+	NOT AUTO_CONFIG_DONE(0) AND autoconfig)
+	OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND A(6) AND NOT A(3) AND 
+	NOT A(2) AND NOT AUTO_CONFIG_DONE(0) AND autoconfig)
+	OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND A(6) AND NOT A(3) AND 
+	NOT A(2) AND NOT AUTO_CONFIG_DONE(1) AND autoconfig)
+	OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND A(6) AND NOT A(3) AND 
+	NOT A(2) AND NOT AUTO_CONFIG_DONE(2) AND autoconfig)
+	OR (RESET AND RW AND NOT AS AND NOT A(5) AND A(1) AND NOT A(6) AND NOT A(3) AND 
+	AUTO_CONFIG_DONE(1) AND NOT AUTO_CONFIG_DONE(2) AND autoconfig)
+	OR (RESET AND RW AND NOT AS AND NOT A(5) AND A(4) AND A(1) AND NOT A(6) AND 
+	A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND 
+	autoconfig)
+	OR (RESET AND RW AND NOT AS AND A(5) AND NOT A(4) AND NOT A(1) AND NOT A(6) AND 
+	NOT A(3) AND A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND 
+	autoconfig)
+	OR (RESET AND RW AND NOT AS AND NOT A(5) AND A(4) AND NOT A(1) AND NOT A(6) AND 
+	A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND 
+	autoconfig)
+	OR (RESET AND NOT D(15) AND NOT RW)
+	OR (RESET AND NOT D(15) AND AS)
+	OR (RESET AND NOT D(15) AND NOT autoconfig)
+	OR (RESET AND RW AND NOT AS AND NOT A(5) AND A(1) AND NOT A(6) AND NOT A(3) AND 
+	NOT A(2) AND NOT AUTO_CONFIG_DONE(1) AND autoconfig));
+
+
+DTACK_I <= '0';
+DTACK <= DTACK_I when DTACK_OE = '1' else 'Z';
+DTACK_OE <= '0';
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+IDE_A(0) <= A(9);
+
+
+IDE_A(1) <= A(10);
+
+
+IDE_A(2) <= A(11);
+
+FTCPE_IDE_BASEADR0: FTCPE port map (IDE_BASEADR(0),IDE_BASEADR_T(0),ide/ide_CLKF,'0','0');
+IDE_BASEADR_T(0) <= ((NOT RESET AND NOT IDE_BASEADR(0))
+	OR (NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND A(6) AND 
+	A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND 
+	NOT IDE_BASEADR(0) AND autoconfig AND D(8).PIN)
+	OR (RESET AND NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND 
+	A(6) AND A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND 
+	NOT AUTO_CONFIG_DONE(1) AND IDE_BASEADR(0) AND autoconfig AND NOT D(8).PIN));
+
+FTCPE_IDE_BASEADR1: FTCPE port map (IDE_BASEADR(1),IDE_BASEADR_T(1),ide/ide_CLKF,'0','0');
+IDE_BASEADR_T(1) <= ((NOT RESET AND NOT IDE_BASEADR(1))
+	OR (NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND A(6) AND 
+	A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND 
+	NOT IDE_BASEADR(1) AND autoconfig AND D(9).PIN)
+	OR (RESET AND NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND 
+	A(6) AND A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND 
+	NOT AUTO_CONFIG_DONE(1) AND IDE_BASEADR(1) AND autoconfig AND NOT D(9).PIN));
+
+FTCPE_IDE_BASEADR2: FTCPE port map (IDE_BASEADR(2),IDE_BASEADR_T(2),ide/ide_CLKF,'0','0');
+IDE_BASEADR_T(2) <= ((NOT RESET AND NOT IDE_BASEADR(2))
+	OR (NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND A(6) AND 
+	A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND 
+	NOT IDE_BASEADR(2) AND autoconfig AND D(10).PIN)
+	OR (RESET AND NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND 
+	A(6) AND A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND 
+	NOT AUTO_CONFIG_DONE(1) AND IDE_BASEADR(2) AND autoconfig AND NOT D(10).PIN));
+
+FTCPE_IDE_BASEADR3: FTCPE port map (IDE_BASEADR(3),IDE_BASEADR_T(3),ide/ide_CLKF,'0','0');
+IDE_BASEADR_T(3) <= ((NOT RESET AND NOT IDE_BASEADR(3))
+	OR (NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND A(6) AND 
+	A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND 
+	NOT IDE_BASEADR(3) AND autoconfig AND D(11).PIN)
+	OR (RESET AND NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND 
+	A(6) AND A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND 
+	NOT AUTO_CONFIG_DONE(1) AND IDE_BASEADR(3) AND autoconfig AND NOT D(11).PIN));
+
+FTCPE_IDE_BASEADR4: FTCPE port map (IDE_BASEADR(4),IDE_BASEADR_T(4),ide/ide_CLKF,'0','0');
+IDE_BASEADR_T(4) <= ((NOT RESET AND NOT IDE_BASEADR(4))
+	OR (NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND A(6) AND 
+	A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND 
+	NOT IDE_BASEADR(4) AND autoconfig AND D(12).PIN)
+	OR (RESET AND NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND 
+	A(6) AND A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND 
+	NOT AUTO_CONFIG_DONE(1) AND IDE_BASEADR(4) AND autoconfig AND NOT D(12).PIN));
+
+FTCPE_IDE_BASEADR5: FTCPE port map (IDE_BASEADR(5),IDE_BASEADR_T(5),ide/ide_CLKF,'0','0');
+IDE_BASEADR_T(5) <= ((NOT RESET AND NOT IDE_BASEADR(5))
+	OR (NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND A(6) AND 
+	A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND 
+	NOT IDE_BASEADR(5) AND autoconfig AND D(13).PIN)
+	OR (RESET AND NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND 
+	A(6) AND A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND 
+	NOT AUTO_CONFIG_DONE(1) AND IDE_BASEADR(5) AND autoconfig AND NOT D(13).PIN));
+
+FTCPE_IDE_BASEADR6: FTCPE port map (IDE_BASEADR(6),IDE_BASEADR_T(6),ide/ide_CLKF,'0','0');
+IDE_BASEADR_T(6) <= ((NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND A(6) AND 
+	A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND 
+	NOT IDE_BASEADR(6) AND autoconfig AND D(14).PIN)
+	OR (RESET AND NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND 
+	A(6) AND A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND 
+	NOT AUTO_CONFIG_DONE(1) AND IDE_BASEADR(6) AND autoconfig AND NOT D(14).PIN)
+	OR (NOT RESET AND NOT IDE_BASEADR(6)));
+
+FTCPE_IDE_BASEADR7: FTCPE port map (IDE_BASEADR(7),IDE_BASEADR_T(7),ide/ide_CLKF,'0','0');
+IDE_BASEADR_T(7) <= ((RESET AND NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND 
+	A(6) AND A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND 
+	NOT AUTO_CONFIG_DONE(1) AND IDE_BASEADR(7) AND autoconfig AND NOT D(15).PIN)
+	OR (NOT RESET AND NOT IDE_BASEADR(7))
+	OR (NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND A(6) AND 
+	A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND 
+	NOT IDE_BASEADR(7) AND autoconfig AND D(15).PIN));
+
+
+IDE_CS(0) <= NOT A(12);
+
+
+IDE_CS(1) <= NOT A(13);
+
+FDCPE_IDE_ENABLE: FDCPE port map (IDE_ENABLE,IDE_ENABLE_D,ide/ide_CLKF,'0','0');
+IDE_ENABLE_D <= ((RESET AND NOT IDE_ENABLE)
+	OR (RESET AND NOT RW AND NOT AS AND ide));
+
+FDCPE_IDE_R: FDCPE port map (IDE_R,IDE_R_D,ide/ide_CLKF,'0','0');
+IDE_R_D <= (RESET AND RW AND NOT AS AND NOT IDE_ENABLE AND ide);
+
+FDCPE_IDE_W: FDCPE port map (IDE_W,IDE_W_D,ide/ide_CLKF,'0','0');
+IDE_W_D <= (RESET AND NOT RW AND NOT AS AND ide);
+
+
+ROM_B(0) <= '0';
+
+
+ROM_B(1) <= '0';
+
+FDCPE_ROM_OE: FDCPE port map (ROM_OE,ROM_OE_D,ide/ide_CLKF,'0','0');
+ROM_OE_D <= (RESET AND RW AND NOT AS AND IDE_ENABLE AND ide);
+
+FDCPE_SHUT_UP1: FDCPE port map (SHUT_UP(1),SHUT_UP_D(1),ide/ide_CLKF,'0','0');
+SHUT_UP_D(1) <= ((RESET AND NOT SHUT_UP(1))
+	OR (RESET AND NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND 
+	A(6) AND A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND 
+	NOT AUTO_CONFIG_DONE(1) AND autoconfig));
+
+FDCPE_autoconfig: FDCPE port map (autoconfig,autoconfig_D,ide/ide_CLKF,'0','0');
+autoconfig_D <= ((A(23) AND A(22) AND A(21) AND A(19) AND 
+	NOT AUTO_CONFIG_DONE(0) AND BERR AND NOT A(17) AND NOT A(16) AND NOT A(20) AND NOT A(18))
+	OR (A(23) AND A(22) AND A(21) AND A(19) AND 
+	NOT AUTO_CONFIG_DONE(1) AND BERR AND NOT A(17) AND NOT A(16) AND NOT A(20) AND NOT A(18))
+	OR (A(23) AND A(22) AND A(21) AND A(19) AND 
+	NOT AUTO_CONFIG_DONE(2) AND BERR AND NOT A(17) AND NOT A(16) AND NOT A(20) AND NOT A(18)));
+
+FDCPE_ide: FDCPE port map (ide,ide_D,ide/ide_CLKF,'0','0');
+ide_D <= ((SHUT_UP(1))
+	OR (NOT BERR)
+	OR (EXP20_.EXP)
+	OR (A(23) AND NOT IDE_BASEADR(7))
+	OR (NOT A(23) AND IDE_BASEADR(7))
+	OR (A(22) AND NOT IDE_BASEADR(6))
+	OR (NOT A(22) AND IDE_BASEADR(6))
+	OR (IDE_BASEADR(1) AND NOT A(17))
+	OR (autoconfig.EXP)
+	OR (IDE_BASEADR(0) AND NOT A(16))
+	OR (NOT IDE_BASEADR(0) AND A(16))
+	OR (NOT IDE_BASEADR(1) AND A(17))
+	OR (IDE_BASEADR(2) AND NOT A(18))
+	OR (NOT IDE_BASEADR(2) AND A(18))
+	OR (A(19) AND NOT IDE_BASEADR(3))
+	OR (NOT A(19) AND IDE_BASEADR(3)));
+
+
+ide/ide_CLKF <= NOT (C3
+	 XOR 
+ide/ide_CLKF <= NOT (C1);
+
+Register Legend:
+ FDCPE (Q,D,C,CLR,PRE,CE); 
+ FTCPE (Q,D,C,CLR,PRE,CE); 
+ LDCP  (Q,D,G,CLR,PRE); 
+
+******************************  Device Pin Out *****************************
+
+Device : XC95144XL-10-TQ144
+
+
+Pin Signal                         Pin Signal                        
+No. Name                           No. Name                          
+  1 VCC                              73 VCC                           
+  2 D<0>                             74 KPR                           
+  3 KPR                              75 AUTOBOOT_OFF                  
+  4 KPR                              76 KPR                           
+  5 KPR                              77 KPR                           
+  6 KPR                              78 KPR                           
+  7 KPR                              79 KPR                           
+  8 VCC                              80 AS                            
+  9 KPR                              81 UDS                           
+ 10 KPR                              82 KPR                           
+ 11 KPR                              83 RW                            
+ 12 KPR                              84 VCC                           
+ 13 KPR                              85 DTACK                         
+ 14 D<6>                             86 A<23>                         
+ 15 D<3>                             87 A<22>                         
+ 16 D<7>                             88 A<21>                         
+ 17 D<1>                             89 GND                           
+ 18 GND                              90 GND                           
+ 19 D<8>                             91 A<20>                         
+ 20 D<5>                             92 A<19>                         
+ 21 D<4>                             93 KPR                           
+ 22 IDE_CS<0>                        94 A<18>                         
+ 23 IDE_CS<1>                        95 A<17>                         
+ 24 IDE_A<0>                         96 KPR                           
+ 25 IDE_A<2>                         97 A<16>                         
+ 26 IDE_A<1>                         98 BERR                          
+ 27 IDE_R                            99 GND                           
+ 28 IDE_W                           100 KPR                           
+ 29 GND                             101 KPR                           
+ 30 KPR                             102 C3                            
+ 31 KPR                             103 C1                            
+ 32 KPR                             104 KPR                           
+ 33 KPR                             105 KPR                           
+ 34 KPR                             106 KPR                           
+ 35 ROM_OE                          107 KPR                           
+ 36 GND                             108 GND                           
+ 37 VCC                             109 VCC                           
+ 38 KPR                             110 KPR                           
+ 39 D<2>                            111 KPR                           
+ 40 D<9>                            112 KPR                           
+ 41 D<10>                           113 KPR                           
+ 42 VCC                             114 GND                           
+ 43 D<11>                           115 KPR                           
+ 44 D<12>                           116 KPR                           
+ 45 D<13>                           117 KPR                           
+ 46 D<14>                           118 KPR                           
+ 47 GND                             119 KPR                           
+ 48 D<15>                           120 KPR                           
+ 49 A<5>                            121 KPR                           
+ 50 A<4>                            122 TDO                           
+ 51 A<6>                            123 GND                           
+ 52 A<3>                            124 KPR                           
+ 53 KPR                             125 KPR                           
+ 54 A<2>                            126 KPR                           
+ 55 VCC                             127 VCC                           
+ 56 KPR                             128 KPR                           
+ 57 A<1>                            129 KPR                           
+ 58 A<9>                            130 KPR                           
+ 59 A<10>                           131 KPR                           
+ 60 A<11>                           132 KPR                           
+ 61 A<12>                           133 KPR                           
+ 62 GND                             134 KPR                           
+ 63 TDI                             135 KPR                           
+ 64 A<13>                           136 KPR                           
+ 65 TMS                             137 KPR                           
+ 66 KPR                             138 KPR                           
+ 67 TCK                             139 KPR                           
+ 68 ROM_B<0>                        140 KPR                           
+ 69 ROM_B<1>                        141 VCC                           
+ 70 KPR                             142 KPR                           
+ 71 KPR                             143 RESET                         
+ 72 GND                             144 GND                           
+
+
+Legend :  NC  = Not Connected, unbonded pin
+         PGND = Unused I/O configured as additional Ground pin
+         TIE  = Unused I/O floating -- must tie to VCC, GND or other signal
+         KPR  = Unused I/O with weak keeper (leave unconnected)
+         VCC  = Dedicated Power Pin
+         GND  = Dedicated Ground Pin
+         TDI  = Test Data In, JTAG pin
+         TDO  = Test Data Out, JTAG pin
+         TCK  = Test Clock, JTAG pin
+         TMS  = Test Mode Select, JTAG pin
+  PROHIBITED  = User reserved pin
+****************************  Compiler Options  ****************************
+
+Following is a list of all global compiler options used by the fitter run.
+
+Device(s) Specified                         : xc95144xl-10-TQ144
+Optimization Method                         : SPEED
+Multi-Level Logic Optimization              : ON
+Ignore Timing Specifications                : OFF
+Default Register Power Up Value             : LOW
+Keep User Location Constraints              : ON
+What-You-See-Is-What-You-Get                : OFF
+Exhaustive Fitting                          : OFF
+Keep Unused Inputs                          : OFF
+Slew Rate                                   : FAST
+Power Mode                                  : STD
+Ground on Unused IOs                        : OFF
+Set I/O Pin Termination                     : KEEPER
+Global Clock Optimization                   : ON
+Global Set/Reset Optimization               : ON
+Global Ouput Enable Optimization            : ON
+Input Limit                                 : 54
+Pterm Limit                                 : 25
+</pre>
+<form><span class="pgRef"><table width="90%" align="center"><tr>
+<td align="left"><input type="button" onclick="javascript:parent.leftnav.showTop()" onmouseover="window.status='goto top of page'; return true;" onmouseout="window.status=''" value="back to top"></td>
+<td align="right"><input type="button" onclick="window.print()" onmouseover="window.status='print page'; return true;" onmouseout="window.status=''" value="print page"></td>
+</tr></table></span></form>
+</body></html>
diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/ascii.tmp b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/ascii.tmp
new file mode 100644
index 0000000..9b23fb5
--- /dev/null
+++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/ascii.tmp
@@ -0,0 +1,4 @@
+<form><span class="pgRef"><table width="90%" align="center"><tr>
+<td align="left"><input type="button" onclick="javascript:parent.leftnav.showTop()" onmouseover="window.status='goto top of page'; return true;" onmouseout="window.status=''" value="back to top"></td>
+<td align="right"><input type="button" onclick="window.print()" onmouseover="window.status='print page'; return true;" onmouseout="window.status=''" value="print page"></td>
+</tr></table></span></form>
diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/asciidoc.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/asciidoc.htm
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--- /dev/null
+++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/asciidoc.htm
@@ -0,0 +1,71 @@
+<!doctype HTML public "-//W3C//DTD HTML 4.0 Frameset//EN">
+
+<html>
+
+<!--(==============================================================)-->
+<!--(Document created with RoboEditor. )============================-->
+<!--(==============================================================)-->
+
+<head>
+
+<title>Text Report</title>
+
+<!--(Meta)==========================================================-->
+
+<meta name=generator content="RoboHELP by eHelp Corporation - www.ehelp.com">
+<meta name=generator-major-version content=0.1>
+<meta name=generator-minor-version content=1>
+<meta name=filetype content=kadov>
+<meta name=filetype-version content=1>
+<meta name=page-count content=1>
+<meta name=layout-height content=375>
+<meta name=layout-width content=798>
+<meta name=date content="05 1, 2002 4:24:59 PM">
+
+
+
+<style>
+<!--
+p.whs1 {font-family: arial, sans-serif; font-size: 10pt;}
+
+--></style><script language="javascript" title="WebHelpInlineScript">
+<!--
+function reDo() {
+  if (innerWidth != origWidth || innerHeight != origHeight)
+     location.reload();
+}
+if ((parseInt(navigator.appVersion) == 4) && (navigator.appName == "Netscape")) {
+	origWidth = innerWidth;
+	origHeight = innerHeight;
+	onresize = reDo;
+}
+//-->
+</script><style>
+<!--
+  div.WebHelpPopupMenu {position:absolute; left:0px; top:0px; z-index:4; visibility:hidden;}
+  p.WebHelpNavBar {text-align:right;}
+-->
+</style>
+</head>
+
+<!--(Body)==========================================================-->
+
+
+<body>
+
+
+<h1>Text Report</h1>
+
+<p class="whs1">Selecting Text 
+ Report from the left-hand frame will give you a printable text version 
+ of the fitter report. <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->It 
+ contains sections similar to those of the XML report (a summary section, 
+ errors and warnings, mapped logic, function blocks, function block details, 
+ a text-graphical display of the pinout, and a summary of compiler options), 
+ but it is not easily navigable. <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->It 
+ is best to use the text report only when you need to print out a hard 
+ copy of the fitter results.</p>
+
+</body>
+
+</html>
diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/backtop.jpg b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/backtop.jpg
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+++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/blank.htm
@@ -0,0 +1 @@
+<html></html>
diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/briefview.jpg b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/briefview.jpg
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diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/check.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/check.htm
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--- /dev/null
+++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/check.htm
@@ -0,0 +1,9 @@
+<html>
+  <head>
+   <script src="XilinxD.js"> </script>
+   <script src="plugin.js"> </script>
+
+  </head> 
+  <body onload="javascript:checkJre()" bgcolor="#ffffff" topmargin="0" leftmargin="0" marginheight="0" marginwidth="0" > 
+  </body> 
+</html> 
diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/checkNS4.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/checkNS4.htm
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--- /dev/null
+++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/checkNS4.htm
@@ -0,0 +1,9 @@
+<html>
+  <head>
+   <script src="xilinxD.js"> </script>
+   <script src="ns4plugin.js"> </script>
+
+  </head> 
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+  </body> 
+</html> 
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+<html><head><link type='text/css' href='style.css' rel='stylesheet'></head><body class='pgBgnd'>
+<h3 align='center'>Equations</h3>
+<table width='90%' align='center' border='1' cellpadding='0' cellspacing='0'>
+<tr><td>
+</td></tr><tr><td>
+********** Mapped Logic **********
+</td></tr><tr><td>
+FDCPE_AUTOCONFIG_IN_PROGRESS: FDCPE port map (AUTOCONFIG_IN_PROGRESS,AUTOCONFIG_IN_PROGRESS_D,ide/ide_CLKF,'0','0');
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;AUTOCONFIG_IN_PROGRESS_D <= (NOT AS AND autoconfig);
+</td></tr><tr><td>
+FDCPE_AUTO_CONFIG_DONE0: FDCPE port map (AUTO_CONFIG_DONE(0),AUTO_CONFIG_DONE_CYCLE(0),AS,NOT RESET,'0');
+</td></tr><tr><td>
+FDCPE_AUTO_CONFIG_DONE1: FDCPE port map (AUTO_CONFIG_DONE(1),AUTO_CONFIG_DONE_CYCLE(1),AS,NOT RESET,'0');
+</td></tr><tr><td>
+FDCPE_AUTO_CONFIG_DONE2: FDCPE port map (AUTO_CONFIG_DONE(2),AUTO_CONFIG_DONE_CYCLE(2),AS,NOT RESET,'0');
+</td></tr><tr><td>
+FDCPE_AUTO_CONFIG_DONE_CYCLE0: FDCPE port map (AUTO_CONFIG_DONE_CYCLE(0),AUTO_CONFIG_DONE_CYCLE_D(0),ide/ide_CLKF,'0','0');
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;AUTO_CONFIG_DONE_CYCLE_D(0) <= ((RESET AND AUTO_CONFIG_DONE_CYCLE(0))
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (RESET AND NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND 
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	A(6) AND A(3) AND NOT AUTO_CONFIG_DONE(0) AND autoconfig));
+</td></tr><tr><td>
+FDCPE_AUTO_CONFIG_DONE_CYCLE1: FDCPE port map (AUTO_CONFIG_DONE_CYCLE(1),AUTO_CONFIG_DONE_CYCLE_D(1),ide/ide_CLKF,'0','0');
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;AUTO_CONFIG_DONE_CYCLE_D(1) <= ((RESET AND AUTO_CONFIG_DONE_CYCLE(1))
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (RESET AND NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND 
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	A(6) AND A(3) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND 
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	autoconfig));
+</td></tr><tr><td>
+FDCPE_AUTO_CONFIG_DONE_CYCLE2: FDCPE port map (AUTO_CONFIG_DONE_CYCLE(2),AUTO_CONFIG_DONE_CYCLE_D(2),ide/ide_CLKF,'0','0');
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;AUTO_CONFIG_DONE_CYCLE_D(2) <= ((RESET AND AUTO_CONFIG_DONE_CYCLE(2))
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (RESET AND NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND 
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	A(6) AND A(3) AND AUTO_CONFIG_DONE(0) AND AUTO_CONFIG_DONE(1) AND 
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT AUTO_CONFIG_DONE(2) AND autoconfig));
+</td></tr><tr><td>
+</td></tr><tr><td>
+D_I(0) <= '1';
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;D(0) <= D_I(0) when D_OE(0) = '1' else 'Z';
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;D_OE(0) <= (RW AND AUTOCONFIG_IN_PROGRESS);
+</td></tr><tr><td>
+</td></tr><tr><td>
+D_I(1) <= '1';
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;D(1) <= D_I(1) when D_OE(1) = '1' else 'Z';
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;D_OE(1) <= (RW AND AUTOCONFIG_IN_PROGRESS);
+</td></tr><tr><td>
+</td></tr><tr><td>
+D_I(2) <= '1';
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;D(2) <= D_I(2) when D_OE(2) = '1' else 'Z';
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;D_OE(2) <= (RW AND AUTOCONFIG_IN_PROGRESS);
+</td></tr><tr><td>
+</td></tr><tr><td>
+D_I(3) <= '1';
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;D(3) <= D_I(3) when D_OE(3) = '1' else 'Z';
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;D_OE(3) <= (RW AND AUTOCONFIG_IN_PROGRESS);
+</td></tr><tr><td>
+</td></tr><tr><td>
+D_I(4) <= '1';
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;D(4) <= D_I(4) when D_OE(4) = '1' else 'Z';
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;D_OE(4) <= (RW AND AUTOCONFIG_IN_PROGRESS);
+</td></tr><tr><td>
+</td></tr><tr><td>
+D_I(5) <= '1';
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;D(5) <= D_I(5) when D_OE(5) = '1' else 'Z';
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;D_OE(5) <= (RW AND AUTOCONFIG_IN_PROGRESS);
+</td></tr><tr><td>
+</td></tr><tr><td>
+D_I(6) <= '1';
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;D(6) <= D_I(6) when D_OE(6) = '1' else 'Z';
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;D_OE(6) <= (RW AND AUTOCONFIG_IN_PROGRESS);
+</td></tr><tr><td>
+</td></tr><tr><td>
+D_I(7) <= '1';
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;D(7) <= D_I(7) when D_OE(7) = '1' else 'Z';
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;D_OE(7) <= (RW AND AUTOCONFIG_IN_PROGRESS);
+</td></tr><tr><td>
+</td></tr><tr><td>
+D_I(8) <= '1';
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;D(8) <= D_I(8) when D_OE(8) = '1' else 'Z';
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;D_OE(8) <= (RW AND AUTOCONFIG_IN_PROGRESS);
+</td></tr><tr><td>
+</td></tr><tr><td>
+D_I(9) <= '1';
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;D(9) <= D_I(9) when D_OE(9) = '1' else 'Z';
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;D_OE(9) <= (RW AND AUTOCONFIG_IN_PROGRESS);
+</td></tr><tr><td>
+</td></tr><tr><td>
+D_I(10) <= '1';
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;D(10) <= D_I(10) when D_OE(10) = '1' else 'Z';
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;D_OE(10) <= (RW AND AUTOCONFIG_IN_PROGRESS);
+</td></tr><tr><td>
+</td></tr><tr><td>
+D_I(11) <= '1';
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;D(11) <= D_I(11) when D_OE(11) = '1' else 'Z';
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;D_OE(11) <= (RW AND AUTOCONFIG_IN_PROGRESS);
+</td></tr><tr><td>
+FDCPE_D12_BUFR: FDCPE port map (D(12)_BUFR,D_D(12)_BUFR,ide/ide_CLKF,'0','0');
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;D_D(12)_BUFR <= ((RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND A(6) AND NOT A(3) AND 
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT A(2) AND NOT AUTO_CONFIG_DONE(0) AND autoconfig)
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND A(6) AND NOT A(3) AND 
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT A(2) AND NOT AUTO_CONFIG_DONE(1) AND autoconfig)
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND A(6) AND NOT A(3) AND 
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT A(2) AND NOT AUTO_CONFIG_DONE(2) AND autoconfig)
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(1) AND NOT A(6) AND NOT A(3) AND 
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	A(2) AND NOT AUTO_CONFIG_DONE(0) AND autoconfig)
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (RESET AND RW AND NOT AS AND A(5) AND NOT A(4) AND A(1) AND NOT A(6) AND 
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND 
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	autoconfig)
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (ROM_OE_S.EXP)
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (RESET AND NOT D(12) AND NOT RW)
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (RESET AND NOT D(12) AND AS)
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (RESET AND NOT D(12) AND NOT autoconfig)
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (RESET AND NOT D(12) AND AUTO_CONFIG_DONE(0) AND 
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	AUTO_CONFIG_DONE(1) AND AUTO_CONFIG_DONE(2))
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND NOT A(3) AND 
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT A(2) AND NOT AUTO_CONFIG_DONE(0) AND autoconfig)
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (RESET AND RW AND NOT AS AND NOT A(4) AND A(1) AND NOT A(6) AND NOT A(3) AND 
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	A(2) AND NOT AUTO_CONFIG_DONE(0) AND autoconfig)
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (RESET AND RW AND NOT AS AND NOT A(5) AND A(4) AND NOT A(6) AND A(3) AND 
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND 
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	autoconfig)
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND NOT A(3) AND 
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT A(2) AND AUTO_CONFIG_DONE(1) AND NOT AUTO_CONFIG_DONE(2) AND 
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	autoconfig)
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND NOT A(3) AND 
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT A(2) AND NOT AUTO_CONFIG_DONE(1) AND AUTOBOOT_OFF AND autoconfig));
+</td></tr><tr><td>
+</td></tr><tr><td>
+D_I(12) <= D(12)_BUFR;
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;D(12) <= D_I(12) when D_OE(12) = '1' else 'Z';
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;D_OE(12) <= (RW AND AUTOCONFIG_IN_PROGRESS);
+</td></tr><tr><td>
+FDCPE_D13_BUFR: FDCPE port map (D(13)_BUFR,D_D(13)_BUFR,ide/ide_CLKF,'0','0');
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;D_D(13)_BUFR <= ((IDE_BASEADR(6).EXP)
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (RESET AND NOT D(13) AND NOT RW)
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (RESET AND NOT D(13) AND AUTO_CONFIG_DONE(0) AND 
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	AUTO_CONFIG_DONE(1) AND AUTO_CONFIG_DONE(2))
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(6) AND NOT A(3) AND 
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT AUTO_CONFIG_DONE(0) AND autoconfig)
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(3) AND NOT A(2) AND 
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT AUTO_CONFIG_DONE(0) AND autoconfig)
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(3) AND NOT A(2) AND 
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT AUTO_CONFIG_DONE(1) AND autoconfig)
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(3) AND NOT A(2) AND 
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT AUTO_CONFIG_DONE(2) AND autoconfig)
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND A(1) AND NOT A(6) AND 
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT A(3) AND NOT AUTO_CONFIG_DONE(1) AND autoconfig)
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (RESET AND RW AND NOT AS AND NOT A(5) AND A(1) AND NOT A(6) AND NOT A(3) AND 
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT A(2) AND NOT AUTO_CONFIG_DONE(0) AND autoconfig)
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (RESET AND RW AND NOT AS AND NOT A(5) AND A(4) AND NOT A(1) AND NOT A(6) AND 
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND 
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	autoconfig)
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (RESET AND NOT D(13) AND AS)
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (RESET AND NOT D(13) AND NOT autoconfig)
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (RESET AND RW AND NOT AS AND NOT A(5) AND A(4) AND NOT A(6) AND A(3) AND 
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND 
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	autoconfig)
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (RESET AND RW AND NOT AS AND NOT A(5) AND A(1) AND NOT A(6) AND NOT A(3) AND 
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT A(2) AND AUTO_CONFIG_DONE(1) AND NOT AUTO_CONFIG_DONE(2) AND 
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	autoconfig));
+</td></tr><tr><td>
+</td></tr><tr><td>
+D_I(13) <= D(13)_BUFR;
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;D(13) <= D_I(13) when D_OE(13) = '1' else 'Z';
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;D_OE(13) <= (RW AND AUTOCONFIG_IN_PROGRESS);
+</td></tr><tr><td>
+</td></tr><tr><td>
+D_I(14) <= D(14)_BUFR;
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;D(14) <= D_I(14) when D_OE(14) = '1' else 'Z';
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;D_OE(14) <= (RW AND AUTOCONFIG_IN_PROGRESS);
+</td></tr><tr><td>
+FDCPE_D14_BUFR: FDCPE port map (D(14)_BUFR,D_D(14)_BUFR,ide/ide_CLKF,'0','0');
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;D_D(14)_BUFR <= ((EXP16_.EXP)
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND A(1) AND NOT A(3) AND 
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT A(2) AND NOT AUTO_CONFIG_DONE(0) AND autoconfig)
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND A(6) AND NOT A(3) AND 
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT A(2) AND NOT AUTO_CONFIG_DONE(0) AND autoconfig)
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND A(6) AND NOT A(3) AND 
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT A(2) AND NOT AUTO_CONFIG_DONE(1) AND autoconfig)
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND A(6) AND NOT A(3) AND 
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT A(2) AND NOT AUTO_CONFIG_DONE(2) AND autoconfig)
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (RESET AND RW AND NOT AS AND NOT A(4) AND A(1) AND NOT A(6) AND NOT A(3) AND 
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND 
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	autoconfig)
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (RESET AND NOT D(14) AND NOT RW)
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (RESET AND NOT D(14) AND AS)
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (RESET AND NOT D(14) AND NOT autoconfig)
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (RESET AND NOT D(14) AND AUTO_CONFIG_DONE(0) AND 
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	AUTO_CONFIG_DONE(1) AND AUTO_CONFIG_DONE(2))
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (RESET AND RW AND NOT AS AND NOT A(5) AND A(1) AND NOT A(6) AND NOT A(3) AND 
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(2) AND 
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	autoconfig)
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND A(1) AND NOT A(3) AND 
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT A(2) AND NOT AUTO_CONFIG_DONE(1) AND autoconfig)
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND A(1) AND NOT A(3) AND 
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT A(2) AND NOT AUTO_CONFIG_DONE(2) AND autoconfig)
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (RESET AND RW AND NOT AS AND NOT A(5) AND A(1) AND NOT A(6) AND NOT A(3) AND 
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND 
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	autoconfig)
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(6) AND NOT A(3) AND 
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	A(2) AND AUTO_CONFIG_DONE(0) AND AUTO_CONFIG_DONE(1) AND 
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT AUTO_CONFIG_DONE(2) AND autoconfig));
+</td></tr><tr><td>
+</td></tr><tr><td>
+D_I(15) <= D(15)_BUFR;
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;D(15) <= D_I(15) when D_OE(15) = '1' else 'Z';
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;D_OE(15) <= (RW AND AUTOCONFIG_IN_PROGRESS);
+</td></tr><tr><td>
+FDCPE_D15_BUFR: FDCPE port map (D(15)_BUFR,D_D(15)_BUFR,ide/ide_CLKF,'0','0');
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;D_D(15)_BUFR <= ((RESET AND NOT D(15) AND AUTO_CONFIG_DONE(0) AND 
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	AUTO_CONFIG_DONE(1) AND AUTO_CONFIG_DONE(2))
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (RESET AND RW AND NOT AS AND NOT A(5) AND A(1) AND NOT A(6) AND NOT A(3) AND 
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT AUTO_CONFIG_DONE(0) AND autoconfig)
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND A(6) AND NOT A(3) AND 
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT A(2) AND NOT AUTO_CONFIG_DONE(0) AND autoconfig)
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND A(6) AND NOT A(3) AND 
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT A(2) AND NOT AUTO_CONFIG_DONE(1) AND autoconfig)
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (RESET AND RW AND NOT AS AND NOT A(5) AND NOT A(4) AND A(6) AND NOT A(3) AND 
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT A(2) AND NOT AUTO_CONFIG_DONE(2) AND autoconfig)
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (RESET AND RW AND NOT AS AND NOT A(5) AND A(1) AND NOT A(6) AND NOT A(3) AND 
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	AUTO_CONFIG_DONE(1) AND NOT AUTO_CONFIG_DONE(2) AND autoconfig)
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (RESET AND RW AND NOT AS AND NOT A(5) AND A(4) AND A(1) AND NOT A(6) AND 
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND 
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	autoconfig)
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (RESET AND RW AND NOT AS AND A(5) AND NOT A(4) AND NOT A(1) AND NOT A(6) AND 
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT A(3) AND A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND 
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	autoconfig)
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (RESET AND RW AND NOT AS AND NOT A(5) AND A(4) AND NOT A(1) AND NOT A(6) AND 
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND 
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	autoconfig)
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (RESET AND NOT D(15) AND NOT RW)
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (RESET AND NOT D(15) AND AS)
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (RESET AND NOT D(15) AND NOT autoconfig)
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (RESET AND RW AND NOT AS AND NOT A(5) AND A(1) AND NOT A(6) AND NOT A(3) AND 
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT A(2) AND NOT AUTO_CONFIG_DONE(1) AND autoconfig));
+</td></tr><tr><td>
+</td></tr><tr><td>
+DTACK_I <= '0';
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;DTACK <= DTACK_I when DTACK_OE = '1' else 'Z';
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;DTACK_OE <= '0';
+</td></tr><tr><td>
+</td></tr><tr><td>
+</td></tr><tr><td>
+</td></tr><tr><td>
+</td></tr><tr><td>
+</td></tr><tr><td>
+</td></tr><tr><td>
+</td></tr><tr><td>
+</td></tr><tr><td>
+</td></tr><tr><td>
+</td></tr><tr><td>
+</td></tr><tr><td>
+</td></tr><tr><td>
+</td></tr><tr><td>
+</td></tr><tr><td>
+</td></tr><tr><td>
+</td></tr><tr><td>
+</td></tr><tr><td>
+</td></tr><tr><td>
+</td></tr><tr><td>
+</td></tr><tr><td>
+</td></tr><tr><td>
+IDE_A(0) <= A(9);
+</td></tr><tr><td>
+</td></tr><tr><td>
+IDE_A(1) <= A(10);
+</td></tr><tr><td>
+</td></tr><tr><td>
+IDE_A(2) <= A(11);
+</td></tr><tr><td>
+FTCPE_IDE_BASEADR0: FTCPE port map (IDE_BASEADR(0),IDE_BASEADR_T(0),ide/ide_CLKF,'0','0');
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;IDE_BASEADR_T(0) <= ((NOT RESET AND NOT IDE_BASEADR(0))
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND A(6) AND 
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND 
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT IDE_BASEADR(0) AND autoconfig AND D(8).PIN)
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (RESET AND NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND 
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	A(6) AND A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND 
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT AUTO_CONFIG_DONE(1) AND IDE_BASEADR(0) AND autoconfig AND NOT D(8).PIN));
+</td></tr><tr><td>
+FTCPE_IDE_BASEADR1: FTCPE port map (IDE_BASEADR(1),IDE_BASEADR_T(1),ide/ide_CLKF,'0','0');
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;IDE_BASEADR_T(1) <= ((NOT RESET AND NOT IDE_BASEADR(1))
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND A(6) AND 
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND 
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT IDE_BASEADR(1) AND autoconfig AND D(9).PIN)
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (RESET AND NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND 
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	A(6) AND A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND 
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT AUTO_CONFIG_DONE(1) AND IDE_BASEADR(1) AND autoconfig AND NOT D(9).PIN));
+</td></tr><tr><td>
+FTCPE_IDE_BASEADR2: FTCPE port map (IDE_BASEADR(2),IDE_BASEADR_T(2),ide/ide_CLKF,'0','0');
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;IDE_BASEADR_T(2) <= ((NOT RESET AND NOT IDE_BASEADR(2))
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND A(6) AND 
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND 
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT IDE_BASEADR(2) AND autoconfig AND D(10).PIN)
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (RESET AND NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND 
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	A(6) AND A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND 
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT AUTO_CONFIG_DONE(1) AND IDE_BASEADR(2) AND autoconfig AND NOT D(10).PIN));
+</td></tr><tr><td>
+FTCPE_IDE_BASEADR3: FTCPE port map (IDE_BASEADR(3),IDE_BASEADR_T(3),ide/ide_CLKF,'0','0');
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;IDE_BASEADR_T(3) <= ((NOT RESET AND NOT IDE_BASEADR(3))
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND A(6) AND 
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND 
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT IDE_BASEADR(3) AND autoconfig AND D(11).PIN)
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (RESET AND NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND 
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	A(6) AND A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND 
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT AUTO_CONFIG_DONE(1) AND IDE_BASEADR(3) AND autoconfig AND NOT D(11).PIN));
+</td></tr><tr><td>
+FTCPE_IDE_BASEADR4: FTCPE port map (IDE_BASEADR(4),IDE_BASEADR_T(4),ide/ide_CLKF,'0','0');
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;IDE_BASEADR_T(4) <= ((NOT RESET AND NOT IDE_BASEADR(4))
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND A(6) AND 
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND 
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT IDE_BASEADR(4) AND autoconfig AND D(12).PIN)
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (RESET AND NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND 
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	A(6) AND A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND 
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT AUTO_CONFIG_DONE(1) AND IDE_BASEADR(4) AND autoconfig AND NOT D(12).PIN));
+</td></tr><tr><td>
+FTCPE_IDE_BASEADR5: FTCPE port map (IDE_BASEADR(5),IDE_BASEADR_T(5),ide/ide_CLKF,'0','0');
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;IDE_BASEADR_T(5) <= ((NOT RESET AND NOT IDE_BASEADR(5))
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND A(6) AND 
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND 
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT IDE_BASEADR(5) AND autoconfig AND D(13).PIN)
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (RESET AND NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND 
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	A(6) AND A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND 
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT AUTO_CONFIG_DONE(1) AND IDE_BASEADR(5) AND autoconfig AND NOT D(13).PIN));
+</td></tr><tr><td>
+FTCPE_IDE_BASEADR6: FTCPE port map (IDE_BASEADR(6),IDE_BASEADR_T(6),ide/ide_CLKF,'0','0');
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;IDE_BASEADR_T(6) <= ((NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND A(6) AND 
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND 
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT IDE_BASEADR(6) AND autoconfig AND D(14).PIN)
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (RESET AND NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND 
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	A(6) AND A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND 
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT AUTO_CONFIG_DONE(1) AND IDE_BASEADR(6) AND autoconfig AND NOT D(14).PIN)
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT RESET AND NOT IDE_BASEADR(6)));
+</td></tr><tr><td>
+FTCPE_IDE_BASEADR7: FTCPE port map (IDE_BASEADR(7),IDE_BASEADR_T(7),ide/ide_CLKF,'0','0');
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;IDE_BASEADR_T(7) <= ((RESET AND NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND 
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	A(6) AND A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND 
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT AUTO_CONFIG_DONE(1) AND IDE_BASEADR(7) AND autoconfig AND NOT D(15).PIN)
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT RESET AND NOT IDE_BASEADR(7))
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND A(6) AND 
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND NOT AUTO_CONFIG_DONE(1) AND 
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT IDE_BASEADR(7) AND autoconfig AND D(15).PIN));
+</td></tr><tr><td>
+</td></tr><tr><td>
+IDE_CS(0) <= NOT A(12);
+</td></tr><tr><td>
+</td></tr><tr><td>
+IDE_CS(1) <= NOT A(13);
+</td></tr><tr><td>
+FDCPE_IDE_ENABLE: FDCPE port map (IDE_ENABLE,IDE_ENABLE_D,ide/ide_CLKF,'0','0');
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;IDE_ENABLE_D <= ((RESET AND NOT IDE_ENABLE)
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (RESET AND NOT RW AND NOT AS AND ide));
+</td></tr><tr><td>
+FDCPE_IDE_R: FDCPE port map (IDE_R,IDE_R_D,ide/ide_CLKF,'0','0');
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;IDE_R_D <= (RESET AND RW AND NOT AS AND NOT IDE_ENABLE AND ide);
+</td></tr><tr><td>
+FDCPE_IDE_W: FDCPE port map (IDE_W,IDE_W_D,ide/ide_CLKF,'0','0');
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;IDE_W_D <= (RESET AND NOT RW AND NOT AS AND ide);
+</td></tr><tr><td>
+</td></tr><tr><td>
+ROM_B(0) <= '0';
+</td></tr><tr><td>
+</td></tr><tr><td>
+ROM_B(1) <= '0';
+</td></tr><tr><td>
+FDCPE_ROM_OE: FDCPE port map (ROM_OE,ROM_OE_D,ide/ide_CLKF,'0','0');
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;ROM_OE_D <= (RESET AND RW AND NOT AS AND IDE_ENABLE AND ide);
+</td></tr><tr><td>
+FDCPE_SHUT_UP1: FDCPE port map (SHUT_UP(1),SHUT_UP_D(1),ide/ide_CLKF,'0','0');
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;SHUT_UP_D(1) <= ((RESET AND NOT SHUT_UP(1))
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (RESET AND NOT UDS AND NOT RW AND NOT AS AND NOT A(5) AND NOT A(4) AND NOT A(1) AND 
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	A(6) AND A(3) AND NOT A(2) AND AUTO_CONFIG_DONE(0) AND 
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT AUTO_CONFIG_DONE(1) AND autoconfig));
+</td></tr><tr><td>
+FDCPE_autoconfig: FDCPE port map (autoconfig,autoconfig_D,ide/ide_CLKF,'0','0');
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;autoconfig_D <= ((A(23) AND A(22) AND A(21) AND A(19) AND 
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT AUTO_CONFIG_DONE(0) AND BERR AND NOT A(17) AND NOT A(16) AND NOT A(20) AND NOT A(18))
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (A(23) AND A(22) AND A(21) AND A(19) AND 
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT AUTO_CONFIG_DONE(1) AND BERR AND NOT A(17) AND NOT A(16) AND NOT A(20) AND NOT A(18))
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (A(23) AND A(22) AND A(21) AND A(19) AND 
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT AUTO_CONFIG_DONE(2) AND BERR AND NOT A(17) AND NOT A(16) AND NOT A(20) AND NOT A(18)));
+</td></tr><tr><td>
+FDCPE_ide: FDCPE port map (ide,ide_D,ide/ide_CLKF,'0','0');
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;ide_D <= ((SHUT_UP(1))
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT BERR)
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (EXP20_.EXP)
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (A(23) AND NOT IDE_BASEADR(7))
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT A(23) AND IDE_BASEADR(7))
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (A(22) AND NOT IDE_BASEADR(6))
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT A(22) AND IDE_BASEADR(6))
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (IDE_BASEADR(1) AND NOT A(17))
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (autoconfig.EXP)
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (IDE_BASEADR(0) AND NOT A(16))
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT IDE_BASEADR(0) AND A(16))
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT IDE_BASEADR(1) AND A(17))
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (IDE_BASEADR(2) AND NOT A(18))
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT IDE_BASEADR(2) AND A(18))
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (A(19) AND NOT IDE_BASEADR(3))
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT A(19) AND IDE_BASEADR(3)));
+</td></tr><tr><td>
+</td></tr><tr><td>
+ide/ide_CLKF <= NOT (C3
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	 XOR 
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;ide/ide_CLKF <= NOT (C1);
+</td></tr><tr><td>
+Register Legend:
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; FDCPE (Q,D,C,CLR,PRE,CE); 
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; FTCPE (Q,D,C,CLR,PRE,CE); 
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; LDCP  (Q,D,G,CLR,PRE); 
+</td></tr><tr><td>
+</td></tr>
+</table>
+<form><span class="pgRef"><table width="90%" align="center"><tr>
+<td align="left"><input type="button" onclick="javascript:parent.leftnav.showTop()" onmouseover="window.status='goto top of page'; return true;" onmouseout="window.status=''" value="back to top"></td>
+<td align="right"><input type="button" onclick="window.print()" onmouseover="window.status='print page'; return true;" onmouseout="window.status=''" value="print page"></td>
+</tr></table></span></form>
+</body></html>
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diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/eqns.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/eqns.htm
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--- /dev/null
+++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/eqns.htm
@@ -0,0 +1,965 @@
+<html><head>
+<meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+<script src="paths.js"></script><script src="eqns.js"></script><script>
+      var design = "LAN_IDE_CP";
+      var device = "XC95144XL";
+      signals = new Array("AUTOCONFIG_IN_PROGRESS","AUTO_CONFIG_DONE0_SPECSIG","AUTO_CONFIG_DONE1_SPECSIG","AUTO_CONFIG_DONE2_SPECSIG","AUTO_CONFIG_DONE_CYCLE0_SPECSIG","AUTO_CONFIG_DONE_CYCLE1_SPECSIG","AUTO_CONFIG_DONE_CYCLE2_SPECSIG","D0_SPECSIG","D10_SPECSIG","D11_SPECSIG","D12_BUFR_SPECSIG","D12_SPECSIG","D13_BUFR_SPECSIG","D13_SPECSIG","D14_BUFR_SPECSIG","D14_SPECSIG","D15_BUFR_SPECSIG","D15_SPECSIG","D1_SPECSIG","D2_SPECSIG","D3_SPECSIG","D4_SPECSIG","D5_SPECSIG","D6_SPECSIG","D7_SPECSIG","D8_SPECSIG","D9_SPECSIG","DTACK","IDE_A0_SPECSIG","IDE_A1_SPECSIG","IDE_A2_SPECSIG","IDE_BASEADR0_SPECSIG","IDE_BASEADR1_SPECSIG","IDE_BASEADR2_SPECSIG","IDE_BASEADR3_SPECSIG","IDE_BASEADR4_SPECSIG","IDE_BASEADR5_SPECSIG","IDE_BASEADR6_SPECSIG","IDE_BASEADR7_SPECSIG","IDE_CS0_SPECSIG","IDE_CS1_SPECSIG","IDE_ENABLE","IDE_R","IDE_W","ROM_B0_SPECSIG","ROM_B1_SPECSIG","ROM_OE","SHUT_UP1_SPECSIG","autoconfig","ide","ideide_CLKF_SPECSIG");
+      sigNegs = new Array("OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","ON","OFF","ON","OFF","ON","OFF","ON","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","ON","ON","ON","OFF","OFF","ON","ON","OFF","ON","ON");
+      sigTypes = new Array("D","D","D","D","D","D","D","","","","D","","D","","D","","D","","","","","","","","","","","","","","","T","T","T","T","T","T","T","T","","","D","D","D","","","D","D","D","D","");
+
+      
+        specSig["A1_SPECSIG"]=new Array("A<1>");
+      
+        specSig["A2_SPECSIG"]=new Array("A<2>");
+      
+        specSig["A5_SPECSIG"]=new Array("A<5>");
+      
+        specSig["A6_SPECSIG"]=new Array("A<6>");
+      
+        specSig["A3_SPECSIG"]=new Array("A<3>");
+      
+        specSig["A4_SPECSIG"]=new Array("A<4>");
+      
+        specSig["A23_SPECSIG"]=new Array("A<23>");
+      
+        specSig["A22_SPECSIG"]=new Array("A<22>");
+      
+        specSig["A21_SPECSIG"]=new Array("A<21>");
+      
+        specSig["A19_SPECSIG"]=new Array("A<19>");
+      
+        specSig["D8PIN_SPECSIG"]=new Array("D<8>.PIN");
+      
+        specSig["D12PIN_SPECSIG"]=new Array("D<12>.PIN");
+      
+        specSig["D13PIN_SPECSIG"]=new Array("D<13>.PIN");
+      
+        specSig["D9PIN_SPECSIG"]=new Array("D<9>.PIN");
+      
+        specSig["D10PIN_SPECSIG"]=new Array("D<10>.PIN");
+      
+        specSig["D11PIN_SPECSIG"]=new Array("D<11>.PIN");
+      
+        specSig["D14PIN_SPECSIG"]=new Array("D<14>.PIN");
+      
+        specSig["D15PIN_SPECSIG"]=new Array("D<15>.PIN");
+      
+        specSig["A16_SPECSIG"]=new Array("A<16>");
+      
+        specSig["A20_SPECSIG"]=new Array("A<20>");
+      
+        specSig["A17_SPECSIG"]=new Array("A<17>");
+      
+        specSig["A18_SPECSIG"]=new Array("A<18>");
+      
+        specSig["A9_SPECSIG"]=new Array("A<9>");
+      
+        specSig["A10_SPECSIG"]=new Array("A<10>");
+      
+        specSig["A11_SPECSIG"]=new Array("A<11>");
+      
+        specSig["A12_SPECSIG"]=new Array("A<12>");
+      
+        specSig["A13_SPECSIG"]=new Array("A<13>");
+      
+        specSig["IDE_CS1_SPECSIG"]=new Array("IDE_CS<1>");
+      
+        specSig["D7_SPECSIG"]=new Array("D<7>");
+      
+        specSig["D1_SPECSIG"]=new Array("D<1>");
+      
+        specSig["IDE_A2_SPECSIG"]=new Array("IDE_A<2>");
+      
+        specSig["IO_SPECSIG"]=new Array("I/O");
+      
+        specSig["D8_SPECSIG"]=new Array("D<8>");
+      
+        specSig["D5_SPECSIG"]=new Array("D<5>");
+      
+        specSig["D4_SPECSIG"]=new Array("D<4>");
+      
+        specSig["IDE_CS0_SPECSIG"]=new Array("IDE_CS<0>");
+      
+        specSig["b_SPECSIG"]=new Array("(b)");
+      
+        specSig["IDE_A0_SPECSIG"]=new Array("IDE_A<0>");
+      
+        specSig["IDE_A1_SPECSIG"]=new Array("IDE_A<1>");
+      
+        specSig["D14_BUFR_SPECSIG"]=new Array("D<14>_BUFR");
+      
+        specSig["GSRI_SPECSIG"]=new Array("GSR/I");
+      
+        specSig["D0_SPECSIG"]=new Array("D<0>");
+      
+        specSig["AUTO_CONFIG_DONE2_SPECSIG"]=new Array("AUTO_CONFIG_DONE<2>");
+      
+        specSig["AUTO_CONFIG_DONE0_SPECSIG"]=new Array("AUTO_CONFIG_DONE<0>");
+      
+        specSig["AUTO_CONFIG_DONE_CYCLE2_SPECSIG"]=new Array("AUTO_CONFIG_DONE_CYCLE<2>");
+      
+        specSig["AUTO_CONFIG_DONE_CYCLE0_SPECSIG"]=new Array("AUTO_CONFIG_DONE_CYCLE<0>");
+      
+        specSig["IDE_BASEADR7_SPECSIG"]=new Array("IDE_BASEADR<7>");
+      
+        specSig["IDE_BASEADR6_SPECSIG"]=new Array("IDE_BASEADR<6>");
+      
+        specSig["D13_BUFR_SPECSIG"]=new Array("D<13>_BUFR");
+      
+        specSig["D6_SPECSIG"]=new Array("D<6>");
+      
+        specSig["D3_SPECSIG"]=new Array("D<3>");
+      
+        specSig["D2_SPECSIG"]=new Array("D<2>");
+      
+        specSig["D10_SPECSIG"]=new Array("D<10>");
+      
+        specSig["D12_SPECSIG"]=new Array("D<12>");
+      
+        specSig["D14_SPECSIG"]=new Array("D<14>");
+      
+        specSig["D9_SPECSIG"]=new Array("D<9>");
+      
+        specSig["D15_SPECSIG"]=new Array("D<15>");
+      
+        specSig["D11_SPECSIG"]=new Array("D<11>");
+      
+        specSig["D13_SPECSIG"]=new Array("D<13>");
+      
+        specSig["ideide_CLKF_SPECSIG"]=new Array("ide/ide_CLKF");
+      
+        specSig["ROM_B0_SPECSIG"]=new Array("ROM_B<0>");
+      
+        specSig["SHUT_UP1_SPECSIG"]=new Array("SHUT_UP<1>");
+      
+        specSig["ROM_B1_SPECSIG"]=new Array("ROM_B<1>");
+      
+        specSig["D15_BUFR_SPECSIG"]=new Array("D<15>_BUFR");
+      
+        specSig["D12_BUFR_SPECSIG"]=new Array("D<12>_BUFR");
+      
+        specSig["AUTO_CONFIG_DONE1_SPECSIG"]=new Array("AUTO_CONFIG_DONE<1>");
+      
+        specSig["AUTO_CONFIG_DONE_CYCLE1_SPECSIG"]=new Array("AUTO_CONFIG_DONE_CYCLE<1>");
+      
+        specSig["IDE_BASEADR3_SPECSIG"]=new Array("IDE_BASEADR<3>");
+      
+        specSig["IDE_BASEADR2_SPECSIG"]=new Array("IDE_BASEADR<2>");
+      
+        specSig["IDE_BASEADR0_SPECSIG"]=new Array("IDE_BASEADR<0>");
+      
+        specSig["IDE_BASEADR1_SPECSIG"]=new Array("IDE_BASEADR<1>");
+      
+        specSig["IDE_BASEADR4_SPECSIG"]=new Array("IDE_BASEADR<4>");
+      
+        specSig["IDE_BASEADR5_SPECSIG"]=new Array("IDE_BASEADR<5>");
+      
+            pterms["FB1_1_1"]=new Array("RESET","RW","/AS","/A5_SPECSIG","/A4_SPECSIG","A6_SPECSIG","/A3_SPECSIG","/A2_SPECSIG","/AUTO_CONFIG_DONE0_SPECSIG","autoconfig");
+          
+            pterms["FB1_1_2"]=new Array("RESET","RW","/AS","/A5_SPECSIG","/A4_SPECSIG","A6_SPECSIG","/A3_SPECSIG","/A2_SPECSIG","/AUTO_CONFIG_DONE1_SPECSIG","autoconfig");
+          
+            pterms["FB1_1_3"]=new Array("RESET","RW","/AS","/A5_SPECSIG","/A4_SPECSIG","A6_SPECSIG","/A3_SPECSIG","/A2_SPECSIG","/AUTO_CONFIG_DONE2_SPECSIG","autoconfig");
+          
+            pterms["FB1_1_4"]=new Array("RESET","RW","/AS","/A5_SPECSIG","/A1_SPECSIG","/A6_SPECSIG","/A3_SPECSIG","A2_SPECSIG","/AUTO_CONFIG_DONE0_SPECSIG","autoconfig");
+          
+            pterms["FB1_1_5"]=new Array("RESET","RW","/AS","A5_SPECSIG","/A4_SPECSIG","A1_SPECSIG","/A6_SPECSIG","A2_SPECSIG","AUTO_CONFIG_DONE0_SPECSIG","/AUTO_CONFIG_DONE1_SPECSIG","autoconfig");
+          
+            pterms["FB1_2_1"]=new Array("RW","AUTOCONFIG_IN_PROGRESS");
+          
+            pterms["FB1_2_2"]=new Array("/A13_SPECSIG");
+          
+            pterms["FB1_3_1"]=new Array("RW","AUTOCONFIG_IN_PROGRESS");
+          
+            pterms["FB1_4_1"]=new Array("A11_SPECSIG");
+          
+            pterms["FB1_5_1"]=new Array("RW","AUTOCONFIG_IN_PROGRESS");
+          
+            pterms["FB1_6_1"]=new Array("RW","AUTOCONFIG_IN_PROGRESS");
+          
+            pterms["FB1_7_1"]=new Array("/AS","autoconfig");
+          
+            pterms["FB1_7_2"]=new Array("ideide_CLKF_SPECSIG");
+          
+            pterms["FB1_8_1"]=new Array("RW","AUTOCONFIG_IN_PROGRESS");
+          
+            pterms["FB1_9_1"]=new Array("/A12_SPECSIG");
+          
+            pterms["FB1_10_1"]=new Array("RESET","/IDE_ENABLE");
+          
+            pterms["FB1_10_2"]=new Array("RESET","/RW","/AS","ide");
+          
+            pterms["FB1_10_3"]=new Array("ideide_CLKF_SPECSIG");
+          
+            pterms["FB1_11_1"]=new Array("A9_SPECSIG");
+          
+            pterms["FB1_12_1"]=new Array("A10_SPECSIG");
+          
+            pterms["FB1_14_1"]=new Array("RESET","RW","/AS","/IDE_ENABLE","ide");
+          
+            pterms["FB1_14_2"]=new Array("ideide_CLKF_SPECSIG");
+          
+            pterms["FB1_15_1"]=new Array("RESET","/RW","/AS","ide");
+          
+            pterms["FB1_15_2"]=new Array("ideide_CLKF_SPECSIG");
+          
+            pterms["FB1_15_3"]=new Array("RESET","RW","/AS","IDE_ENABLE","ide");
+          
+            pterms["FB1_16_1"]=new Array("ideide_CLKF_SPECSIG");
+          
+            pterms["FB1_16_2"]=new Array("RESET","RW","/AS","A5_SPECSIG","/A4_SPECSIG","A1_SPECSIG","/A6_SPECSIG","/A3_SPECSIG","A2_SPECSIG","/AUTO_CONFIG_DONE2_SPECSIG","autoconfig");
+          
+            pterms["FB1_16_3"]=new Array("RESET","RW","/AS","A5_SPECSIG","/A4_SPECSIG","/A6_SPECSIG","/A3_SPECSIG","A2_SPECSIG","AUTO_CONFIG_DONE0_SPECSIG","/AUTO_CONFIG_DONE1_SPECSIG","autoconfig");
+          
+            pterms["FB1_16_4"]=new Array("RESET","RW","/AS","/A5_SPECSIG","A4_SPECSIG","A1_SPECSIG","/A6_SPECSIG","A3_SPECSIG","AUTO_CONFIG_DONE0_SPECSIG","/AUTO_CONFIG_DONE1_SPECSIG","autoconfig");
+          
+            pterms["FB1_16_5"]=new Array("RESET","RW","/AS","/A5_SPECSIG","/A1_SPECSIG","/A6_SPECSIG","/A3_SPECSIG","A2_SPECSIG","AUTO_CONFIG_DONE1_SPECSIG","/AUTO_CONFIG_DONE2_SPECSIG","autoconfig");
+          
+            pterms["FB1_17_1"]=new Array("RESET","/D12_SPECSIG","/RW");
+          
+            pterms["FB1_17_2"]=new Array("RESET","/D12_SPECSIG","AS");
+          
+            pterms["FB1_17_3"]=new Array("RESET","/D12_SPECSIG","/autoconfig");
+          
+            pterms["FB1_17_4"]=new Array("RESET","/D12_SPECSIG","AUTO_CONFIG_DONE0_SPECSIG","AUTO_CONFIG_DONE1_SPECSIG","AUTO_CONFIG_DONE2_SPECSIG");
+          
+            pterms["FB1_17_5"]=new Array("RESET","RW","/AS","/A5_SPECSIG","/A4_SPECSIG","/A1_SPECSIG","/A3_SPECSIG","/A2_SPECSIG","/AUTO_CONFIG_DONE0_SPECSIG","autoconfig");
+          
+            pterms["FB1_18_1"]=new Array("RESET","RW","/AS","/A4_SPECSIG","A1_SPECSIG","/A6_SPECSIG","/A3_SPECSIG","A2_SPECSIG","/AUTO_CONFIG_DONE0_SPECSIG","autoconfig");
+          
+            pterms["FB1_18_2"]=new Array("RESET","RW","/AS","/A5_SPECSIG","A4_SPECSIG","/A6_SPECSIG","A3_SPECSIG","/A2_SPECSIG","AUTO_CONFIG_DONE0_SPECSIG","/AUTO_CONFIG_DONE1_SPECSIG","autoconfig");
+          
+            pterms["FB1_18_3"]=new Array("RESET","RW","/AS","/A5_SPECSIG","/A4_SPECSIG","/A1_SPECSIG","/A3_SPECSIG","/A2_SPECSIG","AUTO_CONFIG_DONE1_SPECSIG","/AUTO_CONFIG_DONE2_SPECSIG","autoconfig");
+          
+            pterms["FB1_18_4"]=new Array("RESET","RW","/AS","/A5_SPECSIG","/A4_SPECSIG","/A1_SPECSIG","/A3_SPECSIG","/A2_SPECSIG","/AUTO_CONFIG_DONE1_SPECSIG","AUTOBOOT_OFF","autoconfig");
+          
+            pterms["FB1_18_5"]=new Array("ideide_CLKF_SPECSIG");
+          
+            pterms["FB2_1_1"]=new Array("RESET","RW","/AS","/A5_SPECSIG","/A4_SPECSIG","A1_SPECSIG","/A3_SPECSIG","/A2_SPECSIG","/AUTO_CONFIG_DONE1_SPECSIG","autoconfig");
+          
+            pterms["FB2_1_2"]=new Array("RESET","RW","/AS","/A5_SPECSIG","/A4_SPECSIG","A1_SPECSIG","/A3_SPECSIG","/A2_SPECSIG","/AUTO_CONFIG_DONE2_SPECSIG","autoconfig");
+          
+            pterms["FB2_1_3"]=new Array("RESET","RW","/AS","/A5_SPECSIG","A1_SPECSIG","/A6_SPECSIG","/A3_SPECSIG","A2_SPECSIG","AUTO_CONFIG_DONE0_SPECSIG","/AUTO_CONFIG_DONE1_SPECSIG","autoconfig");
+          
+            pterms["FB2_1_4"]=new Array("RESET","RW","/AS","/A5_SPECSIG","/A4_SPECSIG","/A6_SPECSIG","/A3_SPECSIG","A2_SPECSIG","AUTO_CONFIG_DONE0_SPECSIG","AUTO_CONFIG_DONE1_SPECSIG","/AUTO_CONFIG_DONE2_SPECSIG","autoconfig");
+          
+            pterms["FB2_1_5"]=new Array("ideide_CLKF_SPECSIG");
+          
+            pterms["FB2_2_1"]=new Array("RESET","RW","/AS","/A5_SPECSIG","/A4_SPECSIG","A1_SPECSIG","/A3_SPECSIG","/A2_SPECSIG","/AUTO_CONFIG_DONE0_SPECSIG","autoconfig");
+          
+            pterms["FB2_2_2"]=new Array("RESET","RW","/AS","/A5_SPECSIG","/A4_SPECSIG","A6_SPECSIG","/A3_SPECSIG","/A2_SPECSIG","/AUTO_CONFIG_DONE0_SPECSIG","autoconfig");
+          
+            pterms["FB2_2_3"]=new Array("RESET","RW","/AS","/A5_SPECSIG","/A4_SPECSIG","A6_SPECSIG","/A3_SPECSIG","/A2_SPECSIG","/AUTO_CONFIG_DONE1_SPECSIG","autoconfig");
+          
+            pterms["FB2_2_4"]=new Array("RESET","RW","/AS","/A5_SPECSIG","/A4_SPECSIG","A6_SPECSIG","/A3_SPECSIG","/A2_SPECSIG","/AUTO_CONFIG_DONE2_SPECSIG","autoconfig");
+          
+            pterms["FB2_2_5"]=new Array("RESET","RW","/AS","/A4_SPECSIG","A1_SPECSIG","/A6_SPECSIG","/A3_SPECSIG","A2_SPECSIG","AUTO_CONFIG_DONE0_SPECSIG","/AUTO_CONFIG_DONE1_SPECSIG","autoconfig");
+          
+            pterms["FB2_3_1"]=new Array("RESET","RW","/AS","/A5_SPECSIG","A4_SPECSIG","A1_SPECSIG","/A6_SPECSIG","/A3_SPECSIG","A2_SPECSIG","/AUTO_CONFIG_DONE0_SPECSIG","autoconfig");
+          
+            pterms["FB2_3_2"]=new Array("RESET","RW","/AS","/A5_SPECSIG","/A4_SPECSIG","/A1_SPECSIG","/A6_SPECSIG","/A3_SPECSIG","A2_SPECSIG","/AUTO_CONFIG_DONE0_SPECSIG","autoconfig");
+          
+            pterms["FB2_3_3"]=new Array("RESET","RW","/AS","/A5_SPECSIG","A4_SPECSIG","/A1_SPECSIG","/A6_SPECSIG","A3_SPECSIG","A2_SPECSIG","AUTO_CONFIG_DONE0_SPECSIG","/AUTO_CONFIG_DONE1_SPECSIG","autoconfig");
+          
+            pterms["FB2_5_1"]=new Array("RW","AUTOCONFIG_IN_PROGRESS");
+          
+            pterms["FB2_8_1"]=new Array("AUTO_CONFIG_DONE_CYCLE2_SPECSIG");
+          
+            pterms["FB2_8_2"]=new Array("AS");
+          
+            pterms["FB2_9_1"]=new Array("AUTO_CONFIG_DONE_CYCLE0_SPECSIG");
+          
+            pterms["FB2_9_2"]=new Array("AS");
+          
+            pterms["FB2_10_1"]=new Array("RESET","AUTO_CONFIG_DONE_CYCLE2_SPECSIG");
+          
+            pterms["FB2_10_2"]=new Array("RESET","/UDS","/RW","/AS","/A5_SPECSIG","/A4_SPECSIG","/A1_SPECSIG","A6_SPECSIG","A3_SPECSIG","AUTO_CONFIG_DONE0_SPECSIG","AUTO_CONFIG_DONE1_SPECSIG","/AUTO_CONFIG_DONE2_SPECSIG","autoconfig");
+          
+            pterms["FB2_10_3"]=new Array("ideide_CLKF_SPECSIG");
+          
+            pterms["FB2_11_1"]=new Array("RESET","AUTO_CONFIG_DONE_CYCLE0_SPECSIG");
+          
+            pterms["FB2_11_2"]=new Array("RESET","/UDS","/RW","/AS","/A5_SPECSIG","/A4_SPECSIG","/A1_SPECSIG","A6_SPECSIG","A3_SPECSIG","/AUTO_CONFIG_DONE0_SPECSIG","autoconfig");
+          
+            pterms["FB2_11_3"]=new Array("ideide_CLKF_SPECSIG");
+          
+            pterms["FB2_11_4"]=new Array("RESET","/UDS","/RW","/AS","/A5_SPECSIG","/A4_SPECSIG","/A1_SPECSIG","A6_SPECSIG","A3_SPECSIG","/A2_SPECSIG","AUTO_CONFIG_DONE0_SPECSIG","/AUTO_CONFIG_DONE1_SPECSIG","IDE_BASEADR7_SPECSIG","autoconfig","/D15PIN_SPECSIG");
+          
+            pterms["FB2_12_1"]=new Array("/RESET","/IDE_BASEADR7_SPECSIG");
+          
+            pterms["FB2_12_2"]=new Array("/UDS","/RW","/AS","/A5_SPECSIG","/A4_SPECSIG","/A1_SPECSIG","A6_SPECSIG","A3_SPECSIG","/A2_SPECSIG","AUTO_CONFIG_DONE0_SPECSIG","/AUTO_CONFIG_DONE1_SPECSIG","/IDE_BASEADR7_SPECSIG","autoconfig","D15PIN_SPECSIG");
+          
+            pterms["FB2_12_3"]=new Array("ideide_CLKF_SPECSIG");
+          
+            pterms["FB2_12_4"]=new Array("/UDS","/RW","/AS","/A5_SPECSIG","/A4_SPECSIG","/A1_SPECSIG","A6_SPECSIG","A3_SPECSIG","/A2_SPECSIG","AUTO_CONFIG_DONE0_SPECSIG","/AUTO_CONFIG_DONE1_SPECSIG","/IDE_BASEADR6_SPECSIG","autoconfig","D14PIN_SPECSIG");
+          
+            pterms["FB2_12_5"]=new Array("RESET","/UDS","/RW","/AS","/A5_SPECSIG","/A4_SPECSIG","/A1_SPECSIG","A6_SPECSIG","A3_SPECSIG","/A2_SPECSIG","AUTO_CONFIG_DONE0_SPECSIG","/AUTO_CONFIG_DONE1_SPECSIG","IDE_BASEADR6_SPECSIG","autoconfig","/D14PIN_SPECSIG");
+          
+            pterms["FB2_13_1"]=new Array("/RESET","/IDE_BASEADR6_SPECSIG");
+          
+            pterms["FB2_13_2"]=new Array("ideide_CLKF_SPECSIG");
+          
+            pterms["FB2_13_3"]=new Array("RESET","RW","/AS","/A5_SPECSIG","A4_SPECSIG","/A1_SPECSIG","/A6_SPECSIG","A3_SPECSIG","AUTO_CONFIG_DONE0_SPECSIG","/AUTO_CONFIG_DONE1_SPECSIG","autoconfig");
+          
+            pterms["FB2_13_4"]=new Array("RESET","RW","/AS","/A5_SPECSIG","/A4_SPECSIG","/A1_SPECSIG","/A6_SPECSIG","/A3_SPECSIG","AUTO_CONFIG_DONE1_SPECSIG","/AUTO_CONFIG_DONE2_SPECSIG","autoconfig");
+          
+            pterms["FB2_13_5"]=new Array("RESET","RW","/AS","A5_SPECSIG","/A4_SPECSIG","/A1_SPECSIG","/A6_SPECSIG","/A3_SPECSIG","A2_SPECSIG","AUTO_CONFIG_DONE0_SPECSIG","/AUTO_CONFIG_DONE1_SPECSIG","autoconfig");
+          
+            pterms["FB2_14_1"]=new Array("RESET","/D13_SPECSIG","/RW");
+          
+            pterms["FB2_14_2"]=new Array("RESET","/D13_SPECSIG","AUTO_CONFIG_DONE0_SPECSIG","AUTO_CONFIG_DONE1_SPECSIG","AUTO_CONFIG_DONE2_SPECSIG");
+          
+            pterms["FB2_14_3"]=new Array("RESET","RW","/AS","/A5_SPECSIG","/A4_SPECSIG","/A6_SPECSIG","/A3_SPECSIG","/AUTO_CONFIG_DONE0_SPECSIG","autoconfig");
+          
+            pterms["FB2_14_4"]=new Array("RESET","RW","/AS","/A5_SPECSIG","/A4_SPECSIG","/A3_SPECSIG","/A2_SPECSIG","/AUTO_CONFIG_DONE0_SPECSIG","autoconfig");
+          
+            pterms["FB2_14_5"]=new Array("RESET","RW","/AS","/A5_SPECSIG","/A4_SPECSIG","/A3_SPECSIG","/A2_SPECSIG","/AUTO_CONFIG_DONE1_SPECSIG","autoconfig");
+          
+            pterms["FB2_15_1"]=new Array("RESET","/D13_SPECSIG","AS");
+          
+            pterms["FB2_15_2"]=new Array("RESET","/D13_SPECSIG","/autoconfig");
+          
+            pterms["FB2_15_3"]=new Array("RESET","RW","/AS","/A5_SPECSIG","A4_SPECSIG","/A6_SPECSIG","A3_SPECSIG","A2_SPECSIG","AUTO_CONFIG_DONE0_SPECSIG","/AUTO_CONFIG_DONE1_SPECSIG","autoconfig");
+          
+            pterms["FB2_15_4"]=new Array("RESET","RW","/AS","/A5_SPECSIG","A1_SPECSIG","/A6_SPECSIG","/A3_SPECSIG","/A2_SPECSIG","AUTO_CONFIG_DONE1_SPECSIG","/AUTO_CONFIG_DONE2_SPECSIG","autoconfig");
+          
+            pterms["FB2_15_5"]=new Array("ideide_CLKF_SPECSIG");
+          
+            pterms["FB2_16_1"]=new Array("RW","AUTOCONFIG_IN_PROGRESS");
+          
+            pterms["FB2_16_2"]=new Array("RESET","RW","/AS","/A5_SPECSIG","/A4_SPECSIG","/A3_SPECSIG","/A2_SPECSIG","/AUTO_CONFIG_DONE2_SPECSIG","autoconfig");
+          
+            pterms["FB2_16_3"]=new Array("RESET","RW","/AS","/A5_SPECSIG","/A4_SPECSIG","A1_SPECSIG","/A6_SPECSIG","/A3_SPECSIG","/AUTO_CONFIG_DONE1_SPECSIG","autoconfig");
+          
+            pterms["FB2_16_4"]=new Array("RESET","RW","/AS","/A5_SPECSIG","A1_SPECSIG","/A6_SPECSIG","/A3_SPECSIG","/A2_SPECSIG","/AUTO_CONFIG_DONE0_SPECSIG","autoconfig");
+          
+            pterms["FB2_16_5"]=new Array("RESET","RW","/AS","/A5_SPECSIG","A4_SPECSIG","/A1_SPECSIG","/A6_SPECSIG","A2_SPECSIG","AUTO_CONFIG_DONE0_SPECSIG","/AUTO_CONFIG_DONE1_SPECSIG","autoconfig");
+          
+            pterms["FB2_17_1"]=new Array("RW","AUTOCONFIG_IN_PROGRESS");
+          
+            pterms["FB2_18_1"]=new Array("RESET","/D14_SPECSIG","/RW");
+          
+            pterms["FB2_18_2"]=new Array("RESET","/D14_SPECSIG","AS");
+          
+            pterms["FB2_18_3"]=new Array("RESET","/D14_SPECSIG","/autoconfig");
+          
+            pterms["FB2_18_4"]=new Array("RESET","/D14_SPECSIG","AUTO_CONFIG_DONE0_SPECSIG","AUTO_CONFIG_DONE1_SPECSIG","AUTO_CONFIG_DONE2_SPECSIG");
+          
+            pterms["FB2_18_5"]=new Array("RESET","RW","/AS","/A5_SPECSIG","A1_SPECSIG","/A6_SPECSIG","/A3_SPECSIG","A2_SPECSIG","AUTO_CONFIG_DONE0_SPECSIG","/AUTO_CONFIG_DONE2_SPECSIG","autoconfig");
+          
+            pterms["FB3_1_1"]=new Array("RW","AUTOCONFIG_IN_PROGRESS");
+          
+            pterms["FB3_3_1"]=new Array("RW","AUTOCONFIG_IN_PROGRESS");
+          
+            pterms["FB3_4_1"]=new Array("D12_BUFR_SPECSIG");
+          
+            pterms["FB3_4_2"]=new Array("RW","AUTOCONFIG_IN_PROGRESS");
+          
+            pterms["FB3_7_1"]=new Array("D14_BUFR_SPECSIG");
+          
+            pterms["FB3_7_2"]=new Array("RW","AUTOCONFIG_IN_PROGRESS");
+          
+            pterms["FB3_9_1"]=new Array("RW","AUTOCONFIG_IN_PROGRESS");
+          
+            pterms["FB3_10_1"]=new Array("D15_BUFR_SPECSIG");
+          
+            pterms["FB3_10_2"]=new Array("RW","AUTOCONFIG_IN_PROGRESS");
+          
+            pterms["FB3_11_1"]=new Array("RW","AUTOCONFIG_IN_PROGRESS");
+          
+            pterms["FB3_12_1"]=new Array("D13_BUFR_SPECSIG");
+          
+            pterms["FB3_12_2"]=new Array("RW","AUTOCONFIG_IN_PROGRESS");
+          
+            pterms["FB3_15_1"]=new Array("AUTO_CONFIG_DONE_CYCLE1_SPECSIG");
+          
+            pterms["FB3_15_2"]=new Array("AS");
+          
+            pterms["FB3_16_1"]=new Array("RESET","AUTO_CONFIG_DONE_CYCLE1_SPECSIG");
+          
+            pterms["FB3_16_2"]=new Array("RESET","/UDS","/RW","/AS","/A5_SPECSIG","/A4_SPECSIG","/A1_SPECSIG","A6_SPECSIG","A3_SPECSIG","AUTO_CONFIG_DONE0_SPECSIG","/AUTO_CONFIG_DONE1_SPECSIG","autoconfig");
+          
+            pterms["FB3_16_3"]=new Array("ideide_CLKF_SPECSIG");
+          
+            pterms["FB3_17_1"]=new Array("/RESET","/IDE_BASEADR3_SPECSIG");
+          
+            pterms["FB3_17_2"]=new Array("/UDS","/RW","/AS","/A5_SPECSIG","/A4_SPECSIG","/A1_SPECSIG","A6_SPECSIG","A3_SPECSIG","/A2_SPECSIG","AUTO_CONFIG_DONE0_SPECSIG","/AUTO_CONFIG_DONE1_SPECSIG","/IDE_BASEADR3_SPECSIG","autoconfig","D11PIN_SPECSIG");
+          
+            pterms["FB3_17_3"]=new Array("RESET","/UDS","/RW","/AS","/A5_SPECSIG","/A4_SPECSIG","/A1_SPECSIG","A6_SPECSIG","A3_SPECSIG","/A2_SPECSIG","AUTO_CONFIG_DONE0_SPECSIG","/AUTO_CONFIG_DONE1_SPECSIG","IDE_BASEADR3_SPECSIG","autoconfig","/D11PIN_SPECSIG");
+          
+            pterms["FB3_17_4"]=new Array("ideide_CLKF_SPECSIG");
+          
+            pterms["FB3_18_1"]=new Array("/RESET","/IDE_BASEADR2_SPECSIG");
+          
+            pterms["FB3_18_2"]=new Array("/UDS","/RW","/AS","/A5_SPECSIG","/A4_SPECSIG","/A1_SPECSIG","A6_SPECSIG","A3_SPECSIG","/A2_SPECSIG","AUTO_CONFIG_DONE0_SPECSIG","/AUTO_CONFIG_DONE1_SPECSIG","/IDE_BASEADR2_SPECSIG","autoconfig","D10PIN_SPECSIG");
+          
+            pterms["FB3_18_3"]=new Array("RESET","/UDS","/RW","/AS","/A5_SPECSIG","/A4_SPECSIG","/A1_SPECSIG","A6_SPECSIG","A3_SPECSIG","/A2_SPECSIG","AUTO_CONFIG_DONE0_SPECSIG","/AUTO_CONFIG_DONE1_SPECSIG","IDE_BASEADR2_SPECSIG","autoconfig","/D10PIN_SPECSIG");
+          
+            pterms["FB3_18_4"]=new Array("ideide_CLKF_SPECSIG");
+          
+            pterms["FB4_1_1"]=new Array("SHUT_UP1_SPECSIG");
+          
+            pterms["FB4_1_2"]=new Array("/BERR");
+          
+            pterms["FB4_1_3"]=new Array("A19_SPECSIG","/IDE_BASEADR3_SPECSIG");
+          
+            pterms["FB4_1_4"]=new Array("/A19_SPECSIG","IDE_BASEADR3_SPECSIG");
+          
+            pterms["FB4_1_5"]=new Array("ideide_CLKF_SPECSIG");
+          
+            pterms["FB4_2_1"]=new Array("A23_SPECSIG","/IDE_BASEADR7_SPECSIG");
+          
+            pterms["FB4_2_2"]=new Array("/A23_SPECSIG","IDE_BASEADR7_SPECSIG");
+          
+            pterms["FB4_2_3"]=new Array("A22_SPECSIG","/IDE_BASEADR6_SPECSIG");
+          
+            pterms["FB4_2_4"]=new Array("/A22_SPECSIG","IDE_BASEADR6_SPECSIG");
+          
+            pterms["FB4_2_5"]=new Array("IDE_BASEADR1_SPECSIG","/A17_SPECSIG");
+          
+            pterms["FB4_3_1"]=new Array("/A21_SPECSIG","IDE_BASEADR5_SPECSIG");
+          
+            pterms["FB4_3_2"]=new Array("IDE_BASEADR4_SPECSIG","/A20_SPECSIG");
+          
+            pterms["FB4_3_3"]=new Array("/IDE_BASEADR4_SPECSIG","A20_SPECSIG");
+          
+            pterms["FB4_16_1"]=new Array("C3");
+          
+            pterms["FB4_16_2"]=new Array("C1");
+          
+            pterms["FB4_17_1"]=new Array("A23_SPECSIG","A22_SPECSIG","A21_SPECSIG","A19_SPECSIG","/AUTO_CONFIG_DONE0_SPECSIG","BERR","/A17_SPECSIG","/A16_SPECSIG","/A20_SPECSIG","/A18_SPECSIG");
+          
+            pterms["FB4_17_2"]=new Array("A23_SPECSIG","A22_SPECSIG","A21_SPECSIG","A19_SPECSIG","/AUTO_CONFIG_DONE1_SPECSIG","BERR","/A17_SPECSIG","/A16_SPECSIG","/A20_SPECSIG","/A18_SPECSIG");
+          
+            pterms["FB4_17_3"]=new Array("A23_SPECSIG","A22_SPECSIG","A21_SPECSIG","A19_SPECSIG","/AUTO_CONFIG_DONE2_SPECSIG","BERR","/A17_SPECSIG","/A16_SPECSIG","/A20_SPECSIG","/A18_SPECSIG");
+          
+            pterms["FB4_17_4"]=new Array("ideide_CLKF_SPECSIG");
+          
+            pterms["FB4_17_5"]=new Array("A21_SPECSIG","/IDE_BASEADR5_SPECSIG");
+          
+            pterms["FB4_18_1"]=new Array("IDE_BASEADR0_SPECSIG","/A16_SPECSIG");
+          
+            pterms["FB4_18_2"]=new Array("/IDE_BASEADR0_SPECSIG","A16_SPECSIG");
+          
+            pterms["FB4_18_3"]=new Array("/IDE_BASEADR1_SPECSIG","A17_SPECSIG");
+          
+            pterms["FB4_18_4"]=new Array("IDE_BASEADR2_SPECSIG","/A18_SPECSIG");
+          
+            pterms["FB4_18_5"]=new Array("/IDE_BASEADR2_SPECSIG","A18_SPECSIG");
+          
+            pterms["FB5_13_1"]=new Array("RESET","/SHUT_UP1_SPECSIG");
+          
+            pterms["FB5_13_2"]=new Array("RESET","/UDS","/RW","/AS","/A5_SPECSIG","/A4_SPECSIG","/A1_SPECSIG","A6_SPECSIG","A3_SPECSIG","/A2_SPECSIG","AUTO_CONFIG_DONE0_SPECSIG","/AUTO_CONFIG_DONE1_SPECSIG","autoconfig");
+          
+            pterms["FB5_13_3"]=new Array("ideide_CLKF_SPECSIG");
+          
+            pterms["FB5_14_1"]=new Array("/RESET","/IDE_BASEADR5_SPECSIG");
+          
+            pterms["FB5_14_2"]=new Array("/UDS","/RW","/AS","/A5_SPECSIG","/A4_SPECSIG","/A1_SPECSIG","A6_SPECSIG","A3_SPECSIG","/A2_SPECSIG","AUTO_CONFIG_DONE0_SPECSIG","/AUTO_CONFIG_DONE1_SPECSIG","/IDE_BASEADR5_SPECSIG","autoconfig","D13PIN_SPECSIG");
+          
+            pterms["FB5_14_3"]=new Array("RESET","/UDS","/RW","/AS","/A5_SPECSIG","/A4_SPECSIG","/A1_SPECSIG","A6_SPECSIG","A3_SPECSIG","/A2_SPECSIG","AUTO_CONFIG_DONE0_SPECSIG","/AUTO_CONFIG_DONE1_SPECSIG","IDE_BASEADR5_SPECSIG","autoconfig","/D13PIN_SPECSIG");
+          
+            pterms["FB5_14_4"]=new Array("ideide_CLKF_SPECSIG");
+          
+            pterms["FB5_15_1"]=new Array("/RESET","/IDE_BASEADR4_SPECSIG");
+          
+            pterms["FB5_15_2"]=new Array("/UDS","/RW","/AS","/A5_SPECSIG","/A4_SPECSIG","/A1_SPECSIG","A6_SPECSIG","A3_SPECSIG","/A2_SPECSIG","AUTO_CONFIG_DONE0_SPECSIG","/AUTO_CONFIG_DONE1_SPECSIG","/IDE_BASEADR4_SPECSIG","autoconfig","D12PIN_SPECSIG");
+          
+            pterms["FB5_15_3"]=new Array("RESET","/UDS","/RW","/AS","/A5_SPECSIG","/A4_SPECSIG","/A1_SPECSIG","A6_SPECSIG","A3_SPECSIG","/A2_SPECSIG","AUTO_CONFIG_DONE0_SPECSIG","/AUTO_CONFIG_DONE1_SPECSIG","IDE_BASEADR4_SPECSIG","autoconfig","/D12PIN_SPECSIG");
+          
+            pterms["FB5_15_4"]=new Array("ideide_CLKF_SPECSIG");
+          
+            pterms["FB5_16_1"]=new Array("/RESET","/IDE_BASEADR1_SPECSIG");
+          
+            pterms["FB5_16_2"]=new Array("/UDS","/RW","/AS","/A5_SPECSIG","/A4_SPECSIG","/A1_SPECSIG","A6_SPECSIG","A3_SPECSIG","/A2_SPECSIG","AUTO_CONFIG_DONE0_SPECSIG","/AUTO_CONFIG_DONE1_SPECSIG","/IDE_BASEADR1_SPECSIG","autoconfig","D9PIN_SPECSIG");
+          
+            pterms["FB5_16_3"]=new Array("RESET","/UDS","/RW","/AS","/A5_SPECSIG","/A4_SPECSIG","/A1_SPECSIG","A6_SPECSIG","A3_SPECSIG","/A2_SPECSIG","AUTO_CONFIG_DONE0_SPECSIG","/AUTO_CONFIG_DONE1_SPECSIG","IDE_BASEADR1_SPECSIG","autoconfig","/D9PIN_SPECSIG");
+          
+            pterms["FB5_16_4"]=new Array("ideide_CLKF_SPECSIG");
+          
+            pterms["FB5_18_1"]=new Array("/RESET","/IDE_BASEADR0_SPECSIG");
+          
+            pterms["FB5_18_2"]=new Array("/UDS","/RW","/AS","/A5_SPECSIG","/A4_SPECSIG","/A1_SPECSIG","A6_SPECSIG","A3_SPECSIG","/A2_SPECSIG","AUTO_CONFIG_DONE0_SPECSIG","/AUTO_CONFIG_DONE1_SPECSIG","/IDE_BASEADR0_SPECSIG","autoconfig","D8PIN_SPECSIG");
+          
+            pterms["FB5_18_3"]=new Array("RESET","/UDS","/RW","/AS","/A5_SPECSIG","/A4_SPECSIG","/A1_SPECSIG","A6_SPECSIG","A3_SPECSIG","/A2_SPECSIG","AUTO_CONFIG_DONE0_SPECSIG","/AUTO_CONFIG_DONE1_SPECSIG","IDE_BASEADR0_SPECSIG","autoconfig","/D8PIN_SPECSIG");
+          
+            pterms["FB5_18_4"]=new Array("ideide_CLKF_SPECSIG");
+          
+            pterms["FB6_16_1"]=new Array("RESET","/D15_SPECSIG","AUTO_CONFIG_DONE0_SPECSIG","AUTO_CONFIG_DONE1_SPECSIG","AUTO_CONFIG_DONE2_SPECSIG");
+          
+            pterms["FB6_16_2"]=new Array("RESET","RW","/AS","/A5_SPECSIG","A1_SPECSIG","/A6_SPECSIG","/A3_SPECSIG","/AUTO_CONFIG_DONE0_SPECSIG","autoconfig");
+          
+            pterms["FB6_16_3"]=new Array("RESET","RW","/AS","/A5_SPECSIG","/A4_SPECSIG","A6_SPECSIG","/A3_SPECSIG","/A2_SPECSIG","/AUTO_CONFIG_DONE0_SPECSIG","autoconfig");
+          
+            pterms["FB6_16_4"]=new Array("RESET","RW","/AS","/A5_SPECSIG","/A4_SPECSIG","A6_SPECSIG","/A3_SPECSIG","/A2_SPECSIG","/AUTO_CONFIG_DONE1_SPECSIG","autoconfig");
+          
+            pterms["FB6_17_1"]=new Array("RESET","/D15_SPECSIG","/RW");
+          
+            pterms["FB6_17_2"]=new Array("RESET","/D15_SPECSIG","AS");
+          
+            pterms["FB6_17_3"]=new Array("RESET","/D15_SPECSIG","/autoconfig");
+          
+            pterms["FB6_17_4"]=new Array("RESET","RW","/AS","/A5_SPECSIG","A1_SPECSIG","/A6_SPECSIG","/A3_SPECSIG","/A2_SPECSIG","/AUTO_CONFIG_DONE1_SPECSIG","autoconfig");
+          
+            pterms["FB6_17_5"]=new Array("ideide_CLKF_SPECSIG");
+          
+            pterms["FB6_18_1"]=new Array("RESET","RW","/AS","/A5_SPECSIG","/A4_SPECSIG","A6_SPECSIG","/A3_SPECSIG","/A2_SPECSIG","/AUTO_CONFIG_DONE2_SPECSIG","autoconfig");
+          
+            pterms["FB6_18_2"]=new Array("RESET","RW","/AS","/A5_SPECSIG","A1_SPECSIG","/A6_SPECSIG","/A3_SPECSIG","AUTO_CONFIG_DONE1_SPECSIG","/AUTO_CONFIG_DONE2_SPECSIG","autoconfig");
+          
+            pterms["FB6_18_3"]=new Array("RESET","RW","/AS","/A5_SPECSIG","A4_SPECSIG","A1_SPECSIG","/A6_SPECSIG","A2_SPECSIG","AUTO_CONFIG_DONE0_SPECSIG","/AUTO_CONFIG_DONE1_SPECSIG","autoconfig");
+          
+            pterms["FB6_18_4"]=new Array("RESET","RW","/AS","A5_SPECSIG","/A4_SPECSIG","/A1_SPECSIG","/A6_SPECSIG","/A3_SPECSIG","A2_SPECSIG","AUTO_CONFIG_DONE0_SPECSIG","/AUTO_CONFIG_DONE1_SPECSIG","autoconfig");
+          
+            pterms["FB6_18_5"]=new Array("RESET","RW","/AS","/A5_SPECSIG","A4_SPECSIG","/A1_SPECSIG","/A6_SPECSIG","A3_SPECSIG","/A2_SPECSIG","AUTO_CONFIG_DONE0_SPECSIG","/AUTO_CONFIG_DONE1_SPECSIG","autoconfig");
+          
+          d2["IDE_CS1_SPECSIG"]=new Array("FB1_2_2");
+          
+            d2imp["IDE_CS1_SPECSIG"]=new Array("1");
+          
+          d2["D7_SPECSIG"]=new Array("VCC");
+          
+            d2imp["D7_SPECSIG"]=new Array("1");
+          
+              trst["D7_SPECSIG"]=new Array("FB1_2_1");
+              
+                trstimp["D7_SPECSIG"]=new Array("1");
+              
+          d2["D1_SPECSIG"]=new Array("VCC");
+          
+            d2imp["D1_SPECSIG"]=new Array("1");
+          
+              trst["D1_SPECSIG"]=new Array("FB1_3_1");
+              
+                trstimp["D1_SPECSIG"]=new Array("1");
+              
+          d2["IDE_A2_SPECSIG"]=new Array("FB1_4_1");
+          
+            d2imp["IDE_A2_SPECSIG"]=new Array("1");
+          
+          d2["D8_SPECSIG"]=new Array("VCC");
+          
+            d2imp["D8_SPECSIG"]=new Array("1");
+          
+              trst["D8_SPECSIG"]=new Array("FB1_5_1");
+              
+                trstimp["D8_SPECSIG"]=new Array("1");
+              
+          d2["D5_SPECSIG"]=new Array("VCC");
+          
+            d2imp["D5_SPECSIG"]=new Array("1");
+          
+              trst["D5_SPECSIG"]=new Array("FB1_6_1");
+              
+                trstimp["D5_SPECSIG"]=new Array("1");
+              
+          d2["AUTOCONFIG_IN_PROGRESS"]=new Array("FB1_7_1");
+          
+            d2imp["AUTOCONFIG_IN_PROGRESS"]=new Array("1");
+          
+              clk["AUTOCONFIG_IN_PROGRESS"]=new Array("FB1_7_2");
+              
+                clkimp["AUTOCONFIG_IN_PROGRESS"]=new Array("1");
+              prld["AUTOCONFIG_IN_PROGRESS"]="GND";
+          d2["D4_SPECSIG"]=new Array("VCC");
+          
+            d2imp["D4_SPECSIG"]=new Array("1");
+          
+              trst["D4_SPECSIG"]=new Array("FB1_8_1");
+              
+                trstimp["D4_SPECSIG"]=new Array("1");
+              
+          d2["IDE_CS0_SPECSIG"]=new Array("FB1_9_1");
+          
+            d2imp["IDE_CS0_SPECSIG"]=new Array("1");
+          
+          d2["IDE_ENABLE"]=new Array("FB1_10_1","FB1_10_2");
+          
+            d2imp["IDE_ENABLE"]=new Array("1","1");
+          
+              clk["IDE_ENABLE"]=new Array("FB1_10_3");
+              
+                clkimp["IDE_ENABLE"]=new Array("1");
+              prld["IDE_ENABLE"]="GND";
+          d2["IDE_A0_SPECSIG"]=new Array("FB1_11_1");
+          
+            d2imp["IDE_A0_SPECSIG"]=new Array("1");
+          
+          d2["IDE_A1_SPECSIG"]=new Array("FB1_12_1");
+          
+            d2imp["IDE_A1_SPECSIG"]=new Array("1");
+          
+          d2["IDE_R"]=new Array("FB1_14_1");
+          
+            d2imp["IDE_R"]=new Array("1");
+          
+              clk["IDE_R"]=new Array("FB1_14_2");
+              
+                clkimp["IDE_R"]=new Array("1");
+              prld["IDE_R"]="VCC";
+          d2["IDE_W"]=new Array("FB1_15_1");
+          
+            d2imp["IDE_W"]=new Array("1");
+          
+              clk["IDE_W"]=new Array("FB1_15_2");
+              
+                clkimp["IDE_W"]=new Array("1");
+              prld["IDE_W"]="VCC";
+          d2["ROM_OE"]=new Array("FB1_15_3");
+          
+            d2imp["ROM_OE"]=new Array("1");
+          
+              clk["ROM_OE"]=new Array("FB1_16_1");
+              
+                clkimp["ROM_OE"]=new Array("1");
+              prld["ROM_OE"]="VCC";
+          d2["D12_BUFR_SPECSIG"]=new Array("FB1_18_1","FB1_18_2","FB1_18_3","FB1_18_4","FB1_1_1","FB1_1_2","FB1_1_3","FB1_1_4","FB1_1_5","FB1_17_1","FB1_17_2","FB1_17_3","FB1_17_4","FB1_17_5","FB1_16_2","FB1_16_3","FB1_16_4","FB1_16_5");
+          
+            d2imp["D12_BUFR_SPECSIG"]=new Array("1","1","1","1","1","1","1","1","1","1","1","1","1","1","1","1","1","1");
+          
+              clk["D12_BUFR_SPECSIG"]=new Array("FB1_18_5");
+              
+                clkimp["D12_BUFR_SPECSIG"]=new Array("1");
+              prld["D12_BUFR_SPECSIG"]="GND";
+          d2["D14_BUFR_SPECSIG"]=new Array("FB2_1_1","FB2_1_2","FB2_1_3","FB2_1_4","FB2_2_1","FB2_2_2","FB2_2_3","FB2_2_4","FB2_2_5","FB2_3_1","FB2_3_2","FB2_3_3","FB2_18_1","FB2_18_2","FB2_18_3","FB2_18_4","FB2_18_5");
+          
+            d2imp["D14_BUFR_SPECSIG"]=new Array("1","1","1","1","1","1","1","1","1","1","1","1","1","1","1","1","1");
+          
+              clk["D14_BUFR_SPECSIG"]=new Array("FB2_1_5");
+              
+                clkimp["D14_BUFR_SPECSIG"]=new Array("1");
+              prld["D14_BUFR_SPECSIG"]="GND";
+          d2["D0_SPECSIG"]=new Array("VCC");
+          
+            d2imp["D0_SPECSIG"]=new Array("1");
+          
+              trst["D0_SPECSIG"]=new Array("FB2_5_1");
+              
+                trstimp["D0_SPECSIG"]=new Array("1");
+              
+          d2["AUTO_CONFIG_DONE2_SPECSIG"]=new Array("FB2_8_1");
+          
+            d2imp["AUTO_CONFIG_DONE2_SPECSIG"]=new Array("1");
+          
+              clk["AUTO_CONFIG_DONE2_SPECSIG"]=new Array("FB2_8_2");
+              
+                clkimp["AUTO_CONFIG_DONE2_SPECSIG"]=new Array("1");
+              
+              gblrst["AUTO_CONFIG_DONE2_SPECSIG"]=new Array("RESET");
+            prld["AUTO_CONFIG_DONE2_SPECSIG"]="GND";
+          d2["AUTO_CONFIG_DONE0_SPECSIG"]=new Array("FB2_9_1");
+          
+            d2imp["AUTO_CONFIG_DONE0_SPECSIG"]=new Array("1");
+          
+              clk["AUTO_CONFIG_DONE0_SPECSIG"]=new Array("FB2_9_2");
+              
+                clkimp["AUTO_CONFIG_DONE0_SPECSIG"]=new Array("1");
+              
+              gblrst["AUTO_CONFIG_DONE0_SPECSIG"]=new Array("RESET");
+            prld["AUTO_CONFIG_DONE0_SPECSIG"]="GND";
+          d2["AUTO_CONFIG_DONE_CYCLE2_SPECSIG"]=new Array("FB2_10_1","FB2_10_2");
+          
+            d2imp["AUTO_CONFIG_DONE_CYCLE2_SPECSIG"]=new Array("1","1");
+          
+              clk["AUTO_CONFIG_DONE_CYCLE2_SPECSIG"]=new Array("FB2_10_3");
+              
+                clkimp["AUTO_CONFIG_DONE_CYCLE2_SPECSIG"]=new Array("1");
+              prld["AUTO_CONFIG_DONE_CYCLE2_SPECSIG"]="GND";
+          d2["AUTO_CONFIG_DONE_CYCLE0_SPECSIG"]=new Array("FB2_11_1","FB2_11_2");
+          
+            d2imp["AUTO_CONFIG_DONE_CYCLE0_SPECSIG"]=new Array("1","1");
+          
+              clk["AUTO_CONFIG_DONE_CYCLE0_SPECSIG"]=new Array("FB2_11_3");
+              
+                clkimp["AUTO_CONFIG_DONE_CYCLE0_SPECSIG"]=new Array("1");
+              prld["AUTO_CONFIG_DONE_CYCLE0_SPECSIG"]="GND";
+          d2["IDE_BASEADR7_SPECSIG"]=new Array("FB2_12_1","FB2_12_2","FB2_11_4");
+          
+            d2imp["IDE_BASEADR7_SPECSIG"]=new Array("1","1","1");
+          
+              clk["IDE_BASEADR7_SPECSIG"]=new Array("FB2_12_3");
+              
+                clkimp["IDE_BASEADR7_SPECSIG"]=new Array("1");
+              prld["IDE_BASEADR7_SPECSIG"]="GND";
+          d2["IDE_BASEADR6_SPECSIG"]=new Array("FB2_13_1","FB2_12_4","FB2_12_5");
+          
+            d2imp["IDE_BASEADR6_SPECSIG"]=new Array("1","1","1");
+          
+              clk["IDE_BASEADR6_SPECSIG"]=new Array("FB2_13_2");
+              
+                clkimp["IDE_BASEADR6_SPECSIG"]=new Array("1");
+              prld["IDE_BASEADR6_SPECSIG"]="GND";
+          d2["D13_BUFR_SPECSIG"]=new Array("FB2_15_1","FB2_15_2","FB2_15_3","FB2_15_4","FB2_14_1","FB2_14_2","FB2_14_3","FB2_14_4","FB2_14_5","FB2_13_3","FB2_13_4","FB2_13_5","FB2_16_2","FB2_16_3","FB2_16_4","FB2_16_5");
+          
+            d2imp["D13_BUFR_SPECSIG"]=new Array("1","1","1","1","1","1","1","1","1","1","1","1","1","1","1","1");
+          
+              clk["D13_BUFR_SPECSIG"]=new Array("FB2_15_5");
+              
+                clkimp["D13_BUFR_SPECSIG"]=new Array("1");
+              prld["D13_BUFR_SPECSIG"]="GND";
+          d2["D6_SPECSIG"]=new Array("VCC");
+          
+            d2imp["D6_SPECSIG"]=new Array("1");
+          
+              trst["D6_SPECSIG"]=new Array("FB2_16_1");
+              
+                trstimp["D6_SPECSIG"]=new Array("1");
+              
+          d2["D3_SPECSIG"]=new Array("VCC");
+          
+            d2imp["D3_SPECSIG"]=new Array("1");
+          
+              trst["D3_SPECSIG"]=new Array("FB2_17_1");
+              
+                trstimp["D3_SPECSIG"]=new Array("1");
+              
+          d2["D2_SPECSIG"]=new Array("VCC");
+          
+            d2imp["D2_SPECSIG"]=new Array("1");
+          
+              trst["D2_SPECSIG"]=new Array("FB3_1_1");
+              
+                trstimp["D2_SPECSIG"]=new Array("1");
+              
+          d2["D10_SPECSIG"]=new Array("VCC");
+          
+            d2imp["D10_SPECSIG"]=new Array("1");
+          
+              trst["D10_SPECSIG"]=new Array("FB3_3_1");
+              
+                trstimp["D10_SPECSIG"]=new Array("1");
+              
+          d2["D12_SPECSIG"]=new Array("FB3_4_1");
+          
+            d2imp["D12_SPECSIG"]=new Array("1");
+          
+              trst["D12_SPECSIG"]=new Array("FB3_4_2");
+              
+                trstimp["D12_SPECSIG"]=new Array("1");
+              
+          d2["D14_SPECSIG"]=new Array("FB3_7_1");
+          
+            d2imp["D14_SPECSIG"]=new Array("1");
+          
+              trst["D14_SPECSIG"]=new Array("FB3_7_2");
+              
+                trstimp["D14_SPECSIG"]=new Array("1");
+              
+          d2["D9_SPECSIG"]=new Array("VCC");
+          
+            d2imp["D9_SPECSIG"]=new Array("1");
+          
+              trst["D9_SPECSIG"]=new Array("FB3_9_1");
+              
+                trstimp["D9_SPECSIG"]=new Array("1");
+              
+          d2["D15_SPECSIG"]=new Array("FB3_10_1");
+          
+            d2imp["D15_SPECSIG"]=new Array("1");
+          
+              trst["D15_SPECSIG"]=new Array("FB3_10_2");
+              
+                trstimp["D15_SPECSIG"]=new Array("1");
+              
+          d2["D11_SPECSIG"]=new Array("VCC");
+          
+            d2imp["D11_SPECSIG"]=new Array("1");
+          
+              trst["D11_SPECSIG"]=new Array("FB3_11_1");
+              
+                trstimp["D11_SPECSIG"]=new Array("1");
+              
+          d2["D13_SPECSIG"]=new Array("FB3_12_1");
+          
+            d2imp["D13_SPECSIG"]=new Array("1");
+          
+              trst["D13_SPECSIG"]=new Array("FB3_12_2");
+              
+                trstimp["D13_SPECSIG"]=new Array("1");
+              
+          d2["AUTO_CONFIG_DONE1_SPECSIG"]=new Array("FB3_15_1");
+          
+            d2imp["AUTO_CONFIG_DONE1_SPECSIG"]=new Array("1");
+          
+              clk["AUTO_CONFIG_DONE1_SPECSIG"]=new Array("FB3_15_2");
+              
+                clkimp["AUTO_CONFIG_DONE1_SPECSIG"]=new Array("1");
+              
+              gblrst["AUTO_CONFIG_DONE1_SPECSIG"]=new Array("RESET");
+            prld["AUTO_CONFIG_DONE1_SPECSIG"]="GND";
+          d2["AUTO_CONFIG_DONE_CYCLE1_SPECSIG"]=new Array("FB3_16_1","FB3_16_2");
+          
+            d2imp["AUTO_CONFIG_DONE_CYCLE1_SPECSIG"]=new Array("1","1");
+          
+              clk["AUTO_CONFIG_DONE_CYCLE1_SPECSIG"]=new Array("FB3_16_3");
+              
+                clkimp["AUTO_CONFIG_DONE_CYCLE1_SPECSIG"]=new Array("1");
+              prld["AUTO_CONFIG_DONE_CYCLE1_SPECSIG"]="GND";
+          d2["IDE_BASEADR3_SPECSIG"]=new Array("FB3_17_1","FB3_17_2","FB3_17_3");
+          
+            d2imp["IDE_BASEADR3_SPECSIG"]=new Array("1","1","1");
+          
+              clk["IDE_BASEADR3_SPECSIG"]=new Array("FB3_17_4");
+              
+                clkimp["IDE_BASEADR3_SPECSIG"]=new Array("1");
+              prld["IDE_BASEADR3_SPECSIG"]="GND";
+          d2["IDE_BASEADR2_SPECSIG"]=new Array("FB3_18_1","FB3_18_2","FB3_18_3");
+          
+            d2imp["IDE_BASEADR2_SPECSIG"]=new Array("1","1","1");
+          
+              clk["IDE_BASEADR2_SPECSIG"]=new Array("FB3_18_4");
+              
+                clkimp["IDE_BASEADR2_SPECSIG"]=new Array("1");
+              prld["IDE_BASEADR2_SPECSIG"]="GND";
+          d2["ide"]=new Array("FB4_1_1","FB4_1_2","FB4_1_3","FB4_1_4","FB4_2_1","FB4_2_2","FB4_2_3","FB4_2_4","FB4_2_5","FB4_3_1","FB4_3_2","FB4_3_3","FB4_18_1","FB4_18_2","FB4_18_3","FB4_18_4","FB4_18_5","FB4_17_5");
+          
+            d2imp["ide"]=new Array("1","1","1","1","1","1","1","1","1","1","1","1","1","1","1","1","1","1");
+          
+              clk["ide"]=new Array("FB4_1_5");
+              
+                clkimp["ide"]=new Array("1");
+              prld["ide"]="GND";
+          d1["ideide_CLKF_SPECSIG"]=new Array("FB4_16_1");
+          
+            d1imp["ideide_CLKF_SPECSIG"]=new Array("1");
+          
+          d2["ideide_CLKF_SPECSIG"]=new Array("FB4_16_2");
+          
+            d2imp["ideide_CLKF_SPECSIG"]=new Array("1");
+          
+          d2["autoconfig"]=new Array("FB4_17_1","FB4_17_2","FB4_17_3");
+          
+            d2imp["autoconfig"]=new Array("1","1","1");
+          
+              clk["autoconfig"]=new Array("FB4_17_4");
+              
+                clkimp["autoconfig"]=new Array("1");
+              prld["autoconfig"]="GND";
+          d2["ROM_B0_SPECSIG"]=new Array("GND");
+          
+            d2imp["ROM_B0_SPECSIG"]=new Array("1");
+          
+          d2["SHUT_UP1_SPECSIG"]=new Array("FB5_13_1","FB5_13_2");
+          
+            d2imp["SHUT_UP1_SPECSIG"]=new Array("1","1");
+          
+              clk["SHUT_UP1_SPECSIG"]=new Array("FB5_13_3");
+              
+                clkimp["SHUT_UP1_SPECSIG"]=new Array("1");
+              prld["SHUT_UP1_SPECSIG"]="GND";
+          d2["IDE_BASEADR5_SPECSIG"]=new Array("FB5_14_1","FB5_14_2","FB5_14_3");
+          
+            d2imp["IDE_BASEADR5_SPECSIG"]=new Array("1","1","1");
+          
+              clk["IDE_BASEADR5_SPECSIG"]=new Array("FB5_14_4");
+              
+                clkimp["IDE_BASEADR5_SPECSIG"]=new Array("1");
+              prld["IDE_BASEADR5_SPECSIG"]="GND";
+          d2["IDE_BASEADR4_SPECSIG"]=new Array("FB5_15_1","FB5_15_2","FB5_15_3");
+          
+            d2imp["IDE_BASEADR4_SPECSIG"]=new Array("1","1","1");
+          
+              clk["IDE_BASEADR4_SPECSIG"]=new Array("FB5_15_4");
+              
+                clkimp["IDE_BASEADR4_SPECSIG"]=new Array("1");
+              prld["IDE_BASEADR4_SPECSIG"]="GND";
+          d2["IDE_BASEADR1_SPECSIG"]=new Array("FB5_16_1","FB5_16_2","FB5_16_3");
+          
+            d2imp["IDE_BASEADR1_SPECSIG"]=new Array("1","1","1");
+          
+              clk["IDE_BASEADR1_SPECSIG"]=new Array("FB5_16_4");
+              
+                clkimp["IDE_BASEADR1_SPECSIG"]=new Array("1");
+              prld["IDE_BASEADR1_SPECSIG"]="GND";
+          d2["ROM_B1_SPECSIG"]=new Array("GND");
+          
+            d2imp["ROM_B1_SPECSIG"]=new Array("1");
+          
+          d2["IDE_BASEADR0_SPECSIG"]=new Array("FB5_18_1","FB5_18_2","FB5_18_3");
+          
+            d2imp["IDE_BASEADR0_SPECSIG"]=new Array("1","1","1");
+          
+              clk["IDE_BASEADR0_SPECSIG"]=new Array("FB5_18_4");
+              
+                clkimp["IDE_BASEADR0_SPECSIG"]=new Array("1");
+              prld["IDE_BASEADR0_SPECSIG"]="GND";
+          d2["D15_BUFR_SPECSIG"]=new Array("FB6_17_1","FB6_17_2","FB6_17_3","FB6_17_4","FB6_16_1","FB6_16_2","FB6_16_3","FB6_16_4","FB6_18_1","FB6_18_2","FB6_18_3","FB6_18_4","FB6_18_5");
+          
+            d2imp["D15_BUFR_SPECSIG"]=new Array("1","1","1","1","1","1","1","1","1","1","1","1","1");
+          
+              clk["D15_BUFR_SPECSIG"]=new Array("FB6_17_5");
+              
+                clkimp["D15_BUFR_SPECSIG"]=new Array("1");
+              prld["D15_BUFR_SPECSIG"]="GND";
+          d2["DTACK"]=new Array("GND");
+          
+            d2imp["DTACK"]=new Array("1");
+          
+              trst["DTACK"]=new Array("GND");
+              
+                trstimp["DTACK"]=new Array("1");
+              
+
+      uimSignals = new Array();
+
+      uimSigNegs = new Array();
+
+      uimPterms = new Array();
+      
+
+      
+        function getEqnList() {
+          var str = "<html><head><link type='text/css' href='style.css' rel='stylesheet'></head><body class='pgBgnd'>";
+          str += "<center><h3>Equations</h3></center>";
+          str += "<table width='90%' align='center' border='1' cellpadding='0' cellspacing='0'>";
+          for (s=0; s<uimSignals.length; s++) {
+            str += "<tr><td>";
+            str += retUimEqn(uimSignals[s]);
+            str += "</td></tr>";
+          }
+          for (s=0; s<signals.length; s++) {
+            str += "<tr><td>";
+            str += retEqn(signals[s]);
+            str += "</td></tr>";
+          }
+
+          var legend = retLegend();
+		      if (legend != "") {
+		        str += "<tr><td>" + legend + "</td></tr>";
+		      }
+
+          str += "</table>";
+          str += "<form><span class='pgRef'>";
+
+          if (!parent.leftnav.IsNS()) {
+            str += "<table width='90%' align='center'>";
+            str += "<tr><td align='left'><input type='button' value='back to top' ";
+            str += "onclick='javascript:parent.leftnav.showEqnAll()' ";
+            str += "onmouseover=\"window.status='goto top of page'; return true;\" ";
+            str += "onmouseout=\"window.status=''\">";
+            str += "</td>";
+            str += "<td align='right'>";
+            str += "<input type='button' value='print page' ";
+            str += "onclick='javascript:window.print()' ";
+            str += "onmouseover=\"window.status='print page'; return true;\" ";
+            str += "onmouseout=\"window.status=''\">";
+            str += "</td>";
+            str += "</tr></table>";
+          }
+          else {
+            str += "<table width='90%' align='center'>";
+            str += "<tr><td align='left'><a href='javascript:parent.leftnav.showEqnAll()'>back to top</a>";
+            str += "</td>";
+            str += "<td align='right'>";
+            str += "<a href='javascript:window.print()'>";
+            str += "print page</a>";
+            str += "</td>";
+            str += "</tr></table>";
+          }
+
+          str += "</span></form>";
+          str += "</body></html>";
+          return str;
+        }
+      
+    </script>
+</head></html>
diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/eqns.js b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/eqns.js
new file mode 100644
index 0000000..0459153
--- /dev/null
+++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/eqns.js
@@ -0,0 +1,929 @@
+var eqnType = 0;
+var spcStr = "&nbsp;";
+var nlStr = "<br>";
+var tabStr = spcStr + spcStr + spcStr + spcStr + spcStr; 
+var nlTabStr = nlStr + tabStr;
+var rClrS = "<font color='blue'>";
+var rClrE = "</font>";
+var cClrS = "<font color='green'>";
+var cClrE = "</font>";
+
+var abelOper = new Array();
+abelOper["GND"] = new Array("Gnd");
+abelOper["VCC"] = new Array("Vcc");
+abelOper["NOT"] = new Array(rClrS + "!" + rClrE);
+abelOper["AND"] = new Array(rClrS + "&" + rClrE);
+abelOper["OR"]  = new Array(rClrS + "#" + rClrE);
+abelOper["XOR"] = new Array(rClrS + "$" + rClrE);
+abelOper["EQUAL_COLON"] = new Array(":= ");
+abelOper["EQUAL"] = new Array("= ");
+abelOper["ASSIGN"] = new Array("");
+abelOper["OPEN_NEGATE"] = new Array("(");
+abelOper["CLOSE_NEGATE"] = new Array(")");
+abelOper["OPEN_PTERM"] = new Array("");
+abelOper["CLOSE_PTERM"] = new Array("");
+abelOper["OPEN_BRACE"] = new Array("<");
+abelOper["CLOSE_BRACE"] = new Array(">");
+abelOper["INVALID_OPEN_BRACE"] = new Array("<");
+abelOper["INVALID_CLOSE_BRACE"] = new Array(">");
+
+abelOper["ENDLN"] = new Array(";");
+abelOper["COMMENT"] = new Array("//");
+abelOper["IMPORT"] = new Array(";Imported pterms ");
+abelOper["GCK_COM"] = new Array("GCK");
+abelOper["GTS_COM"] = new Array("GTS");
+abelOper["GSR_COM"] = new Array("GSR");
+abelOper["OD_COM"] = new Array("Open Drain");
+abelOper["START_EQN"] = new Array("");
+abelOper["END_EQN"] = new Array("");
+
+abelOper["_I"] = new Array(".I");
+abelOper["_T"] = new Array(".T");
+abelOper["_D"] = new Array(".D");
+abelOper["_C"] = new Array(".CLK");
+abelOper["_DEC"] = new Array(".DEC");
+abelOper["_LH"] = new Array(".LH");
+abelOper["_CLR"] = new Array(".AR");
+abelOper["_PRE"] = new Array(".AP");
+abelOper["_CE"] = new Array(".CE");
+abelOper["_OE"] = new Array(".OE");
+
+abelOper["OE_START"] = new Array(" <= ");
+abelOper["OE_WHEN"] = new Array(" when ");
+abelOper["OE_EQUAL"] = new Array(" = ");
+abelOper["OE_ELSE"] = new Array(" else ");
+abelOper["B0"] = new Array("'0'");
+abelOper["B1"] = new Array("'1'");
+abelOper["BZ"] = new Array("'Z'");
+
+abelOper["FD"] = new Array(".D");
+abelOper["FT"] = new Array(".T");
+abelOper["FDD"] = new Array(".DEC");
+abelOper["FTD"] = new Array(".T");
+abelOper["LD"] = new Array(".LH");
+abelOper["Q"] = new Array(".Q");
+
+var vhdlOper = new Array();
+vhdlOper["GND"] = new Array("'0'");
+vhdlOper["VCC"] = new Array("'1'");
+vhdlOper["NOT"] = new Array(rClrS + "NOT " + rClrE);
+vhdlOper["AND"] = new Array(rClrS + "AND" + rClrE);
+vhdlOper["OR"]  = new Array(rClrS + "OR" + rClrE);
+vhdlOper["XOR"] = new Array(rClrS + "XOR" + rClrE);
+vhdlOper["EQUAL_COLON"] = new Array("<= ");
+vhdlOper["EQUAL"] = new Array("<= ");
+vhdlOper["ASSIGN"] = new Array("");
+vhdlOper["OPEN_NEGATE"] = new Array("(");
+vhdlOper["CLOSE_NEGATE"] = new Array(")");
+vhdlOper["OPEN_PTERM"] = new Array("(");
+vhdlOper["CLOSE_PTERM"] = new Array(")");
+vhdlOper["OPEN_BRACE"] = new Array("(");
+vhdlOper["CLOSE_BRACE"] = new Array(")");
+vhdlOper["INVALID_OPEN_BRACE"] = new Array("<");
+vhdlOper["INVALID_CLOSE_BRACE"] = new Array(">");
+
+vhdlOper["ENDLN"] = new Array(";");
+vhdlOper["COMMENT"] = new Array("--");
+vhdlOper["IMPORT"] = new Array("");
+vhdlOper["GCK_COM"] = new Array("GCK");
+vhdlOper["GTS_COM"] = new Array("GTS");
+vhdlOper["GSR_COM"] = new Array("GSR");
+vhdlOper["OD_COM"] = new Array("Open Drain");
+vhdlOper["START_EQN"] = new Array(rClrS + "port map" + rClrE + " (");
+vhdlOper["END_EQN"] = new Array(")");
+
+vhdlOper["_I"] = new Array("_I");
+vhdlOper["_T"] = new Array("_T");
+vhdlOper["_D"] = new Array("_D");
+vhdlOper["_C"] = new Array("_C");
+vhdlOper["_DEC"] = new Array("_C");
+vhdlOper["_LH"] = new Array("_C");
+vhdlOper["_CLR"] = new Array("_CLR");
+vhdlOper["_PRE"] = new Array("_PRE");
+vhdlOper["_CE"] = new Array("_CE");
+vhdlOper["_OE"] = new Array("_OE");
+
+vhdlOper["OE_START"] = new Array(" <= ");
+vhdlOper["OE_WHEN"] = new Array(" when ");
+vhdlOper["OE_EQUAL"] = new Array(" = ");
+vhdlOper["OE_ELSE"] = new Array(" else ");
+vhdlOper["B0"] = new Array("'0'");
+vhdlOper["B1"] = new Array("'1'");
+vhdlOper["BZ"] = new Array("'Z'");
+
+vhdlOper["FD"] = new Array("FDCPE");
+vhdlOper["FT"] = new Array("FTCPE");
+vhdlOper["FDD"] = new Array("FDDCPE");
+vhdlOper["FTD"] = new Array("FTDCPE");
+vhdlOper["LD"] = new Array("LDCP");
+vhdlOper["Q"] = new Array("");
+
+var verOper = new Array();
+verOper["GND"] = new Array("1'b0");
+verOper["VCC"] = new Array("1'b1");
+verOper["NOT"] = new Array(rClrS + "!" + rClrE);
+verOper["AND"] = new Array(rClrS + "&&" + rClrE);
+verOper["OR"]  = new Array(rClrS + "||" + rClrE);
+verOper["XOR"] = new Array(rClrS + "XOR" + rClrE);
+verOper["EQUAL_COLON"] = new Array("= ");
+verOper["EQUAL"] = new Array("= ");
+verOper["ASSIGN"] = new Array("assign ");
+verOper["OPEN_NEGATE"] = new Array("(");
+verOper["CLOSE_NEGATE"] = new Array(")");
+verOper["OPEN_PTERM"] = new Array("(");
+verOper["CLOSE_PTERM"] = new Array(")");
+verOper["OPEN_BRACE"] = new Array("[");
+verOper["CLOSE_BRACE"] = new Array("]");
+verOper["INVALID_OPEN_BRACE"] = new Array("<");
+verOper["INVALID_CLOSE_BRACE"] = new Array(">");
+
+verOper["ENDLN"] = new Array(";");
+verOper["COMMENT"] = new Array("//");
+verOper["IMPORT"] = new Array("");
+verOper["GCK_COM"] = new Array("GCK");
+verOper["GTS_COM"] = new Array("GTS");
+verOper["GSR_COM"] = new Array("GSR");
+verOper["OD_COM"] = new Array("Open Drain");
+verOper["START_EQN"] = new Array(" (");
+verOper["END_EQN"] = new Array(")");
+
+verOper["_I"] = new Array("_I");
+verOper["_T"] = new Array("_T");
+verOper["_D"] = new Array("_D");
+verOper["_C"] = new Array("_C");
+verOper["_DEC"] = new Array("_C");
+verOper["_LH"] = new Array("_C");
+verOper["_CLR"] = new Array("_CLR");
+verOper["_PRE"] = new Array("_PRE");
+verOper["_CE"] = new Array("_CE");
+verOper["_OE"] = new Array("_OE");
+
+verOper["OE_START"] = new Array(" = ");
+verOper["OE_WHEN"] = new Array(" ? ");
+verOper["OE_EQUAL"] = new Array("");
+verOper["OE_ELSE"] = new Array(" : ");
+verOper["B0"] = new Array("1'b0");
+verOper["B1"] = new Array("1'b1");
+verOper["BZ"] = new Array("1'bz");
+
+verOper["FD"] = new Array("FDCPE");
+verOper["FT"] = new Array("FTCPE");
+verOper["FDD"] = new Array("FDDCPE");
+verOper["FTD"] = new Array("FTDCPE");
+verOper["LD"] = new Array("LDCP");
+verOper["Q"] = new Array("");
+
+var operator = abelOper;
+
+var pterms = new Array();
+var d1 = new Array();
+var d2 = new Array();
+var clk = new Array();
+var set = new Array();
+var rst = new Array();
+var trst = new Array();
+var d1imp = new Array();
+var d2imp = new Array();
+var clkimp = new Array();
+var setimp = new Array();
+var rstimp = new Array();
+var trstimp = new Array();
+var gblclk = new Array();
+var gblset = new Array();
+var gblrst = new Array();
+var gbltrst = new Array();
+var ce = new Array();
+var ceimp = new Array();
+var prld = new Array();
+var specSig = new Array();
+var clkNegs = new Array();
+var setNegs = new Array();
+var rstNegs = new Array();
+var trstNegs = new Array();
+var ceNegs = new Array();
+var fbnand = new Array();
+var inreg = new Array();
+var iostyle = new Array();
+
+var dOneLit = true;
+
+function setOper(type) {
+  if      (type == "1") { operator = vhdlOper; eqnType = 1; }
+  else if (type == "2") { operator = verOper;  eqnType = 2; }
+  else                  { operator = abelOper; eqnType = 0; }
+}
+
+function isXC95() {
+  if (device.indexOf("95") != -1) return true;
+  return false;
+}
+
+function is9500() {
+  if ((device.indexOf("95") != -1) &&
+      (device.indexOf("XL") == -1) &&
+      (device.indexOf("XV") == -1)) return true;
+  return false;
+}
+
+function retSigType(s) {
+  var sigType = sigTypes[s];
+  var str = operator["Q"];
+  if (sigType == "D") str = operator["FD"];
+  else if (sigType == "T") str = operator["FT"];
+  else if (sigType.indexOf("LATCH") != -1) str = operator["LD"];
+  else if (sigType.indexOf("DDEFF") != -1) str = operator["FDD"];
+  else if (sigType.indexOf("DEFF") != -1) str =  operator["FD"];
+  else if (sigType.indexOf("DDFF") != -1) str =  operator["FDD"];
+  else if (sigType.indexOf("TDFF") != -1) str =  operator["FTD"];
+  else if (sigType.indexOf("DFF") != -1) str =   operator["FD"];
+  else if (sigType.indexOf("TFF") != -1) str =   operator["FT"];
+  return str;
+}
+
+function retSigIndex(signal) {
+  for (s=0; s<signals.length; s++) { if (signals[s] == signal) return s; }
+  return -1;
+}
+
+function retSigName(signal) {
+  var str = "";
+  if (specSig[signal]) str += specSig[signal];
+  else str += signal;
+
+  var idx1 = str.indexOf(operator["INVALID_OPEN_BRACE"]);
+  var idx2 = str.indexOf(operator["INVALID_CLOSE_BRACE"]);
+  if ((idx1 != -1) && (idx2 != -1))
+    str = str.substring(0,idx1) + operator["OPEN_BRACE"] +
+          str.substring(idx1+1,idx2) + operator["CLOSE_BRACE"] + 
+          str.substring(idx2+1,str.length);
+  return str;
+}
+
+function removePar(signal) {
+  var str = signal;
+
+  var idx = str.indexOf(operator["OPEN_BRACE"]);
+  if (idx != -1)
+    str = str.substring(0,idx) +
+          str.substring(idx+1,str.indexOf(operator["CLOSE_BRACE"]));
+
+  return str;
+}
+
+
+function isOneLiteral(str) {
+  if ((str.indexOf(operator["AND"]) != -1) ||
+      (str.indexOf(operator["OR"]) != -1) ||
+      (str.indexOf(operator["XOR"]) != -1)) return false;
+  return true;
+}
+
+function updateName(signal, index) {
+  var str;
+
+  var idx = signal.indexOf(operator["OPEN_BRACE"]);
+  if (idx != -1)
+    str = signal.substring(0,idx) +
+          index + signal.substring(idx);
+  else str = signal + index;
+
+  return str;
+}
+
+function retPterm(pt) {
+  var str = "";
+  if (!pterms[pt]) {
+    if (specSig[pt]) pt = specSig[pt];
+    return pt;
+  }
+
+  if (pterms[pt].length > 1) str += operator["OPEN_PTERM"];
+  for (p=0; p<pterms[pt].length; p++) {
+    var sig = pterms[pt][p];
+    if (sig.indexOf("xPUP_0") != -1) continue;
+    if (p>0) str += " " + operator["AND"] + " ";
+    var neg = 0;
+    if (sig.indexOf("/") != -1) {
+      sig = sig.substring(1, sig.length);
+      str += operator["NOT"];
+      neg = 1;
+    }
+
+    str += retSigName(sig);
+  }
+  if (pterms[pt].length > 1) str += operator["CLOSE_PTERM"];
+
+  return str;
+}
+
+function retFBMC(str) {
+  return str.substring(0,str.length-2) + nlStr + tabStr;
+}
+
+function retD1D2(signal) {
+  var str = "";
+
+  dOneLit = true;
+  if (d1[signal]) {
+    var currImp = "";
+    for (i=0; i<d1[signal].length; i++) {
+      if (!eqnType && d1imp[signal] && (d1imp[signal][i] == "1")) {
+        if ((currImp != retFBMC(d1[signal][i])) && 
+            (d1[signal][i].indexOf("FB") == 0))  {
+          currImp = retFBMC(d1[signal][i]);
+          str += nlStr + operator["IMPORT"] + currImp;
+        }
+      }
+      if (i>0) str += nlTabStr + operator["OR"] + spcStr;
+      str += retPterm(d1[signal][i]);
+    }
+
+    if (d2[signal]) str += nlTabStr + operator["XOR"]+ spcStr;
+  }
+
+  if (d2[signal]) {
+    var currImp = "";
+    for (i=0; i<d2[signal].length; i++) {
+      if (!eqnType && d2imp[signal] && (d2imp[signal][i] == "1")) {
+        if ((currImp != retFBMC(d2[signal][i])) && 
+            (d2[signal][i].indexOf("FB") == 0))  {
+          currImp = retFBMC(d2[signal][i]);
+          str += nlStr + operator["IMPORT"] + currImp;
+        }
+      }
+      if (i>0) str += nlTabStr + operator["OR"] + spcStr;
+      str += retPterm(d2[signal][i]);
+    }
+  }
+
+  if (str == "GND") str = operator["GND"];
+  else if (str == "VCC") str = operator["VCC"];
+  else if (!isOneLiteral(str)) {
+    dOneLit = false;
+
+    var type = retSigType(retSigIndex(signal));
+    if ((type == operator["FD"]) ||
+        (type == operator["FDD"])) type = operator["_D"];
+    else if ((type == operator["FT"]) ||
+             (type == operator["FTD"])) type = operator["_T"];
+    else if (type == operator["LD"] && eqnType) type = "_D";
+
+    var tmpStr = updateName(retSigName(signal), type);
+    tmpStr += spcStr + operator["EQUAL_COLON"];
+    var idx = retSigIndex(signal);
+    if (eqnType && sigNegs[idx] == "ON") tmpStr += operator["NOT"] + operator["OPEN_NEGATE"];
+    str = tmpStr + str;
+    if (eqnType && sigNegs[idx] == "ON") str += operator["CLOSE_NEGATE"];
+    str += operator["ENDLN"];
+  }
+
+  return str;
+}
+
+function retClk(signal) {
+  var str = "";
+
+  if (clk[signal]) {
+    if (clk[signal].length == 1) {
+      var pterm = retPterm(clk[signal][0]);
+      if (clkNegs[signal]) {
+        str += operator["NOT"];
+        if (!isOneLiteral(pterm)) str += operator["OPEN_NEGATE"];
+      }
+      str += pterm;
+      if (clkNegs[signal] && !isOneLiteral(pterm)) str += operator["CLOSE_NEGATE"];
+    }
+    else {
+      if (clkNegs[signal]) str += operator["NOT"] + operator["OPEN_NEGATE"];
+      var currImp = "";
+      for (i=0; i<clk[signal].length; i++) {
+        if (!eqnType && clkimp[signal] && (clkimp[signal][i] == "1")) {
+        if ((currImp != retFBMC(clk[signal][i])) && 
+            (clk[signal][i].indexOf("FB") == 0))  {
+            currImp = retFBMC(clk[signal][i]);
+            str += nlStr + operator["IMPORT"] + currImp;
+          }
+        }
+        if (i>0) str += nlTabStr + operator["OR"] + spcStr;
+        str += retPterm(clk[signal][i]);
+      }
+      if (clkNegs[signal]) str += operator["CLOSE_NEGATE"];
+      str += operator["ENDLN"];
+    }
+  }
+  else if (gblclk[signal]) {
+    if (gblclk[signal].length == 1) {
+      var pterm = retPterm(gblclk[signal][0]);
+      if (clkNegs[signal]) {
+        str += operator["NOT"];
+        if (!isOneLiteral(pterm)) str += operator["OPEN_NEGATE"];
+      }
+      str += pterm;
+      if (clkNegs[signal] && !isOneLiteral(pterm)) str += operator["CLOSE_NEGATE"];
+    }
+    else {
+      if (clkNegs[signal]) str += operator["NOT"] + operator["OPEN_NEGATE"];
+      for (i=0; i<gblclk[signal].length; i++) {
+        if (i>0) str += nlTabStr + operator["OR"] + spcStr;
+        str += retPterm(gblclk[signal][i]);
+      }
+      if (clkNegs[signal]) str += operator["CLOSE_NEGATE"];
+      str += operator["ENDLN"] + tabStr + cClrS +
+             operator["COMMENT"] + spcStr + operator["GCK_COM"] + cClrE;
+    }
+  }
+  else if (eqnType) str += operator["B0"];
+
+  return str;
+}
+
+function retRst(signal) {
+  var str = "";
+
+  if (rst[signal]) {
+    if (rst[signal].length == 1) {
+      var currImp;
+      if (!eqnType && rstimp[signal] && (rstimp[signal][0] == "1")) {
+        if ((currImp != retFBMC(rst[signal][i])) && 
+            (rst[signal][i].indexOf("FB") == 0))  {
+          currImp = retFBMC(rst[signal][0]);
+          str += nlStr + operator["IMPORT"] + currImp;
+        }
+      }
+      if (rstNegs[signal]) str += operator["NOT"];
+      str += retPterm(rst[signal][0]);
+    }
+    else {
+      var currImp = "";
+      if (rstNegs[signal]) str += operator["NOT"] + operator["OPEN_NEGATE"];
+      for (i=0; i<rst[signal].length; i++) {
+        if (!eqnType && rstimp[signal] && (rstimp[signal][i] == "1")) {
+        if ((currImp != retFBMC(rst[signal][i])) && 
+            (rst[signal][i].indexOf("FB") == 0))  {
+            currImp = retFBMC(rst[signal][i]);
+            str += nlStr + operator["IMPORT"] + currImp;
+          }
+        }
+        if (i>0) str += nlTabStr + operator["OR"] + spcStr;
+        str += retPterm(rst[signal][i]);
+      }
+      if (rstNegs[signal]) str += operator["CLOSE_NEGATE"];
+      str += operator["ENDLN"];
+    }
+  }
+  else if (gblrst[signal]) {
+    if (gblrst[signal].length == 1) {
+      if (rstNegs[signal]) str += operator["NOT"];
+      str += retPterm(gblrst[signal][0]);
+    }
+    else {
+      if (rstNegs[signal]) str += operator["NOT"] + operator["OPEN_NEGATE"];
+      for (i=0; i<gblrst[signal].length; i++) {
+        if (i>0) str += nlTabStr + operator["OR"] + spcStr;
+        str += retPterm(gblrst[signal][i]);
+      }
+      if (rstNegs[signal]) str += operator["CLOSE_NEGATE"];
+      str += operator["ENDLN"] + tabStr + cClrS +
+             operator["COMMENT"] + spcStr + operator["GSR_COM"] + cClrE;
+    }
+  }
+  else if (eqnType) str += operator["B0"];
+
+  return str;
+}
+
+function retSet(signal) {
+  var str = "";
+
+  if (set[signal]) {
+    if (set[signal].length == 1) {
+      var currImp = "";
+      if (!eqnType && setimp[signal] && (setimp[signal][0] == "1")) {
+        if ((currImp != retFBMC(set[signal][i])) && 
+            (set[signal][i].indexOf("FB") == 0))  {
+          currImp = retFBMC(set[signal][0]);
+          str += nlStr + operator["IMPORT"] + currImp;
+        }
+      }
+      if (setNegs[signal]) str += operator["NOT"];
+      str += retPterm(set[signal][0]);
+    }
+    else {
+      var currImp = "";
+      if (setNegs[signal]) str += operator["NOT"] + operator["OPEN_NEGATE"];
+      for (i=0; i<set[signal].length; i++) {
+        if (!eqnType && setimp[signal] && (setimp[signal][i] == "1")) {
+        if ((currImp != retFBMC(set[signal][i])) && 
+            (set[signal][i].indexOf("FB") == 0))  {
+            currImp = retFBMC(set[signal][i]);
+            str += nlStr + operator["IMPORT"] + currImp;
+          }
+        }
+        if (i>0) str += nlTabStr + operator["OR"] + spcStr;
+        str += retPterm(set[signal][i]);
+      }
+      if (setNegs[signal]) str += operator["CLOSE_NEGATE"];
+      str += operator["ENDLN"];
+    }
+  }
+  else if (gblset[signal]) {
+    if (gblset[signal].length == 1) {
+      if (setNegs[signal]) str += operator["NOT"];
+      str += retPterm(gblset[signal][0]);
+    }
+    else {
+      if (setNegs[signal]) str += operator["NOT"] + operator["OPEN_NEGATE"];
+      for (i=0; i<gblset[signal].length; i++) {
+        if (i>0) str += nlTabStr + operator["OR"] + spcStr;
+        str += retPterm(gblset[signal][i]);
+      }
+      if (setNegs[signal]) str += operator["CLOSE_NEGATE"];
+      str += operator["ENDLN"] + tabStr + cClrS +
+             operator["COMMENT"] + spcStr + operator["GSR_COM"] + cClrE;
+    }
+  }
+  else if (eqnType) str += operator["B0"];
+
+  return str;
+}
+
+function retCE(signal) {
+  var str = "";
+
+  if (ce[signal]) {
+    if (ce[signal].length == 1) {
+      var currImp = "";
+      if (!eqnType && ceimp[signal] && (ceimp[signal][0] == "1")) {
+        if ((currImp != retFBMC(ce[signal][i])) && 
+            (ce[signal][i].indexOf("FB") == 0))  {
+          currImp = retFBMC(ce[signal][0]);
+          str += nlStr + operator["IMPORT"] + currImp;
+        }
+      }
+      if (ceNegs[signal]) str += operator["NOT"];
+      str += retPterm(ce[signal][0]);
+    }
+    else {
+      var currImp = "";
+      if (ceNegs[signal]) str += operator["NOT"] + operator["OPEN_NEGATE"];
+      for (i=0; i<ce[signal].length; i++) {
+        if (!eqnType && ceimp[signal] && (ceimp[signal][i] == "1")) {
+        if ((currImp != retFBMC(ce[signal][i])) && 
+            (ce[signal][i].indexOf("FB") == 0))  {
+            currImp = retFBMC(ce[signal][i]);
+            str += nlStr + operator["IMPORT"] + currImp;
+          }
+        }
+        if (i>0) str += nlTabStr + operator["OR"] + spcStr;
+        str += retPterm(ce[signal][i]);
+      }
+      if (ceNegs[signal]) str += operator["CLOSE_NEGATE"];
+      str += operator["ENDLN"];
+    }
+  }
+  else if (eqnType) str += operator["B1"];
+
+  return str;
+}
+
+function retTrst(signal) {
+  var str = "";
+  if (trst[signal]) {
+    if (trstNegs[signal])
+      str += operator["NOT"] + operator["OPEN_NEGATE"];
+    for (i=0; i<trst[signal].length; i++) {
+      var currImp = "";
+      if (!eqnType && trstimp[signal] && (trstimp[signal][0] == "1")) {
+        if ((currImp != retFBMC(trst[signal][i])) && 
+            (trst[signal][i].indexOf("FB") == 0))  {
+          currImp = retFBMC(trst[signal][0]);
+          str += nlStr + operator["IMPORT"] + currImp;
+        }
+      }
+      if (i>0) str += nlTabStr + operator["OR"] + spcStr;
+      str += retPterm(trst[signal][i]);
+    }
+    if (trstNegs[signal]) str += operator["CLOSE_NEGATE"]; 
+  }
+  else if (gbltrst[signal]) {
+    if (trstNegs[signal])
+      str += operator["NOT"] + operator["OPEN_NEGATE"];
+    for (i=0; i<gbltrst[signal].length; i++) {
+      if (i>0) str += nlTabStr + operator["OR"] + spcStr;
+      str += retPterm(gbltrst[signal][i]);
+    }
+    if (trstNegs[signal]) str += operator["CLOSE_NEGATE"]; 
+  }
+
+  str += operator["ENDLN"];
+  return str;
+}
+
+function retEqn(signal) {
+  var str = inregStr = "";
+  var iStr = qStr = "";
+  var dStr = dEqn = "";
+  var cStr = cEqn = "";
+  var clrStr = clrEqn = "";
+  var preStr = preEqn = "";
+  var ceStr = ceEqn = "";
+  var oeStr = oeEqn = "";
+  var sigName = retSigName(signal);
+
+  var type = retSigType(retSigIndex(signal));
+
+  if (gbltrst[signal] || trst[signal]) iStr = operator["_I"];
+  if (eqnType) qStr = updateName(sigName, iStr);
+
+  if (inreg[signal]) {
+    if (!eqnType)
+      inregStr = operator["COMMENT"] + " Direct Input Register" + nlStr;
+    dStr = retSigName(inreg[signal][0]);
+  }
+  else dStr = retD1D2(signal);
+  if (eqnType && !dOneLit) {
+    dEqn = dStr;
+    dStr = dStr.substring(0,dStr.indexOf(operator["EQUAL_COLON"]));
+  }
+  else if (!eqnType) {
+    if (!dOneLit) dStr = dStr.substring(dStr.indexOf(operator["EQUAL_COLON"])+2);
+    if (sigNegs[retSigIndex(signal)] == "ON") dEqn += operator["NOT"];
+    dEqn += sigName;
+    if ((type == operator["FT"]) ||
+        (type == operator["FTD"])) dEqn += operator["_T"];
+    else if ((type == operator["FD"]) ||
+             (type == operator["FTD"])||
+             (type == operator["LD"])) dEqn += operator["_D"];
+    dEqn += " ";
+    if ((type != operator["Q"]) && (type != operator["LD"]))
+      dEqn += operator["EQUAL_COLON"];
+    else  dEqn += operator["EQUAL"];
+    dEqn += dStr;
+    if (dOneLit) {
+      dEqn += operator["ENDLN"];
+      if (iostyle[signal] && iostyle[signal].indexOf("OD"))
+        dEqn += tabStr + operator["COMMENT"] + " " + operator["OD_COM"];
+    }
+  }
+
+  cStr = retClk(signal);
+  if (eqnType && !isOneLiteral(cStr)){
+    cEqn = cStr;
+    if (cEqn.indexOf(operator["ENDLN"]) == -1)
+      cEqn += operator["ENDLN"];
+    cStr = updateName(sigName, operator["_C"]);
+  }
+  else if (!eqnType && cStr) {
+    cEqn += cStr;
+    cStr = tabStr + sigName;
+    if (type == operator["LD"]) cStr += operator["_LH"];
+    else if (type == operator["FDD"]) cStr += operator["_DEC"];
+    else                        cStr += operator["_C"];
+    if (cEqn.indexOf(operator["ENDLN"]) == -1)
+      cEqn += operator["ENDLN"];
+    if (gblclk[signal]) cEqn += tabStr + operator["COMMENT"] + " " + operator["GCK_COM"];
+  }
+
+  clrStr = retRst(signal);
+  if (eqnType && !isOneLiteral(clrStr)){
+    clrEqn = clrStr;
+    if (cEqn.indexOf(operator["ENDLN"]) == -1)
+      clrEqn += operator["ENDLN"];
+    clrStr = updateName(sigName, operator["_CLR"]);
+  }
+  else if (!eqnType && clrStr) {
+    clrEqn += clrStr;
+    clrStr = tabStr + sigName + operator["_CLR"];
+    if (clrEqn.indexOf(operator["ENDLN"]) == -1)
+      clrEqn += operator["ENDLN"];
+    if (gblrst[signal]) clrEqn += tabStr + operator["COMMENT"] + " " + operator["GSR_COM"];
+  }
+
+  preStr = retSet(signal);
+  if (eqnType && !isOneLiteral(preStr)){
+    preEqn = preStr;
+    if (cEqn.indexOf(operator["ENDLN"]) == -1)
+      preEqn += operator["ENDLN"];
+    preStr = updateName(sigName, operator["_PRE"]);
+  }
+  else if (!eqnType && preStr) {
+    preEqn += preStr;
+    preStr = tabStr + sigName + operator["_PRE"];
+    if (preEqn.indexOf(operator["ENDLN"]) == -1)
+      preEqn += operator["ENDLN"];
+    if (gblset[signal]) preEqn += tabStr + operator["COMMENT"] + " " + operator["GSR_COM"];
+  }
+
+  if (!is9500()) {
+    ceStr = retCE(signal); 
+    if (eqnType && !isOneLiteral(ceStr)){
+      ceEqn = ceStr;
+      if (cEqn.indexOf(operator["ENDLN"]) == -1)
+        ceEqn += operator["ENDLN"];
+      ceStr = updateName(sigName, operator["_CE"]);
+    }
+    else if (!eqnType && ceStr) {
+      ceEqn += ceStr;
+      ceStr = tabStr + sigName + operator["_CE"];
+      if (ceEqn.indexOf(operator["ENDLN"]) == -1)
+        ceEqn += operator["ENDLN"];
+    }
+  }
+
+  if (eqnType && gbltrst[signal]) oeEqn = retTrst(signal);
+  else if (!eqnType && (trst[signal] || gbltrst[signal])) oeEqn = retTrst(signal);
+
+  var newline = false;
+  if ((type == "") && (clrStr == "")) {
+    str += operator["ASSIGN"] + qStr + " " + operator["EQUAL"];
+    if (dOneLit) str += dStr;
+    else         str += dEqn.substring(dEqn.indexOf(operator["EQUAL"])+2);
+    if (oeEqn != "") {
+      var oeStr = updateName(sigName, operator["_OE"]);
+      if (eqnType == 1) {
+        str += nlStr + sigName + operator["OE_START"] + qStr + operator["OE_WHEN"] + oeStr +
+               operator["OE_EQUAL"] + operator["B1"] + operator["OE_ELSE"] +
+               operator["OE_EQUAL"] + operator["BZ"] + operator["ENDLN"];
+      }
+      else if (eqnType == 2) {
+        str += nlStr + operator["ASSIGN"] + sigName + operator["OE_START"] +
+               oeStr + operator["OE_WHEN"] + qStr +
+               operator["OE_ELSE"] + operator["BZ"] + operator["ENDLN"];
+      }
+      str += nlStr + operator["ASSIGN"] + oeStr + " " + operator["EQUAL"] + " " + oeEqn;
+    }
+  }
+  else {
+    if (eqnType == 1) {
+      str += type + "_" + removePar(retSigName(signal)) +
+             ": " + type + " " + operator["START_EQN"] +
+             qStr + ", " + dStr + ", " + cStr + ", " +
+             clrStr + ", " + preStr;
+      if (!is9500() && (type != operator["LD"])) str += ", " + ceStr;
+      str += operator["END_EQN"] + operator["ENDLN"];
+      newline = true;
+    }
+    else if (eqnType == 2) {
+      str += type + " " +
+             type + "_" + removePar(retSigName(signal)) +
+             operator["START_EQN"] +
+             qStr + ", " + dStr + ", " + cStr + ", " +
+             clrStr + ", " + preStr;
+      if (!is9500() && (type != operator["LD"])) str += ", " + ceStr;
+      str += operator["END_EQN"] + operator["ENDLN"];
+      newline = true;
+    }
+
+    if (dEqn != "") {
+      if (newline) str += nlStr;
+      if (inregStr) str += inregStr;
+      str += operator["ASSIGN"] + dEqn;
+    }
+
+    if (cEqn != "") {
+      if (newline || !eqnType) str += nlStr;
+      str += operator["ASSIGN"] + cStr + " " + operator["EQUAL"] + " " + cEqn;
+    }
+
+    if (clrEqn != "")  {
+      if (newline || !eqnType) str += nlStr;
+      str += operator["ASSIGN"] + clrStr + " " + operator["EQUAL"] + " " + clrEqn;
+    }
+
+
+    if (preEqn != "")  {
+      if (newline || !eqnType) str += nlStr;
+      str += operator["ASSIGN"] + preStr + " " + operator["EQUAL"] + " " + preEqn;
+    }
+
+    if (ceEqn != "")  {
+      if (newline || !eqnType) str += nlStr;
+      str += operator["ASSIGN"] + ceStr + " " + operator["EQUAL"] + " " + ceEqn;
+    }
+
+    if (oeEqn != "") {
+      if (eqnType == 1) {
+        // var oeStr = updateName(sigName, operator["_OE"]);
+        var oeStr = sigName;
+        str += nlStr + sigName + operator["OE_START"] + qStr + operator["OE_WHEN"] + oeStr +
+               operator["OE_EQUAL"] + operator["B1"] + operator["OE_ELSE"] +
+               operator["OE_EQUAL"] + operator["BZ"] + operator["ENDLN"];
+        // str += nlStr + oeStr + " " + operator["EQUAL"] + " " + oeEqn;
+      }
+      else if (eqnType == 2) {
+        // var oeStr = updateName(sigName, operator["_OE"]);
+        var oeStr = sigName;
+        str += nlStr + operator["ASSIGN"] + sigName + operator["OE_START"] + oeStr + operator["OE_WHEN"] + qStr +
+               operator["OE_ELSE"] + operator["BZ"] + operator["ENDLN"];
+        // str += nlStr + operator["ASSIGN"] + oeStr + " " + operator["EQUAL"] + " " + oeEqn;
+      }
+      else {
+        var oeStr = sigName + operator["_OE"];
+        if (gbltrst[signal])
+          oeEqn += tabStr + operator["COMMENT"] + " " + operator["GTS_COM"];
+        str += nlStr + tabStr + oeStr + " " + operator["EQUAL"] + " " + oeEqn;
+      }
+    }
+  }
+
+  if (iostyle[signal] && iostyle[signal].indexOf("OD")) {
+    if (str.indexOf("//") == -1)
+      str += tabStr + operator["COMMENT"] + " " + operator["OD_COM"];
+  }
+
+  return str;
+}
+
+function retFamily() {
+  var family = "xc9500";
+  if (device.indexOf("XC2C") != -1) {
+    if (device.indexOf("S") != -1)  family = "cr2s";
+    else                            family = "xbr";
+  }
+  else if (device.indexOf("XCR3") != -1) family = "xpla3";
+  else {
+    if (device.indexOf("XL") != -1)  family = "xc9500xl";
+    if (device.indexOf("XV") != -1)  family = "xc9500xv";
+  }
+
+  return family;
+}
+
+function retDesign() { return design; }
+
+function getPterm(pt, type) { 
+  if (type) return type + " = " + retPterm(pt);
+  return "PT" + pt.substring(pt.indexOf('_')+1,pt.length) + " = " + retPterm(pt);
+}
+
+function getPRLDName(prld) {
+  if (eqnType != 0) return prld;
+  else if (prld == "VCC") return "S";
+  return "R";
+}
+
+function retFbnand(signal) {
+  var str = operator["COMMENT"] + spcStr + "Foldback NAND";
+  str += nlStr + retSigName(signal) + spcStr + operator["EQUAL"] + spcStr;
+  for (i=0; i<fbnand[signal].length; i++) {
+    if (i>0) str += nlTabStr + operator["OR"] + spcStr;
+    str += retPterm(fbnand[signal][i]);
+  }
+
+  return str;
+}
+
+function getEqn(signal) { return retEqn(signal); }
+
+function retUimPterm(pt) {
+  var str = "";
+  if (!uimPterms[pt]) return pt;
+  for (p=0; p<uimPterms[pt].length; p++) {
+    if (p>0) str += spcStr + operator["AND"] + spcStr;
+    var sig = uimPterms[pt][p];
+    if (sig.indexOf("/") != -1) sig = sig.substring(1, sig.length);
+
+    str += retSigName(sig);
+  }
+  return str;
+}
+
+function retUimEqn(signal) {
+  var str = operator["COMMENT"] + spcStr + "FC Node" + nlStr;
+  var neg = 0;
+  if (uimSigNegs[s] == "ON") str += operator["NOT"];
+  str += retSigName(signal) + spcStr + operator["EQUAL"];
+  str += retUimPterm(signal) + ";";
+
+  return str;
+}
+
+function retLegend(url) {
+  var str = "";
+  if (!eqnType && !isXC95()) {
+    str = "Legend: " + "&lt;" + "signame" + "&gt;" + ".COMB = combinational node mapped to ";
+    str += "the same physical macrocell as the FastInput \"signal\" (not logically related)";
+  }
+  else if (eqnType) {
+    str = "Register Legend:";
+    if (is9500()) {
+      str += nlTabStr + "FDCPE (Q,D,C,CLR,PRE);";
+      str += nlTabStr + "FTCPE (Q,D,C,CLR,PRE);";
+      str += nlTabStr + "LDCP  (Q,D,G,CLR,PRE);";
+    }
+    else if (retFamily() == "xbr") {
+      str += nlTabStr + "FDCPE (Q,D,C,CLR,PRE,CE);";
+      str += nlTabStr + "FDDCPE (Q,D,C,CLR,PRE,CE);";
+      str += nlTabStr + "FTCPE (Q,D,C,CLR,PRE,CE);";
+      str += nlTabStr + "FTDCPE (Q,D,C,CLR,PRE,CE);";
+      str += nlTabStr + "LDCP  (Q,D,G,CLR,PRE);";
+    }
+    else {
+      str += nlTabStr + "FDCPE (Q,D,C,CLR,PRE,CE);";
+      str += nlTabStr + "FTCPE (Q,D,C,CLR,PRE,CE);";
+      str += nlTabStr + "LDCP  (Q,D,G,CLR,PRE);";
+    }
+  }
+  return str;
+}
+
diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/equations.gif b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/equations.gif
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diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/equations.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/equations.htm
new file mode 100644
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--- /dev/null
+++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/equations.htm
@@ -0,0 +1,13 @@
+<html>
+<head>
+  <script>
+    function init() {
+      document.open();
+      document.write(parent.leftnav.document.options.htmlStr.value);
+      document.close();
+    }
+  </script>
+</head>
+<body onload="javascript:init()">
+</body>
+</html>
diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/equationsdoc.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/equationsdoc.htm
new file mode 100644
index 0000000..e335b77
--- /dev/null
+++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/equationsdoc.htm
@@ -0,0 +1,53 @@
+<!doctype HTML public "-//W3C//DTD HTML 4.0 Frameset//EN">
+
+<html>
+
+<!--(==============================================================)-->
+<!--(Document created with RoboEditor. )============================-->
+<!--(==============================================================)-->
+
+<head>
+
+<title>Equations</title>
+
+<!--(Meta)==========================================================-->
+
+<meta name=generator content="RoboHELP by eHelp Corporation - www.ehelp.com">
+<meta name=generator-major-version content=0.1>
+<meta name=generator-minor-version content=1>
+<meta name=filetype content=kadov>
+<meta name=filetype-version content=1>
+<meta name=page-count content=1>
+<meta name=layout-height content=582>
+<meta name=layout-width content=798>
+<meta name=date content="05 1, 2002 4:30:09 PM">
+
+
+
+</head>
+
+<!--(Body)==========================================================-->
+
+
+<body>
+
+<h1>Equations</h1>
+
+<p><span style="font-size: 10pt; font-family: arial, sans-serif;">The Equations 
+ page provides a list of equations organized by signal name. <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->You 
+ can use the pulldown menu in the left-hand frame of the page to select 
+ ABEL, VHDL, or Verilog as your language of display.</span> </p>
+
+<p><img src="xml8.jpg"
+		x-maintain-ratio=TRUE
+		style="border: none;
+				width: 181px;
+				height: 448px;
+				float: none;"
+		width=181
+		height=448
+		border=0></p>
+
+</body>
+
+</html>
diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/errors.js b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/errors.js
new file mode 100644
index 0000000..9df6118
--- /dev/null
+++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/errors.js
@@ -0,0 +1,41 @@
+var infoList = new Array();
+var warnList = new Array();
+var errorList = new Array();
+
+function updateError(type) {
+  with (document.options) {
+    switch (type) {
+    case 0:
+      if (info.checked) parent.leftnav.document.options.info.value = 1;
+      else              parent.leftnav.document.options.info.value = 0;
+      break;
+
+    case 1:
+      if (warn.checked) parent.leftnav.document.options.warn.value = 1;
+      else              parent.leftnav.document.options.warn.value = 0;
+      break;
+
+    case 2:
+      if (error.checked) parent.leftnav.document.options.error.value = 1;
+      else               parent.leftnav.document.options.error.value = 0;
+      break;
+    }
+  }
+
+  parent.leftnav.showError();
+}
+
+function init() {
+  if (!document.options) return;
+  with (document.options) {
+    if (parent.leftnav.document.options.info.value == 1)  info.checked = 1;
+    else                                                  info.checked = 0;
+    if (parent.leftnav.document.options.warn.value == 1)  warn.checked = 1;
+    else                                                  warn.checked = 0;
+    if (parent.leftnav.document.options.error.value == 1) error.checked = 1;
+    else                                                  error.checked = 0;
+
+  }
+}
+
+function showError(url) { parent.leftnav.showErrorLink(url); }
diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/errors1.gif b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/errors1.gif
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diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/errors2.gif b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/errors2.gif
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diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/errorsdoc.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/errorsdoc.htm
new file mode 100644
index 0000000..460449a
--- /dev/null
+++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/errorsdoc.htm
@@ -0,0 +1,91 @@
+<!doctype HTML public "-//W3C//DTD HTML 4.0 Frameset//EN">
+
+<html>
+
+<!--(==============================================================)-->
+<!--(Document created with RoboEditor. )============================-->
+<!--(==============================================================)-->
+
+<head>
+
+<title>Errors</title>
+
+<!--(Meta)==========================================================-->
+
+<meta name=generator content="RoboHELP by eHelp Corporation - www.ehelp.com">
+<meta name=generator-major-version content=0.1>
+<meta name=generator-minor-version content=1>
+<meta name=filetype content=kadov>
+<meta name=filetype-version content=1>
+<meta name=page-count content=1>
+<meta name=layout-height content=715>
+<meta name=layout-width content=798>
+<meta name=date content="05 1, 2002 4:22:26 PM">
+
+
+
+<style>
+<!--
+p.whs1 {font-family: arial, sans-serif; font-size: 10pt;}
+p.whs2 {font-family: arial, sans-serif; font-size: 10pt;}
+p.whs3 {font-family: arial, sans-serif; font-size: 10pt;}
+
+--></style><script language="javascript" title="WebHelpInlineScript">
+<!--
+function reDo() {
+  if (innerWidth != origWidth || innerHeight != origHeight)
+     location.reload();
+}
+if ((parseInt(navigator.appVersion) == 4) && (navigator.appName == "Netscape")) {
+	origWidth = innerWidth;
+	origHeight = innerHeight;
+	onresize = reDo;
+}
+//-->
+</script><style>
+<!--
+  div.WebHelpPopupMenu {position:absolute; left:0px; top:0px; z-index:4; visibility:hidden;}
+  p.WebHelpNavBar {text-align:right;}
+-->
+</style>
+</head>
+
+<!--(Body)==========================================================-->
+
+
+<body>
+
+
+<h1>Errors/Warnings</h1>
+
+<p class="whs1">The Errors/Warnings 
+ section of the report lists all of the error, warning, and information 
+ messages generated by the fitter. By default, this section will display 
+ the number of each kind of message you have and the full text of the messages, 
+ but checkboxes at the top of the screen allow you to filter message details 
+ as you choose. </p>
+
+<p class="whs2">Checking all 
+ the boxes will give you a display like this:</p>
+
+<p><SCRIPT LANGUAGE="JavaScript"><!--
+if (navigator.appName=="Netscape")
+{ document.write("<img src='xml6.jpg' x-maintain-ratio='TRUE' width='540' height='254' border='0'>");}
+else
+{ document.write("<img src='xml6.jpg' x-maintain-ratio='TRUE' style='border: none; width: 540px; height: 254px; float: none;' width='540' height='254' border='0'>");}
+//--></SCRIPT></p>
+
+<p class="whs3">Deselecting 
+ the Warning box in this particular example would result in this less detailed 
+ display:</p>
+
+<p><SCRIPT LANGUAGE="JavaScript"><!--
+if (navigator.appName=="Netscape")
+{ document.write("<img src='xml7.jpg' x-maintain-ratio='TRUE' width='576' height='226' border='0'>");}
+else
+{ document.write("<img src='xml7.jpg' x-maintain-ratio='TRUE' style='border: none; width: 576px; height: 226px; float: none;' width='576' height='226' border='0'>");}
+//--></SCRIPT></p>
+
+</body>
+
+</html>
diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/errs.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/errs.htm
new file mode 100644
index 0000000..0fb2572
--- /dev/null
+++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/errs.htm
@@ -0,0 +1,81 @@
+<html>
+<head>
+<meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+<script src="errors.js"></script><link rel="stylesheet" type="text/css" href="style.css">
+</head>
+<body class="pgBgnd" id="XC95144XL">
+<span id="error" class="pgRef"><h3 align="center">Errors and Warnings</h3>
+<b>There are 0 error(s), 67 warning(s), and 0 information.</b><br><br><table width="90%" border="1" cellpadding="0" cellspacing="0">
+<tr><td>[Warning]:Cpld - Unable to retrieve the path to the iSE Project Repository. Will   use the default filename of 'LAN_IDE_CP.ise'.INFO:Cpld - Inferring BUFG constraint for signal 'CLK_EXT' based upon the LOC   constraint 'P30'. It is recommended that you declare this BUFG explicitedly   in your design. Note that for certain device families the output of a BUFG   constraint can not drive a gated clock, and the BUFG constraint will be   ignored.</td></tr>
+<tr><td>[Warning]:Cpld:936 - The output buffer 'SLAVE_OBUF' is missing an input and will   be deleted.</td></tr>
+<tr><td>[Warning]:Cpld:936 - The output buffer 'OWN_OBUF' is missing an input and will be   deleted.</td></tr>
+<tr><td>[Warning]:Cpld:936 - The output buffer 'OVR_OBUF' is missing an input and will be   deleted.</td></tr>
+<tr><td>[Warning]:Cpld:936 - The output buffer 'MTACK_OBUF' is missing an input and will   be deleted.</td></tr>
+<tr><td>[Warning]:Cpld:936 - The output buffer 'LAN_WRH_OBUF' is missing an input and will   be deleted.</td></tr>
+<tr><td>[Warning]:Cpld:936 - The output buffer 'LAN_RD_OBUF' is missing an input and will   be deleted.</td></tr>
+<tr><td>[Warning]:Cpld:936 - The output buffer 'LAN_EN_OBUF' is missing an input and will   be deleted.</td></tr>
+<tr><td>[Warning]:Cpld:936 - The output buffer 'LAN_CS_OBUF' is missing an input and will   be deleted.</td></tr>
+<tr><td>[Warning]:Cpld:936 - The output buffer 'LAN_CFG&lt;4&gt;_OBUF' is missing an input and   will be deleted.</td></tr>
+<tr><td>[Warning]:Cpld:936 - The output buffer 'LAN_CFG&lt;3&gt;_OBUF' is missing an input and   will be deleted.</td></tr>
+<tr><td>[Warning]:Cpld:936 - The output buffer 'LAN_CFG&lt;2&gt;_OBUF' is missing an input and   will be deleted.</td></tr>
+<tr><td>[Warning]:Cpld:936 - The output buffer 'LAN_CFG&lt;1&gt;_OBUF' is missing an input and   will be deleted.</td></tr>
+<tr><td>[Warning]:Cpld:936 - The output buffer 'INT_OUT_OBUF' is missing an input and will   be deleted.</td></tr>
+<tr><td>[Warning]:Cpld:936 - The output buffer 'CP_WE_OBUF' is missing an input and will   be deleted.</td></tr>
+<tr><td>[Warning]:Cpld:936 - The output buffer 'CP_RD_OBUF' is missing an input and will   be deleted.</td></tr>
+<tr><td>[Warning]:Cpld:936 - The output buffer 'CP_CS_OBUF' is missing an input and will   be deleted.</td></tr>
+<tr><td>[Warning]:Cpld:936 - The output buffer 'CFOUT_OBUF' is missing an input and will   be deleted.</td></tr>
+<tr><td>[Warning]:Cpld:936 - The output buffer 'A_LAN&lt;9&gt;_OBUF' is missing an input and   will be deleted.</td></tr>
+<tr><td>[Warning]:Cpld:936 - The output buffer 'A_LAN&lt;8&gt;_OBUF' is missing an input and   will be deleted.</td></tr>
+<tr><td>[Warning]:Cpld:936 - The output buffer 'A_LAN&lt;7&gt;_OBUF' is missing an input and   will be deleted.</td></tr>
+<tr><td>[Warning]:Cpld:936 - The output buffer 'A_LAN&lt;6&gt;_OBUF' is missing an input and   will be deleted.</td></tr>
+<tr><td>[Warning]:Cpld:936 - The output buffer 'A_LAN&lt;5&gt;_OBUF' is missing an input and   will be deleted.</td></tr>
+<tr><td>[Warning]:Cpld:936 - The output buffer 'A_LAN&lt;4&gt;_OBUF' is missing an input and   will be deleted.</td></tr>
+<tr><td>[Warning]:Cpld:936 - The output buffer 'A_LAN&lt;3&gt;_OBUF' is missing an input and   will be deleted.</td></tr>
+<tr><td>[Warning]:Cpld:936 - The output buffer 'A_LAN&lt;2&gt;_OBUF' is missing an input and   will be deleted.</td></tr>
+<tr><td>[Warning]:Cpld:936 - The output buffer 'A_LAN&lt;1&gt;_OBUF' is missing an input and   will be deleted.</td></tr>
+<tr><td>[Warning]:Cpld:936 - The output buffer 'A_LAN&lt;13&gt;_OBUF' is missing an input and   will be deleted.</td></tr>
+<tr><td>[Warning]:Cpld:936 - The output buffer 'A_LAN&lt;12&gt;_OBUF' is missing an input and   will be deleted.</td></tr>
+<tr><td>[Warning]:Cpld:936 - The output buffer 'A_LAN&lt;11&gt;_OBUF' is missing an input and   will be deleted.</td></tr>
+<tr><td>[Warning]:Cpld:936 - The output buffer 'A_LAN&lt;10&gt;_OBUF' is missing an input and   will be deleted.</td></tr>
+<tr><td>[Warning]:Cpld:936 - The output buffer 'A_LAN&lt;0&gt;_OBUF' is missing an input and   will be deleted.</td></tr>
+<tr><td>[Warning]:Cpld:1007 - Removing unused input(s) 'A&lt;14&gt;'.  The input(s) are unused   after optimization. Please verify functionality via simulation.</td></tr>
+<tr><td>[Warning]:Cpld:1007 - Removing unused input(s) 'A&lt;15&gt;'.  The input(s) are unused   after optimization. Please verify functionality via simulation.</td></tr>
+<tr><td>[Warning]:Cpld:1007 - Removing unused input(s) 'A&lt;7&gt;'.  The input(s) are unused   after optimization. Please verify functionality via simulation.</td></tr>
+<tr><td>[Warning]:Cpld:1007 - Removing unused input(s) 'A&lt;8&gt;'.  The input(s) are unused   after optimization. Please verify functionality via simulation.</td></tr>
+<tr><td>[Warning]:Cpld:1007 - Removing unused input(s) 'CFIN'.  The input(s) are unused   after optimization. Please verify functionality via simulation.</td></tr>
+<tr><td>[Warning]:Cpld:1007 - Removing unused input(s) 'CLK_EXT'.  The input(s) are unused   after optimization. Please verify functionality via simulation.</td></tr>
+<tr><td>[Warning]:Cpld:1007 - Removing unused input(s) 'CP_IRQ'.  The input(s) are unused   after optimization. Please verify functionality via simulation.</td></tr>
+<tr><td>[Warning]:Cpld:1007 - Removing unused input(s) 'DQ&lt;0&gt;'.  The input(s) are unused   after optimization. Please verify functionality via simulation.</td></tr>
+<tr><td>[Warning]:Cpld:1007 - Removing unused input(s) 'DQ&lt;10&gt;'.  The input(s) are unused   after optimization. Please verify functionality via simulation.</td></tr>
+<tr><td>[Warning]:Cpld:1007 - Removing unused input(s) 'DQ&lt;11&gt;'.  The input(s) are unused   after optimization. Please verify functionality via simulation.</td></tr>
+<tr><td>[Warning]:Cpld:1007 - Removing unused input(s) 'DQ&lt;12&gt;'.  The input(s) are unused   after optimization. Please verify functionality via simulation.</td></tr>
+<tr><td>[Warning]:Cpld:1007 - Removing unused input(s) 'DQ&lt;13&gt;'.  The input(s) are unused   after optimization. Please verify functionality via simulation.</td></tr>
+<tr><td>[Warning]:Cpld:1007 - Removing unused input(s) 'DQ&lt;14&gt;'.  The input(s) are unused   after optimization. Please verify functionality via simulation.</td></tr>
+<tr><td>[Warning]:Cpld:1007 - Removing unused input(s) 'DQ&lt;15&gt;'.  The input(s) are unused   after optimization. Please verify functionality via simulation.</td></tr>
+<tr><td>[Warning]:Cpld:1007 - Removing unused input(s) 'DQ&lt;1&gt;'.  The input(s) are unused   after optimization. Please verify functionality via simulation.</td></tr>
+<tr><td>[Warning]:Cpld:1007 - Removing unused input(s) 'DQ&lt;2&gt;'.  The input(s) are unused   after optimization. Please verify functionality via simulation.</td></tr>
+<tr><td>[Warning]:Cpld:1007 - Removing unused input(s) 'DQ&lt;3&gt;'.  The input(s) are unused   after optimization. Please verify functionality via simulation.</td></tr>
+<tr><td>[Warning]:Cpld:1007 - Removing unused input(s) 'DQ&lt;4&gt;'.  The input(s) are unused   after optimization. Please verify functionality via simulation.</td></tr>
+<tr><td>[Warning]:Cpld:1007 - Removing unused input(s) 'DQ&lt;5&gt;'.  The input(s) are unused   after optimization. Please verify functionality via simulation.</td></tr>
+<tr><td>[Warning]:Cpld:1007 - Removing unused input(s) 'DQ&lt;6&gt;'.  The input(s) are unused   after optimization. Please verify functionality via simulation.</td></tr>
+<tr><td>[Warning]:Cpld:1007 - Removing unused input(s) 'DQ&lt;7&gt;'.  The input(s) are unused   after optimization. Please verify functionality via simulation.</td></tr>
+<tr><td>[Warning]:Cpld:1007 - Removing unused input(s) 'DQ&lt;8&gt;'.  The input(s) are unused   after optimization. Please verify functionality via simulation.</td></tr>
+<tr><td>[Warning]:Cpld:1007 - Removing unused input(s) 'DQ&lt;9&gt;'.  The input(s) are unused   after optimization. Please verify functionality via simulation.</td></tr>
+<tr><td>[Warning]:Cpld:1007 - Removing unused input(s) 'DS0'.  The input(s) are unused   after optimization. Please verify functionality via simulation.</td></tr>
+<tr><td>[Warning]:Cpld:1007 - Removing unused input(s) 'DS1'.  The input(s) are unused   after optimization. Please verify functionality via simulation.</td></tr>
+<tr><td>[Warning]:Cpld:1007 - Removing unused input(s) 'FCS'.  The input(s) are unused   after optimization. Please verify functionality via simulation.</td></tr>
+<tr><td>[Warning]:Cpld:1007 - Removing unused input(s) 'IDE_WAIT'.  The input(s) are   unused after optimization. Please verify functionality via simulation.</td></tr>
+<tr><td>[Warning]:Cpld:1007 - Removing unused input(s) 'LAN_INT'.  The input(s) are unused   after optimization. Please verify functionality via simulation.</td></tr>
+<tr><td>[Warning]:Cpld:1007 - Removing unused input(s) 'LDS'.  The input(s) are unused   after optimization. Please verify functionality via simulation.</td></tr>
+<tr><td>[Warning]:Cpld:1007 - Removing unused input(s) 'MTCR'.  The input(s) are unused   after optimization. Please verify functionality via simulation.</td></tr>
+<tr><td>[Warning]:Cpld:1007 - Removing unused input(s) 'Z3'.  The input(s) are unused   after optimization. Please verify functionality via simulation.</td></tr>
+<tr><td>[Warning]:Cpld:896 - Unable to map all desired signals into function block, FB3,   because too many function block product terms are required. Buffering output   signal D&lt;12&gt; to allow all signals assigned to this function block to be   placed.</td></tr>
+<tr><td>[Warning]:Cpld:896 - Unable to map all desired signals into function block, FB3,   because too many function block product terms are required. Buffering output   signal D&lt;14&gt; to allow all signals assigned to this function block to be   placed.</td></tr>
+<tr><td>[Warning]:Cpld:896 - Unable to map all desired signals into function block, FB3,   because too many function block product terms are required. Buffering output   signal D&lt;13&gt; to allow all signals assigned to this function block to be   placed.</td></tr>
+<tr><td>[Warning]:Cpld:896 - Unable to map all desired signals into function block, FB3,   because too many function block product terms are required. Buffering output   signal D&lt;15&gt; to allow all signals assigned to this function block to be   placed.</td></tr>
+</table></span><form><span class="pgRef"><table width="90%" align="center"><tr>
+<td align="left"><input type="button" onclick="javascript:parent.leftnav.showTop()" onmouseover="window.status='goto top of page'; return true;" onmouseout="window.status=''" value="back to top"></td>
+<td align="right"><input type="button" onclick="window.print()" onmouseover="window.status='print page'; return true;" onmouseout="window.status=''" value="print page"></td>
+</tr></table></span></form>
+</body>
+</html>
diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/failtable.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/failtable.htm
new file mode 100644
index 0000000..ed152cf
--- /dev/null
+++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/failtable.htm
@@ -0,0 +1,42 @@
+<html>
+<head>
+<meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+<script src="maplogic.js"></script><link rel="stylesheet" type="text/css" href="style.css">
+</head>
+<body class="pgBgnd">
+<h3 align="center">Failure Table</h3>
+<table width="90%" border="1" cellpadding="0" cellspacing="0">
+<tr class="pgHeader">
+<th align="left">Signal Name</th>
+<th align="left">FB1</th>
+<th align="left">FB2</th>
+<th align="left">FB3</th>
+<th align="left">FB4</th>
+</tr>
+<tr class="pgHeader">
+<th align="left">Signal Name</th>
+<th align="left">FB5</th>
+<th align="left">FB6</th>
+<th align="left">FB7</th>
+<th align="left">FB8</th>
+</tr>
+</table>
+<table width="90%" border="1" cellpadding="0" cellspacing="0"><table width="90%" border="1" cellpadding="0" cellspacing="0">
+<tr><td>Legend:</td></tr>
+<tr><td>       ce  - signal clock enable cannot be placed</td></tr>
+<tr><td>       clk - signal clock cannot be placed</td></tr>
+<tr><td>       fbi - insufficient function block inputs available to place signal</td></tr>
+<tr><td>       io  - insufficient I/O pins available to place output</td></tr>
+<tr><td>       loc - signal cannot be placed in this FB because it is assigned to a different FB</td></tr>
+<tr><td>       mc  - insufficient macrocells available to place signal</td></tr>
+<tr><td>       oe  - signal output enable cannot be placed</td></tr>
+<tr><td>       pt  - insufficient product terms available to place signal</td></tr>
+<tr><td>       sr  - signal set/reset cannot be placed</td></tr>
+<tr><td>       unk - unknown reason for failure - Please contact Xilinx Support</td></tr>
+</table></table>
+</body>
+<form><span class="pgRef"><table width="90%" align="center"><tr>
+<td align="left"><input type="button" onclick="javascript:parent.leftnav.showTop()" onmouseover="window.status='goto top of page'; return true;" onmouseout="window.status=''" value="back to top"></td>
+<td align="right"><input type="button" onclick="window.print()" onmouseover="window.status='print page'; return true;" onmouseout="window.status=''" value="print page"></td>
+</tr></table></span></form>
+</html>
diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/failtable.js b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/failtable.js
new file mode 100644
index 0000000..045081f
--- /dev/null
+++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/failtable.js
@@ -0,0 +1 @@
+function showFailTable() { parent.leftnav.showFailTable(); }
diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/failtabledoc.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/failtabledoc.htm
new file mode 100644
index 0000000..c95037a
--- /dev/null
+++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/failtabledoc.htm
@@ -0,0 +1,95 @@
+<!doctype html public "-//w3c//dtd html 4.0 transitional//en">
+<html>
+<head>
+   <meta http-equiv="Content-Type" content="text/html; charset=iso-8859-1">
+   <meta name="generator" content="RoboHELP by eHelp Corporation - www.ehelp.com">
+   <meta name="generator-major-version" content="0.1">
+   <meta name="generator-minor-version" content="1">
+   <meta name="filetype" content="kadov">
+   <meta name="filetype-version" content="1">
+   <meta name="page-count" content="1">
+   <meta name="layout-height" content="1506">
+   <meta name="layout-width" content="639">
+   <meta name="date" content="05 24, 2002 5:49:09 PM">
+   <meta name="GENERATOR" content="Mozilla/4.79 [en]C-CCK-MCD   (Windows NT 5.0; U) [Netscape]">
+   <meta name="Author" content="gitu jain">
+   <title>Failure Table</title>
+<!--(==============================================================)-->
+<!--(Document created with RoboEditor. )============================-->
+<!--(==============================================================)-->
+<!--(Meta)==========================================================-->
+<style>
+<!--
+ul.whs1 {list-style: disc;}
+p.whs2 {margin-left: 80px;}
+ul.whs3 {list-style: disc;}
+p.whs4 {margin-left: 80px; font-family: arial, sans-serif; font-size: 10pt;}
+ul.whs5 {list-style: disc;}
+p.whs6 {margin-left: 80px; font-family: arial, sans-serif; font-size: 10pt;}
+p.whs7 {margin-left: 80px; font-family: arial, sans-serif; font-size: 10pt;}
+ul.whs8 {list-style: disc;}
+p.whs9 {margin-left: 80px; font-family: arial, sans-serif; font-size: 10pt;}
+p.whs10 {margin-left: 80px; font-family: arial, sans-serif; font-size: 10pt;}
+ul.whs11 {list-style: disc;}
+
+--></style>
+<script language="javascript" title="WebHelpInlineScript">
+<!--
+function reDo() {
+  if (innerWidth != origWidth || innerHeight != origHeight)
+     location.reload();
+}
+if ((parseInt(navigator.appVersion) == 4) && (navigator.appName == "Netscape")) {
+	origWidth = innerWidth;
+	origHeight = innerHeight;
+	onresize = reDo;
+}
+//-->
+</script>
+<style>
+<!--
+  div.WebHelpPopupMenu {position:absolute; left:0px; top:0px; z-index:4; visibility:hidden;}
+  p.WebHelpNavBar {text-align:right;}
+-->
+</style>
+<!--(Body)==========================================================-->
+</head>
+<body>
+
+<h1>
+Failure Table</h1>
+<span style="font-family: arial, sans-serif; font-size: 10pt;"><font size=-1>The
+Failure Table section provides a table listing all logic failing to be
+placed as well as the cause for failure to fit for each individual Function
+Block. </font>The user can use this table to determine primary cause of
+failure and try to correct it.</span><!--begin!kadov{{-->
+<br><!--}}end!kadov--><!--kadov_tag{{<implicit_p>}}--><!--begin!kadov{{-->
+<br><!--}}end!kadov--><!--kadov_tag{{<implicit_p>}}--><span 
+ style="font-family: arial, sans-serif; font-size: 10pt;"><font size=-1>The
+Failure Table contains the following:&nbsp;</font></span>
+<ul type="disc" class="whs1">
+<li class="kadov-p" class="kadov-p">
+<span style="font-family: arial, sans-serif; font-size: 10pt;"><font size=-1>The
+signal name&nbsp;</font></span></li>
+</ul>
+
+<div class="whs2"><span style="font-weight: bold;
+											font-family: arial, sans-serif;
+											font-size: 10pt;"><font size=-1><b>Note:</span><span 
+ style="font-family: arial, sans-serif; font-size: 10pt;"></b>
+Clicking on the signal name will open a new window with the equations for
+that signal.&nbsp;</font></span></div>
+
+<ul type="disc" class="whs3">
+<li class="kadov-p" class="kadov-p">
+<span style="font-family: arial, sans-serif; font-size: 10pt;"><font size=-1>A
+column for each Function Block in device, with reason for failure to fit
+for each FB</font></span></li>
+
+<li class="kadov-p" class="kadov-p">
+<span style="font-family: arial, sans-serif; font-size: 10pt;"><font size=-1>A
+legend at the bottom listing all possible reasons for failure</font></span></li>
+</ul>
+
+</body>
+</html>
diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/fb.gif b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/fb.gif
new file mode 100644
index 0000000..9783d6a
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diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/fb1.gif b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/fb1.gif
new file mode 100644
index 0000000..5d8b734
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diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/fbs.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/fbs.htm
new file mode 100644
index 0000000..f20c18c
--- /dev/null
+++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/fbs.htm
@@ -0,0 +1,77 @@
+<html>
+<head>
+<meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+<script src="fbs.js"></script><link rel="stylesheet" type="text/css" href="style.css">
+</head>
+<body class="pgBgnd" id="XC95144XL">
+<span id="fbsum" class="pgRef"><h3 align="center">Function Blocks</h3>
+<table align="center" width="90%" border="1" cellpadding="0" cellspacing="0">
+<tr class="pgHeader">
+<th>Function Block</th>
+<th>Macrocells Used/Total</th>
+<th>Function Block Inputs Used/Total</th>
+<th>Product Terms Used/Total</th>
+<th>Pins Used/Total</th>
+</tr>
+<tr>
+<td align="center"><a href="javascript:showFBDetail('FB1');" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB1</a></td>
+<td align="center">16 / 18</td>
+<td align="center">24 / 54</td>
+<td align="center">40 / 90</td>
+<td align="center">13 / 15</td>
+</tr>
+<tr>
+<td align="center"><a href="javascript:showFBDetail('FB2');" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB2</a></td>
+<td align="center">11 / 18</td>
+<td align="center">24 / 54</td>
+<td align="center">56 / 90</td>
+<td align="center">4 / 15</td>
+</tr>
+<tr>
+<td align="center"><a href="javascript:showFBDetail('FB3');" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB3</a></td>
+<td align="center">12 / 18</td>
+<td align="center">24 / 54</td>
+<td align="center">25 / 90</td>
+<td align="center">11 / 15</td>
+</tr>
+<tr>
+<td align="center"><a href="javascript:showFBDetail('FB4');" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB4</a></td>
+<td align="center">3 / 18</td>
+<td align="center">24 / 54</td>
+<td align="center">25 / 90</td>
+<td align="center">0 / 15</td>
+</tr>
+<tr>
+<td align="center"><a href="javascript:showFBDetail('FB5');" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB5</a></td>
+<td align="center">7 / 18</td>
+<td align="center">23 / 54</td>
+<td align="center">19 / 90</td>
+<td align="center">10 / 14</td>
+</tr>
+<tr>
+<td align="center"><a href="javascript:showFBDetail('FB6');" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB6</a></td>
+<td align="center">1 / 18</td>
+<td align="center">15 / 54</td>
+<td align="center">14 / 90</td>
+<td align="center">0 / 13</td>
+</tr>
+<tr>
+<td align="center"><a href="javascript:showFBDetail('FB7');" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB7</a></td>
+<td align="center">1 / 18</td>
+<td align="center">0 / 54</td>
+<td align="center">0 / 90</td>
+<td align="center">8 / 15</td>
+</tr>
+<tr>
+<td align="center"><a href="javascript:showFBDetail('FB8');" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB8</a></td>
+<td align="center">0 / 18</td>
+<td align="center">0 / 54</td>
+<td align="center">0 / 90</td>
+<td align="center">8 / 15</td>
+</tr>
+</table></span><form><span class="pgRef"><table width="90%" align="center"><tr>
+<td align="left"><input type="button" onclick="javascript:parent.leftnav.showTop()" onmouseover="window.status='goto top of page'; return true;" onmouseout="window.status=''" value="back to top"></td>
+<td align="right"><input type="button" onclick="window.print()" onmouseover="window.status='print page'; return true;" onmouseout="window.status=''" value="print page"></td>
+</tr></table></span></form>
+</body>
+</html>
diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/fbs.js b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/fbs.js
new file mode 100644
index 0000000..8e97ea6
--- /dev/null
+++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/fbs.js
@@ -0,0 +1,9 @@
+function showFBApplet(fb) { parent.leftnav.showAppletFB(fb); }
+function showFB(fb) { parent.leftnav.showFB(fb); }
+function showMC(mc) { parent.leftnav.showAppletMC(mc); }
+function showPT(pterm, type) { parent.leftnav.showPterm(pterm, type); }
+function showPin(pin) { parent.leftnav.showAppletPin(pin); }
+function showEqn(sig) { parent.leftnav.showEqn(sig); }
+function showFBDetail(fb) { parent.leftnav.showFB(fb); }
+function showLegend(url) { parent.leftnav.showLegend(url, 650, 350); }
+function showTop() { parent.leftnav.showTop(); }
diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/fbs_FB1.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/fbs_FB1.htm
new file mode 100644
index 0000000..319a21e
--- /dev/null
+++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/fbs_FB1.htm
@@ -0,0 +1,260 @@
+<html>
+<head>
+<meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+<script src="tooltips.js"></script><script src="fbs.js"></script><link rel="stylesheet" type="text/css" href="style.css">
+</head>
+<body class="pgBgnd" id="XC95144XL">
+<span id="fbsel" class="pgRef"><table cellspacing="0" cellpadding="0" border="0" width="90%" align="center"><tr>
+<td width="33%" valign="center" align="left"></td>
+<td width="33%" valign="center" align="center"><form name="fbopt"><select onchange="javascript:showFB(document.fbopt.fbType.options[document.fbopt.fbType.options.selectedIndex].value)" name="fbType"><option value="FB1" selected>FB1</option>
+<option value="FB2">FB2</option>
+<option value="FB3">FB3</option>
+<option value="FB4">FB4</option>
+<option value="FB5">FB5</option>
+<option value="FB6">FB6</option>
+<option value="FB7">FB7</option>
+<option value="FB8">FB8</option></select></form></td>
+<td width="33%" valign="center" align="right"></td>
+</tr></table></span><div><span id="fbdata" class="pgRef"><table align="center" width="90%" border="1" cellpadding="0" cellspacing="0">
+<tr class="pgHeader">
+<th width="10%">Signal Name</th>
+<th width="10%">Total Product Terms</th>
+<th width="30%">Product Terms</th>
+<th width="10%">Location</th>
+<th width="10%">Power Mode</th>
+<th width="10%">Pin Number</th>
+<th width="10%">PinType</th>
+<th width="10%">Pin Use</th>
+</tr>
+<tr>
+<td align="center" width="10%"><a href="Javascript:showEqn('IDE_CS1_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">IDE_CS&lt;1&gt;</a></td>
+<td align="center" width="10%">1</td>
+<td align="center" width="30%"> <a href="Javascript:showPT('FB1_2_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">2_2</a>
+</td>
+<td align="center" width="10%">MC1</td>
+<td align="center" width="10%">STD</td>
+<td align="center" width="10%">23</td>
+<td width="8%" align="center">I/O</td>
+<td align="center" width="10%">O</td>
+</tr>
+<tr>
+<td align="center" width="10%"><a href="Javascript:showEqn('D7_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">D&lt;7&gt;</a></td>
+<td align="center" width="10%">1</td>
+<td align="center" width="30%"> <a href="Javascript:showPT('FB1_2_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">2_1</a> <a href="Javascript:showPT('VCC')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''"></a>
+</td>
+<td align="center" width="10%">MC2</td>
+<td align="center" width="10%">STD</td>
+<td align="center" width="10%">16</td>
+<td width="8%" align="center">I/O</td>
+<td align="center" width="10%">O</td>
+</tr>
+<tr>
+<td align="center" width="10%"><a href="Javascript:showEqn('D1_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">D&lt;1&gt;</a></td>
+<td align="center" width="10%">1</td>
+<td align="center" width="30%"> <a href="Javascript:showPT('FB1_3_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">3_1</a> <a href="Javascript:showPT('VCC')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''"></a>
+</td>
+<td align="center" width="10%">MC3</td>
+<td align="center" width="10%">STD</td>
+<td align="center" width="10%">17</td>
+<td width="8%" align="center">I/O</td>
+<td align="center" width="10%">O</td>
+</tr>
+<tr>
+<td align="center" width="10%"><a href="Javascript:showEqn('IDE_A2_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">IDE_A&lt;2&gt;</a></td>
+<td align="center" width="10%">1</td>
+<td align="center" width="30%"> <a href="Javascript:showPT('FB1_4_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">4_1</a>
+</td>
+<td align="center" width="10%">MC4</td>
+<td align="center" width="10%">STD</td>
+<td align="center" width="10%">25</td>
+<td width="8%" align="center">I/O</td>
+<td align="center" width="10%">O</td>
+</tr>
+<tr>
+<td align="center" width="10%"><a href="Javascript:showEqn('D8_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">D&lt;8&gt;</a></td>
+<td align="center" width="10%">1</td>
+<td align="center" width="30%"> <a href="Javascript:showPT('FB1_5_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">5_1</a> <a href="Javascript:showPT('VCC')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''"></a>
+</td>
+<td align="center" width="10%">MC5</td>
+<td align="center" width="10%">STD</td>
+<td align="center" width="10%">19</td>
+<td width="8%" align="center">I/O</td>
+<td align="center" width="10%">I/O</td>
+</tr>
+<tr>
+<td align="center" width="10%"><a href="Javascript:showEqn('D5_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">D&lt;5&gt;</a></td>
+<td align="center" width="10%">1</td>
+<td align="center" width="30%"> <a href="Javascript:showPT('FB1_6_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">6_1</a> <a href="Javascript:showPT('VCC')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''"></a>
+</td>
+<td align="center" width="10%">MC6</td>
+<td align="center" width="10%">STD</td>
+<td align="center" width="10%">20</td>
+<td width="8%" align="center">I/O</td>
+<td align="center" width="10%">O</td>
+</tr>
+<tr>
+<td align="center" width="10%"><a href="Javascript:showEqn('AUTOCONFIG_IN_PROGRESS')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">AUTOCONFIG_IN_PROGRESS</a></td>
+<td align="center" width="10%">2</td>
+<td align="center" width="30%"> <a href="Javascript:showPT('FB1_7_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">7_1</a> <a href="Javascript:showPT('FB1_7_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">7_2</a>
+</td>
+<td align="center" width="10%">MC7</td>
+<td align="center" width="10%">STD</td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%">(b)</td>
+<td align="center" width="10%">(b)</td>
+</tr>
+<tr>
+<td align="center" width="10%"><a href="Javascript:showEqn('D4_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">D&lt;4&gt;</a></td>
+<td align="center" width="10%">1</td>
+<td align="center" width="30%"> <a href="Javascript:showPT('FB1_8_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">8_1</a> <a href="Javascript:showPT('VCC')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''"></a>
+</td>
+<td align="center" width="10%">MC8</td>
+<td align="center" width="10%">STD</td>
+<td align="center" width="10%">21</td>
+<td width="8%" align="center">I/O</td>
+<td align="center" width="10%">O</td>
+</tr>
+<tr>
+<td align="center" width="10%"><a href="Javascript:showEqn('IDE_CS0_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">IDE_CS&lt;0&gt;</a></td>
+<td align="center" width="10%">1</td>
+<td align="center" width="30%"> <a href="Javascript:showPT('FB1_9_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">9_1</a>
+</td>
+<td align="center" width="10%">MC9</td>
+<td align="center" width="10%">STD</td>
+<td align="center" width="10%">22</td>
+<td width="8%" align="center">I/O</td>
+<td align="center" width="10%">O</td>
+</tr>
+<tr>
+<td align="center" width="10%"><a href="Javascript:showEqn('IDE_ENABLE')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">IDE_ENABLE</a></td>
+<td align="center" width="10%">3</td>
+<td align="center" width="30%"> <a href="Javascript:showPT('FB1_10_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">10_1</a> <a href="Javascript:showPT('FB1_10_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">10_2</a> <a href="Javascript:showPT('FB1_10_3')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">10_3</a>
+</td>
+<td align="center" width="10%">MC10</td>
+<td align="center" width="10%">STD</td>
+<td align="center" width="10%">31</td>
+<td width="8%" align="center">I/O</td>
+<td align="center" width="10%">(b)</td>
+</tr>
+<tr>
+<td align="center" width="10%"><a href="Javascript:showEqn('IDE_A0_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">IDE_A&lt;0&gt;</a></td>
+<td align="center" width="10%">1</td>
+<td align="center" width="30%"> <a href="Javascript:showPT('FB1_11_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">11_1</a>
+</td>
+<td align="center" width="10%">MC11</td>
+<td align="center" width="10%">STD</td>
+<td align="center" width="10%">24</td>
+<td width="8%" align="center">I/O</td>
+<td align="center" width="10%">O</td>
+</tr>
+<tr>
+<td align="center" width="10%"><a href="Javascript:showEqn('IDE_A1_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">IDE_A&lt;1&gt;</a></td>
+<td align="center" width="10%">1</td>
+<td align="center" width="30%"> <a href="Javascript:showPT('FB1_12_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">12_1</a>
+</td>
+<td align="center" width="10%">MC12</td>
+<td align="center" width="10%">STD</td>
+<td align="center" width="10%">26</td>
+<td width="8%" align="center">I/O</td>
+<td align="center" width="10%">O</td>
+</tr>
+<tr>
+<td align="center" width="10%">(unused)</td>
+<td align="center" width="10%">0</td>
+<td align="center" width="30%"> </td>
+<td align="center" width="10%">MC13</td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%">(b)</td>
+<td align="center" width="10%"> </td>
+</tr>
+<tr>
+<td align="center" width="10%"><a href="Javascript:showEqn('IDE_R')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">IDE_R</a></td>
+<td align="center" width="10%">2</td>
+<td align="center" width="30%"> <a href="Javascript:showPT('FB1_14_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">14_1</a> <a href="Javascript:showPT('FB1_14_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">14_2</a>
+</td>
+<td align="center" width="10%">MC14</td>
+<td align="center" width="10%">STD</td>
+<td align="center" width="10%">27</td>
+<td width="8%" align="center">I/O</td>
+<td align="center" width="10%">O</td>
+</tr>
+<tr>
+<td align="center" width="10%"><a href="Javascript:showEqn('IDE_W')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">IDE_W</a></td>
+<td align="center" width="10%">2</td>
+<td align="center" width="30%"> <a href="Javascript:showPT('FB1_15_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">15_1</a> <a href="Javascript:showPT('FB1_15_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">15_2</a>
+</td>
+<td align="center" width="10%">MC15</td>
+<td align="center" width="10%">STD</td>
+<td align="center" width="10%">28</td>
+<td width="8%" align="center">I/O</td>
+<td align="center" width="10%">O</td>
+</tr>
+<tr>
+<td align="center" width="10%"><a href="Javascript:showEqn('ROM_OE')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">ROM_OE</a></td>
+<td align="center" width="10%">2</td>
+<td align="center" width="30%"> <a href="Javascript:showPT('FB1_15_3')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">15_3</a> <a href="Javascript:showPT('FB1_16_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">16_1</a>
+</td>
+<td align="center" width="10%">MC16</td>
+<td align="center" width="10%">STD</td>
+<td align="center" width="10%">35</td>
+<td width="8%" align="center">I/O</td>
+<td align="center" width="10%">O</td>
+</tr>
+<tr>
+<td align="center" width="10%">(unused)</td>
+<td align="center" width="10%">0</td>
+<td align="center" width="30%"> </td>
+<td align="center" width="10%">MC17</td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%">30</td>
+<td width="8%" align="center">I/O/GCK1</td>
+<td align="center" width="10%">(b)</td>
+</tr>
+<tr>
+<td align="center" width="10%"><a href="Javascript:showEqn('D12_BUFR_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">D&lt;12&gt;_BUFR</a></td>
+<td align="center" width="10%">19</td>
+<td align="center" width="30%"> <a href="Javascript:showPT('FB1_16_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">16_2</a> <a href="Javascript:showPT('FB1_16_3')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">16_3</a> <a href="Javascript:showPT('FB1_16_4')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">16_4</a> <a href="Javascript:showPT('FB1_16_5')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">16_5</a> <a href="Javascript:showPT('FB1_17_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">17_1</a> <a href="Javascript:showPT('FB1_17_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">17_2</a> <a href="Javascript:showPT('FB1_17_3')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">17_3</a> <a href="Javascript:showPT('FB1_17_4')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">17_4</a> <a href="Javascript:showPT('FB1_17_5')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">17_5</a> <a href="Javascript:showPT('FB1_18_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">18_1</a> <a href="Javascript:showPT('FB1_18_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">18_2</a> <a href="Javascript:showPT('FB1_18_3')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">18_3</a> <a href="Javascript:showPT('FB1_18_4')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">18_4</a> <a href="Javascript:showPT('FB1_18_5')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">18_5</a> <a href="Javascript:showPT('FB1_1_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">1_1</a> <a href="Javascript:showPT('FB1_1_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">1_2</a> <a href="Javascript:showPT('FB1_1_3')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">1_3</a> <a href="Javascript:showPT('FB1_1_4')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">1_4</a> <a href="Javascript:showPT('FB1_1_5')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">1_5</a>
+</td>
+<td align="center" width="10%">MC18</td>
+<td align="center" width="10%">STD</td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%">(b)</td>
+<td align="center" width="10%">(b)</td>
+</tr>
+</table></span></div>
+<div id="tipBox"></div>
+<br><span id="fbsiguse" class="pgRef"><b>Signals Used By Logic in Function Block</b><br><ol>
+<li>AS</li>
+<li>AUTOBOOT_OFF</li>
+<li><a href="Javascript:showEqn('AUTOCONFIG_IN_PROGRESS')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">AUTOCONFIG_IN_PROGRESS</a></li>
+<li><a href="Javascript:showEqn('AUTO_CONFIG_DONE0_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">AUTO_CONFIG_DONE&lt;0&gt;</a></li>
+<li><a href="Javascript:showEqn('AUTO_CONFIG_DONE1_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">AUTO_CONFIG_DONE&lt;1&gt;</a></li>
+<li><a href="Javascript:showEqn('AUTO_CONFIG_DONE2_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">AUTO_CONFIG_DONE&lt;2&gt;</a></li>
+<li>A&lt;12&gt;</li>
+<li>A&lt;13&gt;</li>
+<li>A&lt;1&gt;</li>
+<li>A&lt;2&gt;</li>
+<li>A&lt;3&gt;</li>
+<li>A&lt;4&gt;</li>
+<li>A&lt;5&gt;</li>
+<li>A&lt;6&gt;</li>
+<li><a href="Javascript:showEqn('D12_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">D&lt;12&gt;</a></li>
+<li>A&lt;9&gt;</li>
+<li>A&lt;10&gt;</li>
+<li>A&lt;11&gt;</li>
+<li><a href="Javascript:showEqn('IDE_ENABLE')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">IDE_ENABLE</a></li>
+<li>RESET</li>
+<li>RW</li>
+<li><a href="Javascript:showEqn('autoconfig')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">autoconfig</a></li>
+<li><a href="Javascript:showEqn('ide')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">ide</a></li>
+<li><a href="Javascript:showEqn('ideide_CLKF_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">ide/ide_CLKF</a></li>
+</ol></span><form><span class="pgRef"><table width="90%" align="center"><tr>
+<td align="left"><input type="button" onclick="javascript:parent.leftnav.showTop()" onmouseover="window.status='goto top of page'; return true;" onmouseout="window.status=''" value="back to top"></td>
+<td align="center"><table align="center" width="90%" border="0" cellpadding="0" cellspacing="0"><tr><td width="100%" align="center"><input type="button" onclick="javascript:showFB('FB2')" onmouseover="window.status='show next Function Block'; return true;" onmouseout="window.status=''" value="next"></td></tr></table></td>
+<td align="right">
+<input type="button" onclick="javascript:showLegend('logiclegend.htm')" onmouseover="window.status='show Legend'; return true;" onmouseout="window.status=''" value="legend"><input type="button" onclick="window.print()" onmouseover="window.status='print page'; return true;" onmouseout="window.status=''" value="print page">
+</td>
+</tr></table></span></form>
+</body>
+</html>
diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/fbs_FB2.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/fbs_FB2.htm
new file mode 100644
index 0000000..ab9109a
--- /dev/null
+++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/fbs_FB2.htm
@@ -0,0 +1,259 @@
+<html>
+<head>
+<meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+<script src="tooltips.js"></script><script src="fbs.js"></script><link rel="stylesheet" type="text/css" href="style.css">
+</head>
+<body class="pgBgnd" id="XC95144XL">
+<span id="fbsel" class="pgRef"><table cellspacing="0" cellpadding="0" border="0" width="90%" align="center"><tr>
+<td width="33%" valign="center" align="left"></td>
+<td width="33%" valign="center" align="center"><form name="fbopt"><select onchange="javascript:showFB(document.fbopt.fbType.options[document.fbopt.fbType.options.selectedIndex].value)" name="fbType"><option value="FB1">FB1</option>
+<option value="FB2" selected>FB2</option>
+<option value="FB3">FB3</option>
+<option value="FB4">FB4</option>
+<option value="FB5">FB5</option>
+<option value="FB6">FB6</option>
+<option value="FB7">FB7</option>
+<option value="FB8">FB8</option></select></form></td>
+<td width="33%" valign="center" align="right"></td>
+</tr></table></span><div><span id="fbdata" class="pgRef"><table align="center" width="90%" border="1" cellpadding="0" cellspacing="0">
+<tr class="pgHeader">
+<th width="10%">Signal Name</th>
+<th width="10%">Total Product Terms</th>
+<th width="30%">Product Terms</th>
+<th width="10%">Location</th>
+<th width="10%">Power Mode</th>
+<th width="10%">Pin Number</th>
+<th width="10%">PinType</th>
+<th width="10%">Pin Use</th>
+</tr>
+<tr>
+<td align="center" width="10%"><a href="Javascript:showEqn('D14_BUFR_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">D&lt;14&gt;_BUFR</a></td>
+<td align="center" width="10%">18</td>
+<td align="center" width="30%"> <a href="Javascript:showPT('FB2_18_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">18_1</a> <a href="Javascript:showPT('FB2_18_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">18_2</a> <a href="Javascript:showPT('FB2_18_3')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">18_3</a> <a href="Javascript:showPT('FB2_18_4')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">18_4</a> <a href="Javascript:showPT('FB2_18_5')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">18_5</a> <a href="Javascript:showPT('FB2_1_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">1_1</a> <a href="Javascript:showPT('FB2_1_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">1_2</a> <a href="Javascript:showPT('FB2_1_3')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">1_3</a> <a href="Javascript:showPT('FB2_1_4')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">1_4</a> <a href="Javascript:showPT('FB2_1_5')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">1_5</a> <a href="Javascript:showPT('FB2_2_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">2_1</a> <a href="Javascript:showPT('FB2_2_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">2_2</a> <a href="Javascript:showPT('FB2_2_3')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">2_3</a> <a href="Javascript:showPT('FB2_2_4')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">2_4</a> <a href="Javascript:showPT('FB2_2_5')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">2_5</a> <a href="Javascript:showPT('FB2_3_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">3_1</a> <a href="Javascript:showPT('FB2_3_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">3_2</a> <a href="Javascript:showPT('FB2_3_3')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">3_3</a>
+</td>
+<td align="center" width="10%">MC1</td>
+<td align="center" width="10%">STD</td>
+<td align="center" width="10%">142</td>
+<td width="8%" align="center">I/O</td>
+<td align="center" width="10%">(b)</td>
+</tr>
+<tr>
+<td align="center" width="10%">(unused)</td>
+<td align="center" width="10%">0</td>
+<td align="center" width="30%"> </td>
+<td align="center" width="10%">MC2</td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%">143</td>
+<td width="8%" align="center">I/O/GSR</td>
+<td align="center" width="10%">GSR/I</td>
+</tr>
+<tr>
+<td align="center" width="10%">(unused)</td>
+<td align="center" width="10%">0</td>
+<td align="center" width="30%"> </td>
+<td align="center" width="10%">MC3</td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%">(b)</td>
+<td align="center" width="10%">(b)</td>
+</tr>
+<tr>
+<td align="center" width="10%">(unused)</td>
+<td align="center" width="10%">0</td>
+<td align="center" width="30%"> </td>
+<td align="center" width="10%">MC4</td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%">4</td>
+<td width="8%" align="center">I/O</td>
+<td align="center" width="10%"> </td>
+</tr>
+<tr>
+<td align="center" width="10%"><a href="Javascript:showEqn('D0_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">D&lt;0&gt;</a></td>
+<td align="center" width="10%">1</td>
+<td align="center" width="30%"> <a href="Javascript:showPT('FB2_5_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">5_1</a> <a href="Javascript:showPT('VCC')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''"></a>
+</td>
+<td align="center" width="10%">MC5</td>
+<td align="center" width="10%">STD</td>
+<td align="center" width="10%">2</td>
+<td width="8%" align="center">I/O/GTS3</td>
+<td align="center" width="10%">O</td>
+</tr>
+<tr>
+<td align="center" width="10%">(unused)</td>
+<td align="center" width="10%">0</td>
+<td align="center" width="30%"> </td>
+<td align="center" width="10%">MC6</td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%">3</td>
+<td width="8%" align="center">I/O/GTS4</td>
+<td align="center" width="10%"> </td>
+</tr>
+<tr>
+<td align="center" width="10%">(unused)</td>
+<td align="center" width="10%">0</td>
+<td align="center" width="30%"> </td>
+<td align="center" width="10%">MC7</td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%">(b)</td>
+<td align="center" width="10%"> </td>
+</tr>
+<tr>
+<td align="center" width="10%"><a href="Javascript:showEqn('AUTO_CONFIG_DONE2_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">AUTO_CONFIG_DONE&lt;2&gt;</a></td>
+<td align="center" width="10%">2</td>
+<td align="center" width="30%"> <a href="Javascript:showPT('FB2_8_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">8_1</a> <a href="Javascript:showPT('FB2_8_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">8_2</a>
+</td>
+<td align="center" width="10%">MC8</td>
+<td align="center" width="10%">STD</td>
+<td align="center" width="10%">5</td>
+<td width="8%" align="center">I/O/GTS1</td>
+<td align="center" width="10%">(b)</td>
+</tr>
+<tr>
+<td align="center" width="10%"><a href="Javascript:showEqn('AUTO_CONFIG_DONE0_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">AUTO_CONFIG_DONE&lt;0&gt;</a></td>
+<td align="center" width="10%">2</td>
+<td align="center" width="30%"> <a href="Javascript:showPT('FB2_9_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">9_1</a> <a href="Javascript:showPT('FB2_9_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">9_2</a>
+</td>
+<td align="center" width="10%">MC9</td>
+<td align="center" width="10%">STD</td>
+<td align="center" width="10%">6</td>
+<td width="8%" align="center">I/O/GTS2</td>
+<td align="center" width="10%">(b)</td>
+</tr>
+<tr>
+<td align="center" width="10%"><a href="Javascript:showEqn('AUTO_CONFIG_DONE_CYCLE2_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">AUTO_CONFIG_DONE_CYCLE&lt;2&gt;</a></td>
+<td align="center" width="10%">3</td>
+<td align="center" width="30%"> <a href="Javascript:showPT('FB2_10_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">10_1</a> <a href="Javascript:showPT('FB2_10_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">10_2</a> <a href="Javascript:showPT('FB2_10_3')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">10_3</a>
+</td>
+<td align="center" width="10%">MC10</td>
+<td align="center" width="10%">STD</td>
+<td align="center" width="10%">7</td>
+<td width="8%" align="center">I/O</td>
+<td align="center" width="10%">(b)</td>
+</tr>
+<tr>
+<td align="center" width="10%"><a href="Javascript:showEqn('AUTO_CONFIG_DONE_CYCLE0_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">AUTO_CONFIG_DONE_CYCLE&lt;0&gt;</a></td>
+<td align="center" width="10%">3</td>
+<td align="center" width="30%"> <a href="Javascript:showPT('FB2_11_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">11_1</a> <a href="Javascript:showPT('FB2_11_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">11_2</a> <a href="Javascript:showPT('FB2_11_3')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">11_3</a>
+</td>
+<td align="center" width="10%">MC11</td>
+<td align="center" width="10%">STD</td>
+<td align="center" width="10%">9</td>
+<td width="8%" align="center">I/O</td>
+<td align="center" width="10%">(b)</td>
+</tr>
+<tr>
+<td align="center" width="10%"><a href="Javascript:showEqn('IDE_BASEADR7_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">IDE_BASEADR&lt;7&gt;</a></td>
+<td align="center" width="10%">4</td>
+<td align="center" width="30%"> <a href="Javascript:showPT('FB2_11_4')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">11_4</a> <a href="Javascript:showPT('FB2_12_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">12_1</a> <a href="Javascript:showPT('FB2_12_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">12_2</a> <a href="Javascript:showPT('FB2_12_3')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">12_3</a>
+</td>
+<td align="center" width="10%">MC12</td>
+<td align="center" width="10%">STD</td>
+<td align="center" width="10%">10</td>
+<td width="8%" align="center">I/O</td>
+<td align="center" width="10%">(b)</td>
+</tr>
+<tr>
+<td align="center" width="10%"><a href="Javascript:showEqn('IDE_BASEADR6_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">IDE_BASEADR&lt;6&gt;</a></td>
+<td align="center" width="10%">4</td>
+<td align="center" width="30%"> <a href="Javascript:showPT('FB2_12_4')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">12_4</a> <a href="Javascript:showPT('FB2_12_5')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">12_5</a> <a href="Javascript:showPT('FB2_13_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">13_1</a> <a href="Javascript:showPT('FB2_13_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">13_2</a>
+</td>
+<td align="center" width="10%">MC13</td>
+<td align="center" width="10%">STD</td>
+<td align="center" width="10%">12</td>
+<td width="8%" align="center">I/O</td>
+<td align="center" width="10%">(b)</td>
+</tr>
+<tr>
+<td align="center" width="10%">(unused)</td>
+<td align="center" width="10%">0</td>
+<td align="center" width="30%"> </td>
+<td align="center" width="10%">MC14</td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%">11</td>
+<td width="8%" align="center">I/O</td>
+<td align="center" width="10%">(b)</td>
+</tr>
+<tr>
+<td align="center" width="10%"><a href="Javascript:showEqn('D13_BUFR_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">D&lt;13&gt;_BUFR</a></td>
+<td align="center" width="10%">17</td>
+<td align="center" width="30%"> <a href="Javascript:showPT('FB2_13_3')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">13_3</a> <a href="Javascript:showPT('FB2_13_4')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">13_4</a> <a href="Javascript:showPT('FB2_13_5')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">13_5</a> <a href="Javascript:showPT('FB2_14_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">14_1</a> <a href="Javascript:showPT('FB2_14_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">14_2</a> <a href="Javascript:showPT('FB2_14_3')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">14_3</a> <a href="Javascript:showPT('FB2_14_4')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">14_4</a> <a href="Javascript:showPT('FB2_14_5')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">14_5</a> <a href="Javascript:showPT('FB2_15_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">15_1</a> <a href="Javascript:showPT('FB2_15_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">15_2</a> <a href="Javascript:showPT('FB2_15_3')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">15_3</a> <a href="Javascript:showPT('FB2_15_4')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">15_4</a> <a href="Javascript:showPT('FB2_15_5')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">15_5</a> <a href="Javascript:showPT('FB2_16_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">16_2</a> <a href="Javascript:showPT('FB2_16_3')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">16_3</a> <a href="Javascript:showPT('FB2_16_4')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">16_4</a> <a href="Javascript:showPT('FB2_16_5')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">16_5</a>
+</td>
+<td align="center" width="10%">MC15</td>
+<td align="center" width="10%">STD</td>
+<td align="center" width="10%">13</td>
+<td width="8%" align="center">I/O</td>
+<td align="center" width="10%">(b)</td>
+</tr>
+<tr>
+<td align="center" width="10%"><a href="Javascript:showEqn('D6_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">D&lt;6&gt;</a></td>
+<td align="center" width="10%">1</td>
+<td align="center" width="30%"> <a href="Javascript:showPT('FB2_16_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">16_1</a> <a href="Javascript:showPT('VCC')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''"></a>
+</td>
+<td align="center" width="10%">MC16</td>
+<td align="center" width="10%">STD</td>
+<td align="center" width="10%">14</td>
+<td width="8%" align="center">I/O</td>
+<td align="center" width="10%">O</td>
+</tr>
+<tr>
+<td align="center" width="10%"><a href="Javascript:showEqn('D3_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">D&lt;3&gt;</a></td>
+<td align="center" width="10%">1</td>
+<td align="center" width="30%"> <a href="Javascript:showPT('FB2_17_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">17_1</a> <a href="Javascript:showPT('VCC')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''"></a>
+</td>
+<td align="center" width="10%">MC17</td>
+<td align="center" width="10%">STD</td>
+<td align="center" width="10%">15</td>
+<td width="8%" align="center">I/O</td>
+<td align="center" width="10%">O</td>
+</tr>
+<tr>
+<td align="center" width="10%">(unused)</td>
+<td align="center" width="10%">0</td>
+<td align="center" width="30%"> </td>
+<td align="center" width="10%">MC18</td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%">(b)</td>
+<td align="center" width="10%">(b)</td>
+</tr>
+</table></span></div>
+<div id="tipBox"></div>
+<br><span id="fbsiguse" class="pgRef"><b>Signals Used By Logic in Function Block</b><br><ol>
+<li>AS</li>
+<li><a href="Javascript:showEqn('AUTOCONFIG_IN_PROGRESS')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">AUTOCONFIG_IN_PROGRESS</a></li>
+<li><a href="Javascript:showEqn('AUTO_CONFIG_DONE0_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">AUTO_CONFIG_DONE&lt;0&gt;</a></li>
+<li><a href="Javascript:showEqn('AUTO_CONFIG_DONE1_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">AUTO_CONFIG_DONE&lt;1&gt;</a></li>
+<li><a href="Javascript:showEqn('AUTO_CONFIG_DONE2_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">AUTO_CONFIG_DONE&lt;2&gt;</a></li>
+<li><a href="Javascript:showEqn('AUTO_CONFIG_DONE_CYCLE0_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">AUTO_CONFIG_DONE_CYCLE&lt;0&gt;</a></li>
+<li><a href="Javascript:showEqn('AUTO_CONFIG_DONE_CYCLE2_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">AUTO_CONFIG_DONE_CYCLE&lt;2&gt;</a></li>
+<li>A&lt;1&gt;</li>
+<li>A&lt;2&gt;</li>
+<li>A&lt;3&gt;</li>
+<li>A&lt;4&gt;</li>
+<li>A&lt;5&gt;</li>
+<li>A&lt;6&gt;</li>
+<li><a href="Javascript:showEqn('D13_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">D&lt;13&gt;</a></li>
+<li><a href="Javascript:showEqn('D14_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">D&lt;14&gt;</a></li>
+<li><a href="Javascript:showEqn('IDE_BASEADR6_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">IDE_BASEADR&lt;6&gt;</a></li>
+<li><a href="Javascript:showEqn('IDE_BASEADR7_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">IDE_BASEADR&lt;7&gt;</a></li>
+<li>D&lt;14&gt;.PIN</li>
+<li>D&lt;15&gt;.PIN</li>
+<li>RESET</li>
+<li>RW</li>
+<li>UDS</li>
+<li><a href="Javascript:showEqn('autoconfig')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">autoconfig</a></li>
+<li><a href="Javascript:showEqn('ideide_CLKF_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">ide/ide_CLKF</a></li>
+</ol></span><form><span class="pgRef"><table width="90%" align="center"><tr>
+<td align="left"><input type="button" onclick="javascript:parent.leftnav.showTop()" onmouseover="window.status='goto top of page'; return true;" onmouseout="window.status=''" value="back to top"></td>
+<td align="center"><table align="center" width="90%" border="0" cellpadding="0" cellspacing="0"><tr><td width="100%" align="center">
+<input type="button" onclick="javascript:showFB('FB1')" onmouseover="window.status='show previous Function Block'; return true;" onmouseout="window.status=''" value="prev">
+                    
+                  <input type="button" onclick="javascript:showFB('FB3')" onmouseover="window.status='show next Function Block'; return true;" onmouseout="window.status=''" value="next">
+</td></tr></table></td>
+<td align="right">
+<input type="button" onclick="javascript:showLegend('logiclegend.htm')" onmouseover="window.status='show Legend'; return true;" onmouseout="window.status=''" value="legend"><input type="button" onclick="window.print()" onmouseover="window.status='print page'; return true;" onmouseout="window.status=''" value="print page">
+</td>
+</tr></table></span></form>
+</body>
+</html>
diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/fbs_FB3.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/fbs_FB3.htm
new file mode 100644
index 0000000..408e55f
--- /dev/null
+++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/fbs_FB3.htm
@@ -0,0 +1,260 @@
+<html>
+<head>
+<meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+<script src="tooltips.js"></script><script src="fbs.js"></script><link rel="stylesheet" type="text/css" href="style.css">
+</head>
+<body class="pgBgnd" id="XC95144XL">
+<span id="fbsel" class="pgRef"><table cellspacing="0" cellpadding="0" border="0" width="90%" align="center"><tr>
+<td width="33%" valign="center" align="left"></td>
+<td width="33%" valign="center" align="center"><form name="fbopt"><select onchange="javascript:showFB(document.fbopt.fbType.options[document.fbopt.fbType.options.selectedIndex].value)" name="fbType"><option value="FB1">FB1</option>
+<option value="FB2">FB2</option>
+<option value="FB3" selected>FB3</option>
+<option value="FB4">FB4</option>
+<option value="FB5">FB5</option>
+<option value="FB6">FB6</option>
+<option value="FB7">FB7</option>
+<option value="FB8">FB8</option></select></form></td>
+<td width="33%" valign="center" align="right"></td>
+</tr></table></span><div><span id="fbdata" class="pgRef"><table align="center" width="90%" border="1" cellpadding="0" cellspacing="0">
+<tr class="pgHeader">
+<th width="10%">Signal Name</th>
+<th width="10%">Total Product Terms</th>
+<th width="30%">Product Terms</th>
+<th width="10%">Location</th>
+<th width="10%">Power Mode</th>
+<th width="10%">Pin Number</th>
+<th width="10%">PinType</th>
+<th width="10%">Pin Use</th>
+</tr>
+<tr>
+<td align="center" width="10%"><a href="Javascript:showEqn('D2_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">D&lt;2&gt;</a></td>
+<td align="center" width="10%">1</td>
+<td align="center" width="30%"> <a href="Javascript:showPT('FB3_1_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">1_1</a> <a href="Javascript:showPT('VCC')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''"></a>
+</td>
+<td align="center" width="10%">MC1</td>
+<td align="center" width="10%">STD</td>
+<td align="center" width="10%">39</td>
+<td width="8%" align="center">I/O</td>
+<td align="center" width="10%">O</td>
+</tr>
+<tr>
+<td align="center" width="10%">(unused)</td>
+<td align="center" width="10%">0</td>
+<td align="center" width="30%"> </td>
+<td align="center" width="10%">MC2</td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%">32</td>
+<td width="8%" align="center">I/O/GCK2</td>
+<td align="center" width="10%"> </td>
+</tr>
+<tr>
+<td align="center" width="10%"><a href="Javascript:showEqn('D10_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">D&lt;10&gt;</a></td>
+<td align="center" width="10%">1</td>
+<td align="center" width="30%"> <a href="Javascript:showPT('FB3_3_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">3_1</a> <a href="Javascript:showPT('VCC')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''"></a>
+</td>
+<td align="center" width="10%">MC3</td>
+<td align="center" width="10%">STD</td>
+<td align="center" width="10%">41</td>
+<td width="8%" align="center">I/O</td>
+<td align="center" width="10%">I/O</td>
+</tr>
+<tr>
+<td align="center" width="10%"><a href="Javascript:showEqn('D12_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">D&lt;12&gt;</a></td>
+<td align="center" width="10%">2</td>
+<td align="center" width="30%"> <a href="Javascript:showPT('FB3_4_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">4_1</a> <a href="Javascript:showPT('FB3_4_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">4_2</a>
+</td>
+<td align="center" width="10%">MC4</td>
+<td align="center" width="10%">STD</td>
+<td align="center" width="10%">44</td>
+<td width="8%" align="center">I/O</td>
+<td align="center" width="10%">I/O</td>
+</tr>
+<tr>
+<td align="center" width="10%">(unused)</td>
+<td align="center" width="10%">0</td>
+<td align="center" width="30%"> </td>
+<td align="center" width="10%">MC5</td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%">33</td>
+<td width="8%" align="center">I/O</td>
+<td align="center" width="10%"> </td>
+</tr>
+<tr>
+<td align="center" width="10%">(unused)</td>
+<td align="center" width="10%">0</td>
+<td align="center" width="30%"> </td>
+<td align="center" width="10%">MC6</td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%">34</td>
+<td width="8%" align="center">I/O</td>
+<td align="center" width="10%"> </td>
+</tr>
+<tr>
+<td align="center" width="10%"><a href="Javascript:showEqn('D14_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">D&lt;14&gt;</a></td>
+<td align="center" width="10%">2</td>
+<td align="center" width="30%"> <a href="Javascript:showPT('FB3_7_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">7_1</a> <a href="Javascript:showPT('FB3_7_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">7_2</a>
+</td>
+<td align="center" width="10%">MC7</td>
+<td align="center" width="10%">STD</td>
+<td align="center" width="10%">46</td>
+<td width="8%" align="center">I/O</td>
+<td align="center" width="10%">I/O</td>
+</tr>
+<tr>
+<td align="center" width="10%">(unused)</td>
+<td align="center" width="10%">0</td>
+<td align="center" width="30%"> </td>
+<td align="center" width="10%">MC8</td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%">38</td>
+<td width="8%" align="center">I/O/GCK3</td>
+<td align="center" width="10%"> </td>
+</tr>
+<tr>
+<td align="center" width="10%"><a href="Javascript:showEqn('D9_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">D&lt;9&gt;</a></td>
+<td align="center" width="10%">1</td>
+<td align="center" width="30%"> <a href="Javascript:showPT('FB3_9_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">9_1</a> <a href="Javascript:showPT('VCC')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''"></a>
+</td>
+<td align="center" width="10%">MC9</td>
+<td align="center" width="10%">STD</td>
+<td align="center" width="10%">40</td>
+<td width="8%" align="center">I/O</td>
+<td align="center" width="10%">I/O</td>
+</tr>
+<tr>
+<td align="center" width="10%"><a href="Javascript:showEqn('D15_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">D&lt;15&gt;</a></td>
+<td align="center" width="10%">2</td>
+<td align="center" width="30%"> <a href="Javascript:showPT('FB3_10_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">10_1</a> <a href="Javascript:showPT('FB3_10_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">10_2</a>
+</td>
+<td align="center" width="10%">MC10</td>
+<td align="center" width="10%">STD</td>
+<td align="center" width="10%">48</td>
+<td width="8%" align="center">I/O</td>
+<td align="center" width="10%">I/O</td>
+</tr>
+<tr>
+<td align="center" width="10%"><a href="Javascript:showEqn('D11_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">D&lt;11&gt;</a></td>
+<td align="center" width="10%">1</td>
+<td align="center" width="30%"> <a href="Javascript:showPT('FB3_11_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">11_1</a> <a href="Javascript:showPT('VCC')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''"></a>
+</td>
+<td align="center" width="10%">MC11</td>
+<td align="center" width="10%">STD</td>
+<td align="center" width="10%">43</td>
+<td width="8%" align="center">I/O</td>
+<td align="center" width="10%">I/O</td>
+</tr>
+<tr>
+<td align="center" width="10%"><a href="Javascript:showEqn('D13_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">D&lt;13&gt;</a></td>
+<td align="center" width="10%">2</td>
+<td align="center" width="30%"> <a href="Javascript:showPT('FB3_12_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">12_1</a> <a href="Javascript:showPT('FB3_12_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">12_2</a>
+</td>
+<td align="center" width="10%">MC12</td>
+<td align="center" width="10%">STD</td>
+<td align="center" width="10%">45</td>
+<td width="8%" align="center">I/O</td>
+<td align="center" width="10%">I/O</td>
+</tr>
+<tr>
+<td align="center" width="10%">(unused)</td>
+<td align="center" width="10%">0</td>
+<td align="center" width="30%"> </td>
+<td align="center" width="10%">MC13</td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%">(b)</td>
+<td align="center" width="10%"> </td>
+</tr>
+<tr>
+<td align="center" width="10%">(unused)</td>
+<td align="center" width="10%">0</td>
+<td align="center" width="30%"> </td>
+<td align="center" width="10%">MC14</td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%">49</td>
+<td width="8%" align="center">I/O</td>
+<td align="center" width="10%"><a href="#" onmouseover="this._tip = 'A&lt;5&gt;'; window.status='Input Signal'; return true;" onmouseout="window.status=''" class="tipBoxCursor">I</a></td>
+</tr>
+<tr>
+<td align="center" width="10%"><a href="Javascript:showEqn('AUTO_CONFIG_DONE1_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">AUTO_CONFIG_DONE&lt;1&gt;</a></td>
+<td align="center" width="10%">2</td>
+<td align="center" width="30%"> <a href="Javascript:showPT('FB3_15_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">15_1</a> <a href="Javascript:showPT('FB3_15_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">15_2</a>
+</td>
+<td align="center" width="10%">MC15</td>
+<td align="center" width="10%">STD</td>
+<td align="center" width="10%">50</td>
+<td width="8%" align="center">I/O</td>
+<td align="center" width="10%"><a href="#" onmouseover="this._tip = 'A&lt;4&gt;'; window.status='Input Signal'; return true;" onmouseout="window.status=''" class="tipBoxCursor">I</a></td>
+</tr>
+<tr>
+<td align="center" width="10%"><a href="Javascript:showEqn('AUTO_CONFIG_DONE_CYCLE1_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">AUTO_CONFIG_DONE_CYCLE&lt;1&gt;</a></td>
+<td align="center" width="10%">3</td>
+<td align="center" width="30%"> <a href="Javascript:showPT('FB3_16_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">16_1</a> <a href="Javascript:showPT('FB3_16_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">16_2</a> <a href="Javascript:showPT('FB3_16_3')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">16_3</a>
+</td>
+<td align="center" width="10%">MC16</td>
+<td align="center" width="10%">STD</td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%">(b)</td>
+<td align="center" width="10%">(b)</td>
+</tr>
+<tr>
+<td align="center" width="10%"><a href="Javascript:showEqn('IDE_BASEADR3_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">IDE_BASEADR&lt;3&gt;</a></td>
+<td align="center" width="10%">4</td>
+<td align="center" width="30%"> <a href="Javascript:showPT('FB3_17_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">17_1</a> <a href="Javascript:showPT('FB3_17_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">17_2</a> <a href="Javascript:showPT('FB3_17_3')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">17_3</a> <a href="Javascript:showPT('FB3_17_4')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">17_4</a>
+</td>
+<td align="center" width="10%">MC17</td>
+<td align="center" width="10%">STD</td>
+<td align="center" width="10%">51</td>
+<td width="8%" align="center">I/O</td>
+<td align="center" width="10%"><a href="#" onmouseover="this._tip = 'A&lt;6&gt;'; window.status='Input Signal'; return true;" onmouseout="window.status=''" class="tipBoxCursor">I</a></td>
+</tr>
+<tr>
+<td align="center" width="10%"><a href="Javascript:showEqn('IDE_BASEADR2_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">IDE_BASEADR&lt;2&gt;</a></td>
+<td align="center" width="10%">4</td>
+<td align="center" width="30%"> <a href="Javascript:showPT('FB3_18_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">18_1</a> <a href="Javascript:showPT('FB3_18_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">18_2</a> <a href="Javascript:showPT('FB3_18_3')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">18_3</a> <a href="Javascript:showPT('FB3_18_4')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">18_4</a>
+</td>
+<td align="center" width="10%">MC18</td>
+<td align="center" width="10%">STD</td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%">(b)</td>
+<td align="center" width="10%">(b)</td>
+</tr>
+</table></span></div>
+<div id="tipBox"></div>
+<br><span id="fbsiguse" class="pgRef"><b>Signals Used By Logic in Function Block</b><br><ol>
+<li>AS</li>
+<li><a href="Javascript:showEqn('AUTOCONFIG_IN_PROGRESS')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">AUTOCONFIG_IN_PROGRESS</a></li>
+<li><a href="Javascript:showEqn('AUTO_CONFIG_DONE0_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">AUTO_CONFIG_DONE&lt;0&gt;</a></li>
+<li><a href="Javascript:showEqn('AUTO_CONFIG_DONE1_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">AUTO_CONFIG_DONE&lt;1&gt;</a></li>
+<li><a href="Javascript:showEqn('AUTO_CONFIG_DONE_CYCLE1_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">AUTO_CONFIG_DONE_CYCLE&lt;1&gt;</a></li>
+<li>A&lt;1&gt;</li>
+<li>A&lt;2&gt;</li>
+<li>A&lt;3&gt;</li>
+<li>A&lt;4&gt;</li>
+<li>A&lt;5&gt;</li>
+<li>A&lt;6&gt;</li>
+<li><a href="Javascript:showEqn('D12_BUFR_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">D&lt;12&gt;_BUFR</a></li>
+<li><a href="Javascript:showEqn('D13_BUFR_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">D&lt;13&gt;_BUFR</a></li>
+<li><a href="Javascript:showEqn('D14_BUFR_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">D&lt;14&gt;_BUFR</a></li>
+<li><a href="Javascript:showEqn('D15_BUFR_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">D&lt;15&gt;_BUFR</a></li>
+<li><a href="Javascript:showEqn('IDE_BASEADR2_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">IDE_BASEADR&lt;2&gt;</a></li>
+<li><a href="Javascript:showEqn('IDE_BASEADR3_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">IDE_BASEADR&lt;3&gt;</a></li>
+<li>D&lt;11&gt;.PIN</li>
+<li>D&lt;10&gt;.PIN</li>
+<li>RESET</li>
+<li>RW</li>
+<li>UDS</li>
+<li><a href="Javascript:showEqn('autoconfig')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">autoconfig</a></li>
+<li><a href="Javascript:showEqn('ideide_CLKF_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">ide/ide_CLKF</a></li>
+</ol></span><form><span class="pgRef"><table width="90%" align="center"><tr>
+<td align="left"><input type="button" onclick="javascript:parent.leftnav.showTop()" onmouseover="window.status='goto top of page'; return true;" onmouseout="window.status=''" value="back to top"></td>
+<td align="center"><table align="center" width="90%" border="0" cellpadding="0" cellspacing="0"><tr><td width="100%" align="center">
+<input type="button" onclick="javascript:showFB('FB2')" onmouseover="window.status='show previous Function Block'; return true;" onmouseout="window.status=''" value="prev">
+                    
+                  <input type="button" onclick="javascript:showFB('FB4')" onmouseover="window.status='show next Function Block'; return true;" onmouseout="window.status=''" value="next">
+</td></tr></table></td>
+<td align="right">
+<input type="button" onclick="javascript:showLegend('logiclegend.htm')" onmouseover="window.status='show Legend'; return true;" onmouseout="window.status=''" value="legend"><input type="button" onclick="window.print()" onmouseover="window.status='print page'; return true;" onmouseout="window.status=''" value="print page">
+</td>
+</tr></table></span></form>
+</body>
+</html>
diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/fbs_FB4.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/fbs_FB4.htm
new file mode 100644
index 0000000..40a601f
--- /dev/null
+++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/fbs_FB4.htm
@@ -0,0 +1,251 @@
+<html>
+<head>
+<meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+<script src="tooltips.js"></script><script src="fbs.js"></script><link rel="stylesheet" type="text/css" href="style.css">
+</head>
+<body class="pgBgnd" id="XC95144XL">
+<span id="fbsel" class="pgRef"><table cellspacing="0" cellpadding="0" border="0" width="90%" align="center"><tr>
+<td width="33%" valign="center" align="left"></td>
+<td width="33%" valign="center" align="center"><form name="fbopt"><select onchange="javascript:showFB(document.fbopt.fbType.options[document.fbopt.fbType.options.selectedIndex].value)" name="fbType"><option value="FB1">FB1</option>
+<option value="FB2">FB2</option>
+<option value="FB3">FB3</option>
+<option value="FB4" selected>FB4</option>
+<option value="FB5">FB5</option>
+<option value="FB6">FB6</option>
+<option value="FB7">FB7</option>
+<option value="FB8">FB8</option></select></form></td>
+<td width="33%" valign="center" align="right"></td>
+</tr></table></span><div><span id="fbdata" class="pgRef"><table align="center" width="90%" border="1" cellpadding="0" cellspacing="0">
+<tr class="pgHeader">
+<th width="10%">Signal Name</th>
+<th width="10%">Total Product Terms</th>
+<th width="30%">Product Terms</th>
+<th width="10%">Location</th>
+<th width="10%">Power Mode</th>
+<th width="10%">Pin Number</th>
+<th width="10%">PinType</th>
+<th width="10%">Pin Use</th>
+</tr>
+<tr>
+<td align="center" width="10%"><a href="Javascript:showEqn('ide')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">ide</a></td>
+<td align="center" width="10%">19</td>
+<td align="center" width="30%"> <a href="Javascript:showPT('FB4_17_5')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">17_5</a> <a href="Javascript:showPT('FB4_18_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">18_1</a> <a href="Javascript:showPT('FB4_18_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">18_2</a> <a href="Javascript:showPT('FB4_18_3')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">18_3</a> <a href="Javascript:showPT('FB4_18_4')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">18_4</a> <a href="Javascript:showPT('FB4_18_5')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">18_5</a> <a href="Javascript:showPT('FB4_1_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">1_1</a> <a href="Javascript:showPT('FB4_1_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">1_2</a> <a href="Javascript:showPT('FB4_1_3')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">1_3</a> <a href="Javascript:showPT('FB4_1_4')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">1_4</a> <a href="Javascript:showPT('FB4_1_5')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">1_5</a> <a href="Javascript:showPT('FB4_2_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">2_1</a> <a href="Javascript:showPT('FB4_2_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">2_2</a> <a href="Javascript:showPT('FB4_2_3')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">2_3</a> <a href="Javascript:showPT('FB4_2_4')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">2_4</a> <a href="Javascript:showPT('FB4_2_5')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">2_5</a> <a href="Javascript:showPT('FB4_3_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">3_1</a> <a href="Javascript:showPT('FB4_3_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">3_2</a> <a href="Javascript:showPT('FB4_3_3')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">3_3</a>
+</td>
+<td align="center" width="10%">MC1</td>
+<td align="center" width="10%">STD</td>
+<td align="center" width="10%">118</td>
+<td width="8%" align="center">I/O</td>
+<td align="center" width="10%">(b)</td>
+</tr>
+<tr>
+<td align="center" width="10%">(unused)</td>
+<td align="center" width="10%">0</td>
+<td align="center" width="30%"> </td>
+<td align="center" width="10%">MC2</td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%">126</td>
+<td width="8%" align="center">I/O</td>
+<td align="center" width="10%">(b)</td>
+</tr>
+<tr>
+<td align="center" width="10%">(unused)</td>
+<td align="center" width="10%">0</td>
+<td align="center" width="30%"> </td>
+<td align="center" width="10%">MC3</td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%">133</td>
+<td width="8%" align="center">I/O</td>
+<td align="center" width="10%">(b)</td>
+</tr>
+<tr>
+<td align="center" width="10%">(unused)</td>
+<td align="center" width="10%">0</td>
+<td align="center" width="30%"> </td>
+<td align="center" width="10%">MC4</td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%">(b)</td>
+<td align="center" width="10%"> </td>
+</tr>
+<tr>
+<td align="center" width="10%">(unused)</td>
+<td align="center" width="10%">0</td>
+<td align="center" width="30%"> </td>
+<td align="center" width="10%">MC5</td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%">128</td>
+<td width="8%" align="center">I/O</td>
+<td align="center" width="10%"> </td>
+</tr>
+<tr>
+<td align="center" width="10%">(unused)</td>
+<td align="center" width="10%">0</td>
+<td align="center" width="30%"> </td>
+<td align="center" width="10%">MC6</td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%">129</td>
+<td width="8%" align="center">I/O</td>
+<td align="center" width="10%"> </td>
+</tr>
+<tr>
+<td align="center" width="10%">(unused)</td>
+<td align="center" width="10%">0</td>
+<td align="center" width="30%"> </td>
+<td align="center" width="10%">MC7</td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%">(b)</td>
+<td align="center" width="10%"> </td>
+</tr>
+<tr>
+<td align="center" width="10%">(unused)</td>
+<td align="center" width="10%">0</td>
+<td align="center" width="30%"> </td>
+<td align="center" width="10%">MC8</td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%">130</td>
+<td width="8%" align="center">I/O</td>
+<td align="center" width="10%"> </td>
+</tr>
+<tr>
+<td align="center" width="10%">(unused)</td>
+<td align="center" width="10%">0</td>
+<td align="center" width="30%"> </td>
+<td align="center" width="10%">MC9</td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%">131</td>
+<td width="8%" align="center">I/O</td>
+<td align="center" width="10%"> </td>
+</tr>
+<tr>
+<td align="center" width="10%">(unused)</td>
+<td align="center" width="10%">0</td>
+<td align="center" width="30%"> </td>
+<td align="center" width="10%">MC10</td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%">135</td>
+<td width="8%" align="center">I/O</td>
+<td align="center" width="10%"> </td>
+</tr>
+<tr>
+<td align="center" width="10%">(unused)</td>
+<td align="center" width="10%">0</td>
+<td align="center" width="30%"> </td>
+<td align="center" width="10%">MC11</td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%">132</td>
+<td width="8%" align="center">I/O</td>
+<td align="center" width="10%"> </td>
+</tr>
+<tr>
+<td align="center" width="10%">(unused)</td>
+<td align="center" width="10%">0</td>
+<td align="center" width="30%"> </td>
+<td align="center" width="10%">MC12</td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%">134</td>
+<td width="8%" align="center">I/O</td>
+<td align="center" width="10%"> </td>
+</tr>
+<tr>
+<td align="center" width="10%">(unused)</td>
+<td align="center" width="10%">0</td>
+<td align="center" width="30%"> </td>
+<td align="center" width="10%">MC13</td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%">137</td>
+<td width="8%" align="center">I/O</td>
+<td align="center" width="10%"> </td>
+</tr>
+<tr>
+<td align="center" width="10%">(unused)</td>
+<td align="center" width="10%">0</td>
+<td align="center" width="30%"> </td>
+<td align="center" width="10%">MC14</td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%">136</td>
+<td width="8%" align="center">I/O</td>
+<td align="center" width="10%"> </td>
+</tr>
+<tr>
+<td align="center" width="10%">(unused)</td>
+<td align="center" width="10%">0</td>
+<td align="center" width="30%"> </td>
+<td align="center" width="10%">MC15</td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%">138</td>
+<td width="8%" align="center">I/O</td>
+<td align="center" width="10%"> </td>
+</tr>
+<tr>
+<td align="center" width="10%"><a href="Javascript:showEqn('ideide_CLKF_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">ide/ide_CLKF</a></td>
+<td align="center" width="10%">2</td>
+<td align="center" width="30%"> <a href="Javascript:showPT('FB4_16_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">16_1</a> <a href="Javascript:showPT('FB4_16_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">16_2</a>
+</td>
+<td align="center" width="10%">MC16</td>
+<td align="center" width="10%">STD</td>
+<td align="center" width="10%">139</td>
+<td width="8%" align="center">I/O</td>
+<td align="center" width="10%">(b)</td>
+</tr>
+<tr>
+<td align="center" width="10%"><a href="Javascript:showEqn('autoconfig')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">autoconfig</a></td>
+<td align="center" width="10%">4</td>
+<td align="center" width="30%"> <a href="Javascript:showPT('FB4_17_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">17_1</a> <a href="Javascript:showPT('FB4_17_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">17_2</a> <a href="Javascript:showPT('FB4_17_3')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">17_3</a> <a href="Javascript:showPT('FB4_17_4')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">17_4</a>
+</td>
+<td align="center" width="10%">MC17</td>
+<td align="center" width="10%">STD</td>
+<td align="center" width="10%">140</td>
+<td width="8%" align="center">I/O</td>
+<td align="center" width="10%">(b)</td>
+</tr>
+<tr>
+<td align="center" width="10%">(unused)</td>
+<td align="center" width="10%">0</td>
+<td align="center" width="30%"> </td>
+<td align="center" width="10%">MC18</td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%">(b)</td>
+<td align="center" width="10%">(b)</td>
+</tr>
+</table></span></div>
+<div id="tipBox"></div>
+<br><span id="fbsiguse" class="pgRef"><b>Signals Used By Logic in Function Block</b><br><ol>
+<li><a href="Javascript:showEqn('AUTO_CONFIG_DONE0_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">AUTO_CONFIG_DONE&lt;0&gt;</a></li>
+<li><a href="Javascript:showEqn('AUTO_CONFIG_DONE1_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">AUTO_CONFIG_DONE&lt;1&gt;</a></li>
+<li><a href="Javascript:showEqn('AUTO_CONFIG_DONE2_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">AUTO_CONFIG_DONE&lt;2&gt;</a></li>
+<li>A&lt;16&gt;</li>
+<li>A&lt;17&gt;</li>
+<li>A&lt;18&gt;</li>
+<li>A&lt;19&gt;</li>
+<li>A&lt;20&gt;</li>
+<li>A&lt;21&gt;</li>
+<li>A&lt;22&gt;</li>
+<li>A&lt;23&gt;</li>
+<li>BERR</li>
+<li>C1</li>
+<li>C3</li>
+<li><a href="Javascript:showEqn('IDE_BASEADR0_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">IDE_BASEADR&lt;0&gt;</a></li>
+<li><a href="Javascript:showEqn('IDE_BASEADR1_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">IDE_BASEADR&lt;1&gt;</a></li>
+<li><a href="Javascript:showEqn('IDE_BASEADR2_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">IDE_BASEADR&lt;2&gt;</a></li>
+<li><a href="Javascript:showEqn('IDE_BASEADR3_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">IDE_BASEADR&lt;3&gt;</a></li>
+<li><a href="Javascript:showEqn('IDE_BASEADR4_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">IDE_BASEADR&lt;4&gt;</a></li>
+<li><a href="Javascript:showEqn('IDE_BASEADR5_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">IDE_BASEADR&lt;5&gt;</a></li>
+<li><a href="Javascript:showEqn('IDE_BASEADR6_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">IDE_BASEADR&lt;6&gt;</a></li>
+<li><a href="Javascript:showEqn('IDE_BASEADR7_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">IDE_BASEADR&lt;7&gt;</a></li>
+<li><a href="Javascript:showEqn('SHUT_UP1_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">SHUT_UP&lt;1&gt;</a></li>
+<li><a href="Javascript:showEqn('ideide_CLKF_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">ide/ide_CLKF</a></li>
+</ol></span><form><span class="pgRef"><table width="90%" align="center"><tr>
+<td align="left"><input type="button" onclick="javascript:parent.leftnav.showTop()" onmouseover="window.status='goto top of page'; return true;" onmouseout="window.status=''" value="back to top"></td>
+<td align="center"><table align="center" width="90%" border="0" cellpadding="0" cellspacing="0"><tr><td width="100%" align="center">
+<input type="button" onclick="javascript:showFB('FB3')" onmouseover="window.status='show previous Function Block'; return true;" onmouseout="window.status=''" value="prev">
+                    
+                  <input type="button" onclick="javascript:showFB('FB5')" onmouseover="window.status='show next Function Block'; return true;" onmouseout="window.status=''" value="next">
+</td></tr></table></td>
+<td align="right">
+<input type="button" onclick="javascript:showLegend('logiclegend.htm')" onmouseover="window.status='show Legend'; return true;" onmouseout="window.status=''" value="legend"><input type="button" onclick="window.print()" onmouseover="window.status='print page'; return true;" onmouseout="window.status=''" value="print page">
+</td>
+</tr></table></span></form>
+</body>
+</html>
diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/fbs_FB5.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/fbs_FB5.htm
new file mode 100644
index 0000000..ddc400f
--- /dev/null
+++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/fbs_FB5.htm
@@ -0,0 +1,254 @@
+<html>
+<head>
+<meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+<script src="tooltips.js"></script><script src="fbs.js"></script><link rel="stylesheet" type="text/css" href="style.css">
+</head>
+<body class="pgBgnd" id="XC95144XL">
+<span id="fbsel" class="pgRef"><table cellspacing="0" cellpadding="0" border="0" width="90%" align="center"><tr>
+<td width="33%" valign="center" align="left"></td>
+<td width="33%" valign="center" align="center"><form name="fbopt"><select onchange="javascript:showFB(document.fbopt.fbType.options[document.fbopt.fbType.options.selectedIndex].value)" name="fbType"><option value="FB1">FB1</option>
+<option value="FB2">FB2</option>
+<option value="FB3">FB3</option>
+<option value="FB4">FB4</option>
+<option value="FB5" selected>FB5</option>
+<option value="FB6">FB6</option>
+<option value="FB7">FB7</option>
+<option value="FB8">FB8</option></select></form></td>
+<td width="33%" valign="center" align="right"></td>
+</tr></table></span><div><span id="fbdata" class="pgRef"><table align="center" width="90%" border="1" cellpadding="0" cellspacing="0">
+<tr class="pgHeader">
+<th width="10%">Signal Name</th>
+<th width="10%">Total Product Terms</th>
+<th width="30%">Product Terms</th>
+<th width="10%">Location</th>
+<th width="10%">Power Mode</th>
+<th width="10%">Pin Number</th>
+<th width="10%">PinType</th>
+<th width="10%">Pin Use</th>
+</tr>
+<tr>
+<td align="center" width="10%">(unused)</td>
+<td align="center" width="10%">0</td>
+<td align="center" width="30%"> </td>
+<td align="center" width="10%">MC1</td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%">(b)</td>
+<td align="center" width="10%"> </td>
+</tr>
+<tr>
+<td align="center" width="10%">(unused)</td>
+<td align="center" width="10%">0</td>
+<td align="center" width="30%"> </td>
+<td align="center" width="10%">MC2</td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%">52</td>
+<td width="8%" align="center">I/O</td>
+<td align="center" width="10%"><a href="#" onmouseover="this._tip = 'A&lt;3&gt;'; window.status='Input Signal'; return true;" onmouseout="window.status=''" class="tipBoxCursor">I</a></td>
+</tr>
+<tr>
+<td align="center" width="10%">(unused)</td>
+<td align="center" width="10%">0</td>
+<td align="center" width="30%"> </td>
+<td align="center" width="10%">MC3</td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%">59</td>
+<td width="8%" align="center">I/O</td>
+<td align="center" width="10%"><a href="#" onmouseover="this._tip = 'A&lt;10&gt;'; window.status='Input Signal'; return true;" onmouseout="window.status=''" class="tipBoxCursor">I</a></td>
+</tr>
+<tr>
+<td align="center" width="10%">(unused)</td>
+<td align="center" width="10%">0</td>
+<td align="center" width="30%"> </td>
+<td align="center" width="10%">MC4</td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%">(b)</td>
+<td align="center" width="10%"> </td>
+</tr>
+<tr>
+<td align="center" width="10%">(unused)</td>
+<td align="center" width="10%">0</td>
+<td align="center" width="30%"> </td>
+<td align="center" width="10%">MC5</td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%">53</td>
+<td width="8%" align="center">I/O</td>
+<td align="center" width="10%"> </td>
+</tr>
+<tr>
+<td align="center" width="10%">(unused)</td>
+<td align="center" width="10%">0</td>
+<td align="center" width="30%"> </td>
+<td align="center" width="10%">MC6</td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%">54</td>
+<td width="8%" align="center">I/O</td>
+<td align="center" width="10%"><a href="#" onmouseover="this._tip = 'A&lt;2&gt;'; window.status='Input Signal'; return true;" onmouseout="window.status=''" class="tipBoxCursor">I</a></td>
+</tr>
+<tr>
+<td align="center" width="10%">(unused)</td>
+<td align="center" width="10%">0</td>
+<td align="center" width="30%"> </td>
+<td align="center" width="10%">MC7</td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%">66</td>
+<td width="8%" align="center">I/O</td>
+<td align="center" width="10%"> </td>
+</tr>
+<tr>
+<td align="center" width="10%">(unused)</td>
+<td align="center" width="10%">0</td>
+<td align="center" width="30%"> </td>
+<td align="center" width="10%">MC8</td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%">56</td>
+<td width="8%" align="center">I/O</td>
+<td align="center" width="10%"> </td>
+</tr>
+<tr>
+<td align="center" width="10%">(unused)</td>
+<td align="center" width="10%">0</td>
+<td align="center" width="30%"> </td>
+<td align="center" width="10%">MC9</td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%">57</td>
+<td width="8%" align="center">I/O</td>
+<td align="center" width="10%"><a href="#" onmouseover="this._tip = 'A&lt;1&gt;'; window.status='Input Signal'; return true;" onmouseout="window.status=''" class="tipBoxCursor">I</a></td>
+</tr>
+<tr>
+<td align="center" width="10%"><a href="Javascript:showEqn('ROM_B0_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">ROM_B&lt;0&gt;</a></td>
+<td align="center" width="10%">0</td>
+<td align="center" width="30%"> <a href="Javascript:showPT('GND')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''"></a>
+</td>
+<td align="center" width="10%">MC10</td>
+<td align="center" width="10%">STD</td>
+<td align="center" width="10%">68</td>
+<td width="8%" align="center">I/O</td>
+<td align="center" width="10%">O</td>
+</tr>
+<tr>
+<td align="center" width="10%">(unused)</td>
+<td align="center" width="10%">0</td>
+<td align="center" width="30%"> </td>
+<td align="center" width="10%">MC11</td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%">58</td>
+<td width="8%" align="center">I/O</td>
+<td align="center" width="10%"><a href="#" onmouseover="this._tip = 'A&lt;9&gt;'; window.status='Input Signal'; return true;" onmouseout="window.status=''" class="tipBoxCursor">I</a></td>
+</tr>
+<tr>
+<td align="center" width="10%">(unused)</td>
+<td align="center" width="10%">0</td>
+<td align="center" width="30%"> </td>
+<td align="center" width="10%">MC12</td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%">60</td>
+<td width="8%" align="center">I/O</td>
+<td align="center" width="10%"><a href="#" onmouseover="this._tip = 'A&lt;11&gt;'; window.status='Input Signal'; return true;" onmouseout="window.status=''" class="tipBoxCursor">I</a></td>
+</tr>
+<tr>
+<td align="center" width="10%"><a href="Javascript:showEqn('SHUT_UP1_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">SHUT_UP&lt;1&gt;</a></td>
+<td align="center" width="10%">3</td>
+<td align="center" width="30%"> <a href="Javascript:showPT('FB5_13_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">13_1</a> <a href="Javascript:showPT('FB5_13_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">13_2</a> <a href="Javascript:showPT('FB5_13_3')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">13_3</a>
+</td>
+<td align="center" width="10%">MC13</td>
+<td align="center" width="10%">STD</td>
+<td align="center" width="10%">70</td>
+<td width="8%" align="center">I/O</td>
+<td align="center" width="10%">(b)</td>
+</tr>
+<tr>
+<td align="center" width="10%"><a href="Javascript:showEqn('IDE_BASEADR5_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">IDE_BASEADR&lt;5&gt;</a></td>
+<td align="center" width="10%">4</td>
+<td align="center" width="30%"> <a href="Javascript:showPT('FB5_14_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">14_1</a> <a href="Javascript:showPT('FB5_14_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">14_2</a> <a href="Javascript:showPT('FB5_14_3')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">14_3</a> <a href="Javascript:showPT('FB5_14_4')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">14_4</a>
+</td>
+<td align="center" width="10%">MC14</td>
+<td align="center" width="10%">STD</td>
+<td align="center" width="10%">61</td>
+<td width="8%" align="center">I/O</td>
+<td align="center" width="10%"><a href="#" onmouseover="this._tip = 'A&lt;12&gt;'; window.status='Input Signal'; return true;" onmouseout="window.status=''" class="tipBoxCursor">I</a></td>
+</tr>
+<tr>
+<td align="center" width="10%"><a href="Javascript:showEqn('IDE_BASEADR4_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">IDE_BASEADR&lt;4&gt;</a></td>
+<td align="center" width="10%">4</td>
+<td align="center" width="30%"> <a href="Javascript:showPT('FB5_15_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">15_1</a> <a href="Javascript:showPT('FB5_15_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">15_2</a> <a href="Javascript:showPT('FB5_15_3')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">15_3</a> <a href="Javascript:showPT('FB5_15_4')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">15_4</a>
+</td>
+<td align="center" width="10%">MC15</td>
+<td align="center" width="10%">STD</td>
+<td align="center" width="10%">64</td>
+<td width="8%" align="center">I/O</td>
+<td align="center" width="10%"><a href="#" onmouseover="this._tip = 'A&lt;13&gt;'; window.status='Input Signal'; return true;" onmouseout="window.status=''" class="tipBoxCursor">I</a></td>
+</tr>
+<tr>
+<td align="center" width="10%"><a href="Javascript:showEqn('IDE_BASEADR1_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">IDE_BASEADR&lt;1&gt;</a></td>
+<td align="center" width="10%">4</td>
+<td align="center" width="30%"> <a href="Javascript:showPT('FB5_16_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">16_1</a> <a href="Javascript:showPT('FB5_16_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">16_2</a> <a href="Javascript:showPT('FB5_16_3')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">16_3</a> <a href="Javascript:showPT('FB5_16_4')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">16_4</a>
+</td>
+<td align="center" width="10%">MC16</td>
+<td align="center" width="10%">STD</td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%">(b)</td>
+<td align="center" width="10%">(b)</td>
+</tr>
+<tr>
+<td align="center" width="10%"><a href="Javascript:showEqn('ROM_B1_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">ROM_B&lt;1&gt;</a></td>
+<td align="center" width="10%">0</td>
+<td align="center" width="30%"> <a href="Javascript:showPT('GND')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''"></a>
+</td>
+<td align="center" width="10%">MC17</td>
+<td align="center" width="10%">STD</td>
+<td align="center" width="10%">69</td>
+<td width="8%" align="center">I/O</td>
+<td align="center" width="10%">O</td>
+</tr>
+<tr>
+<td align="center" width="10%"><a href="Javascript:showEqn('IDE_BASEADR0_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">IDE_BASEADR&lt;0&gt;</a></td>
+<td align="center" width="10%">4</td>
+<td align="center" width="30%"> <a href="Javascript:showPT('FB5_18_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">18_1</a> <a href="Javascript:showPT('FB5_18_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">18_2</a> <a href="Javascript:showPT('FB5_18_3')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">18_3</a> <a href="Javascript:showPT('FB5_18_4')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">18_4</a>
+</td>
+<td align="center" width="10%">MC18</td>
+<td align="center" width="10%">STD</td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%">(b)</td>
+<td align="center" width="10%">(b)</td>
+</tr>
+</table></span></div>
+<div id="tipBox"></div>
+<br><span id="fbsiguse" class="pgRef"><b>Signals Used By Logic in Function Block</b><br><ol>
+<li>AS</li>
+<li><a href="Javascript:showEqn('AUTO_CONFIG_DONE0_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">AUTO_CONFIG_DONE&lt;0&gt;</a></li>
+<li><a href="Javascript:showEqn('AUTO_CONFIG_DONE1_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">AUTO_CONFIG_DONE&lt;1&gt;</a></li>
+<li>A&lt;1&gt;</li>
+<li>A&lt;2&gt;</li>
+<li>A&lt;3&gt;</li>
+<li>A&lt;4&gt;</li>
+<li>A&lt;5&gt;</li>
+<li>A&lt;6&gt;</li>
+<li><a href="Javascript:showEqn('IDE_BASEADR0_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">IDE_BASEADR&lt;0&gt;</a></li>
+<li><a href="Javascript:showEqn('IDE_BASEADR1_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">IDE_BASEADR&lt;1&gt;</a></li>
+<li><a href="Javascript:showEqn('IDE_BASEADR4_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">IDE_BASEADR&lt;4&gt;</a></li>
+<li><a href="Javascript:showEqn('IDE_BASEADR5_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">IDE_BASEADR&lt;5&gt;</a></li>
+<li>D&lt;12&gt;.PIN</li>
+<li>D&lt;13&gt;.PIN</li>
+<li>D&lt;8&gt;.PIN</li>
+<li>D&lt;9&gt;.PIN</li>
+<li>RESET</li>
+<li>RW</li>
+<li><a href="Javascript:showEqn('SHUT_UP1_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">SHUT_UP&lt;1&gt;</a></li>
+<li>UDS</li>
+<li><a href="Javascript:showEqn('autoconfig')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">autoconfig</a></li>
+<li><a href="Javascript:showEqn('ideide_CLKF_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">ide/ide_CLKF</a></li>
+</ol></span><form><span class="pgRef"><table width="90%" align="center"><tr>
+<td align="left"><input type="button" onclick="javascript:parent.leftnav.showTop()" onmouseover="window.status='goto top of page'; return true;" onmouseout="window.status=''" value="back to top"></td>
+<td align="center"><table align="center" width="90%" border="0" cellpadding="0" cellspacing="0"><tr><td width="100%" align="center">
+<input type="button" onclick="javascript:showFB('FB4')" onmouseover="window.status='show previous Function Block'; return true;" onmouseout="window.status=''" value="prev">
+                    
+                  <input type="button" onclick="javascript:showFB('FB6')" onmouseover="window.status='show next Function Block'; return true;" onmouseout="window.status=''" value="next">
+</td></tr></table></td>
+<td align="right">
+<input type="button" onclick="javascript:showLegend('logiclegend.htm')" onmouseover="window.status='show Legend'; return true;" onmouseout="window.status=''" value="legend"><input type="button" onclick="window.print()" onmouseover="window.status='print page'; return true;" onmouseout="window.status=''" value="print page">
+</td>
+</tr></table></span></form>
+</body>
+</html>
diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/fbs_FB6.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/fbs_FB6.htm
new file mode 100644
index 0000000..96b5d7c
--- /dev/null
+++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/fbs_FB6.htm
@@ -0,0 +1,240 @@
+<html>
+<head>
+<meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+<script src="tooltips.js"></script><script src="fbs.js"></script><link rel="stylesheet" type="text/css" href="style.css">
+</head>
+<body class="pgBgnd" id="XC95144XL">
+<span id="fbsel" class="pgRef"><table cellspacing="0" cellpadding="0" border="0" width="90%" align="center"><tr>
+<td width="33%" valign="center" align="left"></td>
+<td width="33%" valign="center" align="center"><form name="fbopt"><select onchange="javascript:showFB(document.fbopt.fbType.options[document.fbopt.fbType.options.selectedIndex].value)" name="fbType"><option value="FB1">FB1</option>
+<option value="FB2">FB2</option>
+<option value="FB3">FB3</option>
+<option value="FB4">FB4</option>
+<option value="FB5">FB5</option>
+<option value="FB6" selected>FB6</option>
+<option value="FB7">FB7</option>
+<option value="FB8">FB8</option></select></form></td>
+<td width="33%" valign="center" align="right"></td>
+</tr></table></span><div><span id="fbdata" class="pgRef"><table align="center" width="90%" border="1" cellpadding="0" cellspacing="0">
+<tr class="pgHeader">
+<th width="10%">Signal Name</th>
+<th width="10%">Total Product Terms</th>
+<th width="30%">Product Terms</th>
+<th width="10%">Location</th>
+<th width="10%">Power Mode</th>
+<th width="10%">Pin Number</th>
+<th width="10%">PinType</th>
+<th width="10%">Pin Use</th>
+</tr>
+<tr>
+<td align="center" width="10%">(unused)</td>
+<td align="center" width="10%">0</td>
+<td align="center" width="30%"> </td>
+<td align="center" width="10%">MC1</td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%">(b)</td>
+<td align="center" width="10%"> </td>
+</tr>
+<tr>
+<td align="center" width="10%">(unused)</td>
+<td align="center" width="10%">0</td>
+<td align="center" width="30%"> </td>
+<td align="center" width="10%">MC2</td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%">106</td>
+<td width="8%" align="center">I/O</td>
+<td align="center" width="10%"> </td>
+</tr>
+<tr>
+<td align="center" width="10%">(unused)</td>
+<td align="center" width="10%">0</td>
+<td align="center" width="30%"> </td>
+<td align="center" width="10%">MC3</td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%">(b)</td>
+<td align="center" width="10%"> </td>
+</tr>
+<tr>
+<td align="center" width="10%">(unused)</td>
+<td align="center" width="10%">0</td>
+<td align="center" width="30%"> </td>
+<td align="center" width="10%">MC4</td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%">111</td>
+<td width="8%" align="center">I/O</td>
+<td align="center" width="10%"> </td>
+</tr>
+<tr>
+<td align="center" width="10%">(unused)</td>
+<td align="center" width="10%">0</td>
+<td align="center" width="30%"> </td>
+<td align="center" width="10%">MC5</td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%">110</td>
+<td width="8%" align="center">I/O</td>
+<td align="center" width="10%"> </td>
+</tr>
+<tr>
+<td align="center" width="10%">(unused)</td>
+<td align="center" width="10%">0</td>
+<td align="center" width="30%"> </td>
+<td align="center" width="10%">MC6</td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%">112</td>
+<td width="8%" align="center">I/O</td>
+<td align="center" width="10%"> </td>
+</tr>
+<tr>
+<td align="center" width="10%">(unused)</td>
+<td align="center" width="10%">0</td>
+<td align="center" width="30%"> </td>
+<td align="center" width="10%">MC7</td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%">(b)</td>
+<td align="center" width="10%"> </td>
+</tr>
+<tr>
+<td align="center" width="10%">(unused)</td>
+<td align="center" width="10%">0</td>
+<td align="center" width="30%"> </td>
+<td align="center" width="10%">MC8</td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%">113</td>
+<td width="8%" align="center">I/O</td>
+<td align="center" width="10%"> </td>
+</tr>
+<tr>
+<td align="center" width="10%">(unused)</td>
+<td align="center" width="10%">0</td>
+<td align="center" width="30%"> </td>
+<td align="center" width="10%">MC9</td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%">116</td>
+<td width="8%" align="center">I/O</td>
+<td align="center" width="10%"> </td>
+</tr>
+<tr>
+<td align="center" width="10%">(unused)</td>
+<td align="center" width="10%">0</td>
+<td align="center" width="30%"> </td>
+<td align="center" width="10%">MC10</td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%">115</td>
+<td width="8%" align="center">I/O</td>
+<td align="center" width="10%"> </td>
+</tr>
+<tr>
+<td align="center" width="10%">(unused)</td>
+<td align="center" width="10%">0</td>
+<td align="center" width="30%"> </td>
+<td align="center" width="10%">MC11</td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%">119</td>
+<td width="8%" align="center">I/O</td>
+<td align="center" width="10%"> </td>
+</tr>
+<tr>
+<td align="center" width="10%">(unused)</td>
+<td align="center" width="10%">0</td>
+<td align="center" width="30%"> </td>
+<td align="center" width="10%">MC12</td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%">120</td>
+<td width="8%" align="center">I/O</td>
+<td align="center" width="10%"> </td>
+</tr>
+<tr>
+<td align="center" width="10%">(unused)</td>
+<td align="center" width="10%">0</td>
+<td align="center" width="30%"> </td>
+<td align="center" width="10%">MC13</td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%">(b)</td>
+<td align="center" width="10%"> </td>
+</tr>
+<tr>
+<td align="center" width="10%">(unused)</td>
+<td align="center" width="10%">0</td>
+<td align="center" width="30%"> </td>
+<td align="center" width="10%">MC14</td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%">121</td>
+<td width="8%" align="center">I/O</td>
+<td align="center" width="10%"> </td>
+</tr>
+<tr>
+<td align="center" width="10%">(unused)</td>
+<td align="center" width="10%">0</td>
+<td align="center" width="30%"> </td>
+<td align="center" width="10%">MC15</td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%">124</td>
+<td width="8%" align="center">I/O</td>
+<td align="center" width="10%"> </td>
+</tr>
+<tr>
+<td align="center" width="10%">(unused)</td>
+<td align="center" width="10%">0</td>
+<td align="center" width="30%"> </td>
+<td align="center" width="10%">MC16</td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%">117</td>
+<td width="8%" align="center">I/O</td>
+<td align="center" width="10%">(b)</td>
+</tr>
+<tr>
+<td align="center" width="10%"><a href="Javascript:showEqn('D15_BUFR_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">D&lt;15&gt;_BUFR</a></td>
+<td align="center" width="10%">14</td>
+<td align="center" width="30%"> <a href="Javascript:showPT('FB6_16_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">16_1</a> <a href="Javascript:showPT('FB6_16_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">16_2</a> <a href="Javascript:showPT('FB6_16_3')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">16_3</a> <a href="Javascript:showPT('FB6_16_4')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">16_4</a> <a href="Javascript:showPT('FB6_17_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">17_1</a> <a href="Javascript:showPT('FB6_17_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">17_2</a> <a href="Javascript:showPT('FB6_17_3')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">17_3</a> <a href="Javascript:showPT('FB6_17_4')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">17_4</a> <a href="Javascript:showPT('FB6_17_5')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">17_5</a> <a href="Javascript:showPT('FB6_18_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">18_1</a> <a href="Javascript:showPT('FB6_18_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">18_2</a> <a href="Javascript:showPT('FB6_18_3')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">18_3</a> <a href="Javascript:showPT('FB6_18_4')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">18_4</a> <a href="Javascript:showPT('FB6_18_5')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">18_5</a>
+</td>
+<td align="center" width="10%">MC17</td>
+<td align="center" width="10%">STD</td>
+<td align="center" width="10%">125</td>
+<td width="8%" align="center">I/O</td>
+<td align="center" width="10%">(b)</td>
+</tr>
+<tr>
+<td align="center" width="10%">(unused)</td>
+<td align="center" width="10%">0</td>
+<td align="center" width="30%"> </td>
+<td align="center" width="10%">MC18</td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%">(b)</td>
+<td align="center" width="10%">(b)</td>
+</tr>
+</table></span></div>
+<div id="tipBox"></div>
+<br><span id="fbsiguse" class="pgRef"><b>Signals Used By Logic in Function Block</b><br><ol>
+<li>AS</li>
+<li><a href="Javascript:showEqn('AUTO_CONFIG_DONE0_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">AUTO_CONFIG_DONE&lt;0&gt;</a></li>
+<li><a href="Javascript:showEqn('AUTO_CONFIG_DONE1_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">AUTO_CONFIG_DONE&lt;1&gt;</a></li>
+<li><a href="Javascript:showEqn('AUTO_CONFIG_DONE2_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">AUTO_CONFIG_DONE&lt;2&gt;</a></li>
+<li>A&lt;1&gt;</li>
+<li>A&lt;2&gt;</li>
+<li>A&lt;3&gt;</li>
+<li>A&lt;4&gt;</li>
+<li>A&lt;5&gt;</li>
+<li>A&lt;6&gt;</li>
+<li><a href="Javascript:showEqn('D15_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">D&lt;15&gt;</a></li>
+<li>RESET</li>
+<li>RW</li>
+<li><a href="Javascript:showEqn('autoconfig')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">autoconfig</a></li>
+<li><a href="Javascript:showEqn('ideide_CLKF_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">ide/ide_CLKF</a></li>
+</ol></span><form><span class="pgRef"><table width="90%" align="center"><tr>
+<td align="left"><input type="button" onclick="javascript:parent.leftnav.showTop()" onmouseover="window.status='goto top of page'; return true;" onmouseout="window.status=''" value="back to top"></td>
+<td align="center"><table align="center" width="90%" border="0" cellpadding="0" cellspacing="0"><tr><td width="100%" align="center">
+<input type="button" onclick="javascript:showFB('FB5')" onmouseover="window.status='show previous Function Block'; return true;" onmouseout="window.status=''" value="prev">
+                    
+                  <input type="button" onclick="javascript:showFB('FB7')" onmouseover="window.status='show next Function Block'; return true;" onmouseout="window.status=''" value="next">
+</td></tr></table></td>
+<td align="right">
+<input type="button" onclick="javascript:showLegend('logiclegend.htm')" onmouseover="window.status='show Legend'; return true;" onmouseout="window.status=''" value="legend"><input type="button" onclick="window.print()" onmouseover="window.status='print page'; return true;" onmouseout="window.status=''" value="print page">
+</td>
+</tr></table></span></form>
+</body>
+</html>
diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/fbs_FB7.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/fbs_FB7.htm
new file mode 100644
index 0000000..497cf70
--- /dev/null
+++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/fbs_FB7.htm
@@ -0,0 +1,224 @@
+<html>
+<head>
+<meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+<script src="tooltips.js"></script><script src="fbs.js"></script><link rel="stylesheet" type="text/css" href="style.css">
+</head>
+<body class="pgBgnd" id="XC95144XL">
+<span id="fbsel" class="pgRef"><table cellspacing="0" cellpadding="0" border="0" width="90%" align="center"><tr>
+<td width="33%" valign="center" align="left"></td>
+<td width="33%" valign="center" align="center"><form name="fbopt"><select onchange="javascript:showFB(document.fbopt.fbType.options[document.fbopt.fbType.options.selectedIndex].value)" name="fbType"><option value="FB1">FB1</option>
+<option value="FB2">FB2</option>
+<option value="FB3">FB3</option>
+<option value="FB4">FB4</option>
+<option value="FB5">FB5</option>
+<option value="FB6">FB6</option>
+<option value="FB7" selected>FB7</option>
+<option value="FB8">FB8</option></select></form></td>
+<td width="33%" valign="center" align="right"></td>
+</tr></table></span><div><span id="fbdata" class="pgRef"><table align="center" width="90%" border="1" cellpadding="0" cellspacing="0">
+<tr class="pgHeader">
+<th width="10%">Signal Name</th>
+<th width="10%">Total Product Terms</th>
+<th width="30%">Product Terms</th>
+<th width="10%">Location</th>
+<th width="10%">Power Mode</th>
+<th width="10%">Pin Number</th>
+<th width="10%">PinType</th>
+<th width="10%">Pin Use</th>
+</tr>
+<tr>
+<td align="center" width="10%">(unused)</td>
+<td align="center" width="10%">0</td>
+<td align="center" width="30%"> </td>
+<td align="center" width="10%">MC1</td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%">(b)</td>
+<td align="center" width="10%"> </td>
+</tr>
+<tr>
+<td align="center" width="10%">(unused)</td>
+<td align="center" width="10%">0</td>
+<td align="center" width="30%"> </td>
+<td align="center" width="10%">MC2</td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%">71</td>
+<td width="8%" align="center">I/O</td>
+<td align="center" width="10%"> </td>
+</tr>
+<tr>
+<td align="center" width="10%">(unused)</td>
+<td align="center" width="10%">0</td>
+<td align="center" width="30%"> </td>
+<td align="center" width="10%">MC3</td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%">75</td>
+<td width="8%" align="center">I/O</td>
+<td align="center" width="10%"><a href="#" onmouseover="this._tip = 'AUTOBOOT_OFF'; window.status='Input Signal'; return true;" onmouseout="window.status=''" class="tipBoxCursor">I</a></td>
+</tr>
+<tr>
+<td align="center" width="10%">(unused)</td>
+<td align="center" width="10%">0</td>
+<td align="center" width="30%"> </td>
+<td align="center" width="10%">MC4</td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%">(b)</td>
+<td align="center" width="10%"> </td>
+</tr>
+<tr>
+<td align="center" width="10%">(unused)</td>
+<td align="center" width="10%">0</td>
+<td align="center" width="30%"> </td>
+<td align="center" width="10%">MC5</td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%">74</td>
+<td width="8%" align="center">I/O</td>
+<td align="center" width="10%"> </td>
+</tr>
+<tr>
+<td align="center" width="10%">(unused)</td>
+<td align="center" width="10%">0</td>
+<td align="center" width="30%"> </td>
+<td align="center" width="10%">MC6</td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%">76</td>
+<td width="8%" align="center">I/O</td>
+<td align="center" width="10%"> </td>
+</tr>
+<tr>
+<td align="center" width="10%">(unused)</td>
+<td align="center" width="10%">0</td>
+<td align="center" width="30%"> </td>
+<td align="center" width="10%">MC7</td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%">77</td>
+<td width="8%" align="center">I/O</td>
+<td align="center" width="10%"> </td>
+</tr>
+<tr>
+<td align="center" width="10%">(unused)</td>
+<td align="center" width="10%">0</td>
+<td align="center" width="30%"> </td>
+<td align="center" width="10%">MC8</td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%">78</td>
+<td width="8%" align="center">I/O</td>
+<td align="center" width="10%"> </td>
+</tr>
+<tr>
+<td align="center" width="10%">(unused)</td>
+<td align="center" width="10%">0</td>
+<td align="center" width="30%"> </td>
+<td align="center" width="10%">MC9</td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%">80</td>
+<td width="8%" align="center">I/O</td>
+<td align="center" width="10%"><a href="#" onmouseover="this._tip = 'AS'; window.status='Input Signal'; return true;" onmouseout="window.status=''" class="tipBoxCursor">I</a></td>
+</tr>
+<tr>
+<td align="center" width="10%">(unused)</td>
+<td align="center" width="10%">0</td>
+<td align="center" width="30%"> </td>
+<td align="center" width="10%">MC10</td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%">79</td>
+<td width="8%" align="center">I/O</td>
+<td align="center" width="10%"> </td>
+</tr>
+<tr>
+<td align="center" width="10%">(unused)</td>
+<td align="center" width="10%">0</td>
+<td align="center" width="30%"> </td>
+<td align="center" width="10%">MC11</td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%">82</td>
+<td width="8%" align="center">I/O</td>
+<td align="center" width="10%"> </td>
+</tr>
+<tr>
+<td align="center" width="10%"><a href="Javascript:showEqn('DTACK')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">DTACK</a></td>
+<td align="center" width="10%">0</td>
+<td align="center" width="30%"> <a href="Javascript:showPT('GND')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''"></a> <a href="Javascript:showPT('GND')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''"></a>
+</td>
+<td align="center" width="10%">MC12</td>
+<td align="center" width="10%">STD</td>
+<td align="center" width="10%">85</td>
+<td width="8%" align="center">I/O</td>
+<td align="center" width="10%">O</td>
+</tr>
+<tr>
+<td align="center" width="10%">(unused)</td>
+<td align="center" width="10%">0</td>
+<td align="center" width="30%"> </td>
+<td align="center" width="10%">MC13</td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%">81</td>
+<td width="8%" align="center">I/O</td>
+<td align="center" width="10%"><a href="#" onmouseover="this._tip = 'UDS'; window.status='Input Signal'; return true;" onmouseout="window.status=''" class="tipBoxCursor">I</a></td>
+</tr>
+<tr>
+<td align="center" width="10%">(unused)</td>
+<td align="center" width="10%">0</td>
+<td align="center" width="30%"> </td>
+<td align="center" width="10%">MC14</td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%">86</td>
+<td width="8%" align="center">I/O</td>
+<td align="center" width="10%"><a href="#" onmouseover="this._tip = 'A&lt;23&gt;'; window.status='Input Signal'; return true;" onmouseout="window.status=''" class="tipBoxCursor">I</a></td>
+</tr>
+<tr>
+<td align="center" width="10%">(unused)</td>
+<td align="center" width="10%">0</td>
+<td align="center" width="30%"> </td>
+<td align="center" width="10%">MC15</td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%">87</td>
+<td width="8%" align="center">I/O</td>
+<td align="center" width="10%"><a href="#" onmouseover="this._tip = 'A&lt;22&gt;'; window.status='Input Signal'; return true;" onmouseout="window.status=''" class="tipBoxCursor">I</a></td>
+</tr>
+<tr>
+<td align="center" width="10%">(unused)</td>
+<td align="center" width="10%">0</td>
+<td align="center" width="30%"> </td>
+<td align="center" width="10%">MC16</td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%">83</td>
+<td width="8%" align="center">I/O</td>
+<td align="center" width="10%"><a href="#" onmouseover="this._tip = 'RW'; window.status='Input Signal'; return true;" onmouseout="window.status=''" class="tipBoxCursor">I</a></td>
+</tr>
+<tr>
+<td align="center" width="10%">(unused)</td>
+<td align="center" width="10%">0</td>
+<td align="center" width="30%"> </td>
+<td align="center" width="10%">MC17</td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%">88</td>
+<td width="8%" align="center">I/O</td>
+<td align="center" width="10%"><a href="#" onmouseover="this._tip = 'A&lt;21&gt;'; window.status='Input Signal'; return true;" onmouseout="window.status=''" class="tipBoxCursor">I</a></td>
+</tr>
+<tr>
+<td align="center" width="10%">(unused)</td>
+<td align="center" width="10%">0</td>
+<td align="center" width="30%"> </td>
+<td align="center" width="10%">MC18</td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%">(b)</td>
+<td align="center" width="10%"> </td>
+</tr>
+</table></span></div>
+<div id="tipBox"></div>
+<br><span id="fbsiguse" class="pgRef"><b>Signals Used By Logic in Function Block</b><br><ol></ol></span><form><span class="pgRef"><table width="90%" align="center"><tr>
+<td align="left"><input type="button" onclick="javascript:parent.leftnav.showTop()" onmouseover="window.status='goto top of page'; return true;" onmouseout="window.status=''" value="back to top"></td>
+<td align="center"><table align="center" width="90%" border="0" cellpadding="0" cellspacing="0"><tr><td width="100%" align="center">
+<input type="button" onclick="javascript:showFB('FB6')" onmouseover="window.status='show previous Function Block'; return true;" onmouseout="window.status=''" value="prev">
+                    
+                  <input type="button" onclick="javascript:showFB('FB8')" onmouseover="window.status='show next Function Block'; return true;" onmouseout="window.status=''" value="next">
+</td></tr></table></td>
+<td align="right">
+<input type="button" onclick="javascript:showLegend('logiclegend.htm')" onmouseover="window.status='show Legend'; return true;" onmouseout="window.status=''" value="legend"><input type="button" onclick="window.print()" onmouseover="window.status='print page'; return true;" onmouseout="window.status=''" value="print page">
+</td>
+</tr></table></span></form>
+</body>
+</html>
diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/fbs_FB8.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/fbs_FB8.htm
new file mode 100644
index 0000000..ec5fac6
--- /dev/null
+++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/fbs_FB8.htm
@@ -0,0 +1,219 @@
+<html>
+<head>
+<meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+<script src="tooltips.js"></script><script src="fbs.js"></script><link rel="stylesheet" type="text/css" href="style.css">
+</head>
+<body class="pgBgnd" id="XC95144XL">
+<span id="fbsel" class="pgRef"><table cellspacing="0" cellpadding="0" border="0" width="90%" align="center"><tr>
+<td width="33%" valign="center" align="left"></td>
+<td width="33%" valign="center" align="center"><form name="fbopt"><select onchange="javascript:showFB(document.fbopt.fbType.options[document.fbopt.fbType.options.selectedIndex].value)" name="fbType"><option value="FB1">FB1</option>
+<option value="FB2">FB2</option>
+<option value="FB3">FB3</option>
+<option value="FB4">FB4</option>
+<option value="FB5">FB5</option>
+<option value="FB6">FB6</option>
+<option value="FB7">FB7</option>
+<option value="FB8" selected>FB8</option></select></form></td>
+<td width="33%" valign="center" align="right"></td>
+</tr></table></span><div><span id="fbdata" class="pgRef"><table align="center" width="90%" border="1" cellpadding="0" cellspacing="0">
+<tr class="pgHeader">
+<th width="10%">Signal Name</th>
+<th width="10%">Total Product Terms</th>
+<th width="30%">Product Terms</th>
+<th width="10%">Location</th>
+<th width="10%">Power Mode</th>
+<th width="10%">Pin Number</th>
+<th width="10%">PinType</th>
+<th width="10%">Pin Use</th>
+</tr>
+<tr>
+<td align="center" width="10%">(unused)</td>
+<td align="center" width="10%">0</td>
+<td align="center" width="30%"> </td>
+<td align="center" width="10%">MC1</td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%">(b)</td>
+<td align="center" width="10%"> </td>
+</tr>
+<tr>
+<td align="center" width="10%">(unused)</td>
+<td align="center" width="10%">0</td>
+<td align="center" width="30%"> </td>
+<td align="center" width="10%">MC2</td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%">91</td>
+<td width="8%" align="center">I/O</td>
+<td align="center" width="10%"><a href="#" onmouseover="this._tip = 'A&lt;20&gt;'; window.status='Input Signal'; return true;" onmouseout="window.status=''" class="tipBoxCursor">I</a></td>
+</tr>
+<tr>
+<td align="center" width="10%">(unused)</td>
+<td align="center" width="10%">0</td>
+<td align="center" width="30%"> </td>
+<td align="center" width="10%">MC3</td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%">95</td>
+<td width="8%" align="center">I/O</td>
+<td align="center" width="10%"><a href="#" onmouseover="this._tip = 'A&lt;17&gt;'; window.status='Input Signal'; return true;" onmouseout="window.status=''" class="tipBoxCursor">I</a></td>
+</tr>
+<tr>
+<td align="center" width="10%">(unused)</td>
+<td align="center" width="10%">0</td>
+<td align="center" width="30%"> </td>
+<td align="center" width="10%">MC4</td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%">97</td>
+<td width="8%" align="center">I/O</td>
+<td align="center" width="10%"><a href="#" onmouseover="this._tip = 'A&lt;16&gt;'; window.status='Input Signal'; return true;" onmouseout="window.status=''" class="tipBoxCursor">I</a></td>
+</tr>
+<tr>
+<td align="center" width="10%">(unused)</td>
+<td align="center" width="10%">0</td>
+<td align="center" width="30%"> </td>
+<td align="center" width="10%">MC5</td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%">92</td>
+<td width="8%" align="center">I/O</td>
+<td align="center" width="10%"><a href="#" onmouseover="this._tip = 'A&lt;19&gt;'; window.status='Input Signal'; return true;" onmouseout="window.status=''" class="tipBoxCursor">I</a></td>
+</tr>
+<tr>
+<td align="center" width="10%">(unused)</td>
+<td align="center" width="10%">0</td>
+<td align="center" width="30%"> </td>
+<td align="center" width="10%">MC6</td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%">93</td>
+<td width="8%" align="center">I/O</td>
+<td align="center" width="10%"> </td>
+</tr>
+<tr>
+<td align="center" width="10%">(unused)</td>
+<td align="center" width="10%">0</td>
+<td align="center" width="30%"> </td>
+<td align="center" width="10%">MC7</td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%">(b)</td>
+<td align="center" width="10%"> </td>
+</tr>
+<tr>
+<td align="center" width="10%">(unused)</td>
+<td align="center" width="10%">0</td>
+<td align="center" width="30%"> </td>
+<td align="center" width="10%">MC8</td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%">94</td>
+<td width="8%" align="center">I/O</td>
+<td align="center" width="10%"><a href="#" onmouseover="this._tip = 'A&lt;18&gt;'; window.status='Input Signal'; return true;" onmouseout="window.status=''" class="tipBoxCursor">I</a></td>
+</tr>
+<tr>
+<td align="center" width="10%">(unused)</td>
+<td align="center" width="10%">0</td>
+<td align="center" width="30%"> </td>
+<td align="center" width="10%">MC9</td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%">96</td>
+<td width="8%" align="center">I/O</td>
+<td align="center" width="10%"> </td>
+</tr>
+<tr>
+<td align="center" width="10%">(unused)</td>
+<td align="center" width="10%">0</td>
+<td align="center" width="30%"> </td>
+<td align="center" width="10%">MC10</td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%">101</td>
+<td width="8%" align="center">I/O</td>
+<td align="center" width="10%"> </td>
+</tr>
+<tr>
+<td align="center" width="10%">(unused)</td>
+<td align="center" width="10%">0</td>
+<td align="center" width="30%"> </td>
+<td align="center" width="10%">MC11</td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%">98</td>
+<td width="8%" align="center">I/O</td>
+<td align="center" width="10%"><a href="#" onmouseover="this._tip = 'BERR'; window.status='Input Signal'; return true;" onmouseout="window.status=''" class="tipBoxCursor">I</a></td>
+</tr>
+<tr>
+<td align="center" width="10%">(unused)</td>
+<td align="center" width="10%">0</td>
+<td align="center" width="30%"> </td>
+<td align="center" width="10%">MC12</td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%">100</td>
+<td width="8%" align="center">I/O</td>
+<td align="center" width="10%"> </td>
+</tr>
+<tr>
+<td align="center" width="10%">(unused)</td>
+<td align="center" width="10%">0</td>
+<td align="center" width="30%"> </td>
+<td align="center" width="10%">MC13</td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%">103</td>
+<td width="8%" align="center">I/O</td>
+<td align="center" width="10%"><a href="#" onmouseover="this._tip = 'C1'; window.status='Input Signal'; return true;" onmouseout="window.status=''" class="tipBoxCursor">I</a></td>
+</tr>
+<tr>
+<td align="center" width="10%">(unused)</td>
+<td align="center" width="10%">0</td>
+<td align="center" width="30%"> </td>
+<td align="center" width="10%">MC14</td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%">102</td>
+<td width="8%" align="center">I/O</td>
+<td align="center" width="10%"><a href="#" onmouseover="this._tip = 'C3'; window.status='Input Signal'; return true;" onmouseout="window.status=''" class="tipBoxCursor">I</a></td>
+</tr>
+<tr>
+<td align="center" width="10%">(unused)</td>
+<td align="center" width="10%">0</td>
+<td align="center" width="30%"> </td>
+<td align="center" width="10%">MC15</td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%">104</td>
+<td width="8%" align="center">I/O</td>
+<td align="center" width="10%"> </td>
+</tr>
+<tr>
+<td align="center" width="10%">(unused)</td>
+<td align="center" width="10%">0</td>
+<td align="center" width="30%"> </td>
+<td align="center" width="10%">MC16</td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%">107</td>
+<td width="8%" align="center">I/O</td>
+<td align="center" width="10%"> </td>
+</tr>
+<tr>
+<td align="center" width="10%">(unused)</td>
+<td align="center" width="10%">0</td>
+<td align="center" width="30%"> </td>
+<td align="center" width="10%">MC17</td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%">105</td>
+<td width="8%" align="center">I/O</td>
+<td align="center" width="10%"> </td>
+</tr>
+<tr>
+<td align="center" width="10%">(unused)</td>
+<td align="center" width="10%">0</td>
+<td align="center" width="30%"> </td>
+<td align="center" width="10%">MC18</td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%"> </td>
+<td align="center" width="10%">(b)</td>
+<td align="center" width="10%"> </td>
+</tr>
+</table></span></div>
+<div id="tipBox"></div>
+<br><span id="fbsiguse" class="pgRef"><b>Signals Used By Logic in Function Block</b><br><ol></ol></span><form><span class="pgRef"><table width="90%" align="center"><tr>
+<td align="left"><input type="button" onclick="javascript:parent.leftnav.showTop()" onmouseover="window.status='goto top of page'; return true;" onmouseout="window.status=''" value="back to top"></td>
+<td align="center"><table align="center" width="90%" border="0" cellpadding="0" cellspacing="0"><tr><td width="100%" align="center"><input type="button" onclick="javascript:showFB('FB7')" onmouseover="window.status='show previous Function Block'; return true;" onmouseout="window.status=''" value="prev"></td></tr></table></td>
+<td align="right">
+<input type="button" onclick="javascript:showLegend('logiclegend.htm')" onmouseover="window.status='show Legend'; return true;" onmouseout="window.status=''" value="legend"><input type="button" onclick="window.print()" onmouseover="window.status='print page'; return true;" onmouseout="window.status=''" value="print page">
+</td>
+</tr></table></span></form>
+</body>
+</html>
diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/fbs_FBdoc.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/fbs_FBdoc.htm
new file mode 100644
index 0000000..36e7c96
--- /dev/null
+++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/fbs_FBdoc.htm
@@ -0,0 +1,310 @@
+<!doctype html public "-//w3c//dtd html 4.0 transitional//en">
+<html>
+<head>
+   <meta http-equiv="Content-Type" content="text/html; charset=iso-8859-1">
+   <meta name="generator" content="RoboHELP by eHelp Corporation - www.ehelp.com">
+   <meta name="generator-major-version" content="0.1">
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+   <meta name="filetype" content="kadov">
+   <meta name="filetype-version" content="1">
+   <meta name="page-count" content="1">
+   <meta name="layout-height" content="3556">
+   <meta name="layout-width" content="670">
+   <meta name="date" content="05 24, 2002 6:03:49 PM">
+   <meta name="GENERATOR" content="Mozilla/4.79 [en]C-CCK-MCD   (Windows NT 5.0; U) [Netscape]">
+   <title>Function Block Specifics</title>
+<!--(==============================================================)-->
+<!--(Document created with RoboEditor. )============================-->
+<!--(==============================================================)-->
+<!--(Meta)==========================================================-->
+<style>
+<!--
+p.whs1 {font-family: arial, sans-serif; font-size: 10pt;}
+p.whs2 {font-family: arial, sans-serif; font-size: 12pt;}
+p.whs3 {font-family: arial, sans-serif; font-size: 12pt;}
+h4.whs4 {font-family: arial, sans-serif;}
+ul.whs5 {list-style: disc;}
+p.whs6 {margin-left: 80px;}
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+ul.whs9 {list-style: disc;}
+p.whs10 {margin-left: 80px; font-family: arial, sans-serif; font-size: 10pt;}
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+h4.whs19 {font-family: arial, sans-serif;}
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+p.whs24 {font-family: arial, sans-serif; font-size: 10pt;}
+p.whs25 {font-family: arial, sans-serif; font-size: 10pt;}
+p.whs26 {font-family: arial, sans-serif; font-size: 10pt;}
+ul.whs27 {list-style: disc;}
+p.whs28 {font-family: arial, sans-serif; font-size: 10pt;}
+p.whs29 {font-family: arial, sans-serif; font-size: 10pt;}
+p.whs30 {font-family: arial, sans-serif; font-size: 10pt;}
+p.whs31 {font-family: arial, sans-serif; font-size: 10pt;}
+p.whs32 {font-family: arial, sans-serif; font-size: 10pt;}
+
+--></style>
+<script language="javascript" title="WebHelpInlineScript">
+<!--
+function reDo() {
+  if (innerWidth != origWidth || innerHeight != origHeight)
+     location.reload();
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+if ((parseInt(navigator.appVersion) == 4) && (navigator.appName == "Netscape")) {
+	origWidth = innerWidth;
+	origHeight = innerHeight;
+	onresize = reDo;
+}
+//-->
+</script>
+<style>
+<!--
+  div.WebHelpPopupMenu {position:absolute; left:0px; top:0px; z-index:4; visibility:hidden;}
+  p.WebHelpNavBar {text-align:right;}
+-->
+</style>
+<!--(Body)==========================================================-->
+</head>
+<body>
+
+<h1>
+Function Block Specifics</h1>
+
+<div class="whs1">To access specific details for a particular function
+block, click on that function block in either the <a href="maplogicdoc.htm">Mapped
+Logic</a>, <a href="mapinputdoc.htm">Mapped Inputs</a>, or <a href="fbsdoc.htm" style="font-family: arial, sans-serif; font-size: 10pt;">Function
+Blocks</a> sections of the fitter report.&nbsp;<!--kadov_tag{{<spaces>}}--><!--kadov_tag{{</spaces>}}-->The
+function block details page displays a table of details about the particular
+function block you selected, a view button you can click to show a graphical
+display of the function block, and a pulldown menu you can use to select
+other function blocks to see.</div>
+
+
+<p class="whs2">The Table
+
+<p class="whs3">The View
+<p><script LANGUAGE="JavaScript"><!--
+if (navigator.appName=="Netscape")
+{ document.write("<img src='xml5.jpg' x-maintain-ratio='TRUE' width='648' height='397' border='0'>");}
+else
+{ document.write("<img src='xml5.jpg' x-maintain-ratio='TRUE' style='border: none; width: 648px; height: 397px; float: none;' width='648' height='397' border='0'>");}
+//--></script>
+
+<h4 class="whs4">
+<a NAME="table"></a>The Table</h4>
+<span style="font-family: arial, sans-serif; font-size: 10pt;"><font size=-1>The
+table at the top of the function block details page provides the following
+information about the function block:</font></span>
+<ul type="disc" class="whs5">
+<li class="kadov-p" class="kadov-p">
+<span style="font-family: arial, sans-serif; font-size: 10pt;"><font size=-1>The
+signal name&nbsp;</font></span></li>
+</ul>
+
+<div class="whs6"><span style="font-weight: bold;
+											font-family: arial, sans-serif;
+											font-size: 10pt;"><font size=-1><b>Note:</span><span 
+ style="font-family: arial, sans-serif; font-size: 10pt;"></b>
+Clicking on a signal name will open a new window with the equations for
+that signal.&nbsp;</font></span></div>
+
+<ul type="disc" class="whs7">
+<li class="kadov-p" class="kadov-p">
+<span style="font-family: arial, sans-serif; font-size: 10pt;"><font size=-1>The
+total product terms used&nbsp;</font></span></li>
+
+<li class="kadov-p" class="kadov-p">
+<span style="font-family: arial, sans-serif; font-size: 10pt;"><!--kadov_tag{{<spaces>}}--><font size=-1>&nbsp;<!--kadov_tag{{</spaces>}}-->A
+list of product terms</font></span></li>
+</ul>
+
+<div class="whs8"><span style="font-weight: bold;
+											font-family: arial, sans-serif;
+											font-size: 10pt;"><font size=-1><b>Note:</span><span 
+ style="font-family: arial, sans-serif; font-size: 10pt;"></b>
+Clicking on a&nbsp;<!--kadov_tag{{<spaces>}}--><!--kadov_tag{{</spaces>}}-->product
+term will open a new window with the equations for that term.&nbsp;</font></span></div>
+
+<ul type="disc" class="whs9">
+<li class="kadov-p" class="kadov-p">
+<span style="font-family: arial, sans-serif; font-size: 10pt;"><font size=-1>The
+macrocell number in which the function block is located</font></span></li>
+</ul>
+
+<div class="whs10"><span style="font-family: arial, sans-serif; font-size: 10pt;"><span 
+ style="font-weight: bold;"><font size=-1><b>Note:</span></b>
+Clicking on the underscored macrocell number will provide a graphical display
+of the macrocell that looks like this:</font></span></div>
+
+
+<p class="whs11"><script LANGUAGE="JavaScript"><!--
+if (navigator.appName=="Netscape")
+{ document.write("<img src='macrocell.gif' x-maintain-ratio='TRUE' width='540' height='420' border='0'>");}
+else
+{ document.write("<img src='macrocell.gif' x-maintain-ratio='TRUE' style='border: none; width: 540px; height: 420px; float: none;' width='540' height='420' border='0'>");}
+//--></script>
+.
+<ul type="disc" class="whs12">
+<li class="kadov-p" class="kadov-p">
+<span style="font-family: arial, sans-serif; font-size: 10pt;"><font size=-1>The
+power mode</font></span></li>
+
+<li class="kadov-p" class="kadov-p">
+<span style="font-family: arial, sans-serif; font-size: 10pt;"><font size=-1>The
+pin number - an asterisk "*" indicates a user assignment</font></span></li>
+</ul>
+
+<ul type="disc" class="whs13">
+<div class="whs14"><span style="font-family: arial, sans-serif; font-size: 10pt;"><span 
+ style="font-weight: bold;"><font size=-1><b>N</span></b>ote:</span><span style="font-family: arial, sans-serif; font-size: 10pt;">
+Clicking on the underscored pin number will provide the pin layout diagram
+for the highlighted pin.&nbsp;<!--kadov_tag{{<spaces>}}--><!--kadov_tag{{</spaces>}}-->Rolling
+your mouse over the colored pin will pop up a tooltip with the signal name
+assigned to the pin, the I/O standard,&nbsp;<!--kadov_tag{{<spaces>}}--><!--kadov_tag{{</spaces>}}-->the
+I/O style, the slew rate, and/or any constraints assigned to the pin:</font></span></div>
+</ul>
+
+<div class="whs15"><script LANGUAGE="JavaScript"><!--
+if (navigator.appName=="Netscape")
+{ document.write("<img src='pin.gif' x-maintain-ratio='TRUE' width='309' height='312' border='0'>");}
+else
+{ document.write("<img src='pin.gif' x-maintain-ratio='TRUE' style='border: none; width: 309px; height: 312px; float: none;' width='309' height='312' border='0'>");}
+//--></script>
+</div>
+
+<ul type="disc" class="whs16">
+<li class="kadov-p" class="kadov-p">
+<span style="font-family: arial, sans-serif; font-size: 10pt;"><font size=-1>The
+pin type</font></span></li>
+
+<li class="kadov-p" class="kadov-p">
+<span style="font-family: arial, sans-serif; font-size: 10pt;"><font size=-1>The
+pin use&nbsp;</font></span></li>
+
+<li class="kadov-p" class="kadov-p">
+<span style="font-family: arial, sans-serif; font-size: 10pt;"><font size=-1><i>XPLA3
+only</i> - The GCK (Global Clock Signal) mapping&nbsp;</font></span></li>
+</ul>
+
+<div class="whs17"><span style="font-weight: bold;
+											font-family: arial, sans-serif;
+											font-size: 10pt;"><font size=-1><b>Note:</span><span 
+ style="font-family: arial, sans-serif; font-size: 10pt;"></b>
+Moving your mouse cursor over an "I" in the Pin Use column will display
+that input signal as a tooltip.</font></span></div>
+
+<br><span style="font-family: arial, sans-serif; font-size: 10pt;">
+<br><span style="font-family: arial, sans-serif; font-size: 10pt;"><i>XBR
+only</i> - Below the resource table there is another table listing the
+<b>Function Block Control Term</b> usage, the product term mapped to the
+control term is listed. Clicking on the product term will bring up a pop-up
+window displaying that product term.
+<blockquote>
+<li>
+CTC - control term clock</li>
+
+<li>
+CTR - control term reset</li>
+
+<li>
+CTS - control term set</li>
+
+<li>
+CTE - control term output enable</li>
+</blockquote>
+
+<p><br><span style="font-family: arial, sans-serif; font-size: 10pt;"><font size=-1>Below
+this table you will find a list of signals used by logic in the function
+block you are viewing.&nbsp;<!--kadov_tag{{<spaces>}}--><!--kadov_tag{{</spaces>}}-->The
+list displays output signals as links.&nbsp;<!--kadov_tag{{<spaces>}}--><!--kadov_tag{{</spaces>}}-->Clicking
+on an output signal link will open a new window showing the equations for
+that signal.</font></span><!--begin!kadov{{-->
+<br><!--}}end!kadov--><!--kadov_tag{{<implicit_p>}}-->
+
+<p class="whs18"><span style="font-family: arial, sans-serif;
+											font-size: 10pt;
+											font-weight: bold;"><font size=-1><b>Note:</span><span 
+ style="font-family: arial, sans-serif; font-size: 10pt;"><!--kadov_tag{{<spaces>}}--><!--kadov_tag{{</spaces>}}--></b>There
+is also a&nbsp;<script LANGUAGE="JavaScript"><!--
+if (navigator.appName=="Netscape")
+{ document.write("<img src='legend.gif' x-maintain-ratio='TRUE' width='68' height='28' border='0'>");}
+else
+{ document.write("<img src='legend.gif' x-maintain-ratio='TRUE' style='border: none; width: 68px; height: 28px; float: none;' width='68' height='28' border='0'>");}
+//--></script>
+button
+below the table.&nbsp;<!--kadov_tag{{<spaces>}}--><!--kadov_tag{{</spaces>}}-->Click
+this button to open a new window describing all of the acronyms used in
+the function block table.&nbsp;<!--kadov_tag{{<spaces>}}--><!--kadov_tag{{</spaces>}}-->You
+can select either brief descriptions or more detailed descriptions by clicking
+the "Verbose" button at the top of the window.</font></span>
+<h4 class="whs19">
+<a NAME="view"></a>The View</h4>
+
+<div class="whs20">When you click on the&nbsp;<script LANGUAGE="JavaScript"><!--
+if (navigator.appName=="Netscape")
+{ document.write("<img src='view.gif' x-maintain-ratio='TRUE' width='61' height='53' border='0'>");}
+else
+{ document.write("<img src='view.gif' x-maintain-ratio='TRUE' style='border: none; width: 61px; height: 53px; float: none;' width='61' height='53' border='0'>");}
+//--></script>
+button
+above the table, a new window will open with a graphical display of the
+function block you are examining.&nbsp;<!--kadov_tag{{<spaces>}}--><!--kadov_tag{{</spaces>}}-->The
+pins are all color-coded: input pins are green, output pins are blue, and
+clocks are magenta:</div>
+
+
+<p class="whs21"><script LANGUAGE="JavaScript"><!--
+if (navigator.appName=="Netscape")
+{ document.write("<img src='fb1.gif' x-maintain-ratio='TRUE' width='482' height='378' border='0'>");}
+else
+{ document.write("<img src='fb1.gif' x-maintain-ratio='TRUE' style='border: none; width: 482px; height: 378px; float: none;' width='482' height='378' border='0'>");}
+//--></script>
+
+
+<p class="whs22">Right-click anywhere within the window to pull up a menu
+that allows you to zoom in or out for easier viewing.&nbsp;<!--kadov_tag{{<spaces>}}--><!--kadov_tag{{</spaces>}}-->
+
+<p class="whs23">This menu also allows you choose to see all of the input
+connections, all of the output connections, or both at once.&nbsp;<!--kadov_tag{{<spaces>}}--><!--kadov_tag{{</spaces>}}-->Like
+the pins, the signals are color-coded: inputs are red, outputs are yellow,
+and macrocell connections are aqua:
+
+<p class="whs24"><script LANGUAGE="JavaScript"><!--
+if (navigator.appName=="Netscape")
+{ document.write("<img src='fb.gif' x-maintain-ratio='TRUE' width='497' height='377' border='0'>");}
+else
+{ document.write("<img src='fb.gif' x-maintain-ratio='TRUE' style='border: none; width: 497px; height: 377px; float: none;' width='497' height='377' border='0'>");}
+//--></script>
+
+
+<p class="whs25">To examine the signals of single pins, simply click the
+pin whose signals you wish to see.&nbsp;<!--kadov_tag{{<spaces>}}--><!--kadov_tag{{</spaces>}}-->To
+examine multiple pins without having to see everything at once, hold down
+the control key while you click the pins you want to view.
+
+<p class="whs26">To view the signals for individual macrocells:
+<ul type="disc" class="whs27">
+<div class="whs28">Click the inside edge of the macrocell to display its
+macrocell connections and inputs.</div>
+
+
+<p class="whs29">Click the outer edge to display its output signals
+
+<p class="whs30">Click in the center to display everything
+
+<p class="whs31">Double click in the center to open a new window with a
+detailed macrocell diagram</ul>
+
+<div class="whs32"></div>
+
+</body>
+</html>
diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/fbsdoc.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/fbsdoc.htm
new file mode 100644
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--- /dev/null
+++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/fbsdoc.htm
@@ -0,0 +1,103 @@
+<!doctype HTML public "-//W3C//DTD HTML 4.0 Frameset//EN">
+
+<html>
+
+<!--(==============================================================)-->
+<!--(Document created with RoboEditor. )============================-->
+<!--(==============================================================)-->
+
+<head>
+
+<title>Function Blocks</title>
+
+<!--(Meta)==========================================================-->
+
+<meta name=generator content="RoboHELP by eHelp Corporation - www.ehelp.com">
+<meta name=generator-major-version content=0.1>
+<meta name=generator-minor-version content=1>
+<meta name=filetype content=kadov>
+<meta name=filetype-version content=1>
+<meta name=page-count content=1>
+<meta name=layout-height content=405>
+<meta name=layout-width content=615>
+<meta name=date content="05 24, 2002 5:49:51 PM">
+
+
+
+<style>
+<!--
+ul.whs1 {list-style: disc;}
+
+--></style><script language="javascript" title="WebHelpInlineScript">
+<!--
+function reDo() {
+  if (innerWidth != origWidth || innerHeight != origHeight)
+     location.reload();
+}
+if ((parseInt(navigator.appVersion) == 4) && (navigator.appName == "Netscape")) {
+	origWidth = innerWidth;
+	origHeight = innerHeight;
+	onresize = reDo;
+}
+//-->
+</script><style>
+<!--
+  div.WebHelpPopupMenu {position:absolute; left:0px; top:0px; z-index:4; visibility:hidden;}
+  p.WebHelpNavBar {text-align:right;}
+-->
+</style>
+</head>
+
+<!--(Body)==========================================================-->
+
+
+<body>
+
+
+<h1>Function Blocks</h1>
+
+<span style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">The Function 
+ Blocks page provides a summary of all function blocks' resources. Clicking 
+ on one of the function blocks in the summary table will display the <a href="fbs_FBdoc.htm">specific details</a> for that function block. <!--kadov_tag{{<spaces>}}-->&nbsp;</FONT></span><!--kadov_tag{{</spaces>}}-->
+
+<!--begin!kadov{{--><br><!--}}end!kadov--><!--kadov_tag{{<implicit_p>}}-->&nbsp; 
+ 
+
+<!--begin!kadov{{--><br><!--}}end!kadov--><!--kadov_tag{{<implicit_p>}}--><span 
+ style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">The summary table 
+ contains the following: <!--kadov_tag{{<spaces>}}-->&nbsp;</FONT></span><!--kadov_tag{{</spaces>}}-->
+
+<ul type="disc" class="whs1">
+	
+	<li class=kadov-p
+		class=kadov-p><span style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">The 
+ function block</FONT></span></li>
+	
+	<li class=kadov-p
+		class=kadov-p><span style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">The 
+ number of macrocell used </FONT></span></li>
+	
+	<li class=kadov-p
+		class=kadov-p><span style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">The 
+ number of function block inputs used </FONT></span></li>
+	
+	<li class=kadov-p
+		class=kadov-p><span style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">The 
+ number of product terms used</FONT></span></li>
+	
+	<li class=kadov-p
+		class=kadov-p><span style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">The 
+ pins used</FONT></span></li>
+	
+	<li class=kadov-p
+		class=kadov-p><span style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">The 
+ local control terms used</FONT></span></li>
+	
+	<li class=kadov-p
+		class=kadov-p><span style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">The 
+ number of foldback NANDs used (CoolRunner only)</FONT></span></li>
+</ul>
+
+</body>
+
+</html>
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diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/genmsg.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/genmsg.htm
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--- /dev/null
+++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/genmsg.htm
@@ -0,0 +1,17 @@
+<!doctype html public "-//w3c//dtd html 4.0 transitional//en">
+<html>
+<head>
+   <meta http-equiv="Content-Type" content="text/html; charset=iso-8859-1">
+   <title>genmsg</title>
+</head>
+<body>
+&nbsp;
+<br>&nbsp;
+<dl>
+<dd>
+This file is currently being generated. Please recheck the link after some
+time for this report data.</dd>
+</dl>
+
+</body>
+</html>
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diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/index.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/index.htm
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--- /dev/null
+++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/index.htm
@@ -0,0 +1,14 @@
+<html>
+  <head>
+    <title></title>
+  </head>
+  <frameset frameborder="NO" framespacing="0" border="0" rows="94,*,0,0" cols="*">
+    <frame name="topnav" src="../tim/topnav.htm" scrolling="no" noresize marginwidth="0" marginheight="0">
+    <frameset frameborder="NO" framespacing="0" border="0" cols="125,*">
+      <frame name="leftnav" src="leftnav.htm" noresize marginwidth="0" marginheight="0">
+      <frame name="content" src="summary.htm">
+    </frameset>
+    <frame name="eqns" src="eqns.htm" scrolling="no">
+  </frameset>
+</html>
+
diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/inputleft.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/inputleft.htm
new file mode 100644
index 0000000..83dc5e0
--- /dev/null
+++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/inputleft.htm
@@ -0,0 +1,14 @@
+<html>
+<head>
+<meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+<script src="maplogic.js"></script><link rel="stylesheet" type="text/css" href="style.css">
+</head>
+<span id="maplog" class="pgRef"><h3 align="center">Unmapped Inputs</h3>
+<table width="90%" border="1" cellpadding="0" cellspacing="0"><tr class="pgHeader">
+<th width="28%">Signal Name</th>
+<th align="center">User Assignment</th>
+</tr></table></span><form><span class="pgRef"><table width="90%" align="center"><tr>
+<td align="left"><input type="button" onclick="javascript:parent.leftnav.showTop()" onmouseover="window.status='goto top of page'; return true;" onmouseout="window.status=''" value="back to top"></td>
+<td align="right"><input type="button" onclick="window.print()" onmouseover="window.status='print page'; return true;" onmouseout="window.status=''" value="print page"></td>
+</tr></table></span></form>
+</html>
diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/inputleft.js b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/inputleft.js
new file mode 100644
index 0000000..63fe42f
--- /dev/null
+++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/inputleft.js
@@ -0,0 +1 @@
+function showInputLeft() { parent.leftnav.showInputLeft(); }
diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/inputleftdoc.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/inputleftdoc.htm
new file mode 100644
index 0000000..0cb5adb
--- /dev/null
+++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/inputleftdoc.htm
@@ -0,0 +1,81 @@
+<!doctype html public "-//w3c//dtd html 4.0 transitional//en">
+<html>
+<head>
+   <meta http-equiv="Content-Type" content="text/html; charset=iso-8859-1">
+   <meta name="generator" content="RoboHELP by eHelp Corporation - www.ehelp.com">
+   <meta name="generator-major-version" content="0.1">
+   <meta name="generator-minor-version" content="1">
+   <meta name="filetype" content="kadov">
+   <meta name="filetype-version" content="1">
+   <meta name="page-count" content="1">
+   <meta name="layout-height" content="1506">
+   <meta name="layout-width" content="639">
+   <meta name="date" content="05 24, 2002 5:49:09 PM">
+   <meta name="GENERATOR" content="Mozilla/4.79 [en]C-CCK-MCD   (Windows NT 5.0; U) [Netscape]">
+   <title>Mapped Logic</title>
+<!--(==============================================================)-->
+<!--(Document created with RoboEditor. )============================-->
+<!--(==============================================================)-->
+<!--(Meta)==========================================================-->
+<style>
+<!--
+ul.whs1 {list-style: disc;}
+p.whs2 {margin-left: 80px;}
+ul.whs3 {list-style: disc;}
+p.whs4 {margin-left: 80px; font-family: arial, sans-serif; font-size: 10pt;}
+ul.whs5 {list-style: disc;}
+p.whs6 {margin-left: 80px; font-family: arial, sans-serif; font-size: 10pt;}
+p.whs7 {margin-left: 80px; font-family: arial, sans-serif; font-size: 10pt;}
+ul.whs8 {list-style: disc;}
+p.whs9 {margin-left: 80px; font-family: arial, sans-serif; font-size: 10pt;}
+p.whs10 {margin-left: 80px; font-family: arial, sans-serif; font-size: 10pt;}
+ul.whs11 {list-style: disc;}
+
+--></style>
+<script language="javascript" title="WebHelpInlineScript">
+<!--
+function reDo() {
+  if (innerWidth != origWidth || innerHeight != origHeight)
+     location.reload();
+}
+if ((parseInt(navigator.appVersion) == 4) && (navigator.appName == "Netscape")) {
+	origWidth = innerWidth;
+	origHeight = innerHeight;
+	onresize = reDo;
+}
+//-->
+</script>
+<style>
+<!--
+  div.WebHelpPopupMenu {position:absolute; left:0px; top:0px; z-index:4; visibility:hidden;}
+  p.WebHelpNavBar {text-align:right;}
+-->
+</style>
+<!--(Body)==========================================================-->
+</head>
+<body>
+
+<h1>
+Unmapped Inputs</h1>
+<span style="font-family: arial, sans-serif; font-size: 10pt;"><font size=-1>The
+Unmapped Inputs section provides a table listing all inputs that failed
+to fit into the specified device. The page will appear in your browser
+sorted by Signal Name.&nbsp;</font></span><!--begin!kadov{{-->
+<br><!--}}end!kadov--><!--kadov_tag{{<implicit_p>}}--><!--begin!kadov{{-->
+<br><!--}}end!kadov--><!--kadov_tag{{<implicit_p>}}--><span 
+ style="font-family: arial, sans-serif; font-size: 10pt;"><font size=-1>The
+Unmapped Inputs table contains the following:&nbsp;</font></span>
+<ul type="disc" class="whs1">
+<li class="kadov-p" class="kadov-p">
+<span style="font-family: arial, sans-serif; font-size: 10pt;"><font size=-1>The
+input signal name&nbsp;</font></span></li>
+</ul>
+
+<ul type="disc" class="whs11">
+<li class="kadov-p" class="kadov-p">
+<span style="font-family: arial, sans-serif; font-size: 10pt;"><font size=-1>The
+Pin/FB Assignment specified by the user.</font></span></li>
+</ul>
+
+</body>
+</html>
diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/leftnav.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/leftnav.htm
new file mode 100644
index 0000000..99d935f
--- /dev/null
+++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/leftnav.htm
@@ -0,0 +1,63 @@
+<html>
+<head>
+<meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+<script>var currEqnType = defEqnType = 1</script><script src="applet.js"></script><script src="leftnav.js"></script><link rel="stylesheet" type="text/css" href="../tim/toc.css">
+</head>
+<body bgcolor="#CCCCCC" text="#000000"><form name="options">
+<span class="tocRef"><table width="105" border="0" cellspacing="0" cellpadding="0">
+<tr><td colspan="2"><div align="left"><span class="HEADING">Fitter Report</span></div></td></tr>
+<tr>
+<td width="7"> </td>
+<td><a href="javascript:showSummary();" class="SECONDARY-NAV" onmouseover="window.status='goto Summary'; return true;" onmouseout="window.status=''">Summary</a></td>
+</tr>
+<tr>
+<td width="7"> </td>
+<td><a href="javascript:showError(10);" class="SECONDARY-NAV" onmouseover="window.status='goto Errors/Warnings'; return true;" onmouseout="window.status=''">Errors/Warnings</a></td>
+</tr>
+<tr>
+<td width="7"> </td>
+<td><a href="javascript:showMappedLogics(0);" class="SECONDARY-NAV" onmouseover="window.status='goto Logic'; return true;" onmouseout="window.status=''">Logic</a></td>
+</tr>
+<tr>
+<td width="7"> </td>
+<td><a href="javascript:showMappedInputs(0);" class="SECONDARY-NAV" onmouseover="window.status='goto Inputs'; return true;" onmouseout="window.status=''">Inputs</a></td>
+</tr>
+<tr>
+<td width="7"> </td>
+<td><a href="javascript:showFBSum();" class="SECONDARY-NAV" onmouseover="window.status='goto Function Blocks Summary'; return true;" onmouseout="window.status=''">Function Blocks</a></td>
+</tr>
+<tr>
+<td width="7"> </td>
+<td><a href="javascript:showEqnAll();" class="SECONDARY-NAV" onmouseover="window.status='goto Equations'; return true;" onmouseout="window.status=''">Equations</a></td>
+</tr>
+<tr>
+<td width="7"> </td>
+<td><a href="javascript:showPinOut(10);" class="SECONDARY-NAV" onmouseover="window.status='goto Pin List'; return true;" onmouseout="window.status=''">Pin List</a></td>
+</tr>
+<tr>
+<td width="7"> </td>
+<td><a href="javascript:showOptions();" class="SECONDARY-NAV" onmouseover="window.status='goto Compiler Options'; return true;" onmouseout="window.status=''">Compiler Options</a></td>
+</tr>
+<tr>
+<td width="7"> </td>
+<td><a href="javascript:showAscii();" class="SECONDARY-NAV" onmouseover="window.status='goto Text Report'; return true;" onmouseout="window.status=''">Text Report</a></td>
+</tr>
+<tr>
+<td width="7"> </td>
+<td><a href="javascript:showHelp();" class="SECONDARY-NAV" onmouseover="window.status='goto Help'; return true;" onmouseout="window.status=''">Help</a></td>
+</tr>
+</table></span><div align="left">
+<br><br><br><table width="105" border="0" cellspacing="0" cellpadding="0">
+<tr><td colspan="2"><b><span class="HEADING">Equation Display Style</span></b></td></tr>
+<tr>
+<td width="7"> </td>
+<td><select name="eqnType" onchange="doEqnFormat()"><option value="0">ABEL</option>
+<option value="1" selected>VHDL</option>
+<option value="2">Verilog</option></select></td>
+</tr>
+</table>
+<br><b> </b>
+</div>
+<input type="hidden" name="info" value="1"><input type="hidden" name="warn" value="1"><input type="hidden" name="error" value="1"><input type="hidden" name="inOn" value="1"><input type="hidden" name="outOn" value="1"><input type="hidden" name="glbOn" value="1"><input type="hidden" name="ispOn" value="1"><input type="hidden" name="vccOn" value="1"><input type="hidden" name="gndOn" value="1"><input type="hidden" name="prohibitOn" value="1"><input type="hidden" name="unuseOn" value="1"><input type="hidden" name="ncOn" value="1"><input type="hidden" name="htmlStr" value=""><input type="hidden" name="pinStr" value=""><input type="hidden" name="eqnStr" value=""><input type="hidden" name="errStr" value=""><input type="hidden" name="pinSel" value="0"><input type="hidden" name="currPage" value="summary">
+</form></body>
+</html>
diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/leftnav.js b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/leftnav.js
new file mode 100644
index 0000000..bbc0028
--- /dev/null
+++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/leftnav.js
@@ -0,0 +1,180 @@
+var noAppletOnClicked = 1;
+var appletMsg = "";
+var waitWin;
+var oldIn =  oldOut = oldGbl = oldIsp = oldVcc = oldGnd = oldProhibit = oldUnuse = oldNc = 1;
+var oldInfo = oldWarn = oldError = 1;
+var verbose = 0;
+var dispPage, mapLogPage, mapInPage, unLogPage, unInPage;
+var javaPermission = 0;
+var abelEqn = vhdlEqn = verEqn = "";
+
+function IsNS() {
+  return ((navigator.appName.indexOf("Netscape") >= 0) &&
+          (parseFloat(navigator.appVersion) >= 4)) ? true : false;
+}
+
+function openWait() {
+  waitWin = window.open("wait.htm", "wait",
+                        "toolbar=no,location=no,"+
+                        "directories=no,status=no,menubar=no,scrollbars=no,"+
+                        "resizable=no,width=300,height=50" );
+}
+
+function closeWait() { if (waitWin) waitWin.close(); }
+
+function popHTML(name, str) {
+  document.options.htmlStr.value = str;
+  if (name.indexOf(":") > -1)
+    name = name.substring(0,name.indexOf(":")) + "_COLON_" +
+           name.substring(name.indexOf(":")+1,name.length);
+  if (name.indexOf(".") > -1)
+    name = name.substring(0,name.indexOf(".")) + "_DOT_" +
+           name.substring(name.indexOf(".")+1,name.length);
+  var win = window.open("result.htm", "win_"+name,
+                        "toolbar=no,location=no,"+
+                        "directories=no,status=no,menubar=no,scrollbars=yes,"+
+                        "resizable=yes,width=300,height=200" );
+  win.focus();
+}
+
+function setAppletPermission() { appletPermission = 1; }
+function getAppletPermission() { return( appletPermission); }
+function getAppletMsg() { return(appletMsg); }
+function setAppletMsg(msg) { appletMsg = msg; }
+
+
+function showHTML(page, html) {
+
+      dispPage = html;
+      document.options.currPage.value = page;
+      parent.content.location.href = html;
+}
+
+function showTop() { showHTML(document.options.currPage.value, dispPage); }
+
+function setVerbose(value) { verbose = value; }
+
+function showLegend(url, w, h) {
+  if (verbose == 1) {
+    url = url.substring(0,name.indexOf(".htm")) + "V.htm";
+  }
+  var win = window.open(url, 'win',
+              'toolbar=no,location=no,directories=no,status=no,menubar=no,scrollbars=yes,resizable=yes,width='+w+',height='+h);
+  win.focus();
+}
+
+function showSummary()    { showHTML("summary", "summary.htm"); }
+function showOptions()    { showHTML("options", "options.htm"); }
+function showFBSum()      { showHTML("fbs", "fbs.htm"); }
+function showFB(fb)       { showHTML("fbs_FB", "fbs_"+fb+".htm"); }
+function showPinOut()     { showHTML("pins", "pins.htm"); }
+function showError()      { showHTML("errors", "errs.htm"); }
+function showFailTable()  { showHTML("failtable", "failtable.htm"); }
+
+function showEqnAll()     {
+  openWait();
+  parent.eqns.setOper(currEqnType);
+  if (currEqnType == defEqnType) showHTML("equations", "defeqns.htm");
+  else if (currEqnType == 0) {
+    if (abelEqn == "") abelEqn = parent.eqns.getEqnList();
+    document.options.htmlStr.value = abelEqn;
+    showHTML("equations", "equations.htm");
+  }
+  else if (currEqnType == 1) {
+      if (vhdlEqn == "") vhdlEqn = parent.eqns.getEqnList();
+      document.options.htmlStr.value = vhdlEqn;
+      showHTML("equations", "equations.htm");
+  }
+  else {
+      if (verEqn == "") verEqn = parent.eqns.getEqnList();
+      document.options.htmlStr.value = verEqn;
+      showHTML("equations", "equations.htm");
+  }
+  closeWait();
+}
+
+function showEqn(sig)     {
+  popHTML(sig, parent.eqns.getEqn(sig));
+}
+
+function showPterm(pterm, type) {
+  popHTML(pterm, parent.eqns.getPterm(pterm, type));
+}
+
+function showAscii() { showHTML("ascii", "ascii.htm"); }
+
+function showHelp() { 
+  var helpDoc = document.options.currPage.value + "doc.htm";
+  popWin(helpDoc);
+}
+
+function getMapParam(type) {
+  var paramStr = "";
+  switch(type) {
+    case 1: paramStr  += "10"; break;
+    case 2: paramStr  += "01"; break;
+    case 3: paramStr  += "11"; break;
+    case 4: paramStr  += "02"; break;
+    case 5: paramStr  += "12"; break;
+    default: paramStr += "00";
+  }
+
+  return paramStr;
+}
+
+function showMappedLogics(type) {
+  showHTML("maplogic", "maplogic_" + getMapParam(type) + ".htm");
+}
+
+function showMappedInputs(type) {
+  showHTML("mapinput", "mapinput_" + getMapParam(type) + ".htm");
+}
+
+function showUnMappedLogics(type) {
+  showHTML("unmaplogic", "unmaplogic_" + getMapParam(type) + ".htm");
+}
+
+function showLogicLeft()  { showHTML("logicleft", "logicleft.htm"); }
+
+function showUnMappedInputs(type) {
+  showHTML("unmapinput", "unmapinput_" + getMapParam(type) + ".htm");
+}
+
+function showInputLeft()  { showHTML("inputleft", "inputleft.htm"); }
+
+function doEqnFormat() {
+  var type = document.options.eqnType.options[document.options.eqnType.options.selectedIndex].value;
+  currEqnType = type;
+  parent.eqns.setOper(currEqnType);
+  if (document.options.currPage.value == "equations") showEqnAll();
+}
+
+function showNoAppletAlert() {
+  window.alert("No Applet supported for this session!!!");
+}
+
+function showAppletMC(mc) {
+  if (parent.applets) parent.applets.showAppletGraphicMC(mc);
+  else showNoAppletAlert();
+}
+
+function showAppletFB(fb) {
+  if (parent.applets) parent.applets.showAppletGraphicFB(fb);
+  else showNoAppletAlert();
+}
+
+function showAppletPin(pin)  {
+  if (parent.applets) parent.applets.showAppletGraphicPin(pin);
+  else showNoAppletAlert();
+}
+
+function printAppletPkg() {
+  if (parent.applets) parent.applets.printAppletPkg();
+  else showNoAppletAlert();
+}
+
+function popWin(url) {
+  var win = window.open(url, 'win',
+              'location=yes,directories=yes,menubar=yes,toolbar=yes,status=yes,scrollbars=yes,resizable=yes,width=800,height=600');
+  win.focus();
+}
diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/legend.gif b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/legend.gif
new file mode 100644
index 0000000..0aad0eb
Binary files /dev/null and b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/legend.gif differ
diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/legend.jpg b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/legend.jpg
new file mode 100644
index 0000000..1d04af0
Binary files /dev/null and b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/legend.jpg differ
diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/logic_legXC95.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/logic_legXC95.htm
new file mode 100644
index 0000000..e253a0b
--- /dev/null
+++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/logic_legXC95.htm
@@ -0,0 +1,2 @@
+<html><body><pre>
+</pre></body></html>
diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/logic_legXbr.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/logic_legXbr.htm
new file mode 100644
index 0000000..d256e25
--- /dev/null
+++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/logic_legXbr.htm
@@ -0,0 +1,16 @@
+<html><body><pre>
+I/O Style - OD    - OpenDrain
+          - PU    - Pullup
+          - PN    - Pulldown
+          - KPR   - Keeper
+          - S     - SchmittTrigger
+          - DG    - DataGate
+Reg Use   - LATCH - Transparent latch
+          - DFF   - D-flip-flop
+          - DEFF  - D-flip-flop with clock enable
+          - TFF   - T-flip-flop
+          - TDFF  - Dual-edge-triggered T-flip-flop
+          - DDFF  - Dual-edge-triggered flip-flop
+          - DDEFF - Dual-edge-triggered flip-flop with clock enable
+          /S (after any above flop/latch type) indicates initial state is Set
+</pre></body></html>
diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/logic_legXpla3.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/logic_legXpla3.htm
new file mode 100644
index 0000000..c0e6f4a
--- /dev/null
+++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/logic_legXpla3.htm
@@ -0,0 +1,3 @@
+<html><body><pre>
+Legend: PU  - Pull Up
+</pre></body></html>
diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/logicleft.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/logicleft.htm
new file mode 100644
index 0000000..5da8011
--- /dev/null
+++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/logicleft.htm
@@ -0,0 +1,16 @@
+<html>
+<head>
+<meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+<script src="maplogic.js"></script><link rel="stylesheet" type="text/css" href="style.css">
+</head>
+<span id="maplog" class="pgRef"><h3 align="center">Unmapped Logic</h3>
+<table width="90%" border="1" cellpadding="0" cellspacing="0"><tr class="pgHeader">
+<th width="28%">Signal Name</th>
+<th align="center">Total Pterms</th>
+<th align="center">Total Inputs</th>
+<th align="center">User Assignment</th>
+</tr></table></span><form><span class="pgRef"><table width="90%" align="center"><tr>
+<td align="left"><input type="button" onclick="javascript:parent.leftnav.showTop()" onmouseover="window.status='goto top of page'; return true;" onmouseout="window.status=''" value="back to top"></td>
+<td align="right"><input type="button" onclick="window.print()" onmouseover="window.status='print page'; return true;" onmouseout="window.status=''" value="print page"></td>
+</tr></table></span></form>
+</html>
diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/logicleft.js b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/logicleft.js
new file mode 100644
index 0000000..2fa4142
--- /dev/null
+++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/logicleft.js
@@ -0,0 +1 @@
+function showLogicLeft() { parent.leftnav.showLogicLeft(); }
diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/logicleftdoc.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/logicleftdoc.htm
new file mode 100644
index 0000000..3537167
--- /dev/null
+++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/logicleftdoc.htm
@@ -0,0 +1,100 @@
+<!doctype html public "-//w3c//dtd html 4.0 transitional//en">
+<html>
+<head>
+   <meta http-equiv="Content-Type" content="text/html; charset=iso-8859-1">
+   <meta name="generator" content="RoboHELP by eHelp Corporation - www.ehelp.com">
+   <meta name="generator-major-version" content="0.1">
+   <meta name="generator-minor-version" content="1">
+   <meta name="filetype" content="kadov">
+   <meta name="filetype-version" content="1">
+   <meta name="page-count" content="1">
+   <meta name="layout-height" content="1506">
+   <meta name="layout-width" content="639">
+   <meta name="date" content="05 24, 2002 5:49:09 PM">
+   <meta name="GENERATOR" content="Mozilla/4.79 [en]C-CCK-MCD   (Windows NT 5.0; U) [Netscape]">
+   <title>Mapped Logic</title>
+<!--(==============================================================)-->
+<!--(Document created with RoboEditor. )============================-->
+<!--(==============================================================)-->
+<!--(Meta)==========================================================-->
+<style>
+<!--
+ul.whs1 {list-style: disc;}
+p.whs2 {margin-left: 80px;}
+ul.whs3 {list-style: disc;}
+p.whs4 {margin-left: 80px; font-family: arial, sans-serif; font-size: 10pt;}
+ul.whs5 {list-style: disc;}
+p.whs6 {margin-left: 80px; font-family: arial, sans-serif; font-size: 10pt;}
+p.whs7 {margin-left: 80px; font-family: arial, sans-serif; font-size: 10pt;}
+ul.whs8 {list-style: disc;}
+p.whs9 {margin-left: 80px; font-family: arial, sans-serif; font-size: 10pt;}
+p.whs10 {margin-left: 80px; font-family: arial, sans-serif; font-size: 10pt;}
+ul.whs11 {list-style: disc;}
+
+--></style>
+<script language="javascript" title="WebHelpInlineScript">
+<!--
+function reDo() {
+  if (innerWidth != origWidth || innerHeight != origHeight)
+     location.reload();
+}
+if ((parseInt(navigator.appVersion) == 4) && (navigator.appName == "Netscape")) {
+	origWidth = innerWidth;
+	origHeight = innerHeight;
+	onresize = reDo;
+}
+//-->
+</script>
+<style>
+<!--
+  div.WebHelpPopupMenu {position:absolute; left:0px; top:0px; z-index:4; visibility:hidden;}
+  p.WebHelpNavBar {text-align:right;}
+-->
+</style>
+<!--(Body)==========================================================-->
+</head>
+<body>
+
+<h1>
+Unmapped Logic</h1>
+<span style="font-family: arial, sans-serif; font-size: 10pt;"><font size=-1>The
+Unmapped Logic section provides a table listing all logic that failed to
+fit into the specified device. The page will appear in your browser sorted
+by Signal Name.&nbsp;</font></span><!--begin!kadov{{-->
+<br><!--}}end!kadov--><!--kadov_tag{{<implicit_p>}}--><!--begin!kadov{{-->
+<br><!--}}end!kadov--><!--kadov_tag{{<implicit_p>}}--><span 
+ style="font-family: arial, sans-serif; font-size: 10pt;"><font size=-1>The
+Mapped Logic table contains the following:&nbsp;</font></span>
+<ul type="disc" class="whs1">
+<li class="kadov-p" class="kadov-p">
+<span style="font-family: arial, sans-serif; font-size: 10pt;"><font size=-1>The
+signal name&nbsp;</font></span></li>
+</ul>
+
+<div class="whs2"><span style="font-weight: bold;
+											font-family: arial, sans-serif;
+											font-size: 10pt;"><font size=-1><b>Note:</span><span 
+ style="font-family: arial, sans-serif; font-size: 10pt;"></b>
+Clicking on the signal name will open a new window with the equations for
+that signal.&nbsp;</font></span></div>
+
+<ul type="disc" class="whs3">
+<li class="kadov-p" class="kadov-p">
+<span style="font-family: arial, sans-serif; font-size: 10pt;"><font size=-1>The
+total number of product terms&nbsp;</font></span></li>
+
+<li class="kadov-p" class="kadov-p">
+<span style="font-family: arial, sans-serif; font-size: 10pt;"><font size=-1>The
+total number of inputs&nbsp;</font></span></li>
+
+<li class="kadov-p" class="kadov-p">
+<span style="font-family: arial, sans-serif; font-size: 10pt;"><font size=-1>The
+I/O standard where appropriate</font></span></li>
+
+<li class="kadov-p" class="kadov-p">
+<span style="font-family: arial, sans-serif; font-size: 10pt;"><font size=-1>The
+Pin/FB Assignment specified by the user.</font></span></li>
+</ul>
+
+</body>
+</html>
diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/logiclegend.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/logiclegend.htm
new file mode 100644
index 0000000..7033b9e
--- /dev/null
+++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/logiclegend.htm
@@ -0,0 +1,106 @@
+<html>
+<head>
+<meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+<link rel="stylesheet" type="text/css" href="style.css">
+<script>
+      function showTop() { document.location.href = '#'; }
+    </script>
+</head>
+<body class="pgBgnd">
+<span id="legend" class="pgRef"><h3 align="center">Legends</h3>
+<table align="center" width="90%" border="0" cellpadding="0" cellspacing="0"><tr><td align="right"><form><input type="button" onclick="javascript:document.location.href='logiclegendV.htm'" value="verbose"></form></td></tr></table>
+<table align="center" width="90%" border="1" cellpadding="0" cellspacing="0">
+<tr>
+<th width="20%">Acronym</th>
+<th width="80%">Brief Description</th>
+</tr>
+<tr>
+<td width="20%"> *</td>
+<td width="80%"> User Assigned</td>
+</tr>
+<tr>
+<td width="20%"> (b)</td>
+<td width="80%"> Buried macrocell</td>
+</tr>
+<tr>
+<td width="20%"> FB#</td>
+<td width="80%"> Function Block number </td>
+</tr>
+<tr>
+<td width="20%"> GCK#</td>
+<td width="80%"> Global Clock number</td>
+</tr>
+<tr>
+<td width="20%"> GTS#</td>
+<td width="80%"> Global Output Enable number</td>
+</tr>
+<tr>
+<td width="20%"> GSR</td>
+<td width="80%"> Global Set/Reset</td>
+</tr>
+<tr>
+<td width="20%"> I</td>
+<td width="80%"> Input</td>
+</tr>
+<tr>
+<td width="20%"> I/O</td>
+<td width="80%"> Input/Output</td>
+</tr>
+<tr>
+<td width="20%"> Latch</td>
+<td width="80%"> Transparent latch</td>
+</tr>
+<tr>
+<td width="20%"> LOW</td>
+<td width="80%"> Low Power Mode</td>
+</tr>
+<tr>
+<td width="20%"> MC#</td>
+<td width="80%"> Macrocell number</td>
+</tr>
+<tr>
+<td width="20%"> O</td>
+<td width="80%"> Output</td>
+</tr>
+<tr>
+<td width="20%"> OD</td>
+<td width="80%"> Open Drain</td>
+</tr>
+<tr>
+<td width="20%"> PU</td>
+<td width="80%"> Pullup</td>
+</tr>
+<tr>
+<td width="20%"> /S</td>
+<td width="80%"> After any flop/latch type indicates initial state is Set</td>
+</tr>
+<tr>
+<td width="20%"> STD</td>
+<td width="80%"> Standard Power Mode</td>
+</tr>
+<tr>
+<td width="20%"> TCK</td>
+<td width="80%"> Test clock</td>
+</tr>
+<tr>
+<td width="20%"> TDI</td>
+<td width="80%"> Test data input</td>
+</tr>
+<tr>
+<td width="20%"> TDO</td>
+<td width="80%"> Test data output</td>
+</tr>
+<tr>
+<td width="20%"> TFF</td>
+<td width="80%"> Toggle Flip-Flop</td>
+</tr>
+<tr>
+<td width="20%"> TMS</td>
+<td width="80%"> Test mode select</td>
+</tr>
+</table></span><form><span class="pgRef"><table width="90%" align="center"><tr>
+<td align="left"><input type="button" onclick="showTop()" onmouseover="window.status='goto top of page'; return true;" onmouseout="window.status=''" value="back to top"></td>
+<td align="right"><input type="button" onclick="window.print()" onmouseover="window.status='print page'; return true;" onmouseout="window.status=''" value="print page"></td>
+</tr></table></span></form>
+</body>
+</html>
diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/logiclegendV.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/logiclegendV.htm
new file mode 100644
index 0000000..e1813d1
--- /dev/null
+++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/logiclegendV.htm
@@ -0,0 +1,106 @@
+<html>
+<head>
+<meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+<link rel="stylesheet" type="text/css" href="style.css">
+<script>
+      function showTop() { document.location.href = '#'; }
+    </script>
+</head>
+<body class="pgBgnd">
+<span id="legend" class="pgRef"><h3 align="center">Legends</h3>
+<table align="center" width="90%" border="0" cellpadding="0" cellspacing="0"><tr><td align="right"><form><input type="button" onclick="javascript:document.location.href='logiclegend.htm'" value="brief"></form></td></tr></table>
+<table align="center" width="90%" border="1" cellpadding="0" cellspacing="0">
+<tr>
+<th width="20%">Acronym</th>
+<th width="80%">Verbose Description</th>
+</tr>
+<tr>
+<td width="20%"> *</td>
+<td width="60%"> User Assigned</td>
+</tr>
+<tr>
+<td width="20%"> (b)</td>
+<td width="60%"> Buried macrocell</td>
+</tr>
+<tr>
+<td width="20%"> FB#</td>
+<td width="60%"> Function Block number</td>
+</tr>
+<tr>
+<td width="20%"> GCK#</td>
+<td width="60%"> Global Clock number</td>
+</tr>
+<tr>
+<td width="20%"> GTS#</td>
+<td width="60%"> Global Output Enable number</td>
+</tr>
+<tr>
+<td width="20%"> GSR</td>
+<td width="60%"> Global Set/Reset</td>
+</tr>
+<tr>
+<td width="20%"> I</td>
+<td width="60%"> Input</td>
+</tr>
+<tr>
+<td width="20%"> I/O</td>
+<td width="60%"> Input/Output</td>
+</tr>
+<tr>
+<td width="20%"> Latch</td>
+<td width="60%"> Transparent latch</td>
+</tr>
+<tr>
+<td width="20%"> LOW</td>
+<td width="60%"> Low Power Mode</td>
+</tr>
+<tr>
+<td width="20%"> MC#</td>
+<td width="60%"> Macrocell number</td>
+</tr>
+<tr>
+<td width="20%"> O</td>
+<td width="60%"> Output</td>
+</tr>
+<tr>
+<td width="20%"> OD</td>
+<td width="60%"> Open Drain</td>
+</tr>
+<tr>
+<td width="20%"> PU</td>
+<td width="60%"> Pullup</td>
+</tr>
+<tr>
+<td width="20%"> /S</td>
+<td width="60%"> After any flop/latch type indicates initial state is Set</td>
+</tr>
+<tr>
+<td width="20%"> STD</td>
+<td width="60%"> Standard Power Mode</td>
+</tr>
+<tr>
+<td width="20%"> TCK</td>
+<td width="60%"> One of four terminals required by (JTAG) IEEE Std 1149 or IEEE Std 1532.  Test operations of the device are synchronous to TCK.  Data is captured on the rising edge of TCK and outputs change on the falling edge of TCK.  An internal pull-up forces TCK to a high level if left unconnected.</td>
+</tr>
+<tr>
+<td width="20%"> TDI</td>
+<td width="60%"> One of four terminals required by (JTAG) IEEE Std 1149 or IEEE Std 1532. It is the serial input for shifting data through the instruction register or selected data register.  An internal pull-up forces TDI to a high level if left unconnected.</td>
+</tr>
+<tr>
+<td width="20%"> TDO</td>
+<td width="60%"> One of four terminals required by (JTAG) IEEE Std 1149 or IEEE Std 1532. It is the serial output for shifting data through the instruction register or selected data register.  An internal pull-up forces TDI to a high level when it is not driven from an external source.</td>
+</tr>
+<tr>
+<td width="20%"> TFF</td>
+<td width="60%"> Toggle Flip-Flop</td>
+</tr>
+<tr>
+<td width="20%"> TMS</td>
+<td width="60%"> One of four terminals required by (JTAG) IEEE Std 1149 or IEEE Std 1532. It directs the device through its Test Access Port controller states.  An internal pull-up forces TDI to a high level when it is not driven from an external source.  TMS also provides the optional test reset signal of IEEE Std 1149 or IEEE Std 1532.  </td>
+</tr>
+</table></span><form><span class="pgRef"><table width="90%" align="center"><tr>
+<td align="left"><input type="button" onclick="showTop()" onmouseover="window.status='goto top of page'; return true;" onmouseout="window.status=''" value="back to top"></td>
+<td align="right"><input type="button" onclick="window.print()" onmouseover="window.status='print page'; return true;" onmouseout="window.status=''" value="print page"></td>
+</tr></table></span></form>
+</body>
+</html>
diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/macrocell.gif b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/macrocell.gif
new file mode 100644
index 0000000..ec9e68e
Binary files /dev/null and b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/macrocell.gif differ
diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/mapinput_00.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/mapinput_00.htm
new file mode 100644
index 0000000..1aafeda
--- /dev/null
+++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/mapinput_00.htm
@@ -0,0 +1,240 @@
+<html>
+<head>
+<meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+<script src="maplogic.js"></script><link rel="stylesheet" type="text/css" href="style.css">
+</head>
+<body class="pgBgnd" id="XC95144XL">
+<span id="mapin" class="pgRef"><h3 align="center">Inputs</h3>
+<table width="90%" border="1" cellpadding="0" cellspacing="0">
+<tr class="pgHeader">
+<th width="60%"><a href="javascript:Sort(10);">Signal Name</a></th>
+<th><a href="javascript:Sort(11);">Function Block</a></th>
+<th align="center">Macrocell</th>
+<th><a href="javascript:Sort(12);">Pin Number</a></th>
+<th align="center">Pin Type</th>
+<th align="center">Pin Use</th>
+</tr>
+<tr>
+<td width="60%">A&lt;10&gt;</td>
+<td align="center"><a href="javascript:showFB('FB5')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB5</a></td>
+<td align="center">MC3</td>
+<td align="center">59</td>
+<td align="center">I/O</td>
+<td align="center">I</td>
+</tr>
+<tr>
+<td width="60%">A&lt;11&gt;</td>
+<td align="center"><a href="javascript:showFB('FB5')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB5</a></td>
+<td align="center">MC12</td>
+<td align="center">60</td>
+<td align="center">I/O</td>
+<td align="center">I</td>
+</tr>
+<tr>
+<td width="60%">A&lt;12&gt;</td>
+<td align="center"><a href="javascript:showFB('FB5')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB5</a></td>
+<td align="center">MC14</td>
+<td align="center">61</td>
+<td align="center">I/O</td>
+<td align="center">I</td>
+</tr>
+<tr>
+<td width="60%">A&lt;13&gt;</td>
+<td align="center"><a href="javascript:showFB('FB5')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB5</a></td>
+<td align="center">MC15</td>
+<td align="center">64</td>
+<td align="center">I/O</td>
+<td align="center">I</td>
+</tr>
+<tr>
+<td width="60%">A&lt;16&gt;</td>
+<td align="center"><a href="javascript:showFB('FB8')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB8</a></td>
+<td align="center">MC4</td>
+<td align="center">97</td>
+<td align="center">I/O</td>
+<td align="center">I</td>
+</tr>
+<tr>
+<td width="60%">A&lt;17&gt;</td>
+<td align="center"><a href="javascript:showFB('FB8')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB8</a></td>
+<td align="center">MC3</td>
+<td align="center">95</td>
+<td align="center">I/O</td>
+<td align="center">I</td>
+</tr>
+<tr>
+<td width="60%">A&lt;18&gt;</td>
+<td align="center"><a href="javascript:showFB('FB8')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB8</a></td>
+<td align="center">MC8</td>
+<td align="center">94</td>
+<td align="center">I/O</td>
+<td align="center">I</td>
+</tr>
+<tr>
+<td width="60%">A&lt;19&gt;</td>
+<td align="center"><a href="javascript:showFB('FB8')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB8</a></td>
+<td align="center">MC5</td>
+<td align="center">92</td>
+<td align="center">I/O</td>
+<td align="center">I</td>
+</tr>
+<tr>
+<td width="60%">A&lt;1&gt;</td>
+<td align="center"><a href="javascript:showFB('FB5')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB5</a></td>
+<td align="center">MC9</td>
+<td align="center">57</td>
+<td align="center">I/O</td>
+<td align="center">I</td>
+</tr>
+<tr>
+<td width="60%">A&lt;20&gt;</td>
+<td align="center"><a href="javascript:showFB('FB8')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB8</a></td>
+<td align="center">MC2</td>
+<td align="center">91</td>
+<td align="center">I/O</td>
+<td align="center">I</td>
+</tr>
+<tr>
+<td width="60%">A&lt;21&gt;</td>
+<td align="center"><a href="javascript:showFB('FB7')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB7</a></td>
+<td align="center">MC17</td>
+<td align="center">88</td>
+<td align="center">I/O</td>
+<td align="center">I</td>
+</tr>
+<tr>
+<td width="60%">A&lt;22&gt;</td>
+<td align="center"><a href="javascript:showFB('FB7')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB7</a></td>
+<td align="center">MC15</td>
+<td align="center">87</td>
+<td align="center">I/O</td>
+<td align="center">I</td>
+</tr>
+<tr>
+<td width="60%">A&lt;23&gt;</td>
+<td align="center"><a href="javascript:showFB('FB7')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB7</a></td>
+<td align="center">MC14</td>
+<td align="center">86</td>
+<td align="center">I/O</td>
+<td align="center">I</td>
+</tr>
+<tr>
+<td width="60%">A&lt;2&gt;</td>
+<td align="center"><a href="javascript:showFB('FB5')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB5</a></td>
+<td align="center">MC6</td>
+<td align="center">54</td>
+<td align="center">I/O</td>
+<td align="center">I</td>
+</tr>
+<tr>
+<td width="60%">A&lt;3&gt;</td>
+<td align="center"><a href="javascript:showFB('FB5')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB5</a></td>
+<td align="center">MC2</td>
+<td align="center">52</td>
+<td align="center">I/O</td>
+<td align="center">I</td>
+</tr>
+<tr>
+<td width="60%">A&lt;4&gt;</td>
+<td align="center"><a href="javascript:showFB('FB3')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB3</a></td>
+<td align="center">MC15</td>
+<td align="center">50</td>
+<td align="center">I/O</td>
+<td align="center">I</td>
+</tr>
+<tr>
+<td width="60%">A&lt;5&gt;</td>
+<td align="center"><a href="javascript:showFB('FB3')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB3</a></td>
+<td align="center">MC14</td>
+<td align="center">49</td>
+<td align="center">I/O</td>
+<td align="center">I</td>
+</tr>
+<tr>
+<td width="60%">A&lt;6&gt;</td>
+<td align="center"><a href="javascript:showFB('FB3')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB3</a></td>
+<td align="center">MC17</td>
+<td align="center">51</td>
+<td align="center">I/O</td>
+<td align="center">I</td>
+</tr>
+<tr>
+<td width="60%">A&lt;9&gt;</td>
+<td align="center"><a href="javascript:showFB('FB5')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB5</a></td>
+<td align="center">MC11</td>
+<td align="center">58</td>
+<td align="center">I/O</td>
+<td align="center">I</td>
+</tr>
+<tr>
+<td width="60%">AS</td>
+<td align="center"><a href="javascript:showFB('FB7')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB7</a></td>
+<td align="center">MC9</td>
+<td align="center">80</td>
+<td align="center">I/O</td>
+<td align="center">I</td>
+</tr>
+<tr>
+<td width="60%">AUTOBOOT_OFF</td>
+<td align="center"><a href="javascript:showFB('FB7')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB7</a></td>
+<td align="center">MC3</td>
+<td align="center">75</td>
+<td align="center">I/O</td>
+<td align="center">I</td>
+</tr>
+<tr>
+<td width="60%">BERR</td>
+<td align="center"><a href="javascript:showFB('FB8')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB8</a></td>
+<td align="center">MC11</td>
+<td align="center">98</td>
+<td align="center">I/O</td>
+<td align="center">I</td>
+</tr>
+<tr>
+<td width="60%">C1</td>
+<td align="center"><a href="javascript:showFB('FB8')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB8</a></td>
+<td align="center">MC13</td>
+<td align="center">103</td>
+<td align="center">I/O</td>
+<td align="center">I</td>
+</tr>
+<tr>
+<td width="60%">C3</td>
+<td align="center"><a href="javascript:showFB('FB8')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB8</a></td>
+<td align="center">MC14</td>
+<td align="center">102</td>
+<td align="center">I/O</td>
+<td align="center">I</td>
+</tr>
+<tr>
+<td width="60%">RESET</td>
+<td align="center"><a href="javascript:showFB('FB2')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB2</a></td>
+<td align="center">MC2</td>
+<td align="center">143</td>
+<td align="center">I/O/GSR</td>
+<td align="center">GSR/I</td>
+</tr>
+<tr>
+<td width="60%">RW</td>
+<td align="center"><a href="javascript:showFB('FB7')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB7</a></td>
+<td align="center">MC16</td>
+<td align="center">83</td>
+<td align="center">I/O</td>
+<td align="center">I</td>
+</tr>
+<tr>
+<td width="60%">UDS</td>
+<td align="center"><a href="javascript:showFB('FB7')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB7</a></td>
+<td align="center">MC13</td>
+<td align="center">81</td>
+<td align="center">I/O</td>
+<td align="center">I</td>
+</tr>
+</table></span><form><span class="pgRef"><table width="90%" align="center"><tr>
+<td align="left"><input type="button" onclick="javascript:parent.leftnav.showTop()" onmouseover="window.status='goto top of page'; return true;" onmouseout="window.status=''" value="back to top"></td>
+<td align="right">
+<input type="button" onclick="javascript:showLegend('logiclegend.htm')" onmouseover="window.status='show Legend'; return true;" onmouseout="window.status=''" value="legend"><input type="button" onclick="window.print()" onmouseover="window.status='print page'; return true;" onmouseout="window.status=''" value="print page">
+</td>
+</tr></table></span></form>
+</body>
+</html>
diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/mapinput_01.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/mapinput_01.htm
new file mode 100644
index 0000000..078acde
--- /dev/null
+++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/mapinput_01.htm
@@ -0,0 +1,240 @@
+<html>
+<head>
+<meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+<script src="maplogic.js"></script><link rel="stylesheet" type="text/css" href="style.css">
+</head>
+<body class="pgBgnd" id="XC95144XL">
+<span id="mapin" class="pgRef"><h3 align="center">Inputs</h3>
+<table width="90%" border="1" cellpadding="0" cellspacing="0">
+<tr class="pgHeader">
+<th width="60%"><a href="javascript:Sort(10);">Signal Name</a></th>
+<th><a href="javascript:Sort(11);">Function Block</a></th>
+<th align="center">Macrocell</th>
+<th><a href="javascript:Sort(12);">Pin Number</a></th>
+<th align="center">Pin Type</th>
+<th align="center">Pin Use</th>
+</tr>
+<tr>
+<td width="60%">RESET</td>
+<td align="center"><a href="javascript:showFB('FB2')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB2</a></td>
+<td align="center">MC2</td>
+<td align="center">143</td>
+<td align="center">I/O/GSR</td>
+<td align="center">GSR/I</td>
+</tr>
+<tr>
+<td width="60%">A&lt;5&gt;</td>
+<td align="center"><a href="javascript:showFB('FB3')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB3</a></td>
+<td align="center">MC14</td>
+<td align="center">49</td>
+<td align="center">I/O</td>
+<td align="center">I</td>
+</tr>
+<tr>
+<td width="60%">A&lt;4&gt;</td>
+<td align="center"><a href="javascript:showFB('FB3')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB3</a></td>
+<td align="center">MC15</td>
+<td align="center">50</td>
+<td align="center">I/O</td>
+<td align="center">I</td>
+</tr>
+<tr>
+<td width="60%">A&lt;6&gt;</td>
+<td align="center"><a href="javascript:showFB('FB3')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB3</a></td>
+<td align="center">MC17</td>
+<td align="center">51</td>
+<td align="center">I/O</td>
+<td align="center">I</td>
+</tr>
+<tr>
+<td width="60%">A&lt;3&gt;</td>
+<td align="center"><a href="javascript:showFB('FB5')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB5</a></td>
+<td align="center">MC2</td>
+<td align="center">52</td>
+<td align="center">I/O</td>
+<td align="center">I</td>
+</tr>
+<tr>
+<td width="60%">A&lt;10&gt;</td>
+<td align="center"><a href="javascript:showFB('FB5')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB5</a></td>
+<td align="center">MC3</td>
+<td align="center">59</td>
+<td align="center">I/O</td>
+<td align="center">I</td>
+</tr>
+<tr>
+<td width="60%">A&lt;2&gt;</td>
+<td align="center"><a href="javascript:showFB('FB5')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB5</a></td>
+<td align="center">MC6</td>
+<td align="center">54</td>
+<td align="center">I/O</td>
+<td align="center">I</td>
+</tr>
+<tr>
+<td width="60%">A&lt;1&gt;</td>
+<td align="center"><a href="javascript:showFB('FB5')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB5</a></td>
+<td align="center">MC9</td>
+<td align="center">57</td>
+<td align="center">I/O</td>
+<td align="center">I</td>
+</tr>
+<tr>
+<td width="60%">A&lt;9&gt;</td>
+<td align="center"><a href="javascript:showFB('FB5')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB5</a></td>
+<td align="center">MC11</td>
+<td align="center">58</td>
+<td align="center">I/O</td>
+<td align="center">I</td>
+</tr>
+<tr>
+<td width="60%">A&lt;11&gt;</td>
+<td align="center"><a href="javascript:showFB('FB5')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB5</a></td>
+<td align="center">MC12</td>
+<td align="center">60</td>
+<td align="center">I/O</td>
+<td align="center">I</td>
+</tr>
+<tr>
+<td width="60%">A&lt;12&gt;</td>
+<td align="center"><a href="javascript:showFB('FB5')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB5</a></td>
+<td align="center">MC14</td>
+<td align="center">61</td>
+<td align="center">I/O</td>
+<td align="center">I</td>
+</tr>
+<tr>
+<td width="60%">A&lt;13&gt;</td>
+<td align="center"><a href="javascript:showFB('FB5')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB5</a></td>
+<td align="center">MC15</td>
+<td align="center">64</td>
+<td align="center">I/O</td>
+<td align="center">I</td>
+</tr>
+<tr>
+<td width="60%">AUTOBOOT_OFF</td>
+<td align="center"><a href="javascript:showFB('FB7')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB7</a></td>
+<td align="center">MC3</td>
+<td align="center">75</td>
+<td align="center">I/O</td>
+<td align="center">I</td>
+</tr>
+<tr>
+<td width="60%">AS</td>
+<td align="center"><a href="javascript:showFB('FB7')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB7</a></td>
+<td align="center">MC9</td>
+<td align="center">80</td>
+<td align="center">I/O</td>
+<td align="center">I</td>
+</tr>
+<tr>
+<td width="60%">UDS</td>
+<td align="center"><a href="javascript:showFB('FB7')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB7</a></td>
+<td align="center">MC13</td>
+<td align="center">81</td>
+<td align="center">I/O</td>
+<td align="center">I</td>
+</tr>
+<tr>
+<td width="60%">A&lt;23&gt;</td>
+<td align="center"><a href="javascript:showFB('FB7')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB7</a></td>
+<td align="center">MC14</td>
+<td align="center">86</td>
+<td align="center">I/O</td>
+<td align="center">I</td>
+</tr>
+<tr>
+<td width="60%">A&lt;22&gt;</td>
+<td align="center"><a href="javascript:showFB('FB7')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB7</a></td>
+<td align="center">MC15</td>
+<td align="center">87</td>
+<td align="center">I/O</td>
+<td align="center">I</td>
+</tr>
+<tr>
+<td width="60%">RW</td>
+<td align="center"><a href="javascript:showFB('FB7')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB7</a></td>
+<td align="center">MC16</td>
+<td align="center">83</td>
+<td align="center">I/O</td>
+<td align="center">I</td>
+</tr>
+<tr>
+<td width="60%">A&lt;21&gt;</td>
+<td align="center"><a href="javascript:showFB('FB7')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB7</a></td>
+<td align="center">MC17</td>
+<td align="center">88</td>
+<td align="center">I/O</td>
+<td align="center">I</td>
+</tr>
+<tr>
+<td width="60%">A&lt;20&gt;</td>
+<td align="center"><a href="javascript:showFB('FB8')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB8</a></td>
+<td align="center">MC2</td>
+<td align="center">91</td>
+<td align="center">I/O</td>
+<td align="center">I</td>
+</tr>
+<tr>
+<td width="60%">A&lt;17&gt;</td>
+<td align="center"><a href="javascript:showFB('FB8')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB8</a></td>
+<td align="center">MC3</td>
+<td align="center">95</td>
+<td align="center">I/O</td>
+<td align="center">I</td>
+</tr>
+<tr>
+<td width="60%">A&lt;16&gt;</td>
+<td align="center"><a href="javascript:showFB('FB8')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB8</a></td>
+<td align="center">MC4</td>
+<td align="center">97</td>
+<td align="center">I/O</td>
+<td align="center">I</td>
+</tr>
+<tr>
+<td width="60%">A&lt;19&gt;</td>
+<td align="center"><a href="javascript:showFB('FB8')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB8</a></td>
+<td align="center">MC5</td>
+<td align="center">92</td>
+<td align="center">I/O</td>
+<td align="center">I</td>
+</tr>
+<tr>
+<td width="60%">A&lt;18&gt;</td>
+<td align="center"><a href="javascript:showFB('FB8')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB8</a></td>
+<td align="center">MC8</td>
+<td align="center">94</td>
+<td align="center">I/O</td>
+<td align="center">I</td>
+</tr>
+<tr>
+<td width="60%">BERR</td>
+<td align="center"><a href="javascript:showFB('FB8')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB8</a></td>
+<td align="center">MC11</td>
+<td align="center">98</td>
+<td align="center">I/O</td>
+<td align="center">I</td>
+</tr>
+<tr>
+<td width="60%">C1</td>
+<td align="center"><a href="javascript:showFB('FB8')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB8</a></td>
+<td align="center">MC13</td>
+<td align="center">103</td>
+<td align="center">I/O</td>
+<td align="center">I</td>
+</tr>
+<tr>
+<td width="60%">C3</td>
+<td align="center"><a href="javascript:showFB('FB8')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB8</a></td>
+<td align="center">MC14</td>
+<td align="center">102</td>
+<td align="center">I/O</td>
+<td align="center">I</td>
+</tr>
+</table></span><form><span class="pgRef"><table width="90%" align="center"><tr>
+<td align="left"><input type="button" onclick="javascript:parent.leftnav.showTop()" onmouseover="window.status='goto top of page'; return true;" onmouseout="window.status=''" value="back to top"></td>
+<td align="right">
+<input type="button" onclick="javascript:showLegend('logiclegend.htm')" onmouseover="window.status='show Legend'; return true;" onmouseout="window.status=''" value="legend"><input type="button" onclick="window.print()" onmouseover="window.status='print page'; return true;" onmouseout="window.status=''" value="print page">
+</td>
+</tr></table></span></form>
+</body>
+</html>
diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/mapinput_02.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/mapinput_02.htm
new file mode 100644
index 0000000..cfc0057
--- /dev/null
+++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/mapinput_02.htm
@@ -0,0 +1,240 @@
+<html>
+<head>
+<meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+<script src="maplogic.js"></script><link rel="stylesheet" type="text/css" href="style.css">
+</head>
+<body class="pgBgnd" id="XC95144XL">
+<span id="mapin" class="pgRef"><h3 align="center">Inputs</h3>
+<table width="90%" border="1" cellpadding="0" cellspacing="0">
+<tr class="pgHeader">
+<th width="60%"><a href="javascript:Sort(10);">Signal Name</a></th>
+<th><a href="javascript:Sort(11);">Function Block</a></th>
+<th align="center">Macrocell</th>
+<th><a href="javascript:Sort(12);">Pin Number</a></th>
+<th align="center">Pin Type</th>
+<th align="center">Pin Use</th>
+</tr>
+<tr>
+<td width="60%">A&lt;5&gt;</td>
+<td align="center"><a href="javascript:showFB('FB3')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB3</a></td>
+<td align="center">MC14</td>
+<td align="center">49</td>
+<td align="center">I/O</td>
+<td align="center">I</td>
+</tr>
+<tr>
+<td width="60%">A&lt;4&gt;</td>
+<td align="center"><a href="javascript:showFB('FB3')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB3</a></td>
+<td align="center">MC15</td>
+<td align="center">50</td>
+<td align="center">I/O</td>
+<td align="center">I</td>
+</tr>
+<tr>
+<td width="60%">A&lt;6&gt;</td>
+<td align="center"><a href="javascript:showFB('FB3')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB3</a></td>
+<td align="center">MC17</td>
+<td align="center">51</td>
+<td align="center">I/O</td>
+<td align="center">I</td>
+</tr>
+<tr>
+<td width="60%">A&lt;3&gt;</td>
+<td align="center"><a href="javascript:showFB('FB5')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB5</a></td>
+<td align="center">MC2</td>
+<td align="center">52</td>
+<td align="center">I/O</td>
+<td align="center">I</td>
+</tr>
+<tr>
+<td width="60%">A&lt;2&gt;</td>
+<td align="center"><a href="javascript:showFB('FB5')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB5</a></td>
+<td align="center">MC6</td>
+<td align="center">54</td>
+<td align="center">I/O</td>
+<td align="center">I</td>
+</tr>
+<tr>
+<td width="60%">A&lt;1&gt;</td>
+<td align="center"><a href="javascript:showFB('FB5')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB5</a></td>
+<td align="center">MC9</td>
+<td align="center">57</td>
+<td align="center">I/O</td>
+<td align="center">I</td>
+</tr>
+<tr>
+<td width="60%">A&lt;9&gt;</td>
+<td align="center"><a href="javascript:showFB('FB5')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB5</a></td>
+<td align="center">MC11</td>
+<td align="center">58</td>
+<td align="center">I/O</td>
+<td align="center">I</td>
+</tr>
+<tr>
+<td width="60%">A&lt;10&gt;</td>
+<td align="center"><a href="javascript:showFB('FB5')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB5</a></td>
+<td align="center">MC3</td>
+<td align="center">59</td>
+<td align="center">I/O</td>
+<td align="center">I</td>
+</tr>
+<tr>
+<td width="60%">A&lt;11&gt;</td>
+<td align="center"><a href="javascript:showFB('FB5')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB5</a></td>
+<td align="center">MC12</td>
+<td align="center">60</td>
+<td align="center">I/O</td>
+<td align="center">I</td>
+</tr>
+<tr>
+<td width="60%">A&lt;12&gt;</td>
+<td align="center"><a href="javascript:showFB('FB5')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB5</a></td>
+<td align="center">MC14</td>
+<td align="center">61</td>
+<td align="center">I/O</td>
+<td align="center">I</td>
+</tr>
+<tr>
+<td width="60%">A&lt;13&gt;</td>
+<td align="center"><a href="javascript:showFB('FB5')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB5</a></td>
+<td align="center">MC15</td>
+<td align="center">64</td>
+<td align="center">I/O</td>
+<td align="center">I</td>
+</tr>
+<tr>
+<td width="60%">AUTOBOOT_OFF</td>
+<td align="center"><a href="javascript:showFB('FB7')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB7</a></td>
+<td align="center">MC3</td>
+<td align="center">75</td>
+<td align="center">I/O</td>
+<td align="center">I</td>
+</tr>
+<tr>
+<td width="60%">AS</td>
+<td align="center"><a href="javascript:showFB('FB7')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB7</a></td>
+<td align="center">MC9</td>
+<td align="center">80</td>
+<td align="center">I/O</td>
+<td align="center">I</td>
+</tr>
+<tr>
+<td width="60%">UDS</td>
+<td align="center"><a href="javascript:showFB('FB7')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB7</a></td>
+<td align="center">MC13</td>
+<td align="center">81</td>
+<td align="center">I/O</td>
+<td align="center">I</td>
+</tr>
+<tr>
+<td width="60%">RW</td>
+<td align="center"><a href="javascript:showFB('FB7')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB7</a></td>
+<td align="center">MC16</td>
+<td align="center">83</td>
+<td align="center">I/O</td>
+<td align="center">I</td>
+</tr>
+<tr>
+<td width="60%">A&lt;23&gt;</td>
+<td align="center"><a href="javascript:showFB('FB7')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB7</a></td>
+<td align="center">MC14</td>
+<td align="center">86</td>
+<td align="center">I/O</td>
+<td align="center">I</td>
+</tr>
+<tr>
+<td width="60%">A&lt;22&gt;</td>
+<td align="center"><a href="javascript:showFB('FB7')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB7</a></td>
+<td align="center">MC15</td>
+<td align="center">87</td>
+<td align="center">I/O</td>
+<td align="center">I</td>
+</tr>
+<tr>
+<td width="60%">A&lt;21&gt;</td>
+<td align="center"><a href="javascript:showFB('FB7')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB7</a></td>
+<td align="center">MC17</td>
+<td align="center">88</td>
+<td align="center">I/O</td>
+<td align="center">I</td>
+</tr>
+<tr>
+<td width="60%">A&lt;20&gt;</td>
+<td align="center"><a href="javascript:showFB('FB8')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB8</a></td>
+<td align="center">MC2</td>
+<td align="center">91</td>
+<td align="center">I/O</td>
+<td align="center">I</td>
+</tr>
+<tr>
+<td width="60%">A&lt;19&gt;</td>
+<td align="center"><a href="javascript:showFB('FB8')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB8</a></td>
+<td align="center">MC5</td>
+<td align="center">92</td>
+<td align="center">I/O</td>
+<td align="center">I</td>
+</tr>
+<tr>
+<td width="60%">A&lt;18&gt;</td>
+<td align="center"><a href="javascript:showFB('FB8')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB8</a></td>
+<td align="center">MC8</td>
+<td align="center">94</td>
+<td align="center">I/O</td>
+<td align="center">I</td>
+</tr>
+<tr>
+<td width="60%">A&lt;17&gt;</td>
+<td align="center"><a href="javascript:showFB('FB8')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB8</a></td>
+<td align="center">MC3</td>
+<td align="center">95</td>
+<td align="center">I/O</td>
+<td align="center">I</td>
+</tr>
+<tr>
+<td width="60%">A&lt;16&gt;</td>
+<td align="center"><a href="javascript:showFB('FB8')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB8</a></td>
+<td align="center">MC4</td>
+<td align="center">97</td>
+<td align="center">I/O</td>
+<td align="center">I</td>
+</tr>
+<tr>
+<td width="60%">BERR</td>
+<td align="center"><a href="javascript:showFB('FB8')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB8</a></td>
+<td align="center">MC11</td>
+<td align="center">98</td>
+<td align="center">I/O</td>
+<td align="center">I</td>
+</tr>
+<tr>
+<td width="60%">C3</td>
+<td align="center"><a href="javascript:showFB('FB8')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB8</a></td>
+<td align="center">MC14</td>
+<td align="center">102</td>
+<td align="center">I/O</td>
+<td align="center">I</td>
+</tr>
+<tr>
+<td width="60%">C1</td>
+<td align="center"><a href="javascript:showFB('FB8')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB8</a></td>
+<td align="center">MC13</td>
+<td align="center">103</td>
+<td align="center">I/O</td>
+<td align="center">I</td>
+</tr>
+<tr>
+<td width="60%">RESET</td>
+<td align="center"><a href="javascript:showFB('FB2')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB2</a></td>
+<td align="center">MC2</td>
+<td align="center">143</td>
+<td align="center">I/O/GSR</td>
+<td align="center">GSR/I</td>
+</tr>
+</table></span><form><span class="pgRef"><table width="90%" align="center"><tr>
+<td align="left"><input type="button" onclick="javascript:parent.leftnav.showTop()" onmouseover="window.status='goto top of page'; return true;" onmouseout="window.status=''" value="back to top"></td>
+<td align="right">
+<input type="button" onclick="javascript:showLegend('logiclegend.htm')" onmouseover="window.status='show Legend'; return true;" onmouseout="window.status=''" value="legend"><input type="button" onclick="window.print()" onmouseover="window.status='print page'; return true;" onmouseout="window.status=''" value="print page">
+</td>
+</tr></table></span></form>
+</body>
+</html>
diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/mapinputdoc.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/mapinputdoc.htm
new file mode 100644
index 0000000..3ac20d8
--- /dev/null
+++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/mapinputdoc.htm
@@ -0,0 +1,147 @@
+<!doctype html public "-//w3c//dtd html 4.0 transitional//en">
+<html>
+<head>
+   <meta http-equiv="Content-Type" content="text/html; charset=iso-8859-1">
+   <meta name="generator" content="RoboHELP by eHelp Corporation - www.ehelp.com">
+   <meta name="generator-major-version" content="0.1">
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+   <meta name="layout-width" content="615">
+   <meta name="date" content="05 24, 2002 5:49:24 PM">
+   <meta name="GENERATOR" content="Mozilla/4.79 [en]C-CCK-MCD   (Windows NT 5.0; U) [Netscape]">
+   <title>Mapped Inputs</title>
+<!--(==============================================================)-->
+<!--(Document created with RoboEditor. )============================-->
+<!--(==============================================================)-->
+<!--(Meta)==========================================================-->
+<style>
+<!--
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+<!--(Body)==========================================================-->
+</head>
+<body>
+
+<h1>
+Mapped Inputs</h1>
+<span style="font-family: arial, sans-serif; font-size: 10pt;"><font size=-1>Like
+the <a href="maplogicdoc.htm">Mapped Logic</a> section, the Mapped Inputs
+section of the report displays a table detailing the resources allocated
+by the fitter to mapped inputs.&nbsp;<!--kadov_tag{{<spaces>}}--><!--kadov_tag{{</spaces>}}-->Again,
+the table can be sorted by Signal Name, Function Block, or Pin Number by
+clicking on the appropriate table headings.&nbsp;</font><!--kadov_tag{{<spaces>}}--></span><!--kadov_tag{{</spaces>}}--><!--begin!kadov{{-->
+<br><!--}}end!kadov--><!--kadov_tag{{<implicit_p>}}--><!--begin!kadov{{-->
+<br><!--}}end!kadov--><!--kadov_tag{{<implicit_p>}}--><span 
+ style="font-family: arial, sans-serif; font-size: 10pt;"><font size=-1>The
+inputs table contains the following:&nbsp;</font></span>
+<ul type="disc" class="whs1">
+<li class="kadov-p" class="kadov-p">
+<span style="font-family: arial, sans-serif; font-size: 10pt;"><font size=-1>The
+input signal name&nbsp;</font></span></li>
+
+<li class="kadov-p" class="kadov-p">
+<span style="font-family: arial, sans-serif; font-size: 10pt;"><font size=-1>The
+function block number - an asterisk "*" indicates a user assignment</font></span></li>
+</ul>
+
+<div class="whs2"><span style="font-weight: bold;"><b>Note:</span></b>
+Clicking on the function block will provide a detailed table of all the
+block's resources and a graphical display of the function block diagram
+(see <a href="fbs_FBdoc.htm">Function Block Specifics</a> for more details).</div>
+
+<ul type="disc" class="whs3">
+<li class="kadov-p" class="kadov-p">
+<span style="font-family: arial, sans-serif; font-size: 10pt;"><font size=-1>The
+macrocell number</font></span></li>
+</ul>
+
+<ul type="disc" class="whs4">
+<div class="whs5"><span style="font-family: arial, sans-serif; font-size: 10pt;"><span 
+ style="font-family: arial, sans-serif; font-size: 10pt;"><span style="font-weight: bold;"><font size=-1><b>N</span></b>ote:</span>
+Clicking on the underscored macrocell number will provide a graphical display
+of the macrocell that looks like this:</font></span></div>
+
+<div class="kadov-p" class="kadov-p"><script LANGUAGE="JavaScript"><!--
+if (navigator.appName=="Netscape")
+{ document.write("<img src='macrocell.gif' x-maintain-ratio='TRUE' width='540' height='420' border='0'>");}
+else
+{ document.write("<img src='macrocell.gif' x-maintain-ratio='TRUE' style='border: none; width: 540px; height: 420px; float: none;' width='540' height='420' border='0'>");}
+//--></script>
+</div>
+
+<div class="kadov-p" class="kadov-p"></div>&nbsp;
+
+<li class="kadov-p" class="kadov-p">
+<span style="font-family: arial, sans-serif; font-size: 10pt;"><font size=-1>The
+pin number - an asterisk "*" indicates a user assignment</font></span></li>
+</ul>
+
+<div class="whs6"><span style="font-weight: bold;"><b>Note:</span><span 
+ style="font-family: arial, sans-serif; font-size: 10pt;"></b><font size=-1>
+Clicking on the underscored pin number will provide the pin layout diagram
+for the highlighted pin.&nbsp;<!--kadov_tag{{<spaces>}}--><!--kadov_tag{{</spaces>}}-->Rolling
+your mouse over the colored pin will pop up a tooltip with the signal name
+assigned to the pin, the I/O standard,&nbsp;<!--kadov_tag{{<spaces>}}--><!--kadov_tag{{</spaces>}}-->the
+I/O style, the slew rate, and/or any constraints assigned to the pin:</font></span></div>
+
+
+<p class="whs7"><script LANGUAGE="JavaScript"><!--
+if (navigator.appName=="Netscape")
+{ document.write("<img src='pin.gif' x-maintain-ratio='TRUE' width='309' height='312' border='0'>");}
+else
+{ document.write("<img src='pin.gif' x-maintain-ratio='TRUE' style='border: none; width: 309px; height: 312px; float: none;' width='309' height='312' border='0'>");}
+//--></script>
+
+<div class="whs8"></div>&nbsp;
+
+<ul type="disc" class="whs9">
+<li class="kadov-p" class="kadov-p">
+<span style="font-family: arial, sans-serif; font-size: 10pt;"><font size=-1>The
+pin type</font></span></li>
+
+<li class="kadov-p" class="kadov-p">
+<span style="font-family: arial, sans-serif; font-size: 10pt;"><font size=-1>The
+pin use&nbsp;</font></span></li>
+
+<li class="kadov-p" class="kadov-p">
+<span style="font-family: arial, sans-serif; font-size: 10pt;"><font size=-1>The
+I/O standard</font></span></li>
+
+<li class="kadov-p" class="kadov-p">
+<span style="font-family: arial, sans-serif; font-size: 10pt;"><font size=-1>The
+I/O style</font></span></li>
+</ul>
+
+</body>
+</html>
diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/maplogic.js b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/maplogic.js
new file mode 100644
index 0000000..e40c8f2
--- /dev/null
+++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/maplogic.js
@@ -0,0 +1,23 @@
+function showFB(fb) { parent.leftnav.showFB(fb); }
+function showMC(mc) { parent.leftnav.showAppletMC(mc); }
+function showEqn(sig) { parent.leftnav.showEqn(sig); }
+function showPin(pin) { parent.leftnav.showAppletPin(pin); }
+function showLegend(url) { parent.leftnav.showLegend(url, 650, 350); }
+function showTop() { parent.leftnav.showTop(); }
+
+function Sort(x) {
+  switch (x) {
+    case 0: parent.leftnav.showMappedLogics(0); break;
+    case 1: parent.leftnav.showMappedLogics(2); break;
+    case 2: parent.leftnav.showMappedLogics(4); break;
+    case 10: parent.leftnav.showMappedInputs(0); break;
+    case 11: parent.leftnav.showMappedInputs(2); break;
+    case 12: parent.leftnav.showMappedInputs(4); break;
+    case 20: parent.leftnav.showUnMappedLogics(0); break;
+    case 21: parent.leftnav.showUnMappedLogics(2); break;
+    case 22: parent.leftnav.showUnMappedLogics(4); break;
+    case 30: parent.leftnav.showUnMappedInputs(0); break;
+    case 31: parent.leftnav.showUnMappedInputs(2); break;
+    case 32: parent.leftnav.showUnMappedInputs(4); break;
+  }
+}
diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/maplogic_00.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/maplogic_00.htm
new file mode 100644
index 0000000..0ce2973
--- /dev/null
+++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/maplogic_00.htm
@@ -0,0 +1,692 @@
+<html>
+<head>
+<meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+<script src="maplogic.js"></script><link rel="stylesheet" type="text/css" href="style.css">
+</head>
+<body class="pgBgnd" id="XC95144XL">
+<span id="maplog" class="pgRef"><h3 align="center">Logic</h3>
+<table width="90%" border="1" cellpadding="0" cellspacing="0">
+<tr class="pgHeader">
+<th width="28%"><a href="javascript:Sort(0);">Signal Name</a></th>
+<th align="center">Total Pterms</th>
+<th align="center">Total Inputs</th>
+<th><a href="javascript:Sort(1);">Function Block</a></th>
+<th align="center">Macrocell</th>
+<th align="center">Power Mode</th>
+<th align="center">Slew Rate</th>
+<th><a href="javascript:Sort(2);">Pin Number</a></th>
+<th align="center">Pin Type</th>
+<th align="center">Pin Use</th>
+<th align="center">Reg Init State</th>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('AUTOCONFIG_IN_PROGRESS')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">AUTOCONFIG_IN_PROGRESS</a></td>
+<td align="center">2</td>
+<td align="center">3</td>
+<td align="center"><a href="javascript:showFB('FB1')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB1</a></td>
+<td align="center">MC7</td>
+<td align="center">STD</td>
+<td align="center"> </td>
+<td align="center"> </td>
+<td align="center">(b)</td>
+<td align="center">(b)</td>
+<td align="center">RESET</td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('AUTO_CONFIG_DONE0_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">AUTO_CONFIG_DONE&lt;0&gt;</a></td>
+<td align="center">2</td>
+<td align="center">2</td>
+<td align="center"><a href="javascript:showFB('FB2')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB2</a></td>
+<td align="center">MC9</td>
+<td align="center">STD</td>
+<td align="center"> </td>
+<td align="center">6</td>
+<td align="center">I/O/GTS2</td>
+<td align="center">(b)</td>
+<td align="center">RESET</td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('AUTO_CONFIG_DONE1_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">AUTO_CONFIG_DONE&lt;1&gt;</a></td>
+<td align="center">2</td>
+<td align="center">2</td>
+<td align="center"><a href="javascript:showFB('FB3')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB3</a></td>
+<td align="center">MC15</td>
+<td align="center">STD</td>
+<td align="center"> </td>
+<td align="center">50</td>
+<td align="center">I/O</td>
+<td align="center">I</td>
+<td align="center">RESET</td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('AUTO_CONFIG_DONE2_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">AUTO_CONFIG_DONE&lt;2&gt;</a></td>
+<td align="center">2</td>
+<td align="center">2</td>
+<td align="center"><a href="javascript:showFB('FB2')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB2</a></td>
+<td align="center">MC8</td>
+<td align="center">STD</td>
+<td align="center"> </td>
+<td align="center">5</td>
+<td align="center">I/O/GTS1</td>
+<td align="center">(b)</td>
+<td align="center">RESET</td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('AUTO_CONFIG_DONE_CYCLE0_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">AUTO_CONFIG_DONE_CYCLE&lt;0&gt;</a></td>
+<td align="center">3</td>
+<td align="center">13</td>
+<td align="center"><a href="javascript:showFB('FB2')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB2</a></td>
+<td align="center">MC11</td>
+<td align="center">STD</td>
+<td align="center"> </td>
+<td align="center">9</td>
+<td align="center">I/O</td>
+<td align="center">(b)</td>
+<td align="center">RESET</td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('AUTO_CONFIG_DONE_CYCLE1_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">AUTO_CONFIG_DONE_CYCLE&lt;1&gt;</a></td>
+<td align="center">3</td>
+<td align="center">14</td>
+<td align="center"><a href="javascript:showFB('FB3')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB3</a></td>
+<td align="center">MC16</td>
+<td align="center">STD</td>
+<td align="center"> </td>
+<td align="center"> </td>
+<td align="center">(b)</td>
+<td align="center">(b)</td>
+<td align="center">RESET</td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('AUTO_CONFIG_DONE_CYCLE2_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">AUTO_CONFIG_DONE_CYCLE&lt;2&gt;</a></td>
+<td align="center">3</td>
+<td align="center">15</td>
+<td align="center"><a href="javascript:showFB('FB2')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB2</a></td>
+<td align="center">MC10</td>
+<td align="center">STD</td>
+<td align="center"> </td>
+<td align="center">7</td>
+<td align="center">I/O</td>
+<td align="center">(b)</td>
+<td align="center">RESET</td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('D0_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">D&lt;0&gt;</a></td>
+<td align="center">1</td>
+<td align="center">2</td>
+<td align="center"><a href="javascript:showFB('FB2')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB2</a></td>
+<td align="center">MC5</td>
+<td align="center">STD</td>
+<td align="center">FAST</td>
+<td align="center">2</td>
+<td align="center">I/O/GTS3</td>
+<td align="center">O</td>
+<td align="center"> </td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('D10_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">D&lt;10&gt;</a></td>
+<td align="center">1</td>
+<td align="center">2</td>
+<td align="center"><a href="javascript:showFB('FB3')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB3</a></td>
+<td align="center">MC3</td>
+<td align="center">STD</td>
+<td align="center">FAST</td>
+<td align="center">41</td>
+<td align="center">I/O</td>
+<td align="center">I/O</td>
+<td align="center"> </td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('D11_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">D&lt;11&gt;</a></td>
+<td align="center">1</td>
+<td align="center">2</td>
+<td align="center"><a href="javascript:showFB('FB3')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB3</a></td>
+<td align="center">MC11</td>
+<td align="center">STD</td>
+<td align="center">FAST</td>
+<td align="center">43</td>
+<td align="center">I/O</td>
+<td align="center">I/O</td>
+<td align="center"> </td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('D12_BUFR_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">D&lt;12&gt;_BUFR</a></td>
+<td align="center">19</td>
+<td align="center">16</td>
+<td align="center"><a href="javascript:showFB('FB1')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB1</a></td>
+<td align="center">MC18</td>
+<td align="center">STD</td>
+<td align="center"> </td>
+<td align="center"> </td>
+<td align="center">(b)</td>
+<td align="center">(b)</td>
+<td align="center">RESET</td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('D12_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">D&lt;12&gt;</a></td>
+<td align="center">2</td>
+<td align="center">3</td>
+<td align="center"><a href="javascript:showFB('FB3')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB3</a></td>
+<td align="center">MC4</td>
+<td align="center">STD</td>
+<td align="center">FAST</td>
+<td align="center">44</td>
+<td align="center">I/O</td>
+<td align="center">I/O</td>
+<td align="center"> </td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('D13_BUFR_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">D&lt;13&gt;_BUFR</a></td>
+<td align="center">17</td>
+<td align="center">15</td>
+<td align="center"><a href="javascript:showFB('FB2')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB2</a></td>
+<td align="center">MC15</td>
+<td align="center">STD</td>
+<td align="center"> </td>
+<td align="center">13</td>
+<td align="center">I/O</td>
+<td align="center">(b)</td>
+<td align="center">RESET</td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('D13_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">D&lt;13&gt;</a></td>
+<td align="center">2</td>
+<td align="center">3</td>
+<td align="center"><a href="javascript:showFB('FB3')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB3</a></td>
+<td align="center">MC12</td>
+<td align="center">STD</td>
+<td align="center">FAST</td>
+<td align="center">45</td>
+<td align="center">I/O</td>
+<td align="center">I/O</td>
+<td align="center"> </td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('D14_BUFR_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">D&lt;14&gt;_BUFR</a></td>
+<td align="center">18</td>
+<td align="center">15</td>
+<td align="center"><a href="javascript:showFB('FB2')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB2</a></td>
+<td align="center">MC1</td>
+<td align="center">STD</td>
+<td align="center"> </td>
+<td align="center">142</td>
+<td align="center">I/O</td>
+<td align="center">(b)</td>
+<td align="center">RESET</td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('D14_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">D&lt;14&gt;</a></td>
+<td align="center">2</td>
+<td align="center">3</td>
+<td align="center"><a href="javascript:showFB('FB3')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB3</a></td>
+<td align="center">MC7</td>
+<td align="center">STD</td>
+<td align="center">FAST</td>
+<td align="center">46</td>
+<td align="center">I/O</td>
+<td align="center">I/O</td>
+<td align="center"> </td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('D15_BUFR_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">D&lt;15&gt;_BUFR</a></td>
+<td align="center">14</td>
+<td align="center">15</td>
+<td align="center"><a href="javascript:showFB('FB6')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB6</a></td>
+<td align="center">MC17</td>
+<td align="center">STD</td>
+<td align="center"> </td>
+<td align="center">125</td>
+<td align="center">I/O</td>
+<td align="center">(b)</td>
+<td align="center">RESET</td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('D15_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">D&lt;15&gt;</a></td>
+<td align="center">2</td>
+<td align="center">3</td>
+<td align="center"><a href="javascript:showFB('FB3')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB3</a></td>
+<td align="center">MC10</td>
+<td align="center">STD</td>
+<td align="center">FAST</td>
+<td align="center">48</td>
+<td align="center">I/O</td>
+<td align="center">I/O</td>
+<td align="center"> </td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('D1_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">D&lt;1&gt;</a></td>
+<td align="center">1</td>
+<td align="center">2</td>
+<td align="center"><a href="javascript:showFB('FB1')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB1</a></td>
+<td align="center">MC3</td>
+<td align="center">STD</td>
+<td align="center">FAST</td>
+<td align="center">17</td>
+<td align="center">I/O</td>
+<td align="center">O</td>
+<td align="center"> </td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('D2_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">D&lt;2&gt;</a></td>
+<td align="center">1</td>
+<td align="center">2</td>
+<td align="center"><a href="javascript:showFB('FB3')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB3</a></td>
+<td align="center">MC1</td>
+<td align="center">STD</td>
+<td align="center">FAST</td>
+<td align="center">39</td>
+<td align="center">I/O</td>
+<td align="center">O</td>
+<td align="center"> </td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('D3_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">D&lt;3&gt;</a></td>
+<td align="center">1</td>
+<td align="center">2</td>
+<td align="center"><a href="javascript:showFB('FB2')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB2</a></td>
+<td align="center">MC17</td>
+<td align="center">STD</td>
+<td align="center">FAST</td>
+<td align="center">15</td>
+<td align="center">I/O</td>
+<td align="center">O</td>
+<td align="center"> </td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('D4_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">D&lt;4&gt;</a></td>
+<td align="center">1</td>
+<td align="center">2</td>
+<td align="center"><a href="javascript:showFB('FB1')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB1</a></td>
+<td align="center">MC8</td>
+<td align="center">STD</td>
+<td align="center">FAST</td>
+<td align="center">21</td>
+<td align="center">I/O</td>
+<td align="center">O</td>
+<td align="center"> </td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('D5_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">D&lt;5&gt;</a></td>
+<td align="center">1</td>
+<td align="center">2</td>
+<td align="center"><a href="javascript:showFB('FB1')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB1</a></td>
+<td align="center">MC6</td>
+<td align="center">STD</td>
+<td align="center">FAST</td>
+<td align="center">20</td>
+<td align="center">I/O</td>
+<td align="center">O</td>
+<td align="center"> </td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('D6_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">D&lt;6&gt;</a></td>
+<td align="center">1</td>
+<td align="center">2</td>
+<td align="center"><a href="javascript:showFB('FB2')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB2</a></td>
+<td align="center">MC16</td>
+<td align="center">STD</td>
+<td align="center">FAST</td>
+<td align="center">14</td>
+<td align="center">I/O</td>
+<td align="center">O</td>
+<td align="center"> </td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('D7_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">D&lt;7&gt;</a></td>
+<td align="center">1</td>
+<td align="center">2</td>
+<td align="center"><a href="javascript:showFB('FB1')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB1</a></td>
+<td align="center">MC2</td>
+<td align="center">STD</td>
+<td align="center">FAST</td>
+<td align="center">16</td>
+<td align="center">I/O</td>
+<td align="center">O</td>
+<td align="center"> </td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('D8_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">D&lt;8&gt;</a></td>
+<td align="center">1</td>
+<td align="center">2</td>
+<td align="center"><a href="javascript:showFB('FB1')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB1</a></td>
+<td align="center">MC5</td>
+<td align="center">STD</td>
+<td align="center">FAST</td>
+<td align="center">19</td>
+<td align="center">I/O</td>
+<td align="center">I/O</td>
+<td align="center"> </td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('D9_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">D&lt;9&gt;</a></td>
+<td align="center">1</td>
+<td align="center">2</td>
+<td align="center"><a href="javascript:showFB('FB3')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB3</a></td>
+<td align="center">MC9</td>
+<td align="center">STD</td>
+<td align="center">FAST</td>
+<td align="center">40</td>
+<td align="center">I/O</td>
+<td align="center">I/O</td>
+<td align="center"> </td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('DTACK')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">DTACK</a></td>
+<td align="center">0</td>
+<td align="center">0</td>
+<td align="center"><a href="javascript:showFB('FB7')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB7</a></td>
+<td align="center">MC12</td>
+<td align="center">STD</td>
+<td align="center">FAST</td>
+<td align="center">85</td>
+<td align="center">I/O</td>
+<td align="center">O</td>
+<td align="center"> </td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('IDE_A0_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">IDE_A&lt;0&gt;</a></td>
+<td align="center">1</td>
+<td align="center">1</td>
+<td align="center"><a href="javascript:showFB('FB1')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB1</a></td>
+<td align="center">MC11</td>
+<td align="center">STD</td>
+<td align="center">FAST</td>
+<td align="center">24</td>
+<td align="center">I/O</td>
+<td align="center">O</td>
+<td align="center"> </td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('IDE_A1_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">IDE_A&lt;1&gt;</a></td>
+<td align="center">1</td>
+<td align="center">1</td>
+<td align="center"><a href="javascript:showFB('FB1')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB1</a></td>
+<td align="center">MC12</td>
+<td align="center">STD</td>
+<td align="center">FAST</td>
+<td align="center">26</td>
+<td align="center">I/O</td>
+<td align="center">O</td>
+<td align="center"> </td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('IDE_A2_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">IDE_A&lt;2&gt;</a></td>
+<td align="center">1</td>
+<td align="center">1</td>
+<td align="center"><a href="javascript:showFB('FB1')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB1</a></td>
+<td align="center">MC4</td>
+<td align="center">STD</td>
+<td align="center">FAST</td>
+<td align="center">25</td>
+<td align="center">I/O</td>
+<td align="center">O</td>
+<td align="center"> </td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('IDE_BASEADR0_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">IDE_BASEADR&lt;0&gt;</a></td>
+<td align="center">4</td>
+<td align="center">16</td>
+<td align="center"><a href="javascript:showFB('FB5')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB5</a></td>
+<td align="center">MC18</td>
+<td align="center">STD</td>
+<td align="center"> </td>
+<td align="center"> </td>
+<td align="center">(b)</td>
+<td align="center">(b)</td>
+<td align="center">RESET</td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('IDE_BASEADR1_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">IDE_BASEADR&lt;1&gt;</a></td>
+<td align="center">4</td>
+<td align="center">16</td>
+<td align="center"><a href="javascript:showFB('FB5')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB5</a></td>
+<td align="center">MC16</td>
+<td align="center">STD</td>
+<td align="center"> </td>
+<td align="center"> </td>
+<td align="center">(b)</td>
+<td align="center">(b)</td>
+<td align="center">RESET</td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('IDE_BASEADR2_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">IDE_BASEADR&lt;2&gt;</a></td>
+<td align="center">4</td>
+<td align="center">16</td>
+<td align="center"><a href="javascript:showFB('FB3')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB3</a></td>
+<td align="center">MC18</td>
+<td align="center">STD</td>
+<td align="center"> </td>
+<td align="center"> </td>
+<td align="center">(b)</td>
+<td align="center">(b)</td>
+<td align="center">RESET</td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('IDE_BASEADR3_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">IDE_BASEADR&lt;3&gt;</a></td>
+<td align="center">4</td>
+<td align="center">16</td>
+<td align="center"><a href="javascript:showFB('FB3')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB3</a></td>
+<td align="center">MC17</td>
+<td align="center">STD</td>
+<td align="center"> </td>
+<td align="center">51</td>
+<td align="center">I/O</td>
+<td align="center">I</td>
+<td align="center">RESET</td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('IDE_BASEADR4_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">IDE_BASEADR&lt;4&gt;</a></td>
+<td align="center">4</td>
+<td align="center">16</td>
+<td align="center"><a href="javascript:showFB('FB5')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB5</a></td>
+<td align="center">MC15</td>
+<td align="center">STD</td>
+<td align="center"> </td>
+<td align="center">64</td>
+<td align="center">I/O</td>
+<td align="center">I</td>
+<td align="center">RESET</td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('IDE_BASEADR5_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">IDE_BASEADR&lt;5&gt;</a></td>
+<td align="center">4</td>
+<td align="center">16</td>
+<td align="center"><a href="javascript:showFB('FB5')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB5</a></td>
+<td align="center">MC14</td>
+<td align="center">STD</td>
+<td align="center"> </td>
+<td align="center">61</td>
+<td align="center">I/O</td>
+<td align="center">I</td>
+<td align="center">RESET</td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('IDE_BASEADR6_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">IDE_BASEADR&lt;6&gt;</a></td>
+<td align="center">4</td>
+<td align="center">16</td>
+<td align="center"><a href="javascript:showFB('FB2')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB2</a></td>
+<td align="center">MC13</td>
+<td align="center">STD</td>
+<td align="center"> </td>
+<td align="center">12</td>
+<td align="center">I/O</td>
+<td align="center">(b)</td>
+<td align="center">RESET</td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('IDE_BASEADR7_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">IDE_BASEADR&lt;7&gt;</a></td>
+<td align="center">4</td>
+<td align="center">16</td>
+<td align="center"><a href="javascript:showFB('FB2')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB2</a></td>
+<td align="center">MC12</td>
+<td align="center">STD</td>
+<td align="center"> </td>
+<td align="center">10</td>
+<td align="center">I/O</td>
+<td align="center">(b)</td>
+<td align="center">RESET</td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('IDE_CS0_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">IDE_CS&lt;0&gt;</a></td>
+<td align="center">1</td>
+<td align="center">1</td>
+<td align="center"><a href="javascript:showFB('FB1')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB1</a></td>
+<td align="center">MC9</td>
+<td align="center">STD</td>
+<td align="center">FAST</td>
+<td align="center">22</td>
+<td align="center">I/O</td>
+<td align="center">O</td>
+<td align="center"> </td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('IDE_CS1_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">IDE_CS&lt;1&gt;</a></td>
+<td align="center">1</td>
+<td align="center">1</td>
+<td align="center"><a href="javascript:showFB('FB1')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB1</a></td>
+<td align="center">MC1</td>
+<td align="center">STD</td>
+<td align="center">FAST</td>
+<td align="center">23</td>
+<td align="center">I/O</td>
+<td align="center">O</td>
+<td align="center"> </td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('IDE_ENABLE')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">IDE_ENABLE</a></td>
+<td align="center">3</td>
+<td align="center">6</td>
+<td align="center"><a href="javascript:showFB('FB1')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB1</a></td>
+<td align="center">MC10</td>
+<td align="center">STD</td>
+<td align="center"> </td>
+<td align="center">31</td>
+<td align="center">I/O</td>
+<td align="center">(b)</td>
+<td align="center">RESET</td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('IDE_R')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">IDE_R</a></td>
+<td align="center">2</td>
+<td align="center">6</td>
+<td align="center"><a href="javascript:showFB('FB1')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB1</a></td>
+<td align="center">MC14</td>
+<td align="center">STD</td>
+<td align="center">FAST</td>
+<td align="center">27</td>
+<td align="center">I/O</td>
+<td align="center">O</td>
+<td align="center">SET</td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('IDE_W')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">IDE_W</a></td>
+<td align="center">2</td>
+<td align="center">5</td>
+<td align="center"><a href="javascript:showFB('FB1')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB1</a></td>
+<td align="center">MC15</td>
+<td align="center">STD</td>
+<td align="center">FAST</td>
+<td align="center">28</td>
+<td align="center">I/O</td>
+<td align="center">O</td>
+<td align="center">SET</td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('ROM_B0_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">ROM_B&lt;0&gt;</a></td>
+<td align="center">0</td>
+<td align="center">0</td>
+<td align="center"><a href="javascript:showFB('FB5')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB5</a></td>
+<td align="center">MC10</td>
+<td align="center">STD</td>
+<td align="center">FAST</td>
+<td align="center">68</td>
+<td align="center">I/O</td>
+<td align="center">O</td>
+<td align="center"> </td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('ROM_B1_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">ROM_B&lt;1&gt;</a></td>
+<td align="center">0</td>
+<td align="center">0</td>
+<td align="center"><a href="javascript:showFB('FB5')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB5</a></td>
+<td align="center">MC17</td>
+<td align="center">STD</td>
+<td align="center">FAST</td>
+<td align="center">69</td>
+<td align="center">I/O</td>
+<td align="center">O</td>
+<td align="center"> </td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('ROM_OE')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">ROM_OE</a></td>
+<td align="center">2</td>
+<td align="center">6</td>
+<td align="center"><a href="javascript:showFB('FB1')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB1</a></td>
+<td align="center">MC16</td>
+<td align="center">STD</td>
+<td align="center">FAST</td>
+<td align="center">35</td>
+<td align="center">I/O</td>
+<td align="center">O</td>
+<td align="center">SET</td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('SHUT_UP1_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">SHUT_UP&lt;1&gt;</a></td>
+<td align="center">3</td>
+<td align="center">15</td>
+<td align="center"><a href="javascript:showFB('FB5')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB5</a></td>
+<td align="center">MC13</td>
+<td align="center">STD</td>
+<td align="center"> </td>
+<td align="center">70</td>
+<td align="center">I/O</td>
+<td align="center">(b)</td>
+<td align="center">RESET</td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('autoconfig')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">autoconfig</a></td>
+<td align="center">4</td>
+<td align="center">13</td>
+<td align="center"><a href="javascript:showFB('FB4')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB4</a></td>
+<td align="center">MC17</td>
+<td align="center">STD</td>
+<td align="center"> </td>
+<td align="center">140</td>
+<td align="center">I/O</td>
+<td align="center">(b)</td>
+<td align="center">RESET</td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('ide')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">ide</a></td>
+<td align="center">19</td>
+<td align="center">19</td>
+<td align="center"><a href="javascript:showFB('FB4')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB4</a></td>
+<td align="center">MC1</td>
+<td align="center">STD</td>
+<td align="center"> </td>
+<td align="center">118</td>
+<td align="center">I/O</td>
+<td align="center">(b)</td>
+<td align="center">RESET</td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('ideide_CLKF_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">ide/ide_CLKF</a></td>
+<td align="center">2</td>
+<td align="center">2</td>
+<td align="center"><a href="javascript:showFB('FB4')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB4</a></td>
+<td align="center">MC16</td>
+<td align="center">STD</td>
+<td align="center"> </td>
+<td align="center">139</td>
+<td align="center">I/O</td>
+<td align="center">(b)</td>
+<td align="center"> </td>
+</tr>
+</table></span><form><span class="pgRef"><table width="90%" align="center"><tr>
+<td align="left"><input type="button" onclick="javascript:parent.leftnav.showTop()" onmouseover="window.status='goto top of page'; return true;" onmouseout="window.status=''" value="back to top"></td>
+<td align="right">
+<input type="button" onclick="javascript:showLegend('logiclegend.htm')" onmouseover="window.status='show Legend'; return true;" onmouseout="window.status=''" value="legend"><input type="button" onclick="window.print()" onmouseover="window.status='print page'; return true;" onmouseout="window.status=''" value="print page">
+</td>
+</tr></table></span></form>
+</body>
+</html>
diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/maplogic_01.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/maplogic_01.htm
new file mode 100644
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--- /dev/null
+++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/maplogic_01.htm
@@ -0,0 +1,692 @@
+<html>
+<head>
+<meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+<script src="maplogic.js"></script><link rel="stylesheet" type="text/css" href="style.css">
+</head>
+<body class="pgBgnd" id="XC95144XL">
+<span id="maplog" class="pgRef"><h3 align="center">Logic</h3>
+<table width="90%" border="1" cellpadding="0" cellspacing="0">
+<tr class="pgHeader">
+<th width="28%"><a href="javascript:Sort(0);">Signal Name</a></th>
+<th align="center">Total Pterms</th>
+<th align="center">Total Inputs</th>
+<th><a href="javascript:Sort(1);">Function Block</a></th>
+<th align="center">Macrocell</th>
+<th align="center">Power Mode</th>
+<th align="center">Slew Rate</th>
+<th><a href="javascript:Sort(2);">Pin Number</a></th>
+<th align="center">Pin Type</th>
+<th align="center">Pin Use</th>
+<th align="center">Reg Init State</th>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('IDE_CS1_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">IDE_CS&lt;1&gt;</a></td>
+<td align="center">1</td>
+<td align="center">1</td>
+<td align="center"><a href="javascript:showFB('FB1')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB1</a></td>
+<td align="center">MC1</td>
+<td align="center">STD</td>
+<td align="center">FAST</td>
+<td align="center">23</td>
+<td align="center">I/O</td>
+<td align="center">O</td>
+<td align="center"> </td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('D7_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">D&lt;7&gt;</a></td>
+<td align="center">1</td>
+<td align="center">2</td>
+<td align="center"><a href="javascript:showFB('FB1')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB1</a></td>
+<td align="center">MC2</td>
+<td align="center">STD</td>
+<td align="center">FAST</td>
+<td align="center">16</td>
+<td align="center">I/O</td>
+<td align="center">O</td>
+<td align="center"> </td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('D1_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">D&lt;1&gt;</a></td>
+<td align="center">1</td>
+<td align="center">2</td>
+<td align="center"><a href="javascript:showFB('FB1')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB1</a></td>
+<td align="center">MC3</td>
+<td align="center">STD</td>
+<td align="center">FAST</td>
+<td align="center">17</td>
+<td align="center">I/O</td>
+<td align="center">O</td>
+<td align="center"> </td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('IDE_A2_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">IDE_A&lt;2&gt;</a></td>
+<td align="center">1</td>
+<td align="center">1</td>
+<td align="center"><a href="javascript:showFB('FB1')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB1</a></td>
+<td align="center">MC4</td>
+<td align="center">STD</td>
+<td align="center">FAST</td>
+<td align="center">25</td>
+<td align="center">I/O</td>
+<td align="center">O</td>
+<td align="center"> </td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('D8_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">D&lt;8&gt;</a></td>
+<td align="center">1</td>
+<td align="center">2</td>
+<td align="center"><a href="javascript:showFB('FB1')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB1</a></td>
+<td align="center">MC5</td>
+<td align="center">STD</td>
+<td align="center">FAST</td>
+<td align="center">19</td>
+<td align="center">I/O</td>
+<td align="center">I/O</td>
+<td align="center"> </td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('D5_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">D&lt;5&gt;</a></td>
+<td align="center">1</td>
+<td align="center">2</td>
+<td align="center"><a href="javascript:showFB('FB1')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB1</a></td>
+<td align="center">MC6</td>
+<td align="center">STD</td>
+<td align="center">FAST</td>
+<td align="center">20</td>
+<td align="center">I/O</td>
+<td align="center">O</td>
+<td align="center"> </td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('AUTOCONFIG_IN_PROGRESS')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">AUTOCONFIG_IN_PROGRESS</a></td>
+<td align="center">2</td>
+<td align="center">3</td>
+<td align="center"><a href="javascript:showFB('FB1')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB1</a></td>
+<td align="center">MC7</td>
+<td align="center">STD</td>
+<td align="center"> </td>
+<td align="center"> </td>
+<td align="center">(b)</td>
+<td align="center">(b)</td>
+<td align="center">RESET</td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('D4_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">D&lt;4&gt;</a></td>
+<td align="center">1</td>
+<td align="center">2</td>
+<td align="center"><a href="javascript:showFB('FB1')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB1</a></td>
+<td align="center">MC8</td>
+<td align="center">STD</td>
+<td align="center">FAST</td>
+<td align="center">21</td>
+<td align="center">I/O</td>
+<td align="center">O</td>
+<td align="center"> </td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('IDE_CS0_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">IDE_CS&lt;0&gt;</a></td>
+<td align="center">1</td>
+<td align="center">1</td>
+<td align="center"><a href="javascript:showFB('FB1')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB1</a></td>
+<td align="center">MC9</td>
+<td align="center">STD</td>
+<td align="center">FAST</td>
+<td align="center">22</td>
+<td align="center">I/O</td>
+<td align="center">O</td>
+<td align="center"> </td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('IDE_ENABLE')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">IDE_ENABLE</a></td>
+<td align="center">3</td>
+<td align="center">6</td>
+<td align="center"><a href="javascript:showFB('FB1')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB1</a></td>
+<td align="center">MC10</td>
+<td align="center">STD</td>
+<td align="center"> </td>
+<td align="center">31</td>
+<td align="center">I/O</td>
+<td align="center">(b)</td>
+<td align="center">RESET</td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('IDE_A0_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">IDE_A&lt;0&gt;</a></td>
+<td align="center">1</td>
+<td align="center">1</td>
+<td align="center"><a href="javascript:showFB('FB1')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB1</a></td>
+<td align="center">MC11</td>
+<td align="center">STD</td>
+<td align="center">FAST</td>
+<td align="center">24</td>
+<td align="center">I/O</td>
+<td align="center">O</td>
+<td align="center"> </td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('IDE_A1_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">IDE_A&lt;1&gt;</a></td>
+<td align="center">1</td>
+<td align="center">1</td>
+<td align="center"><a href="javascript:showFB('FB1')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB1</a></td>
+<td align="center">MC12</td>
+<td align="center">STD</td>
+<td align="center">FAST</td>
+<td align="center">26</td>
+<td align="center">I/O</td>
+<td align="center">O</td>
+<td align="center"> </td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('IDE_R')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">IDE_R</a></td>
+<td align="center">2</td>
+<td align="center">6</td>
+<td align="center"><a href="javascript:showFB('FB1')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB1</a></td>
+<td align="center">MC14</td>
+<td align="center">STD</td>
+<td align="center">FAST</td>
+<td align="center">27</td>
+<td align="center">I/O</td>
+<td align="center">O</td>
+<td align="center">SET</td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('IDE_W')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">IDE_W</a></td>
+<td align="center">2</td>
+<td align="center">5</td>
+<td align="center"><a href="javascript:showFB('FB1')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB1</a></td>
+<td align="center">MC15</td>
+<td align="center">STD</td>
+<td align="center">FAST</td>
+<td align="center">28</td>
+<td align="center">I/O</td>
+<td align="center">O</td>
+<td align="center">SET</td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('ROM_OE')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">ROM_OE</a></td>
+<td align="center">2</td>
+<td align="center">6</td>
+<td align="center"><a href="javascript:showFB('FB1')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB1</a></td>
+<td align="center">MC16</td>
+<td align="center">STD</td>
+<td align="center">FAST</td>
+<td align="center">35</td>
+<td align="center">I/O</td>
+<td align="center">O</td>
+<td align="center">SET</td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('D12_BUFR_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">D&lt;12&gt;_BUFR</a></td>
+<td align="center">19</td>
+<td align="center">16</td>
+<td align="center"><a href="javascript:showFB('FB1')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB1</a></td>
+<td align="center">MC18</td>
+<td align="center">STD</td>
+<td align="center"> </td>
+<td align="center"> </td>
+<td align="center">(b)</td>
+<td align="center">(b)</td>
+<td align="center">RESET</td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('D14_BUFR_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">D&lt;14&gt;_BUFR</a></td>
+<td align="center">18</td>
+<td align="center">15</td>
+<td align="center"><a href="javascript:showFB('FB2')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB2</a></td>
+<td align="center">MC1</td>
+<td align="center">STD</td>
+<td align="center"> </td>
+<td align="center">142</td>
+<td align="center">I/O</td>
+<td align="center">(b)</td>
+<td align="center">RESET</td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('D0_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">D&lt;0&gt;</a></td>
+<td align="center">1</td>
+<td align="center">2</td>
+<td align="center"><a href="javascript:showFB('FB2')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB2</a></td>
+<td align="center">MC5</td>
+<td align="center">STD</td>
+<td align="center">FAST</td>
+<td align="center">2</td>
+<td align="center">I/O/GTS3</td>
+<td align="center">O</td>
+<td align="center"> </td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('AUTO_CONFIG_DONE2_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">AUTO_CONFIG_DONE&lt;2&gt;</a></td>
+<td align="center">2</td>
+<td align="center">2</td>
+<td align="center"><a href="javascript:showFB('FB2')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB2</a></td>
+<td align="center">MC8</td>
+<td align="center">STD</td>
+<td align="center"> </td>
+<td align="center">5</td>
+<td align="center">I/O/GTS1</td>
+<td align="center">(b)</td>
+<td align="center">RESET</td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('AUTO_CONFIG_DONE0_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">AUTO_CONFIG_DONE&lt;0&gt;</a></td>
+<td align="center">2</td>
+<td align="center">2</td>
+<td align="center"><a href="javascript:showFB('FB2')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB2</a></td>
+<td align="center">MC9</td>
+<td align="center">STD</td>
+<td align="center"> </td>
+<td align="center">6</td>
+<td align="center">I/O/GTS2</td>
+<td align="center">(b)</td>
+<td align="center">RESET</td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('AUTO_CONFIG_DONE_CYCLE2_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">AUTO_CONFIG_DONE_CYCLE&lt;2&gt;</a></td>
+<td align="center">3</td>
+<td align="center">15</td>
+<td align="center"><a href="javascript:showFB('FB2')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB2</a></td>
+<td align="center">MC10</td>
+<td align="center">STD</td>
+<td align="center"> </td>
+<td align="center">7</td>
+<td align="center">I/O</td>
+<td align="center">(b)</td>
+<td align="center">RESET</td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('AUTO_CONFIG_DONE_CYCLE0_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">AUTO_CONFIG_DONE_CYCLE&lt;0&gt;</a></td>
+<td align="center">3</td>
+<td align="center">13</td>
+<td align="center"><a href="javascript:showFB('FB2')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB2</a></td>
+<td align="center">MC11</td>
+<td align="center">STD</td>
+<td align="center"> </td>
+<td align="center">9</td>
+<td align="center">I/O</td>
+<td align="center">(b)</td>
+<td align="center">RESET</td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('IDE_BASEADR7_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">IDE_BASEADR&lt;7&gt;</a></td>
+<td align="center">4</td>
+<td align="center">16</td>
+<td align="center"><a href="javascript:showFB('FB2')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB2</a></td>
+<td align="center">MC12</td>
+<td align="center">STD</td>
+<td align="center"> </td>
+<td align="center">10</td>
+<td align="center">I/O</td>
+<td align="center">(b)</td>
+<td align="center">RESET</td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('IDE_BASEADR6_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">IDE_BASEADR&lt;6&gt;</a></td>
+<td align="center">4</td>
+<td align="center">16</td>
+<td align="center"><a href="javascript:showFB('FB2')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB2</a></td>
+<td align="center">MC13</td>
+<td align="center">STD</td>
+<td align="center"> </td>
+<td align="center">12</td>
+<td align="center">I/O</td>
+<td align="center">(b)</td>
+<td align="center">RESET</td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('D13_BUFR_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">D&lt;13&gt;_BUFR</a></td>
+<td align="center">17</td>
+<td align="center">15</td>
+<td align="center"><a href="javascript:showFB('FB2')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB2</a></td>
+<td align="center">MC15</td>
+<td align="center">STD</td>
+<td align="center"> </td>
+<td align="center">13</td>
+<td align="center">I/O</td>
+<td align="center">(b)</td>
+<td align="center">RESET</td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('D6_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">D&lt;6&gt;</a></td>
+<td align="center">1</td>
+<td align="center">2</td>
+<td align="center"><a href="javascript:showFB('FB2')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB2</a></td>
+<td align="center">MC16</td>
+<td align="center">STD</td>
+<td align="center">FAST</td>
+<td align="center">14</td>
+<td align="center">I/O</td>
+<td align="center">O</td>
+<td align="center"> </td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('D3_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">D&lt;3&gt;</a></td>
+<td align="center">1</td>
+<td align="center">2</td>
+<td align="center"><a href="javascript:showFB('FB2')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB2</a></td>
+<td align="center">MC17</td>
+<td align="center">STD</td>
+<td align="center">FAST</td>
+<td align="center">15</td>
+<td align="center">I/O</td>
+<td align="center">O</td>
+<td align="center"> </td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('D2_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">D&lt;2&gt;</a></td>
+<td align="center">1</td>
+<td align="center">2</td>
+<td align="center"><a href="javascript:showFB('FB3')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB3</a></td>
+<td align="center">MC1</td>
+<td align="center">STD</td>
+<td align="center">FAST</td>
+<td align="center">39</td>
+<td align="center">I/O</td>
+<td align="center">O</td>
+<td align="center"> </td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('D10_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">D&lt;10&gt;</a></td>
+<td align="center">1</td>
+<td align="center">2</td>
+<td align="center"><a href="javascript:showFB('FB3')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB3</a></td>
+<td align="center">MC3</td>
+<td align="center">STD</td>
+<td align="center">FAST</td>
+<td align="center">41</td>
+<td align="center">I/O</td>
+<td align="center">I/O</td>
+<td align="center"> </td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('D12_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">D&lt;12&gt;</a></td>
+<td align="center">2</td>
+<td align="center">3</td>
+<td align="center"><a href="javascript:showFB('FB3')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB3</a></td>
+<td align="center">MC4</td>
+<td align="center">STD</td>
+<td align="center">FAST</td>
+<td align="center">44</td>
+<td align="center">I/O</td>
+<td align="center">I/O</td>
+<td align="center"> </td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('D14_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">D&lt;14&gt;</a></td>
+<td align="center">2</td>
+<td align="center">3</td>
+<td align="center"><a href="javascript:showFB('FB3')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB3</a></td>
+<td align="center">MC7</td>
+<td align="center">STD</td>
+<td align="center">FAST</td>
+<td align="center">46</td>
+<td align="center">I/O</td>
+<td align="center">I/O</td>
+<td align="center"> </td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('D9_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">D&lt;9&gt;</a></td>
+<td align="center">1</td>
+<td align="center">2</td>
+<td align="center"><a href="javascript:showFB('FB3')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB3</a></td>
+<td align="center">MC9</td>
+<td align="center">STD</td>
+<td align="center">FAST</td>
+<td align="center">40</td>
+<td align="center">I/O</td>
+<td align="center">I/O</td>
+<td align="center"> </td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('D15_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">D&lt;15&gt;</a></td>
+<td align="center">2</td>
+<td align="center">3</td>
+<td align="center"><a href="javascript:showFB('FB3')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB3</a></td>
+<td align="center">MC10</td>
+<td align="center">STD</td>
+<td align="center">FAST</td>
+<td align="center">48</td>
+<td align="center">I/O</td>
+<td align="center">I/O</td>
+<td align="center"> </td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('D11_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">D&lt;11&gt;</a></td>
+<td align="center">1</td>
+<td align="center">2</td>
+<td align="center"><a href="javascript:showFB('FB3')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB3</a></td>
+<td align="center">MC11</td>
+<td align="center">STD</td>
+<td align="center">FAST</td>
+<td align="center">43</td>
+<td align="center">I/O</td>
+<td align="center">I/O</td>
+<td align="center"> </td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('D13_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">D&lt;13&gt;</a></td>
+<td align="center">2</td>
+<td align="center">3</td>
+<td align="center"><a href="javascript:showFB('FB3')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB3</a></td>
+<td align="center">MC12</td>
+<td align="center">STD</td>
+<td align="center">FAST</td>
+<td align="center">45</td>
+<td align="center">I/O</td>
+<td align="center">I/O</td>
+<td align="center"> </td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('AUTO_CONFIG_DONE1_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">AUTO_CONFIG_DONE&lt;1&gt;</a></td>
+<td align="center">2</td>
+<td align="center">2</td>
+<td align="center"><a href="javascript:showFB('FB3')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB3</a></td>
+<td align="center">MC15</td>
+<td align="center">STD</td>
+<td align="center"> </td>
+<td align="center">50</td>
+<td align="center">I/O</td>
+<td align="center">I</td>
+<td align="center">RESET</td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('AUTO_CONFIG_DONE_CYCLE1_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">AUTO_CONFIG_DONE_CYCLE&lt;1&gt;</a></td>
+<td align="center">3</td>
+<td align="center">14</td>
+<td align="center"><a href="javascript:showFB('FB3')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB3</a></td>
+<td align="center">MC16</td>
+<td align="center">STD</td>
+<td align="center"> </td>
+<td align="center"> </td>
+<td align="center">(b)</td>
+<td align="center">(b)</td>
+<td align="center">RESET</td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('IDE_BASEADR3_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">IDE_BASEADR&lt;3&gt;</a></td>
+<td align="center">4</td>
+<td align="center">16</td>
+<td align="center"><a href="javascript:showFB('FB3')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB3</a></td>
+<td align="center">MC17</td>
+<td align="center">STD</td>
+<td align="center"> </td>
+<td align="center">51</td>
+<td align="center">I/O</td>
+<td align="center">I</td>
+<td align="center">RESET</td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('IDE_BASEADR2_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">IDE_BASEADR&lt;2&gt;</a></td>
+<td align="center">4</td>
+<td align="center">16</td>
+<td align="center"><a href="javascript:showFB('FB3')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB3</a></td>
+<td align="center">MC18</td>
+<td align="center">STD</td>
+<td align="center"> </td>
+<td align="center"> </td>
+<td align="center">(b)</td>
+<td align="center">(b)</td>
+<td align="center">RESET</td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('ide')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">ide</a></td>
+<td align="center">19</td>
+<td align="center">19</td>
+<td align="center"><a href="javascript:showFB('FB4')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB4</a></td>
+<td align="center">MC1</td>
+<td align="center">STD</td>
+<td align="center"> </td>
+<td align="center">118</td>
+<td align="center">I/O</td>
+<td align="center">(b)</td>
+<td align="center">RESET</td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('ideide_CLKF_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">ide/ide_CLKF</a></td>
+<td align="center">2</td>
+<td align="center">2</td>
+<td align="center"><a href="javascript:showFB('FB4')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB4</a></td>
+<td align="center">MC16</td>
+<td align="center">STD</td>
+<td align="center"> </td>
+<td align="center">139</td>
+<td align="center">I/O</td>
+<td align="center">(b)</td>
+<td align="center"> </td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('autoconfig')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">autoconfig</a></td>
+<td align="center">4</td>
+<td align="center">13</td>
+<td align="center"><a href="javascript:showFB('FB4')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB4</a></td>
+<td align="center">MC17</td>
+<td align="center">STD</td>
+<td align="center"> </td>
+<td align="center">140</td>
+<td align="center">I/O</td>
+<td align="center">(b)</td>
+<td align="center">RESET</td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('ROM_B0_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">ROM_B&lt;0&gt;</a></td>
+<td align="center">0</td>
+<td align="center">0</td>
+<td align="center"><a href="javascript:showFB('FB5')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB5</a></td>
+<td align="center">MC10</td>
+<td align="center">STD</td>
+<td align="center">FAST</td>
+<td align="center">68</td>
+<td align="center">I/O</td>
+<td align="center">O</td>
+<td align="center"> </td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('SHUT_UP1_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">SHUT_UP&lt;1&gt;</a></td>
+<td align="center">3</td>
+<td align="center">15</td>
+<td align="center"><a href="javascript:showFB('FB5')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB5</a></td>
+<td align="center">MC13</td>
+<td align="center">STD</td>
+<td align="center"> </td>
+<td align="center">70</td>
+<td align="center">I/O</td>
+<td align="center">(b)</td>
+<td align="center">RESET</td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('IDE_BASEADR5_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">IDE_BASEADR&lt;5&gt;</a></td>
+<td align="center">4</td>
+<td align="center">16</td>
+<td align="center"><a href="javascript:showFB('FB5')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB5</a></td>
+<td align="center">MC14</td>
+<td align="center">STD</td>
+<td align="center"> </td>
+<td align="center">61</td>
+<td align="center">I/O</td>
+<td align="center">I</td>
+<td align="center">RESET</td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('IDE_BASEADR4_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">IDE_BASEADR&lt;4&gt;</a></td>
+<td align="center">4</td>
+<td align="center">16</td>
+<td align="center"><a href="javascript:showFB('FB5')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB5</a></td>
+<td align="center">MC15</td>
+<td align="center">STD</td>
+<td align="center"> </td>
+<td align="center">64</td>
+<td align="center">I/O</td>
+<td align="center">I</td>
+<td align="center">RESET</td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('IDE_BASEADR1_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">IDE_BASEADR&lt;1&gt;</a></td>
+<td align="center">4</td>
+<td align="center">16</td>
+<td align="center"><a href="javascript:showFB('FB5')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB5</a></td>
+<td align="center">MC16</td>
+<td align="center">STD</td>
+<td align="center"> </td>
+<td align="center"> </td>
+<td align="center">(b)</td>
+<td align="center">(b)</td>
+<td align="center">RESET</td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('ROM_B1_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">ROM_B&lt;1&gt;</a></td>
+<td align="center">0</td>
+<td align="center">0</td>
+<td align="center"><a href="javascript:showFB('FB5')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB5</a></td>
+<td align="center">MC17</td>
+<td align="center">STD</td>
+<td align="center">FAST</td>
+<td align="center">69</td>
+<td align="center">I/O</td>
+<td align="center">O</td>
+<td align="center"> </td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('IDE_BASEADR0_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">IDE_BASEADR&lt;0&gt;</a></td>
+<td align="center">4</td>
+<td align="center">16</td>
+<td align="center"><a href="javascript:showFB('FB5')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB5</a></td>
+<td align="center">MC18</td>
+<td align="center">STD</td>
+<td align="center"> </td>
+<td align="center"> </td>
+<td align="center">(b)</td>
+<td align="center">(b)</td>
+<td align="center">RESET</td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('D15_BUFR_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">D&lt;15&gt;_BUFR</a></td>
+<td align="center">14</td>
+<td align="center">15</td>
+<td align="center"><a href="javascript:showFB('FB6')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB6</a></td>
+<td align="center">MC17</td>
+<td align="center">STD</td>
+<td align="center"> </td>
+<td align="center">125</td>
+<td align="center">I/O</td>
+<td align="center">(b)</td>
+<td align="center">RESET</td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('DTACK')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">DTACK</a></td>
+<td align="center">0</td>
+<td align="center">0</td>
+<td align="center"><a href="javascript:showFB('FB7')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB7</a></td>
+<td align="center">MC12</td>
+<td align="center">STD</td>
+<td align="center">FAST</td>
+<td align="center">85</td>
+<td align="center">I/O</td>
+<td align="center">O</td>
+<td align="center"> </td>
+</tr>
+</table></span><form><span class="pgRef"><table width="90%" align="center"><tr>
+<td align="left"><input type="button" onclick="javascript:parent.leftnav.showTop()" onmouseover="window.status='goto top of page'; return true;" onmouseout="window.status=''" value="back to top"></td>
+<td align="right">
+<input type="button" onclick="javascript:showLegend('logiclegend.htm')" onmouseover="window.status='show Legend'; return true;" onmouseout="window.status=''" value="legend"><input type="button" onclick="window.print()" onmouseover="window.status='print page'; return true;" onmouseout="window.status=''" value="print page">
+</td>
+</tr></table></span></form>
+</body>
+</html>
diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/maplogic_02.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/maplogic_02.htm
new file mode 100644
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@@ -0,0 +1,710 @@
+<html>
+<head>
+<meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+<script src="maplogic.js"></script><link rel="stylesheet" type="text/css" href="style.css">
+</head>
+<body class="pgBgnd" id="XC95144XL">
+<span id="maplog" class="pgRef"><h3 align="center">Logic</h3>
+<table width="90%" border="1" cellpadding="0" cellspacing="0">
+<tr class="pgHeader">
+<th width="28%"><a href="javascript:Sort(0);">Signal Name</a></th>
+<th align="center">Total Pterms</th>
+<th align="center">Total Inputs</th>
+<th><a href="javascript:Sort(1);">Function Block</a></th>
+<th align="center">Macrocell</th>
+<th align="center">Power Mode</th>
+<th align="center">Slew Rate</th>
+<th><a href="javascript:Sort(2);">Pin Number</a></th>
+<th align="center">Pin Type</th>
+<th align="center">Pin Use</th>
+<th align="center">Reg Init State</th>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('D0_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">D&lt;0&gt;</a></td>
+<td align="center">1</td>
+<td align="center">2</td>
+<td align="center"><a href="javascript:showFB('FB2')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB2</a></td>
+<td align="center">MC5</td>
+<td align="center">STD</td>
+<td align="center">FAST</td>
+<td align="center">2</td>
+<td align="center">I/O/GTS3</td>
+<td align="center">O</td>
+<td align="center"> </td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('AUTO_CONFIG_DONE2_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">AUTO_CONFIG_DONE&lt;2&gt;</a></td>
+<td align="center">2</td>
+<td align="center">2</td>
+<td align="center"><a href="javascript:showFB('FB2')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB2</a></td>
+<td align="center">MC8</td>
+<td align="center">STD</td>
+<td align="center"> </td>
+<td align="center">5</td>
+<td align="center">I/O/GTS1</td>
+<td align="center">(b)</td>
+<td align="center">RESET</td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('AUTO_CONFIG_DONE0_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">AUTO_CONFIG_DONE&lt;0&gt;</a></td>
+<td align="center">2</td>
+<td align="center">2</td>
+<td align="center"><a href="javascript:showFB('FB2')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB2</a></td>
+<td align="center">MC9</td>
+<td align="center">STD</td>
+<td align="center"> </td>
+<td align="center">6</td>
+<td align="center">I/O/GTS2</td>
+<td align="center">(b)</td>
+<td align="center">RESET</td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('AUTO_CONFIG_DONE_CYCLE2_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">AUTO_CONFIG_DONE_CYCLE&lt;2&gt;</a></td>
+<td align="center">3</td>
+<td align="center">15</td>
+<td align="center"><a href="javascript:showFB('FB2')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB2</a></td>
+<td align="center">MC10</td>
+<td align="center">STD</td>
+<td align="center"> </td>
+<td align="center">7</td>
+<td align="center">I/O</td>
+<td align="center">(b)</td>
+<td align="center">RESET</td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('AUTO_CONFIG_DONE_CYCLE0_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">AUTO_CONFIG_DONE_CYCLE&lt;0&gt;</a></td>
+<td align="center">3</td>
+<td align="center">13</td>
+<td align="center"><a href="javascript:showFB('FB2')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB2</a></td>
+<td align="center">MC11</td>
+<td align="center">STD</td>
+<td align="center"> </td>
+<td align="center">9</td>
+<td align="center">I/O</td>
+<td align="center">(b)</td>
+<td align="center">RESET</td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('IDE_BASEADR7_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">IDE_BASEADR&lt;7&gt;</a></td>
+<td align="center">4</td>
+<td align="center">16</td>
+<td align="center"><a href="javascript:showFB('FB2')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB2</a></td>
+<td align="center">MC12</td>
+<td align="center">STD</td>
+<td align="center"> </td>
+<td align="center">10</td>
+<td align="center">I/O</td>
+<td align="center">(b)</td>
+<td align="center">RESET</td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('IDE_BASEADR6_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">IDE_BASEADR&lt;6&gt;</a></td>
+<td align="center">4</td>
+<td align="center">16</td>
+<td align="center"><a href="javascript:showFB('FB2')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB2</a></td>
+<td align="center">MC13</td>
+<td align="center">STD</td>
+<td align="center"> </td>
+<td align="center">12</td>
+<td align="center">I/O</td>
+<td align="center">(b)</td>
+<td align="center">RESET</td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('D13_BUFR_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">D&lt;13&gt;_BUFR</a></td>
+<td align="center">17</td>
+<td align="center">15</td>
+<td align="center"><a href="javascript:showFB('FB2')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB2</a></td>
+<td align="center">MC15</td>
+<td align="center">STD</td>
+<td align="center"> </td>
+<td align="center">13</td>
+<td align="center">I/O</td>
+<td align="center">(b)</td>
+<td align="center">RESET</td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('D6_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">D&lt;6&gt;</a></td>
+<td align="center">1</td>
+<td align="center">2</td>
+<td align="center"><a href="javascript:showFB('FB2')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB2</a></td>
+<td align="center">MC16</td>
+<td align="center">STD</td>
+<td align="center">FAST</td>
+<td align="center">14</td>
+<td align="center">I/O</td>
+<td align="center">O</td>
+<td align="center"> </td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('D3_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">D&lt;3&gt;</a></td>
+<td align="center">1</td>
+<td align="center">2</td>
+<td align="center"><a href="javascript:showFB('FB2')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB2</a></td>
+<td align="center">MC17</td>
+<td align="center">STD</td>
+<td align="center">FAST</td>
+<td align="center">15</td>
+<td align="center">I/O</td>
+<td align="center">O</td>
+<td align="center"> </td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('D7_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">D&lt;7&gt;</a></td>
+<td align="center">1</td>
+<td align="center">2</td>
+<td align="center"><a href="javascript:showFB('FB1')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB1</a></td>
+<td align="center">MC2</td>
+<td align="center">STD</td>
+<td align="center">FAST</td>
+<td align="center">16</td>
+<td align="center">I/O</td>
+<td align="center">O</td>
+<td align="center"> </td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('D1_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">D&lt;1&gt;</a></td>
+<td align="center">1</td>
+<td align="center">2</td>
+<td align="center"><a href="javascript:showFB('FB1')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB1</a></td>
+<td align="center">MC3</td>
+<td align="center">STD</td>
+<td align="center">FAST</td>
+<td align="center">17</td>
+<td align="center">I/O</td>
+<td align="center">O</td>
+<td align="center"> </td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('D8_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">D&lt;8&gt;</a></td>
+<td align="center">1</td>
+<td align="center">2</td>
+<td align="center"><a href="javascript:showFB('FB1')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB1</a></td>
+<td align="center">MC5</td>
+<td align="center">STD</td>
+<td align="center">FAST</td>
+<td align="center">19</td>
+<td align="center">I/O</td>
+<td align="center">I/O</td>
+<td align="center"> </td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('D5_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">D&lt;5&gt;</a></td>
+<td align="center">1</td>
+<td align="center">2</td>
+<td align="center"><a href="javascript:showFB('FB1')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB1</a></td>
+<td align="center">MC6</td>
+<td align="center">STD</td>
+<td align="center">FAST</td>
+<td align="center">20</td>
+<td align="center">I/O</td>
+<td align="center">O</td>
+<td align="center"> </td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('D4_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">D&lt;4&gt;</a></td>
+<td align="center">1</td>
+<td align="center">2</td>
+<td align="center"><a href="javascript:showFB('FB1')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB1</a></td>
+<td align="center">MC8</td>
+<td align="center">STD</td>
+<td align="center">FAST</td>
+<td align="center">21</td>
+<td align="center">I/O</td>
+<td align="center">O</td>
+<td align="center"> </td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('IDE_CS0_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">IDE_CS&lt;0&gt;</a></td>
+<td align="center">1</td>
+<td align="center">1</td>
+<td align="center"><a href="javascript:showFB('FB1')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB1</a></td>
+<td align="center">MC9</td>
+<td align="center">STD</td>
+<td align="center">FAST</td>
+<td align="center">22</td>
+<td align="center">I/O</td>
+<td align="center">O</td>
+<td align="center"> </td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('IDE_CS1_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">IDE_CS&lt;1&gt;</a></td>
+<td align="center">1</td>
+<td align="center">1</td>
+<td align="center"><a href="javascript:showFB('FB1')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB1</a></td>
+<td align="center">MC1</td>
+<td align="center">STD</td>
+<td align="center">FAST</td>
+<td align="center">23</td>
+<td align="center">I/O</td>
+<td align="center">O</td>
+<td align="center"> </td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('IDE_A0_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">IDE_A&lt;0&gt;</a></td>
+<td align="center">1</td>
+<td align="center">1</td>
+<td align="center"><a href="javascript:showFB('FB1')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB1</a></td>
+<td align="center">MC11</td>
+<td align="center">STD</td>
+<td align="center">FAST</td>
+<td align="center">24</td>
+<td align="center">I/O</td>
+<td align="center">O</td>
+<td align="center"> </td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('IDE_A2_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">IDE_A&lt;2&gt;</a></td>
+<td align="center">1</td>
+<td align="center">1</td>
+<td align="center"><a href="javascript:showFB('FB1')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB1</a></td>
+<td align="center">MC4</td>
+<td align="center">STD</td>
+<td align="center">FAST</td>
+<td align="center">25</td>
+<td align="center">I/O</td>
+<td align="center">O</td>
+<td align="center"> </td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('IDE_A1_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">IDE_A&lt;1&gt;</a></td>
+<td align="center">1</td>
+<td align="center">1</td>
+<td align="center"><a href="javascript:showFB('FB1')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB1</a></td>
+<td align="center">MC12</td>
+<td align="center">STD</td>
+<td align="center">FAST</td>
+<td align="center">26</td>
+<td align="center">I/O</td>
+<td align="center">O</td>
+<td align="center"> </td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('IDE_R')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">IDE_R</a></td>
+<td align="center">2</td>
+<td align="center">6</td>
+<td align="center"><a href="javascript:showFB('FB1')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB1</a></td>
+<td align="center">MC14</td>
+<td align="center">STD</td>
+<td align="center">FAST</td>
+<td align="center">27</td>
+<td align="center">I/O</td>
+<td align="center">O</td>
+<td align="center">SET</td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('IDE_W')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">IDE_W</a></td>
+<td align="center">2</td>
+<td align="center">5</td>
+<td align="center"><a href="javascript:showFB('FB1')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB1</a></td>
+<td align="center">MC15</td>
+<td align="center">STD</td>
+<td align="center">FAST</td>
+<td align="center">28</td>
+<td align="center">I/O</td>
+<td align="center">O</td>
+<td align="center">SET</td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('IDE_ENABLE')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">IDE_ENABLE</a></td>
+<td align="center">3</td>
+<td align="center">6</td>
+<td align="center"><a href="javascript:showFB('FB1')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB1</a></td>
+<td align="center">MC10</td>
+<td align="center">STD</td>
+<td align="center"> </td>
+<td align="center">31</td>
+<td align="center">I/O</td>
+<td align="center">(b)</td>
+<td align="center">RESET</td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('ROM_OE')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">ROM_OE</a></td>
+<td align="center">2</td>
+<td align="center">6</td>
+<td align="center"><a href="javascript:showFB('FB1')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB1</a></td>
+<td align="center">MC16</td>
+<td align="center">STD</td>
+<td align="center">FAST</td>
+<td align="center">35</td>
+<td align="center">I/O</td>
+<td align="center">O</td>
+<td align="center">SET</td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('D2_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">D&lt;2&gt;</a></td>
+<td align="center">1</td>
+<td align="center">2</td>
+<td align="center"><a href="javascript:showFB('FB3')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB3</a></td>
+<td align="center">MC1</td>
+<td align="center">STD</td>
+<td align="center">FAST</td>
+<td align="center">39</td>
+<td align="center">I/O</td>
+<td align="center">O</td>
+<td align="center"> </td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('D9_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">D&lt;9&gt;</a></td>
+<td align="center">1</td>
+<td align="center">2</td>
+<td align="center"><a href="javascript:showFB('FB3')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB3</a></td>
+<td align="center">MC9</td>
+<td align="center">STD</td>
+<td align="center">FAST</td>
+<td align="center">40</td>
+<td align="center">I/O</td>
+<td align="center">I/O</td>
+<td align="center"> </td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('D10_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">D&lt;10&gt;</a></td>
+<td align="center">1</td>
+<td align="center">2</td>
+<td align="center"><a href="javascript:showFB('FB3')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB3</a></td>
+<td align="center">MC3</td>
+<td align="center">STD</td>
+<td align="center">FAST</td>
+<td align="center">41</td>
+<td align="center">I/O</td>
+<td align="center">I/O</td>
+<td align="center"> </td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('D11_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">D&lt;11&gt;</a></td>
+<td align="center">1</td>
+<td align="center">2</td>
+<td align="center"><a href="javascript:showFB('FB3')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB3</a></td>
+<td align="center">MC11</td>
+<td align="center">STD</td>
+<td align="center">FAST</td>
+<td align="center">43</td>
+<td align="center">I/O</td>
+<td align="center">I/O</td>
+<td align="center"> </td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('D12_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">D&lt;12&gt;</a></td>
+<td align="center">2</td>
+<td align="center">3</td>
+<td align="center"><a href="javascript:showFB('FB3')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB3</a></td>
+<td align="center">MC4</td>
+<td align="center">STD</td>
+<td align="center">FAST</td>
+<td align="center">44</td>
+<td align="center">I/O</td>
+<td align="center">I/O</td>
+<td align="center"> </td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('D13_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">D&lt;13&gt;</a></td>
+<td align="center">2</td>
+<td align="center">3</td>
+<td align="center"><a href="javascript:showFB('FB3')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB3</a></td>
+<td align="center">MC12</td>
+<td align="center">STD</td>
+<td align="center">FAST</td>
+<td align="center">45</td>
+<td align="center">I/O</td>
+<td align="center">I/O</td>
+<td align="center"> </td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('D14_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">D&lt;14&gt;</a></td>
+<td align="center">2</td>
+<td align="center">3</td>
+<td align="center"><a href="javascript:showFB('FB3')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB3</a></td>
+<td align="center">MC7</td>
+<td align="center">STD</td>
+<td align="center">FAST</td>
+<td align="center">46</td>
+<td align="center">I/O</td>
+<td align="center">I/O</td>
+<td align="center"> </td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('D15_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">D&lt;15&gt;</a></td>
+<td align="center">2</td>
+<td align="center">3</td>
+<td align="center"><a href="javascript:showFB('FB3')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB3</a></td>
+<td align="center">MC10</td>
+<td align="center">STD</td>
+<td align="center">FAST</td>
+<td align="center">48</td>
+<td align="center">I/O</td>
+<td align="center">I/O</td>
+<td align="center"> </td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('AUTO_CONFIG_DONE1_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">AUTO_CONFIG_DONE&lt;1&gt;</a></td>
+<td align="center">2</td>
+<td align="center">2</td>
+<td align="center"><a href="javascript:showFB('FB3')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB3</a></td>
+<td align="center">MC15</td>
+<td align="center">STD</td>
+<td align="center"> </td>
+<td align="center">50</td>
+<td align="center">I/O</td>
+<td align="center">I</td>
+<td align="center">RESET</td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('IDE_BASEADR3_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">IDE_BASEADR&lt;3&gt;</a></td>
+<td align="center">4</td>
+<td align="center">16</td>
+<td align="center"><a href="javascript:showFB('FB3')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB3</a></td>
+<td align="center">MC17</td>
+<td align="center">STD</td>
+<td align="center"> </td>
+<td align="center">51</td>
+<td align="center">I/O</td>
+<td align="center">I</td>
+<td align="center">RESET</td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('IDE_BASEADR5_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">IDE_BASEADR&lt;5&gt;</a></td>
+<td align="center">4</td>
+<td align="center">16</td>
+<td align="center"><a href="javascript:showFB('FB5')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB5</a></td>
+<td align="center">MC14</td>
+<td align="center">STD</td>
+<td align="center"> </td>
+<td align="center">61</td>
+<td align="center">I/O</td>
+<td align="center">I</td>
+<td align="center">RESET</td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('IDE_BASEADR4_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">IDE_BASEADR&lt;4&gt;</a></td>
+<td align="center">4</td>
+<td align="center">16</td>
+<td align="center"><a href="javascript:showFB('FB5')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB5</a></td>
+<td align="center">MC15</td>
+<td align="center">STD</td>
+<td align="center"> </td>
+<td align="center">64</td>
+<td align="center">I/O</td>
+<td align="center">I</td>
+<td align="center">RESET</td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('ROM_B0_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">ROM_B&lt;0&gt;</a></td>
+<td align="center">0</td>
+<td align="center">0</td>
+<td align="center"><a href="javascript:showFB('FB5')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB5</a></td>
+<td align="center">MC10</td>
+<td align="center">STD</td>
+<td align="center">FAST</td>
+<td align="center">68</td>
+<td align="center">I/O</td>
+<td align="center">O</td>
+<td align="center"> </td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('ROM_B1_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">ROM_B&lt;1&gt;</a></td>
+<td align="center">0</td>
+<td align="center">0</td>
+<td align="center"><a href="javascript:showFB('FB5')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB5</a></td>
+<td align="center">MC17</td>
+<td align="center">STD</td>
+<td align="center">FAST</td>
+<td align="center">69</td>
+<td align="center">I/O</td>
+<td align="center">O</td>
+<td align="center"> </td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('SHUT_UP1_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">SHUT_UP&lt;1&gt;</a></td>
+<td align="center">3</td>
+<td align="center">15</td>
+<td align="center"><a href="javascript:showFB('FB5')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB5</a></td>
+<td align="center">MC13</td>
+<td align="center">STD</td>
+<td align="center"> </td>
+<td align="center">70</td>
+<td align="center">I/O</td>
+<td align="center">(b)</td>
+<td align="center">RESET</td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('DTACK')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">DTACK</a></td>
+<td align="center">0</td>
+<td align="center">0</td>
+<td align="center"><a href="javascript:showFB('FB7')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB7</a></td>
+<td align="center">MC12</td>
+<td align="center">STD</td>
+<td align="center">FAST</td>
+<td align="center">85</td>
+<td align="center">I/O</td>
+<td align="center">O</td>
+<td align="center"> </td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('ide')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">ide</a></td>
+<td align="center">19</td>
+<td align="center">19</td>
+<td align="center"><a href="javascript:showFB('FB4')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB4</a></td>
+<td align="center">MC1</td>
+<td align="center">STD</td>
+<td align="center"> </td>
+<td align="center">118</td>
+<td align="center">I/O</td>
+<td align="center">(b)</td>
+<td align="center">RESET</td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('D15_BUFR_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">D&lt;15&gt;_BUFR</a></td>
+<td align="center">14</td>
+<td align="center">15</td>
+<td align="center"><a href="javascript:showFB('FB6')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB6</a></td>
+<td align="center">MC17</td>
+<td align="center">STD</td>
+<td align="center"> </td>
+<td align="center">125</td>
+<td align="center">I/O</td>
+<td align="center">(b)</td>
+<td align="center">RESET</td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('ideide_CLKF_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">ide/ide_CLKF</a></td>
+<td align="center">2</td>
+<td align="center">2</td>
+<td align="center"><a href="javascript:showFB('FB4')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB4</a></td>
+<td align="center">MC16</td>
+<td align="center">STD</td>
+<td align="center"> </td>
+<td align="center">139</td>
+<td align="center">I/O</td>
+<td align="center">(b)</td>
+<td align="center"> </td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('autoconfig')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">autoconfig</a></td>
+<td align="center">4</td>
+<td align="center">13</td>
+<td align="center"><a href="javascript:showFB('FB4')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB4</a></td>
+<td align="center">MC17</td>
+<td align="center">STD</td>
+<td align="center"> </td>
+<td align="center">140</td>
+<td align="center">I/O</td>
+<td align="center">(b)</td>
+<td align="center">RESET</td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('D14_BUFR_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">D&lt;14&gt;_BUFR</a></td>
+<td align="center">18</td>
+<td align="center">15</td>
+<td align="center"><a href="javascript:showFB('FB2')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB2</a></td>
+<td align="center">MC1</td>
+<td align="center">STD</td>
+<td align="center"> </td>
+<td align="center">142</td>
+<td align="center">I/O</td>
+<td align="center">(b)</td>
+<td align="center">RESET</td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('AUTOCONFIG_IN_PROGRESS')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">AUTOCONFIG_IN_PROGRESS</a></td>
+<td align="center">2</td>
+<td align="center">3</td>
+<td align="center"><a href="javascript:showFB('FB1')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB1</a></td>
+<td align="center">MC7</td>
+<td align="center">STD</td>
+<td align="center"> </td>
+<td align="center"> </td>
+<td align="center">(b)</td>
+<td align="center">(b)</td>
+<td align="center">D</td>
+<td align="center"> </td>
+<td align="center"> </td>
+<td align="center">RESET</td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('D12_BUFR_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">D&lt;12&gt;_BUFR</a></td>
+<td align="center">19</td>
+<td align="center">16</td>
+<td align="center"><a href="javascript:showFB('FB1')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB1</a></td>
+<td align="center">MC18</td>
+<td align="center">STD</td>
+<td align="center"> </td>
+<td align="center"> </td>
+<td align="center">(b)</td>
+<td align="center">(b)</td>
+<td align="center">D</td>
+<td align="center"> </td>
+<td align="center"> </td>
+<td align="center">RESET</td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('AUTO_CONFIG_DONE_CYCLE1_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">AUTO_CONFIG_DONE_CYCLE&lt;1&gt;</a></td>
+<td align="center">3</td>
+<td align="center">14</td>
+<td align="center"><a href="javascript:showFB('FB3')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB3</a></td>
+<td align="center">MC16</td>
+<td align="center">STD</td>
+<td align="center"> </td>
+<td align="center"> </td>
+<td align="center">(b)</td>
+<td align="center">(b)</td>
+<td align="center">D</td>
+<td align="center"> </td>
+<td align="center"> </td>
+<td align="center">RESET</td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('IDE_BASEADR2_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">IDE_BASEADR&lt;2&gt;</a></td>
+<td align="center">4</td>
+<td align="center">16</td>
+<td align="center"><a href="javascript:showFB('FB3')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB3</a></td>
+<td align="center">MC18</td>
+<td align="center">STD</td>
+<td align="center"> </td>
+<td align="center"> </td>
+<td align="center">(b)</td>
+<td align="center">(b)</td>
+<td align="center">T</td>
+<td align="center"> </td>
+<td align="center"> </td>
+<td align="center">RESET</td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('IDE_BASEADR1_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">IDE_BASEADR&lt;1&gt;</a></td>
+<td align="center">4</td>
+<td align="center">16</td>
+<td align="center"><a href="javascript:showFB('FB5')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB5</a></td>
+<td align="center">MC16</td>
+<td align="center">STD</td>
+<td align="center"> </td>
+<td align="center"> </td>
+<td align="center">(b)</td>
+<td align="center">(b)</td>
+<td align="center">T</td>
+<td align="center"> </td>
+<td align="center"> </td>
+<td align="center">RESET</td>
+</tr>
+<tr>
+<td width="28%"><a href="javascript:showEqn('IDE_BASEADR0_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">IDE_BASEADR&lt;0&gt;</a></td>
+<td align="center">4</td>
+<td align="center">16</td>
+<td align="center"><a href="javascript:showFB('FB5')" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB5</a></td>
+<td align="center">MC18</td>
+<td align="center">STD</td>
+<td align="center"> </td>
+<td align="center"> </td>
+<td align="center">(b)</td>
+<td align="center">(b)</td>
+<td align="center">T</td>
+<td align="center"> </td>
+<td align="center"> </td>
+<td align="center">RESET</td>
+</tr>
+</table></span><form><span class="pgRef"><table width="90%" align="center"><tr>
+<td align="left"><input type="button" onclick="javascript:parent.leftnav.showTop()" onmouseover="window.status='goto top of page'; return true;" onmouseout="window.status=''" value="back to top"></td>
+<td align="right">
+<input type="button" onclick="javascript:showLegend('logiclegend.htm')" onmouseover="window.status='show Legend'; return true;" onmouseout="window.status=''" value="legend"><input type="button" onclick="window.print()" onmouseover="window.status='print page'; return true;" onmouseout="window.status=''" value="print page">
+</td>
+</tr></table></span></form>
+</body>
+</html>
diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/maplogicdoc.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/maplogicdoc.htm
new file mode 100644
index 0000000..75e0468
--- /dev/null
+++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/maplogicdoc.htm
@@ -0,0 +1,167 @@
+<!doctype html public "-//w3c//dtd html 4.0 transitional//en">
+<html>
+<head>
+   <meta http-equiv="Content-Type" content="text/html; charset=iso-8859-1">
+   <meta name="generator" content="RoboHELP by eHelp Corporation - www.ehelp.com">
+   <meta name="generator-major-version" content="0.1">
+   <meta name="generator-minor-version" content="1">
+   <meta name="filetype" content="kadov">
+   <meta name="filetype-version" content="1">
+   <meta name="page-count" content="1">
+   <meta name="layout-height" content="1506">
+   <meta name="layout-width" content="639">
+   <meta name="date" content="05 24, 2002 5:49:09 PM">
+   <meta name="GENERATOR" content="Mozilla/4.79 [en]C-CCK-MCD   (Windows NT 5.0; U) [Netscape]">
+   <title>Mapped Logic</title>
+<!--(==============================================================)-->
+<!--(Document created with RoboEditor. )============================-->
+<!--(==============================================================)-->
+<!--(Meta)==========================================================-->
+<style>
+<!--
+ul.whs1 {list-style: disc;}
+p.whs2 {margin-left: 80px;}
+ul.whs3 {list-style: disc;}
+p.whs4 {margin-left: 80px; font-family: arial, sans-serif; font-size: 10pt;}
+ul.whs5 {list-style: disc;}
+p.whs6 {margin-left: 80px; font-family: arial, sans-serif; font-size: 10pt;}
+p.whs7 {margin-left: 80px; font-family: arial, sans-serif; font-size: 10pt;}
+ul.whs8 {list-style: disc;}
+p.whs9 {margin-left: 80px; font-family: arial, sans-serif; font-size: 10pt;}
+p.whs10 {margin-left: 80px; font-family: arial, sans-serif; font-size: 10pt;}
+ul.whs11 {list-style: disc;}
+
+--></style>
+<script language="javascript" title="WebHelpInlineScript">
+<!--
+function reDo() {
+  if (innerWidth != origWidth || innerHeight != origHeight)
+     location.reload();
+}
+if ((parseInt(navigator.appVersion) == 4) && (navigator.appName == "Netscape")) {
+	origWidth = innerWidth;
+	origHeight = innerHeight;
+	onresize = reDo;
+}
+//-->
+</script>
+<style>
+<!--
+  div.WebHelpPopupMenu {position:absolute; left:0px; top:0px; z-index:4; visibility:hidden;}
+  p.WebHelpNavBar {text-align:right;}
+-->
+</style>
+<!--(Body)==========================================================-->
+</head>
+<body>
+
+<h1>
+Mapped Logic</h1>
+<span style="font-family: arial, sans-serif; font-size: 10pt;"><font size=-1>The
+Mapped Logic section provides a table listing resources allocated by the
+fitter to mapped logic. The page will appear in your browser sorted by
+Signal Name, but you can choose to sort it by Signal Name, Function Block,
+and Pin Number by clicking on the appropriate table headers.&nbsp;</font></span><!--begin!kadov{{-->
+<br><!--}}end!kadov--><!--kadov_tag{{<implicit_p>}}--><!--begin!kadov{{-->
+<br><!--}}end!kadov--><!--kadov_tag{{<implicit_p>}}--><span 
+ style="font-family: arial, sans-serif; font-size: 10pt;"><font size=-1>The
+Mapped Logic table contains the following:&nbsp;</font></span>
+<ul type="disc" class="whs1">
+<li class="kadov-p" class="kadov-p">
+<span style="font-family: arial, sans-serif; font-size: 10pt;"><font size=-1>The
+output signal name&nbsp;</font></span></li>
+</ul>
+
+<div class="whs2"><span style="font-weight: bold;
+											font-family: arial, sans-serif;
+											font-size: 10pt;"><font size=-1><b>Note:</span><span 
+ style="font-family: arial, sans-serif; font-size: 10pt;"></b>
+Clicking on the signal name will open a new window with the equations for
+that signal.&nbsp;</font></span></div>
+
+<ul type="disc" class="whs3">
+<li class="kadov-p" class="kadov-p">
+<span style="font-family: arial, sans-serif; font-size: 10pt;"><font size=-1>The
+total number of product terms&nbsp;</font></span></li>
+
+<li class="kadov-p" class="kadov-p">
+<span style="font-family: arial, sans-serif; font-size: 10pt;"><font size=-1>The
+number of signals used&nbsp;</font></span></li>
+
+<li class="kadov-p" class="kadov-p">
+<span style="font-family: arial, sans-serif; font-size: 10pt;"><font size=-1>The
+function block number - an asterisk "<b>*</b>" indicates a user assignment&nbsp;</font></span></li>
+</ul>
+
+<div class="whs4"><span style="font-weight: bold;"><b>Note:</span></b>
+Clicking on the function block will provide a detailed table of all the
+block's resources and a graphical display of the function block diagram
+(see <a href="fbs_FBdoc.htm">Function Block Specifics</a> for more details).</div>
+
+<ul type="disc" class="whs5">
+<li class="kadov-p" class="kadov-p">
+<span style="font-family: arial, sans-serif; font-size: 10pt;"><font size=-1>The
+macrocell number</font></span></li>
+</ul>
+
+<div class="whs6"><span style="font-weight: bold;"><b>Note:</span></b>
+Clicking on the underscored macrocell number will provide a graphical display
+of the macrocell that looks like this:</div>
+
+
+<p class="whs7"><script LANGUAGE="JavaScript"><!--
+if (navigator.appName=="Netscape")
+{ document.write("<img src='macrocell.gif' x-maintain-ratio='TRUE' width='540' height='420' border='0'>");}
+else
+{ document.write("<img src='macrocell.gif' x-maintain-ratio='TRUE' style='border: none; width: 540px; height: 420px; float: none;' width='540' height='420' border='0'>");}
+//--></script>
+.
+<ul type="disc" class="whs8">
+<li class="kadov-p" class="kadov-p">
+<span style="font-family: arial, sans-serif; font-size: 10pt;"><font size=-1>The
+slew rate</font></span></li>
+
+<li class="kadov-p" class="kadov-p">
+<span style="font-family: arial, sans-serif; font-size: 10pt;"><font size=-1>The
+pin number - an asterisk "<b>*</b>" indicates a user assignment&nbsp;</font></span></li>
+</ul>
+
+<div class="whs9"><span style="font-weight: bold;"><b>Note:</span></b>
+Clicking on the underscored pin number will provide the pin layout diagram
+for the highlighted pin.&nbsp;<!--kadov_tag{{<spaces>}}--><!--kadov_tag{{</spaces>}}-->Rolling
+your mouse over the colored pin will pop up a tooltip with the signal name
+assigned to the pin, the I/O standard,&nbsp;<!--kadov_tag{{<spaces>}}--><!--kadov_tag{{</spaces>}}-->the
+I/O style, the slew rate, and/or any constraints assigned to the pin:</div>
+
+
+<p class="whs10"><script LANGUAGE="JavaScript"><!--
+if (navigator.appName=="Netscape")
+{ document.write("<img src='pin.gif' x-maintain-ratio='TRUE' width='309' height='312' border='0'>");}
+else
+{ document.write("<img src='pin.gif' x-maintain-ratio='TRUE' style='border: none; width: 309px; height: 312px; float: none;' width='309' height='312' border='0'>");}
+//--></script>
+
+<ul type="disc" class="whs11">
+<li class="kadov-p" class="kadov-p">
+<span style="font-family: arial, sans-serif; font-size: 10pt;"><font size=-1>The
+pin type</font></span></li>
+
+<li class="kadov-p" class="kadov-p">
+<span style="font-family: arial, sans-serif; font-size: 10pt;"><font size=-1>The
+pin use</font></span></li>
+
+<li class="kadov-p" class="kadov-p">
+<span style="font-family: arial, sans-serif; font-size: 10pt;"><font size=-1>The
+input register use</font></span></li>
+
+<li class="kadov-p" class="kadov-p">
+<span style="font-family: arial, sans-serif; font-size: 10pt;"><font size=-1>The
+I/O standard</font></span></li>
+
+<li class="kadov-p" class="kadov-p">
+<span style="font-family: arial, sans-serif; font-size: 10pt;"><font size=-1>The
+I/O style</font></span></li>
+</ul>
+
+</body>
+</html>
diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/newappletref.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/newappletref.htm
new file mode 100644
index 0000000..37f3d7f
--- /dev/null
+++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/newappletref.htm
@@ -0,0 +1,14 @@
+<html>
+  <head>
+    <title></title>
+  </head>
+  <frameset frameborder="NO" framespacing="0" border="0" rows="94,*,0,0" cols="*">
+    <frame name="topnav" src="../tim/topnav.htm" scrolling="no" noresize marginwidth="0" marginheight="0">
+    <frameset frameborder="NO" framespacing="0" border="0" cols="125,*">
+      <frame name="leftnav" noresize src="leftnav.htm" marginwidth="0" marginheight="0">
+      <frame name="content" src="summary.htm">
+    </frameset>
+    <frame name="eqns" src="eqns.htm" scrolling="no">
+  </frameset>
+</html>
+
diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/next.jpg b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/next.jpg
new file mode 100644
index 0000000..b8bbb99
Binary files /dev/null and b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/next.jpg differ
diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/ns4plugin.js b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/ns4plugin.js
new file mode 100644
index 0000000..0292ee1
--- /dev/null
+++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/ns4plugin.js
@@ -0,0 +1,55 @@
+
+function checkJre(){
+
+var agt=navigator.userAgent.toLowerCase();
+var is_major = parseInt(navigator.appVersion);
+
+
+var is_nav = ((agt.indexOf('mozilla')!=-1) && (agt.indexOf('spoofer')== -1)
+&& (agt.indexOf('compatible') == -1) && (agt.indexOf('opera')== -1)
+&& (agt.indexOf('webtv')==-1) && (agt.indexOf('hotjava')== -1));
+var is_nav4up = (is_nav && (is_major >= 4)); 
+
+var pluginDetected = false;
+
+// we can check for plugin existence only when browser is 'is_ie5up' or 'is_nav4up'
+if(is_nav4up) {
+
+  // Refresh 'navigator.plugins' to get newly installed plugins.
+  // Use 'navigator.plugins.refresh(false)' to refresh plugins 
+  // without refreshing open documents (browser windows)
+  if(navigator.plugins) { 
+    navigator.plugins.refresh(false);
+  }
+
+  // check for Java plugin in installed plugins
+  if(navigator.mimeTypes) {
+    // window.alert( navigator.mimeTypes.length); 
+    for (i=0; i <  navigator.mimeTypes.length; i++) {
+      // window.alert( navigator.mimeTypes[i].type); 
+      if( (navigator.mimeTypes[ i].type != null)
+        &&(navigator.mimeTypes[ i].type.indexOf(
+        "application/x-java-applet;jpi-version=1.4") != -1) ) {
+        //window.alert("Found"); 
+        pluginDetected = true; 
+       break;
+      }
+
+    }
+  }
+
+} 
+
+if (pluginDetected) {
+  // show applet page
+  document.location.href="appletref.htm";
+
+} else if (confirm("Java Plugin 1.4+ not found, Do you want to download it?\n" + 
+                   "if you choose not to install the plugin  the reports graphical applets will not be available.")) {
+  document.location.href=XilinxD;
+} else {
+  document.location.href="appletref.htm";
+}
+
+}
+
diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/options.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/options.htm
new file mode 100644
index 0000000..afaa252
--- /dev/null
+++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/options.htm
@@ -0,0 +1,106 @@
+<html>
+<head>
+<meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+<script src="paths.js"></script><script src="summary.js"></script><link rel="stylesheet" type="text/css" href="../tim/toc.css">
+</head>
+<body class="pgBgnd" id="XC95144XL">
+<span id="options" class="pgRef"><h3 align="center">Compiler Options</h3>
+<table align="center" width="90%" border="1" cellpadding="0" cellspacing="0">
+<tr>
+<th width="50%">Option</th>
+<th width="30%">Value</th>
+</tr>
+<tr>
+<td width="50%"> <b>Device(s) Specified</b>
+</td>
+<td width="30%"> xc95144xl-10-TQ144</td>
+</tr>
+<tr>
+<td width="50%"> <b>Optimization Method</b>
+</td>
+<td width="30%"> SPEED</td>
+</tr>
+<tr>
+<td width="50%"> <b>Multi-Level Logic Optimization</b>
+</td>
+<td width="30%"> ON</td>
+</tr>
+<tr>
+<td width="50%"> <b>Ignore Timing Specifications</b>
+</td>
+<td width="30%"> OFF</td>
+</tr>
+<tr>
+<td width="50%"> <b>Default Register Power Up Value</b>
+</td>
+<td width="30%"> LOW</td>
+</tr>
+<tr>
+<td width="50%"> <b>Slew Rate</b>
+</td>
+<td width="30%"> FAST</td>
+</tr>
+<tr>
+<td width="50%"> <b>Keep User Location Constraints</b>
+</td>
+<td width="30%"> ON</td>
+</tr>
+<tr>
+<td width="50%"> <b>What-You-See-Is-What-You-Get</b>
+</td>
+<td width="30%"> OFF</td>
+</tr>
+<tr>
+<td width="50%"> <b>Exhaustive Fitting</b>
+</td>
+<td width="30%"> OFF</td>
+</tr>
+<tr>
+<td width="50%"> <b>Keep Unused Inputs</b>
+</td>
+<td width="30%"> OFF</td>
+</tr>
+<tr>
+<td width="50%"> <b>Power Mode</b>
+</td>
+<td width="30%"> STD</td>
+</tr>
+<tr>
+<td width="50%"> <b>Ground on Unused IOs</b>
+</td>
+<td width="30%"> OFF</td>
+</tr>
+<tr>
+<td width="50%"> <b>Global Clock Optimization</b>
+</td>
+<td width="30%"> ON</td>
+</tr>
+<tr>
+<td width="50%"> <b>Global Set/Reset Optimization</b>
+</td>
+<td width="30%"> ON</td>
+</tr>
+<tr>
+<td width="50%"> <b>Global Ouput Enable Optimization</b>
+</td>
+<td width="30%"> ON</td>
+</tr>
+<tr>
+<td width="50%"> <b>Set I/O Pin Termination</b>
+</td>
+<td width="30%"> KEEPER</td>
+</tr>
+<tr>
+<td width="50%"> <b>Input Limit</b> (2-54)</td>
+<td width="30%"> 54</td>
+</tr>
+<tr>
+<td width="50%"> <b>Pterm Limit</b> (1-90)</td>
+<td width="30%"> 25</td>
+</tr>
+</table></span><form><span class="pgRef"><table width="90%" align="center"><tr>
+<td align="left"><input type="button" onclick="javascript:parent.leftnav.showTop()" onmouseover="window.status='goto top of page'; return true;" onmouseout="window.status=''" value="back to top"></td>
+<td align="right"><input type="button" onclick="window.print()" onmouseover="window.status='print page'; return true;" onmouseout="window.status=''" value="print page"></td>
+</tr></table></span></form>
+</body>
+</html>
diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/optionsdoc.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/optionsdoc.htm
new file mode 100644
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--- /dev/null
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+<title>Compiler Options</title>
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+
+
+<body>
+
+
+<h1>Compiler Options</h1>
+
+<p class="whs1">The Compiler 
+ Options page provides all the fitter options settings for the device family 
+ the fitter has selected.</p>
+
+<h1 class="whs2">Fitter Options</h1>
+
+<p class="whs3"><a href="#Basic Tab"
+								style="font-family: arial, sans-serif; font-size: 10pt;"><span 
+ style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">Basic Tab</a></FONT></span></p>
+
+<p class="whs4"><a href="#XPLA Advanced Options"
+								style="font-family: arial, sans-serif; font-size: 10pt;"><span 
+ style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">XPLA3 Advanced 
+ Options</a></FONT></span></p>
+
+<p class="whs5"><a href="#CoolRunner-II Advanced Options"
+								style="font-family: arial, sans-serif; font-size: 10pt;"><span 
+ style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">CoolRunner-II 
+ Advanced Options</a></FONT></span></p>
+
+<p class="whs6"><a href="#XC9500/XL/XV Advanced Options"
+								style="font-family: arial, sans-serif; font-size: 10pt;">XC9500/XL/XV 
+ Advanced Options</a></p>
+
+<h2 class="whs7"><a name="Basic Tab"></a>Basic 
+ Tab</h2>
+
+<p class=whs1
+	style="font-family: arial, sans-serif; font-size: 10pt;">The CPLD devices 
+ have the following fitter <span style="font-weight: bold;"><B><b>Implementation 
+ Options </B></span><span style="font-weight: bold;"><B>available</B></span></b> in 
+ the <span style="font-weight: bold;"><B>Basic</B></span> tab:</p>
+
+<ul>
+	
+	<li class=kadov-h4><h4 class="whs8">Use 
+ Multi-Level Logic Optimization</h4></li>
+</ul>
+
+<p class="whs9">This option simplifies the total number 
+ of logic expressions in a design, and then collapses the logic in order 
+ to meet user objectives such as density, speed and timing constraints. 
+ This optimization targets CPLD architecture, making it possible to collapse 
+ to the macrocell limits, reduce levels of logic, and minimize the total 
+ number of p-terms.</p>
+
+<p class="whs10">Multi-level Logic Optimization optimizes 
+ all combinatorial logic arcs spanning from an input pad or register output 
+ to an output pad or register input.</p>
+
+<p class="whs11">Multi-level Logic Optimization operates 
+ on combinatorial logic according to the following rules.</p>
+
+<p class="whs12">If timing constraints are set, the program 
+ optimizes for speed to meet timing constraints.</p>
+
+<p class="whs13">If timing constraints are not set, the 
+ program optimizes either for speed or density, depending on the user setting 
+ for the <span style="font-weight: bold;"><B>Use Timing Optimization</B></span> 
+ option.</p>
+
+<ul>
+	
+	<ul class=whs1
+		style="list-style: disc;"
+		type=disc>
+		
+		<ul class=whs2
+			style="list-style: circle;"
+			type=circle>
+			
+			<li class=kadov-p><p class="whs14">If 
+ <span style="font-weight: bold;"><B>Use Timing Optimization</B></span> is turned 
+ on, the combinatorial logic will be mapped for speed.</p></li>
+			
+			<li class=kadov-p-Cwhs3><p class=whs3
+										style="font-family: arial; font-size: 10pt;">If 
+ <span style="font-weight: bold;"><B>Use Timing Optimization</B></span> is turned 
+ off, the combinatorial logic will be mapped for density. The goal of optimization 
+ will then be to reduce the total number of p-terms.</p></li>
+		</ul>
+	</ul>
+</ul>
+
+<p class="whs15"><font style="font-family: arial; font-size: 10pt;"
+									face=arial
+									size=2><span style="font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">Logic 
+ marked with the </FONT></span><span style="font-weight: bold;"><B><b style="font-size: 10pt;">NOREDUCE</b></B></span><span 
+ style="font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;"> property will not be extracted or optimized.</FONT></span></font></p>
+
+<p class=whs3
+	style="font-family: arial, sans-serif;
+			font-size: 10pt;
+			font-weight: bold;
+			margin-left: 40px;"><span style="font-family: arial; font-weight: normal;">By 
+ default, this option is on.</span> </p>
+
+<ul>
+	
+	<li class=kadov-p-Cwhs3><p class=whs3
+								style="font-family: arial, sans-serif;
+										font-size: 10pt;
+										font-weight: bold;"><b style="font-weight: bold;"><span 
+ style="font-weight: bold;"><B>Use Timing Constraints -- </B></span><span style="font-weight: normal;">This 
+ option instructs the fitter use Timing Constraints when fitting the design. 
+ <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->If this 
+ box is not checked, the fitter will ignore timing constraints, if necessary.</span></b></p></li>
+	
+	<li class=kadov-p-Cwhs3><p class=whs3
+								style="font-family: arial, sans-serif; font-size: 10pt;"><b 
+ style="font-weight: bold;"><span style="font-weight: bold;"><B>Enable WYSIWYG 
+ Mode -- (CoolRunner only) </B></span><span style="font-weight: normal;">T</span></b>he 
+ goal of the WYSIWYG options is to have a netlist reflect the user's specifications, 
+ as much as possible. All the nodes declared in the HDL design are preserved. 
+ By default, this property is set to Off (Checkbox is not checked) When 
+ this property is On (checkbox is checked), XST:</p></li>
+	
+	<ul>
+		
+		<li style="list-style: circle;"
+			type=circle
+			class=kadov-p-Cwhs3><p class=whs3
+									style="font-family: arial, sans-serif; font-size: 10pt;">Preserves 
+ all the user internal signals (nodes)</p></li>
+		
+		<li style="list-style: circle;"
+			type=circle
+			class=kadov-p-Cwhs3><p class=whs3
+									style="font-family: arial, sans-serif; font-size: 10pt;">Creates 
+ source_node constraints in NGC file for all these nodes.</p></li>
+		
+		<li style="list-style: circle;"
+			type=circle
+			class=kadov-p-Cwhs3><p class=whs3
+									style="font-family: arial, sans-serif; font-size: 10pt;">Skips 
+ the design optimization (collapse, factorization). Only the Boolean equation 
+ minimization is performed.</p></li>
+	</ul>
+	
+	<li class=kadov-p-Cwhs3><p class=whs3
+								style="font-family: arial, sans-serif; font-size: 10pt;"><b><span 
+ style="font-weight: bold;"><B>Optimization Style</B></span></b>-- The Optimization 
+ Method allows you to select from one of two basic optimization strategies: 
+ <span style="font-weight: bold;"><B><b>Density</b></B></span> or <span style="font-weight: bold;"><B><b>Speed</b></B></span>. 
+ <span style="font-weight: bold;"><B><b>Density</b></B></span> focuses on solely 
+ on density, and <span style="font-weight: bold;"><B><b>Speed</b></B></span> focuses 
+ solely on speed.</p></li>
+	
+	<li class=kadov-p><p class="whs16"><span 
+ style="font-weight: bold;"><B>Location Constraints</B></span> -- The Try selection 
+ will attempt to fit the design with the pin assignments specified in the 
+ design source. If the design cannot be fit with these pin assignments, 
+ the fitter will remove the location constraints and attempt to fit the 
+ design with no location constraints. A warning message will tell the user 
+ if the location constraints have been removed.</p></li>
+	
+	<ul class=whs5
+		style="list-style: circle;"
+		type=circle>
+		
+		<li class=kadov-p><p class="whs17">The 
+ <span style="font-weight: bold;"><B><b>Try</b></B></span> selection will attempt 
+ to fit the design with the pin assignments specified in the design source. 
+ If the design cannot be fit with these pin assignments, the fitter will 
+ ignore the pin assignments.</p></li>
+	</ul>
+	
+	<li style="list-style: circle;"
+		type=circle
+		class=kadov-p-Cwhs6><p class=whs6
+								style="font-family: arial, sans-serif; font-size: 10pt;">The 
+ <span style="font-weight: bold;"><B>On </B></span>selection will attempt to fit 
+ the design with the pin assignments specified in the design source. If 
+ the design cannot be fit with these pin assignments, the fitter will notify 
+ the user that the device could not fit. It will not unlock the pins under 
+ this option.</p></li>
+	
+	<li style="list-style: circle;"
+		type=circle
+		class=kadov-p-Cwhs7><p class=whs7
+								style="font-family: arial, sans-serif; font-size: 10pt;">The 
+ <span style="font-weight: bold;"><B>Off</B></span> selection will attempt to 
+ fit the design and will ignore the pin assignments specified in the design 
+ source. If the design can be fit with no pre-assigned pins, the fitter 
+ will assign pins, which can be viewed in the fitter report (filename.fit). 
+ The user should take these pin assignments and incorporate them back into 
+ the design source file. The user will be notified whether the fitting 
+ operation was successful.</p></li>
+	
+	<li class=kadov-p-Cwhs8><p class=whs8
+								style="font-family: arial, sans-serif;
+										font-size: 10pt;
+										font-weight: bold;"><b><span style="font-weight: bold;"><B>Output 
+ Slew Rate -- </B></span></b><span style="font-weight: normal;">Use this option 
+ to control the default output slew rate. You can control the transition 
+ time of device output pins by setting the slew rate to Slow or Fast. Limiting 
+ the slew rate (Slow) reduces output switching surges in the device. The 
+ default is Fast.</span></p></li>
+</ul>
+
+<p class="whs18"><span style="font-weight: bold;"><B>Note</B></span>: 
+ Any explicit slew rate control properties in the design or constraints 
+ file take precedence over this Output Slew Rate setting. </p>
+
+<ul>
+	
+	<li class=kadov-p-Cwhs8><p class=whs8
+								style="font-family: arial, sans-serif;
+										font-size: 10pt;
+										font-weight: bold;"><b style="font-weight: bold;"><span 
+ style="font-weight: bold;"><B>FF Initial State -- </B></span><span style="font-weight: normal;">Sets 
+ the initial state for all Flip-Flops. <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->The 
+ options are Low, High and FPGA.</span></b></p></li>
+	
+	<li class=kadov-p-Cwhs8><p class=whs8
+								style="font-family: arial, sans-serif;
+										font-size: 10pt;
+										font-weight: bold;"><b><span style="font-weight: bold;"><B>Collapsing 
+ P-Term Limit -- </B></span></b><span style="font-weight: normal;">This option 
+ controls the degree to which the fitter flattens a design netlist. A logic 
+ gate can collapse forward into a subsequent gate only if the number of 
+ product terms in the resulting logic function does not exceed the p-term 
+ limit. If the path delay of a logic function is not acceptable, increase 
+ the p-term limit to allow the larger functions to be further flattened. 
+ Choose a number from 3 to 48.</span> </p></li>
+	
+	<li class=kadov-p-Cwhs8><p class=whs8
+								style="font-family: arial, sans-serif;
+										font-size: 10pt;
+										font-weight: bold;"><b><span style="font-weight: bold;"><B>Collapsing 
+ Input Limit -- </B></span></b><span style="font-weight: normal;">This is a 
+ secondary option for controlling the degree to which the fitter flattens 
+ a design netlist. A logic gate can collapse forward into a subsequent 
+ gate only if the number of inputs in the resulting logic function does 
+ not exceed the input limit. If the design fails to fit the target device 
+ because flattening uses up too many of the function block inputs, decrease 
+ the input limit to prevent flattening of certain high fan-in functions. 
+ </span><!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}--></p></li>
+</ul>
+
+<h2 class="whs19"><b><span 
+ style="font-weight: bold;"><B><a name="XPLA Advanced Options"></a>XPLA Advanced 
+ Options</B></span></b></h2>
+
+<p class="whs20"><b><span style="font-weight: normal;">The 
+ following options are available under XPLA </span><span style="font-weight: bold;"><B>Implementation 
+ Options</B></span><span style="font-weight: normal;">, </span><span style="font-weight: bold;"><B>Advanced</B></span><span 
+ style="font-weight: normal;"> tab.</span></b></p>
+
+<ul>
+	
+	<li class=kadov-p-Cwhs8><p class=whs8
+								style="font-family: arial, sans-serif;
+										font-size: 10pt;
+										font-weight: bold;">Enable Fast 
+ Input Registers -<span style="font-weight: normal;">- Enables the use 
+ of the Fast Input path in XPLA3 devices.</span></p></li>
+	
+	<li class=kadov-p-Cwhs8><p class=whs8
+								style="font-family: arial, sans-serif;
+										font-size: 10pt;
+										font-weight: bold;">Enable Use 
+ of Foldback NANDs -- <span style="font-weight: normal;">When selected, 
+ the software will use foldback NANDs. This increases the capability to 
+ fit a design, sometimes at the expense of speed.</span></p></li>
+	
+	<li class=kadov-p-Cwhs8><p class=whs8
+								style="font-family: arial, sans-serif; font-size: 10pt;"><span 
+ style="font-weight: bold;"><B>Reserve JTAG Pins for ISP -- </B></span>Checking 
+ this box will instruct the fitter to reserve JTAG pins.</p></li>
+</ul>
+
+<h2 class="whs21"><a name="CoolRunner-II Advanced Options"></a>CoolRunner-II 
+ Advanced Options</h2>
+
+<p class="whs22">The following 
+ options are found under the Advanced tab for CoolRunner-II devices.</p>
+
+<ul type="disc" class="whs23">
+	
+	<li class=kadov-h4><h4 class="whs24">Use 
+ Global Clock(s) -- <span style="font-weight: normal;">Select this option 
+ to allow the fitter to assign input pins used as clocks to dedicated global 
+ clock (GCK) pins of the device. If this option is disabled, only pins 
+ identified with the BUFG=CLK property in the design (or UCF file) will 
+ be assigned to GCK device pins. By default, this option is on.</span> 
+ </h4></li>
+	
+	<li class=kadov-p><p class="whs25"><span 
+ style="font-weight: bold;"><B>Use Global Output Enable(s)</B></span> -- Select 
+ this option to allow the fitter to assign input pins used as output enable 
+ control to dedicated global OE (GTS) pins of the device. If this option 
+ is disabled, only pins identified with the BUFG=OE property in the design 
+ (or UCF file) will be assigned to GTS device pins. By default, this option 
+ is on. </p></li>
+	
+	<li class=kadov-p><p class="whs26"><span 
+ style="font-weight: bold;"><B>Use Global Set/Reset</B></span> -- Select this 
+ option to allow the fitter to assign input pins used as register asynchronous 
+ reset or preset control to the dedicated global set/reset (GSR) pin of 
+ the device. If this option is disabled, only a pin identified with the 
+ BUFG=SR property in the design (or UCF file) will be assigned to the GSR 
+ device pin. By default, this option is on.</p></li>
+	
+	<li class=kadov-p><p class="whs27"><span 
+ style="font-weight: bold;"><B>Enable Fast Input Registers</B></span> -- Enables 
+ fast input registers.</p></li>
+	
+	<li class=kadov-p><p class="whs28"><span 
+ style="font-weight: bold;"><B>Ignore DATA_GATE Attributes</B></span> -- Data 
+ Gate is a power saving property that can be used in CoolRunner-II designs. 
+ <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->This option 
+ allows you to turn Data Gate off in case you want the fitter to ignore 
+ data gate.</p></li>
+	
+	<li class=kadov-p><p class="whs29"><span 
+ style="font-weight: bold;"><B>Tristate Outputs Termination Node</B></span> -- 
+ The Tristate Output Termination Mode globally sets all tristate outputs 
+ to the specified termination mode. By default, this field is set to Pullup.. 
+ <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->The options 
+ are Pullup, Keeper and Float.</p></li>
+	
+	<li class=kadov-p><p class="whs30"><span 
+ style="font-weight: bold;"><B>Create Programmable Ground Pins on Unused I/O</B></span> 
+ -- The Create Programmable GND Pins on Unused I/O property controls the 
+ option to indicate that you want all unused I/O pads to be configured 
+ as ground pins. This can reduce ground bounce. By default, this option 
+ is set to ground. <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->The 
+ options are Ground, Pullup, Keeper and Float.</p></li>
+	
+	<li class=kadov-p>
+	<p class="whs31"><span style="font-weight: bold;"><B>Default 
+ Output Voltage Standard</B></span> -- set a default voltage standard for CoolRunner-II 
+ device pins.</p>
+	
+	<p class="whs32">IOSTANDARD 
+ names supported by CoolRunner-II are:</p>
+	
+	<!--(Table)=====================================================-->
+	<table x-use-null-cells width="84.797%" cellspacing="0" class="whs33">
+	<col class="whs34">
+	<col class="whs35">
+	<col class="whs36">
+	<col class="whs37">
+	
+	<tr valign=top>
+	<td width="20.209%" class="whs38">
+	<p class="whs39">I/O Standard</td>
+	<td width="16.192%" class="whs40">
+	<p align="center" class="whs41">VCC<span style="vertical-align: Sub;">IO</span></td>
+	<td width="22.217%" class="whs42">
+	<p align="center" class="whs43">Input V<span style="vertical-align: Sub;">REF</span></td>
+	<td width="41.383%" class="whs44">
+	<p align="center" class="whs45">Board Termination Voltage (V<span style="vertical-align: Sub;">TT</span>)</td></tr>
+	
+	<tr valign=top>
+	<td width="20.209%" class="whs46">
+	<p class="whs47">LVTTL </td>
+	<td width="16.192%" class="whs48">
+	<p align="center" class="whs49">3.3V</td>
+	<td width="22.217%" class="whs50">
+	<p align="center" class="whs51">N/A</td>
+	<td width="41.383%" class="whs52">
+	<p align="center" class="whs53">N/A</td></tr>
+	
+	<tr valign=top>
+	<td width="20.209%" class="whs54">
+	<p class="whs55">LVCMOS33</td>
+	<td width="16.192%" class="whs56">
+	<p align="center" class="whs57">3.3V</td>
+	<td width="22.217%" class="whs58">
+	<p align="center" class="whs59">N/A</td>
+	<td width="41.383%" class="whs60">
+	<p align="center" class="whs61">N/A</td></tr>
+	
+	<tr valign=top>
+	<td width="20.209%" class="whs62">
+	<p class="whs63">LVCMOS25</td>
+	<td width="16.192%" class="whs64">
+	<p align="center" class="whs65">2.5V</td>
+	<td width="22.217%" class="whs66">
+	<p align="center" class="whs67">N/A</td>
+	<td width="41.383%" class="whs68">
+	<p align="center" class="whs69">N/A</td></tr>
+	
+	<tr valign=top>
+	<td width="20.209%" class="whs70">
+	<p class="whs71">LVCMOS18</td>
+	<td width="16.192%" class="whs72">
+	<p align="center" class="whs73">1.8V</td>
+	<td width="22.217%" class="whs74">
+	<p align="center" class="whs75">N/A</td>
+	<td width="41.383%" class="whs76">
+	<p align="center" class="whs77">N/A</td></tr>
+	
+	<tr valign=top>
+	<td width="20.209%" class="whs78">
+	<p class="whs79">LVCMOS15</td>
+	<td width="16.192%" class="whs80">
+	<p align="center" class="whs81">1.5V</td>
+	<td width="22.217%" class="whs82">
+	<p align="center" class="whs83">N/A</td>
+	<td width="41.383%" class="whs84">
+	<p align="center" class="whs85">N/A</td></tr>
+	
+	<tr valign=top>
+	<td width="20.209%" class="whs86">
+	<p class="whs87">HSTL_I</td>
+	<td width="16.192%" class="whs88">
+	<p align="center" class="whs89">1.5V</td>
+	<td width="22.217%" class="whs90">
+	<p align="center" class="whs91">0.75V</td>
+	<td width="41.383%" class="whs92">
+	<p align="center" class="whs93">0.75V</td></tr>
+	
+	<tr valign=top>
+	<td width="20.209%" class="whs94">
+	<p class="whs95">SSTL2_I</td>
+	<td width="16.192%" class="whs96">
+	<p align="center" class="whs97">2.5V</td>
+	<td width="22.217%" class="whs98">
+	<p align="center" class="whs99">1.25V</td>
+	<td width="41.383%" class="whs100">
+	<p align="center" class="whs101">1.25V</td></tr>
+	
+	<tr valign=top>
+	<td width="20.209%" class="whs102">
+	<p class="whs103">SSTL3_I</td>
+	<td width="16.192%" class="whs104">
+	<p align="center" class="whs105">3.3V</td>
+	<td width="22.217%" class="whs106">
+	<p align="center" class="whs107">1.5V</td>
+	<td width="41.383%" class="whs108">
+	<p align="center" class="whs109">1.5V</td></tr>
+	</table>
+	
+	<p class="whs110">The software 
+ automatically groups outputs with similar IOSTANDARD settings into the 
+ same bank when no location constraints are specified. </p>
+	</li>
+</ul>
+
+<h2 class="whs111"><a name="XC9500/XL/XV Advanced Options"></a>XC9500/XL/XV 
+ Advanced Options</h2>
+
+<p class="whs112">The following 
+ options are found under the Advanced tab for XC9500/XL/XV. <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->Note 
+ that additional options for XC9500 only are also described below.</p>
+
+<ul type="disc" class="whs113">
+	
+	<li class=kadov-h4><h4 class="whs114">Use 
+ Global Clock(s) -- <span style="font-weight: normal;">Select this option 
+ to allow the fitter to assign input pins used as clocks to dedicated global 
+ clock (GCK) pins of the device. If this option is disabled, only pins 
+ identified with the BUFG=CLK property in the design (or UCF file) will 
+ be assigned to GCK device pins. By default, this option is on.</span> 
+ </h4></li>
+	
+	<li class=kadov-p><p class="whs115"><span 
+ style="font-weight: bold;"><B>Use Global Output Enable(s)</B></span> -- Select 
+ this option to allow the fitter to assign input pins used as output enable 
+ control to dedicated global OE (GTS) pins of the device. If this option 
+ is disabled, only pins identified with the BUFG=OE property in the design 
+ (or UCF file) will be assigned to GTS device pins. By default, this option 
+ is on. </p></li>
+	
+	<li class=kadov-p><p class="whs116"><span 
+ style="font-weight: bold;"><B>Use Global Set/Reset</B></span> -- Select this 
+ option to allow the fitter to assign input pins used as register asynchronous 
+ reset or preset control to the dedicated global set/reset (GSR) pin of 
+ the device. If this option is disabled, only a pin identified with the 
+ BUFG=SR property in the design (or UCF file) will be assigned to the GSR 
+ device pin. By default, this option is on.</p></li>
+	
+	<li class=kadov-p><p class="whs117"><span 
+ style="font-weight: bold;"><B>Create Programmable Ground Pins on Unused I/O</B></span> 
+ -- Select this option to indicate that you want all unused I/O pads to 
+ be configured as ground pins. This can reduce ground bounce. By default, 
+ this option is off.</p></li>
+	
+	<li class=kadov-p><p class="whs118"><span 
+ style="font-weight: bold;"><B>Macrocell Power Setting</B></span> -- Use this 
+ option to control device power consumption. Select Low or Standard to 
+ set the default power mode for the macrocells used to implement the design. 
+ Select Timing Driven to automatically reduce power on paths covered by 
+ timing specifications that can meet speed requirements while operating 
+ in low power. The default is Standard, which results in highest speed.</p></li>
+</ul>
+
+<p class="whs119">Note: Any explicit power control (PWR_MODE) 
+ properties in the design or constraints file take precedence over this 
+ Macrocell Power Setting. </p>
+
+<ul type="disc" class="whs120">
+	
+	<li class=kadov-p><p class="whs121"><span 
+ style="font-weight: bold;"><B>Enable FASTConnect/UIM Optimization (XC9500 
+ only)</B></span> -- Enables optimization of the FASTConnect/UIM for XC9500 
+ devices.</p></li>
+	
+	<li class=kadov-h4><h4 class="whs122">Use 
+ Local Feedback (XC9500 only)</h4></li>
+</ul>
+
+<p class="whs123">Select this option to enable the software 
+ to use local macrocell feedback whenever possible. The local feedback 
+ path, running from each macrocell output to an input of the same function 
+ block, has shorter propagation delay than the global feedback path. The 
+ fitter always tries to use local macrocell feedback (if possible) to satisfy 
+ timing constraints. This option allows the fitter to use local feedback 
+ to generally improve timing on remaining paths. Using local feedback can 
+ speed up your design but could also make it difficult to maintain the 
+ same timing after a design change. By default, this option is on.</p>
+
+
+<!--(HR)============================================================-->
+<hr class=whs4
+	style="margin-left: 40px; /*begin!kadov{{*/ float: aligncenter; /*}}end!kadov*/ "
+	align=center>
+
+
+<p class="whs124"><b><span style="font-weight: bold;"><B>Note: 
+ </B></span></b>To force the fitter to use local feedback, manually map both 
+ the source and load functions into the same function block using the property 
+ <span style="font-weight: bold;"><B><b>LOC=FB</b></B></span><span style="font-style: italic;"><I><i>nn</i></I></span>, 
+ then apply a timespec across the path.&nbsp;</p>
+
+
+<!--(HR)============================================================-->
+<hr class=whs5
+	style="margin-left: 40px; /*begin!kadov{{*/ float: aligncenter; /*}}end!kadov*/ "
+	align=center>
+
+
+<p class="whs125"><span><FONT SIZE=2 style="font-size:10pt;"><b style="font-weight: bold;">Note: 
+ </b></FONT></span>The XC9536 device does not have local feedback.</p>
+
+
+<!--(HR)============================================================-->
+<hr class=whs6
+	style="margin-left: 40px; /*begin!kadov{{*/ float: aligncenter; /*}}end!kadov*/ "
+	align=center>
+
+
+<ul type="disc" class="whs126">
+	
+	<li class=kadov-h4><h4 class="whs127">Use 
+ Pin Feedback (XC9500 only)</h4></li>
+</ul>
+
+<p class="whs128">Select this option to enable the software 
+ to use I/O pin feedback whenever possible. The pin feedback path has slightly 
+ shorter propagation delay than the global feedback path. If this option 
+ is enabled, the software uses the pin feedback path instead of the global 
+ feedback path for macrocell signals that do not drive 3-state outputs 
+ or slew-rate-limited outputs, and where the associated I/O pin is not 
+ used as input-only. By default, this option is on.</p>
+
+</body>
+
+</html>
diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/paths.js b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/paths.js
new file mode 100644
index 0000000..ff4aa89
--- /dev/null
+++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/paths.js
@@ -0,0 +1,39 @@
+rootURL = "http://www.xilinx.com/";
+prodURL = "xlnx/xil_prodcat_product.jsp?title=";
+cpldURL = "CPLD+Products";
+acr2URL = "coolrunner2_page";
+xbrURL = "coolrunner2_page";
+xpla3URL = "xpla3_page";
+xc9500URL = "xc9500_page";
+xc9500xlURL = "xc9500xl_page";
+xa9500xlURL = "xc9500xl_page";
+xc9500xvURL = "xc9500xv_page";
+marketURL= "esp";
+supportURL = "http://www.support.xilinx.com/";
+educationURL = "support/education-home.htm";
+buyURL = "http://toolbox.xilinx.com/cgi-bin/xilinx.storefront";
+contactURL = "company/contact.htm";
+searchURL = "company/search.htm";
+
+docURL = rootURL + "support/documentation/";
+doc95URL = docURL + "xc9500.htm";
+doc95xlURL = docURL + "xc9500xl.htm";
+docA95xlURL = docURL + "xc9500xl.htm";
+doc95xvURL = docURL + "xc9500xv.htm";
+docXpla3URL = docURL + "coolrunner_xpla3.htm";
+docAcr2URL = docURL + "coolrunner-ii.htm";
+docXbrURL = docURL + "coolrunner-ii.htm";
+docCr2sURL = docURL + "coolrunner-ii.htm";
+
+var messages = new Array();
+messages["fastinreg"] = "Direct Input Register";
+messages["inreg"] = "Direct Input Register";
+messages["fbnand"] = "Foldback NAND";
+messages["fcnode"] = "FC node";
+messages["LATCH"] = "Transparent latch";
+messages["DFF"] = "D-flip-flop";
+messages["DEFF"] = "D-flip-flop with clock enable";
+messages["TFF"] = "T-flip-flop";
+messages["TDFF"] = "Dual-edge-triggered T-flip-flop";
+messages["DDFF"] = "Dual-edge-triggered flip-flop";
+messages["DDEFF"] = "Dual-edge-triggered flip-flop with clock enable";
diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/pin.gif b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/pin.gif
new file mode 100644
index 0000000..f110f3d
Binary files /dev/null and b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/pin.gif differ
diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/pin_legXC95.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/pin_legXC95.htm
new file mode 100644
index 0000000..db88bcb
--- /dev/null
+++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/pin_legXC95.htm
@@ -0,0 +1,13 @@
+<html><body><pre>
+Legend :  NC  = Not Connected, unbonded pin
+         PGND = Unused I/O configured as additional Ground pin
+         TIE  = Unused I/O floating -- must tie to VCC, GND or other signal
+         VCC  = Dedicated Power Pin
+         GND  = Dedicated Ground Pin
+         TDI  = Test Data In, JTAG pin
+         TDO  = Test Data Out, JTAG pin
+         TCK  = Test Clock, JTAG pin
+         TMS  = Test Mode Select, JTAG pin
+         PE   = Port Enable pin
+  PROHIBITED  = User reserved pin
+</pre></body></html>
diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/pin_legXbr.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/pin_legXbr.htm
new file mode 100644
index 0000000..00a6d2c
--- /dev/null
+++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/pin_legXbr.htm
@@ -0,0 +1,21 @@
+<html><body><pre>
+Legend :  NC  = Not Connected, unbonded pin
+        PGND  = Unused I/O configured as additional Ground pin
+         KPR  = Unused I/O with weak keeper (leave unconnected)
+         WPU  = Unused I/O with weak pull up (leave unconnected)
+         WPD  = Unused I/O with weak pull down (leave unconnected)
+         TIE  = Unused I/O floating -- must tie to VCC, GND or other signal
+         VCC  = Dedicated Power Pin
+      VCCAUX  = Power supply for JTAG pins
+   VCCIO-3.3  = I/O supply voltage for LVTTL, LVCMOS33, SSTL3_I
+   VCCIO-2.5  = I/O supply voltage for LVCMOS25, SSTL2_I
+   VCCIO-1.8  = I/O supply voltage for LVCMOS18
+   VCCIO-1.5  = I/O supply voltage for LVCMOS15, HSTL_I
+        VREF  = Reference voltage for indicated input standard
+         GND  = Dedicated Ground Pin
+         TDI  = Test Data In, JTAG pin
+         TDO  = Test Data Out, JTAG pin
+         TCK  = Test Clock, JTAG pin
+         TMS  = Test Mode Select, JTAG pin
+  PROHIBITED  = User reserved pin
+</pre></body></html>
diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/pin_legXpla3.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/pin_legXpla3.htm
new file mode 100644
index 0000000..8dad55d
--- /dev/null
+++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/pin_legXpla3.htm
@@ -0,0 +1,13 @@
+<html><body><pre>
+Legend :  NC  = Not Connected, unbonded pin
+          PE  = Port Enable pin
+         WPU  = Unused with Internal Weak Pull Up
+         TIE  = Unused I/O floating -- must tie to VCC, GND or other signal
+         VCC  = Dedicated Power Pin
+         GND  = Dedicated Ground Pin
+         TDI  = Test Data In, JTAG pin
+         TDO  = Test Data Out, JTAG pin
+         TCK  = Test Clock, JTAG pin
+         TMS  = Test Mode Select, JTAG pin
+  PROHIBITED  = User reserved pin
+</pre></body></html>
diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/pindiagram.gif b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/pindiagram.gif
new file mode 100644
index 0000000..504bb2b
Binary files /dev/null and b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/pindiagram.gif differ
diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/pinlegend.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/pinlegend.htm
new file mode 100644
index 0000000..26f2262
--- /dev/null
+++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/pinlegend.htm
@@ -0,0 +1,150 @@
+<html>
+<head>
+<meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+<link rel="stylesheet" type="text/css" href="style.css">
+<script>
+      function showTop() { document.location.href = '#'; }
+    </script>
+</head>
+<body class="pgBgnd">
+<span id="legend" class="pgRef"><h3 align="center">Legends</h3>
+<table align="center" width="90%" border="0" cellpadding="0" cellspacing="0"><tr><td align="right"><form><input type="button" onclick="javascript:document.location.href='pinlegendV.htm'" value="verbose"></form></td></tr></table>
+<table align="center" width="90%" border="1" cellpadding="0" cellspacing="0">
+<tr>
+<th width="20%">Acronym</th>
+<th width="80%">Brief Description</th>
+</tr>
+<tr>
+<td width="20%"> CLK</td>
+<td width="80%"> Clock</td>
+</tr>
+<tr>
+<td width="20%"> GCK0</td>
+<td width="80%"> Global Clock 0</td>
+</tr>
+<tr>
+<td width="20%"> GCK1</td>
+<td width="80%"> Global Clock 1</td>
+</tr>
+<tr>
+<td width="20%"> GCK2</td>
+<td width="80%"> Global Clock 2</td>
+</tr>
+<tr>
+<td width="20%"> GND</td>
+<td width="80%"> Ground</td>
+</tr>
+<tr>
+<td width="20%"> GSR</td>
+<td width="80%"> Global Set/Reset</td>
+</tr>
+<tr>
+<td width="20%"> GTS0</td>
+<td width="80%"> Global Output Enable 0</td>
+</tr>
+<tr>
+<td width="20%"> GTS1</td>
+<td width="80%"> Global Output Enable 1</td>
+</tr>
+<tr>
+<td width="20%"> GTS2</td>
+<td width="80%"> Global Output Enable 2</td>
+</tr>
+<tr>
+<td width="20%"> GTS3</td>
+<td width="80%"> Global Output Enable 3</td>
+</tr>
+<tr>
+<td width="20%"> I/O</td>
+<td width="80%"> Input/Output</td>
+</tr>
+<tr>
+<td width="20%"> INIT</td>
+<td width="80%"> Initial state</td>
+</tr>
+<tr>
+<td width="20%"> ISP</td>
+<td width="80%"> In system programmable</td>
+</tr>
+<tr>
+<td width="20%"> JTAG</td>
+<td width="80%"> Joint Test Action Group</td>
+</tr>
+<tr>
+<td width="20%"> KPR</td>
+<td width="80%"> Unused I/O with weak keeper</td>
+</tr>
+<tr>
+<td width="20%"> NC</td>
+<td width="80%"> No Connects</td>
+</tr>
+<tr>
+<td width="20%"> PGND</td>
+<td width="80%"> Programmable ground pin</td>
+</tr>
+<tr>
+<td width="20%"> PROHIBITED</td>
+<td width="80%"> User reserved pin</td>
+</tr>
+<tr>
+<td width="20%"> R</td>
+<td width="80%"> Reset</td>
+</tr>
+<tr>
+<td width="20%"> S</td>
+<td width="80%"> Set</td>
+</tr>
+<tr>
+<td width="20%"> TCK</td>
+<td width="80%"> Test clock</td>
+</tr>
+<tr>
+<td width="20%"> TDI</td>
+<td width="80%"> Test data input</td>
+</tr>
+<tr>
+<td width="20%"> TDO</td>
+<td width="80%"> Test data output</td>
+</tr>
+<tr>
+<td width="20%"> TIE</td>
+<td width="80%"> Unused I/O floating</td>
+</tr>
+<tr>
+<td width="20%"> TMS</td>
+<td width="80%"> Test mode select</td>
+</tr>
+<tr>
+<td width="20%"> LVCMOS</td>
+<td width="80%"> Low Voltage CMOS 3.3 Volts</td>
+</tr>
+<tr>
+<td width="20%"> LVCMOS25</td>
+<td width="80%"> Low Voltage CMOS 2.5 Volts</td>
+</tr>
+<tr>
+<td width="20%"> LVCMOS33</td>
+<td width="80%"> Low Voltage CMOS 2.5 to 3.3 Volts</td>
+</tr>
+<tr>
+<td width="20%"> LVTTL</td>
+<td width="80%"> Low Voltage TTL 3.3 Volts</td>
+</tr>
+<tr>
+<td width="20%"> VCCIO</td>
+<td width="80%"> Input/Output Supply Voltage</td>
+</tr>
+<tr>
+<td width="20%"> VCC</td>
+<td width="80%"> Power internal</td>
+</tr>
+<tr>
+<td width="20%"> WPU</td>
+<td width="80%"> Weak Pull Up</td>
+</tr>
+</table></span><form><span class="pgRef"><table width="90%" align="center"><tr>
+<td align="left"><input type="button" onclick="showTop()" onmouseover="window.status='goto top of page'; return true;" onmouseout="window.status=''" value="back to top"></td>
+<td align="right"><input type="button" onclick="window.print()" onmouseover="window.status='print page'; return true;" onmouseout="window.status=''" value="print page"></td>
+</tr></table></span></form>
+</body>
+</html>
diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/pinlegendV.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/pinlegendV.htm
new file mode 100644
index 0000000..577547a
--- /dev/null
+++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/pinlegendV.htm
@@ -0,0 +1,150 @@
+<html>
+<head>
+<meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+<link rel="stylesheet" type="text/css" href="style.css">
+<script>
+      function showTop() { document.location.href = '#'; }
+    </script>
+</head>
+<body class="pgBgnd">
+<span id="legend" class="pgRef"><h3 align="center">Legends</h3>
+<table align="center" width="90%" border="0" cellpadding="0" cellspacing="0"><tr><td align="right"><form><input type="button" onclick="javascript:document.location.href='pinlegend.htm'" value="brief"></form></td></tr></table>
+<table align="center" width="90%" border="1" cellpadding="0" cellspacing="0">
+<tr>
+<th width="20%">Acronym</th>
+<th width="80%">Verbose Description</th>
+</tr>
+<tr>
+<td width="20%"> CLK</td>
+<td width="60%"> Global Clock</td>
+</tr>
+<tr>
+<td width="20%"> GCK0</td>
+<td width="60%"> Global clock zero</td>
+</tr>
+<tr>
+<td width="20%"> GCK1</td>
+<td width="60%"> Global clock one</td>
+</tr>
+<tr>
+<td width="20%"> GCK2</td>
+<td width="60%"> Global clock two</td>
+</tr>
+<tr>
+<td width="20%"> GND</td>
+<td width="60%"> Dedicated Ground Pin</td>
+</tr>
+<tr>
+<td width="20%"> GSR</td>
+<td width="60%"> Global set-reset</td>
+</tr>
+<tr>
+<td width="20%"> GTS0</td>
+<td width="60%"> Global tristate zero (output enable)</td>
+</tr>
+<tr>
+<td width="20%"> GTS1</td>
+<td width="60%"> Global tristate one (output enable)</td>
+</tr>
+<tr>
+<td width="20%"> GTS2</td>
+<td width="60%"> Global tristate two (output enable)</td>
+</tr>
+<tr>
+<td width="20%"> GTS3</td>
+<td width="60%"> Global tristate three (output enable)</td>
+</tr>
+<tr>
+<td width="20%"> I/O</td>
+<td width="60%"> Input/Output</td>
+</tr>
+<tr>
+<td width="20%"> INIT</td>
+<td width="60%"> Initial state</td>
+</tr>
+<tr>
+<td width="20%"> ISP</td>
+<td width="60%"> The use of the JTAG port to program the chip while it is powered in a system.</td>
+</tr>
+<tr>
+<td width="20%"> JTAG</td>
+<td width="60%"> IEEE Standard 1149 (JTAG) boundary-scan test standard.</td>
+</tr>
+<tr>
+<td width="20%"> KPR</td>
+<td width="60%"> Unused I/O with weak keeper (leave unconnected)</td>
+</tr>
+<tr>
+<td width="20%"> NC</td>
+<td width="60%"> Not Connected, unbonded pin</td>
+</tr>
+<tr>
+<td width="20%"> PGND</td>
+<td width="60%"> Programmable ground pin</td>
+</tr>
+<tr>
+<td width="20%"> PROHIBITED</td>
+<td width="60%"> User reserved pin</td>
+</tr>
+<tr>
+<td width="20%"> R</td>
+<td width="60%"> Reset</td>
+</tr>
+<tr>
+<td width="20%"> S</td>
+<td width="60%"> Set</td>
+</tr>
+<tr>
+<td width="20%"> TCK</td>
+<td width="60%"> One of four terminals required by (JTAG) IEEE Std 1149 or IEEE Std 1532.  Test operations of the device are synchronous to TCK.  Data is captured on the rising edge of TCK and outputs change on the falling edge of TCK.  An internal pull-up forces TCK to a high level if left unconnected.</td>
+</tr>
+<tr>
+<td width="20%"> TDI</td>
+<td width="60%"> One of four terminals required by (JTAG) IEEE Std 1149 or IEEE Std 1532. It is the serial input for shifting data through the instruction register or selected data register.  An internal pull-up forces TDI to a high level if left unconnected.</td>
+</tr>
+<tr>
+<td width="20%"> TDO</td>
+<td width="60%"> One of four terminals required by (JTAG) IEEE Std 1149 or IEEE Std 1532. It is the serial output for shifting data through the instruction register or selected data register.  An internal pull-up forces TDI to a high level when it is not driven from an external source.</td>
+</tr>
+<tr>
+<td width="20%"> TIE</td>
+<td width="60%"> Unused I/O floating -- must tie to VCC, GND or other signal</td>
+</tr>
+<tr>
+<td width="20%"> TMS</td>
+<td width="60%"> One of four terminals required by (JTAG) IEEE Std 1149 or IEEE Std 1532. It directs the device through its Test Access Port controller states.  An internal pull-up forces TDI to a high level when it is not driven from an external source.  TMS also provides the optional test reset signal of IEEE Std 1149 or IEEE Std 1532.</td>
+</tr>
+<tr>
+<td width="20%"> LVCMOS</td>
+<td width="60%"> Low Voltage Complementary Metal Oxide Semiconductor 3.3 Volts</td>
+</tr>
+<tr>
+<td width="20%"> LVCMOS25</td>
+<td width="60%"> External I/O supply voltage for LVCMOS25</td>
+</tr>
+<tr>
+<td width="20%"> LVCMOS33</td>
+<td width="60%"> External I/O supply voltage for LVCMOS33</td>
+</tr>
+<tr>
+<td width="20%"> LVTTL</td>
+<td width="60%"> Low Voltage Transistor Transistor Logic 3.3Volts</td>
+</tr>
+<tr>
+<td width="20%"> VCCIO</td>
+<td width="60%"> External power for Inputs/Outputs</td>
+</tr>
+<tr>
+<td width="20%"> VCC</td>
+<td width="60%"> Dedicated Power Pin, Internal supply voltage for the device</td>
+</tr>
+<tr>
+<td width="20%"> WPU</td>
+<td width="60%"> Unused I/O with Internal Weak Pull Up (leave unconnected)</td>
+</tr>
+</table></span><form><span class="pgRef"><table width="90%" align="center"><tr>
+<td align="left"><input type="button" onclick="showTop()" onmouseover="window.status='goto top of page'; return true;" onmouseout="window.status=''" value="back to top"></td>
+<td align="right"><input type="button" onclick="window.print()" onmouseover="window.status='print page'; return true;" onmouseout="window.status=''" value="print page"></td>
+</tr></table></span></form>
+</body>
+</html>
diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/pins.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/pins.htm
new file mode 100644
index 0000000..503aaa4
--- /dev/null
+++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/pins.htm
@@ -0,0 +1,741 @@
+<html>
+<head>
+<meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+<script src="pins.js"></script><link rel="stylesheet" type="text/css" href="style.css">
+</head>
+<body class="pgBgnd" id="XC95144XL">
+<span id="pin" class="pgRef"><table align="center" width="90%" border="0" cellpadding="0" cellspacing="0"><tr><td align="center" vlaign="bottom" width="90%"><h3>Pin List</h3></td></tr></table>
+<table align="center" width="90%" border="1" cellpadding="0" cellspacing="1">
+<tr>
+<th width="10%">Pin Num</th>
+<td width="20%" align="center">Pin Type</td>
+<th width="70%">Assigned Signal</th>
+</tr>
+<tr>
+<td width="10%" align="center">1</td>
+<td width="20%" align="center">VCCIO</td>
+<td width="70%" align="center">VCC</td>
+</tr>
+<tr>
+<td width="10%" align="center">2</td>
+<td width="20%" align="center">I/O/GTS3</td>
+<td width="70%" align="center"><a href="javascript:showEqn('D0_SPECSIG')" onmouseover="window.status='Show Equation'; return true;" onmouseout="window.status=''">D&lt;0&gt;</a></td>
+</tr>
+<tr>
+<td width="10%" align="center">3</td>
+<td width="20%" align="center">I/O/GTS4</td>
+<td width="70%" align="center">KPR</td>
+</tr>
+<tr>
+<td width="10%" align="center">4</td>
+<td width="20%" align="center">I/O</td>
+<td width="70%" align="center">KPR</td>
+</tr>
+<tr>
+<td width="10%" align="center">5</td>
+<td width="20%" align="center">I/O/GTS1</td>
+<td width="70%" align="center">KPR</td>
+</tr>
+<tr>
+<td width="10%" align="center">6</td>
+<td width="20%" align="center">I/O/GTS2</td>
+<td width="70%" align="center">KPR</td>
+</tr>
+<tr>
+<td width="10%" align="center">7</td>
+<td width="20%" align="center">I/O</td>
+<td width="70%" align="center">KPR</td>
+</tr>
+<tr>
+<td width="10%" align="center">8</td>
+<td width="20%" align="center">VCCINT</td>
+<td width="70%" align="center">VCC</td>
+</tr>
+<tr>
+<td width="10%" align="center">9</td>
+<td width="20%" align="center">I/O</td>
+<td width="70%" align="center">KPR</td>
+</tr>
+<tr>
+<td width="10%" align="center">10</td>
+<td width="20%" align="center">I/O</td>
+<td width="70%" align="center">KPR</td>
+</tr>
+<tr>
+<td width="10%" align="center">11</td>
+<td width="20%" align="center">I/O</td>
+<td width="70%" align="center">KPR</td>
+</tr>
+<tr>
+<td width="10%" align="center">12</td>
+<td width="20%" align="center">I/O</td>
+<td width="70%" align="center">KPR</td>
+</tr>
+<tr>
+<td width="10%" align="center">13</td>
+<td width="20%" align="center">I/O</td>
+<td width="70%" align="center">KPR</td>
+</tr>
+<tr>
+<td width="10%" align="center">14</td>
+<td width="20%" align="center">I/O</td>
+<td width="70%" align="center"><a href="javascript:showEqn('D6_SPECSIG')" onmouseover="window.status='Show Equation'; return true;" onmouseout="window.status=''">D&lt;6&gt;</a></td>
+</tr>
+<tr>
+<td width="10%" align="center">15</td>
+<td width="20%" align="center">I/O</td>
+<td width="70%" align="center"><a href="javascript:showEqn('D3_SPECSIG')" onmouseover="window.status='Show Equation'; return true;" onmouseout="window.status=''">D&lt;3&gt;</a></td>
+</tr>
+<tr>
+<td width="10%" align="center">16</td>
+<td width="20%" align="center">I/O</td>
+<td width="70%" align="center"><a href="javascript:showEqn('D7_SPECSIG')" onmouseover="window.status='Show Equation'; return true;" onmouseout="window.status=''">D&lt;7&gt;</a></td>
+</tr>
+<tr>
+<td width="10%" align="center">17</td>
+<td width="20%" align="center">I/O</td>
+<td width="70%" align="center"><a href="javascript:showEqn('D1_SPECSIG')" onmouseover="window.status='Show Equation'; return true;" onmouseout="window.status=''">D&lt;1&gt;</a></td>
+</tr>
+<tr>
+<td width="10%" align="center">18</td>
+<td width="20%" align="center">GND</td>
+<td width="70%" align="center">GND</td>
+</tr>
+<tr>
+<td width="10%" align="center">19</td>
+<td width="20%" align="center">I/O</td>
+<td width="70%" align="center"><a href="javascript:showEqn('D8_SPECSIG')" onmouseover="window.status='Show Equation'; return true;" onmouseout="window.status=''">D&lt;8&gt;</a></td>
+</tr>
+<tr>
+<td width="10%" align="center">20</td>
+<td width="20%" align="center">I/O</td>
+<td width="70%" align="center"><a href="javascript:showEqn('D5_SPECSIG')" onmouseover="window.status='Show Equation'; return true;" onmouseout="window.status=''">D&lt;5&gt;</a></td>
+</tr>
+<tr>
+<td width="10%" align="center">21</td>
+<td width="20%" align="center">I/O</td>
+<td width="70%" align="center"><a href="javascript:showEqn('D4_SPECSIG')" onmouseover="window.status='Show Equation'; return true;" onmouseout="window.status=''">D&lt;4&gt;</a></td>
+</tr>
+<tr>
+<td width="10%" align="center">22</td>
+<td width="20%" align="center">I/O</td>
+<td width="70%" align="center"><a href="javascript:showEqn('IDE_CS0_SPECSIG')" onmouseover="window.status='Show Equation'; return true;" onmouseout="window.status=''">IDE_CS&lt;0&gt;</a></td>
+</tr>
+<tr>
+<td width="10%" align="center">23</td>
+<td width="20%" align="center">I/O</td>
+<td width="70%" align="center"><a href="javascript:showEqn('IDE_CS1_SPECSIG')" onmouseover="window.status='Show Equation'; return true;" onmouseout="window.status=''">IDE_CS&lt;1&gt;</a></td>
+</tr>
+<tr>
+<td width="10%" align="center">24</td>
+<td width="20%" align="center">I/O</td>
+<td width="70%" align="center"><a href="javascript:showEqn('IDE_A0_SPECSIG')" onmouseover="window.status='Show Equation'; return true;" onmouseout="window.status=''">IDE_A&lt;0&gt;</a></td>
+</tr>
+<tr>
+<td width="10%" align="center">25</td>
+<td width="20%" align="center">I/O</td>
+<td width="70%" align="center"><a href="javascript:showEqn('IDE_A2_SPECSIG')" onmouseover="window.status='Show Equation'; return true;" onmouseout="window.status=''">IDE_A&lt;2&gt;</a></td>
+</tr>
+<tr>
+<td width="10%" align="center">26</td>
+<td width="20%" align="center">I/O</td>
+<td width="70%" align="center"><a href="javascript:showEqn('IDE_A1_SPECSIG')" onmouseover="window.status='Show Equation'; return true;" onmouseout="window.status=''">IDE_A&lt;1&gt;</a></td>
+</tr>
+<tr>
+<td width="10%" align="center">27</td>
+<td width="20%" align="center">I/O</td>
+<td width="70%" align="center"><a href="javascript:showEqn('IDE_R')" onmouseover="window.status='Show Equation'; return true;" onmouseout="window.status=''">IDE_R</a></td>
+</tr>
+<tr>
+<td width="10%" align="center">28</td>
+<td width="20%" align="center">I/O</td>
+<td width="70%" align="center"><a href="javascript:showEqn('IDE_W')" onmouseover="window.status='Show Equation'; return true;" onmouseout="window.status=''">IDE_W</a></td>
+</tr>
+<tr>
+<td width="10%" align="center">29</td>
+<td width="20%" align="center">GND</td>
+<td width="70%" align="center">GND</td>
+</tr>
+<tr>
+<td width="10%" align="center">30</td>
+<td width="20%" align="center">I/O/GCK1</td>
+<td width="70%" align="center">KPR</td>
+</tr>
+<tr>
+<td width="10%" align="center">31</td>
+<td width="20%" align="center">I/O</td>
+<td width="70%" align="center">KPR</td>
+</tr>
+<tr>
+<td width="10%" align="center">32</td>
+<td width="20%" align="center">I/O/GCK2</td>
+<td width="70%" align="center">KPR</td>
+</tr>
+<tr>
+<td width="10%" align="center">33</td>
+<td width="20%" align="center">I/O</td>
+<td width="70%" align="center">KPR</td>
+</tr>
+<tr>
+<td width="10%" align="center">34</td>
+<td width="20%" align="center">I/O</td>
+<td width="70%" align="center">KPR</td>
+</tr>
+<tr>
+<td width="10%" align="center">35</td>
+<td width="20%" align="center">I/O</td>
+<td width="70%" align="center"><a href="javascript:showEqn('ROM_OE')" onmouseover="window.status='Show Equation'; return true;" onmouseout="window.status=''">ROM_OE</a></td>
+</tr>
+<tr>
+<td width="10%" align="center">36</td>
+<td width="20%" align="center">GND</td>
+<td width="70%" align="center">GND</td>
+</tr>
+<tr>
+<td width="10%" align="center">37</td>
+<td width="20%" align="center">VCCIO</td>
+<td width="70%" align="center">VCC</td>
+</tr>
+<tr>
+<td width="10%" align="center">38</td>
+<td width="20%" align="center">I/O/GCK3</td>
+<td width="70%" align="center">KPR</td>
+</tr>
+<tr>
+<td width="10%" align="center">39</td>
+<td width="20%" align="center">I/O</td>
+<td width="70%" align="center"><a href="javascript:showEqn('D2_SPECSIG')" onmouseover="window.status='Show Equation'; return true;" onmouseout="window.status=''">D&lt;2&gt;</a></td>
+</tr>
+<tr>
+<td width="10%" align="center">40</td>
+<td width="20%" align="center">I/O</td>
+<td width="70%" align="center"><a href="javascript:showEqn('D9_SPECSIG')" onmouseover="window.status='Show Equation'; return true;" onmouseout="window.status=''">D&lt;9&gt;</a></td>
+</tr>
+<tr>
+<td width="10%" align="center">41</td>
+<td width="20%" align="center">I/O</td>
+<td width="70%" align="center"><a href="javascript:showEqn('D10_SPECSIG')" onmouseover="window.status='Show Equation'; return true;" onmouseout="window.status=''">D&lt;10&gt;</a></td>
+</tr>
+<tr>
+<td width="10%" align="center">42</td>
+<td width="20%" align="center">VCCINT</td>
+<td width="70%" align="center">VCC</td>
+</tr>
+<tr>
+<td width="10%" align="center">43</td>
+<td width="20%" align="center">I/O</td>
+<td width="70%" align="center"><a href="javascript:showEqn('D11_SPECSIG')" onmouseover="window.status='Show Equation'; return true;" onmouseout="window.status=''">D&lt;11&gt;</a></td>
+</tr>
+<tr>
+<td width="10%" align="center">44</td>
+<td width="20%" align="center">I/O</td>
+<td width="70%" align="center"><a href="javascript:showEqn('D12_SPECSIG')" onmouseover="window.status='Show Equation'; return true;" onmouseout="window.status=''">D&lt;12&gt;</a></td>
+</tr>
+<tr>
+<td width="10%" align="center">45</td>
+<td width="20%" align="center">I/O</td>
+<td width="70%" align="center"><a href="javascript:showEqn('D13_SPECSIG')" onmouseover="window.status='Show Equation'; return true;" onmouseout="window.status=''">D&lt;13&gt;</a></td>
+</tr>
+<tr>
+<td width="10%" align="center">46</td>
+<td width="20%" align="center">I/O</td>
+<td width="70%" align="center"><a href="javascript:showEqn('D14_SPECSIG')" onmouseover="window.status='Show Equation'; return true;" onmouseout="window.status=''">D&lt;14&gt;</a></td>
+</tr>
+<tr>
+<td width="10%" align="center">47</td>
+<td width="20%" align="center">GND</td>
+<td width="70%" align="center">GND</td>
+</tr>
+<tr>
+<td width="10%" align="center">48</td>
+<td width="20%" align="center">I/O</td>
+<td width="70%" align="center"><a href="javascript:showEqn('D15_SPECSIG')" onmouseover="window.status='Show Equation'; return true;" onmouseout="window.status=''">D&lt;15&gt;</a></td>
+</tr>
+<tr>
+<td width="10%" align="center">49</td>
+<td width="20%" align="center">I/O</td>
+<td width="70%" align="center">A&lt;5&gt;</td>
+</tr>
+<tr>
+<td width="10%" align="center">50</td>
+<td width="20%" align="center">I/O</td>
+<td width="70%" align="center">A&lt;4&gt;</td>
+</tr>
+<tr>
+<td width="10%" align="center">51</td>
+<td width="20%" align="center">I/O</td>
+<td width="70%" align="center">A&lt;6&gt;</td>
+</tr>
+<tr>
+<td width="10%" align="center">52</td>
+<td width="20%" align="center">I/O</td>
+<td width="70%" align="center">A&lt;3&gt;</td>
+</tr>
+<tr>
+<td width="10%" align="center">53</td>
+<td width="20%" align="center">I/O</td>
+<td width="70%" align="center">KPR</td>
+</tr>
+<tr>
+<td width="10%" align="center">54</td>
+<td width="20%" align="center">I/O</td>
+<td width="70%" align="center">A&lt;2&gt;</td>
+</tr>
+<tr>
+<td width="10%" align="center">55</td>
+<td width="20%" align="center">VCCIO</td>
+<td width="70%" align="center">VCC</td>
+</tr>
+<tr>
+<td width="10%" align="center">56</td>
+<td width="20%" align="center">I/O</td>
+<td width="70%" align="center">KPR</td>
+</tr>
+<tr>
+<td width="10%" align="center">57</td>
+<td width="20%" align="center">I/O</td>
+<td width="70%" align="center">A&lt;1&gt;</td>
+</tr>
+<tr>
+<td width="10%" align="center">58</td>
+<td width="20%" align="center">I/O</td>
+<td width="70%" align="center">A&lt;9&gt;</td>
+</tr>
+<tr>
+<td width="10%" align="center">59</td>
+<td width="20%" align="center">I/O</td>
+<td width="70%" align="center">A&lt;10&gt;</td>
+</tr>
+<tr>
+<td width="10%" align="center">60</td>
+<td width="20%" align="center">I/O</td>
+<td width="70%" align="center">A&lt;11&gt;</td>
+</tr>
+<tr>
+<td width="10%" align="center">61</td>
+<td width="20%" align="center">I/O</td>
+<td width="70%" align="center">A&lt;12&gt;</td>
+</tr>
+<tr>
+<td width="10%" align="center">62</td>
+<td width="20%" align="center">GND</td>
+<td width="70%" align="center">GND</td>
+</tr>
+<tr>
+<td width="10%" align="center">63</td>
+<td width="20%" align="center">TDI</td>
+<td width="70%" align="center">TDI</td>
+</tr>
+<tr>
+<td width="10%" align="center">64</td>
+<td width="20%" align="center">I/O</td>
+<td width="70%" align="center">A&lt;13&gt;</td>
+</tr>
+<tr>
+<td width="10%" align="center">65</td>
+<td width="20%" align="center">TMS</td>
+<td width="70%" align="center">TMS</td>
+</tr>
+<tr>
+<td width="10%" align="center">66</td>
+<td width="20%" align="center">I/O</td>
+<td width="70%" align="center">KPR</td>
+</tr>
+<tr>
+<td width="10%" align="center">67</td>
+<td width="20%" align="center">TCK</td>
+<td width="70%" align="center">TCK</td>
+</tr>
+<tr>
+<td width="10%" align="center">68</td>
+<td width="20%" align="center">I/O</td>
+<td width="70%" align="center"><a href="javascript:showEqn('ROM_B0_SPECSIG')" onmouseover="window.status='Show Equation'; return true;" onmouseout="window.status=''">ROM_B&lt;0&gt;</a></td>
+</tr>
+<tr>
+<td width="10%" align="center">69</td>
+<td width="20%" align="center">I/O</td>
+<td width="70%" align="center"><a href="javascript:showEqn('ROM_B1_SPECSIG')" onmouseover="window.status='Show Equation'; return true;" onmouseout="window.status=''">ROM_B&lt;1&gt;</a></td>
+</tr>
+<tr>
+<td width="10%" align="center">70</td>
+<td width="20%" align="center">I/O</td>
+<td width="70%" align="center">KPR</td>
+</tr>
+<tr>
+<td width="10%" align="center">71</td>
+<td width="20%" align="center">I/O</td>
+<td width="70%" align="center">KPR</td>
+</tr>
+<tr>
+<td width="10%" align="center">72</td>
+<td width="20%" align="center">GND</td>
+<td width="70%" align="center">GND</td>
+</tr>
+<tr>
+<td width="10%" align="center">73</td>
+<td width="20%" align="center">VCCIO</td>
+<td width="70%" align="center">VCC</td>
+</tr>
+<tr>
+<td width="10%" align="center">74</td>
+<td width="20%" align="center">I/O</td>
+<td width="70%" align="center">KPR</td>
+</tr>
+<tr>
+<td width="10%" align="center">75</td>
+<td width="20%" align="center">I/O</td>
+<td width="70%" align="center">AUTOBOOT_OFF</td>
+</tr>
+<tr>
+<td width="10%" align="center">76</td>
+<td width="20%" align="center">I/O</td>
+<td width="70%" align="center">KPR</td>
+</tr>
+<tr>
+<td width="10%" align="center">77</td>
+<td width="20%" align="center">I/O</td>
+<td width="70%" align="center">KPR</td>
+</tr>
+<tr>
+<td width="10%" align="center">78</td>
+<td width="20%" align="center">I/O</td>
+<td width="70%" align="center">KPR</td>
+</tr>
+<tr>
+<td width="10%" align="center">79</td>
+<td width="20%" align="center">I/O</td>
+<td width="70%" align="center">KPR</td>
+</tr>
+<tr>
+<td width="10%" align="center">80</td>
+<td width="20%" align="center">I/O</td>
+<td width="70%" align="center">AS</td>
+</tr>
+<tr>
+<td width="10%" align="center">81</td>
+<td width="20%" align="center">I/O</td>
+<td width="70%" align="center">UDS</td>
+</tr>
+<tr>
+<td width="10%" align="center">82</td>
+<td width="20%" align="center">I/O</td>
+<td width="70%" align="center">KPR</td>
+</tr>
+<tr>
+<td width="10%" align="center">83</td>
+<td width="20%" align="center">I/O</td>
+<td width="70%" align="center">RW</td>
+</tr>
+<tr>
+<td width="10%" align="center">84</td>
+<td width="20%" align="center">VCCINT</td>
+<td width="70%" align="center">VCC</td>
+</tr>
+<tr>
+<td width="10%" align="center">85</td>
+<td width="20%" align="center">I/O</td>
+<td width="70%" align="center"><a href="javascript:showEqn('DTACK')" onmouseover="window.status='Show Equation'; return true;" onmouseout="window.status=''">DTACK</a></td>
+</tr>
+<tr>
+<td width="10%" align="center">86</td>
+<td width="20%" align="center">I/O</td>
+<td width="70%" align="center">A&lt;23&gt;</td>
+</tr>
+<tr>
+<td width="10%" align="center">87</td>
+<td width="20%" align="center">I/O</td>
+<td width="70%" align="center">A&lt;22&gt;</td>
+</tr>
+<tr>
+<td width="10%" align="center">88</td>
+<td width="20%" align="center">I/O</td>
+<td width="70%" align="center">A&lt;21&gt;</td>
+</tr>
+<tr>
+<td width="10%" align="center">89</td>
+<td width="20%" align="center">GND</td>
+<td width="70%" align="center">GND</td>
+</tr>
+<tr>
+<td width="10%" align="center">90</td>
+<td width="20%" align="center">GND</td>
+<td width="70%" align="center">GND</td>
+</tr>
+<tr>
+<td width="10%" align="center">91</td>
+<td width="20%" align="center">I/O</td>
+<td width="70%" align="center">A&lt;20&gt;</td>
+</tr>
+<tr>
+<td width="10%" align="center">92</td>
+<td width="20%" align="center">I/O</td>
+<td width="70%" align="center">A&lt;19&gt;</td>
+</tr>
+<tr>
+<td width="10%" align="center">93</td>
+<td width="20%" align="center">I/O</td>
+<td width="70%" align="center">KPR</td>
+</tr>
+<tr>
+<td width="10%" align="center">94</td>
+<td width="20%" align="center">I/O</td>
+<td width="70%" align="center">A&lt;18&gt;</td>
+</tr>
+<tr>
+<td width="10%" align="center">95</td>
+<td width="20%" align="center">I/O</td>
+<td width="70%" align="center">A&lt;17&gt;</td>
+</tr>
+<tr>
+<td width="10%" align="center">96</td>
+<td width="20%" align="center">I/O</td>
+<td width="70%" align="center">KPR</td>
+</tr>
+<tr>
+<td width="10%" align="center">97</td>
+<td width="20%" align="center">I/O</td>
+<td width="70%" align="center">A&lt;16&gt;</td>
+</tr>
+<tr>
+<td width="10%" align="center">98</td>
+<td width="20%" align="center">I/O</td>
+<td width="70%" align="center">BERR</td>
+</tr>
+<tr>
+<td width="10%" align="center">99</td>
+<td width="20%" align="center">GND</td>
+<td width="70%" align="center">GND</td>
+</tr>
+<tr>
+<td width="10%" align="center">100</td>
+<td width="20%" align="center">I/O</td>
+<td width="70%" align="center">KPR</td>
+</tr>
+<tr>
+<td width="10%" align="center">101</td>
+<td width="20%" align="center">I/O</td>
+<td width="70%" align="center">KPR</td>
+</tr>
+<tr>
+<td width="10%" align="center">102</td>
+<td width="20%" align="center">I/O</td>
+<td width="70%" align="center">C3</td>
+</tr>
+<tr>
+<td width="10%" align="center">103</td>
+<td width="20%" align="center">I/O</td>
+<td width="70%" align="center">C1</td>
+</tr>
+<tr>
+<td width="10%" align="center">104</td>
+<td width="20%" align="center">I/O</td>
+<td width="70%" align="center">KPR</td>
+</tr>
+<tr>
+<td width="10%" align="center">105</td>
+<td width="20%" align="center">I/O</td>
+<td width="70%" align="center">KPR</td>
+</tr>
+<tr>
+<td width="10%" align="center">106</td>
+<td width="20%" align="center">I/O</td>
+<td width="70%" align="center">KPR</td>
+</tr>
+<tr>
+<td width="10%" align="center">107</td>
+<td width="20%" align="center">I/O</td>
+<td width="70%" align="center">KPR</td>
+</tr>
+<tr>
+<td width="10%" align="center">108</td>
+<td width="20%" align="center">GND</td>
+<td width="70%" align="center">GND</td>
+</tr>
+<tr>
+<td width="10%" align="center">109</td>
+<td width="20%" align="center">VCCIO</td>
+<td width="70%" align="center">VCC</td>
+</tr>
+<tr>
+<td width="10%" align="center">110</td>
+<td width="20%" align="center">I/O</td>
+<td width="70%" align="center">KPR</td>
+</tr>
+<tr>
+<td width="10%" align="center">111</td>
+<td width="20%" align="center">I/O</td>
+<td width="70%" align="center">KPR</td>
+</tr>
+<tr>
+<td width="10%" align="center">112</td>
+<td width="20%" align="center">I/O</td>
+<td width="70%" align="center">KPR</td>
+</tr>
+<tr>
+<td width="10%" align="center">113</td>
+<td width="20%" align="center">I/O</td>
+<td width="70%" align="center">KPR</td>
+</tr>
+<tr>
+<td width="10%" align="center">114</td>
+<td width="20%" align="center">GND</td>
+<td width="70%" align="center">GND</td>
+</tr>
+<tr>
+<td width="10%" align="center">115</td>
+<td width="20%" align="center">I/O</td>
+<td width="70%" align="center">KPR</td>
+</tr>
+<tr>
+<td width="10%" align="center">116</td>
+<td width="20%" align="center">I/O</td>
+<td width="70%" align="center">KPR</td>
+</tr>
+<tr>
+<td width="10%" align="center">117</td>
+<td width="20%" align="center">I/O</td>
+<td width="70%" align="center">KPR</td>
+</tr>
+<tr>
+<td width="10%" align="center">118</td>
+<td width="20%" align="center">I/O</td>
+<td width="70%" align="center">KPR</td>
+</tr>
+<tr>
+<td width="10%" align="center">119</td>
+<td width="20%" align="center">I/O</td>
+<td width="70%" align="center">KPR</td>
+</tr>
+<tr>
+<td width="10%" align="center">120</td>
+<td width="20%" align="center">I/O</td>
+<td width="70%" align="center">KPR</td>
+</tr>
+<tr>
+<td width="10%" align="center">121</td>
+<td width="20%" align="center">I/O</td>
+<td width="70%" align="center">KPR</td>
+</tr>
+<tr>
+<td width="10%" align="center">122</td>
+<td width="20%" align="center">TDO</td>
+<td width="70%" align="center">TDO</td>
+</tr>
+<tr>
+<td width="10%" align="center">123</td>
+<td width="20%" align="center">GND</td>
+<td width="70%" align="center">GND</td>
+</tr>
+<tr>
+<td width="10%" align="center">124</td>
+<td width="20%" align="center">I/O</td>
+<td width="70%" align="center">KPR</td>
+</tr>
+<tr>
+<td width="10%" align="center">125</td>
+<td width="20%" align="center">I/O</td>
+<td width="70%" align="center">KPR</td>
+</tr>
+<tr>
+<td width="10%" align="center">126</td>
+<td width="20%" align="center">I/O</td>
+<td width="70%" align="center">KPR</td>
+</tr>
+<tr>
+<td width="10%" align="center">127</td>
+<td width="20%" align="center">VCCIO</td>
+<td width="70%" align="center">VCC</td>
+</tr>
+<tr>
+<td width="10%" align="center">128</td>
+<td width="20%" align="center">I/O</td>
+<td width="70%" align="center">KPR</td>
+</tr>
+<tr>
+<td width="10%" align="center">129</td>
+<td width="20%" align="center">I/O</td>
+<td width="70%" align="center">KPR</td>
+</tr>
+<tr>
+<td width="10%" align="center">130</td>
+<td width="20%" align="center">I/O</td>
+<td width="70%" align="center">KPR</td>
+</tr>
+<tr>
+<td width="10%" align="center">131</td>
+<td width="20%" align="center">I/O</td>
+<td width="70%" align="center">KPR</td>
+</tr>
+<tr>
+<td width="10%" align="center">132</td>
+<td width="20%" align="center">I/O</td>
+<td width="70%" align="center">KPR</td>
+</tr>
+<tr>
+<td width="10%" align="center">133</td>
+<td width="20%" align="center">I/O</td>
+<td width="70%" align="center">KPR</td>
+</tr>
+<tr>
+<td width="10%" align="center">134</td>
+<td width="20%" align="center">I/O</td>
+<td width="70%" align="center">KPR</td>
+</tr>
+<tr>
+<td width="10%" align="center">135</td>
+<td width="20%" align="center">I/O</td>
+<td width="70%" align="center">KPR</td>
+</tr>
+<tr>
+<td width="10%" align="center">136</td>
+<td width="20%" align="center">I/O</td>
+<td width="70%" align="center">KPR</td>
+</tr>
+<tr>
+<td width="10%" align="center">137</td>
+<td width="20%" align="center">I/O</td>
+<td width="70%" align="center">KPR</td>
+</tr>
+<tr>
+<td width="10%" align="center">138</td>
+<td width="20%" align="center">I/O</td>
+<td width="70%" align="center">KPR</td>
+</tr>
+<tr>
+<td width="10%" align="center">139</td>
+<td width="20%" align="center">I/O</td>
+<td width="70%" align="center">KPR</td>
+</tr>
+<tr>
+<td width="10%" align="center">140</td>
+<td width="20%" align="center">I/O</td>
+<td width="70%" align="center">KPR</td>
+</tr>
+<tr>
+<td width="10%" align="center">141</td>
+<td width="20%" align="center">VCCINT</td>
+<td width="70%" align="center">VCC</td>
+</tr>
+<tr>
+<td width="10%" align="center">142</td>
+<td width="20%" align="center">I/O</td>
+<td width="70%" align="center">KPR</td>
+</tr>
+<tr>
+<td width="10%" align="center">143</td>
+<td width="20%" align="center">I/O/GSR</td>
+<td width="70%" align="center">RESET</td>
+</tr>
+<tr>
+<td width="10%" align="center">144</td>
+<td width="20%" align="center">GND</td>
+<td width="70%" align="center">GND</td>
+</tr>
+</table></span><form><span class="pgRef"><table width="90%" align="center"><tr>
+<td align="left"><input type="button" onclick="javascript:parent.leftnav.showTop()" onmouseover="window.status='goto top of page'; return true;" onmouseout="window.status=''" value="back to top"></td>
+<td align="right">
+<input type="button" onclick="javascript:showLegend('pinlegend.htm')" onmouseover="window.status='show Legend'; return true;" onmouseout="window.status=''" value="legend"><input type="button" onclick="window.print()" onmouseover="window.status='print page'; return true;" onmouseout="window.status=''" value="print page">
+</td>
+</tr></table></span></form>
+</body>
+</html>
diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/pins.js b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/pins.js
new file mode 100644
index 0000000..591e563
--- /dev/null
+++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/pins.js
@@ -0,0 +1,62 @@
+var specSig = new Array();
+var pins = new Array();
+var pinsAssign = new Array();
+var prohibit = new Array();
+var unusedStr = "WPU";
+var gndStr = "GND";
+var vccStr = "VCC";
+var tdiStr = "TDI";
+var tdoStr = "TDO";
+var tmsStr = "TMS";
+var tckStr = "TCK";
+
+function showPin(pin) { parent.leftnav.showAppletPin(pin); }
+
+function printPage() { window.print();  parent.leftnav.printAppletPkg(); }
+
+function showEqn(signal) { parent.leftnav.showEqn(signal); }
+
+function updatePin(type) {
+  with (document.options) {
+    switch (type) {
+    case 0:
+      if (inp.checked) parent.leftnav.document.options.inOn.value = 1;
+      else             parent.leftnav.document.options.inOn.value = 0;
+      break;
+
+    case 1:
+      if (out.checked) parent.leftnav.document.options.outOn.value = 1;
+      else             parent.leftnav.document.options.outOn.value = 0;
+      break;
+
+    case 2:
+      if (glb.checked) parent.leftnav.document.options.glbOn.value = 1;
+      else             parent.leftnav.document.options.glbOn.value = 0;
+      break;
+
+    case 3:
+      if (isp.checked) parent.leftnav.document.options.ispOn.value = 1;
+      else             parent.leftnav.document.options.ispOn.value = 0;
+      break;
+
+    case 4:
+      if (vcc.checked) parent.leftnav.document.options.vccOn.value = 1;
+      else             parent.leftnav.document.options.vccOn.value = 0;
+      break;
+
+    case 5:
+      if (gnd.checked) parent.leftnav.document.options.gndOn.value = 1;
+      else             parent.leftnav.document.options.gndOn.value = 0;
+      break;
+
+    case 6:
+      if (unuse.checked) parent.leftnav.document.options.unuseOn.value = 1;
+      else               parent.leftnav.document.options.unuseOn.value = 0;
+      break;
+    }
+  }
+
+  parent.leftnav.showPinOut();
+}
+
+function showLegend(url) { parent.leftnav.showLegend(url, 650, 350); }
diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/pinsdoc.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/pinsdoc.htm
new file mode 100644
index 0000000..9da2708
--- /dev/null
+++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/pinsdoc.htm
@@ -0,0 +1,265 @@
+<!doctype HTML public "-//W3C//DTD HTML 4.0 Frameset//EN">
+
+<html>
+
+<!--(==============================================================)-->
+<!--(Document created with RoboEditor. )============================-->
+<!--(==============================================================)-->
+
+<head>
+
+<title>Pin List</title>
+
+<!--(Meta)==========================================================-->
+
+<meta name=generator content="RoboHELP by eHelp Corporation - www.ehelp.com">
+<meta name=generator-major-version content=0.1>
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+<meta name=filetype-version content=1>
+<meta name=page-count content=1>
+<meta name=layout-height content=1449>
+<meta name=layout-width content=615>
+<meta name=date content="05 24, 2002 6:19:23 PM">
+
+
+
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+
+--></style><script>
+<!--
+if (navigator.appName == "Netscape")
+{
+  var strNSS = "<style>";
+  strNSS += "p.whs3 {margin-left:1; }";
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+  strNSS += "p.whs55 {margin-left:1; }";
+  strNSS +="</style>";
+  document.write(strNSS);
+}
+//-->
+</script><script language="javascript" title="WebHelpInlineScript">
+<!--
+function reDo() {
+  if (innerWidth != origWidth || innerHeight != origHeight)
+     location.reload();
+}
+if ((parseInt(navigator.appVersion) == 4) && (navigator.appName == "Netscape")) {
+	origWidth = innerWidth;
+	origHeight = innerHeight;
+	onresize = reDo;
+}
+//-->
+</script><style>
+<!--
+  div.WebHelpPopupMenu {position:absolute; left:0px; top:0px; z-index:4; visibility:hidden;}
+  p.WebHelpNavBar {text-align:right;}
+-->
+</style>
+</head>
+
+<!--(Body)==========================================================-->
+
+
+<body>
+
+
+<h1>Pin List</h1>
+
+<p class="whs1">The Pin List 
+ page lists each pin of your design with its pin type and associated signal. 
+ <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->Check boxes 
+ at the top of the table allow you to select and deselect which pin types 
+ you want displayed in the table (the default view will display all of 
+ them).</p>
+
+<p class="whs2"><span style="font-weight: bold;"><B>Note:</B></span> 
+ <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->There is 
+ a <SCRIPT LANGUAGE="JavaScript"><!--
+if (navigator.appName=="Netscape")
+{ document.write("<img src='legend.gif' x-maintain-ratio='TRUE' width='68' height='28' border='0'>");}
+else
+{ document.write("<img src='legend.gif' x-maintain-ratio='TRUE' style='border: none; width: 68px; height: 28px; float: none;' width='68' height='28' border='0'>");}
+//--></SCRIPT> button below the table. <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->Click 
+ this button to open a new window describing all of the acronyms used in 
+ the function block table. <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->You 
+ can select either brief descriptions or more detailed descriptions by 
+ clicking the &quot;Verbose&quot; button at the top of the window. </p>
+
+<span style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">Clicking 
+ on the underscored pin numbers in the first column of the table will open 
+ a new window displaying the pin layout diagram for the selected pin. <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->Rolling 
+ your mouse over the colored pin will pop up a tooltip with the signal 
+ name assigned to the pin, the I/O standard, <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->the 
+ I/O style, the slew rate, and/or any constraints assigned to the pin: 
+ </FONT></span>
+
+<p class="whs3"><SCRIPT LANGUAGE="JavaScript"><!--
+if (navigator.appName=="Netscape")
+{ document.write("<img src='pin.gif' x-maintain-ratio='TRUE' width='309' height='312' border='0'>");}
+else
+{ document.write("<img src='pin.gif' x-maintain-ratio='TRUE' style='border: none; width: 309px; height: 312px; float: none;' width='309' height='312' border='0'>");}
+//--></SCRIPT></p>
+
+<p class="whs4">Clicking any underscored signal in the 
+ third column of the table will open a new window displaying the equations 
+ for that particular signal.</p>
+
+<p class="whs5">Clicking on the <SCRIPT LANGUAGE="JavaScript"><!--
+if (navigator.appName=="Netscape")
+{ document.write("<img src='view.gif' x-maintain-ratio='TRUE' width='61' height='53' border='0'>");}
+else
+{ document.write("<img src='view.gif' x-maintain-ratio='TRUE' style='border: none; width: 61px; height: 53px; float: none;' width='61' height='53' border='0'>");}
+//--></SCRIPT>button 
+ at the top of the screen will open a new window with a graphical, top 
+ view of all of the pins: <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}--></p>
+
+<p class="whs6"><SCRIPT LANGUAGE="JavaScript"><!--
+if (navigator.appName=="Netscape")
+{ document.write("<img src='pindiagram.gif' x-maintain-ratio='TRUE' width='312' height='318' border='0'>");}
+else
+{ document.write("<img src='pindiagram.gif' x-maintain-ratio='TRUE' style='border: none; width: 312px; height: 318px; float: none;' width='312' height='318' border='0'>");}
+//--></SCRIPT></p>
+
+<p class="whs7">They are color-coded as follows:</p>
+
+<!--(Table)=========================================================-->
+<table x-use-null-cells width="63.089%" cellspacing="0" class="whs8">
+<col class="whs9">
+<col class="whs10">
+
+<tr valign=top>
+<td colspan="1" rowspan="1" width="43.569%" class="whs11">
+<p class="whs12">Color</td>
+<td colspan="1" rowspan="1" width="56.431%" class="whs13">
+<p class="whs14">Signal</td></tr>
+
+<tr valign=top>
+<td width="43.569%" class="whs15">
+<p class="whs16">Green</td>
+<td width="56.431%" class="whs17">
+<p class="whs18">Input</td></tr>
+
+<tr valign=top>
+<td width="43.569%" class="whs19">
+<p class="whs20">Aqua</td>
+<td width="56.431%" class="whs21">
+<p class="whs22">Bidirectional</td></tr>
+
+<tr valign=top>
+<td width="43.569%" class="whs23">
+<p class="whs24">Blue</td>
+<td width="56.431%" class="whs25">
+<p class="whs26">Output</td></tr>
+
+<tr valign=top>
+<td width="43.569%" class="whs27">
+<p class="whs28">Magenta</td>
+<td width="56.431%" class="whs29">
+<p class="whs30">Clock</td></tr>
+
+<tr valign=top>
+<td width="43.569%" class="whs31">
+<p class="whs32">Red</td>
+<td width="56.431%" class="whs33">
+<p class="whs34">VCC</td></tr>
+
+<tr valign=top>
+<td width="43.569%" class="whs35">
+<p class="whs36">Black</td>
+<td width="56.431%" class="whs37">
+<p class="whs38">GND</td></tr>
+
+<tr valign=top>
+<td width="43.569%" class="whs39">
+<p class="whs40">Yellow</td>
+<td width="56.431%" class="whs41">
+<p class="whs42">TDO</td></tr>
+
+<tr valign=top>
+<td width="43.569%" class="whs43">
+<p class="whs44">Gray</td>
+<td width="56.431%" class="whs45">
+<p class="whs46">TDI</td></tr>
+
+<tr valign=top>
+<td width="43.569%" class="whs47">
+<p class="whs48">White</td>
+<td width="56.431%" class="whs49">
+<p class="whs50">Unused Pin</td></tr>
+
+<tr valign=top>
+<td width="43.569%" class="whs51">
+<p class="whs52">Black Outline</td>
+<td width="56.431%" class="whs53">
+<p class="whs54">No available 
+ Pad</td></tr>
+</table>
+
+<p class="whs55">As with the single pin display, rolling 
+ your mouse over any colored pin will pop up a tooltip with the signal 
+ name assigned to the pin, the I/O standard, <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->the 
+ I/O style, the slew rate, and/or any constraints assigned to the pin.</p>
+
+</body>
+
+</html>
diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/pinview.jpg b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/pinview.jpg
new file mode 100644
index 0000000..c3a27ca
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diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/plugin.js b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/plugin.js
new file mode 100644
index 0000000..cc34368
--- /dev/null
+++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/plugin.js
@@ -0,0 +1,96 @@
+
+function checkJre(){
+
+var agt=navigator.userAgent.toLowerCase();
+var is_major = parseInt(navigator.appVersion);
+
+
+var is_nav = ((agt.indexOf('mozilla')!=-1) && (agt.indexOf('spoofer')== -1)
+&& (agt.indexOf('compatible') == -1) && (agt.indexOf('opera')== -1)
+&& (agt.indexOf('webtv')==-1) && (agt.indexOf('hotjava')== -1));
+var is_nav4up = (is_nav && (is_major >= 4)); 
+
+var is_ie = ((agt.indexOf("msie") != -1) && (agt.indexOf("opera") == -1)); 
+var is_ie5 = (is_ie && (is_major == 4) && (agt.indexOf("msie 5.0")!= -1) );
+var is_ie5_5 = (is_ie && (is_major == 4) && (agt.indexOf("msie 5.5") != -1));
+var is_ie6 = (is_ie && (is_major == 4) && (agt.indexOf("msie 6.0") != -1));
+
+var is_ie5up = (is_ie && (is_major == 4) && ( (agt.indexOf("msie 5.0")!=-1) || (agt.indexOf("msie 5.5")!=-1) || (agt.indexOf("msie 6.0")!=-1) ) );
+
+var pluginDetected = false;
+var activeXDisabled = false;
+
+// we can check for plugin existence only when browser is 'is_ie5up' or 'is_nav4up'
+if(is_nav4up) {
+
+  // Refresh 'navigator.mimeTypes' to get newly installed mimeTypes.
+  // Use 'navigator.mimeTypes.refresh(false)' to refresh mimeTypes 
+  // without refreshing open documents (browser windows)
+
+  // check for Java plugin in installed mimeTypes
+  if(navigator.mimeTypes ) {
+    //window.alert( "length");
+    //window.alert( navigator.mimeTypes.length);
+    for (i=0; i <  navigator.mimeTypes.length; i++) {
+      //window.alert(navigator.mimeTypes[i].type);
+      if( (navigator.mimeTypes[ i].type != null)
+        &&(navigator.mimeTypes[ i].type.indexOf(
+        "application/x-java-applet;jpi-version=1.4") != -1) ) {
+
+        pluginDetected = true; 
+       break;
+      }
+
+    }
+  }
+
+} else if (is_ie5up) {
+  var javaVersion;
+  var shell;
+  try {
+    // Create WSH(WindowsScriptHost) shell, available on Windows only
+    shell = new ActiveXObject("WScript.Shell");
+
+    if (shell != null) {
+    // Read JRE version from Window Registry
+      try {
+        javaVersion = shell.regRead
+        ("HKEY_LOCAL_MACHINE\\Software\\JavaSoft\\Java Runtime Environment\\CurrentVersion");
+      } catch(e) {
+      // handle exceptions raised by 'shell.regRead(...)' here
+      // so that the outer try-catch block would receive only
+      // exceptions raised by 'shell = new ActiveXObject(...)'
+      }
+    } 
+  } catch(e) {
+   window.alert(" Creating ActiveX controls thru script is disabled \n in InternetExplorer security options \n To enable it: \n a. Go to the 'Tools -->; Internet Options' menu\n b. Select the 'Security' tab\n c. Select zone (Internet/Intranet)\n d. Click the 'Custom Level..' button which will display the\n 'Security Settings' window.\n e. Enable the option 'Initialize and script ActiveX controls\n not marked as safe' ");
+
+    activeXDisabled = true;
+  } 
+
+  // Check whether we got required (1.4+) Java Plugin
+  if ( (javaVersion != null) && (javaVersion.indexOf("1.4") != -1) ) {
+    pluginDetected = true;
+  }
+
+}
+
+
+if (pluginDetected) {
+
+  // show applet page
+  document.location.href="newappletref.htm";
+
+} else if (confirm("Java Plugin 1.4+ not found, Do you want to download it?\n" +
+                   "if you choose not to install the plugin  the reports graphical applets will not be available.")) {
+
+  // show install page
+  document.location.href=XilinxD;
+
+} else {
+  // show error page
+  document.location.href="newappletref.htm";
+}
+
+}
+
diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/prev.jpg b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/prev.jpg
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diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/print.jpg b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/print.jpg
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diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/products.gif b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/products.gif
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diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/purchase.gif b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/purchase.gif
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diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/report.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/report.htm
new file mode 100644
index 0000000..70e46e7
--- /dev/null
+++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/report.htm
@@ -0,0 +1,19 @@
+<html>
+  <head>
+    <script>
+      function isNS7() {
+      return ((navigator.appName.indexOf("Netscape") >= 0) && (parseFloat(navigator.appVersion) >= 5) ) ? true : false;
+      }
+
+      function init(){
+        if( isNS7() ){
+          document.location.href="newappletref.htm";
+        }
+        document.location.href="appletref.htm";
+      } 
+    </script
+  </head>
+  <body onload="javascript:init()" bgcolor="#ffffff" topmargin="0" leftmargin="0" marginheight="0" marginwidth="0">
+  </body>
+
+</html>
diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/result.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/result.htm
new file mode 100644
index 0000000..a63a253
--- /dev/null
+++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/result.htm
@@ -0,0 +1,14 @@
+<html>
+<head>
+  <script>
+    function init() {
+      document.open();
+      document.write(window.opener.document.options.htmlStr.value);
+      document.write("<form><center><input type='button' value='close' onclick='window.close()'></center></form>");
+      document.close();
+    }
+  </script>
+</head>
+<body onload="javascript:init()">
+</body>
+</html>
diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/search.gif b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/search.gif
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index 0000000..714dc20
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diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/spacer.gif b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/spacer.gif
new file mode 100644
index 0000000..0eba199
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diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/style.css b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/style.css
new file mode 100644
index 0000000..5f32596
--- /dev/null
+++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/style.css
@@ -0,0 +1,19 @@
+<!-- for TOC -->
+.tocRef A:link {font-family:arial black; font-size:14px;}
+.tocRef A:visited {font-family:arial black; font-size:14px;}
+.tocRef A:active {font-family:arial black; font-size:14px;}
+.tocRef A:hover {font-family:arial black; font-size:14px;}
+.tocBgnd {background:#CCCCCC;}
+
+<!-- for page -->
+.pgRef A:link { }
+.pgRef A:visited { }
+.pgRef A:active { }
+.pgRef A:hover { }
+.pgHeader {background:#E7CF5A;}
+.pgBgnd {background:#FFFFFF;}
+
+<!-- for Input ToolTips -->
+#tipBox {position: absolute; width: 150px; z-index: 100;border: 1pt black solid; background: white; visibility: hidden;}
+.tipBoxCursor {cursor:crosshair;}
+
diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/summary.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/summary.htm
new file mode 100644
index 0000000..3014f7e
--- /dev/null
+++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/summary.htm
@@ -0,0 +1,141 @@
+<html>
+<head>
+<meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+<script src="paths.js"></script><script src="summary.js"></script><link rel="stylesheet" type="text/css" href="../tim/toc.css">
+</head>
+<body class="pgBgnd" id="XC95144XL">
+<span id="summary" class="pgRef"><h3 align="center">Summary</h3>
+<table align="center" width="75%" border="1" cellspacing="0" cellpadding="3">
+<tr>
+<td width="40%"> <b>Design Name</b>
+</td>
+<td width="60%"> LAN_IDE_CP</td>
+</tr>
+<tr>
+<td width="40%"> <b>Fitting Status</b>
+</td>
+<td width="60%"> Successful</td>
+</tr>
+<tr>
+<td width="40%"> <b>Software Version</b>
+</td>
+<td width="60%"> P.68d</td>
+</tr>
+<tr>
+<td width="40%"> <b>Device Used</b>
+</td>
+<td width="60%"> <a href="#" onclick="showDoc('XC95144XL')" onmouseover="window.status='show Device Info'; return true;" onmouseout="window.status=''">XC95144XL-10-TQ144</a>
+</td>
+</tr>
+<tr>
+<td width="40%"> <b>Date</b>
+</td>
+<td width="60%"> 12-15-2016,  7:48PM</td>
+</tr>
+</table></span><br><span id="sumres" class="pgRef"><h5 align="center">RESOURCES SUMMARY</h5>
+<table align="center" width="90%" border="1" cellspacing="0" cellpadding="0">
+<tr class="pgHeader">
+<th width="20%">Macrocells Used</th>
+<th width="20%">Pterms Used</th>
+<th width="20%">Registers Used</th>
+<th width="20%">Pins Used</th>
+<th width="20%">Function Block Inputs Used</th>
+</tr>
+<tr>
+<td width="20%" align="center">51/144  (36%)</td>
+<td width="20%" align="center">179/720  (25%)</td>
+<td width="20%" align="center">26/144  (19%)</td>
+<td width="20%" align="center">54/117  (47%)</td>
+<td width="20%" align="center">134/432  (32%)</td>
+</tr>
+</table></span><br><span id="pinres" class="pgRef"><h5 align="center">PIN RESOURCES</h5>
+<table align="center" width="90%" border="0" cellspacing="0" cellpadding="0"><tr>
+<td width="50%" valign="top"><table align="center" width="100%" border="1" cellspacing="0" cellpadding="0">
+<tr class="pgHeader">
+<th width="33%">Signal Type</th>
+<th width="33%">Required</th>
+<th width="33%">Mapped</th>
+</tr>
+<tr>
+<td width="33%"> Input</td>
+<td width="33%" align="center"> 26</td>
+<td width="33%" align="center"> 26</td>
+</tr>
+<tr>
+<td width="33%"> Output</td>
+<td width="33%" align="center"> 19</td>
+<td width="33%" align="center"> 19</td>
+</tr>
+<tr>
+<td width="33%"> Bidirectional</td>
+<td width="33%" align="center"> 8</td>
+<td width="33%" align="center"> 8</td>
+</tr>
+<tr>
+<td width="33%"> GCK</td>
+<td width="33%" align="center"> 0</td>
+<td width="33%" align="center"> 0</td>
+</tr>
+<tr>
+<td width="33%"> GTS</td>
+<td width="33%" align="center"> 0</td>
+<td width="33%" align="center"> 0</td>
+</tr>
+<tr>
+<td width="33%"> GSR</td>
+<td width="33%" align="center"> 1</td>
+<td width="33%" align="center"> 1</td>
+</tr>
+</table></td>
+<td width="50%" valign="top"><table align="center" width="100%" border="1" cellspacing="0" cellpadding="0">
+<tr class="pgHeader">
+<th width="33%">Pin Type</th>
+<th width="33%">Used</th>
+<th width="33%">Total</th>
+</tr>
+<tr>
+<td width="33%"> I/O</td>
+<td width="33%" align="center"> 
+              52</td>
+<td width="33%" align="center"> 110</td>
+</tr>
+<tr>
+<td width="33%"> GCK/IO</td>
+<td width="33%" align="center"> 0</td>
+<td width="33%" align="center"> 3</td>
+</tr>
+<tr>
+<td width="33%"> GTS/IO</td>
+<td width="33%" align="center"> 1</td>
+<td width="33%" align="center"> 4</td>
+</tr>
+<tr>
+<td width="33%"> GSR/IO</td>
+<td width="33%" align="center"> 1</td>
+<td width="33%" align="center"> 1</td>
+</tr>
+</table></td>
+</tr></table></span><br><span id="glbres" class="pgRef"><h5 align="center">GLOBAL RESOURCES</h5>
+<table align="center" width="90%" border="1" cellspacing="0" cellpadding="0"><tr>
+<td width="50%"> Signal mapped onto global output enable net (GSR)</td>
+<td width="50%"> RESET</td>
+</tr></table></span><br><span id="pwrres" class="pgRef"><h5 align="center">POWER DATA</h5>
+<table align="center" width="90%" border="1" cellspacing="0" cellpadding="0">
+<tr>
+<td width="50%"> Macrocells in high performance mode (MCHP)</td>
+<td width="50%"> 51</td>
+</tr>
+<tr>
+<td width="50%"> Macrocells in low power mode (MCLP)</td>
+<td width="50%"> 0</td>
+</tr>
+<tr>
+<td width="50%"> Total macrocells used (MC)</td>
+<td width="50%"> 51</td>
+</tr>
+</table></span><form><span class="pgRef"><table width="90%" align="center"><tr>
+<td align="left"><input type="button" onclick="javascript:parent.leftnav.showTop()" onmouseover="window.status='goto top of page'; return true;" onmouseout="window.status=''" value="back to top"></td>
+<td align="right"><input type="button" onclick="window.print()" onmouseover="window.status='print page'; return true;" onmouseout="window.status=''" value="print page"></td>
+</tr></table></span></form>
+</body>
+</html>
diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/summary.js b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/summary.js
new file mode 100644
index 0000000..8702822
--- /dev/null
+++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/summary.js
@@ -0,0 +1,28 @@
+function popWin(url, w, h) {
+  var win = window.open(url, 'win',
+              'toolbar=no,location=no,directories=no,status=no,menubar=no,scrollbars=yes,resizable=yes,width='+w+',height='+h);
+  win.focus();
+}
+
+function showTop() { parent.leftnav.showTop(); }
+
+function showDoc(device) {
+  var url = docURL;
+  
+  if ((device.indexOf("XC2") != -1) && (device.indexOf("S") != -1))
+    url = docCr2sURL;
+  else if (device.indexOf("XC2") != -1) url = docXbrURL;
+  else if (device.indexOf("XA2") != -1) url = docAcr2URL;
+  else if (device.indexOf("XCR3") != -1) url = docXpla3URL;
+  else if (device.indexOf("XV") != -1) url = doc95xvURL;
+  else if (device.indexOf("XL") != -1) url = doc95xlURL;
+  else if (device.indexOf("XA") != -1) url = doc95xaURL;
+  else url = doc95URL;
+
+  popWin(url);
+}
+
+function priceDev(device) {
+  var url = "http://toolbox.xilinx.com/cgi-bin/xilinx.storefront/1816638537/Catalog";
+  popWin(url);
+}
diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/summarydoc.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/summarydoc.htm
new file mode 100644
index 0000000..607f637
--- /dev/null
+++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/summarydoc.htm
@@ -0,0 +1,205 @@
+<!doctype html public "-//w3c//dtd html 4.0 transitional//en">
+<html>
+<head>
+   <meta http-equiv="Content-Type" content="text/html; charset=iso-8859-1">
+   <meta name="generator" content="RoboHELP by eHelp Corporation - www.ehelp.com">
+   <meta name="generator-major-version" content="0.1">
+   <meta name="generator-minor-version" content="1">
+   <meta name="filetype" content="kadov">
+   <meta name="filetype-version" content="1">
+   <meta name="page-count" content="1">
+   <meta name="layout-height" content="509">
+   <meta name="layout-width" content="614">
+   <meta name="date" content="05 24, 2002 11:22:55 AM">
+   <meta name="GENERATOR" content="Mozilla/4.79 [en]C-CCK-MCD   (Windows NT 5.0; U) [Netscape]">
+   <title>Summary</title>
+<!--(==============================================================)-->
+<!--(Document created with RoboEditor. )============================-->
+<!--(==============================================================)-->
+<!--(Meta)==========================================================-->
+<!--(Body)==========================================================-->
+</head>
+<body>
+
+<h1>
+Summary</h1>
+
+<div style="font-size: 10pt;"><span style="font-family: arial, sans-serif;">The
+Summary section of the HTML report contains several tables summarizing
+the fitting results for your design.</span>
+<br>&nbsp;</div>
+<span style="font-family: arial, sans-serif; font-size: 10pt;">The <b>Header</b>
+table contains the following:&nbsp;</span>
+<ul style="list-style: disc;"
+	type=disc>
+<li class="kadov-p" class="kadov-p">
+<span style="font-family: arial, sans-serif; font-size: 10pt;">The Design
+Name</span></li>
+
+<li class="kadov-p" class="kadov-p">
+<span style="font-family: arial, sans-serif; font-size: 10pt;">The Fitting
+Status, which is one of&nbsp; the following:</span></li>
+
+<ul style="list-style: disc;"
+	type=disc>
+<li class="kadov-p" class="kadov-p">
+Successful</span></li>
+
+<li class="kadov-p" class="kadov-p">
+Design Rule Checking Failed</span></li>
+
+<li class="kadov-p" class="kadov-p">
+Placement Failed</span></li>
+
+<li class="kadov-p" class="kadov-p">
+Routing Failed</span></li>
+</ul>
+
+<li class="kadov-p" class="kadov-p">
+<span style="font-family: arial, sans-serif; font-size: 10pt;">The Software
+Version&nbsp;</span></li>
+
+<li class="kadov-p" class="kadov-p">
+<span style="font-family: arial, sans-serif; font-size: 10pt;">The Device
+Used, with a link to a PDF version of the device documentation</span></li>
+
+<li class="kadov-p" class="kadov-p">
+<span style="font-family: arial, sans-serif; font-size: 10pt;">The Date
+and time of completion</span></li>
+</ul>
+<span style="font-family: arial, sans-serif; font-size: 10pt;">The <b>Resources
+Summary</b> table includes:</span><span style="font-size: 10pt;"></span>
+<ul style="list-style: disc;"
+	type=disc>
+<li class="kadov-p" class="kadov-p">
+<span style="font-family: arial, sans-serif; font-size: 10pt;">The number
+and percentage of macrocells used vs total in device&nbsp;</span></li>
+
+<li class="kadov-p" class="kadov-p">
+<span style="font-family: arial, sans-serif; font-size: 10pt;">The number
+and percentage of product terms used vs total in device&nbsp;</span></li>
+
+<li class="kadov-p" class="kadov-p">
+<span style="font-family: arial, sans-serif; font-size: 10pt;">The number
+and percentage of registers used vs total in device&nbsp;</span></li>
+
+<li class="kadov-p" class="kadov-p">
+<span style="font-family: arial, sans-serif; font-size: 10pt;">The number
+and percentage of pins used vs total in device&nbsp;</span></li>
+
+<li class="kadov-p" class="kadov-p">
+<span style="font-family: arial, sans-serif; font-size: 10pt;">The number
+and percentage of function block inputs used vs total in device&nbsp;</span></li>
+</ul>
+<span style="font-family: arial, sans-serif; font-size: 10pt;">The <b>Pin
+Resources</b> table includes two tables:</span><span style="font-size: 10pt;"></span>
+<ul style="list-style: disc;"
+	type=disc>
+<li class="kadov-p" class="kadov-p">
+<span style="font-family: arial, sans-serif; font-size: 10pt;">The first
+table indicates the requirements of the design, broken up by Signal Type.
+The number required and the number mapped onto the device are indicated
+for each signal type.</span></li>
+
+<li class="kadov-p" class="kadov-p">
+<span style="font-family: arial, sans-serif; font-size: 10pt;">The second
+table gives the total number of each pin type available in the device,
+alongwith the number used.</span></li>
+</ul>
+<span style="font-family: arial, sans-serif; font-size: 10pt;"><i>XPLA3
+only</i> - The <b>Local Control Term Resources</b> table lists the local
+control term mapping for each function block:</span><span style="font-size: 10pt;"></span>
+<ul style="list-style: disc;"
+	type=disc>
+<li class="kadov-p" class="kadov-p">
+<span style="font-family: arial, sans-serif; font-size: 10pt;">Each row
+lists the local control term mapping for each of the eight control terms,
+LCT0-LCT7, in a function block.</span></li>
+
+<li class="kadov-p" class="kadov-p">
+<span style="font-family: arial, sans-serif; font-size: 10pt;">The control
+term mapping can be:</span></li>
+
+<ul style="list-style: disc;"
+	type=disc>
+<li class="kadov-p" class="kadov-p">
+<span style="font-family: arial, sans-serif; font-size: 10pt;">ce - clock
+enable</span></li>
+
+<li class="kadov-p" class="kadov-p">
+<span style="font-family: arial, sans-serif; font-size: 10pt;">clk - clock</span></li>
+
+<li class="kadov-p" class="kadov-p">
+<span style="font-family: arial, sans-serif; font-size: 10pt;">ee - output
+enable</span></li>
+
+<li class="kadov-p" class="kadov-p">
+<span style="font-family: arial, sans-serif; font-size: 10pt;">sr - set/reset</span></li>
+
+<li class="kadov-p" class="kadov-p">
+<span style="font-family: arial, sans-serif; font-size: 10pt;">uct1 - universal
+control term clock</span></li>
+
+<li class="kadov-p" class="kadov-p">
+<span style="font-family: arial, sans-serif; font-size: 10pt;">uct2 - universal
+control term output enable</span></li>
+
+<li class="kadov-p" class="kadov-p">
+<span style="font-family: arial, sans-serif; font-size: 10pt;">uct3 - universal
+control term set</span></li>
+
+<li class="kadov-p" class="kadov-p">
+<span style="font-family: arial, sans-serif; font-size: 10pt;">uct4 - universal
+control term reset</span></li>
+</ul>
+
+<li class="kadov-p" class="kadov-p">
+<span style="font-family: arial, sans-serif; font-size: 10pt;">Each LCT
+can have some subset of the signals above mapped onto them:</span></li>
+
+<ul style="list-style: disc;"
+	type=disc>
+<li class="kadov-p" class="kadov-p">
+<span style="font-family: arial, sans-serif; font-size: 10pt;">LCT0 - sr,
+oe</span></li>
+
+<li class="kadov-p" class="kadov-p">
+<span style="font-family: arial, sans-serif; font-size: 10pt;">LCT1 - sr,
+oe</span></li>
+
+<li class="kadov-p" class="kadov-p">
+<span style="font-family: arial, sans-serif; font-size: 10pt;">LCT2 - sr,
+oe</span></li>
+
+<li class="kadov-p" class="kadov-p">
+<span style="font-family: arial, sans-serif; font-size: 10pt;">LCT3 - sr</span></li>
+
+<li class="kadov-p" class="kadov-p">
+<span style="font-family: arial, sans-serif; font-size: 10pt;">LCT4 - ce,
+clk, sr</span></li>
+
+<li class="kadov-p" class="kadov-p">
+<span style="font-family: arial, sans-serif; font-size: 10pt;">LCT5 - clk,
+sr</span></li>
+
+<li class="kadov-p" class="kadov-p">
+<span style="font-family: arial, sans-serif; font-size: 10pt;">LCT6 - clk,
+oe</span></li>
+
+<li class="kadov-p" class="kadov-p">
+<span style="font-family: arial, sans-serif; font-size: 10pt;">LCT7 - clk,
+uct1/uct2/uct3/uct4</span></li>
+</ul>
+</ul>
+<span style="font-family: arial, sans-serif; font-size: 10pt;">The <b>Global
+Resources</b> table indicates the signals used as global signals in the
+device.</span><span style="font-size: 10pt;"></span>
+<p><span style="font-family: arial, sans-serif; font-size: 10pt;"><i>XC9500/XL/XV
+only</i> - The <b>Power Data</b> table indicates the number of macrocells
+in standard and low power mode.</span><span style="font-size: 10pt;"></span>
+<p><span style="font-family: arial, sans-serif; font-size: 10pt;"><i>XPLA3
+only</i> - The <b>Block Resources</b> table indicates the number of function
+block control terms used vs available and the number of foldback NANDs
+used vs available.</span><span style="font-size: 10pt;"></span>
+</body>
+</html>
diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/support.gif b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/support.gif
new file mode 100644
index 0000000..a154620
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diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/time.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/time.htm
new file mode 100644
index 0000000..2856558
--- /dev/null
+++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/time.htm
@@ -0,0 +1,4 @@
+<html><body>
+<pre>
+</pre>
+</body></html>
diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/tooltips.js b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/tooltips.js
new file mode 100644
index 0000000..790ce27
--- /dev/null
+++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/tooltips.js
@@ -0,0 +1,143 @@
+/*  Your are permitted to reuse this code as long as the following copyright
+    notice is not removed:
+
+    This HTML tip handling is copyright 1998 by insideDHTML.com, LLC. More information about this
+    code can be found at Inside Dynamic HTML: HTTP://www.insideDHTML.com
+*/
+
+
+// Support for all collection
+var allSupport = document.all!=null;
+
+function setupEventObject(e) {
+  // Map NS event object to IEs
+  if (e==null) return; // IE returns
+  window.event = e;
+  window.event.fromElement = e.target;
+  window.event.toElement = e.target;
+  window.event.srcElement = e.target;
+  window.event.x = e.x;
+  window.event.y = e.y;
+  // Route the event to the original element
+  // Necessary to make sure _tip is set.
+  window.event.srcElement.handleEvent(e);
+}
+
+function checkName(src) {
+  // Look for tooltip in IE
+  while ((src!=null) && (src._tip==null))
+    src = src.parentElement;
+  return src;
+}
+
+function getElement(elName) {
+  // Get an element from its ID
+  if (allSupport) return document.all[elName];
+  else            return document.layers[elName];
+}
+
+function writeContents(el, tip) {
+  // Replace the contents of the tooltip
+  if (allSupport)
+    el.innerHTML = tip;
+  else {
+    // In NS, insert a table to work around
+    // stylesheet rendering bug.
+    // NS fails to apply style sheets when writing
+    // contents into a positioned element.
+    el.document.open();
+    el.document.write("<TABLE WIDTH=200 BORDER=1 bordercolor=black><TR><TD WIDTH=100% BGCOLOR=yellow>");
+    el.document.write(tip);
+    el.document.write("</TD></TR></TABLE>");
+    el.document.close();
+  }
+}
+
+function getOffset(el, which) {
+  // Function for IE to calculate position
+  // of an element.
+  var amount = el["offset"+which];
+  if (which=="Top") amount+=el.offsetHeight;
+  el = el.offsetParent;
+  while (el!=null) {
+    amount+=el["offset"+which];
+    el = el.offsetParent;
+  }
+  return amount;
+}
+
+
+function setPosition(el) {
+  // Set the position of an element
+
+  src = window.event.srcElement
+  if (allSupport) {
+    el.style.pixelTop = getOffset(src, "Top");
+    el.style.pixelLeft = getOffset(src, "Left");
+  }
+  else {
+    el.top = src.y + 20; //window.event.y + 15
+    el.left = src.x; //window.event.x
+  }
+}
+
+function setVisibility(el, bDisplay) {
+  // Hide or show to tip
+  if (bDisplay) {
+    if (allSupport) el.style.visibility = "visible";
+    else            el.visibility = "show";
+  }
+  else {
+    if (allSupport) el.style.visibility = "hidden";
+    else            el.visibility = "hidden";
+  }
+}
+
+
+function displayContents(tip) {
+  // Display the tooltip.
+  var el = getElement("tipBox");
+  writeContents(el, tip);
+  setPosition(el);
+  setVisibility(el, true);
+}
+
+
+function doMouseOver(e) {
+  // Mouse moves over an element
+  setupEventObject(e);
+  var el, tip;
+  if ((el = checkName(window.event.srcElement))!=null) {
+    if  (!el._display) {
+      displayContents(el._tip);
+      el._display = true;
+    }
+  }
+}
+
+function doMouseOut(e) {
+  // Mouse leaves an element
+  setupEventObject(e);
+  el = checkName(window.event.srcElement);
+  var el, tip;
+  if ((el = checkName(window.event.srcElement))!=null) {
+    if (el._display) {
+      if ((el.contains==null) || (!el.contains(window.event.toElement))) {
+        setVisibility(getElement("tipBox"), false);
+        el._display = false;
+      }
+    }
+  }
+}
+
+function doLoad() {
+  // Do Loading
+  if ((window.document.captureEvents==null) && (!allSupport))
+    return; // Not IE4 or NS4
+  if (window.document.captureEvents!=null)  // NS - capture events
+    window.document.captureEvents(Event.MOUSEOVER | Event.MOUSEOUT)
+  window.document.onmouseover = doMouseOver;
+  window.document.onmouseout = doMouseOut;
+}
+
+window.onload = doLoad;
diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/topnav.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/topnav.htm
new file mode 100644
index 0000000..ac2b452
--- /dev/null
+++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/topnav.htm
@@ -0,0 +1,10 @@
+<html>
+<head>
+<meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+<script src="topnav.js"></script><script src="paths.js"></script>
+</head>
+<body bgcolor="#FFFFFF" text="#000000"><table width="100%" border="0" cellspacing="0" cellpadding="0" vspace="0" hspace="0">
+<tr><td valign="top"><img src="xc9500xl_logo.jpg"></td></tr>
+<td height="25" bgcolor="#000000"><img align="center" width="1" height="1" src="blank.gif"></td>
+</table></body>
+</html>
diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/topnav.js b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/topnav.js
new file mode 100644
index 0000000..9e3bb9a
--- /dev/null
+++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/topnav.js
@@ -0,0 +1,30 @@
+function popWin(url) {
+  var win = window.open(url, 'win',
+              'location=yes,directories=yes,menubar=yes,toolbar=yes,status=yes,scrollbars=yes,resizable=yes,width=800,height=600');
+  win.focus();
+}
+
+function openTab(type, device) {
+  var url = rootURL;
+  switch (type) {
+    case 0: url = rootURL; break;
+    case 1:
+      if (device.indexOf('XC2') != -1) url += prodURL + xbrURL;
+      else if (device.indexOf('XA2') != -1) url += prodURL + acr2URL;
+      else if (device.indexOf('XCR3') != -1) url += prodURL + xpla3URL;
+      else if (device.indexOf('XV') != -1) url += prodURL + xc9500xvURL;
+      else if (device.indexOf('XL') != -1) url += prodURL + xc9500xlURL;
+      else if (device.indexOf('XA') != -1) url += prodURL + xa9500xlURL;
+      else url += prodURL + xc9500URL;
+      break;
+    case 2: url += marketURL; break;
+    case 3: url = supportURL; break;
+    case 4: url += educationURL; break;
+    case 5: url = buyURL; break;
+    case 6: url += contactURL; break;
+    case 7: url += searchURL; break;
+    default: url = rootURL;
+  }
+
+  popWin(url);
+}
diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/unmapinputdoc.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/unmapinputdoc.htm
new file mode 100644
index 0000000..fe242d6
--- /dev/null
+++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/unmapinputdoc.htm
@@ -0,0 +1,65 @@
+<!doctype HTML public "-//W3C//DTD HTML 4.0 Frameset//EN">
+
+<html>
+
+<!--(==============================================================)-->
+<!--(Document created with RoboEditor. )============================-->
+<!--(==============================================================)-->
+
+<head>
+
+<title>unmapinputdoc</title>
+
+<!--(Meta)==========================================================-->
+
+<meta name=generator content="RoboHELP by eHelp Corporation - www.ehelp.com">
+<meta name=generator-major-version content=0.1>
+<meta name=generator-minor-version content=1>
+<meta name=filetype content=kadov>
+<meta name=filetype-version content=1>
+<meta name=page-count content=1>
+<meta name=layout-height content=353>
+<meta name=layout-width content=615>
+<meta name=date content="11 26, 2002 2:10:18 PM">
+
+
+
+<style>
+<!--
+p.whs1 {font-family: arial, sans-serif; font-size: 10pt;}
+
+--></style><script language="javascript" title="WebHelpInlineScript">
+<!--
+function reDo() {
+  if (innerWidth != origWidth || innerHeight != origHeight)
+     location.reload();
+}
+if ((parseInt(navigator.appVersion) == 4) && (navigator.appName == "Netscape")) {
+	origWidth = innerWidth;
+	origHeight = innerHeight;
+	onresize = reDo;
+}
+//-->
+</script><style>
+<!--
+  div.WebHelpPopupMenu {position:absolute; left:0px; top:0px; z-index:4; visibility:hidden;}
+  p.WebHelpNavBar {text-align:right;}
+-->
+</style>
+</head>
+
+<!--(Body)==========================================================-->
+
+
+<body>
+
+
+<h1>Unmapped Inputs</h1>
+
+<p class="whs1">This page shows 
+ input signals which were either not mapped or <span style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">not 
+ routed.</FONT></span></p>
+
+</body>
+
+</html>
diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/unmaplogicdoc.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/unmaplogicdoc.htm
new file mode 100644
index 0000000..6371313
--- /dev/null
+++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/unmaplogicdoc.htm
@@ -0,0 +1,68 @@
+<!doctype HTML public "-//W3C//DTD HTML 4.0 Frameset//EN">
+
+<html>
+
+<!--(==============================================================)-->
+<!--(Document created with RoboEditor. )============================-->
+<!--(==============================================================)-->
+
+<head>
+
+<title>unmaplogicdoc</title>
+
+<!--(Meta)==========================================================-->
+
+<meta name=generator content="RoboHELP by eHelp Corporation - www.ehelp.com">
+<meta name=generator-major-version content=0.1>
+<meta name=generator-minor-version content=1>
+<meta name=filetype content=kadov>
+<meta name=filetype-version content=1>
+<meta name=page-count content=1>
+<meta name=layout-height content=353>
+<meta name=layout-width content=615>
+<meta name=date content="11 26, 2002 2:04:45 PM">
+
+
+
+<style>
+<!--
+p.whs1 {font-size: 22pt; font-weight: bold;}
+p.whs2 {font-family: arial, sans-serif; font-size: 10pt; font-weight: normal;}
+
+--></style><script language="javascript" title="WebHelpInlineScript">
+<!--
+function reDo() {
+  if (innerWidth != origWidth || innerHeight != origHeight)
+     location.reload();
+}
+if ((parseInt(navigator.appVersion) == 4) && (navigator.appName == "Netscape")) {
+	origWidth = innerWidth;
+	origHeight = innerHeight;
+	onresize = reDo;
+}
+//-->
+</script><style>
+<!--
+  div.WebHelpPopupMenu {position:absolute; left:0px; top:0px; z-index:4; visibility:hidden;}
+  p.WebHelpNavBar {text-align:right;}
+-->
+</style>
+</head>
+
+<!--(Body)==========================================================-->
+
+
+<body>
+
+
+<p class="whs1">Unmapped Logic</p>
+
+<p class="whs2">This page shows those equations whose 
+ logic was either not placed or not <span style="font-family: arial, sans-serif;
+													font-size: 10pt;
+													font-weight: normal;"><FONT SIZE=2 style="font-size:10pt;">completely 
+ placed in the specified device.</FONT></span></p>
+
+</body>
+
+</html>
diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/verboseview.jpg b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/verboseview.jpg
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diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/wait.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/wait.htm
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index 0000000..2b6486c
--- /dev/null
+++ b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/wait.htm
@@ -0,0 +1,7 @@
+<html>
+<head>
+<meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+<link rel="stylesheet" type="text/css" href="style.css">
+</head>
+<body class="pgBgnd"><center><h3>Processing...</h3></center></body>
+</html>
diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/fit/xc9500_logo.gif b/Logic/LAN_IDE/LAN_IDE_CP_html/fit/xc9500_logo.gif
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+<!doctype HTML public "-//W3C//DTD HTML 4.0 Frameset//EN">
+
+<html>
+
+<!--(==============================================================)-->
+<!--(Document created with RoboEditor. )============================-->
+<!--(==============================================================)-->
+
+<head>
+
+<title>CPLD Timing Analysis Glossary</title>
+
+<!--(Meta)==========================================================-->
+
+<meta http-equiv=Content-Type content="text/html; charset=UTF-8">
+<meta name=Author content=administrator>
+<meta name=generator content="RoboHELP by eHelp Corporation - www.ehelp.com">
+<meta name=generator-major-version content=0.1>
+<meta name=generator-minor-version content=1>
+<meta name=filetype content=kadov>
+<meta name=filetype-version content=1>
+<meta name=page-count content=1>
+<meta name=layout-height content=2677>
+<meta name=layout-width content=716>
+<meta name=date content="04 8, 2003 10:49:54 AM">
+
+
+<!--(Links)=========================================================-->
+
+<link rel=StyleSheet href=xilhtml.css>
+
+
+
+</head>
+
+<!--(Body)==========================================================-->
+
+
+<body>
+
+<h1>Introduction</h1>
+
+<p>This report is the result of a static timing analysis of your design 
+ after it has been fit in the device that you selected. The timing values 
+ given represent the worst-case values over the recommended operating conditions 
+ for the part. </p>
+
+<h1>Overview</h1>
+
+<p>The timing report consists of a series of sections: </p>
+
+<h2>Summary</h2>
+
+<p>This table summarizes the external timing parameters for your device, 
+ including <a href="#tPD"><!--kadov_tag{{<ignored>}}-->tPD<!--kadov_tag{{</ignored>}}--></a>, 
+ <a href="#tCO"><!--kadov_tag{{<ignored>}}-->tCO<!--kadov_tag{{</ignored>}}--></a>, 
+ <a href="#tSU"><!--kadov_tag{{<ignored>}}-->tSU<!--kadov_tag{{</ignored>}}--></a>, 
+ <a href="#tCYC"><!--kadov_tag{{<ignored>}}-->tCYC<!--kadov_tag{{</ignored>}}--></a>, 
+ and <a href="#fSYSTEM"><!--kadov_tag{{<ignored>}}-->fSYSTEM<!--kadov_tag{{</ignored>}}--></a>. 
+ <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->For a more 
+ detailed description of the timing model for your device, please refer 
+ to the application notes linked below.</p>
+
+<h2>Timing Constraints</h2>
+
+<p>This section reports on any timing constraints that you created for 
+ your design. Timing constraints can be entered using the Constraints Editor 
+ tool, or by editing an Implementation Constraints File directly. For more 
+ information on creating timing constraints, see the Constraints Guide. 
+ </p>
+
+<p class=Note><span style="font-weight: bold;">Note</span> that if you 
+ did not define any constraints for your design, then the timing analysis 
+ software will automatically create a default set of constraints for you. 
+ These include pad-to-pad, register-to-register, pad-to-register, and period 
+ constraints. A constraint value of 0 <!--kadov_tag{{<ignored>}}-->ns<!--kadov_tag{{</ignored>}}--> 
+ will be used for all of these automatically generated constraints. As 
+ a result, all paths listed under each constraint will violate the constraint, 
+ and will have a negative value for slack.</p>
+
+<p class=Note><span style="font-weight: bold;">Note</span> also that to 
+ limit the size of the report, each path endpoint involved in a timing 
+ path will only be listed once, under a single constraint. <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}--></p>
+
+<p>For each timing path listed under a constraint, there is a hyperlink 
+ that can be used to open a window listing the individual internal delay 
+ elements traversed in the path. To understand these delay elements, consult 
+ the <a href="#Definitions">Definitions</a> section below, or the following 
+ application notes and white papers: </p>
+
+<p><a href="http://www.xilinx.com/apps/epld.htm#CoolRunner2">XAPP375: Understanding 
+ the <!--kadov_tag{{<ignored>}}-->CoolRunner-II<!--kadov_tag{{</ignored>}}--> 
+ Timing Model</a> </p>
+
+<p><a href="http://www.xilinx.com/publications/whitepapers/index.htm">WP122: 
+ Using the <!--kadov_tag{{<ignored>}}-->CoolRunner<!--kadov_tag{{</ignored>}}--> 
+ XPLA3 Timing Model</a> </p>
+
+<p><a href="http://www.xilinx.com/apps/epld.htm#CoolRunner2">XAPP071: Using 
+ the XC9500 Timing Model</a> </p>
+
+<p><a href="http://www.xilinx.com/apps/epld.htm#CoolRunner2">XAPP111: Using 
+ the XC9500XL Timing Model</a></p>
+
+<p><a href="http://www.xilinx.com/apps/epld.htm#CoolRunner2"><!--kadov_tag{{<ignored>}}-->XAPP<!--kadov_tag{{</ignored>}}--> 
+ 362: Using the XC9500XV Timing Model</a></p>
+
+<p>available in the literature section of <a href="http://www.xilinx.com"><!--kadov_tag{{<ignored>}}-->www.xilinx.com</a>.<!--kadov_tag{{</ignored>}}--> 
+ </p>
+
+<h2>Data Sheet Report</h2>
+
+<p>This section of the report lists the external timing parameters for 
+ your design. This includes; maximum external clock speed for each clock, 
+ setup and hold times for each registered input, clock-to-output pad timing 
+ for each registered output, clock to setup time for each register-to-register 
+ timing path, and pad-to-pad time for each combinatorial path through your 
+ design. </p>
+
+<h2>Going Further</h2>
+
+<p>To do more advanced timing analysis of your design, select the process 
+ <span style="font-weight: bold;">Analyze Post-Fit Static Timing</span> 
+ in <!--kadov_tag{{<ignored>}}-->iSE<!--kadov_tag{{</ignored>}}-->. This 
+ will run <!--kadov_tag{{<ignored>}}-->Xilinx's<!--kadov_tag{{</ignored>}}--> 
+ Timing Analyzer tool interactively. <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->The 
+ Timing Analyzer provides a powerful, flexible, and easy way to perform 
+ static timing analysis on <!--kadov_tag{{<ignored>}}-->FPGA<!--kadov_tag{{</ignored>}}--> 
+ and <!--kadov_tag{{<ignored>}}-->CPLD<!--kadov_tag{{</ignored>}}--> designs. 
+ With Timing Analyzer, analysis can be performed immediately after mapping, 
+ placing or routing an <!--kadov_tag{{<ignored>}}-->FPGA<!--kadov_tag{{</ignored>}}--> 
+ design, and after fitting and routing a <!--kadov_tag{{<ignored>}}-->CPLD<!--kadov_tag{{</ignored>}}--> 
+ design. </p>
+
+<p>Timing Analyzer verifies that the delay along a given path or paths 
+ meets specified timing requirements. It organizes and displays data that 
+ allows you to analyze critical paths in a circuit, the cycle time of the 
+ circuit, the delay along any specified <!--kadov_tag{{<ignored>}}-->path(s<!--kadov_tag{{</ignored>}}-->), 
+ and the path with the greatest delay. It also provides a quick analysis 
+ of the effect different speed grades have on the same design. <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}--></p>
+
+<p>Timing Analyzer performs setup and hold checks (skew analysis). It works 
+ with synchronous systems composed of synchronous elements and combinatorial 
+ logic. In synchronous design, Timing Analyzer takes into account all path 
+ delays, including clock-to-out and setup requirements, while calculating 
+ the worst-case timing of the design. </p>
+
+<p>Timing Analyzer creates timing analysis reports based on existing timing 
+ constraints or user specified paths within the program. Timing reports 
+ have a hierarchical browser to quickly jump to different sections of the 
+ reports. Timing paths in reports can be cross probed to synthesis tools 
+ (Exemplar and <!--kadov_tag{{<ignored>}}-->Synplicity<!--kadov_tag{{</ignored>}}-->) 
+ and <!--kadov_tag{{<ignored>}}-->Floorplanner<!--kadov_tag{{</ignored>}}-->. 
+ </p>
+
+<p>There are several ways to issue commands in Timing Analyzer. Timing 
+ Analyzer can be controlled through <!--kadov_tag{{<ignored>}}-->GUI<!--kadov_tag{{</ignored>}}--> 
+ features (menu commands) or its comprehensive macro command language facility. 
+ You can select from menus, click toolbar buttons, type keyboard commands 
+ in the console window, and run macros. </p>
+
+<h1><a name=Definitions></a>Definitions</h1>
+
+<h2><a name=tPD></a>Pad to Pad (<!--kadov_tag{{<ignored>}}-->tPD<!--kadov_tag{{</ignored>}}-->) 
+ </h2>
+
+<p>Reports pad to pad paths that start at input pads and end at output 
+ pads. The maximum external pad to pad delay. <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->Combinatorial 
+ pad-to-pad paths begin at input pads, propagate through one or more levels 
+ of combinatorial logic and end at output pads. Combinatorial paths also 
+ trace through the enable inputs of 3-state controlled pads. Combinatorial 
+ paths are not traced through clock, and asynchronous set and reset inputs 
+ of registers. These paths are also broken at bidirectional pins</p>
+
+<h2><a name=tCO></a>Clock Pad to Output Pad (<!--kadov_tag{{<ignored>}}-->tCO<!--kadov_tag{{</ignored>}}-->) 
+ </h2>
+
+<p>The maximum external clock pad to output pad delay. <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->Reports 
+ paths that start at input <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->pads 
+ trace through clock inputs of <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->registers 
+ and end at output pads. Paths are not traced through PRE/<!--kadov_tag{{<ignored>}}-->CLR<!--kadov_tag{{</ignored>}}--> 
+ <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->inputs 
+ of registers. <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->You 
+ can directly specify <!--kadov_tag{{<ignored>}}-->tCO<!--kadov_tag{{</ignored>}}--> 
+ for all registered output paths in your design using the Pad-to-Pad <!--kadov_tag{{<ignored>}}-->timespec<!--kadov_tag{{</ignored>}}-->. 
+ Clock-Pad-to-Pad paths for global clocks begin at global clock pads, propagate 
+ through global clock buffers, and propagate through the flip-flop <!--kadov_tag{{<ignored>}}-->Q<!--kadov_tag{{</ignored>}}--> 
+ output and any number of levels of combinatorial logic and end at the 
+ output pad. Clock-Pad-to-Pad paths for product term clock paths begin 
+ at input pads, propagate through any number of logic levels feeding into 
+ a clock product term, propagate through the flip-flop <!--kadov_tag{{<ignored>}}-->Q<!--kadov_tag{{</ignored>}}--> 
+ output and any number of levels of combinatorial logic and end at the 
+ output pad. Clock-Pad-to-Pad paths also trace through the enable inputs 
+ of 3-state controlled pads.</p>
+
+<h2><a name=tSU></a>Setup to Clock at Pad (<!--kadov_tag{{<ignored>}}-->tSU<!--kadov_tag{{</ignored>}}--> 
+ or <!--kadov_tag{{<ignored>}}-->tSUF<!--kadov_tag{{</ignored>}}-->) </h2>
+
+<p>Reports external setup time of data <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->to 
+ clock at pad. Data path starts at an input pad and ends at register <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->(Fast 
+ Input Register for <!--kadov_tag{{<ignored>}}-->tSUF<!--kadov_tag{{</ignored>}}-->) 
+ D/<!--kadov_tag{{<ignored>}}-->T<!--kadov_tag{{</ignored>}}--> <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->input. 
+ Clock path starts at input pad and ends at the register clock input. <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->Paths 
+ are not traced through registers. Pin-to-pin setup requirement is not 
+ reported or guaranteed for product-term clocks derived from <!--kadov_tag{{<ignored>}}-->macrocell<!--kadov_tag{{</ignored>}}--> 
+ feedback signals. </p>
+
+<p>The minimum required setup time for flip-flops. <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->You 
+ can specify the <!--kadov_tag{{<ignored>}}-->tSU<!--kadov_tag{{</ignored>}}--> 
+ (setup-to-clock) for all inputs in your design relative to a global clock 
+ or product term clock. Each <!--kadov_tag{{<ignored>}}-->tSU<!--kadov_tag{{</ignored>}}--> 
+ OFFSET timespec involves an input path and a clock path. Input paths start 
+ at input pads, propagate through input buffers and any number of combinatorial 
+ logic levels before ending at a flip-flop D/T input, including the receiving 
+ flip-flop's tSU. <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->Input 
+ paths are not traced through flip-flop clock pins, asynchronous set/reset 
+ inputs or bidirectional I/O pins. Global clock paths start at global clock 
+ pads, propagate through global clock buffers and end at the flip-flop 
+ clock pin. Product term clock paths start at input pads, propagate through 
+ a single level of logic implemented in a clock product term and end at 
+ the flip-flop clock pin.</p>
+
+<h2><a name=tCYC></a>Clock to Setup (tCYC) </h2>
+
+<p>Register to register cycle time. Includes source register tCO and destination 
+ register tSU. </p>
+
+<p class=Note><span style="font-weight: bold;">Note</span> that when the 
+ computed Maximum Clock Speed is limited by tCYC, it is computed assuming 
+ that all registers are rising-edge sensitive. </p>
+
+<h2><a name=fSYSTEM></a>fSYSTEM </h2>
+
+<p>Maximum clock operating frequency. <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->You 
+ can specify the fSYSTEM (clock frequency or period) for all registered 
+ paths in your design using a Register-to-Register timespec. Register-to-Register 
+ paths begin at flip-flop clock inputs, propagate through the flip-flop 
+ Q output and any number of levels of combinatorial logic and end at the 
+ receiving flip-flop D/T input, including the receiving flip-flop's tSU. 
+ When these flip-flops are clocked by the same clock, the delay on this 
+ path is equivalent to the cycle time of the clock. Registered paths do 
+ not propagate through clock, and asynchronous set and reset inputs of 
+ registers as shown below. These paths are also broken at bidirectional 
+ pins.</p>
+
+<p>&nbsp;</p>
+
+</body>
+
+</html>
diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/tim/cpldta_style.css b/Logic/LAN_IDE/LAN_IDE_CP_html/tim/cpldta_style.css
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--- /dev/null
+++ b/Logic/LAN_IDE/LAN_IDE_CP_html/tim/cpldta_style.css
@@ -0,0 +1,144 @@
+<!-- $Id: cpldta_style.css,v 1.2 2003/03/20 05:15:52 soeren Exp $  -->
+<!-- Stylesheet for the CPLD HTML Timing Report                  -->
+
+<!-- style for H1 elements  -->
+.cpldta_text_report_header {
+	font-style: normal;
+	font-weight: bold;
+	font-size: 25pt;
+	font-family: Arial, Helvetica, sans-serif;
+	text-align: center;}
+<!-- style for H2 elements  -->
+.cpldta_text_section_header {
+	font-style: normal;
+	font-weight: bold;
+	font-size: 15pt;
+	font-family: Arial, Helvetica, sans-serif;
+	text-align: center;}
+<!-- style for H3 elements  -->
+.cpldta_text_subsection_header {
+	font-style: normal;
+	font-weight: bold;
+	font-size: 10pt;
+	font-family: Arial, Helvetica, sans-serif;
+	text-align: left;}
+
+<!-- Following used for the header of the notes and warnings table  -->
+.cpldta_warnings_header {
+	font-style: normal;
+	font-weight: normal;
+	font-size: 10pt;
+	font-family: Arial, Helvetica, sans-serif;
+	text-align: center;
+	background-color: #FFFFCC; }
+
+<!-- style for general text value fields  -->
+.cpldta_text_normal {
+	font-style: normal;
+	font-weight: normal;
+	font-size: 10pt;
+	font-family: Arial, Helvetica, sans-serif;
+	text-align: left;}
+	
+<!-- style for general text label fields  -->
+.cpldta_text_normal_bold {
+	font-style: normal;
+	font-weight: bold;
+	font-size: 10pt;
+	font-family: Arial, Helvetica, sans-serif;
+	text-align: left;}
+
+<!-- Following two styles are used for constraint descriptions  -->
+.cpldta_constraint_description_normal {
+	font-style: normal;
+	font-weight: normal;
+	font-size: 10pt;
+	font-family: Arial, Helvetica, sans-serif;
+	text-align: left;}
+.cpldta_constraint_description_bold {
+	font-style: normal;
+	font-weight: bold;
+	font-size: 10pt;
+	font-family: Arial, Helvetica, sans-serif;
+	text-align: left;}
+
+<!-- Style for the name of a constraint that is met  -->
+.cpldta_constraint_name {
+	font-style: normal;
+	font-weight: normal;
+	font-size: 10pt;
+	font-family: Arial, Helvetica, sans-serif;
+	text-align: left;}
+
+<!-- Style for the name of a constraint that is not met  -->
+.cpldta_constraint_name_error {
+	font-style: normal;
+	font-weight: normal;
+	font-size: 10pt;
+	font-family: Arial, Helvetica, sans-serif;
+	text-align: left;
+	background-color: #FFCCCC; }
+
+<!-- Style for the delay of a constraint that is met  -->
+.cpldta_time_value {
+	font-style: normal;
+	font-weight: normal;
+	font-size: 10pt;
+	font-family: Arial, Helvetica, sans-serif;
+	text-align: center;}
+	
+<!-- Style for the delay of a constraint that is not met  -->
+.cpldta_time_value_error {
+	font-style: normal;
+	font-weight: normal;
+	font-size: 10pt;
+	font-family: Arial, Helvetica, sans-serif;
+	text-align: center;
+	background-color: #FFCCCC; }
+
+<!-- Styles for the header of the delay table for a constraint  -->
+.cpldta_delaytable_header {
+	font-style: normal;
+	font-weight: bold;
+	font-size: 12pt;
+	font-family: Arial, Helvetica, sans-serif;
+	text-align: center;
+	background-color: #FFFFCC; }
+.cpldta_constraint_header {
+	font-style: normal;
+	font-weight: bold;
+	font-size: 10pt;
+	font-family: Arial, Helvetica, sans-serif;
+	text-align: left;
+	background-color: #FFFFCC; }
+.cpldta_time_header {
+	font-style: normal;
+	font-weight: bold;
+	font-size: 10pt;
+	font-family: Arial, Helvetica, sans-serif;
+	text-align: center;
+	background-color: #FFFFCC; }
+.cpldta_text_caption {
+	font-style: normal;
+	font-weight: Bold;
+	font-size: 10pt;
+	font-family: Arial, Helvetica, sans-serif;
+	text-align: center;}
+
+<!-- Following styles used for the datasheet section of the report  -->
+.cpldta_datasheet_pathname {
+	font-style: normal;
+	font-weight: normal;
+	font-size: 10pt;
+	font-family: Arial, Helvetica, sans-serif;
+	text-align: left;}
+.cpldta_datasheet_time_value {
+	font-style: normal;
+	font-weight: normal;
+	font-size: 10pt;
+	font-family: Arial, Helvetica, sans-serif;
+	text-align: center;}
+
+
+
+
diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/tim/genreport.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/tim/genreport.htm
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+++ b/Logic/LAN_IDE/LAN_IDE_CP_html/tim/genreport.htm
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+<html>
+<head>
+<title>Reports</title>
+<meta http-equiv="Content-Type" content="text/html; charset=iso-8859-1">
+</head>
+<frameset rows="94,*" cols="*" frameborder="NO" border="0" framespacing="0">;
+  <frame name="topFrame" scrolling="NO" noresize src="topnav.htm" marginwidth="0" marginheight="0">
+  <frameset cols="160,*" frameborder="NO" border="0" framespacing="0" rows="*"> 
+    <frame name="leftFrame" noresize scrolling="NO" src="leftnav.htm" marginwidth="0" marginheight="0">
+    <frame name="mainFrame" src="timing_report.htm" marginwidth="0" marginheight="0">
+  </frameset>
+</frameset>
+<noframes> 
+<body bgcolor="#FFFFFF" text="#000000">
+</body>
+</noframes> 
+</html>
diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/tim/leftnav.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/tim/leftnav.htm
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+<html>
+<head>
+<title>Timing Navigation</title>
+<meta http-equiv="Content-Type" content="text/html; charset=iso-8859-1">
+<link rel="stylesheet" type="text/css" href="../tim/toc.css">
+</head>
+
+<body bgcolor="#CCCCCC" text="#000000" onLoad="parent.frames.mainFrame.location='timing_report.htm'">
+<table width="100%" border="0" cellspacing="0" cellpadding="0">
+  <tr> 
+    <td colspan="3"> 
+      <div align="left"><SPAN class="HEADING">Timing Report</span></div>
+    </td>
+  </tr>
+  <tr>
+    <td width="7">&nbsp;</td>
+    <td colspan="2"><a href="timing_report.htm#TimingReport" target="mainFrame" class="SECONDARY-NAV">Description</a></td>
+  </tr>
+  <tr> 
+    <td width="7">&nbsp;</td>
+    <td colspan="2"><a href="timing_report.htm#Summary" target="mainFrame" class="SECONDARY-NAV">Summary</a></td>
+  </tr>
+  <tr> 
+    <td width="7">&nbsp;</td>
+    <td colspan="2"><a href="timing_report.htm#TimingConstraints" target="mainFrame" class="SECONDARY-NAV">Constraints</a></td>
+  </tr>
+  <tr> 
+    <td width="7">&nbsp;</td>
+    <td colspan="2"><a href="cpldta_glossary.htm" target="mainFrame" class="SECONDARY-NAV">Definitions</a></td>
+  </tr>
+  <tr> 
+    <td width="7">&nbsp;</td>
+    <td colspan="2">&nbsp;</td>
+  </tr>
+</table>
+</body>
+</html>
diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/tim/report.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/tim/report.htm
new file mode 100644
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--- /dev/null
+++ b/Logic/LAN_IDE/LAN_IDE_CP_html/tim/report.htm
@@ -0,0 +1,17 @@
+<html>
+<head>
+<title>Reports</title>
+<meta http-equiv="Content-Type" content="text/html; charset=iso-8859-1">
+</head>
+<frameset rows="94,*" cols="*" frameborder="NO" border="0" framespacing="0">;
+  <frame name="topFrame" scrolling="NO" noresize src="topnav.htm" marginwidth="0" marginheight="0">
+  <frameset cols="160,*" frameborder="NO" border="0" framespacing="0" rows="*"> 
+    <frame name="leftFrame" noresize scrolling="NO" src="leftnav.htm" marginwidth="0" marginheight="0">
+    <frame name="mainFrame" src="timing_report.htm" marginwidth="0" marginheight="0">
+  </frameset>
+</frameset>
+<noframes> 
+<body bgcolor="#FFFFFF" text="#000000">
+</body>
+</noframes> 
+</html>
diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/tim/timing_report.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/tim/timing_report.htm
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@@ -0,0 +1,1534 @@
+<!DOCTYPE HTML PUBLIC "-//w3c//dtd html 4.0 transitional//en">
+<HTML>
+<HEAD>
+<meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+<meta name="Generator" content="Timing Report Generator:  version P.68d">
+<meta name="Author" content="Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.">
+<meta name="Description" content="Timing report for LAN_IDE_CP">
+<TITLE>Timing report for LAN_IDE_CP</TITLE>
+<script language="Javascript"> 
+<!-- 
+   function popWin(url,w,h,name){ 
+   window.open(url,name,'scrollbars=yes,resizable=Yes,WIDTH='+w+',height='+h); 
+   } 
+//--> 
+</script>
+</HEAD>
+<A NAME="Top"></a>
+<A NAME="TimingReport"></a><h1 ALIGN="center" CLASS="cpldta_text_report_header">Timing Report</h1>
+<CENTER><SPAN CLASS="cpldta_text_normal_bold"><A HREF="cpldta_glossary.htm"><B>Need help reading this report?</B></A></SPAN></CENTER><BR>
+<TABLE  WIDTH="60%" border="1" ALIGN="center">
+ <TR>
+  <TD WIDTH="35%" CLASS="cpldta_text_normal_bold"><B>Design Name</B></TD>
+  <TD WIDTH="65%" CLASS="cpldta_text_normal">LAN_IDE_CP</TD>
+ </TR>
+ <TR>
+  <TD WIDTH="35%" CLASS="cpldta_text_normal_bold"><B>Device, Speed (SpeedFile Version)</B></TD>
+  <TD WIDTH="65%" CLASS="cpldta_text_normal"><A HREF="Javascript:popWin('http://www.xilinx.com/literature/index.htm','800','800','test');">XC95144XL</A>, -10 (3.0)</TD>
+ </TR>
+ <TR>
+  <TD WIDTH="35%" CLASS="cpldta_text_normal_bold"><B>Date Created</B></TD>  <TD WIDTH="65%" CLASS="cpldta_text_normal">Thu Dec 15 19:17:49 2016
+</TD>
+ </TR>
+ <TR>
+  <TD WIDTH="35%" CLASS="cpldta_text_normal_bold"><B>Created By</B></TD>  <TD WIDTH="65%" CLASS="cpldta_text_normal">Timing Report Generator:  version P.68d</TD>
+ </TR>
+ <TR>
+  <TD WIDTH="35%" CLASS="cpldta_text_normal_bold"><B>Copyright</B></TD>  <TD WIDTH="65%" CLASS="cpldta_text_normal">Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.</TD>
+ </TR>
+</TABLE>
+<A NAME="Summary"></a><h2 ALIGN="center" CLASS="cpldta_text_section_header">Summary</h2>
+<TABLE  WIDTH="80%" border="1" ALIGN="center">
+ <TR CLASS="cpldta_warnings_header">
+  <TH BGCOLOR="#FFFFCC" WIDTH="100%">Notes and Warnings</TH>
+ </TR>
+ <TR>
+  <TD WIDTH="100%" CLASS="cpldta_text_normal">Note: This design contains no timing constraints.</TD>
+ </TR>
+ <TR>
+  <TD WIDTH="100%" CLASS="cpldta_text_normal">Note: A default set of constraints using a delay of 0.000ns will be used for analysis.</TD>
+ </TR>
+ <TR>
+  <TD WIDTH="100%" CLASS="cpldta_text_normal">Possible asynchronous logic: Clock pin 'AUTO_CONFIG_DONE_CYCLE<1>.CLKF' has multiple original clock nets 'C1' 'C3'.</TD>
+ </TR>
+ <TR>
+  <TD WIDTH="100%" CLASS="cpldta_text_normal">Possible asynchronous logic: Clock pin 'IDE_BASEADR<0>.CLKF' has multiple original clock nets 'C1' 'C3'.</TD>
+ </TR>
+ <TR>
+  <TD WIDTH="100%" CLASS="cpldta_text_normal">Possible asynchronous logic: Clock pin 'IDE_BASEADR<4>.CLKF' has multiple original clock nets 'C1' 'C3'.</TD>
+ </TR>
+ <TR>
+  <TD WIDTH="100%" CLASS="cpldta_text_normal">Possible asynchronous logic: Clock pin 'IDE_BASEADR<5>.CLKF' has multiple original clock nets 'C1' 'C3'.</TD>
+ </TR>
+ <TR>
+  <TD WIDTH="100%" CLASS="cpldta_text_normal">Possible asynchronous logic: Clock pin 'IDE_ENABLE.CLKF' has multiple original clock nets 'C1' 'C3'.</TD>
+ </TR>
+ <TR>
+  <TD WIDTH="100%" CLASS="cpldta_text_normal">Possible asynchronous logic: Clock pin 'IDE_BASEADR<1>.CLKF' has multiple original clock nets 'C1' 'C3'.</TD>
+ </TR>
+ <TR>
+  <TD WIDTH="100%" CLASS="cpldta_text_normal">Possible asynchronous logic: Clock pin 'IDE_BASEADR<2>.CLKF' has multiple original clock nets 'C1' 'C3'.</TD>
+ </TR>
+ <TR>
+  <TD WIDTH="100%" CLASS="cpldta_text_normal">Possible asynchronous logic: Clock pin 'IDE_BASEADR<3>.CLKF' has multiple original clock nets 'C1' 'C3'.</TD>
+ </TR>
+ <TR>
+  <TD WIDTH="100%" CLASS="cpldta_text_normal">Possible asynchronous logic: Clock pin 'IDE_BASEADR<6>.CLKF' has multiple original clock nets 'C1' 'C3'.</TD>
+ </TR>
+ <TR>
+  <TD WIDTH="100%" CLASS="cpldta_text_normal">Possible asynchronous logic: Clock pin 'IDE_BASEADR<7>.CLKF' has multiple original clock nets 'C1' 'C3'.</TD>
+ </TR>
+ <TR>
+  <TD WIDTH="100%" CLASS="cpldta_text_normal">Possible asynchronous logic: Clock pin 'SHUT_UP<1>.CLKF' has multiple original clock nets 'C1' 'C3'.</TD>
+ </TR>
+ <TR>
+  <TD WIDTH="100%" CLASS="cpldta_text_normal">Possible asynchronous logic: Clock pin 'ide.CLKF' has multiple original clock nets 'C1' 'C3'.</TD>
+ </TR>
+ <TR>
+  <TD WIDTH="100%" CLASS="cpldta_text_normal">Possible asynchronous logic: Clock pin 'autoconfig.CLKF' has multiple original clock nets 'C1' 'C3'.</TD>
+ </TR>
+ <TR>
+  <TD WIDTH="100%" CLASS="cpldta_text_normal">Possible asynchronous logic: Clock pin 'IDE_R.CLKF' has multiple original clock nets 'C1' 'C3'.</TD>
+ </TR>
+ <TR>
+  <TD WIDTH="100%" CLASS="cpldta_text_normal">Possible asynchronous logic: Clock pin 'IDE_W.CLKF' has multiple original clock nets 'C1' 'C3'.</TD>
+ </TR>
+ <TR>
+  <TD WIDTH="100%" CLASS="cpldta_text_normal">Possible asynchronous logic: Clock pin 'ROM_OE.CLKF' has multiple original clock nets 'C1' 'C3'.</TD>
+ </TR>
+</TABLE><BR>
+<TABLE WIDTH="80%" border="1" ALIGN="center">
+ <TR CLASS="cpldta_warnings_header">
+  <TH BGCOLOR="#FFFFCC" WIDTH="100%" colspan="2">Performance Summary</TH>
+ </TR>
+ <TR>
+  <TD WIDTH="65%" CLASS="cpldta_text_normal_bold"><B>Min. Clock Period</B></TD>
+  <TD WIDTH="35%" CLASS="cpldta_text_normal">14.000 ns.</TD>
+ </TR>
+ <TR>
+  <TD WIDTH="65%" CLASS="cpldta_text_normal_bold"><B>Max. Clock Frequency </B><A HREF="cpldta_glossary.htm#fSYSTEM">(fSYSTEM)</A></TD>
+  <TD WIDTH="35%" CLASS="cpldta_text_normal">71.429 MHz. </TD>
+ </TR>
+ <TR>
+  <TD WIDTH="100%" colspan="2" CLASS="cpldta_text_normal">Limited by Clock Pulse Width for C1</TD>
+ </TR>
+ <TR>
+  <TD WIDTH="65%" CLASS="cpldta_text_normal_bold"><B>Clock to Setup </B><A HREF="cpldta_glossary.htm#tCYC">(tCYC)</A></TD>
+  <TD WIDTH="35%" CLASS="cpldta_text_normal">11.400 ns. </TD>
+ </TR>
+ <TR>
+  <TD WIDTH="65%" CLASS="cpldta_text_normal_bold"><B>Pad to Pad Delay </B><A HREF="cpldta_glossary.htm#tPD">(tPD)</A></TD>
+  <TD WIDTH="35%" CLASS="cpldta_text_normal">10.000 ns. </TD>
+ </TR>
+ <TR>
+  <TD WIDTH="65%" CLASS="cpldta_text_normal_bold"><B>Setup to Clock at the Pad </B><A HREF="cpldta_glossary.htm#tSU">(tSU)</A></TD>
+  <TD WIDTH="35%" CLASS="cpldta_text_normal">-4.200 ns. </TD>
+ </TR>
+ <TR>
+  <TD WIDTH="65%" CLASS="cpldta_text_normal_bold"><B>Clock Pad to Output Pad Delay </B><A HREF="cpldta_glossary.htm#tCO">(tCO)</A></TD>
+  <TD WIDTH="35%" CLASS="cpldta_text_normal">17.900 ns. </TD>
+ </TR>
+</TABLE>
+<HR>
+<A NAME="TimingConstraints"></a><h2 ALIGN="center" CLASS="cpldta_text_section_header">Timing Constraints</h2>
+<TABLE  WIDTH="80%" border="1" ALIGN="center">
+ <TR>
+  <TH BGCOLOR="#FFFFCC" CLASS="cpldta_constraint_header">Constraint Name</TH>
+  <TH BGCOLOR="#FFFFCC" WIDTH="15%" CLASS="cpldta_time_header">Requirement (ns)</TH>
+  <TH BGCOLOR="#FFFFCC" WIDTH="15%" CLASS="cpldta_time_header">Delay (ns)</TH>
+  <TH BGCOLOR="#FFFFCC" WIDTH="15%" CLASS="cpldta_time_header">Paths</TH>
+  <TH BGCOLOR="#FFFFCC" WIDTH="15%" CLASS="cpldta_time_header">Paths Failing</TH>
+ </TR>
+ <TR>
+  <TD ALIGN="left" CLASS="cpldta_constraint_name"><A HREF="#TS1000">TS1000</A></TD>
+  <TD ALIGN="center" CLASS="cpldta_time_value">0.0</TD>
+  <TD ALIGN="center" CLASS="cpldta_time_value">0.0</TD>
+  <TD ALIGN="center" CLASS="cpldta_time_value">0</TD>
+  <TD ALIGN="center" CLASS="cpldta_time_value">0</TD>
+ </TR>
+ <TR>
+  <TD ALIGN="left" CLASS="cpldta_constraint_name"><A HREF="#TS1001">TS1001</A></TD>
+  <TD ALIGN="center" CLASS="cpldta_time_value">0.0</TD>
+  <TD ALIGN="center" CLASS="cpldta_time_value">0.0</TD>
+  <TD ALIGN="center" CLASS="cpldta_time_value">0</TD>
+  <TD ALIGN="center" CLASS="cpldta_time_value">0</TD>
+ </TR>
+ <TR>
+  <TD ALIGN="left" CLASS="cpldta_constraint_name"><A HREF="#TS1002">TS1002</A></TD>
+  <TD ALIGN="center" CLASS="cpldta_time_value">0.0</TD>
+  <TD ALIGN="center" CLASS="cpldta_time_value">0.0</TD>
+  <TD ALIGN="center" CLASS="cpldta_time_value">0</TD>
+  <TD ALIGN="center" CLASS="cpldta_time_value">0</TD>
+ </TR>
+ <TR>
+  <TD BGCOLOR="#FFCCCC" ALIGN="left" CLASS="cpldta_constraint_name_error"><A HREF="#AUTO_TS_F2F">AUTO_TS_F2F</A></TD>
+  <TD BGCOLOR="#FFCCCC" ALIGN="center" CLASS="cpldta_time_value_error">0.0</TD>
+  <TD BGCOLOR="#FFCCCC" ALIGN="center" CLASS="cpldta_time_value_error">11.4</TD>
+  <TD BGCOLOR="#FFCCCC" ALIGN="center" CLASS="cpldta_time_value_error">59</TD>
+  <TD BGCOLOR="#FFCCCC" ALIGN="center" CLASS="cpldta_time_value_error">59</TD>
+ </TR>
+ <TR>
+  <TD BGCOLOR="#FFCCCC" ALIGN="left" CLASS="cpldta_constraint_name_error"><A HREF="#AUTO_TS_P2P">AUTO_TS_P2P</A></TD>
+  <TD BGCOLOR="#FFCCCC" ALIGN="center" CLASS="cpldta_time_value_error">0.0</TD>
+  <TD BGCOLOR="#FFCCCC" ALIGN="center" CLASS="cpldta_time_value_error">17.9</TD>
+  <TD BGCOLOR="#FFCCCC" ALIGN="center" CLASS="cpldta_time_value_error">11</TD>
+  <TD BGCOLOR="#FFCCCC" ALIGN="center" CLASS="cpldta_time_value_error">11</TD>
+ </TR>
+ <TR>
+  <TD BGCOLOR="#FFCCCC" ALIGN="left" CLASS="cpldta_constraint_name_error"><A HREF="#AUTO_TS_P2F">AUTO_TS_P2F</A></TD>
+  <TD BGCOLOR="#FFCCCC" ALIGN="center" CLASS="cpldta_time_value_error">0.0</TD>
+  <TD BGCOLOR="#FFCCCC" ALIGN="center" CLASS="cpldta_time_value_error">13.9</TD>
+  <TD BGCOLOR="#FFCCCC" ALIGN="center" CLASS="cpldta_time_value_error">171</TD>
+  <TD BGCOLOR="#FFCCCC" ALIGN="center" CLASS="cpldta_time_value_error">171</TD>
+ </TR>
+ <TR>
+  <TD BGCOLOR="#FFCCCC" ALIGN="left" CLASS="cpldta_constraint_name_error"><A HREF="#AUTO_TS_F2P">AUTO_TS_F2P</A></TD>
+  <TD BGCOLOR="#FFCCCC" ALIGN="center" CLASS="cpldta_time_value_error">0.0</TD>
+  <TD BGCOLOR="#FFCCCC" ALIGN="center" CLASS="cpldta_time_value_error">4.0</TD>
+  <TD BGCOLOR="#FFCCCC" ALIGN="center" CLASS="cpldta_time_value_error">3</TD>
+  <TD BGCOLOR="#FFCCCC" ALIGN="center" CLASS="cpldta_time_value_error">3</TD>
+ </TR>
+</TABLE>
+</BR>
+</BR>
+<A NAME="TS1000">
+<h3 CLASS="cpldta_text_subsection_header">Constraint: TS1000</h3>
+ <TABLE  WIDTH="80%" border="1" ALIGN="center">
+  <CAPTION CLASS="cpldta_text_caption"><B>Description: PERIOD:PERIOD_C1:0.000 nS</B></CAPTION>
+  <TR CLASS="cpldta_delaytable_header">
+   <TH BGCOLOR="#FFFFCC" WIDTH="40%" CLASS="cpldta_constraint_header">Path</TH>
+   <TH BGCOLOR="#FFFFCC" WIDTH="20%" CLASS="cpldta_time_header">Requirement (ns)</TH>
+   <TH BGCOLOR="#FFFFCC" WIDTH="20%" CLASS="cpldta_time_header">Delay (ns)</TH>
+   <TH BGCOLOR="#FFFFCC" WIDTH="20%" CLASS="cpldta_time_header">Slack (ns)</TH>
+  </TR>
+ </TABLE>
+ </BR>
+ </BR>
+<A NAME="TS1001">
+<h3 CLASS="cpldta_text_subsection_header">Constraint: TS1001</h3>
+ <TABLE  WIDTH="80%" border="1" ALIGN="center">
+  <CAPTION CLASS="cpldta_text_caption"><B>Description: PERIOD:PERIOD_C3:0.000 nS</B></CAPTION>
+  <TR CLASS="cpldta_delaytable_header">
+   <TH BGCOLOR="#FFFFCC" WIDTH="40%" CLASS="cpldta_constraint_header">Path</TH>
+   <TH BGCOLOR="#FFFFCC" WIDTH="20%" CLASS="cpldta_time_header">Requirement (ns)</TH>
+   <TH BGCOLOR="#FFFFCC" WIDTH="20%" CLASS="cpldta_time_header">Delay (ns)</TH>
+   <TH BGCOLOR="#FFFFCC" WIDTH="20%" CLASS="cpldta_time_header">Slack (ns)</TH>
+  </TR>
+ </TABLE>
+ </BR>
+ </BR>
+<A NAME="TS1002">
+<h3 CLASS="cpldta_text_subsection_header">Constraint: TS1002</h3>
+ <TABLE  WIDTH="80%" border="1" ALIGN="center">
+  <CAPTION CLASS="cpldta_text_caption"><B>Description: PERIOD:PERIOD_AS:0.000 nS</B></CAPTION>
+  <TR CLASS="cpldta_delaytable_header">
+   <TH BGCOLOR="#FFFFCC" WIDTH="40%" CLASS="cpldta_constraint_header">Path</TH>
+   <TH BGCOLOR="#FFFFCC" WIDTH="20%" CLASS="cpldta_time_header">Requirement (ns)</TH>
+   <TH BGCOLOR="#FFFFCC" WIDTH="20%" CLASS="cpldta_time_header">Delay (ns)</TH>
+   <TH BGCOLOR="#FFFFCC" WIDTH="20%" CLASS="cpldta_time_header">Slack (ns)</TH>
+  </TR>
+ </TABLE>
+ </BR>
+ </BR>
+<A NAME="AUTO_TS_F2F">
+<h3 CLASS="cpldta_text_subsection_header">Constraint: AUTO_TS_F2F</h3>
+ <TABLE  WIDTH="80%" border="1" ALIGN="center">
+  <CAPTION CLASS="cpldta_text_caption"><B>Description: MAXDELAY:FROM:FFS(*):TO:FFS(*):0.000 nS</B></CAPTION>
+  <TR CLASS="cpldta_delaytable_header">
+   <TH BGCOLOR="#FFFFCC" WIDTH="40%" CLASS="cpldta_constraint_header">Path</TH>
+   <TH BGCOLOR="#FFFFCC" WIDTH="20%" CLASS="cpldta_time_header">Requirement (ns)</TH>
+   <TH BGCOLOR="#FFFFCC" WIDTH="20%" CLASS="cpldta_time_header">Delay (ns)</TH>
+   <TH BGCOLOR="#FFFFCC" WIDTH="20%" CLASS="cpldta_time_header">Slack (ns)</TH>
+  </TR>
+  <TR>
+   <A NAME="_IDE_BASEADR_4__Q_to_ide_D"></A>
+   <TD BGCOLOR="#FFCCCC" ALIGN="left" CLASS="cpldta_constraint_name_error" WIDTH="40%"><A HREF="javascript:AUTO_TS_F2F_IDE_BASEADR_4__Q_to_ide_D();">IDE_BASEADR<4>.Q to ide.D</A></TD>
+   <TD BGCOLOR="#FFCCCC" ALIGN="center" CLASS="cpldta_time_value_error" WIDTH="10%">0.000</TD>
+   <TD BGCOLOR="#FFCCCC" ALIGN="center" CLASS="cpldta_time_value_error" WIDTH="10%">11.400</TD>
+   <TD BGCOLOR="#FFCCCC" ALIGN="center" CLASS="cpldta_time_value_error" WIDTH="10%">-11.400</TD>
+  </TR>
+<SCRIPT language="JavaScript">
+<!--
+function AUTO_TS_F2F_IDE_BASEADR_4__Q_to_ide_D() {
+   aWindow=window.open("","thewindow","toolbar=no,WIDTH=350,height=300,status=no,scrollbars=yes,resizable=yes,menubar=no")
+   aWindow.document.writeln("<link type=\"text/css\" rel=\"stylesheet\" href=\"cpldta_style.css\">")
+   aWindow.document.writeln("<H3 CLASS=\"cpldta_text_subsection_header\">Path Trace: ")
+   aWindow.document.writeln("IDE_BASEADR<4>.Q to ide.D")
+   aWindow.document.writeln("</H3>")
+   aWindow.document.writeln("<TABLE  WIDTH=\"90%\" border=\"1\" ALIGN=\"center\">")
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+   aWindow.document.writeln("<TH BGCOLOR=\"#FFFFCC\" WIDTH=\"40%\" CLASS=\"cpldta_constraint_header\">Delay Type</TH>")
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+   aWindow.document.writeln("<TD WIDTH=\"40%\" CLASS=\"cpldta_datasheet_pathname\">IDE_BASEADR<4></TD>")
+   aWindow.document.writeln("<TR>")
+   aWindow.document.writeln("<TD WIDTH=\"40%\" CLASS=\"cpldta_datasheet_pathname\">tF + tLOGI + tPTA + tPTA2 + tSUI</TD>")
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+   aWindow.document.writeln("<TD WIDTH=\"40%\" CLASS=\"cpldta_datasheet_pathname\">ide.D</TD>")
+   aWindow.document.writeln("</TABLE>")
+   aWindow.document.close()
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+//-->
+</SCRIPT>
+  <TR>
+   <A NAME="_IDE_BASEADR_5__Q_to_ide_D"></A>
+   <TD BGCOLOR="#FFCCCC" ALIGN="left" CLASS="cpldta_constraint_name_error" WIDTH="40%"><A HREF="javascript:AUTO_TS_F2F_IDE_BASEADR_5__Q_to_ide_D();">IDE_BASEADR<5>.Q to ide.D</A></TD>
+   <TD BGCOLOR="#FFCCCC" ALIGN="center" CLASS="cpldta_time_value_error" WIDTH="10%">0.000</TD>
+   <TD BGCOLOR="#FFCCCC" ALIGN="center" CLASS="cpldta_time_value_error" WIDTH="10%">11.400</TD>
+   <TD BGCOLOR="#FFCCCC" ALIGN="center" CLASS="cpldta_time_value_error" WIDTH="10%">-11.400</TD>
+  </TR>
+<SCRIPT language="JavaScript">
+<!--
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+   aWindow.document.writeln("<link type=\"text/css\" rel=\"stylesheet\" href=\"cpldta_style.css\">")
+   aWindow.document.writeln("<H3 CLASS=\"cpldta_text_subsection_header\">Path Trace: ")
+   aWindow.document.writeln("IDE_BASEADR<5>.Q to ide.D")
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+   aWindow.document.writeln("<TABLE  WIDTH=\"90%\" border=\"1\" ALIGN=\"center\">")
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+   aWindow.document.writeln("<TH BGCOLOR=\"#FFFFCC\" WIDTH=\"40%\" CLASS=\"cpldta_constraint_header\">Delay Type</TH>")
+   aWindow.document.writeln("<TH BGCOLOR=\"#FFFFCC\" WIDTH=\"20%\" CLASS=\"cpldta_time_header\">Delay (ns)</TH>")
+   aWindow.document.writeln("<TH BGCOLOR=\"#FFFFCC\" WIDTH=\"40%\" CLASS=\"cpldta_constraint_header\">Logical Resource</TH>")
+   aWindow.document.writeln("</TR>")
+   aWindow.document.writeln("<TR>")
+   aWindow.document.writeln("<TD WIDTH=\"40%\" CLASS=\"cpldta_datasheet_pathname\">tCOI</TD>")
+   aWindow.document.writeln("<TD WIDTH=\"20%\" CLASS=\"cpldta_datasheet_time_value\">1.000</TD>")
+   aWindow.document.writeln("<TD WIDTH=\"40%\" CLASS=\"cpldta_datasheet_pathname\">IDE_BASEADR<5></TD>")
+   aWindow.document.writeln("<TR>")
+   aWindow.document.writeln("<TD WIDTH=\"40%\" CLASS=\"cpldta_datasheet_pathname\">tF + tLOGI + tPTA + tPTA2 + tSUI</TD>")
+   aWindow.document.writeln("<TD WIDTH=\"20%\" CLASS=\"cpldta_datasheet_time_value\">10.400</TD>")
+   aWindow.document.writeln("<TD WIDTH=\"40%\" CLASS=\"cpldta_datasheet_pathname\">ide.D</TD>")
+   aWindow.document.writeln("</TABLE>")
+   aWindow.document.close()
+}
+//-->
+</SCRIPT>
+  <TR>
+   <A NAME="_IDE_BASEADR_0__Q_to_ide_D"></A>
+   <TD BGCOLOR="#FFCCCC" ALIGN="left" CLASS="cpldta_constraint_name_error" WIDTH="40%"><A HREF="javascript:AUTO_TS_F2F_IDE_BASEADR_0__Q_to_ide_D();">IDE_BASEADR<0>.Q to ide.D</A></TD>
+   <TD BGCOLOR="#FFCCCC" ALIGN="center" CLASS="cpldta_time_value_error" WIDTH="10%">0.000</TD>
+   <TD BGCOLOR="#FFCCCC" ALIGN="center" CLASS="cpldta_time_value_error" WIDTH="10%">11.000</TD>
+   <TD BGCOLOR="#FFCCCC" ALIGN="center" CLASS="cpldta_time_value_error" WIDTH="10%">-11.000</TD>
+  </TR>
+<SCRIPT language="JavaScript">
+<!--
+function AUTO_TS_F2F_IDE_BASEADR_0__Q_to_ide_D() {
+   aWindow=window.open("","thewindow","toolbar=no,WIDTH=350,height=300,status=no,scrollbars=yes,resizable=yes,menubar=no")
+   aWindow.document.writeln("<link type=\"text/css\" rel=\"stylesheet\" href=\"cpldta_style.css\">")
+   aWindow.document.writeln("<H3 CLASS=\"cpldta_text_subsection_header\">Path Trace: ")
+   aWindow.document.writeln("IDE_BASEADR<0>.Q to ide.D")
+   aWindow.document.writeln("</H3>")
+   aWindow.document.writeln("<TABLE  WIDTH=\"90%\" border=\"1\" ALIGN=\"center\">")
+   aWindow.document.writeln("<TR>")
+   aWindow.document.writeln("<TH BGCOLOR=\"#FFFFCC\" WIDTH=\"40%\" CLASS=\"cpldta_constraint_header\">Delay Type</TH>")
+   aWindow.document.writeln("<TH BGCOLOR=\"#FFFFCC\" WIDTH=\"20%\" CLASS=\"cpldta_time_header\">Delay (ns)</TH>")
+   aWindow.document.writeln("<TH BGCOLOR=\"#FFFFCC\" WIDTH=\"40%\" CLASS=\"cpldta_constraint_header\">Logical Resource</TH>")
+   aWindow.document.writeln("</TR>")
+   aWindow.document.writeln("<TR>")
+   aWindow.document.writeln("<TD WIDTH=\"40%\" CLASS=\"cpldta_datasheet_pathname\">tCOI</TD>")
+   aWindow.document.writeln("<TD WIDTH=\"20%\" CLASS=\"cpldta_datasheet_time_value\">1.000</TD>")
+   aWindow.document.writeln("<TD WIDTH=\"40%\" CLASS=\"cpldta_datasheet_pathname\">IDE_BASEADR<0></TD>")
+   aWindow.document.writeln("<TR>")
+   aWindow.document.writeln("<TD WIDTH=\"40%\" CLASS=\"cpldta_datasheet_pathname\">tF + tLOGI + tPTA + tSUI</TD>")
+   aWindow.document.writeln("<TD WIDTH=\"20%\" CLASS=\"cpldta_datasheet_time_value\">10.000</TD>")
+   aWindow.document.writeln("<TD WIDTH=\"40%\" CLASS=\"cpldta_datasheet_pathname\">ide.D</TD>")
+   aWindow.document.writeln("</TABLE>")
+   aWindow.document.close()
+}
+//-->
+</SCRIPT>
+ </TABLE>
+ </BR>
+ </BR>
+<A NAME="AUTO_TS_P2P">
+<h3 CLASS="cpldta_text_subsection_header">Constraint: AUTO_TS_P2P</h3>
+ <TABLE  WIDTH="80%" border="1" ALIGN="center">
+  <CAPTION CLASS="cpldta_text_caption"><B>Description: MAXDELAY:FROM:PADS(*):TO:PADS(*):0.000 nS</B></CAPTION>
+  <TR CLASS="cpldta_delaytable_header">
+   <TH BGCOLOR="#FFFFCC" WIDTH="40%" CLASS="cpldta_constraint_header">Path</TH>
+   <TH BGCOLOR="#FFFFCC" WIDTH="20%" CLASS="cpldta_time_header">Requirement (ns)</TH>
+   <TH BGCOLOR="#FFFFCC" WIDTH="20%" CLASS="cpldta_time_header">Delay (ns)</TH>
+   <TH BGCOLOR="#FFFFCC" WIDTH="20%" CLASS="cpldta_time_header">Slack (ns)</TH>
+  </TR>
+  <TR>
+   <A NAME="_C1_to_IDE_R"></A>
+   <TD BGCOLOR="#FFCCCC" ALIGN="left" CLASS="cpldta_constraint_name_error" WIDTH="40%"><A HREF="javascript:AUTO_TS_P2P_C1_to_IDE_R();">C1 to IDE_R</A></TD>
+   <TD BGCOLOR="#FFCCCC" ALIGN="center" CLASS="cpldta_time_value_error" WIDTH="10%">0.000</TD>
+   <TD BGCOLOR="#FFCCCC" ALIGN="center" CLASS="cpldta_time_value_error" WIDTH="10%">17.900</TD>
+   <TD BGCOLOR="#FFCCCC" ALIGN="center" CLASS="cpldta_time_value_error" WIDTH="10%">-17.900</TD>
+  </TR>
+<SCRIPT language="JavaScript">
+<!--
+function AUTO_TS_P2P_C1_to_IDE_R() {
+   aWindow=window.open("","thewindow","toolbar=no,WIDTH=350,height=300,status=no,scrollbars=yes,resizable=yes,menubar=no")
+   aWindow.document.writeln("<link type=\"text/css\" rel=\"stylesheet\" href=\"cpldta_style.css\">")
+   aWindow.document.writeln("<H3 CLASS=\"cpldta_text_subsection_header\">Path Trace: ")
+   aWindow.document.writeln("C1 to IDE_R")
+   aWindow.document.writeln("</H3>")
+   aWindow.document.writeln("<TABLE  WIDTH=\"90%\" border=\"1\" ALIGN=\"center\">")
+   aWindow.document.writeln("<TR>")
+   aWindow.document.writeln("<TH BGCOLOR=\"#FFFFCC\" WIDTH=\"40%\" CLASS=\"cpldta_constraint_header\">Delay Type</TH>")
+   aWindow.document.writeln("<TH BGCOLOR=\"#FFFFCC\" WIDTH=\"20%\" CLASS=\"cpldta_time_header\">Delay (ns)</TH>")
+   aWindow.document.writeln("<TH BGCOLOR=\"#FFFFCC\" WIDTH=\"40%\" CLASS=\"cpldta_constraint_header\">Logical Resource</TH>")
+   aWindow.document.writeln("</TR>")
+   aWindow.document.writeln("<TR>")
+   aWindow.document.writeln("<TD WIDTH=\"40%\" CLASS=\"cpldta_datasheet_pathname\">-</TD>")
+   aWindow.document.writeln("<TD WIDTH=\"20%\" CLASS=\"cpldta_datasheet_time_value\">0.000</TD>")
+   aWindow.document.writeln("<TD WIDTH=\"40%\" CLASS=\"cpldta_datasheet_pathname\">C1</TD>")
+   aWindow.document.writeln("<TR>")
+   aWindow.document.writeln("<TD WIDTH=\"40%\" CLASS=\"cpldta_datasheet_pathname\">tIN</TD>")
+   aWindow.document.writeln("<TD WIDTH=\"20%\" CLASS=\"cpldta_datasheet_time_value\">3.500</TD>")
+   aWindow.document.writeln("<TD WIDTH=\"40%\" CLASS=\"cpldta_datasheet_pathname\">C1_IBUF</TD>")
+   aWindow.document.writeln("<TR>")
+   aWindow.document.writeln("<TD WIDTH=\"40%\" CLASS=\"cpldta_datasheet_pathname\">tLOGI + tPDI</TD>")
+   aWindow.document.writeln("<TD WIDTH=\"20%\" CLASS=\"cpldta_datasheet_time_value\">3.500</TD>")
+   aWindow.document.writeln("<TD WIDTH=\"40%\" CLASS=\"cpldta_datasheet_pathname\">ide/ide_CLKF.UIM</TD>")
+   aWindow.document.writeln("<TR>")
+   aWindow.document.writeln("<TD WIDTH=\"40%\" CLASS=\"cpldta_datasheet_pathname\">tF + tPTCK + tCOI</TD>")
+   aWindow.document.writeln("<TD WIDTH=\"20%\" CLASS=\"cpldta_datasheet_time_value\">7.900</TD>")
+   aWindow.document.writeln("<TD WIDTH=\"40%\" CLASS=\"cpldta_datasheet_pathname\">IDE_R</TD>")
+   aWindow.document.writeln("<TR>")
+   aWindow.document.writeln("<TD WIDTH=\"40%\" CLASS=\"cpldta_datasheet_pathname\">tOUT</TD>")
+   aWindow.document.writeln("<TD WIDTH=\"20%\" CLASS=\"cpldta_datasheet_time_value\">3.000</TD>")
+   aWindow.document.writeln("<TD WIDTH=\"40%\" CLASS=\"cpldta_datasheet_pathname\">IDE_R</TD>")
+   aWindow.document.writeln("</TABLE>")
+   aWindow.document.close()
+}
+//-->
+</SCRIPT>
+  <TR>
+   <A NAME="_C1_to_IDE_W"></A>
+   <TD BGCOLOR="#FFCCCC" ALIGN="left" CLASS="cpldta_constraint_name_error" WIDTH="40%"><A HREF="javascript:AUTO_TS_P2P_C1_to_IDE_W();">C1 to IDE_W</A></TD>
+   <TD BGCOLOR="#FFCCCC" ALIGN="center" CLASS="cpldta_time_value_error" WIDTH="10%">0.000</TD>
+   <TD BGCOLOR="#FFCCCC" ALIGN="center" CLASS="cpldta_time_value_error" WIDTH="10%">17.900</TD>
+   <TD BGCOLOR="#FFCCCC" ALIGN="center" CLASS="cpldta_time_value_error" WIDTH="10%">-17.900</TD>
+  </TR>
+<SCRIPT language="JavaScript">
+<!--
+function AUTO_TS_P2P_C1_to_IDE_W() {
+   aWindow=window.open("","thewindow","toolbar=no,WIDTH=350,height=300,status=no,scrollbars=yes,resizable=yes,menubar=no")
+   aWindow.document.writeln("<link type=\"text/css\" rel=\"stylesheet\" href=\"cpldta_style.css\">")
+   aWindow.document.writeln("<H3 CLASS=\"cpldta_text_subsection_header\">Path Trace: ")
+   aWindow.document.writeln("C1 to IDE_W")
+   aWindow.document.writeln("</H3>")
+   aWindow.document.writeln("<TABLE  WIDTH=\"90%\" border=\"1\" ALIGN=\"center\">")
+   aWindow.document.writeln("<TR>")
+   aWindow.document.writeln("<TH BGCOLOR=\"#FFFFCC\" WIDTH=\"40%\" CLASS=\"cpldta_constraint_header\">Delay Type</TH>")
+   aWindow.document.writeln("<TH BGCOLOR=\"#FFFFCC\" WIDTH=\"20%\" CLASS=\"cpldta_time_header\">Delay (ns)</TH>")
+   aWindow.document.writeln("<TH BGCOLOR=\"#FFFFCC\" WIDTH=\"40%\" CLASS=\"cpldta_constraint_header\">Logical Resource</TH>")
+   aWindow.document.writeln("</TR>")
+   aWindow.document.writeln("<TR>")
+   aWindow.document.writeln("<TD WIDTH=\"40%\" CLASS=\"cpldta_datasheet_pathname\">-</TD>")
+   aWindow.document.writeln("<TD WIDTH=\"20%\" CLASS=\"cpldta_datasheet_time_value\">0.000</TD>")
+   aWindow.document.writeln("<TD WIDTH=\"40%\" CLASS=\"cpldta_datasheet_pathname\">C1</TD>")
+   aWindow.document.writeln("<TR>")
+   aWindow.document.writeln("<TD WIDTH=\"40%\" CLASS=\"cpldta_datasheet_pathname\">tIN</TD>")
+   aWindow.document.writeln("<TD WIDTH=\"20%\" CLASS=\"cpldta_datasheet_time_value\">3.500</TD>")
+   aWindow.document.writeln("<TD WIDTH=\"40%\" CLASS=\"cpldta_datasheet_pathname\">C1_IBUF</TD>")
+   aWindow.document.writeln("<TR>")
+   aWindow.document.writeln("<TD WIDTH=\"40%\" CLASS=\"cpldta_datasheet_pathname\">tLOGI + tPDI</TD>")
+   aWindow.document.writeln("<TD WIDTH=\"20%\" CLASS=\"cpldta_datasheet_time_value\">3.500</TD>")
+   aWindow.document.writeln("<TD WIDTH=\"40%\" CLASS=\"cpldta_datasheet_pathname\">ide/ide_CLKF.UIM</TD>")
+   aWindow.document.writeln("<TR>")
+   aWindow.document.writeln("<TD WIDTH=\"40%\" CLASS=\"cpldta_datasheet_pathname\">tF + tPTCK + tCOI</TD>")
+   aWindow.document.writeln("<TD WIDTH=\"20%\" CLASS=\"cpldta_datasheet_time_value\">7.900</TD>")
+   aWindow.document.writeln("<TD WIDTH=\"40%\" CLASS=\"cpldta_datasheet_pathname\">IDE_W</TD>")
+   aWindow.document.writeln("<TR>")
+   aWindow.document.writeln("<TD WIDTH=\"40%\" CLASS=\"cpldta_datasheet_pathname\">tOUT</TD>")
+   aWindow.document.writeln("<TD WIDTH=\"20%\" CLASS=\"cpldta_datasheet_time_value\">3.000</TD>")
+   aWindow.document.writeln("<TD WIDTH=\"40%\" CLASS=\"cpldta_datasheet_pathname\">IDE_W</TD>")
+   aWindow.document.writeln("</TABLE>")
+   aWindow.document.close()
+}
+//-->
+</SCRIPT>
+  <TR>
+   <A NAME="_C1_to_ROM_OE"></A>
+   <TD BGCOLOR="#FFCCCC" ALIGN="left" CLASS="cpldta_constraint_name_error" WIDTH="40%"><A HREF="javascript:AUTO_TS_P2P_C1_to_ROM_OE();">C1 to ROM_OE</A></TD>
+   <TD BGCOLOR="#FFCCCC" ALIGN="center" CLASS="cpldta_time_value_error" WIDTH="10%">0.000</TD>
+   <TD BGCOLOR="#FFCCCC" ALIGN="center" CLASS="cpldta_time_value_error" WIDTH="10%">17.900</TD>
+   <TD BGCOLOR="#FFCCCC" ALIGN="center" CLASS="cpldta_time_value_error" WIDTH="10%">-17.900</TD>
+  </TR>
+<SCRIPT language="JavaScript">
+<!--
+function AUTO_TS_P2P_C1_to_ROM_OE() {
+   aWindow=window.open("","thewindow","toolbar=no,WIDTH=350,height=300,status=no,scrollbars=yes,resizable=yes,menubar=no")
+   aWindow.document.writeln("<link type=\"text/css\" rel=\"stylesheet\" href=\"cpldta_style.css\">")
+   aWindow.document.writeln("<H3 CLASS=\"cpldta_text_subsection_header\">Path Trace: ")
+   aWindow.document.writeln("C1 to ROM_OE")
+   aWindow.document.writeln("</H3>")
+   aWindow.document.writeln("<TABLE  WIDTH=\"90%\" border=\"1\" ALIGN=\"center\">")
+   aWindow.document.writeln("<TR>")
+   aWindow.document.writeln("<TH BGCOLOR=\"#FFFFCC\" WIDTH=\"40%\" CLASS=\"cpldta_constraint_header\">Delay Type</TH>")
+   aWindow.document.writeln("<TH BGCOLOR=\"#FFFFCC\" WIDTH=\"20%\" CLASS=\"cpldta_time_header\">Delay (ns)</TH>")
+   aWindow.document.writeln("<TH BGCOLOR=\"#FFFFCC\" WIDTH=\"40%\" CLASS=\"cpldta_constraint_header\">Logical Resource</TH>")
+   aWindow.document.writeln("</TR>")
+   aWindow.document.writeln("<TR>")
+   aWindow.document.writeln("<TD WIDTH=\"40%\" CLASS=\"cpldta_datasheet_pathname\">-</TD>")
+   aWindow.document.writeln("<TD WIDTH=\"20%\" CLASS=\"cpldta_datasheet_time_value\">0.000</TD>")
+   aWindow.document.writeln("<TD WIDTH=\"40%\" CLASS=\"cpldta_datasheet_pathname\">C1</TD>")
+   aWindow.document.writeln("<TR>")
+   aWindow.document.writeln("<TD WIDTH=\"40%\" CLASS=\"cpldta_datasheet_pathname\">tIN</TD>")
+   aWindow.document.writeln("<TD WIDTH=\"20%\" CLASS=\"cpldta_datasheet_time_value\">3.500</TD>")
+   aWindow.document.writeln("<TD WIDTH=\"40%\" CLASS=\"cpldta_datasheet_pathname\">C1_IBUF</TD>")
+   aWindow.document.writeln("<TR>")
+   aWindow.document.writeln("<TD WIDTH=\"40%\" CLASS=\"cpldta_datasheet_pathname\">tLOGI + tPDI</TD>")
+   aWindow.document.writeln("<TD WIDTH=\"20%\" CLASS=\"cpldta_datasheet_time_value\">3.500</TD>")
+   aWindow.document.writeln("<TD WIDTH=\"40%\" CLASS=\"cpldta_datasheet_pathname\">ide/ide_CLKF.UIM</TD>")
+   aWindow.document.writeln("<TR>")
+   aWindow.document.writeln("<TD WIDTH=\"40%\" CLASS=\"cpldta_datasheet_pathname\">tF + tPTCK + tCOI</TD>")
+   aWindow.document.writeln("<TD WIDTH=\"20%\" CLASS=\"cpldta_datasheet_time_value\">7.900</TD>")
+   aWindow.document.writeln("<TD WIDTH=\"40%\" CLASS=\"cpldta_datasheet_pathname\">ROM_OE</TD>")
+   aWindow.document.writeln("<TR>")
+   aWindow.document.writeln("<TD WIDTH=\"40%\" CLASS=\"cpldta_datasheet_pathname\">tOUT</TD>")
+   aWindow.document.writeln("<TD WIDTH=\"20%\" CLASS=\"cpldta_datasheet_time_value\">3.000</TD>")
+   aWindow.document.writeln("<TD WIDTH=\"40%\" CLASS=\"cpldta_datasheet_pathname\">ROM_OE</TD>")
+   aWindow.document.writeln("</TABLE>")
+   aWindow.document.close()
+}
+//-->
+</SCRIPT>
+ </TABLE>
+ </BR>
+ </BR>
+<A NAME="AUTO_TS_P2F">
+<h3 CLASS="cpldta_text_subsection_header">Constraint: AUTO_TS_P2F</h3>
+ <TABLE  WIDTH="80%" border="1" ALIGN="center">
+  <CAPTION CLASS="cpldta_text_caption"><B>Description: MAXDELAY:FROM:PADS(*):TO:FFS(*):0.000 nS</B></CAPTION>
+  <TR CLASS="cpldta_delaytable_header">
+   <TH BGCOLOR="#FFFFCC" WIDTH="40%" CLASS="cpldta_constraint_header">Path</TH>
+   <TH BGCOLOR="#FFFFCC" WIDTH="20%" CLASS="cpldta_time_header">Requirement (ns)</TH>
+   <TH BGCOLOR="#FFFFCC" WIDTH="20%" CLASS="cpldta_time_header">Delay (ns)</TH>
+   <TH BGCOLOR="#FFFFCC" WIDTH="20%" CLASS="cpldta_time_header">Slack (ns)</TH>
+  </TR>
+  <TR>
+   <A NAME="_C1_to_AUTO_CONFIG_DONE_CYCLE_1__CLKF"></A>
+   <TD BGCOLOR="#FFCCCC" ALIGN="left" CLASS="cpldta_constraint_name_error" WIDTH="40%"><A HREF="javascript:AUTO_TS_P2F_C1_to_AUTO_CONFIG_DONE_CYCLE_1__CLKF();">C1 to AUTO_CONFIG_DONE_CYCLE<1>.CLKF</A></TD>
+   <TD BGCOLOR="#FFCCCC" ALIGN="center" CLASS="cpldta_time_value_error" WIDTH="10%">0.000</TD>
+   <TD BGCOLOR="#FFCCCC" ALIGN="center" CLASS="cpldta_time_value_error" WIDTH="10%">13.900</TD>
+   <TD BGCOLOR="#FFCCCC" ALIGN="center" CLASS="cpldta_time_value_error" WIDTH="10%">-13.900</TD>
+  </TR>
+<SCRIPT language="JavaScript">
+<!--
+function AUTO_TS_P2F_C1_to_AUTO_CONFIG_DONE_CYCLE_1__CLKF() {
+   aWindow=window.open("","thewindow","toolbar=no,WIDTH=350,height=300,status=no,scrollbars=yes,resizable=yes,menubar=no")
+   aWindow.document.writeln("<link type=\"text/css\" rel=\"stylesheet\" href=\"cpldta_style.css\">")
+   aWindow.document.writeln("<H3 CLASS=\"cpldta_text_subsection_header\">Path Trace: ")
+   aWindow.document.writeln("C1 to AUTO_CONFIG_DONE_CYCLE<1>.CLKF")
+   aWindow.document.writeln("</H3>")
+   aWindow.document.writeln("<TABLE  WIDTH=\"90%\" border=\"1\" ALIGN=\"center\">")
+   aWindow.document.writeln("<TR>")
+   aWindow.document.writeln("<TH BGCOLOR=\"#FFFFCC\" WIDTH=\"40%\" CLASS=\"cpldta_constraint_header\">Delay Type</TH>")
+   aWindow.document.writeln("<TH BGCOLOR=\"#FFFFCC\" WIDTH=\"20%\" CLASS=\"cpldta_time_header\">Delay (ns)</TH>")
+   aWindow.document.writeln("<TH BGCOLOR=\"#FFFFCC\" WIDTH=\"40%\" CLASS=\"cpldta_constraint_header\">Logical Resource</TH>")
+   aWindow.document.writeln("</TR>")
+   aWindow.document.writeln("<TR>")
+   aWindow.document.writeln("<TD WIDTH=\"40%\" CLASS=\"cpldta_datasheet_pathname\">-</TD>")
+   aWindow.document.writeln("<TD WIDTH=\"20%\" CLASS=\"cpldta_datasheet_time_value\">0.000</TD>")
+   aWindow.document.writeln("<TD WIDTH=\"40%\" CLASS=\"cpldta_datasheet_pathname\">C1</TD>")
+   aWindow.document.writeln("<TR>")
+   aWindow.document.writeln("<TD WIDTH=\"40%\" CLASS=\"cpldta_datasheet_pathname\">tIN</TD>")
+   aWindow.document.writeln("<TD WIDTH=\"20%\" CLASS=\"cpldta_datasheet_time_value\">3.500</TD>")
+   aWindow.document.writeln("<TD WIDTH=\"40%\" CLASS=\"cpldta_datasheet_pathname\">C1_IBUF</TD>")
+   aWindow.document.writeln("<TR>")
+   aWindow.document.writeln("<TD WIDTH=\"40%\" CLASS=\"cpldta_datasheet_pathname\">tLOGI + tPDI</TD>")
+   aWindow.document.writeln("<TD WIDTH=\"20%\" CLASS=\"cpldta_datasheet_time_value\">3.500</TD>")
+   aWindow.document.writeln("<TD WIDTH=\"40%\" CLASS=\"cpldta_datasheet_pathname\">ide/ide_CLKF.UIM</TD>")
+   aWindow.document.writeln("<TR>")
+   aWindow.document.writeln("<TD WIDTH=\"40%\" CLASS=\"cpldta_datasheet_pathname\">tF + tPTCK</TD>")
+   aWindow.document.writeln("<TD WIDTH=\"20%\" CLASS=\"cpldta_datasheet_time_value\">6.900</TD>")
+   aWindow.document.writeln("<TD WIDTH=\"40%\" CLASS=\"cpldta_datasheet_pathname\">AUTO_CONFIG_DONE_CYCLE<1>.CLKF</TD>")
+   aWindow.document.writeln("</TABLE>")
+   aWindow.document.close()
+}
+//-->
+</SCRIPT>
+  <TR>
+   <A NAME="_C1_to_IDE_BASEADR_0__CLKF"></A>
+   <TD BGCOLOR="#FFCCCC" ALIGN="left" CLASS="cpldta_constraint_name_error" WIDTH="40%"><A HREF="javascript:AUTO_TS_P2F_C1_to_IDE_BASEADR_0__CLKF();">C1 to IDE_BASEADR<0>.CLKF</A></TD>
+   <TD BGCOLOR="#FFCCCC" ALIGN="center" CLASS="cpldta_time_value_error" WIDTH="10%">0.000</TD>
+   <TD BGCOLOR="#FFCCCC" ALIGN="center" CLASS="cpldta_time_value_error" WIDTH="10%">13.900</TD>
+   <TD BGCOLOR="#FFCCCC" ALIGN="center" CLASS="cpldta_time_value_error" WIDTH="10%">-13.900</TD>
+  </TR>
+<SCRIPT language="JavaScript">
+<!--
+function AUTO_TS_P2F_C1_to_IDE_BASEADR_0__CLKF() {
+   aWindow=window.open("","thewindow","toolbar=no,WIDTH=350,height=300,status=no,scrollbars=yes,resizable=yes,menubar=no")
+   aWindow.document.writeln("<link type=\"text/css\" rel=\"stylesheet\" href=\"cpldta_style.css\">")
+   aWindow.document.writeln("<H3 CLASS=\"cpldta_text_subsection_header\">Path Trace: ")
+   aWindow.document.writeln("C1 to IDE_BASEADR<0>.CLKF")
+   aWindow.document.writeln("</H3>")
+   aWindow.document.writeln("<TABLE  WIDTH=\"90%\" border=\"1\" ALIGN=\"center\">")
+   aWindow.document.writeln("<TR>")
+   aWindow.document.writeln("<TH BGCOLOR=\"#FFFFCC\" WIDTH=\"40%\" CLASS=\"cpldta_constraint_header\">Delay Type</TH>")
+   aWindow.document.writeln("<TH BGCOLOR=\"#FFFFCC\" WIDTH=\"20%\" CLASS=\"cpldta_time_header\">Delay (ns)</TH>")
+   aWindow.document.writeln("<TH BGCOLOR=\"#FFFFCC\" WIDTH=\"40%\" CLASS=\"cpldta_constraint_header\">Logical Resource</TH>")
+   aWindow.document.writeln("</TR>")
+   aWindow.document.writeln("<TR>")
+   aWindow.document.writeln("<TD WIDTH=\"40%\" CLASS=\"cpldta_datasheet_pathname\">-</TD>")
+   aWindow.document.writeln("<TD WIDTH=\"20%\" CLASS=\"cpldta_datasheet_time_value\">0.000</TD>")
+   aWindow.document.writeln("<TD WIDTH=\"40%\" CLASS=\"cpldta_datasheet_pathname\">C1</TD>")
+   aWindow.document.writeln("<TR>")
+   aWindow.document.writeln("<TD WIDTH=\"40%\" CLASS=\"cpldta_datasheet_pathname\">tIN</TD>")
+   aWindow.document.writeln("<TD WIDTH=\"20%\" CLASS=\"cpldta_datasheet_time_value\">3.500</TD>")
+   aWindow.document.writeln("<TD WIDTH=\"40%\" CLASS=\"cpldta_datasheet_pathname\">C1_IBUF</TD>")
+   aWindow.document.writeln("<TR>")
+   aWindow.document.writeln("<TD WIDTH=\"40%\" CLASS=\"cpldta_datasheet_pathname\">tLOGI + tPDI</TD>")
+   aWindow.document.writeln("<TD WIDTH=\"20%\" CLASS=\"cpldta_datasheet_time_value\">3.500</TD>")
+   aWindow.document.writeln("<TD WIDTH=\"40%\" CLASS=\"cpldta_datasheet_pathname\">ide/ide_CLKF.UIM</TD>")
+   aWindow.document.writeln("<TR>")
+   aWindow.document.writeln("<TD WIDTH=\"40%\" CLASS=\"cpldta_datasheet_pathname\">tF + tPTCK</TD>")
+   aWindow.document.writeln("<TD WIDTH=\"20%\" CLASS=\"cpldta_datasheet_time_value\">6.900</TD>")
+   aWindow.document.writeln("<TD WIDTH=\"40%\" CLASS=\"cpldta_datasheet_pathname\">IDE_BASEADR<0>.CLKF</TD>")
+   aWindow.document.writeln("</TABLE>")
+   aWindow.document.close()
+}
+//-->
+</SCRIPT>
+  <TR>
+   <A NAME="_C1_to_IDE_BASEADR_1__CLKF"></A>
+   <TD BGCOLOR="#FFCCCC" ALIGN="left" CLASS="cpldta_constraint_name_error" WIDTH="40%"><A HREF="javascript:AUTO_TS_P2F_C1_to_IDE_BASEADR_1__CLKF();">C1 to IDE_BASEADR<1>.CLKF</A></TD>
+   <TD BGCOLOR="#FFCCCC" ALIGN="center" CLASS="cpldta_time_value_error" WIDTH="10%">0.000</TD>
+   <TD BGCOLOR="#FFCCCC" ALIGN="center" CLASS="cpldta_time_value_error" WIDTH="10%">13.900</TD>
+   <TD BGCOLOR="#FFCCCC" ALIGN="center" CLASS="cpldta_time_value_error" WIDTH="10%">-13.900</TD>
+  </TR>
+<SCRIPT language="JavaScript">
+<!--
+function AUTO_TS_P2F_C1_to_IDE_BASEADR_1__CLKF() {
+   aWindow=window.open("","thewindow","toolbar=no,WIDTH=350,height=300,status=no,scrollbars=yes,resizable=yes,menubar=no")
+   aWindow.document.writeln("<link type=\"text/css\" rel=\"stylesheet\" href=\"cpldta_style.css\">")
+   aWindow.document.writeln("<H3 CLASS=\"cpldta_text_subsection_header\">Path Trace: ")
+   aWindow.document.writeln("C1 to IDE_BASEADR<1>.CLKF")
+   aWindow.document.writeln("</H3>")
+   aWindow.document.writeln("<TABLE  WIDTH=\"90%\" border=\"1\" ALIGN=\"center\">")
+   aWindow.document.writeln("<TR>")
+   aWindow.document.writeln("<TH BGCOLOR=\"#FFFFCC\" WIDTH=\"40%\" CLASS=\"cpldta_constraint_header\">Delay Type</TH>")
+   aWindow.document.writeln("<TH BGCOLOR=\"#FFFFCC\" WIDTH=\"20%\" CLASS=\"cpldta_time_header\">Delay (ns)</TH>")
+   aWindow.document.writeln("<TH BGCOLOR=\"#FFFFCC\" WIDTH=\"40%\" CLASS=\"cpldta_constraint_header\">Logical Resource</TH>")
+   aWindow.document.writeln("</TR>")
+   aWindow.document.writeln("<TR>")
+   aWindow.document.writeln("<TD WIDTH=\"40%\" CLASS=\"cpldta_datasheet_pathname\">-</TD>")
+   aWindow.document.writeln("<TD WIDTH=\"20%\" CLASS=\"cpldta_datasheet_time_value\">0.000</TD>")
+   aWindow.document.writeln("<TD WIDTH=\"40%\" CLASS=\"cpldta_datasheet_pathname\">C1</TD>")
+   aWindow.document.writeln("<TR>")
+   aWindow.document.writeln("<TD WIDTH=\"40%\" CLASS=\"cpldta_datasheet_pathname\">tIN</TD>")
+   aWindow.document.writeln("<TD WIDTH=\"20%\" CLASS=\"cpldta_datasheet_time_value\">3.500</TD>")
+   aWindow.document.writeln("<TD WIDTH=\"40%\" CLASS=\"cpldta_datasheet_pathname\">C1_IBUF</TD>")
+   aWindow.document.writeln("<TR>")
+   aWindow.document.writeln("<TD WIDTH=\"40%\" CLASS=\"cpldta_datasheet_pathname\">tLOGI + tPDI</TD>")
+   aWindow.document.writeln("<TD WIDTH=\"20%\" CLASS=\"cpldta_datasheet_time_value\">3.500</TD>")
+   aWindow.document.writeln("<TD WIDTH=\"40%\" CLASS=\"cpldta_datasheet_pathname\">ide/ide_CLKF.UIM</TD>")
+   aWindow.document.writeln("<TR>")
+   aWindow.document.writeln("<TD WIDTH=\"40%\" CLASS=\"cpldta_datasheet_pathname\">tF + tPTCK</TD>")
+   aWindow.document.writeln("<TD WIDTH=\"20%\" CLASS=\"cpldta_datasheet_time_value\">6.900</TD>")
+   aWindow.document.writeln("<TD WIDTH=\"40%\" CLASS=\"cpldta_datasheet_pathname\">IDE_BASEADR<1>.CLKF</TD>")
+   aWindow.document.writeln("</TABLE>")
+   aWindow.document.close()
+}
+//-->
+</SCRIPT>
+ </TABLE>
+ </BR>
+ </BR>
+<A NAME="AUTO_TS_F2P">
+<h3 CLASS="cpldta_text_subsection_header">Constraint: AUTO_TS_F2P</h3>
+ <TABLE  WIDTH="80%" border="1" ALIGN="center">
+  <CAPTION CLASS="cpldta_text_caption"><B>Description: MAXDELAY:FROM:FFS(*):TO:PADS(*):0.000 nS</B></CAPTION>
+  <TR CLASS="cpldta_delaytable_header">
+   <TH BGCOLOR="#FFFFCC" WIDTH="40%" CLASS="cpldta_constraint_header">Path</TH>
+   <TH BGCOLOR="#FFFFCC" WIDTH="20%" CLASS="cpldta_time_header">Requirement (ns)</TH>
+   <TH BGCOLOR="#FFFFCC" WIDTH="20%" CLASS="cpldta_time_header">Delay (ns)</TH>
+   <TH BGCOLOR="#FFFFCC" WIDTH="20%" CLASS="cpldta_time_header">Slack (ns)</TH>
+  </TR>
+  <TR>
+   <A NAME="_IDE_R_Q_to_IDE_R"></A>
+   <TD BGCOLOR="#FFCCCC" ALIGN="left" CLASS="cpldta_constraint_name_error" WIDTH="40%"><A HREF="javascript:AUTO_TS_F2P_IDE_R_Q_to_IDE_R();">IDE_R.Q to IDE_R</A></TD>
+   <TD BGCOLOR="#FFCCCC" ALIGN="center" CLASS="cpldta_time_value_error" WIDTH="10%">0.000</TD>
+   <TD BGCOLOR="#FFCCCC" ALIGN="center" CLASS="cpldta_time_value_error" WIDTH="10%">4.000</TD>
+   <TD BGCOLOR="#FFCCCC" ALIGN="center" CLASS="cpldta_time_value_error" WIDTH="10%">-4.000</TD>
+  </TR>
+<SCRIPT language="JavaScript">
+<!--
+function AUTO_TS_F2P_IDE_R_Q_to_IDE_R() {
+   aWindow=window.open("","thewindow","toolbar=no,WIDTH=350,height=300,status=no,scrollbars=yes,resizable=yes,menubar=no")
+   aWindow.document.writeln("<link type=\"text/css\" rel=\"stylesheet\" href=\"cpldta_style.css\">")
+   aWindow.document.writeln("<H3 CLASS=\"cpldta_text_subsection_header\">Path Trace: ")
+   aWindow.document.writeln("IDE_R.Q to IDE_R")
+   aWindow.document.writeln("</H3>")
+   aWindow.document.writeln("<TABLE  WIDTH=\"90%\" border=\"1\" ALIGN=\"center\">")
+   aWindow.document.writeln("<TR>")
+   aWindow.document.writeln("<TH BGCOLOR=\"#FFFFCC\" WIDTH=\"40%\" CLASS=\"cpldta_constraint_header\">Delay Type</TH>")
+   aWindow.document.writeln("<TH BGCOLOR=\"#FFFFCC\" WIDTH=\"20%\" CLASS=\"cpldta_time_header\">Delay (ns)</TH>")
+   aWindow.document.writeln("<TH BGCOLOR=\"#FFFFCC\" WIDTH=\"40%\" CLASS=\"cpldta_constraint_header\">Logical Resource</TH>")
+   aWindow.document.writeln("</TR>")
+   aWindow.document.writeln("<TR>")
+   aWindow.document.writeln("<TD WIDTH=\"40%\" CLASS=\"cpldta_datasheet_pathname\">tCOI</TD>")
+   aWindow.document.writeln("<TD WIDTH=\"20%\" CLASS=\"cpldta_datasheet_time_value\">1.000</TD>")
+   aWindow.document.writeln("<TD WIDTH=\"40%\" CLASS=\"cpldta_datasheet_pathname\">IDE_R</TD>")
+   aWindow.document.writeln("<TR>")
+   aWindow.document.writeln("<TD WIDTH=\"40%\" CLASS=\"cpldta_datasheet_pathname\">tOUT</TD>")
+   aWindow.document.writeln("<TD WIDTH=\"20%\" CLASS=\"cpldta_datasheet_time_value\">3.000</TD>")
+   aWindow.document.writeln("<TD WIDTH=\"40%\" CLASS=\"cpldta_datasheet_pathname\">IDE_R</TD>")
+   aWindow.document.writeln("</TABLE>")
+   aWindow.document.close()
+}
+//-->
+</SCRIPT>
+  <TR>
+   <A NAME="_IDE_W_Q_to_IDE_W"></A>
+   <TD BGCOLOR="#FFCCCC" ALIGN="left" CLASS="cpldta_constraint_name_error" WIDTH="40%"><A HREF="javascript:AUTO_TS_F2P_IDE_W_Q_to_IDE_W();">IDE_W.Q to IDE_W</A></TD>
+   <TD BGCOLOR="#FFCCCC" ALIGN="center" CLASS="cpldta_time_value_error" WIDTH="10%">0.000</TD>
+   <TD BGCOLOR="#FFCCCC" ALIGN="center" CLASS="cpldta_time_value_error" WIDTH="10%">4.000</TD>
+   <TD BGCOLOR="#FFCCCC" ALIGN="center" CLASS="cpldta_time_value_error" WIDTH="10%">-4.000</TD>
+  </TR>
+<SCRIPT language="JavaScript">
+<!--
+function AUTO_TS_F2P_IDE_W_Q_to_IDE_W() {
+   aWindow=window.open("","thewindow","toolbar=no,WIDTH=350,height=300,status=no,scrollbars=yes,resizable=yes,menubar=no")
+   aWindow.document.writeln("<link type=\"text/css\" rel=\"stylesheet\" href=\"cpldta_style.css\">")
+   aWindow.document.writeln("<H3 CLASS=\"cpldta_text_subsection_header\">Path Trace: ")
+   aWindow.document.writeln("IDE_W.Q to IDE_W")
+   aWindow.document.writeln("</H3>")
+   aWindow.document.writeln("<TABLE  WIDTH=\"90%\" border=\"1\" ALIGN=\"center\">")
+   aWindow.document.writeln("<TR>")
+   aWindow.document.writeln("<TH BGCOLOR=\"#FFFFCC\" WIDTH=\"40%\" CLASS=\"cpldta_constraint_header\">Delay Type</TH>")
+   aWindow.document.writeln("<TH BGCOLOR=\"#FFFFCC\" WIDTH=\"20%\" CLASS=\"cpldta_time_header\">Delay (ns)</TH>")
+   aWindow.document.writeln("<TH BGCOLOR=\"#FFFFCC\" WIDTH=\"40%\" CLASS=\"cpldta_constraint_header\">Logical Resource</TH>")
+   aWindow.document.writeln("</TR>")
+   aWindow.document.writeln("<TR>")
+   aWindow.document.writeln("<TD WIDTH=\"40%\" CLASS=\"cpldta_datasheet_pathname\">tCOI</TD>")
+   aWindow.document.writeln("<TD WIDTH=\"20%\" CLASS=\"cpldta_datasheet_time_value\">1.000</TD>")
+   aWindow.document.writeln("<TD WIDTH=\"40%\" CLASS=\"cpldta_datasheet_pathname\">IDE_W</TD>")
+   aWindow.document.writeln("<TR>")
+   aWindow.document.writeln("<TD WIDTH=\"40%\" CLASS=\"cpldta_datasheet_pathname\">tOUT</TD>")
+   aWindow.document.writeln("<TD WIDTH=\"20%\" CLASS=\"cpldta_datasheet_time_value\">3.000</TD>")
+   aWindow.document.writeln("<TD WIDTH=\"40%\" CLASS=\"cpldta_datasheet_pathname\">IDE_W</TD>")
+   aWindow.document.writeln("</TABLE>")
+   aWindow.document.close()
+}
+//-->
+</SCRIPT>
+  <TR>
+   <A NAME="_ROM_OE_Q_to_ROM_OE"></A>
+   <TD BGCOLOR="#FFCCCC" ALIGN="left" CLASS="cpldta_constraint_name_error" WIDTH="40%"><A HREF="javascript:AUTO_TS_F2P_ROM_OE_Q_to_ROM_OE();">ROM_OE.Q to ROM_OE</A></TD>
+   <TD BGCOLOR="#FFCCCC" ALIGN="center" CLASS="cpldta_time_value_error" WIDTH="10%">0.000</TD>
+   <TD BGCOLOR="#FFCCCC" ALIGN="center" CLASS="cpldta_time_value_error" WIDTH="10%">4.000</TD>
+   <TD BGCOLOR="#FFCCCC" ALIGN="center" CLASS="cpldta_time_value_error" WIDTH="10%">-4.000</TD>
+  </TR>
+<SCRIPT language="JavaScript">
+<!--
+function AUTO_TS_F2P_ROM_OE_Q_to_ROM_OE() {
+   aWindow=window.open("","thewindow","toolbar=no,WIDTH=350,height=300,status=no,scrollbars=yes,resizable=yes,menubar=no")
+   aWindow.document.writeln("<link type=\"text/css\" rel=\"stylesheet\" href=\"cpldta_style.css\">")
+   aWindow.document.writeln("<H3 CLASS=\"cpldta_text_subsection_header\">Path Trace: ")
+   aWindow.document.writeln("ROM_OE.Q to ROM_OE")
+   aWindow.document.writeln("</H3>")
+   aWindow.document.writeln("<TABLE  WIDTH=\"90%\" border=\"1\" ALIGN=\"center\">")
+   aWindow.document.writeln("<TR>")
+   aWindow.document.writeln("<TH BGCOLOR=\"#FFFFCC\" WIDTH=\"40%\" CLASS=\"cpldta_constraint_header\">Delay Type</TH>")
+   aWindow.document.writeln("<TH BGCOLOR=\"#FFFFCC\" WIDTH=\"20%\" CLASS=\"cpldta_time_header\">Delay (ns)</TH>")
+   aWindow.document.writeln("<TH BGCOLOR=\"#FFFFCC\" WIDTH=\"40%\" CLASS=\"cpldta_constraint_header\">Logical Resource</TH>")
+   aWindow.document.writeln("</TR>")
+   aWindow.document.writeln("<TR>")
+   aWindow.document.writeln("<TD WIDTH=\"40%\" CLASS=\"cpldta_datasheet_pathname\">tCOI</TD>")
+   aWindow.document.writeln("<TD WIDTH=\"20%\" CLASS=\"cpldta_datasheet_time_value\">1.000</TD>")
+   aWindow.document.writeln("<TD WIDTH=\"40%\" CLASS=\"cpldta_datasheet_pathname\">ROM_OE</TD>")
+   aWindow.document.writeln("<TR>")
+   aWindow.document.writeln("<TD WIDTH=\"40%\" CLASS=\"cpldta_datasheet_pathname\">tOUT</TD>")
+   aWindow.document.writeln("<TD WIDTH=\"20%\" CLASS=\"cpldta_datasheet_time_value\">3.000</TD>")
+   aWindow.document.writeln("<TD WIDTH=\"40%\" CLASS=\"cpldta_datasheet_pathname\">ROM_OE</TD>")
+   aWindow.document.writeln("</TABLE>")
+   aWindow.document.close()
+}
+//-->
+</SCRIPT>
+ </TABLE>
+ </BR>
+ </BR>
+  <BR><B>Number of constraints not met:</B>&nbsp;4<BR>
+<HR>
+<A NAME="DataSheet"></a>
+<h2 ALIGN="center" CLASS="cpldta_text_section_header">Data Sheet Report</h2>
+ <A NAME="ClockSpeedList"></a>
+ <h3 CLASS="cpldta_text_subsection_header">Maximum External Clock Speeds</h3>
+ <TABLE  WIDTH="80%" border="1" ALIGN="center">
+  <TR>
+   <TH BGCOLOR="#FFFFCC" WIDTH="40%" CLASS="cpldta_constraint_header">Clock</TH>
+   <TH BGCOLOR="#FFFFCC" WIDTH="20%" CLASS="cpldta_time_header">fEXT (MHz)</TH>
+   <TH BGCOLOR="#FFFFCC" WIDTH="40%" CLASS="cpldta_constraint_header">Reason</TH>
+  </TR>
+  <TR>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">C1</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">71.429</TD>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">Limited by Clock Pulse Width for C1</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">C3</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">71.429</TD>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">Limited by Clock Pulse Width for C3</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">AS</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">71.429</TD>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">Limited by Clock Pulse Width for AS</TD>
+  </TR>
+ </TABLE>
+ <BR>
+ <A NAME="SetupHoldTimesForClocks"></a>
+ <h3 CLASS="cpldta_text_subsection_header">Setup/Hold Times for Clocks</h3>
+ <TABLE  WIDTH="80%" border="1" ALIGN="center">
+  <CAPTION CLASS="cpldta_text_caption"><B>Setup/Hold Times for Clock C1</B></CAPTION>
+  <TR>
+   <TH BGCOLOR="#FFFFCC" WIDTH="60%" CLASS="cpldta_constraint_header">Source Pad</TH>
+   <TH BGCOLOR="#FFFFCC" WIDTH="20%" CLASS="cpldta_time_header">Setup to clk (edge) </TH>
+   <TH BGCOLOR="#FFFFCC" WIDTH="20%" CLASS="cpldta_time_header">Hold to clk (edge) </TH>
+  </TR>
+  <TR>
+   <TD WIDTH="60%" CLASS="cpldta_datasheet_pathname">A<16></TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">-4.600</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">9.100</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="60%" CLASS="cpldta_datasheet_pathname">A<17></TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">-4.600</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">9.100</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="60%" CLASS="cpldta_datasheet_pathname">A<18></TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">-4.600</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">9.100</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="60%" CLASS="cpldta_datasheet_pathname">A<19></TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">-5.600</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">9.100</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="60%" CLASS="cpldta_datasheet_pathname">A<1></TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">-5.600</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">9.100</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="60%" CLASS="cpldta_datasheet_pathname">A<20></TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">-4.200</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">9.100</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="60%" CLASS="cpldta_datasheet_pathname">A<21></TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">-4.200</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">9.100</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="60%" CLASS="cpldta_datasheet_pathname">A<22></TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">-4.600</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">9.100</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="60%" CLASS="cpldta_datasheet_pathname">A<23></TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">-4.600</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">9.100</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="60%" CLASS="cpldta_datasheet_pathname">A<2></TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">-5.600</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">9.100</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="60%" CLASS="cpldta_datasheet_pathname">A<3></TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">-5.600</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">9.100</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="60%" CLASS="cpldta_datasheet_pathname">A<4></TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">-5.600</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">9.100</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="60%" CLASS="cpldta_datasheet_pathname">A<5></TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">-5.600</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">9.100</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="60%" CLASS="cpldta_datasheet_pathname">A<6></TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">-5.600</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">9.100</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="60%" CLASS="cpldta_datasheet_pathname">AS</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">-5.600</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">9.100</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="60%" CLASS="cpldta_datasheet_pathname">BERR</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">-5.600</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">9.100</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="60%" CLASS="cpldta_datasheet_pathname">D<10></TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">-5.600</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">9.100</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="60%" CLASS="cpldta_datasheet_pathname">D<11></TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">-5.600</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">9.100</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="60%" CLASS="cpldta_datasheet_pathname">D<12></TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">-5.600</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">9.100</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="60%" CLASS="cpldta_datasheet_pathname">D<13></TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">-5.600</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">9.100</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="60%" CLASS="cpldta_datasheet_pathname">D<14></TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">-5.600</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">9.100</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="60%" CLASS="cpldta_datasheet_pathname">D<15></TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">-5.600</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">9.100</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="60%" CLASS="cpldta_datasheet_pathname">D<8></TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">-5.600</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">9.100</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="60%" CLASS="cpldta_datasheet_pathname">D<9></TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">-5.600</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">9.100</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="60%" CLASS="cpldta_datasheet_pathname">RESET</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">-5.600</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">9.100</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="60%" CLASS="cpldta_datasheet_pathname">RW</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">-5.600</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">9.100</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="60%" CLASS="cpldta_datasheet_pathname">UDS</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">-5.600</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">9.100</TD>
+  </TR>
+ </TABLE><BR>
+ <TABLE  WIDTH="80%" border="1" ALIGN="center">
+  <CAPTION CLASS="cpldta_text_caption"><B>Setup/Hold Times for Clock C3</B></CAPTION>
+  <TR>
+   <TH BGCOLOR="#FFFFCC" WIDTH="60%" CLASS="cpldta_constraint_header">Source Pad</TH>
+   <TH BGCOLOR="#FFFFCC" WIDTH="20%" CLASS="cpldta_time_header">Setup to clk (edge) </TH>
+   <TH BGCOLOR="#FFFFCC" WIDTH="20%" CLASS="cpldta_time_header">Hold to clk (edge) </TH>
+  </TR>
+  <TR>
+   <TD WIDTH="60%" CLASS="cpldta_datasheet_pathname">A<16></TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">-4.600</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">9.100</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="60%" CLASS="cpldta_datasheet_pathname">A<17></TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">-4.600</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">9.100</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="60%" CLASS="cpldta_datasheet_pathname">A<18></TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">-4.600</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">9.100</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="60%" CLASS="cpldta_datasheet_pathname">A<19></TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">-5.600</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">9.100</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="60%" CLASS="cpldta_datasheet_pathname">A<1></TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">-5.600</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">9.100</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="60%" CLASS="cpldta_datasheet_pathname">A<20></TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">-4.200</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">9.100</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="60%" CLASS="cpldta_datasheet_pathname">A<21></TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">-4.200</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">9.100</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="60%" CLASS="cpldta_datasheet_pathname">A<22></TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">-4.600</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">9.100</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="60%" CLASS="cpldta_datasheet_pathname">A<23></TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">-4.600</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">9.100</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="60%" CLASS="cpldta_datasheet_pathname">A<2></TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">-5.600</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">9.100</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="60%" CLASS="cpldta_datasheet_pathname">A<3></TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">-5.600</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">9.100</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="60%" CLASS="cpldta_datasheet_pathname">A<4></TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">-5.600</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">9.100</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="60%" CLASS="cpldta_datasheet_pathname">A<5></TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">-5.600</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">9.100</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="60%" CLASS="cpldta_datasheet_pathname">A<6></TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">-5.600</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">9.100</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="60%" CLASS="cpldta_datasheet_pathname">AS</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">-5.600</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">9.100</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="60%" CLASS="cpldta_datasheet_pathname">BERR</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">-5.600</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">9.100</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="60%" CLASS="cpldta_datasheet_pathname">D<10></TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">-5.600</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">9.100</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="60%" CLASS="cpldta_datasheet_pathname">D<11></TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">-5.600</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">9.100</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="60%" CLASS="cpldta_datasheet_pathname">D<12></TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">-5.600</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">9.100</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="60%" CLASS="cpldta_datasheet_pathname">D<13></TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">-5.600</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">9.100</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="60%" CLASS="cpldta_datasheet_pathname">D<14></TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">-5.600</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">9.100</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="60%" CLASS="cpldta_datasheet_pathname">D<15></TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">-5.600</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">9.100</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="60%" CLASS="cpldta_datasheet_pathname">D<8></TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">-5.600</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">9.100</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="60%" CLASS="cpldta_datasheet_pathname">D<9></TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">-5.600</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">9.100</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="60%" CLASS="cpldta_datasheet_pathname">RESET</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">-5.600</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">9.100</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="60%" CLASS="cpldta_datasheet_pathname">RW</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">-5.600</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">9.100</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="60%" CLASS="cpldta_datasheet_pathname">UDS</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">-5.600</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">9.100</TD>
+  </TR>
+ </TABLE><BR>
+ <BR>
+ <A NAME="ClockToPadTiming"></a>
+ <h3 CLASS="cpldta_text_subsection_header">Clock to Pad Timing</h3>
+ <TABLE  WIDTH="80%" border="1" ALIGN="center">
+  <CAPTION CLASS="cpldta_text_caption"><B>Clock C1 to Pad</B></CAPTION>
+  <TR>
+   <TH BGCOLOR="#FFFFCC" WIDTH="80%" CLASS="cpldta_constraint_header">Destination Pad</TH>
+   <TH BGCOLOR="#FFFFCC" WIDTH="20%" CLASS="cpldta_time_header">Clock (edge) to Pad </TH>
+  </TR>
+  <TR>
+   <TD WIDTH="80%" CLASS="cpldta_datasheet_pathname">IDE_R</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">17.900</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="80%" CLASS="cpldta_datasheet_pathname">IDE_W</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">17.900</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="80%" CLASS="cpldta_datasheet_pathname">ROM_OE</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">17.900</TD>
+  </TR>
+ </TABLE><BR>
+ <TABLE  WIDTH="80%" border="1" ALIGN="center">
+  <CAPTION CLASS="cpldta_text_caption"><B>Clock C3 to Pad</B></CAPTION>
+  <TR>
+   <TH BGCOLOR="#FFFFCC" WIDTH="80%" CLASS="cpldta_constraint_header">Destination Pad</TH>
+   <TH BGCOLOR="#FFFFCC" WIDTH="20%" CLASS="cpldta_time_header">Clock (edge) to Pad </TH>
+  </TR>
+  <TR>
+   <TD WIDTH="80%" CLASS="cpldta_datasheet_pathname">IDE_R</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">17.900</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="80%" CLASS="cpldta_datasheet_pathname">IDE_W</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">17.900</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="80%" CLASS="cpldta_datasheet_pathname">ROM_OE</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">17.900</TD>
+  </TR>
+ </TABLE><BR>
+ <BR>
+ <A NAME="ClockToSetupTimesForClocks"></a>
+ <h3 CLASS="cpldta_text_subsection_header">Clock to Setup Times for Clocks</h3>
+ <TABLE  WIDTH="80%" border="1" ALIGN="center">
+  <CAPTION CLASS="cpldta_text_caption"><B>Clock to Setup for clock C1</B></CAPTION>
+  <TR>
+   <TH BGCOLOR="#FFFFCC" WIDTH="40%" CLASS="cpldta_constraint_header">Source</TH>
+   <TH BGCOLOR="#FFFFCC" WIDTH="40%" CLASS="cpldta_constraint_header">Destination</TH>
+   <TH BGCOLOR="#FFFFCC" WIDTH="20%" CLASS="cpldta_time_header">Delay</TH>
+  </TR>
+  <TR>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">IDE_BASEADR<4>.Q</TD>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">ide.D</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">11.400</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">IDE_BASEADR<5>.Q</TD>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">ide.D</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">11.400</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">IDE_BASEADR<0>.Q</TD>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">ide.D</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">11.000</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">IDE_BASEADR<1>.Q</TD>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">ide.D</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">11.000</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">IDE_BASEADR<2>.Q</TD>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">ide.D</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">11.000</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">IDE_BASEADR<6>.Q</TD>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">ide.D</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">11.000</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">IDE_BASEADR<7>.Q</TD>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">ide.D</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">11.000</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">AUTO_CONFIG_DONE_CYCLE<1>.Q</TD>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">AUTO_CONFIG_DONE_CYCLE<1>.D</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">10.000</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">IDE_BASEADR<0>.Q</TD>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">IDE_BASEADR<0>.D</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">10.000</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">IDE_BASEADR<1>.Q</TD>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">IDE_BASEADR<1>.D</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">10.000</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">IDE_BASEADR<2>.Q</TD>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">IDE_BASEADR<2>.D</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">10.000</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">IDE_BASEADR<3>.Q</TD>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">IDE_BASEADR<3>.D</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">10.000</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">IDE_BASEADR<3>.Q</TD>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">ide.D</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">10.000</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">IDE_BASEADR<4>.Q</TD>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">IDE_BASEADR<4>.D</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">10.000</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">IDE_BASEADR<5>.Q</TD>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">IDE_BASEADR<5>.D</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">10.000</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">IDE_BASEADR<6>.Q</TD>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">IDE_BASEADR<6>.D</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">10.000</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">IDE_BASEADR<7>.Q</TD>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">IDE_BASEADR<7>.D</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">10.000</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">IDE_ENABLE.Q</TD>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">IDE_ENABLE.D</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">10.000</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">IDE_ENABLE.Q</TD>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">IDE_R.D</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">10.000</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">IDE_ENABLE.Q</TD>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">ROM_OE.D</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">10.000</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">SHUT_UP<1>.Q</TD>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">SHUT_UP<1>.D</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">10.000</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">SHUT_UP<1>.Q</TD>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">ide.D</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">10.000</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">autoconfig.Q</TD>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">AUTO_CONFIG_DONE_CYCLE<1>.D</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">10.000</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">autoconfig.Q</TD>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">IDE_BASEADR<0>.D</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">10.000</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">autoconfig.Q</TD>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">IDE_BASEADR<1>.D</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">10.000</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">autoconfig.Q</TD>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">IDE_BASEADR<2>.D</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">10.000</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">autoconfig.Q</TD>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">IDE_BASEADR<3>.D</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">10.000</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">autoconfig.Q</TD>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">IDE_BASEADR<4>.D</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">10.000</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">autoconfig.Q</TD>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">IDE_BASEADR<5>.D</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">10.000</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">autoconfig.Q</TD>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">IDE_BASEADR<6>.D</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">10.000</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">autoconfig.Q</TD>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">IDE_BASEADR<7>.D</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">10.000</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">autoconfig.Q</TD>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">SHUT_UP<1>.D</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">10.000</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">ide.Q</TD>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">IDE_ENABLE.D</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">10.000</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">ide.Q</TD>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">IDE_R.D</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">10.000</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">ide.Q</TD>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">IDE_W.D</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">10.000</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">ide.Q</TD>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">ROM_OE.D</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">10.000</TD>
+  </TR>
+ </TABLE><BR>
+ <TABLE  WIDTH="80%" border="1" ALIGN="center">
+  <CAPTION CLASS="cpldta_text_caption"><B>Clock to Setup for clock C3</B></CAPTION>
+  <TR>
+   <TH BGCOLOR="#FFFFCC" WIDTH="40%" CLASS="cpldta_constraint_header">Source</TH>
+   <TH BGCOLOR="#FFFFCC" WIDTH="40%" CLASS="cpldta_constraint_header">Destination</TH>
+   <TH BGCOLOR="#FFFFCC" WIDTH="20%" CLASS="cpldta_time_header">Delay</TH>
+  </TR>
+  <TR>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">IDE_BASEADR<4>.Q</TD>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">ide.D</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">11.400</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">IDE_BASEADR<5>.Q</TD>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">ide.D</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">11.400</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">IDE_BASEADR<0>.Q</TD>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">ide.D</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">11.000</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">IDE_BASEADR<1>.Q</TD>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">ide.D</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">11.000</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">IDE_BASEADR<2>.Q</TD>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">ide.D</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">11.000</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">IDE_BASEADR<6>.Q</TD>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">ide.D</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">11.000</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">IDE_BASEADR<7>.Q</TD>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">ide.D</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">11.000</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">AUTO_CONFIG_DONE_CYCLE<1>.Q</TD>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">AUTO_CONFIG_DONE_CYCLE<1>.D</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">10.000</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">IDE_BASEADR<0>.Q</TD>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">IDE_BASEADR<0>.D</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">10.000</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">IDE_BASEADR<1>.Q</TD>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">IDE_BASEADR<1>.D</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">10.000</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">IDE_BASEADR<2>.Q</TD>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">IDE_BASEADR<2>.D</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">10.000</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">IDE_BASEADR<3>.Q</TD>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">IDE_BASEADR<3>.D</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">10.000</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">IDE_BASEADR<3>.Q</TD>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">ide.D</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">10.000</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">IDE_BASEADR<4>.Q</TD>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">IDE_BASEADR<4>.D</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">10.000</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">IDE_BASEADR<5>.Q</TD>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">IDE_BASEADR<5>.D</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">10.000</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">IDE_BASEADR<6>.Q</TD>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">IDE_BASEADR<6>.D</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">10.000</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">IDE_BASEADR<7>.Q</TD>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">IDE_BASEADR<7>.D</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">10.000</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">IDE_ENABLE.Q</TD>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">IDE_ENABLE.D</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">10.000</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">IDE_ENABLE.Q</TD>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">IDE_R.D</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">10.000</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">IDE_ENABLE.Q</TD>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">ROM_OE.D</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">10.000</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">SHUT_UP<1>.Q</TD>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">SHUT_UP<1>.D</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">10.000</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">SHUT_UP<1>.Q</TD>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">ide.D</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">10.000</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">autoconfig.Q</TD>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">AUTO_CONFIG_DONE_CYCLE<1>.D</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">10.000</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">autoconfig.Q</TD>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">IDE_BASEADR<0>.D</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">10.000</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">autoconfig.Q</TD>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">IDE_BASEADR<1>.D</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">10.000</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">autoconfig.Q</TD>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">IDE_BASEADR<2>.D</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">10.000</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">autoconfig.Q</TD>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">IDE_BASEADR<3>.D</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">10.000</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">autoconfig.Q</TD>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">IDE_BASEADR<4>.D</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">10.000</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">autoconfig.Q</TD>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">IDE_BASEADR<5>.D</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">10.000</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">autoconfig.Q</TD>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">IDE_BASEADR<6>.D</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">10.000</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">autoconfig.Q</TD>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">IDE_BASEADR<7>.D</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">10.000</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">autoconfig.Q</TD>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">SHUT_UP<1>.D</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">10.000</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">ide.Q</TD>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">IDE_ENABLE.D</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">10.000</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">ide.Q</TD>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">IDE_R.D</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">10.000</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">ide.Q</TD>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">IDE_W.D</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">10.000</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">ide.Q</TD>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">ROM_OE.D</TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">10.000</TD>
+  </TR>
+ </TABLE><BR>
+ <BR>
+ <A NAME="Pad2PadList"></a>
+ <h3 CLASS="cpldta_text_subsection_header">Pad to Pad List</h3>
+ <TABLE  WIDTH="80%" border="1" ALIGN="center">
+  <TR>
+   <TH BGCOLOR="#FFFFCC" WIDTH="40%" CLASS="cpldta_constraint_header">Source Pad</TH>
+   <TH BGCOLOR="#FFFFCC" WIDTH="40%" CLASS="cpldta_constraint_header">Destination Pad</TH>
+   <TH BGCOLOR="#FFFFCC" WIDTH="20%" CLASS="cpldta_time_header">Delay</TH>
+  </TR>
+  <TR>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">A<10></TD>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">IDE_A<1></TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">10.000</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">A<11></TD>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">IDE_A<2></TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">10.000</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">A<12></TD>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">IDE_CS<0></TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">10.000</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">A<13></TD>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">IDE_CS<1></TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">10.000</TD>
+  </TR>
+  <TR>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">A<9></TD>
+   <TD WIDTH="40%" CLASS="cpldta_datasheet_pathname">IDE_A<0></TD>
+   <TD WIDTH="20%" CLASS="cpldta_datasheet_time_value">10.000</TD>
+  </TR>
+ </TABLE>
+ <BR>
+<HR>
+<BR><SPAN CLASS="cpldta_text_normal_bold"><B>Number of paths analyzed:</B></SPAN> 
+<SPAN CLASS="cpldta_text_normal">244</SPAN>
+<BR><SPAN CLASS="cpldta_text_normal_bold"><B>Number of Timing errors:</B></SPAN> 
+<SPAN CLASS="cpldta_text_normal">244</SPAN>
+<BR><SPAN CLASS="cpldta_text_normal_bold"><B>Analysis Completed:</B></SPAN> <SPAN CLASS="cpldta_text_normal">Thu Dec 15 19:17:49 2016
+</SPAN>
+<HR>
+</HTML>
diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/tim/toc.css b/Logic/LAN_IDE/LAN_IDE_CP_html/tim/toc.css
new file mode 100644
index 0000000..29af0e1
--- /dev/null
+++ b/Logic/LAN_IDE/LAN_IDE_CP_html/tim/toc.css
@@ -0,0 +1,36 @@
+.HEADING { 
+	font-size: 15px; 
+	font-family: Arial, Geneva, Verdana, Helvetica; 
+	font-weight: bold; color: #000000; 
+	text-align: normal; 
+	margin-left: 0px; } 
+.Fitting { 
+	font-size: 11px; 
+	font-family: Arial, Geneva, Verdana, Helvetica; 
+	font-weight: bold; color: #000000; 
+	text-align: normal; 
+	margin-left: 0px; }	
+.SECONDARY-NAV { 
+	font-size: 11px; 
+	font-family: Arial, Geneva, Verdana, Helvetica; 
+	font-weight: bold; color: #FFFFFF; 
+	margin-left: 0px; 
+	text-decoration: none; ; 
+	list-style-type: disc ; 
+	list-style-position: inside } 
+.Timing { 
+	font-size: 11px; 
+	font-family: Arial, Geneva, Verdana, Helvetica; 
+	font-weight: bold; color: #333333; 
+	margin-left: 0px; 
+	text-decoration: none; ; 
+	list-style-type: disc ; 
+	list-style-position: inside } 
+.Timing-Error { 
+	font-size: 11px; 
+	font-family: Arial, Geneva, Verdana, Helvetica; 
+	font-weight: bold; color: #990000; 
+	margin-left: 0px; 
+	text-decoration: none; ; 
+	list-style-type: disc ; 
+	list-style-position: inside } 
diff --git a/Logic/LAN_IDE/LAN_IDE_CP_html/tim/topnav.htm b/Logic/LAN_IDE/LAN_IDE_CP_html/tim/topnav.htm
new file mode 100644
index 0000000..00e11b8
--- /dev/null
+++ b/Logic/LAN_IDE/LAN_IDE_CP_html/tim/topnav.htm
@@ -0,0 +1,31 @@
+<html>
+<head>
+<title>CPLD Reports Banner</title>
+<meta http-equiv="Content-Type" content="text/html; charset=iso-8859-1">
+</head>
+
+<body bgcolor="#FFFFFF" text="#000000">
+<table width="100%" border="0" cellspacing="0" cellpadding="0">
+  <tr> 
+    <td width="607" height="69"><img src="../images/cpldBanner.jpg" width="486" height="69"></td>
+    <td width="251"><img src="../images/logo.jpg"></td>
+    <td bgcolor="#FFFFFF">&nbsp;</td>
+  </tr>
+  <tr> 
+    <td bgcolor="#000000" height="24">
+	  <img src="../images/blackBar.jpg" width="125" height="24">
+	  <img src="../images/fitterRpt.jpg" width="88" height="24" usemap="#fitReport" border="0">
+	  <img src="../images/spacer.jpg" width="32" height="24">
+	  <img src="../images/timingRpt.jpg" width="100" height="24" usemap="#timReport" border="0">
+    <td bgcolor="#000000" height="24">&nbsp;</td>
+    <td bgcolor="#000000">&nbsp;</td>
+  </tr>
+</table>
+<map name="fitReport"> 
+  <area shape="rect" coords="1,1,86,22" href="../fit/report.htm" target="_top">
+</map>
+<map name="timReport">
+  <area shape="rect" coords="1,1,101,24" href="../tim/report.htm" target="_top">
+</map>
+</body>
+</html>
diff --git a/Logic/LAN_IDE/LAN_IDE_CP_ngdbuild.xrpt b/Logic/LAN_IDE/LAN_IDE_CP_ngdbuild.xrpt
new file mode 100644
index 0000000..e8a8d37
--- /dev/null
+++ b/Logic/LAN_IDE/LAN_IDE_CP_ngdbuild.xrpt
@@ -0,0 +1,113 @@
+<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
+<document OS="nt64" product="ISE" version="14.6">
+
+  <!--The data in this file is primarily intended for consumption by Xilinx tools.
+    The structure and the elements are likely to change over the next few releases.
+    This means code written to parse this file will need to be revisited each subsequent release.-->
+
+  <application stringID="NgdBuild" timeStamp="Thu Dec 15 19:48:31 2016">
+    <section stringID="User_Env">
+      <table stringID="User_EnvVar">
+        <column stringID="variable"/>
+        <column stringID="value"/>
+        <row stringID="row" value="0">
+          <item stringID="variable" value="Path"/>
+          <item stringID="value" value="C:\Xilinx\14.6\ISE_DS\ISE\\lib\nt64;C:\Xilinx\14.6\ISE_DS\ISE\\bin\nt64;C:\Xilinx\14.6\ISE_DS\ISE\bin\nt64;C:\Xilinx\14.6\ISE_DS\ISE\lib\nt64;C:\Xilinx\14.6\ISE_DS\ISE\..\..\..\DocNav;C:\Xilinx\14.6\ISE_DS\PlanAhead\bin;C:\Xilinx\14.6\ISE_DS\EDK\bin\nt64;C:\Xilinx\14.6\ISE_DS\EDK\lib\nt64;C:\Xilinx\14.6\ISE_DS\EDK\gnu\microblaze\nt\bin;C:\Xilinx\14.6\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;C:\Xilinx\14.6\ISE_DS\EDK\gnuwin\bin;C:\Xilinx\14.6\ISE_DS\EDK\gnu\arm\nt\bin;C:\Xilinx\14.6\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;C:\Xilinx\14.6\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;C:\Xilinx\14.6\ISE_DS\common\bin\nt64;C:\Xilinx\14.6\ISE_DS\common\lib\nt64;E:\ispLEVER_Classic2_0\ispcpld\bin;E:\ispLEVER_Classic2_0\ispFPGA\bin\nt;E:\ispLEVER_Classic2_0\active-hdl\BIN;C:\ProgramData\Oracle\Java\javapath;C:\SynaptiCAD\bin\win32;C:\Program Files\Java\jre7\bin;C\Windows\System32;C:\Program Files (x86)\WinAVR\bin;C:\Program Files (x86)\WinAVR\utils\bin;C:\Program Files\Common Files\Microsoft Shared\Windows Live;C:\Program Files (x86)\SSH Communications Security\SSH Secure Shell;C:\Program Files (x86)\UltraEdit;c:\Xilinx\14.6\ISE_DS\ISE\bin\nt64C:\ispLever\ispcpld\bin;C:\ispLever\ispFPGA\bin\nt;C:\ispLever\active-hdl\BIN;C:\Program Files\WinRAR;C:\SynaptiCAD\bin;C:\Program Files (x86)\Windows Kits\8.1\Windows Performance Toolkit\;C:\Program Files\Microsoft SQL Server\110\Tools\Binn\;C:\Program Files (x86)\Microsoft SDKs\TypeScript\1.0\;C:\Program Files\Microsoft SQL Server\120\Tools\Binn\;C:\WINDOWS\system32;C:\WINDOWS;C:\WINDOWS\System32\Wbem;C:\WINDOWS\System32\WindowsPowerShell\v1.0\;C:\Program Files (x86)\ATI Technologies\ATI.ACE\Core-Static;%PATH;C:\Program Files (x86)\IDM Computer Solutions\UltraEdit\;C:\Program Files (x86)\UltraEdit\;C:\Program Files\Java\jdk1.7.0_02\bin;C:\Users\Matze\AppData\Local\Microsoft\WindowsApps"/>
+        </row>
+        <row stringID="row" value="1">
+          <item stringID="variable" value="PATHEXT"/>
+          <item stringID="value" value=".COM;.EXE;.BAT;.CMD;.VBS;.VBE;.JS;.JSE;.WSF;.WSH;.MSC;.PY"/>
+        </row>
+        <row stringID="row" value="2">
+          <item stringID="variable" value="XILINX"/>
+          <item stringID="value" value="C:\Xilinx\14.6\ISE_DS\ISE\"/>
+        </row>
+        <row stringID="row" value="3">
+          <item stringID="variable" value="XILINX_DSP"/>
+          <item stringID="value" value="C:\Xilinx\14.6\ISE_DS\ISE"/>
+        </row>
+        <row stringID="row" value="4">
+          <item stringID="variable" value="XILINX_EDK"/>
+          <item stringID="value" value="C:\Xilinx\14.6\ISE_DS\EDK"/>
+        </row>
+        <row stringID="row" value="5">
+          <item stringID="variable" value="XILINX_PLANAHEAD"/>
+          <item stringID="value" value="C:\Xilinx\14.6\ISE_DS\PlanAhead"/>
+        </row>
+      </table>
+      <item stringID="User_EnvOs" value="OS Information">
+        <item stringID="User_EnvOsname" value="Microsoft , 64-bit"/>
+        <item stringID="User_EnvOsrelease" value="major release  (build 9200)"/>
+      </item>
+      <item stringID="User_EnvHost" value="DeepThought"/>
+      <table stringID="User_EnvCpu">
+        <column stringID="arch"/>
+        <column stringID="speed"/>
+        <row stringID="row" value="0">
+          <item stringID="arch" value="AMD Phenom(tm) II X6 1090T Processor"/>
+          <item stringID="speed" value="3200 MHz"/>
+        </row>
+        <row stringID="row" value="1">
+          <item stringID="arch" value="AMD Phenom(tm) II X6 1090T Processor"/>
+          <item stringID="speed" value="3200 MHz"/>
+        </row>
+      </table>
+    </section>
+    <task stringID="NGDBUILD_OPTION_SUMMARY">
+      <section stringID="NGDBUILD_OPTION_SUMMARY">
+        <item DEFAULT="None" label="-intstyle" stringID="NGDBUILD_intstyle" value="ise"/>
+        <item DEFAULT="None" label="-dd" stringID="NGDBUILD_output_dir" value="_ngo"/>
+        <item DEFAULT="None" label="-p" stringID="NGDBUILD_partname" value="xc95144xl-TQ144-10"/>
+        <item DEFAULT="None" label="-uc" stringID="NGDBUILD_ucf_file" value="pinlist.ucf"/>
+      </section>
+    </task>
+    <task stringID="NGDBUILD_REPORT">
+      <section stringID="NGDBUILD_DESIGN_SUMMARY">
+        <item dataType="int" stringID="NGDBUILD_NUM_ERRORS" value="0"/>
+        <item dataType="int" stringID="NGDBUILD_FILTERED_WARNINGS" value="0"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_WARNINGS" value="20"/>
+        <item dataType="int" stringID="NGDBUILD_FILTERED_INFOS" value="0"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_INFOS" value="0"/>
+      </section>
+      <section stringID="NGDBUILD_PRE_UNISIM_SUMMARY">
+        <item dataType="int" stringID="NGDBUILD_NUM_AND2" value="75"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_AND3" value="16"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_AND4" value="5"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_AND5" value="1"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_FD" value="6"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_FDC" value="3"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_FDCE" value="17"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_GND" value="1"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_IBUF" value="27"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_INV" value="138"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="10"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_OR2" value="63"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_OR3" value="13"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_OR4" value="2"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_OR5" value="1"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_VCC" value="1"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_XOR2" value="6"/>
+      </section>
+      <section stringID="NGDBUILD_POST_UNISIM_SUMMARY">
+        <item dataType="int" stringID="NGDBUILD_NUM_AND2" value="75"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_AND3" value="16"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_AND4" value="5"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_AND5" value="1"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_GND" value="10"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_IBUF" value="66"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_INV" value="138"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="41"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_OR2" value="63"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_OR3" value="13"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_OR4" value="2"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_OR5" value="1"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_VCC" value="1"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_XOR2" value="6"/>
+      </section>
+      <section stringID="NGDBUILD_CORE_GENERATION_SUMMARY">
+        <section stringID="NGDBUILD_CORE_INSTANCES"/>
+      </section>
+    </task>
+  </application>
+
+</document>
diff --git a/Logic/LAN_IDE/LAN_IDE_CP_pad.csv b/Logic/LAN_IDE/LAN_IDE_CP_pad.csv
new file mode 100644
index 0000000..853bd5c
--- /dev/null
+++ b/Logic/LAN_IDE/LAN_IDE_CP_pad.csv
@@ -0,0 +1,173 @@
+Release 8.1i - Fit P.68d
+Copyright(c) 1995-2003 Xilinx Inc. All rights reserved
+
+12-15-2016  7:48PM
+
+NOTE: This file is designed to be imported into a spreadsheet program
+such as Microsoft Excel for viewing, printing and sorting. The comma ','
+character is used as the data field separator.
+This file is also designed to support parsing.
+
+Input file:  LAN_IDE_CP.ngd
+output file: LAN_IDE_CP_pad.csv
+Part type:   xc95144xl
+Speed grade: -10
+Package:     tq144
+
+Pinout by Pin Number:
+
+-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,
+Pin Number,Signal Name,Pin Usage,Pin Name,Direction,IO Standard,IO Bank Number,{blank},Slew Rate,Termination,{blank},Voltage,Constraint,
+P1,VCC,,VCCIO,,,,,,,,,,
+P2,D<0>,O,I/O/GTS3,OUTPUT,,,,,,,,,
+P3,TIE,,I/O/GTS4,,,,,,,,,,
+P4,TIE,,I/O,,,,,,,,,,
+P5,TIE,,I/O/GTS1,,,,,,,,,,
+P6,TIE,,I/O/GTS2,,,,,,,,,,
+P7,TIE,,I/O,,,,,,,,,,
+P8,VCC,,VCCINT,,,,,,,,,,
+P9,TIE,,I/O,,,,,,,,,,
+P10,TIE,,I/O,,,,,,,,,,
+P11,TIE,,I/O,,,,,,,,,,
+P12,TIE,,I/O,,,,,,,,,,
+P13,TIE,,I/O,,,,,,,,,,
+P14,D<6>,O,I/O,OUTPUT,,,,,,,,,
+P15,D<3>,O,I/O,OUTPUT,,,,,,,,,
+P16,D<7>,O,I/O,OUTPUT,,,,,,,,,
+P17,D<1>,O,I/O,OUTPUT,,,,,,,,,
+P18,GND,,GND,,,,,,,,,,
+P19,D<8>,I/O,I/O,BIDIR,,,,,,,,,
+P20,D<5>,O,I/O,OUTPUT,,,,,,,,,
+P21,D<4>,O,I/O,OUTPUT,,,,,,,,,
+P22,IDE_CS<0>,O,I/O,OUTPUT,,,,,,,,,
+P23,IDE_CS<1>,O,I/O,OUTPUT,,,,,,,,,
+P24,IDE_A<0>,O,I/O,OUTPUT,,,,,,,,,
+P25,IDE_A<2>,O,I/O,OUTPUT,,,,,,,,,
+P26,IDE_A<1>,O,I/O,OUTPUT,,,,,,,,,
+P27,IDE_R,O,I/O,OUTPUT,,,,,,,,,
+P28,IDE_W,O,I/O,OUTPUT,,,,,,,,,
+P29,GND,,GND,,,,,,,,,,
+P30,TIE,,I/O/GCK1,,,,,,,,,,
+P31,TIE,,I/O,,,,,,,,,,
+P32,TIE,,I/O/GCK2,,,,,,,,,,
+P33,TIE,,I/O,,,,,,,,,,
+P34,TIE,,I/O,,,,,,,,,,
+P35,ROM_OE,O,I/O,OUTPUT,,,,,,,,,
+P36,GND,,GND,,,,,,,,,,
+P37,VCC,,VCCIO,,,,,,,,,,
+P38,TIE,,I/O/GCK3,,,,,,,,,,
+P39,D<2>,O,I/O,OUTPUT,,,,,,,,,
+P40,D<9>,I/O,I/O,BIDIR,,,,,,,,,
+P41,D<10>,I/O,I/O,BIDIR,,,,,,,,,
+P42,VCC,,VCCINT,,,,,,,,,,
+P43,D<11>,I/O,I/O,BIDIR,,,,,,,,,
+P44,D<12>,I/O,I/O,BIDIR,,,,,,,,,
+P45,D<13>,I/O,I/O,BIDIR,,,,,,,,,
+P46,D<14>,I/O,I/O,BIDIR,,,,,,,,,
+P47,GND,,GND,,,,,,,,,,
+P48,D<15>,I/O,I/O,BIDIR,,,,,,,,,
+P49,A<5>,I,I/O,INPUT,,,,,,,,,
+P50,A<4>,I,I/O,INPUT,,,,,,,,,
+P51,A<6>,I,I/O,INPUT,,,,,,,,,
+P52,A<3>,I,I/O,INPUT,,,,,,,,,
+P53,TIE,,I/O,,,,,,,,,,
+P54,A<2>,I,I/O,INPUT,,,,,,,,,
+P55,VCC,,VCCIO,,,,,,,,,,
+P56,TIE,,I/O,,,,,,,,,,
+P57,A<1>,I,I/O,INPUT,,,,,,,,,
+P58,A<9>,I,I/O,INPUT,,,,,,,,,
+P59,A<10>,I,I/O,INPUT,,,,,,,,,
+P60,A<11>,I,I/O,INPUT,,,,,,,,,
+P61,A<12>,I,I/O,INPUT,,,,,,,,,
+P62,GND,,GND,,,,,,,,,,
+P63,TDI,,TDI,,,,,,,,,,
+P64,A<13>,I,I/O,INPUT,,,,,,,,,
+P65,TMS,,TMS,,,,,,,,,,
+P66,TIE,,I/O,,,,,,,,,,
+P67,TCK,,TCK,,,,,,,,,,
+P68,ROM_B<0>,O,I/O,OUTPUT,,,,,,,,,
+P69,ROM_B<1>,O,I/O,OUTPUT,,,,,,,,,
+P70,TIE,,I/O,,,,,,,,,,
+P71,TIE,,I/O,,,,,,,,,,
+P72,GND,,GND,,,,,,,,,,
+P73,VCC,,VCCIO,,,,,,,,,,
+P74,TIE,,I/O,,,,,,,,,,
+P75,AUTOBOOT_OFF,I,I/O,INPUT,,,,,,,,,
+P76,TIE,,I/O,,,,,,,,,,
+P77,TIE,,I/O,,,,,,,,,,
+P78,TIE,,I/O,,,,,,,,,,
+P79,TIE,,I/O,,,,,,,,,,
+P80,AS,I,I/O,INPUT,,,,,,,,,
+P81,UDS,I,I/O,INPUT,,,,,,,,,
+P82,TIE,,I/O,,,,,,,,,,
+P83,RW,I,I/O,INPUT,,,,,,,,,
+P84,VCC,,VCCINT,,,,,,,,,,
+P85,DTACK,O,I/O,OUTPUT,,,,,,,,,
+P86,A<23>,I,I/O,INPUT,,,,,,,,,
+P87,A<22>,I,I/O,INPUT,,,,,,,,,
+P88,A<21>,I,I/O,INPUT,,,,,,,,,
+P89,GND,,GND,,,,,,,,,,
+P90,GND,,GND,,,,,,,,,,
+P91,A<20>,I,I/O,INPUT,,,,,,,,,
+P92,A<19>,I,I/O,INPUT,,,,,,,,,
+P93,TIE,,I/O,,,,,,,,,,
+P94,A<18>,I,I/O,INPUT,,,,,,,,,
+P95,A<17>,I,I/O,INPUT,,,,,,,,,
+P96,TIE,,I/O,,,,,,,,,,
+P97,A<16>,I,I/O,INPUT,,,,,,,,,
+P98,BERR,I,I/O,INPUT,,,,,,,,,
+P99,GND,,GND,,,,,,,,,,
+P100,TIE,,I/O,,,,,,,,,,
+P101,TIE,,I/O,,,,,,,,,,
+P102,C3,I,I/O,INPUT,,,,,,,,,
+P103,C1,I,I/O,INPUT,,,,,,,,,
+P104,TIE,,I/O,,,,,,,,,,
+P105,TIE,,I/O,,,,,,,,,,
+P106,TIE,,I/O,,,,,,,,,,
+P107,TIE,,I/O,,,,,,,,,,
+P108,GND,,GND,,,,,,,,,,
+P109,VCC,,VCCIO,,,,,,,,,,
+P110,TIE,,I/O,,,,,,,,,,
+P111,TIE,,I/O,,,,,,,,,,
+P112,TIE,,I/O,,,,,,,,,,
+P113,TIE,,I/O,,,,,,,,,,
+P114,GND,,GND,,,,,,,,,,
+P115,TIE,,I/O,,,,,,,,,,
+P116,TIE,,I/O,,,,,,,,,,
+P117,TIE,,I/O,,,,,,,,,,
+P118,TIE,,I/O,,,,,,,,,,
+P119,TIE,,I/O,,,,,,,,,,
+P120,TIE,,I/O,,,,,,,,,,
+P121,TIE,,I/O,,,,,,,,,,
+P122,TDO,,TDO,,,,,,,,,,
+P123,GND,,GND,,,,,,,,,,
+P124,TIE,,I/O,,,,,,,,,,
+P125,TIE,,I/O,,,,,,,,,,
+P126,TIE,,I/O,,,,,,,,,,
+P127,VCC,,VCCIO,,,,,,,,,,
+P128,TIE,,I/O,,,,,,,,,,
+P129,TIE,,I/O,,,,,,,,,,
+P130,TIE,,I/O,,,,,,,,,,
+P131,TIE,,I/O,,,,,,,,,,
+P132,TIE,,I/O,,,,,,,,,,
+P133,TIE,,I/O,,,,,,,,,,
+P134,TIE,,I/O,,,,,,,,,,
+P135,TIE,,I/O,,,,,,,,,,
+P136,TIE,,I/O,,,,,,,,,,
+P137,TIE,,I/O,,,,,,,,,,
+P138,TIE,,I/O,,,,,,,,,,
+P139,TIE,,I/O,,,,,,,,,,
+P140,TIE,,I/O,,,,,,,,,,
+P141,VCC,,VCCINT,,,,,,,,,,
+P142,TIE,,I/O,,,,,,,,,,
+P143,RESET,GSR/I,I/O/GSR,,,,,,,,,,
+P144,GND,,GND,,,,,,,,,,
+
+To preserve the pinout above for future design iterations in
+Project Navigator simply execute the (Lock Pins) process
+located under the (Implement Design) process in a toolbox named
+(Optional Implementation Tools) or invoke PIN2UCF from the
+command line. The location constraints will be written into your
+specified UCF file
+
+
diff --git a/Logic/LAN_IDE/LAN_IDE_CP_summary.html b/Logic/LAN_IDE/LAN_IDE_CP_summary.html
index 5a64987..2288606 100644
--- a/Logic/LAN_IDE/LAN_IDE_CP_summary.html
+++ b/Logic/LAN_IDE/LAN_IDE_CP_summary.html
@@ -2,7 +2,7 @@
 <BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
 <TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
 <TR ALIGN=CENTER BGCOLOR='#99CCFF'>
-<TD ALIGN=CENTER COLSPAN='4'><B>LAN_IDE_CP Project Status</B></TD></TR>
+<TD ALIGN=CENTER COLSPAN='4'><B>LAN_IDE_CP Project Status (12/15/2016 - 19:48:52)</B></TD></TR>
 <TR ALIGN=LEFT>
 <TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
 <TD>LAN_IDE.xise</TD>
@@ -13,18 +13,19 @@
 <TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>
 <TD>LAN_IDE_CP</TD>
 <TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD>
-<TD>New</TD>
+<TD>Fitted</TD>
 </TR>
 <TR ALIGN=LEFT>
 <TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
 <TD>xc95144xl-10TQ144</TD>
 <TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>
-<TD>&nbsp;</TD>
+<TD>
+No Errors</TD>
 </TR>
 <TR ALIGN=LEFT>
 <TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 14.6</TD>
 <TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
-<TD>&nbsp;</TD>
+<TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE\_xmsgs/*.xmsgs?&DataKey=Warning'>72 Warnings (52 new)</A></TD>
 </TR>
 <TR ALIGN=LEFT>
 <TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
@@ -41,7 +42,10 @@
 </TR>
 <TR ALIGN=LEFT>
 <TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD>
-<TD>&nbsp;</TD>
+<TD>
+<A HREF_DISABLED='C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE\LAN_IDE_CP_envsettings.html'>
+System Settings</A>
+</TD>
 <TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD>
 <TD>&nbsp;&nbsp;</TD>
 </TR>
@@ -61,9 +65,9 @@
 <TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
 <TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
 <TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
-<TR ALIGN=LEFT><TD>Synthesis Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
-<TR ALIGN=LEFT><TD>Translation Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
-<TR ALIGN=LEFT><TD>CPLD Fitter Report (Text)</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE\LAN_IDE_CP.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Do 15. Dez 19:48:23 2016</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE\_xmsgs/xst.xmsgs?&DataKey=Warning'>52 Warnings (52 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE\LAN_IDE_CP.bld'>Translation Report</A></TD><TD>Current</TD><TD>Do 15. Dez 19:48:31 2016</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE\_xmsgs/ngdbuild.xmsgs?&DataKey=Warning'>20 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE\LAN_IDE_CP.rpt'>CPLD Fitter Report (Text)</A></TD><TD>Current</TD><TD>Do 15. Dez 19:48:44 2016</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE\_xmsgs/cpldfit.xmsgs?&DataKey=Warning'>67 Warnings (5 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE\_xmsgs/cpldfit.xmsgs?&DataKey=Info'>1 Info (1 new)</A></TD></TR>
 <TR ALIGN=LEFT><TD>Power Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
 </TABLE>
 &nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
@@ -73,5 +77,5 @@
 </TABLE>
 
 
-<br><center><b>Date Generated:</b> 12/13/2016 - 22:08:30</center>
+<br><center><b>Date Generated:</b> 12/15/2016 - 19:48:52</center>
 </BODY></HTML>
\ No newline at end of file
diff --git a/Logic/LAN_IDE/LAN_IDE_CP_vhdl.prj b/Logic/LAN_IDE/LAN_IDE_CP_vhdl.prj
new file mode 100644
index 0000000..80b06c6
--- /dev/null
+++ b/Logic/LAN_IDE/LAN_IDE_CP_vhdl.prj
@@ -0,0 +1 @@
+vhdl work "C:\Users\Matze\Amiga\Hardwarehacks\Zorro-LAN-IDE\Logic\LAN_IDE\LAN_IDE_CP.vhd"
diff --git a/Logic/LAN_IDE/LAN_IDE_CP_xst.xrpt b/Logic/LAN_IDE/LAN_IDE_CP_xst.xrpt
new file mode 100644
index 0000000..985d946
--- /dev/null
+++ b/Logic/LAN_IDE/LAN_IDE_CP_xst.xrpt
@@ -0,0 +1,142 @@
+<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
+<document OS="nt64" product="ISE" version="14.6">
+
+  <!--The data in this file is primarily intended for consumption by Xilinx tools.
+    The structure and the elements are likely to change over the next few releases.
+    This means code written to parse this file will need to be revisited each subsequent release.-->
+
+  <application stringID="Xst" timeStamp="Thu Dec 15 19:48:16 2016">
+    <section stringID="User_Env">
+      <table stringID="User_EnvVar">
+        <column stringID="variable"/>
+        <column stringID="value"/>
+        <row stringID="row" value="0">
+          <item stringID="variable" value="Path"/>
+          <item stringID="value" value="C:\Xilinx\14.6\ISE_DS\ISE\\lib\nt64;C:\Xilinx\14.6\ISE_DS\ISE\\bin\nt64;C:\Xilinx\14.6\ISE_DS\ISE\bin\nt64;C:\Xilinx\14.6\ISE_DS\ISE\lib\nt64;C:\Xilinx\14.6\ISE_DS\ISE\..\..\..\DocNav;C:\Xilinx\14.6\ISE_DS\PlanAhead\bin;C:\Xilinx\14.6\ISE_DS\EDK\bin\nt64;C:\Xilinx\14.6\ISE_DS\EDK\lib\nt64;C:\Xilinx\14.6\ISE_DS\EDK\gnu\microblaze\nt\bin;C:\Xilinx\14.6\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;C:\Xilinx\14.6\ISE_DS\EDK\gnuwin\bin;C:\Xilinx\14.6\ISE_DS\EDK\gnu\arm\nt\bin;C:\Xilinx\14.6\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;C:\Xilinx\14.6\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;C:\Xilinx\14.6\ISE_DS\common\bin\nt64;C:\Xilinx\14.6\ISE_DS\common\lib\nt64;E:\ispLEVER_Classic2_0\ispcpld\bin;E:\ispLEVER_Classic2_0\ispFPGA\bin\nt;E:\ispLEVER_Classic2_0\active-hdl\BIN;C:\ProgramData\Oracle\Java\javapath;C:\SynaptiCAD\bin\win32;C:\Program Files\Java\jre7\bin;C\Windows\System32;C:\Program Files (x86)\WinAVR\bin;C:\Program Files (x86)\WinAVR\utils\bin;C:\Program Files\Common Files\Microsoft Shared\Windows Live;C:\Program Files (x86)\SSH Communications Security\SSH Secure Shell;C:\Program Files (x86)\UltraEdit;c:\Xilinx\14.6\ISE_DS\ISE\bin\nt64C:\ispLever\ispcpld\bin;C:\ispLever\ispFPGA\bin\nt;C:\ispLever\active-hdl\BIN;C:\Program Files\WinRAR;C:\SynaptiCAD\bin;C:\Program Files (x86)\Windows Kits\8.1\Windows Performance Toolkit\;C:\Program Files\Microsoft SQL Server\110\Tools\Binn\;C:\Program Files (x86)\Microsoft SDKs\TypeScript\1.0\;C:\Program Files\Microsoft SQL Server\120\Tools\Binn\;C:\WINDOWS\system32;C:\WINDOWS;C:\WINDOWS\System32\Wbem;C:\WINDOWS\System32\WindowsPowerShell\v1.0\;C:\Program Files (x86)\ATI Technologies\ATI.ACE\Core-Static;%PATH;C:\Program Files (x86)\IDM Computer Solutions\UltraEdit\;C:\Program Files (x86)\UltraEdit\;C:\Program Files\Java\jdk1.7.0_02\bin;C:\Users\Matze\AppData\Local\Microsoft\WindowsApps"/>
+        </row>
+        <row stringID="row" value="1">
+          <item stringID="variable" value="PATHEXT"/>
+          <item stringID="value" value=".COM;.EXE;.BAT;.CMD;.VBS;.VBE;.JS;.JSE;.WSF;.WSH;.MSC;.PY"/>
+        </row>
+        <row stringID="row" value="2">
+          <item stringID="variable" value="XILINX"/>
+          <item stringID="value" value="C:\Xilinx\14.6\ISE_DS\ISE\"/>
+        </row>
+        <row stringID="row" value="3">
+          <item stringID="variable" value="XILINX_DSP"/>
+          <item stringID="value" value="C:\Xilinx\14.6\ISE_DS\ISE"/>
+        </row>
+        <row stringID="row" value="4">
+          <item stringID="variable" value="XILINX_EDK"/>
+          <item stringID="value" value="C:\Xilinx\14.6\ISE_DS\EDK"/>
+        </row>
+        <row stringID="row" value="5">
+          <item stringID="variable" value="XILINX_PLANAHEAD"/>
+          <item stringID="value" value="C:\Xilinx\14.6\ISE_DS\PlanAhead"/>
+        </row>
+      </table>
+      <item stringID="User_EnvOs" value="OS Information">
+        <item stringID="User_EnvOsname" value="Microsoft , 64-bit"/>
+        <item stringID="User_EnvOsrelease" value="major release  (build 9200)"/>
+      </item>
+      <item stringID="User_EnvHost" value="DeepThought"/>
+      <table stringID="User_EnvCpu">
+        <column stringID="arch"/>
+        <column stringID="speed"/>
+        <row stringID="row" value="0">
+          <item stringID="arch" value="AMD Phenom(tm) II X6 1090T Processor"/>
+          <item stringID="speed" value="3200 MHz"/>
+        </row>
+        <row stringID="row" value="1">
+          <item stringID="arch" value="AMD Phenom(tm) II X6 1090T Processor"/>
+          <item stringID="speed" value="3200 MHz"/>
+        </row>
+      </table>
+    </section>
+    <section stringID="XST_OPTION_SUMMARY">
+      <item DEFAULT="" label="-ifn" stringID="XST_IFN" value="LAN_IDE_CP.prj"/>
+      <item DEFAULT="MIXED" label="-ifmt" stringID="XST_IFMT" value="mixed"/>
+      <item DEFAULT="" label="-ofn" stringID="XST_OFN" value="LAN_IDE_CP"/>
+      <item DEFAULT="NGC" label="-ofmt" stringID="XST_OFMT" value="NGC"/>
+      <item DEFAULT="" label="-p" stringID="XST_P" value="xc9500xl"/>
+      <item DEFAULT="" label="-top" stringID="XST_TOP" value="LAN_IDE_CP"/>
+      <item DEFAULT="SPEED" label="-opt_mode" stringID="XST_OPTMODE" value="Speed"/>
+      <item DEFAULT="1" label="-opt_level" stringID="XST_OPTLEVEL" value="1"/>
+      <item DEFAULT="NO" label="-iuc" stringID="XST_IUC" value="NO"/>
+      <item DEFAULT="YES" label="-keep_hierarchy" stringID="XST_KEEPHIERARCHY" value="Yes"/>
+      <item DEFAULT="as_optimized" label="-netlist_hierarchy" stringID="XST_NETLISTHIERARCHY" value="As_Optimized"/>
+      <item DEFAULT="NO" label="-rtlview" stringID="XST_RTLVIEW" value="Yes"/>
+      <item DEFAULT="/" stringID="XST_HIERARCHYSEPARATOR" value="/"/>
+      <item DEFAULT="&lt;>" label="-bus_delimiter" stringID="XST_BUSDELIMITER" value="&lt;>"/>
+      <item DEFAULT="MAINTAIN" stringID="XST_CASE" value="Maintain"/>
+      <item DEFAULT="YES" label="-verilog2001" stringID="XST_VERILOG2001" value="YES"/>
+      <item DEFAULT="YES" label="-fsm_extract" stringID="XST_FSMEXTRACT" value="YES"/>
+      <item DEFAULT="AUTO" label="-fsm_encoding" stringID="XST_FSMENCODING" value="Auto"/>
+      <item DEFAULT="NO" label="-safe_implementation" stringID="XST_SAFEIMPLEMENTATION" value="No"/>
+      <item DEFAULT="YES" stringID="XST_MUXEXTRACT" value="Yes"/>
+      <item DEFAULT="YES" label="-resource_sharing" stringID="XST_RESOURCESHARING" value="YES"/>
+      <item DEFAULT="YES" label="-iobuf" stringID="XST_IOBUF" value="YES"/>
+      <item DEFAULT="YES" label="-equivalent_register_removal" stringID="XST_EQUIVALENTREGISTERREMOVAL" value="YES"/>
+    </section>
+    <section stringID="XST_HDL_SYNTHESIS_REPORT">
+      <item dataType="int" stringID="XST_REGISTERS" value="14">
+        <item dataType="int" stringID="XST_1BIT_REGISTER" value="11"/>
+        <item dataType="int" stringID="XST_3BIT_REGISTER" value="1"/>
+        <item dataType="int" stringID="XST_4BIT_REGISTER" value="1"/>
+        <item dataType="int" stringID="XST_8BIT_REGISTER" value="1"/>
+      </item>
+      <item dataType="int" stringID="XST_COMPARATORS" value="1"></item>
+      <item dataType="int" stringID="XST_TRISTATES" value="2">
+        <item dataType="int" stringID="XST_1BIT_TRISTATE_BUFFER" value="1"/>
+      </item>
+      <item dataType="int" stringID="XST_XORS" value="1">
+        <item dataType="int" stringID="XST_1BIT_XOR2" value="1"/>
+      </item>
+    </section>
+    <section stringID="XST_ADVANCED_HDL_SYNTHESIS_REPORTFOUND_NO_MACRO"/>
+    <section stringID="XST_PARTITION_REPORT">
+      <section stringID="XST_PARTITION_IMPLEMENTATION_STATUS">
+        <section stringID="XST_NO_PARTITIONS_WERE_FOUND_IN_THIS_DESIGN"/>
+      </section>
+    </section>
+    <section stringID="XST_FINAL_REPORT">
+      <section stringID="XST_FINAL_RESULTS">
+        <item stringID="XST_RTL_TOP_LEVEL_OUTPUT_FILE_NAME" value="LAN_IDE_CP.ngr"/>
+        <item stringID="XST_TOP_LEVEL_OUTPUT_FILE_NAME" value="LAN_IDE_CP"/>
+        <item stringID="XST_OUTPUT_FORMAT" value="NGC"/>
+        <item stringID="XST_OPTIMIZATION_GOAL" value="Speed"/>
+        <item stringID="XST_KEEP_HIERARCHY" value="Yes"/>
+      </section>
+      <section stringID="XST_DESIGN_STATISTICS">
+        <item stringID="XST_IOS" value="116"/>
+      </section>
+      <section stringID="XST_CELL_USAGE">
+        <item dataType="int" stringID="XST_BELS" value="322">
+          <item dataType="int" stringID="XST_AND2" value="75"/>
+          <item dataType="int" stringID="XST_AND3" value="16"/>
+          <item dataType="int" stringID="XST_AND4" value="5"/>
+          <item dataType="int" stringID="XST_GND" value="1"/>
+          <item dataType="int" stringID="XST_INV" value="138"/>
+          <item dataType="int" stringID="XST_OR2" value="63"/>
+          <item dataType="int" stringID="XST_VCC" value="1"/>
+          <item dataType="int" stringID="XST_XOR2" value="6"/>
+        </item>
+        <item dataType="int" stringID="XST_FLIPFLOPSLATCHES" value="26">
+          <item dataType="int" stringID="XST_FD" value="6"/>
+          <item dataType="int" stringID="XST_FDC" value="3"/>
+          <item dataType="int" stringID="XST_FDCE" value="17"/>
+        </item>
+        <item dataType="int" stringID="XST_IO_BUFFERS" value="54">
+          <item dataType="int" stringID="XST_IBUF" value="27"/>
+          <item dataType="int" stringID="XST_OBUF" value="10"/>
+        </item>
+      </section>
+    </section>
+    <section stringID="XST_ERRORS_STATISTICS">
+      <item dataType="int" filtered="0" stringID="XST_NUMBER_OF_ERRORS" value="0"/>
+      <item dataType="int" filtered="0" stringID="XST_NUMBER_OF_WARNINGS" value="52"/>
+      <item dataType="int" filtered="0" stringID="XST_NUMBER_OF_INFOS" value="0"/>
+    </section>
+  </application>
+
+</document>
diff --git a/Logic/LAN_IDE/_ngo/netlist.lst b/Logic/LAN_IDE/_ngo/netlist.lst
new file mode 100644
index 0000000..0aeed87
--- /dev/null
+++ b/Logic/LAN_IDE/_ngo/netlist.lst
@@ -0,0 +1,2 @@
+C:\Users\Matze\Amiga\Hardwarehacks\Zorro-LAN-IDE\Logic\LAN_IDE\LAN_IDE_CP.ngc 1481827703
+OK
diff --git a/Logic/LAN_IDE/_pace.ucf b/Logic/LAN_IDE/_pace.ucf
new file mode 100644
index 0000000..4253454
--- /dev/null
+++ b/Logic/LAN_IDE/_pace.ucf
@@ -0,0 +1,68 @@
+#PACE: Start of Constraints generated by PACE
+
+#PACE: Start of PACE I/O Pin Assignments
+NET "A<10>"  LOC = "P59"  ; 
+NET "A<11>"  LOC = "P60"  ; 
+NET "A<12>"  LOC = "P61"  ; 
+NET "A<13>"  LOC = "P64"  ; 
+NET "A<14>"  LOC = "P66"  ; 
+NET "A<15>"  LOC = "P74"  ; 
+NET "A<16>"  LOC = "P97"  ; 
+NET "A<17>"  LOC = "P95"  ; 
+NET "A<18>"  LOC = "P94"  ; 
+NET "A<19>"  LOC = "P92"  ; 
+NET "A<1>"  LOC = "P57"  ; 
+NET "A<20>"  LOC = "P91"  ; 
+NET "A<21>"  LOC = "P88"  ;
+NET "A<22>"  LOC = "P87"  ;
+NET "A<23>"  LOC = "P86"  ;
+NET "A<2>"  LOC = "P54"  ; 
+NET "A<3>"  LOC = "P52"  ; 
+NET "A<4>"  LOC = "P50"  ; 
+NET "A<5>"  LOC = "P49"  ; 
+NET "A<6>"  LOC = "P51"  ; 
+NET "A<7>"  LOC = "P53"  ; 
+NET "A<8>"  LOC = "P56"  ; 
+NET "A<9>"  LOC = "P58"  ; 
+NET "AS"  LOC = "P80"  ;
+NET "AUTOBOOT_OFF"  LOC = "P75"  ;
+NET "BERR"  LOC = "P98"  ;
+NET "C1"  LOC = "P103"  ;
+NET "C3"  LOC = "P102"  ;
+NET "CFIN"  LOC = "P104"  ;
+NET "CFOUT"  LOC = "P105"  ;
+NET "D<0>"  LOC = "P2"  ; 
+NET "D<10>"  LOC = "P41"  ; 
+NET "D<11>"  LOC = "P43"  ; 
+NET "D<12>"  LOC = "P44"  ; 
+NET "D<13>"  LOC = "P45"  ; 
+NET "D<14>"  LOC = "P46"  ; 
+NET "D<15>"  LOC = "P48"  ; 
+NET "D<1>"  LOC = "P17"  ; 
+NET "D<2>"  LOC = "P39"  ; 
+NET "D<3>"  LOC = "P15"  ; 
+NET "D<4>"  LOC = "P21"  ; 
+NET "D<5>"  LOC = "P20"  ; 
+NET "D<6>"  LOC = "P14"  ; 
+NET "D<7>"  LOC = "P16"  ; 
+NET "D<8>"  LOC = "P19"  ; 
+NET "D<9>"  LOC = "P40"  ; 
+NET "DS0"  LOC = "P93"  ;
+NET "DS1"  LOC = "P78"  ;
+NET "DTACK"  LOC = "P85"  ;
+NET "FCS"  LOC = "P77"  ;
+NET "LAN_EN"  LOC = "P76"  ;
+NET "LDS"  LOC = "P82"  ;
+NET "MTACK"  LOC = "P96"  ;
+NET "MTCR"  LOC = "P101"  ;
+NET "OVR"  LOC = "P100"  ;
+NET "OWN"  LOC = "P107"  ;
+NET "SLAVE"  LOC = "P106"  ;
+NET "UDS"  LOC = "P81"  ;
+NET "Z3"  LOC = "P79"  ;
+
+#PACE: Start of PACE Area Constraints
+
+#PACE: Start of PACE Prohibit Constraints
+
+#PACE: End of Constraints generated by PACE
diff --git a/Logic/LAN_IDE/_xmsgs/cpldfit.xmsgs b/Logic/LAN_IDE/_xmsgs/cpldfit.xmsgs
new file mode 100644
index 0000000..043fd08
--- /dev/null
+++ b/Logic/LAN_IDE/_xmsgs/cpldfit.xmsgs
@@ -0,0 +1,213 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- IMPORTANT: This is an internal file that has been generated
+     by the Xilinx ISE software.  Any direct editing or
+     changes made to this file may result in unpredictable
+     behavior or data corruption.  It is strongly advised that
+     users do not edit the contents of this file. -->
+<messages>
+<msg type="warning" file="Cpld" num="0" delta="new" >Unable to retrieve the path to the iSE Project Repository. Will use the default filename of &apos;<arg fmt="%s" index="1">LAN_IDE_CP.ise</arg>&apos;.
+</msg>
+
+<msg type="info" file="Cpld" num="0" delta="new" >Inferring BUFG constraint for signal &apos;<arg fmt="%s" index="1">CLK_EXT</arg>&apos; based upon the LOC constraint &apos;<arg fmt="%s" index="2">P30</arg>&apos;. It is recommended that you declare this BUFG explicitedly in your design. Note that for certain device families the output of a BUFG constraint can not drive a gated clock, and the BUFG constraint will be ignored.
+</msg>
+
+<msg type="warning" file="Cpld" num="936" delta="old" >The output buffer &apos;<arg fmt="%s" index="1">SLAVE_OBUF</arg>&apos; is missing an input and will be deleted.
+</msg>
+
+<msg type="warning" file="Cpld" num="936" delta="old" >The output buffer &apos;<arg fmt="%s" index="1">OWN_OBUF</arg>&apos; is missing an input and will be deleted.
+</msg>
+
+<msg type="warning" file="Cpld" num="936" delta="old" >The output buffer &apos;<arg fmt="%s" index="1">OVR_OBUF</arg>&apos; is missing an input and will be deleted.
+</msg>
+
+<msg type="warning" file="Cpld" num="936" delta="old" >The output buffer &apos;<arg fmt="%s" index="1">MTACK_OBUF</arg>&apos; is missing an input and will be deleted.
+</msg>
+
+<msg type="warning" file="Cpld" num="936" delta="old" >The output buffer &apos;<arg fmt="%s" index="1">LAN_WRH_OBUF</arg>&apos; is missing an input and will be deleted.
+</msg>
+
+<msg type="warning" file="Cpld" num="936" delta="old" >The output buffer &apos;<arg fmt="%s" index="1">LAN_RD_OBUF</arg>&apos; is missing an input and will be deleted.
+</msg>
+
+<msg type="warning" file="Cpld" num="936" delta="old" >The output buffer &apos;<arg fmt="%s" index="1">LAN_EN_OBUF</arg>&apos; is missing an input and will be deleted.
+</msg>
+
+<msg type="warning" file="Cpld" num="936" delta="old" >The output buffer &apos;<arg fmt="%s" index="1">LAN_CS_OBUF</arg>&apos; is missing an input and will be deleted.
+</msg>
+
+<msg type="warning" file="Cpld" num="936" delta="old" >The output buffer &apos;<arg fmt="%s" index="1">LAN_CFG&lt;4&gt;_OBUF</arg>&apos; is missing an input and will be deleted.
+</msg>
+
+<msg type="warning" file="Cpld" num="936" delta="old" >The output buffer &apos;<arg fmt="%s" index="1">LAN_CFG&lt;3&gt;_OBUF</arg>&apos; is missing an input and will be deleted.
+</msg>
+
+<msg type="warning" file="Cpld" num="936" delta="old" >The output buffer &apos;<arg fmt="%s" index="1">LAN_CFG&lt;2&gt;_OBUF</arg>&apos; is missing an input and will be deleted.
+</msg>
+
+<msg type="warning" file="Cpld" num="936" delta="old" >The output buffer &apos;<arg fmt="%s" index="1">LAN_CFG&lt;1&gt;_OBUF</arg>&apos; is missing an input and will be deleted.
+</msg>
+
+<msg type="warning" file="Cpld" num="936" delta="old" >The output buffer &apos;<arg fmt="%s" index="1">INT_OUT_OBUF</arg>&apos; is missing an input and will be deleted.
+</msg>
+
+<msg type="warning" file="Cpld" num="936" delta="old" >The output buffer &apos;<arg fmt="%s" index="1">CP_WE_OBUF</arg>&apos; is missing an input and will be deleted.
+</msg>
+
+<msg type="warning" file="Cpld" num="936" delta="old" >The output buffer &apos;<arg fmt="%s" index="1">CP_RD_OBUF</arg>&apos; is missing an input and will be deleted.
+</msg>
+
+<msg type="warning" file="Cpld" num="936" delta="old" >The output buffer &apos;<arg fmt="%s" index="1">CP_CS_OBUF</arg>&apos; is missing an input and will be deleted.
+</msg>
+
+<msg type="warning" file="Cpld" num="936" delta="old" >The output buffer &apos;<arg fmt="%s" index="1">CFOUT_OBUF</arg>&apos; is missing an input and will be deleted.
+</msg>
+
+<msg type="warning" file="Cpld" num="936" delta="old" >The output buffer &apos;<arg fmt="%s" index="1">A_LAN&lt;9&gt;_OBUF</arg>&apos; is missing an input and will be deleted.
+</msg>
+
+<msg type="warning" file="Cpld" num="936" delta="old" >The output buffer &apos;<arg fmt="%s" index="1">A_LAN&lt;8&gt;_OBUF</arg>&apos; is missing an input and will be deleted.
+</msg>
+
+<msg type="warning" file="Cpld" num="936" delta="old" >The output buffer &apos;<arg fmt="%s" index="1">A_LAN&lt;7&gt;_OBUF</arg>&apos; is missing an input and will be deleted.
+</msg>
+
+<msg type="warning" file="Cpld" num="936" delta="old" >The output buffer &apos;<arg fmt="%s" index="1">A_LAN&lt;6&gt;_OBUF</arg>&apos; is missing an input and will be deleted.
+</msg>
+
+<msg type="warning" file="Cpld" num="936" delta="old" >The output buffer &apos;<arg fmt="%s" index="1">A_LAN&lt;5&gt;_OBUF</arg>&apos; is missing an input and will be deleted.
+</msg>
+
+<msg type="warning" file="Cpld" num="936" delta="old" >The output buffer &apos;<arg fmt="%s" index="1">A_LAN&lt;4&gt;_OBUF</arg>&apos; is missing an input and will be deleted.
+</msg>
+
+<msg type="warning" file="Cpld" num="936" delta="old" >The output buffer &apos;<arg fmt="%s" index="1">A_LAN&lt;3&gt;_OBUF</arg>&apos; is missing an input and will be deleted.
+</msg>
+
+<msg type="warning" file="Cpld" num="936" delta="old" >The output buffer &apos;<arg fmt="%s" index="1">A_LAN&lt;2&gt;_OBUF</arg>&apos; is missing an input and will be deleted.
+</msg>
+
+<msg type="warning" file="Cpld" num="936" delta="old" >The output buffer &apos;<arg fmt="%s" index="1">A_LAN&lt;1&gt;_OBUF</arg>&apos; is missing an input and will be deleted.
+</msg>
+
+<msg type="warning" file="Cpld" num="936" delta="old" >The output buffer &apos;<arg fmt="%s" index="1">A_LAN&lt;13&gt;_OBUF</arg>&apos; is missing an input and will be deleted.
+</msg>
+
+<msg type="warning" file="Cpld" num="936" delta="old" >The output buffer &apos;<arg fmt="%s" index="1">A_LAN&lt;12&gt;_OBUF</arg>&apos; is missing an input and will be deleted.
+</msg>
+
+<msg type="warning" file="Cpld" num="936" delta="old" >The output buffer &apos;<arg fmt="%s" index="1">A_LAN&lt;11&gt;_OBUF</arg>&apos; is missing an input and will be deleted.
+</msg>
+
+<msg type="warning" file="Cpld" num="936" delta="old" >The output buffer &apos;<arg fmt="%s" index="1">A_LAN&lt;10&gt;_OBUF</arg>&apos; is missing an input and will be deleted.
+</msg>
+
+<msg type="warning" file="Cpld" num="936" delta="old" >The output buffer &apos;<arg fmt="%s" index="1">A_LAN&lt;0&gt;_OBUF</arg>&apos; is missing an input and will be deleted.
+</msg>
+
+<msg type="warning" file="Cpld" num="1007" delta="old" >Removing unused input(s) &apos;<arg fmt="%s" index="1">A&lt;14&gt;</arg>&apos;.  The input(s) are unused after optimization. Please verify functionality via simulation.
+</msg>
+
+<msg type="warning" file="Cpld" num="1007" delta="old" >Removing unused input(s) &apos;<arg fmt="%s" index="1">A&lt;15&gt;</arg>&apos;.  The input(s) are unused after optimization. Please verify functionality via simulation.
+</msg>
+
+<msg type="warning" file="Cpld" num="1007" delta="old" >Removing unused input(s) &apos;<arg fmt="%s" index="1">A&lt;7&gt;</arg>&apos;.  The input(s) are unused after optimization. Please verify functionality via simulation.
+</msg>
+
+<msg type="warning" file="Cpld" num="1007" delta="old" >Removing unused input(s) &apos;<arg fmt="%s" index="1">A&lt;8&gt;</arg>&apos;.  The input(s) are unused after optimization. Please verify functionality via simulation.
+</msg>
+
+<msg type="warning" file="Cpld" num="1007" delta="old" >Removing unused input(s) &apos;<arg fmt="%s" index="1">CFIN</arg>&apos;.  The input(s) are unused after optimization. Please verify functionality via simulation.
+</msg>
+
+<msg type="warning" file="Cpld" num="1007" delta="old" >Removing unused input(s) &apos;<arg fmt="%s" index="1">CLK_EXT</arg>&apos;.  The input(s) are unused after optimization. Please verify functionality via simulation.
+</msg>
+
+<msg type="warning" file="Cpld" num="1007" delta="old" >Removing unused input(s) &apos;<arg fmt="%s" index="1">CP_IRQ</arg>&apos;.  The input(s) are unused after optimization. Please verify functionality via simulation.
+</msg>
+
+<msg type="warning" file="Cpld" num="1007" delta="old" >Removing unused input(s) &apos;<arg fmt="%s" index="1">DQ&lt;0&gt;</arg>&apos;.  The input(s) are unused after optimization. Please verify functionality via simulation.
+</msg>
+
+<msg type="warning" file="Cpld" num="1007" delta="old" >Removing unused input(s) &apos;<arg fmt="%s" index="1">DQ&lt;10&gt;</arg>&apos;.  The input(s) are unused after optimization. Please verify functionality via simulation.
+</msg>
+
+<msg type="warning" file="Cpld" num="1007" delta="old" >Removing unused input(s) &apos;<arg fmt="%s" index="1">DQ&lt;11&gt;</arg>&apos;.  The input(s) are unused after optimization. Please verify functionality via simulation.
+</msg>
+
+<msg type="warning" file="Cpld" num="1007" delta="old" >Removing unused input(s) &apos;<arg fmt="%s" index="1">DQ&lt;12&gt;</arg>&apos;.  The input(s) are unused after optimization. Please verify functionality via simulation.
+</msg>
+
+<msg type="warning" file="Cpld" num="1007" delta="old" >Removing unused input(s) &apos;<arg fmt="%s" index="1">DQ&lt;13&gt;</arg>&apos;.  The input(s) are unused after optimization. Please verify functionality via simulation.
+</msg>
+
+<msg type="warning" file="Cpld" num="1007" delta="old" >Removing unused input(s) &apos;<arg fmt="%s" index="1">DQ&lt;14&gt;</arg>&apos;.  The input(s) are unused after optimization. Please verify functionality via simulation.
+</msg>
+
+<msg type="warning" file="Cpld" num="1007" delta="old" >Removing unused input(s) &apos;<arg fmt="%s" index="1">DQ&lt;15&gt;</arg>&apos;.  The input(s) are unused after optimization. Please verify functionality via simulation.
+</msg>
+
+<msg type="warning" file="Cpld" num="1007" delta="old" >Removing unused input(s) &apos;<arg fmt="%s" index="1">DQ&lt;1&gt;</arg>&apos;.  The input(s) are unused after optimization. Please verify functionality via simulation.
+</msg>
+
+<msg type="warning" file="Cpld" num="1007" delta="old" >Removing unused input(s) &apos;<arg fmt="%s" index="1">DQ&lt;2&gt;</arg>&apos;.  The input(s) are unused after optimization. Please verify functionality via simulation.
+</msg>
+
+<msg type="warning" file="Cpld" num="1007" delta="old" >Removing unused input(s) &apos;<arg fmt="%s" index="1">DQ&lt;3&gt;</arg>&apos;.  The input(s) are unused after optimization. Please verify functionality via simulation.
+</msg>
+
+<msg type="warning" file="Cpld" num="1007" delta="old" >Removing unused input(s) &apos;<arg fmt="%s" index="1">DQ&lt;4&gt;</arg>&apos;.  The input(s) are unused after optimization. Please verify functionality via simulation.
+</msg>
+
+<msg type="warning" file="Cpld" num="1007" delta="old" >Removing unused input(s) &apos;<arg fmt="%s" index="1">DQ&lt;5&gt;</arg>&apos;.  The input(s) are unused after optimization. Please verify functionality via simulation.
+</msg>
+
+<msg type="warning" file="Cpld" num="1007" delta="old" >Removing unused input(s) &apos;<arg fmt="%s" index="1">DQ&lt;6&gt;</arg>&apos;.  The input(s) are unused after optimization. Please verify functionality via simulation.
+</msg>
+
+<msg type="warning" file="Cpld" num="1007" delta="old" >Removing unused input(s) &apos;<arg fmt="%s" index="1">DQ&lt;7&gt;</arg>&apos;.  The input(s) are unused after optimization. Please verify functionality via simulation.
+</msg>
+
+<msg type="warning" file="Cpld" num="1007" delta="old" >Removing unused input(s) &apos;<arg fmt="%s" index="1">DQ&lt;8&gt;</arg>&apos;.  The input(s) are unused after optimization. Please verify functionality via simulation.
+</msg>
+
+<msg type="warning" file="Cpld" num="1007" delta="old" >Removing unused input(s) &apos;<arg fmt="%s" index="1">DQ&lt;9&gt;</arg>&apos;.  The input(s) are unused after optimization. Please verify functionality via simulation.
+</msg>
+
+<msg type="warning" file="Cpld" num="1007" delta="old" >Removing unused input(s) &apos;<arg fmt="%s" index="1">DS0</arg>&apos;.  The input(s) are unused after optimization. Please verify functionality via simulation.
+</msg>
+
+<msg type="warning" file="Cpld" num="1007" delta="old" >Removing unused input(s) &apos;<arg fmt="%s" index="1">DS1</arg>&apos;.  The input(s) are unused after optimization. Please verify functionality via simulation.
+</msg>
+
+<msg type="warning" file="Cpld" num="1007" delta="old" >Removing unused input(s) &apos;<arg fmt="%s" index="1">FCS</arg>&apos;.  The input(s) are unused after optimization. Please verify functionality via simulation.
+</msg>
+
+<msg type="warning" file="Cpld" num="1007" delta="old" >Removing unused input(s) &apos;<arg fmt="%s" index="1">IDE_WAIT</arg>&apos;.  The input(s) are unused after optimization. Please verify functionality via simulation.
+</msg>
+
+<msg type="warning" file="Cpld" num="1007" delta="old" >Removing unused input(s) &apos;<arg fmt="%s" index="1">LAN_INT</arg>&apos;.  The input(s) are unused after optimization. Please verify functionality via simulation.
+</msg>
+
+<msg type="warning" file="Cpld" num="1007" delta="old" >Removing unused input(s) &apos;<arg fmt="%s" index="1">LDS</arg>&apos;.  The input(s) are unused after optimization. Please verify functionality via simulation.
+</msg>
+
+<msg type="warning" file="Cpld" num="1007" delta="old" >Removing unused input(s) &apos;<arg fmt="%s" index="1">MTCR</arg>&apos;.  The input(s) are unused after optimization. Please verify functionality via simulation.
+</msg>
+
+<msg type="warning" file="Cpld" num="1007" delta="old" >Removing unused input(s) &apos;<arg fmt="%s" index="1">Z3</arg>&apos;.  The input(s) are unused after optimization. Please verify functionality via simulation.
+</msg>
+
+<msg type="warning" file="Cpld" num="896" delta="new" >Unable to map all desired signals into function block, FB<arg fmt="%d" index="1">3</arg>, because too many function block product terms are required. Buffering output signal <arg fmt="%s" index="2">D&lt;12&gt;</arg> to allow all signals assigned to this function block to be placed.
+</msg>
+
+<msg type="warning" file="Cpld" num="896" delta="new" >Unable to map all desired signals into function block, FB<arg fmt="%d" index="1">3</arg>, because too many function block product terms are required. Buffering output signal <arg fmt="%s" index="2">D&lt;14&gt;</arg> to allow all signals assigned to this function block to be placed.
+</msg>
+
+<msg type="warning" file="Cpld" num="896" delta="new" >Unable to map all desired signals into function block, FB<arg fmt="%d" index="1">3</arg>, because too many function block product terms are required. Buffering output signal <arg fmt="%s" index="2">D&lt;13&gt;</arg> to allow all signals assigned to this function block to be placed.
+</msg>
+
+<msg type="warning" file="Cpld" num="896" delta="new" >Unable to map all desired signals into function block, FB<arg fmt="%d" index="1">3</arg>, because too many function block product terms are required. Buffering output signal <arg fmt="%s" index="2">D&lt;15&gt;</arg> to allow all signals assigned to this function block to be placed.
+</msg>
+
+</messages>
+
diff --git a/Logic/LAN_IDE/_xmsgs/hprep6.xmsgs b/Logic/LAN_IDE/_xmsgs/hprep6.xmsgs
new file mode 100644
index 0000000..f84336a
--- /dev/null
+++ b/Logic/LAN_IDE/_xmsgs/hprep6.xmsgs
@@ -0,0 +1,9 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- IMPORTANT: This is an internal file that has been generated
+     by the Xilinx ISE software.  Any direct editing or
+     changes made to this file may result in unpredictable
+     behavior or data corruption.  It is strongly advised that
+     users do not edit the contents of this file. -->
+<messages>
+</messages>
+
diff --git a/Logic/LAN_IDE/_xmsgs/ngdbuild.xmsgs b/Logic/LAN_IDE/_xmsgs/ngdbuild.xmsgs
new file mode 100644
index 0000000..d581cd4
--- /dev/null
+++ b/Logic/LAN_IDE/_xmsgs/ngdbuild.xmsgs
@@ -0,0 +1,69 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- IMPORTANT: This is an internal file that has been generated
+     by the Xilinx ISE software.  Any direct editing or
+     changes made to this file may result in unpredictable
+     behavior or data corruption.  It is strongly advised that
+     users do not edit the contents of this file. -->
+<messages>
+<msg type="warning" file="NgdBuild" num="470" delta="old" ><arg fmt="%s" index="1">bidirect</arg> pad net &apos;<arg fmt="%s" index="2">DQ&lt;0&gt;</arg>&apos; has no legal driver
+</msg>
+
+<msg type="warning" file="NgdBuild" num="470" delta="old" ><arg fmt="%s" index="1">bidirect</arg> pad net &apos;<arg fmt="%s" index="2">DQ&lt;1&gt;</arg>&apos; has no legal driver
+</msg>
+
+<msg type="warning" file="NgdBuild" num="470" delta="old" ><arg fmt="%s" index="1">bidirect</arg> pad net &apos;<arg fmt="%s" index="2">DQ&lt;2&gt;</arg>&apos; has no legal driver
+</msg>
+
+<msg type="warning" file="NgdBuild" num="470" delta="old" ><arg fmt="%s" index="1">bidirect</arg> pad net &apos;<arg fmt="%s" index="2">DQ&lt;3&gt;</arg>&apos; has no legal driver
+</msg>
+
+<msg type="warning" file="NgdBuild" num="470" delta="old" ><arg fmt="%s" index="1">bidirect</arg> pad net &apos;<arg fmt="%s" index="2">DQ&lt;4&gt;</arg>&apos; has no legal driver
+</msg>
+
+<msg type="warning" file="NgdBuild" num="470" delta="old" ><arg fmt="%s" index="1">bidirect</arg> pad net &apos;<arg fmt="%s" index="2">DQ&lt;10&gt;</arg>&apos; has no legal driver
+</msg>
+
+<msg type="warning" file="NgdBuild" num="470" delta="old" ><arg fmt="%s" index="1">bidirect</arg> pad net &apos;<arg fmt="%s" index="2">DQ&lt;5&gt;</arg>&apos; has no legal driver
+</msg>
+
+<msg type="warning" file="NgdBuild" num="470" delta="old" ><arg fmt="%s" index="1">bidirect</arg> pad net &apos;<arg fmt="%s" index="2">DQ&lt;11&gt;</arg>&apos; has no legal driver
+</msg>
+
+<msg type="warning" file="NgdBuild" num="470" delta="old" ><arg fmt="%s" index="1">bidirect</arg> pad net &apos;<arg fmt="%s" index="2">DQ&lt;6&gt;</arg>&apos; has no legal driver
+</msg>
+
+<msg type="warning" file="NgdBuild" num="470" delta="old" ><arg fmt="%s" index="1">bidirect</arg> pad net &apos;<arg fmt="%s" index="2">DQ&lt;12&gt;</arg>&apos; has no legal driver
+</msg>
+
+<msg type="warning" file="NgdBuild" num="470" delta="old" ><arg fmt="%s" index="1">bidirect</arg> pad net &apos;<arg fmt="%s" index="2">DQ&lt;7&gt;</arg>&apos; has no legal driver
+</msg>
+
+<msg type="warning" file="NgdBuild" num="470" delta="old" ><arg fmt="%s" index="1">bidirect</arg> pad net &apos;<arg fmt="%s" index="2">DQ&lt;13&gt;</arg>&apos; has no legal driver
+</msg>
+
+<msg type="warning" file="NgdBuild" num="470" delta="old" ><arg fmt="%s" index="1">bidirect</arg> pad net &apos;<arg fmt="%s" index="2">DQ&lt;8&gt;</arg>&apos; has no legal driver
+</msg>
+
+<msg type="warning" file="NgdBuild" num="470" delta="old" ><arg fmt="%s" index="1">bidirect</arg> pad net &apos;<arg fmt="%s" index="2">DQ&lt;14&gt;</arg>&apos; has no legal driver
+</msg>
+
+<msg type="warning" file="NgdBuild" num="470" delta="old" ><arg fmt="%s" index="1">bidirect</arg> pad net &apos;<arg fmt="%s" index="2">DQ&lt;9&gt;</arg>&apos; has no legal driver
+</msg>
+
+<msg type="warning" file="NgdBuild" num="470" delta="old" ><arg fmt="%s" index="1">bidirect</arg> pad net &apos;<arg fmt="%s" index="2">DQ&lt;15&gt;</arg>&apos; has no legal driver
+</msg>
+
+<msg type="warning" file="NgdBuild" num="470" delta="old" ><arg fmt="%s" index="1">bidirect</arg> pad net &apos;<arg fmt="%s" index="2">A&lt;14&gt;</arg>&apos; has no legal driver
+</msg>
+
+<msg type="warning" file="NgdBuild" num="470" delta="old" ><arg fmt="%s" index="1">bidirect</arg> pad net &apos;<arg fmt="%s" index="2">A&lt;15&gt;</arg>&apos; has no legal driver
+</msg>
+
+<msg type="warning" file="NgdBuild" num="470" delta="old" ><arg fmt="%s" index="1">bidirect</arg> pad net &apos;<arg fmt="%s" index="2">A&lt;7&gt;</arg>&apos; has no legal driver
+</msg>
+
+<msg type="warning" file="NgdBuild" num="470" delta="old" ><arg fmt="%s" index="1">bidirect</arg> pad net &apos;<arg fmt="%s" index="2">A&lt;8&gt;</arg>&apos; has no legal driver
+</msg>
+
+</messages>
+
diff --git a/Logic/LAN_IDE/_xmsgs/taengine.xmsgs b/Logic/LAN_IDE/_xmsgs/taengine.xmsgs
new file mode 100644
index 0000000..f84336a
--- /dev/null
+++ b/Logic/LAN_IDE/_xmsgs/taengine.xmsgs
@@ -0,0 +1,9 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- IMPORTANT: This is an internal file that has been generated
+     by the Xilinx ISE software.  Any direct editing or
+     changes made to this file may result in unpredictable
+     behavior or data corruption.  It is strongly advised that
+     users do not edit the contents of this file. -->
+<messages>
+</messages>
+
diff --git a/Logic/LAN_IDE/_xmsgs/tsim.xmsgs b/Logic/LAN_IDE/_xmsgs/tsim.xmsgs
new file mode 100644
index 0000000..f84336a
--- /dev/null
+++ b/Logic/LAN_IDE/_xmsgs/tsim.xmsgs
@@ -0,0 +1,9 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- IMPORTANT: This is an internal file that has been generated
+     by the Xilinx ISE software.  Any direct editing or
+     changes made to this file may result in unpredictable
+     behavior or data corruption.  It is strongly advised that
+     users do not edit the contents of this file. -->
+<messages>
+</messages>
+
diff --git a/Logic/LAN_IDE/_xmsgs/xst.xmsgs b/Logic/LAN_IDE/_xmsgs/xst.xmsgs
new file mode 100644
index 0000000..280b83c
--- /dev/null
+++ b/Logic/LAN_IDE/_xmsgs/xst.xmsgs
@@ -0,0 +1,165 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- IMPORTANT: This is an internal file that has been generated
+     by the Xilinx ISE software.  Any direct editing or
+     changes made to this file may result in unpredictable
+     behavior or data corruption.  It is strongly advised that
+     users do not edit the contents of this file. -->
+<messages>
+<msg type="warning" file="Xst" num="2565" delta="new" >Inout &lt;<arg fmt="%s" index="1">DQ&lt;0&gt;</arg>&gt; is never assigned.
+</msg>
+
+<msg type="warning" file="Xst" num="1306" delta="new" >Output &lt;<arg fmt="%s" index="1">SLAVE</arg>&gt; is never assigned.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">IDE_WAIT</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="2565" delta="new" >Inout &lt;<arg fmt="%s" index="1">DQ&lt;1&gt;</arg>&gt; is never assigned.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">LDS</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="1306" delta="new" >Output &lt;<arg fmt="%s" index="1">LAN_CS</arg>&gt; is never assigned.
+</msg>
+
+<msg type="warning" file="Xst" num="2565" delta="new" >Inout &lt;<arg fmt="%s" index="1">DQ&lt;2&gt;</arg>&gt; is never assigned.
+</msg>
+
+<msg type="warning" file="Xst" num="1306" delta="new" >Output &lt;<arg fmt="%s" index="1">LAN_EN</arg>&gt; is never assigned.
+</msg>
+
+<msg type="warning" file="Xst" num="2565" delta="new" >Inout &lt;<arg fmt="%s" index="1">DQ&lt;3&gt;</arg>&gt; is never assigned.
+</msg>
+
+<msg type="warning" file="Xst" num="2565" delta="new" >Inout &lt;<arg fmt="%s" index="1">DQ&lt;4&gt;</arg>&gt; is never assigned.
+</msg>
+
+<msg type="warning" file="Xst" num="2565" delta="new" >Inout &lt;<arg fmt="%s" index="1">DQ&lt;10&gt;</arg>&gt; is never assigned.
+</msg>
+
+<msg type="warning" file="Xst" num="2565" delta="new" >Inout &lt;<arg fmt="%s" index="1">DQ&lt;5&gt;</arg>&gt; is never assigned.
+</msg>
+
+<msg type="warning" file="Xst" num="2565" delta="new" >Inout &lt;<arg fmt="%s" index="1">DQ&lt;11&gt;</arg>&gt; is never assigned.
+</msg>
+
+<msg type="warning" file="Xst" num="2565" delta="new" >Inout &lt;<arg fmt="%s" index="1">DQ&lt;6&gt;</arg>&gt; is never assigned.
+</msg>
+
+<msg type="warning" file="Xst" num="2565" delta="new" >Inout &lt;<arg fmt="%s" index="1">DQ&lt;12&gt;</arg>&gt; is never assigned.
+</msg>
+
+<msg type="warning" file="Xst" num="1306" delta="new" >Output &lt;<arg fmt="%s" index="1">CFOUT</arg>&gt; is never assigned.
+</msg>
+
+<msg type="warning" file="Xst" num="2565" delta="new" >Inout &lt;<arg fmt="%s" index="1">DQ&lt;7&gt;</arg>&gt; is never assigned.
+</msg>
+
+<msg type="warning" file="Xst" num="2565" delta="new" >Inout &lt;<arg fmt="%s" index="1">DQ&lt;13&gt;</arg>&gt; is never assigned.
+</msg>
+
+<msg type="warning" file="Xst" num="1306" delta="new" >Output &lt;<arg fmt="%s" index="1">LAN_WRH</arg>&gt; is never assigned.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">DS0</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">DS1</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="2565" delta="new" >Inout &lt;<arg fmt="%s" index="1">DQ&lt;8&gt;</arg>&gt; is never assigned.
+</msg>
+
+<msg type="warning" file="Xst" num="2565" delta="new" >Inout &lt;<arg fmt="%s" index="1">DQ&lt;14&gt;</arg>&gt; is never assigned.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">FCS</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="2565" delta="new" >Inout &lt;<arg fmt="%s" index="1">DQ&lt;9&gt;</arg>&gt; is never assigned.
+</msg>
+
+<msg type="warning" file="Xst" num="2565" delta="new" >Inout &lt;<arg fmt="%s" index="1">DQ&lt;15&gt;</arg>&gt; is never assigned.
+</msg>
+
+<msg type="warning" file="Xst" num="1306" delta="new" >Output &lt;<arg fmt="%s" index="1">CP_CS</arg>&gt; is never assigned.
+</msg>
+
+<msg type="warning" file="Xst" num="1306" delta="new" >Output &lt;<arg fmt="%s" index="1">LAN_CFG</arg>&gt; is never assigned.
+</msg>
+
+<msg type="warning" file="Xst" num="1306" delta="new" >Output &lt;<arg fmt="%s" index="1">MTACK</arg>&gt; is never assigned.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">LAN_INT</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="1306" delta="new" >Output &lt;<arg fmt="%s" index="1">INT_OUT</arg>&gt; is never assigned.
+</msg>
+
+<msg type="warning" file="Xst" num="1306" delta="new" >Output &lt;<arg fmt="%s" index="1">LAN_RD</arg>&gt; is never assigned.
+</msg>
+
+<msg type="warning" file="Xst" num="2565" delta="new" >Inout &lt;<arg fmt="%s" index="1">A&lt;14&gt;</arg>&gt; is never assigned.
+</msg>
+
+<msg type="warning" file="Xst" num="2565" delta="new" >Inout &lt;<arg fmt="%s" index="1">A&lt;15&gt;</arg>&gt; is never assigned.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">CP_IRQ</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="1306" delta="new" >Output &lt;<arg fmt="%s" index="1">CP_RD</arg>&gt; is never assigned.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">Z3</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="2565" delta="new" >Inout &lt;<arg fmt="%s" index="1">A&lt;7&gt;</arg>&gt; is never assigned.
+</msg>
+
+<msg type="warning" file="Xst" num="2565" delta="new" >Inout &lt;<arg fmt="%s" index="1">A&lt;8&gt;</arg>&gt; is never assigned.
+</msg>
+
+<msg type="warning" file="Xst" num="1306" delta="new" >Output &lt;<arg fmt="%s" index="1">CP_WE</arg>&gt; is never assigned.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">CFIN</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">CLK_EXT</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="1306" delta="new" >Output &lt;<arg fmt="%s" index="1">OVR</arg>&gt; is never assigned.
+</msg>
+
+<msg type="warning" file="Xst" num="1306" delta="new" >Output &lt;<arg fmt="%s" index="1">OWN</arg>&gt; is never assigned.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">MTCR</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="1306" delta="new" >Output &lt;<arg fmt="%s" index="1">A_LAN</arg>&gt; is never assigned.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal &lt;<arg fmt="%s" index="1">SHUT_UP&lt;2&gt;</arg>&gt; is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal &lt;<arg fmt="%s" index="1">SHUT_UP&lt;0&gt;</arg>&gt; is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal &lt;<arg fmt="%s" index="1">LAN_BASEADR</arg>&gt; is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal &lt;<arg fmt="%s" index="1">DTACK_S</arg>&gt; is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal &lt;<arg fmt="%s" index="1">CP_BASEADR</arg>&gt; is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal &lt;<arg fmt="%s" index="1">AS_D</arg>&gt; is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+</messages>
+
diff --git a/Logic/LAN_IDE/iseconfig/LAN_IDE_CP.xreport b/Logic/LAN_IDE/iseconfig/LAN_IDE_CP.xreport
index fd3309e..bb55510 100644
--- a/Logic/LAN_IDE/iseconfig/LAN_IDE_CP.xreport
+++ b/Logic/LAN_IDE/iseconfig/LAN_IDE_CP.xreport
@@ -1,11 +1,11 @@
 <?xml version='1.0' encoding='UTF-8'?>
 <report-views version="2.0" >
  <header>
-  <DateModified>2016-12-13T22:08:30</DateModified>
+  <DateModified>2016-12-15T18:39:52</DateModified>
   <ModuleName>LAN_IDE_CP</ModuleName>
   <SummaryTimeStamp>Unknown</SummaryTimeStamp>
   <SavedFilePath>C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/iseconfig/LAN_IDE_CP.xreport</SavedFilePath>
-  <ImplementationReportsDirectory>C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE</ImplementationReportsDirectory>
+  <ImplementationReportsDirectory>C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE\</ImplementationReportsDirectory>
   <DateInitialized>2016-12-13T22:08:29</DateInitialized>
   <EnableMessageFiltering>false</EnableMessageFiltering>
  </header>
diff --git a/Logic/LAN_IDE/pepExtractor.prj b/Logic/LAN_IDE/pepExtractor.prj
new file mode 100644
index 0000000..30d69dc
--- /dev/null
+++ b/Logic/LAN_IDE/pepExtractor.prj
@@ -0,0 +1 @@
+work	"C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.vhd"
diff --git a/Logic/LAN_IDE/pinlist.lfp b/Logic/LAN_IDE/pinlist.lfp
new file mode 100644
index 0000000..0fdeeb5
--- /dev/null
+++ b/Logic/LAN_IDE/pinlist.lfp
@@ -0,0 +1,93 @@
+# begin LFP file C:\Users\Matze\Amiga\Hardwarehacks\Zorro-LAN-IDE\Logic\LAN_IDE\pinlist.lfp
+designfile LAN_IDE_CP.vhd
+parttype xc95144xl-tq144-10
+bus_delimiter 0;
+set_busdelim_onsave 1;
+IO_GROUP "A"  ;
+IO_GROUP "D"  ;
+IO_GROUP "DQ"  ;
+IO_GROUP "A_LAN"  ;
+IO_GROUP "ROM_B"  ;
+IO_GROUP "IDE_A"  ;
+IO_GROUP "IDE_CS"  ;
+IO_GROUP "LAN_CFG"  ;
+NET "A<23>" IO_GROUP="A"  ;
+NET "A<22>" IO_GROUP="A"  ;
+NET "A<21>" IO_GROUP="A"  ;
+NET "A<20>" IO_GROUP="A"  ;
+NET "A<19>" IO_GROUP="A"  ;
+NET "A<18>" IO_GROUP="A"  ;
+NET "A<17>" IO_GROUP="A"  ;
+NET "A<16>" IO_GROUP="A"  ;
+NET "A<15>" IO_GROUP="A"  ;
+NET "A<14>" IO_GROUP="A"  ;
+NET "A<13>" IO_GROUP="A"  ;
+NET "A<12>" IO_GROUP="A"  ;
+NET "A<11>" IO_GROUP="A"  ;
+NET "A<10>" IO_GROUP="A"  ;
+NET "A<9>" IO_GROUP="A"  ;
+NET "A<8>" IO_GROUP="A"  ;
+NET "A<7>" IO_GROUP="A"  ;
+NET "A<6>" IO_GROUP="A"  ;
+NET "A<5>" IO_GROUP="A"  ;
+NET "A<4>" IO_GROUP="A"  ;
+NET "A<3>" IO_GROUP="A"  ;
+NET "A<2>" IO_GROUP="A"  ;
+NET "A<1>" IO_GROUP="A"  ;
+NET "D<15>" IO_GROUP="D"  ;
+NET "D<14>" IO_GROUP="D"  ;
+NET "D<13>" IO_GROUP="D"  ;
+NET "D<12>" IO_GROUP="D"  ;
+NET "D<11>" IO_GROUP="D"  ;
+NET "D<10>" IO_GROUP="D"  ;
+NET "D<9>" IO_GROUP="D"  ;
+NET "D<8>" IO_GROUP="D"  ;
+NET "D<7>" IO_GROUP="D"  ;
+NET "D<6>" IO_GROUP="D"  ;
+NET "D<5>" IO_GROUP="D"  ;
+NET "D<4>" IO_GROUP="D"  ;
+NET "D<3>" IO_GROUP="D"  ;
+NET "D<2>" IO_GROUP="D"  ;
+NET "D<1>" IO_GROUP="D"  ;
+NET "D<0>" IO_GROUP="D"  ;
+NET "DQ<15>" IO_GROUP="DQ"  ;
+NET "DQ<14>" IO_GROUP="DQ"  ;
+NET "DQ<13>" IO_GROUP="DQ"  ;
+NET "DQ<12>" IO_GROUP="DQ"  ;
+NET "DQ<11>" IO_GROUP="DQ"  ;
+NET "DQ<10>" IO_GROUP="DQ"  ;
+NET "DQ<9>" IO_GROUP="DQ"  ;
+NET "DQ<8>" IO_GROUP="DQ"  ;
+NET "DQ<7>" IO_GROUP="DQ"  ;
+NET "DQ<6>" IO_GROUP="DQ"  ;
+NET "DQ<5>" IO_GROUP="DQ"  ;
+NET "DQ<4>" IO_GROUP="DQ"  ;
+NET "DQ<3>" IO_GROUP="DQ"  ;
+NET "DQ<2>" IO_GROUP="DQ"  ;
+NET "DQ<1>" IO_GROUP="DQ"  ;
+NET "DQ<0>" IO_GROUP="DQ"  ;
+NET "A_LAN<13>" IO_GROUP="A_LAN"  ;
+NET "A_LAN<12>" IO_GROUP="A_LAN"  ;
+NET "A_LAN<11>" IO_GROUP="A_LAN"  ;
+NET "A_LAN<10>" IO_GROUP="A_LAN"  ;
+NET "A_LAN<9>" IO_GROUP="A_LAN"  ;
+NET "A_LAN<8>" IO_GROUP="A_LAN"  ;
+NET "A_LAN<7>" IO_GROUP="A_LAN"  ;
+NET "A_LAN<6>" IO_GROUP="A_LAN"  ;
+NET "A_LAN<5>" IO_GROUP="A_LAN"  ;
+NET "A_LAN<4>" IO_GROUP="A_LAN"  ;
+NET "A_LAN<3>" IO_GROUP="A_LAN"  ;
+NET "A_LAN<2>" IO_GROUP="A_LAN"  ;
+NET "A_LAN<1>" IO_GROUP="A_LAN"  ;
+NET "A_LAN<0>" IO_GROUP="A_LAN"  ;
+NET "ROM_B<1>" IO_GROUP="ROM_B"  ;
+NET "ROM_B<0>" IO_GROUP="ROM_B"  ;
+NET "IDE_A<2>" IO_GROUP="IDE_A"  ;
+NET "IDE_A<1>" IO_GROUP="IDE_A"  ;
+NET "IDE_A<0>" IO_GROUP="IDE_A"  ;
+NET "IDE_CS<1>" IO_GROUP="IDE_CS"  ;
+NET "IDE_CS<0>" IO_GROUP="IDE_CS"  ;
+NET "LAN_CFG<4>" IO_GROUP="LAN_CFG"  ;
+NET "LAN_CFG<3>" IO_GROUP="LAN_CFG"  ;
+NET "LAN_CFG<2>" IO_GROUP="LAN_CFG"  ;
+NET "LAN_CFG<1>" IO_GROUP="LAN_CFG"  ;
diff --git a/Logic/LAN_IDE/pinlist.ucf b/Logic/LAN_IDE/pinlist.ucf
new file mode 100644
index 0000000..92a4910
--- /dev/null
+++ b/Logic/LAN_IDE/pinlist.ucf
@@ -0,0 +1,125 @@
+#PACE: Start of Constraints generated by PACE
+
+#PACE: Start of PACE I/O Pin Assignments
+NET "A<10>"  LOC = "P59"  ; 
+NET "A<11>"  LOC = "P60"  ; 
+NET "A<12>"  LOC = "P61"  ; 
+NET "A<13>"  LOC = "P64"  ; 
+NET "A<14>"  LOC = "P66"  ; 
+NET "A<15>"  LOC = "P74"  ; 
+NET "A<16>"  LOC = "P97"  ; 
+NET "A<17>"  LOC = "P95"  ; 
+NET "A<18>"  LOC = "P94"  ; 
+NET "A<19>"  LOC = "P92"  ; 
+NET "A<1>"  LOC = "P57"  ; 
+NET "A<20>"  LOC = "P91"  ; 
+NET "A<21>"  LOC = "P88"  ; 
+NET "A<22>"  LOC = "P87"  ; 
+NET "A<23>"  LOC = "P86"  ; 
+NET "A<2>"  LOC = "P54"  ; 
+NET "A<3>"  LOC = "P52"  ; 
+NET "A<4>"  LOC = "P50"  ; 
+NET "A<5>"  LOC = "P49"  ; 
+NET "A<6>"  LOC = "P51"  ; 
+NET "A<7>"  LOC = "P53"  ; 
+NET "A<8>"  LOC = "P56"  ; 
+NET "A<9>"  LOC = "P58"  ; 
+NET "A_LAN<0>"  LOC = "P4"  ;
+NET "A_LAN<10>"  LOC = "P138"  ;
+NET "A_LAN<11>"  LOC = "P139"  ;
+NET "A_LAN<12>"  LOC = "P137"  ;
+NET "A_LAN<13>"  LOC = "P136"  ;
+NET "A_LAN<1>"  LOC = "P3"  ;
+NET "A_LAN<2>"  LOC = "P6"  ;
+NET "A_LAN<3>"  LOC = "P5"  ;
+NET "A_LAN<4>"  LOC = "P9"  ;
+NET "A_LAN<5>"  LOC = "P7"  ;
+NET "A_LAN<6>"  LOC = "P11"  ;
+NET "A_LAN<7>"  LOC = "P10"  ;
+NET "A_LAN<8>"  LOC = "P140"  ;
+NET "A_LAN<9>"  LOC = "P142"  ;
+NET "AS"  LOC = "P80"  ; 
+NET "AUTOBOOT_OFF"  LOC = "P75"  ; 
+NET "BERR"  LOC = "P98"  ; 
+NET "C1"  LOC = "P103"  ; 
+NET "C3"  LOC = "P102"  ; 
+NET "CFIN"  LOC = "P104"  ; 
+NET "CFOUT"  LOC = "P105"  ; 
+NET "CLK_EXT"  LOC = "P30"  ;
+NET "CP_CS"  LOC = "P34"  ;
+NET "CP_IRQ"  LOC = "P31"  ;
+NET "CP_RD"  LOC = "P71"  ;
+NET "CP_WE"  LOC = "P70"  ;
+NET "D<0>"  LOC = "P2"  ; 
+NET "D<10>"  LOC = "P41"  ; 
+NET "D<11>"  LOC = "P43"  ; 
+NET "D<12>"  LOC = "P44"  ; 
+NET "D<13>"  LOC = "P45"  ; 
+NET "D<14>"  LOC = "P46"  ; 
+NET "D<15>"  LOC = "P48"  ; 
+NET "D<1>"  LOC = "P17"  ; 
+NET "D<2>"  LOC = "P39"  ; 
+NET "D<3>"  LOC = "P15"  ; 
+NET "D<4>"  LOC = "P21"  ; 
+NET "D<5>"  LOC = "P20"  ; 
+NET "D<6>"  LOC = "P14"  ; 
+NET "D<7>"  LOC = "P16"  ; 
+NET "D<8>"  LOC = "P19"  ; 
+NET "D<9>"  LOC = "P40"  ; 
+NET "DQ<0>"  LOC = "P118"  ;
+NET "DQ<10>"  LOC = "P129"  ;
+NET "DQ<11>"  LOC = "P115"  ;
+NET "DQ<12>"  LOC = "P130"  ;
+NET "DQ<13>"  LOC = "P113"  ;
+NET "DQ<14>"  LOC = "P131"  ;
+NET "DQ<15>"  LOC = "P112"  ;
+NET "DQ<1>"  LOC = "P117"  ;
+NET "DQ<2>"  LOC = "P120"  ;
+NET "DQ<3>"  LOC = "P119"  ;
+NET "DQ<4>"  LOC = "P124"  ;
+NET "DQ<5>"  LOC = "P121"  ;
+NET "DQ<6>"  LOC = "P126"  ;
+NET "DQ<7>"  LOC = "P125"  ;
+NET "DQ<8>"  LOC = "P128"  ;
+NET "DQ<9>"  LOC = "P116"  ;
+NET "DS0"  LOC = "P93"  ; 
+NET "DS1"  LOC = "P78"  ; 
+NET "DTACK"  LOC = "P85"  ; 
+NET "FCS"  LOC = "P77"  ; 
+NET "IDE_A<0>"  LOC = "P24"  ;
+NET "IDE_A<1>"  LOC = "P26"  ;
+NET "IDE_A<2>"  LOC = "P25"  ;
+NET "IDE_CS<0>"  LOC = "P22"  ;
+NET "IDE_CS<1>"  LOC = "P23"  ;
+NET "IDE_R"  LOC = "P27"  ;
+NET "IDE_W"  LOC = "P28"  ;
+NET "IDE_WAIT"  LOC = "P33"  ;
+NET "INT_OUT"  LOC = "P32"  ;
+NET "LAN_CFG<1>"  LOC = "P12"  ;
+NET "LAN_CFG<2>"  LOC = "P135"  ;
+NET "LAN_CFG<3>"  LOC = "P13"  ;
+NET "LAN_CFG<4>"  LOC = "P110"  ;
+NET "LAN_CS"  LOC = "P133"  ;
+NET "LAN_EN"  LOC = "P76"  ; 
+NET "LAN_INT"  LOC = "P111"  ;
+NET "LAN_RD"  LOC = "P134"  ;
+NET "LAN_WRH"  LOC = "P132"  ;
+NET "LDS"  LOC = "P82"  ; 
+NET "MTACK"  LOC = "P96"  ; 
+NET "MTCR"  LOC = "P101"  ; 
+NET "OVR"  LOC = "P100"  ; 
+NET "OWN"  LOC = "P107"  ; 
+NET "RESET"  LOC = "P143"  ;
+NET "ROM_B<0>"  LOC = "P68"  ;
+NET "ROM_B<1>"  LOC = "P69"  ;
+NET "ROM_OE"  LOC = "P35"  ;
+NET "RW"  LOC = "P83"  ;
+NET "SLAVE"  LOC = "P106"  ; 
+NET "UDS"  LOC = "P81"  ; 
+NET "Z3"  LOC = "P79"  ; 
+
+#PACE: Start of PACE Area Constraints
+
+#PACE: Start of PACE Prohibit Constraints
+
+#PACE: End of Constraints generated by PACE
diff --git a/Logic/LAN_IDE/tmperr.err b/Logic/LAN_IDE/tmperr.err
new file mode 100644
index 0000000..e69de29
diff --git a/Logic/LAN_IDE/webtalk_pn.xml b/Logic/LAN_IDE/webtalk_pn.xml
new file mode 100644
index 0000000..a41706b
--- /dev/null
+++ b/Logic/LAN_IDE/webtalk_pn.xml
@@ -0,0 +1,43 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<document>
+<!--The data in this file is primarily intended for consumption by Xilinx tools.
+The structure and the elements are likely to change over the next few releases.
+This means code written to parse this file will need to be revisited each subsequent release.-->
+<application name="pn" timeStamp="Thu Dec 15 19:48:15 2016">
+<section name="Project Information" visible="false">
+<property name="ProjectID" value="D176CAD312EA42C990C709B74E81AC07" type="project"/>
+<property name="ProjectIteration" value="0" type="project"/>
+<property name="ProjectFile" value="C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE.xise" type="project"/>
+<property name="ProjectCreationTimestamp" value="2016-12-13T21:04:49" type="project"/>
+</section>
+<section name="Project Statistics" visible="true">
+<property name="PROP_Enable_Message_Filtering" value="false" type="design"/>
+<property name="PROP_FitterReportFormat" value="HTML" type="process"/>
+<property name="PROP_LastAppliedGoal" value="Balanced" type="design"/>
+<property name="PROP_LastAppliedStrategy" value="Xilinx Default (unlocked)" type="design"/>
+<property name="PROP_ManualCompileOrderImp" value="false" type="design"/>
+<property name="PROP_PropSpecInProjFile" value="Store all values" type="design"/>
+<property name="PROP_Simulator" value="ISim (VHDL/Verilog)" type="design"/>
+<property name="PROP_SynthTopFile" value="changed" type="process"/>
+<property name="PROP_Top_Level_Module_Type" value="HDL" type="design"/>
+<property name="PROP_UseSmartGuide" value="false" type="design"/>
+<property name="PROP_UserConstraintEditorPreference" value="Text Editor" type="process"/>
+<property name="PROP_intProjectCreationTimestamp" value="2016-12-13T21:04:49" type="design"/>
+<property name="PROP_intWbtProjectID" value="D176CAD312EA42C990C709B74E81AC07" type="design"/>
+<property name="PROP_intWorkingDirLocWRTProjDir" value="Same" type="design"/>
+<property name="PROP_intWorkingDirUsed" value="No" type="design"/>
+<property name="PROP_lockPinsUcfFile" value="changed" type="process"/>
+<property name="PROP_xilxSynthMaxFanout" value="100000" type="process"/>
+<property name="PROP_AutoTop" value="true" type="design"/>
+<property name="PROP_DevFamily" value="XC9500XL CPLDs" type="design"/>
+<property name="PROP_DevDevice" value="xc95144xl" type="design"/>
+<property name="PROP_DevFamilyPMName" value="xc9500xl" type="design"/>
+<property name="PROP_DevPackage" value="TQ144" type="design"/>
+<property name="PROP_Synthesis_Tool" value="XST (VHDL/Verilog)" type="design"/>
+<property name="PROP_DevSpeed" value="-10" type="design"/>
+<property name="PROP_PreferredLanguage" value="VHDL" type="design"/>
+<property name="FILE_UCF" value="1" type="source"/>
+<property name="FILE_VHDL" value="1" type="source"/>
+</section>
+</application>
+</document>
diff --git a/Logic/LAN_IDE/xlnx_auto_0_xdb/cst.xbcd b/Logic/LAN_IDE/xlnx_auto_0_xdb/cst.xbcd
new file mode 100644
index 0000000..424eb09
Binary files /dev/null and b/Logic/LAN_IDE/xlnx_auto_0_xdb/cst.xbcd differ
diff --git a/Logic/LAN_IDE/xst/work/hdllib.ref b/Logic/LAN_IDE/xst/work/hdllib.ref
new file mode 100644
index 0000000..6fe7301
--- /dev/null
+++ b/Logic/LAN_IDE/xst/work/hdllib.ref
@@ -0,0 +1,2 @@
+AR lan_ide_cp behavioral C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.vhd sub00/vhpl01 1481827697
+EN lan_ide_cp NULL C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.vhd sub00/vhpl00 1481827696
diff --git a/Logic/LAN_IDE/xst/work/hdpdeps.ref b/Logic/LAN_IDE/xst/work/hdpdeps.ref
new file mode 100644
index 0000000..df0b9ab
--- /dev/null
+++ b/Logic/LAN_IDE/xst/work/hdpdeps.ref
@@ -0,0 +1,8 @@
+V3 3
+FL C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.vhd 2016/12/15.19:48:14 P.68d
+EN work/LAN_IDE_CP 1481827696 \
+      FL C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.vhd \
+      PB ieee/std_logic_1164 1370735607
+AR work/LAN_IDE_CP/Behavioral 1481827697 \
+      FL C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.vhd \
+      EN work/LAN_IDE_CP 1481827696
diff --git a/Logic/LAN_IDE/xst/work/sub00/vhpl00.vho b/Logic/LAN_IDE/xst/work/sub00/vhpl00.vho
new file mode 100644
index 0000000..486e580
Binary files /dev/null and b/Logic/LAN_IDE/xst/work/sub00/vhpl00.vho differ
diff --git a/Logic/LAN_IDE/xst/work/sub00/vhpl01.vho b/Logic/LAN_IDE/xst/work/sub00/vhpl01.vho
new file mode 100644
index 0000000..e03cb44
Binary files /dev/null and b/Logic/LAN_IDE/xst/work/sub00/vhpl01.vho differ