1783 lines
62 KiB
Plaintext
1783 lines
62 KiB
Plaintext
MDF Database: version 1.0
|
|
MDF_INFO | LAN_IDE_CP | XC95288XL-10-TQ144
|
|
MACROCELL | 7 | 7 | lan
|
|
ATTRIBUTES | 8782642 | 0
|
|
OUTPUTMC | 5 | 1 | 6 | 1 | 3 | 1 | 0 | 13 | 13 | 1 | 17
|
|
INPUTS | 7 | SHUT_UP<0> | LAN_BASEADR<4> | A<20> | EXP25_.EXP | EXP26_.EXP | SHUT_UP<2>/SHUT_UP<2>_CLKF | lan/lan_RSTF
|
|
INPUTMC | 6 | 14 | 12 | 12 | 9 | 7 | 6 | 7 | 8 | 10 | 15 | 5 | 11
|
|
INPUTP | 1 | 167
|
|
IMPORTS | 2 | 7 | 6 | 7 | 8
|
|
EQ | 23 |
|
|
!LAN_CS.D = SHUT_UP<0>
|
|
# LAN_BASEADR<4> & !A<20>
|
|
# !LAN_BASEADR<4> & A<20>
|
|
;Imported pterms FB8_7
|
|
# LAN_BASEADR<3> & !A<19>
|
|
# !LAN_BASEADR<3> & A<19>
|
|
# LAN_BASEADR<5> & !A<21>
|
|
# !LAN_BASEADR<5> & A<21>
|
|
# LAN_BASEADR<7> & !A<23>
|
|
;Imported pterms FB8_6
|
|
# LAN_BASEADR<1> & !A<17>
|
|
# !LAN_BASEADR<1> & A<17>
|
|
;Imported pterms FB8_9
|
|
# LAN_BASEADR<0> & !A<16>
|
|
# !LAN_BASEADR<0> & A<16>
|
|
# LAN_BASEADR<6> & !A<22>
|
|
# !LAN_BASEADR<6> & A<22>
|
|
# !LAN_BASEADR<7> & A<23>
|
|
;Imported pterms FB8_10
|
|
# LAN_BASEADR<2> & !A<18>
|
|
# !LAN_BASEADR<2> & A<18>;
|
|
LAN_CS.CLK = !SHUT_UP<2>/SHUT_UP<2>_CLKF;
|
|
LAN_CS.AR = !lan/lan_RSTF;
|
|
|
|
MACROCELL | 3 | 1 | D_0_IOBUFE
|
|
ATTRIBUTES | 265986 | 0
|
|
OUTPUTMC | 1 | 3 | 0
|
|
INPUTS | 12 | DQ<0>.PIN | $OpTx$INV$5 | D_8_IOBUFE/D_8_IOBUFE_TRST | RESET | AUTO_CONFIG_DONE<0> | A<6> | A<5> | A<3> | A<4> | A<1> | AUTO_CONFIG_DONE_CYCLE_0__or0000/AUTO_CONFIG_DONE_CYCLE_0__or0000_D2 | A<2>
|
|
INPUTMC | 4 | 1 | 17 | 1 | 10 | 0 | 17 | 11 | 17
|
|
INPUTP | 8 | 217 | 263 | 98 | 91 | 99 | 97 | 107 | 101
|
|
EXPORTS | 1 | 3 | 0
|
|
EQ | 11 |
|
|
!D<0> = !DQ<0>.PIN & $OpTx$INV$5;
|
|
D<0>.OE = D_8_IOBUFE/D_8_IOBUFE_TRST;
|
|
D_0_IOBUFE.EXP = RESET & AUTO_CONFIG_DONE<0> & !A<6> & !A<5> &
|
|
!A<3> & !A<4> & A<1> &
|
|
AUTO_CONFIG_DONE_CYCLE_0__or0000/AUTO_CONFIG_DONE_CYCLE_0__or0000_D2
|
|
# RESET & !A<6> & A<5> & !A<3> & !A<4> & A<1> &
|
|
A<2> &
|
|
AUTO_CONFIG_DONE_CYCLE_0__or0000/AUTO_CONFIG_DONE_CYCLE_0__or0000_D2
|
|
# RESET & !A<6> & !A<5> & !A<3> & A<4> & A<1> &
|
|
A<2> &
|
|
AUTO_CONFIG_DONE_CYCLE_0__or0000/AUTO_CONFIG_DONE_CYCLE_0__or0000_D2
|
|
|
|
MACROCELL | 4 | 13 | D_10_IOBUFE
|
|
ATTRIBUTES | 265986 | 0
|
|
INPUTS | 3 | DQ<10>.PIN | $OpTx$INV$5 | D_8_IOBUFE/D_8_IOBUFE_TRST
|
|
INPUTMC | 2 | 1 | 17 | 1 | 10
|
|
INPUTP | 1 | 234
|
|
EQ | 2 |
|
|
!D<10> = !DQ<10>.PIN & $OpTx$INV$5;
|
|
D<10>.OE = D_8_IOBUFE/D_8_IOBUFE_TRST;
|
|
|
|
MACROCELL | 4 | 14 | D_11_IOBUFE
|
|
ATTRIBUTES | 265986 | 0
|
|
INPUTS | 3 | DQ<11>.PIN | $OpTx$INV$5 | D_8_IOBUFE/D_8_IOBUFE_TRST
|
|
INPUTMC | 2 | 1 | 17 | 1 | 10
|
|
INPUTP | 1 | 207
|
|
EQ | 2 |
|
|
!D<11> = !DQ<11>.PIN & $OpTx$INV$5;
|
|
D<11>.OE = D_8_IOBUFE/D_8_IOBUFE_TRST;
|
|
|
|
MACROCELL | 4 | 16 | D_12_IOBUFE
|
|
ATTRIBUTES | 265986 | 0
|
|
INPUTS | 4 | DQ<12>.PIN | $OpTx$INV$5 | Dout1<0> | D_8_IOBUFE/D_8_IOBUFE_TRST
|
|
INPUTMC | 3 | 1 | 17 | 2 | 16 | 1 | 10
|
|
INPUTP | 1 | 235
|
|
EQ | 3 |
|
|
D<12> = Dout1<0> & !$OpTx$INV$5
|
|
# DQ<12>.PIN & $OpTx$INV$5;
|
|
D<12>.OE = D_8_IOBUFE/D_8_IOBUFE_TRST;
|
|
|
|
MACROCELL | 6 | 2 | D_13_IOBUFE
|
|
ATTRIBUTES | 265986 | 0
|
|
INPUTS | 4 | DQ<13>.PIN | $OpTx$INV$5 | Dout1<1> | D_8_IOBUFE/D_8_IOBUFE_TRST
|
|
INPUTMC | 3 | 1 | 17 | 3 | 17 | 1 | 10
|
|
INPUTP | 1 | 204
|
|
EQ | 3 |
|
|
D<13> = Dout1<1> & !$OpTx$INV$5
|
|
# DQ<13>.PIN & $OpTx$INV$5;
|
|
D<13>.OE = D_8_IOBUFE/D_8_IOBUFE_TRST;
|
|
|
|
MACROCELL | 6 | 4 | D_14_IOBUFE
|
|
ATTRIBUTES | 265986 | 0
|
|
INPUTS | 4 | DQ<14>.PIN | $OpTx$INV$5 | Dout1<2> | D_8_IOBUFE/D_8_IOBUFE_TRST
|
|
INPUTMC | 3 | 1 | 17 | 3 | 0 | 1 | 10
|
|
INPUTP | 1 | 236
|
|
EQ | 3 |
|
|
D<14> = Dout1<2> & !$OpTx$INV$5
|
|
# DQ<14>.PIN & $OpTx$INV$5;
|
|
D<14>.OE = D_8_IOBUFE/D_8_IOBUFE_TRST;
|
|
|
|
MACROCELL | 6 | 11 | D_15_IOBUFE
|
|
ATTRIBUTES | 265986 | 0
|
|
INPUTS | 4 | DQ<15>.PIN | $OpTx$INV$5 | Dout1<3> | D_8_IOBUFE/D_8_IOBUFE_TRST
|
|
INPUTMC | 3 | 1 | 17 | 3 | 15 | 1 | 10
|
|
INPUTP | 1 | 202
|
|
EQ | 3 |
|
|
D<15> = Dout1<3> & !$OpTx$INV$5
|
|
# DQ<15>.PIN & $OpTx$INV$5;
|
|
D<15>.OE = D_8_IOBUFE/D_8_IOBUFE_TRST;
|
|
|
|
MACROCELL | 1 | 14 | D_1_IOBUFE
|
|
ATTRIBUTES | 265986 | 0
|
|
INPUTS | 3 | DQ<1>.PIN | $OpTx$INV$5 | D_8_IOBUFE/D_8_IOBUFE_TRST
|
|
INPUTMC | 2 | 1 | 17 | 1 | 10
|
|
INPUTP | 1 | 216
|
|
EQ | 2 |
|
|
!D<1> = !DQ<1>.PIN & $OpTx$INV$5;
|
|
D<1>.OE = D_8_IOBUFE/D_8_IOBUFE_TRST;
|
|
|
|
MACROCELL | 4 | 9 | D_2_IOBUFE
|
|
ATTRIBUTES | 265986 | 0
|
|
INPUTS | 3 | DQ<2>.PIN | $OpTx$INV$5 | D_8_IOBUFE/D_8_IOBUFE_TRST
|
|
INPUTMC | 2 | 1 | 17 | 1 | 10
|
|
INPUTP | 1 | 127
|
|
EQ | 2 |
|
|
!D<2> = !DQ<2>.PIN & $OpTx$INV$5;
|
|
D<2>.OE = D_8_IOBUFE/D_8_IOBUFE_TRST;
|
|
|
|
MACROCELL | 1 | 11 | D_3_IOBUFE
|
|
ATTRIBUTES | 265986 | 0
|
|
INPUTS | 3 | DQ<3>.PIN | $OpTx$INV$5 | D_8_IOBUFE/D_8_IOBUFE_TRST
|
|
INPUTMC | 2 | 1 | 17 | 1 | 10
|
|
INPUTP | 1 | 219
|
|
EQ | 2 |
|
|
!D<3> = !DQ<3>.PIN & $OpTx$INV$5;
|
|
D<3>.OE = D_8_IOBUFE/D_8_IOBUFE_TRST;
|
|
|
|
MACROCELL | 0 | 5 | D_4_IOBUFE
|
|
ATTRIBUTES | 265986 | 0
|
|
INPUTS | 3 | DQ<4>.PIN | $OpTx$INV$5 | D_8_IOBUFE/D_8_IOBUFE_TRST
|
|
INPUTMC | 2 | 1 | 17 | 1 | 10
|
|
INPUTP | 1 | 225
|
|
EQ | 2 |
|
|
!D<4> = !DQ<4>.PIN & $OpTx$INV$5;
|
|
D<4>.OE = D_8_IOBUFE/D_8_IOBUFE_TRST;
|
|
|
|
MACROCELL | 0 | 4 | D_5_IOBUFE
|
|
ATTRIBUTES | 265986 | 0
|
|
INPUTS | 3 | DQ<5>.PIN | $OpTx$INV$5 | D_8_IOBUFE/D_8_IOBUFE_TRST
|
|
INPUTMC | 2 | 1 | 17 | 1 | 10
|
|
INPUTP | 1 | 69
|
|
EQ | 2 |
|
|
!D<5> = !DQ<5>.PIN & $OpTx$INV$5;
|
|
D<5>.OE = D_8_IOBUFE/D_8_IOBUFE_TRST;
|
|
|
|
MACROCELL | 1 | 9 | D_6_IOBUFE
|
|
ATTRIBUTES | 265986 | 0
|
|
INPUTS | 3 | DQ<6>.PIN | $OpTx$INV$5 | D_8_IOBUFE/D_8_IOBUFE_TRST
|
|
INPUTMC | 2 | 1 | 17 | 1 | 10
|
|
INPUTP | 1 | 227
|
|
EQ | 2 |
|
|
!D<6> = !DQ<6>.PIN & $OpTx$INV$5;
|
|
D<6>.OE = D_8_IOBUFE/D_8_IOBUFE_TRST;
|
|
|
|
MACROCELL | 1 | 13 | D_7_IOBUFE
|
|
ATTRIBUTES | 265986 | 0
|
|
INPUTS | 3 | DQ<7>.PIN | $OpTx$INV$5 | D_8_IOBUFE/D_8_IOBUFE_TRST
|
|
INPUTMC | 2 | 1 | 17 | 1 | 10
|
|
INPUTP | 1 | 226
|
|
EQ | 2 |
|
|
!D<7> = !DQ<7>.PIN & $OpTx$INV$5;
|
|
D<7>.OE = D_8_IOBUFE/D_8_IOBUFE_TRST;
|
|
|
|
MACROCELL | 1 | 16 | D_8_IOBUFE
|
|
ATTRIBUTES | 265986 | 0
|
|
INPUTS | 3 | DQ<8>.PIN | $OpTx$INV$5 | D_8_IOBUFE/D_8_IOBUFE_TRST
|
|
INPUTMC | 2 | 1 | 17 | 1 | 10
|
|
INPUTP | 1 | 231
|
|
EQ | 2 |
|
|
!D<8> = !DQ<8>.PIN & $OpTx$INV$5;
|
|
D<8>.OE = D_8_IOBUFE/D_8_IOBUFE_TRST;
|
|
|
|
MACROCELL | 4 | 11 | D_9_IOBUFE
|
|
ATTRIBUTES | 265986 | 0
|
|
INPUTS | 3 | DQ<9>.PIN | $OpTx$INV$5 | D_9_IOBUFE/D_9_IOBUFE_TRST
|
|
INPUTMC | 2 | 1 | 17 | 1 | 8
|
|
INPUTP | 1 | 209
|
|
EQ | 2 |
|
|
!D<9> = !DQ<9>.PIN & $OpTx$INV$5;
|
|
D<9>.OE = D_9_IOBUFE/D_9_IOBUFE_TRST;
|
|
|
|
MACROCELL | 6 | 17 | AUTO_CONFIG_DONE<1>
|
|
ATTRIBUTES | 8520480 | 0
|
|
OUTPUTMC | 11 | 6 | 17 | 0 | 6 | 3 | 16 | 3 | 0 | 3 | 14 | 10 | 17 | 0 | 3 | 11 | 15 | 11 | 16 | 2 | 17 | 3 | 17
|
|
INPUTS | 5 | AS | RESET | AUTO_CONFIG_DONE_CYCLE<1> | AUTO_CONFIG_DONE<1> | SHUT_UP<2>/SHUT_UP<2>_CLKF
|
|
INPUTMC | 3 | 6 | 15 | 6 | 17 | 10 | 15
|
|
INPUTP | 2 | 152 | 263
|
|
EQ | 3 |
|
|
AUTO_CONFIG_DONE<1>.D = AS & RESET & AUTO_CONFIG_DONE_CYCLE<1>
|
|
# !AS & RESET & AUTO_CONFIG_DONE<1>;
|
|
AUTO_CONFIG_DONE<1>.CLK = SHUT_UP<2>/SHUT_UP<2>_CLKF;
|
|
|
|
MACROCELL | 0 | 17 | AUTO_CONFIG_DONE<0>
|
|
ATTRIBUTES | 8520480 | 0
|
|
OUTPUTMC | 9 | 0 | 17 | 0 | 6 | 3 | 16 | 2 | 17 | 10 | 17 | 0 | 3 | 11 | 15 | 11 | 16 | 3 | 1
|
|
INPUTS | 5 | AS | RESET | AUTO_CONFIG_DONE_CYCLE<0> | AUTO_CONFIG_DONE<0> | SHUT_UP<2>/SHUT_UP<2>_CLKF
|
|
INPUTMC | 3 | 6 | 16 | 0 | 17 | 10 | 15
|
|
INPUTP | 2 | 152 | 263
|
|
EQ | 3 |
|
|
AUTO_CONFIG_DONE<0>.D = AS & RESET & AUTO_CONFIG_DONE_CYCLE<0>
|
|
# !AS & RESET & AUTO_CONFIG_DONE<0>;
|
|
AUTO_CONFIG_DONE<0>.CLK = SHUT_UP<2>/SHUT_UP<2>_CLKF;
|
|
|
|
MACROCELL | 6 | 16 | AUTO_CONFIG_DONE_CYCLE<0>
|
|
ATTRIBUTES | 4326176 | 0
|
|
OUTPUTMC | 3 | 0 | 17 | 6 | 16 | 6 | 15
|
|
INPUTS | 5 | RESET | AUTO_CONFIG_DONE_CYCLE_0__or0000/AUTO_CONFIG_DONE_CYCLE_0__or0000_D2 | N32/N32_D2 | AUTO_CONFIG_DONE_CYCLE<0> | SHUT_UP<2>/SHUT_UP<2>_CLKF
|
|
INPUTMC | 4 | 11 | 17 | 10 | 17 | 6 | 16 | 10 | 15
|
|
INPUTP | 1 | 263
|
|
EQ | 5 |
|
|
AUTO_CONFIG_DONE_CYCLE<0>.T = RESET &
|
|
AUTO_CONFIG_DONE_CYCLE_0__or0000/AUTO_CONFIG_DONE_CYCLE_0__or0000_D2 & N32/N32_D2
|
|
# !RESET & AUTO_CONFIG_DONE_CYCLE<0> &
|
|
AUTO_CONFIG_DONE_CYCLE_0__or0000/AUTO_CONFIG_DONE_CYCLE_0__or0000_D2;
|
|
AUTO_CONFIG_DONE_CYCLE<0>.CLK = SHUT_UP<2>/SHUT_UP<2>_CLKF;
|
|
|
|
MACROCELL | 8 | 16 | ide
|
|
ATTRIBUTES | 8520496 | 0
|
|
OUTPUTMC | 7 | 0 | 15 | 0 | 12 | 0 | 10 | 0 | 8 | 13 | 2 | 14 | 11 | 13 | 13
|
|
INPUTS | 7 | SHUT_UP<2> | IDE_BASEADR<4> | A<20> | EXP28_.EXP | EXP29_.EXP | SHUT_UP<2>/SHUT_UP<2>_CLKF | lan/lan_RSTF
|
|
INPUTMC | 6 | 13 | 17 | 12 | 14 | 8 | 15 | 8 | 17 | 10 | 15 | 5 | 11
|
|
INPUTP | 1 | 167
|
|
IMPORTS | 2 | 8 | 15 | 8 | 17
|
|
EQ | 22 |
|
|
!ide.D = SHUT_UP<2>
|
|
# IDE_BASEADR<4> & !A<20>
|
|
# !IDE_BASEADR<4> & A<20>
|
|
;Imported pterms FB9_16
|
|
# IDE_BASEADR<3> & !A<19>
|
|
# !IDE_BASEADR<3> & A<19>
|
|
# IDE_BASEADR<5> & !A<21>
|
|
# !IDE_BASEADR<5> & A<21>
|
|
# IDE_BASEADR<6> & !A<22>
|
|
;Imported pterms FB9_15
|
|
# IDE_BASEADR<1> & !A<17>
|
|
# !IDE_BASEADR<1> & A<17>
|
|
# IDE_BASEADR<2> & !A<18>
|
|
# !IDE_BASEADR<2> & A<18>
|
|
;Imported pterms FB9_18
|
|
# IDE_BASEADR<0> & !A<16>
|
|
# !IDE_BASEADR<0> & A<16>
|
|
# !IDE_BASEADR<6> & A<22>
|
|
# IDE_BASEADR<7> & !A<23>
|
|
# !IDE_BASEADR<7> & A<23>;
|
|
ide.CLK = !SHUT_UP<2>/SHUT_UP<2>_CLKF;
|
|
ide.AR = !lan/lan_RSTF;
|
|
|
|
MACROCELL | 6 | 15 | AUTO_CONFIG_DONE_CYCLE<1>
|
|
ATTRIBUTES | 4326176 | 0
|
|
OUTPUTMC | 2 | 6 | 17 | 6 | 15
|
|
INPUTS | 6 | RESET | AUTO_CONFIG_DONE_CYCLE<0> | AUTO_CONFIG_DONE_CYCLE_0__or0000/AUTO_CONFIG_DONE_CYCLE_0__or0000_D2 | N32/N32_D2 | AUTO_CONFIG_DONE_CYCLE<1> | SHUT_UP<2>/SHUT_UP<2>_CLKF
|
|
INPUTMC | 5 | 6 | 16 | 11 | 17 | 10 | 17 | 6 | 15 | 10 | 15
|
|
INPUTP | 1 | 263
|
|
EQ | 5 |
|
|
AUTO_CONFIG_DONE_CYCLE<1>.T = !RESET & AUTO_CONFIG_DONE_CYCLE<1> &
|
|
AUTO_CONFIG_DONE_CYCLE_0__or0000/AUTO_CONFIG_DONE_CYCLE_0__or0000_D2
|
|
# RESET & AUTO_CONFIG_DONE_CYCLE<0> &
|
|
AUTO_CONFIG_DONE_CYCLE_0__or0000/AUTO_CONFIG_DONE_CYCLE_0__or0000_D2 & N32/N32_D2;
|
|
AUTO_CONFIG_DONE_CYCLE<1>.CLK = SHUT_UP<2>/SHUT_UP<2>_CLKF;
|
|
|
|
MACROCELL | 14 | 12 | SHUT_UP<0>
|
|
ATTRIBUTES | 8520480 | 0
|
|
OUTPUTMC | 4 | 7 | 7 | 14 | 12 | 10 | 17 | 11 | 15
|
|
INPUTS | 4 | RESET | SHUT_UP<0> | LAN_BASEADR_0__or0001/LAN_BASEADR_0__or0001_D2 | SHUT_UP<2>/SHUT_UP<2>_CLKF
|
|
INPUTMC | 3 | 14 | 12 | 11 | 15 | 10 | 15
|
|
INPUTP | 1 | 263
|
|
EQ | 4 |
|
|
SHUT_UP<0>.D = !RESET
|
|
# SHUT_UP<0> &
|
|
!LAN_BASEADR_0__or0001/LAN_BASEADR_0__or0001_D2;
|
|
SHUT_UP<0>.CLK = SHUT_UP<2>/SHUT_UP<2>_CLKF;
|
|
|
|
MACROCELL | 14 | 10 | SHUT_UP<1>
|
|
ATTRIBUTES | 8520480 | 0
|
|
OUTPUTMC | 4 | 14 | 10 | 4 | 1 | 10 | 17 | 11 | 16
|
|
INPUTS | 4 | RESET | SHUT_UP<1> | CP_BASEADR_0__or0001/CP_BASEADR_0__or0001_D2 | SHUT_UP<2>/SHUT_UP<2>_CLKF
|
|
INPUTMC | 3 | 14 | 10 | 11 | 16 | 10 | 15
|
|
INPUTP | 1 | 263
|
|
EQ | 4 |
|
|
SHUT_UP<1>.D = !RESET
|
|
# SHUT_UP<1> &
|
|
!CP_BASEADR_0__or0001/CP_BASEADR_0__or0001_D2;
|
|
SHUT_UP<1>.CLK = SHUT_UP<2>/SHUT_UP<2>_CLKF;
|
|
|
|
MACROCELL | 13 | 17 | SHUT_UP<2>
|
|
ATTRIBUTES | 8520480 | 0
|
|
OUTPUTMC | 4 | 8 | 16 | 13 | 17 | 10 | 17 | 13 | 16
|
|
INPUTS | 4 | RESET | SHUT_UP<2> | IDE_BASEADR_0__or0001/IDE_BASEADR_0__or0001_D2 | SHUT_UP<2>/SHUT_UP<2>_CLKF
|
|
INPUTMC | 3 | 13 | 17 | 13 | 16 | 10 | 15
|
|
INPUTP | 1 | 263
|
|
EQ | 4 |
|
|
SHUT_UP<2>.D = !RESET
|
|
# SHUT_UP<2> &
|
|
!IDE_BASEADR_0__or0001/IDE_BASEADR_0__or0001_D2;
|
|
SHUT_UP<2>.CLK = SHUT_UP<2>/SHUT_UP<2>_CLKF;
|
|
|
|
MACROCELL | 15 | 16 | autoconfig
|
|
ATTRIBUTES | 8520496 | 0
|
|
OUTPUTMC | 7 | 13 | 13 | 1 | 10 | 1 | 8 | 11 | 17 | 11 | 15 | 11 | 16 | 13 | 16
|
|
INPUTS | 12 | A<18> | A<17> | A<16> | A<19> | CFIN | A<20> | A<23> | A<22> | A<21> | $OpTx$FX_DC$8 | SHUT_UP<2>/SHUT_UP<2>_CLKF | lan/lan_RSTF
|
|
INPUTMC | 3 | 0 | 3 | 10 | 15 | 5 | 11
|
|
INPUTP | 9 | 171 | 172 | 175 | 169 | 190 | 167 | 161 | 162 | 163
|
|
EQ | 4 |
|
|
autoconfig.D = !A<18> & !A<17> & !A<16> & A<19> & !CFIN & !A<20> &
|
|
A<23> & A<22> & A<21> & !$OpTx$FX_DC$8;
|
|
autoconfig.CLK = !SHUT_UP<2>/SHUT_UP<2>_CLKF;
|
|
autoconfig.AR = !lan/lan_RSTF;
|
|
|
|
MACROCELL | 0 | 15 | IDE_ENABLE
|
|
ATTRIBUTES | 8520480 | 0
|
|
OUTPUTMC | 3 | 0 | 15 | 0 | 12 | 0 | 8
|
|
INPUTS | 6 | RESET | IDE_ENABLE | AS | RW | ide | SHUT_UP<2>/SHUT_UP<2>_CLKF
|
|
INPUTMC | 3 | 0 | 15 | 8 | 16 | 10 | 15
|
|
INPUTP | 3 | 263 | 152 | 158
|
|
EQ | 3 |
|
|
!IDE_ENABLE.D = RESET & !IDE_ENABLE
|
|
# !AS & !RW & RESET & ide;
|
|
IDE_ENABLE.CLK = SHUT_UP<2>/SHUT_UP<2>_CLKF;
|
|
|
|
MACROCELL | 9 | 17 | CP_BASEADR<0>
|
|
ATTRIBUTES | 8520480 | 0
|
|
OUTPUTMC | 2 | 9 | 17 | 4 | 2
|
|
INPUTS | 5 | RESET | D<8>.PIN | CP_BASEADR_0__or0001/CP_BASEADR_0__or0001_D2 | CP_BASEADR<0> | SHUT_UP<2>/SHUT_UP<2>_CLKF
|
|
INPUTMC | 3 | 11 | 16 | 9 | 17 | 10 | 15
|
|
INPUTP | 2 | 263 | 32
|
|
EQ | 5 |
|
|
!CP_BASEADR<0>.D = RESET & !CP_BASEADR<0> &
|
|
!CP_BASEADR_0__or0001/CP_BASEADR_0__or0001_D2
|
|
# RESET & !D<8>.PIN &
|
|
CP_BASEADR_0__or0001/CP_BASEADR_0__or0001_D2;
|
|
CP_BASEADR<0>.CLK = SHUT_UP<2>/SHUT_UP<2>_CLKF;
|
|
|
|
MACROCELL | 9 | 15 | CP_BASEADR<1>
|
|
ATTRIBUTES | 8520480 | 0
|
|
OUTPUTMC | 2 | 9 | 15 | 4 | 3
|
|
INPUTS | 5 | RESET | D<9>.PIN | CP_BASEADR_0__or0001/CP_BASEADR_0__or0001_D2 | CP_BASEADR<1> | SHUT_UP<2>/SHUT_UP<2>_CLKF
|
|
INPUTMC | 3 | 11 | 16 | 9 | 15 | 10 | 15
|
|
INPUTP | 2 | 263 | 73
|
|
EQ | 5 |
|
|
!CP_BASEADR<1>.D = RESET & !CP_BASEADR<1> &
|
|
!CP_BASEADR_0__or0001/CP_BASEADR_0__or0001_D2
|
|
# RESET & !D<9>.PIN &
|
|
CP_BASEADR_0__or0001/CP_BASEADR_0__or0001_D2;
|
|
CP_BASEADR<1>.CLK = SHUT_UP<2>/SHUT_UP<2>_CLKF;
|
|
|
|
MACROCELL | 9 | 14 | CP_BASEADR<2>
|
|
ATTRIBUTES | 8520480 | 0
|
|
OUTPUTMC | 2 | 9 | 14 | 4 | 3
|
|
INPUTS | 5 | RESET | D<10>.PIN | CP_BASEADR_0__or0001/CP_BASEADR_0__or0001_D2 | CP_BASEADR<2> | SHUT_UP<2>/SHUT_UP<2>_CLKF
|
|
INPUTMC | 3 | 11 | 16 | 9 | 14 | 10 | 15
|
|
INPUTP | 2 | 263 | 74
|
|
EQ | 5 |
|
|
!CP_BASEADR<2>.D = RESET & !CP_BASEADR<2> &
|
|
!CP_BASEADR_0__or0001/CP_BASEADR_0__or0001_D2
|
|
# RESET & !D<10>.PIN &
|
|
CP_BASEADR_0__or0001/CP_BASEADR_0__or0001_D2;
|
|
CP_BASEADR<2>.CLK = SHUT_UP<2>/SHUT_UP<2>_CLKF;
|
|
|
|
MACROCELL | 9 | 12 | CP_BASEADR<3>
|
|
ATTRIBUTES | 8520480 | 0
|
|
OUTPUTMC | 2 | 9 | 12 | 4 | 0
|
|
INPUTS | 5 | RESET | D<11>.PIN | CP_BASEADR_0__or0001/CP_BASEADR_0__or0001_D2 | CP_BASEADR<3> | SHUT_UP<2>/SHUT_UP<2>_CLKF
|
|
INPUTMC | 3 | 11 | 16 | 9 | 12 | 10 | 15
|
|
INPUTP | 2 | 263 | 77
|
|
EQ | 5 |
|
|
!CP_BASEADR<3>.D = RESET & !CP_BASEADR<3> &
|
|
!CP_BASEADR_0__or0001/CP_BASEADR_0__or0001_D2
|
|
# RESET & !D<11>.PIN &
|
|
CP_BASEADR_0__or0001/CP_BASEADR_0__or0001_D2;
|
|
CP_BASEADR<3>.CLK = SHUT_UP<2>/SHUT_UP<2>_CLKF;
|
|
|
|
MACROCELL | 6 | 14 | CP_BASEADR<4>
|
|
ATTRIBUTES | 8520480 | 0
|
|
OUTPUTMC | 2 | 6 | 14 | 4 | 1
|
|
INPUTS | 5 | RESET | D<12>.PIN | CP_BASEADR_0__or0001/CP_BASEADR_0__or0001_D2 | CP_BASEADR<4> | SHUT_UP<2>/SHUT_UP<2>_CLKF
|
|
INPUTMC | 3 | 11 | 16 | 6 | 14 | 10 | 15
|
|
INPUTP | 2 | 263 | 78
|
|
EQ | 5 |
|
|
!CP_BASEADR<4>.D = RESET & !CP_BASEADR<4> &
|
|
!CP_BASEADR_0__or0001/CP_BASEADR_0__or0001_D2
|
|
# RESET & !D<12>.PIN &
|
|
CP_BASEADR_0__or0001/CP_BASEADR_0__or0001_D2;
|
|
CP_BASEADR<4>.CLK = SHUT_UP<2>/SHUT_UP<2>_CLKF;
|
|
|
|
MACROCELL | 5 | 17 | CP_BASEADR<5>
|
|
ATTRIBUTES | 8520480 | 0
|
|
OUTPUTMC | 2 | 5 | 17 | 4 | 0
|
|
INPUTS | 5 | RESET | D<13>.PIN | CP_BASEADR_0__or0001/CP_BASEADR_0__or0001_D2 | CP_BASEADR<5> | SHUT_UP<2>/SHUT_UP<2>_CLKF
|
|
INPUTMC | 3 | 11 | 16 | 5 | 17 | 10 | 15
|
|
INPUTP | 2 | 263 | 80
|
|
EQ | 5 |
|
|
!CP_BASEADR<5>.D = RESET & !CP_BASEADR<5> &
|
|
!CP_BASEADR_0__or0001/CP_BASEADR_0__or0001_D2
|
|
# RESET & !D<13>.PIN &
|
|
CP_BASEADR_0__or0001/CP_BASEADR_0__or0001_D2;
|
|
CP_BASEADR<5>.CLK = SHUT_UP<2>/SHUT_UP<2>_CLKF;
|
|
|
|
MACROCELL | 5 | 16 | CP_BASEADR<6>
|
|
ATTRIBUTES | 8520480 | 0
|
|
OUTPUTMC | 3 | 5 | 16 | 4 | 0 | 4 | 2
|
|
INPUTS | 5 | RESET | D<14>.PIN | CP_BASEADR_0__or0001/CP_BASEADR_0__or0001_D2 | CP_BASEADR<6> | SHUT_UP<2>/SHUT_UP<2>_CLKF
|
|
INPUTMC | 3 | 11 | 16 | 5 | 16 | 10 | 15
|
|
INPUTP | 2 | 263 | 81
|
|
EQ | 5 |
|
|
!CP_BASEADR<6>.D = RESET & !CP_BASEADR<6> &
|
|
!CP_BASEADR_0__or0001/CP_BASEADR_0__or0001_D2
|
|
# RESET & !D<14>.PIN &
|
|
CP_BASEADR_0__or0001/CP_BASEADR_0__or0001_D2;
|
|
CP_BASEADR<6>.CLK = SHUT_UP<2>/SHUT_UP<2>_CLKF;
|
|
|
|
MACROCELL | 5 | 15 | CP_BASEADR<7>
|
|
ATTRIBUTES | 8520480 | 0
|
|
OUTPUTMC | 2 | 5 | 15 | 4 | 2
|
|
INPUTS | 5 | RESET | D<15>.PIN | CP_BASEADR_0__or0001/CP_BASEADR_0__or0001_D2 | CP_BASEADR<7> | SHUT_UP<2>/SHUT_UP<2>_CLKF
|
|
INPUTMC | 3 | 11 | 16 | 5 | 15 | 10 | 15
|
|
INPUTP | 2 | 263 | 89
|
|
EQ | 5 |
|
|
!CP_BASEADR<7>.D = RESET & !CP_BASEADR<7> &
|
|
!CP_BASEADR_0__or0001/CP_BASEADR_0__or0001_D2
|
|
# RESET & !D<15>.PIN &
|
|
CP_BASEADR_0__or0001/CP_BASEADR_0__or0001_D2;
|
|
CP_BASEADR<7>.CLK = SHUT_UP<2>/SHUT_UP<2>_CLKF;
|
|
|
|
MACROCELL | 2 | 16 | Dout1<0>
|
|
ATTRIBUTES | 8520480 | 0
|
|
OUTPUTMC | 2 | 4 | 16 | 2 | 16
|
|
INPUTS | 9 | AUTO_CONFIG_DONE_CYCLE_0__or0000/AUTO_CONFIG_DONE_CYCLE_0__or0000_D2 | $OpTx$FX_DC$19 | Dout1<0> | A<3> | $OpTx$FX_DC$33 | A<4> | EXP18_.EXP | EXP19_.EXP | SHUT_UP<2>/SHUT_UP<2>_CLKF
|
|
INPUTMC | 7 | 11 | 17 | 3 | 12 | 2 | 16 | 3 | 10 | 2 | 15 | 2 | 17 | 10 | 15
|
|
INPUTP | 2 | 99 | 97
|
|
IMPORTS | 2 | 2 | 15 | 2 | 17
|
|
EQ | 25 |
|
|
Dout1<0>.D = Dout1<0> &
|
|
!AUTO_CONFIG_DONE_CYCLE_0__or0000/AUTO_CONFIG_DONE_CYCLE_0__or0000_D2
|
|
#
|
|
AUTO_CONFIG_DONE_CYCLE_0__or0000/AUTO_CONFIG_DONE_CYCLE_0__or0000_D2 & !$OpTx$FX_DC$19
|
|
# A<3> &
|
|
AUTO_CONFIG_DONE_CYCLE_0__or0000/AUTO_CONFIG_DONE_CYCLE_0__or0000_D2 & $OpTx$FX_DC$33
|
|
# !A<3> & A<4> &
|
|
AUTO_CONFIG_DONE_CYCLE_0__or0000/AUTO_CONFIG_DONE_CYCLE_0__or0000_D2 & !$OpTx$FX_DC$33
|
|
;Imported pterms FB3_16
|
|
# !A<5> & A<3> & !A<4> &
|
|
AUTO_CONFIG_DONE_CYCLE_0__or0000/AUTO_CONFIG_DONE_CYCLE_0__or0000_D2
|
|
;Imported pterms FB3_18
|
|
# A<3> & !A<4> &
|
|
AUTO_CONFIG_DONE_CYCLE_0__or0000/AUTO_CONFIG_DONE_CYCLE_0__or0000_D2 & !$OpTx$FX_DC$28
|
|
# AUTO_CONFIG_DONE<1> & !A<5> & !A<3> & A<2> &
|
|
AUTO_CONFIG_DONE_CYCLE_0__or0000/AUTO_CONFIG_DONE_CYCLE_0__or0000_D2
|
|
# !A<6> & !A<3> & A<1> & !A<2> &
|
|
AUTO_CONFIG_DONE_CYCLE_0__or0000/AUTO_CONFIG_DONE_CYCLE_0__or0000_D2
|
|
# AUTO_CONFIG_DONE<1> & !A<6> & !A<3> & !A<2> &
|
|
!AUTOBOOT_OFF &
|
|
AUTO_CONFIG_DONE_CYCLE_0__or0000/AUTO_CONFIG_DONE_CYCLE_0__or0000_D2
|
|
# AUTO_CONFIG_DONE<0> & !A<6> & !A<5> & !A<3> &
|
|
A<1> &
|
|
AUTO_CONFIG_DONE_CYCLE_0__or0000/AUTO_CONFIG_DONE_CYCLE_0__or0000_D2;
|
|
Dout1<0>.CLK = SHUT_UP<2>/SHUT_UP<2>_CLKF;
|
|
|
|
MACROCELL | 3 | 17 | Dout1<1>
|
|
ATTRIBUTES | 8520480 | 0
|
|
OUTPUTMC | 3 | 6 | 2 | 3 | 17 | 3 | 0
|
|
INPUTS | 13 | $OpTx$FX_DC$36 | Dout1<1> | AUTO_CONFIG_DONE_CYCLE_0__or0000/AUTO_CONFIG_DONE_CYCLE_0__or0000_D2 | RESET | A<5> | A<3> | A<4> | A<1> | A<2> | AUTO_CONFIG_DONE<1> | SHUT_UP<2>/SHUT_UP<2>_CLKF | A<6> | EXP20_.EXP
|
|
INPUTMC | 6 | 3 | 14 | 3 | 17 | 11 | 17 | 6 | 17 | 10 | 15 | 3 | 16
|
|
INPUTP | 7 | 263 | 91 | 99 | 97 | 107 | 101 | 98
|
|
EXPORTS | 1 | 3 | 0
|
|
IMPORTS | 1 | 3 | 16
|
|
EQ | 22 |
|
|
Dout1<1>.D = $OpTx$FX_DC$36
|
|
# Dout1<1> &
|
|
!AUTO_CONFIG_DONE_CYCLE_0__or0000/AUTO_CONFIG_DONE_CYCLE_0__or0000_D2
|
|
;Imported pterms FB4_17
|
|
# AUTO_CONFIG_DONE<1> & !A<3> & A<4> & A<1> &
|
|
AUTO_CONFIG_DONE_CYCLE_0__or0000/AUTO_CONFIG_DONE_CYCLE_0__or0000_D2
|
|
# !AUTO_CONFIG_DONE<1> & !A<3> & A<4> & A<2> &
|
|
AUTO_CONFIG_DONE_CYCLE_0__or0000/AUTO_CONFIG_DONE_CYCLE_0__or0000_D2
|
|
# !A<3> & A<4> & !A<1> & !A<2> &
|
|
AUTO_CONFIG_DONE_CYCLE_0__or0000/AUTO_CONFIG_DONE_CYCLE_0__or0000_D2
|
|
# AUTO_CONFIG_DONE<1> & !A<5> & !A<4> & !A<1> &
|
|
A<2> &
|
|
AUTO_CONFIG_DONE_CYCLE_0__or0000/AUTO_CONFIG_DONE_CYCLE_0__or0000_D2
|
|
# !AUTO_CONFIG_DONE<1> & AUTO_CONFIG_DONE<0> & !A<4> &
|
|
A<1> & A<2> &
|
|
AUTO_CONFIG_DONE_CYCLE_0__or0000/AUTO_CONFIG_DONE_CYCLE_0__or0000_D2;
|
|
Dout1<1>.CLK = SHUT_UP<2>/SHUT_UP<2>_CLKF;
|
|
Dout1<1>.EXP = RESET & !A<5> & !A<3> & !A<4> & A<1> & !A<2> &
|
|
AUTO_CONFIG_DONE_CYCLE_0__or0000/AUTO_CONFIG_DONE_CYCLE_0__or0000_D2
|
|
# RESET & AUTO_CONFIG_DONE<1> & !A<6> & !A<5> &
|
|
!A<3> & !A<4> & A<1> &
|
|
AUTO_CONFIG_DONE_CYCLE_0__or0000/AUTO_CONFIG_DONE_CYCLE_0__or0000_D2
|
|
|
|
MACROCELL | 3 | 0 | Dout1<2>
|
|
ATTRIBUTES | 8520480 | 0
|
|
OUTPUTMC | 2 | 6 | 4 | 3 | 0
|
|
INPUTS | 13 | Dout1<2> | AUTO_CONFIG_DONE_CYCLE_0__or0000/AUTO_CONFIG_DONE_CYCLE_0__or0000_D2 | RESET | AUTO_CONFIG_DONE<1> | A<6> | A<5> | A<3> | A<4> | A<1> | A<2> | D_0_IOBUFE.EXP | SHUT_UP<2>/SHUT_UP<2>_CLKF | Dout1<1>.EXP
|
|
INPUTMC | 6 | 3 | 0 | 11 | 17 | 6 | 17 | 3 | 1 | 10 | 15 | 3 | 17
|
|
INPUTP | 7 | 263 | 98 | 91 | 99 | 97 | 107 | 101
|
|
IMPORTS | 2 | 3 | 1 | 3 | 17
|
|
EQ | 27 |
|
|
!Dout1<2>.D = !Dout1<2> &
|
|
!AUTO_CONFIG_DONE_CYCLE_0__or0000/AUTO_CONFIG_DONE_CYCLE_0__or0000_D2
|
|
# RESET & A<6> & !A<5> & !A<3> & !A<4> & !A<2> &
|
|
AUTO_CONFIG_DONE_CYCLE_0__or0000/AUTO_CONFIG_DONE_CYCLE_0__or0000_D2
|
|
# RESET & !A<6> & !A<5> & A<3> & A<4> & !A<1> &
|
|
A<2> &
|
|
AUTO_CONFIG_DONE_CYCLE_0__or0000/AUTO_CONFIG_DONE_CYCLE_0__or0000_D2
|
|
# RESET & !AUTO_CONFIG_DONE<1> & !A<6> & !A<5> &
|
|
!A<3> & !A<4> & !A<1> & A<2> &
|
|
AUTO_CONFIG_DONE_CYCLE_0__or0000/AUTO_CONFIG_DONE_CYCLE_0__or0000_D2
|
|
;Imported pterms FB4_2
|
|
# RESET & AUTO_CONFIG_DONE<0> & !A<6> & !A<5> &
|
|
!A<3> & !A<4> & A<1> &
|
|
AUTO_CONFIG_DONE_CYCLE_0__or0000/AUTO_CONFIG_DONE_CYCLE_0__or0000_D2
|
|
# RESET & !A<6> & A<5> & !A<3> & !A<4> & A<1> &
|
|
A<2> &
|
|
AUTO_CONFIG_DONE_CYCLE_0__or0000/AUTO_CONFIG_DONE_CYCLE_0__or0000_D2
|
|
# RESET & !A<6> & !A<5> & !A<3> & A<4> & A<1> &
|
|
A<2> &
|
|
AUTO_CONFIG_DONE_CYCLE_0__or0000/AUTO_CONFIG_DONE_CYCLE_0__or0000_D2
|
|
;Imported pterms FB4_18
|
|
# RESET & !A<5> & !A<3> & !A<4> & A<1> & !A<2> &
|
|
AUTO_CONFIG_DONE_CYCLE_0__or0000/AUTO_CONFIG_DONE_CYCLE_0__or0000_D2
|
|
# RESET & AUTO_CONFIG_DONE<1> & !A<6> & !A<5> &
|
|
!A<3> & !A<4> & A<1> &
|
|
AUTO_CONFIG_DONE_CYCLE_0__or0000/AUTO_CONFIG_DONE_CYCLE_0__or0000_D2;
|
|
Dout1<2>.CLK = SHUT_UP<2>/SHUT_UP<2>_CLKF;
|
|
|
|
MACROCELL | 3 | 15 | Dout1<3>
|
|
ATTRIBUTES | 8520480 | 0
|
|
OUTPUTMC | 2 | 6 | 11 | 3 | 15
|
|
INPUTS | 10 | $OpTx$FX_DC$36 | Dout1<3> | AUTO_CONFIG_DONE_CYCLE_0__or0000/AUTO_CONFIG_DONE_CYCLE_0__or0000_D2 | A<5> | A<1> | A<2> | A<6> | A<3> | $OpTx$FX_DC$36.EXP | SHUT_UP<2>/SHUT_UP<2>_CLKF
|
|
INPUTMC | 5 | 3 | 14 | 3 | 15 | 11 | 17 | 3 | 14 | 10 | 15
|
|
INPUTP | 5 | 91 | 107 | 101 | 98 | 99
|
|
IMPORTS | 1 | 3 | 14
|
|
EQ | 11 |
|
|
Dout1<3>.D = $OpTx$FX_DC$36
|
|
# Dout1<3> &
|
|
!AUTO_CONFIG_DONE_CYCLE_0__or0000/AUTO_CONFIG_DONE_CYCLE_0__or0000_D2
|
|
# !A<5> & !A<1> & A<2> &
|
|
AUTO_CONFIG_DONE_CYCLE_0__or0000/AUTO_CONFIG_DONE_CYCLE_0__or0000_D2
|
|
# !A<6> & !A<5> & !A<3> & !A<1> &
|
|
AUTO_CONFIG_DONE_CYCLE_0__or0000/AUTO_CONFIG_DONE_CYCLE_0__or0000_D2
|
|
;Imported pterms FB4_15
|
|
# AUTO_CONFIG_DONE<1> & !A<5> & !A<4> & A<2> &
|
|
AUTO_CONFIG_DONE_CYCLE_0__or0000/AUTO_CONFIG_DONE_CYCLE_0__or0000_D2;
|
|
Dout1<3>.CLK = SHUT_UP<2>/SHUT_UP<2>_CLKF;
|
|
|
|
MACROCELL | 15 | 17 | IDE_BASEADR<0>
|
|
ATTRIBUTES | 8520480 | 0
|
|
OUTPUTMC | 2 | 15 | 17 | 8 | 17
|
|
INPUTS | 5 | RESET | D<8>.PIN | IDE_BASEADR_0__or0001/IDE_BASEADR_0__or0001_D2 | IDE_BASEADR<0> | SHUT_UP<2>/SHUT_UP<2>_CLKF
|
|
INPUTMC | 3 | 13 | 16 | 15 | 17 | 10 | 15
|
|
INPUTP | 2 | 263 | 32
|
|
EQ | 5 |
|
|
!IDE_BASEADR<0>.D = RESET & !IDE_BASEADR<0> &
|
|
!IDE_BASEADR_0__or0001/IDE_BASEADR_0__or0001_D2
|
|
# RESET & !D<8>.PIN &
|
|
IDE_BASEADR_0__or0001/IDE_BASEADR_0__or0001_D2;
|
|
IDE_BASEADR<0>.CLK = SHUT_UP<2>/SHUT_UP<2>_CLKF;
|
|
|
|
MACROCELL | 12 | 17 | IDE_BASEADR<1>
|
|
ATTRIBUTES | 8520480 | 0
|
|
OUTPUTMC | 2 | 8 | 14 | 12 | 17
|
|
INPUTS | 5 | RESET | D<9>.PIN | IDE_BASEADR_0__or0001/IDE_BASEADR_0__or0001_D2 | IDE_BASEADR<1> | SHUT_UP<2>/SHUT_UP<2>_CLKF
|
|
INPUTMC | 3 | 13 | 16 | 12 | 17 | 10 | 15
|
|
INPUTP | 2 | 263 | 73
|
|
EQ | 5 |
|
|
!IDE_BASEADR<1>.D = RESET & !IDE_BASEADR<1> &
|
|
!IDE_BASEADR_0__or0001/IDE_BASEADR_0__or0001_D2
|
|
# RESET & !D<9>.PIN &
|
|
IDE_BASEADR_0__or0001/IDE_BASEADR_0__or0001_D2;
|
|
IDE_BASEADR<1>.CLK = SHUT_UP<2>/SHUT_UP<2>_CLKF;
|
|
|
|
MACROCELL | 12 | 16 | IDE_BASEADR<2>
|
|
ATTRIBUTES | 8520480 | 0
|
|
OUTPUTMC | 2 | 8 | 14 | 12 | 16
|
|
INPUTS | 5 | RESET | D<10>.PIN | IDE_BASEADR_0__or0001/IDE_BASEADR_0__or0001_D2 | IDE_BASEADR<2> | SHUT_UP<2>/SHUT_UP<2>_CLKF
|
|
INPUTMC | 3 | 13 | 16 | 12 | 16 | 10 | 15
|
|
INPUTP | 2 | 263 | 74
|
|
EQ | 5 |
|
|
!IDE_BASEADR<2>.D = RESET & !IDE_BASEADR<2> &
|
|
!IDE_BASEADR_0__or0001/IDE_BASEADR_0__or0001_D2
|
|
# RESET & !D<10>.PIN &
|
|
IDE_BASEADR_0__or0001/IDE_BASEADR_0__or0001_D2;
|
|
IDE_BASEADR<2>.CLK = SHUT_UP<2>/SHUT_UP<2>_CLKF;
|
|
|
|
MACROCELL | 12 | 15 | IDE_BASEADR<3>
|
|
ATTRIBUTES | 8520480 | 0
|
|
OUTPUTMC | 2 | 8 | 15 | 12 | 15
|
|
INPUTS | 5 | RESET | D<11>.PIN | IDE_BASEADR_0__or0001/IDE_BASEADR_0__or0001_D2 | IDE_BASEADR<3> | SHUT_UP<2>/SHUT_UP<2>_CLKF
|
|
INPUTMC | 3 | 13 | 16 | 12 | 15 | 10 | 15
|
|
INPUTP | 2 | 263 | 77
|
|
EQ | 5 |
|
|
!IDE_BASEADR<3>.D = RESET & !IDE_BASEADR<3> &
|
|
!IDE_BASEADR_0__or0001/IDE_BASEADR_0__or0001_D2
|
|
# RESET & !D<11>.PIN &
|
|
IDE_BASEADR_0__or0001/IDE_BASEADR_0__or0001_D2;
|
|
IDE_BASEADR<3>.CLK = SHUT_UP<2>/SHUT_UP<2>_CLKF;
|
|
|
|
MACROCELL | 12 | 14 | IDE_BASEADR<4>
|
|
ATTRIBUTES | 8520480 | 0
|
|
OUTPUTMC | 2 | 8 | 16 | 12 | 14
|
|
INPUTS | 5 | RESET | D<12>.PIN | IDE_BASEADR_0__or0001/IDE_BASEADR_0__or0001_D2 | IDE_BASEADR<4> | SHUT_UP<2>/SHUT_UP<2>_CLKF
|
|
INPUTMC | 3 | 13 | 16 | 12 | 14 | 10 | 15
|
|
INPUTP | 2 | 263 | 78
|
|
EQ | 5 |
|
|
!IDE_BASEADR<4>.D = RESET & !IDE_BASEADR<4> &
|
|
!IDE_BASEADR_0__or0001/IDE_BASEADR_0__or0001_D2
|
|
# RESET & !D<12>.PIN &
|
|
IDE_BASEADR_0__or0001/IDE_BASEADR_0__or0001_D2;
|
|
IDE_BASEADR<4>.CLK = SHUT_UP<2>/SHUT_UP<2>_CLKF;
|
|
|
|
MACROCELL | 5 | 14 | IDE_BASEADR<5>
|
|
ATTRIBUTES | 8520480 | 0
|
|
OUTPUTMC | 2 | 8 | 15 | 5 | 14
|
|
INPUTS | 5 | RESET | D<13>.PIN | IDE_BASEADR_0__or0001/IDE_BASEADR_0__or0001_D2 | IDE_BASEADR<5> | SHUT_UP<2>/SHUT_UP<2>_CLKF
|
|
INPUTMC | 3 | 13 | 16 | 5 | 14 | 10 | 15
|
|
INPUTP | 2 | 263 | 80
|
|
EQ | 5 |
|
|
!IDE_BASEADR<5>.D = RESET & !IDE_BASEADR<5> &
|
|
!IDE_BASEADR_0__or0001/IDE_BASEADR_0__or0001_D2
|
|
# RESET & !D<13>.PIN &
|
|
IDE_BASEADR_0__or0001/IDE_BASEADR_0__or0001_D2;
|
|
IDE_BASEADR<5>.CLK = SHUT_UP<2>/SHUT_UP<2>_CLKF;
|
|
|
|
MACROCELL | 5 | 12 | IDE_BASEADR<6>
|
|
ATTRIBUTES | 8520480 | 0
|
|
OUTPUTMC | 3 | 8 | 15 | 5 | 12 | 8 | 17
|
|
INPUTS | 5 | RESET | D<14>.PIN | IDE_BASEADR_0__or0001/IDE_BASEADR_0__or0001_D2 | IDE_BASEADR<6> | SHUT_UP<2>/SHUT_UP<2>_CLKF
|
|
INPUTMC | 3 | 13 | 16 | 5 | 12 | 10 | 15
|
|
INPUTP | 2 | 263 | 81
|
|
EQ | 5 |
|
|
!IDE_BASEADR<6>.D = RESET & !IDE_BASEADR<6> &
|
|
!IDE_BASEADR_0__or0001/IDE_BASEADR_0__or0001_D2
|
|
# RESET & !D<14>.PIN &
|
|
IDE_BASEADR_0__or0001/IDE_BASEADR_0__or0001_D2;
|
|
IDE_BASEADR<6>.CLK = SHUT_UP<2>/SHUT_UP<2>_CLKF;
|
|
|
|
MACROCELL | 14 | 17 | IDE_BASEADR<7>
|
|
ATTRIBUTES | 8520480 | 0
|
|
OUTPUTMC | 2 | 14 | 17 | 8 | 17
|
|
INPUTS | 5 | RESET | D<15>.PIN | IDE_BASEADR_0__or0001/IDE_BASEADR_0__or0001_D2 | IDE_BASEADR<7> | SHUT_UP<2>/SHUT_UP<2>_CLKF
|
|
INPUTMC | 3 | 13 | 16 | 14 | 17 | 10 | 15
|
|
INPUTP | 2 | 263 | 89
|
|
EQ | 5 |
|
|
!IDE_BASEADR<7>.D = RESET & !IDE_BASEADR<7> &
|
|
!IDE_BASEADR_0__or0001/IDE_BASEADR_0__or0001_D2
|
|
# RESET & !D<15>.PIN &
|
|
IDE_BASEADR_0__or0001/IDE_BASEADR_0__or0001_D2;
|
|
IDE_BASEADR<7>.CLK = SHUT_UP<2>/SHUT_UP<2>_CLKF;
|
|
|
|
MACROCELL | 14 | 16 | LAN_BASEADR<0>
|
|
ATTRIBUTES | 8520480 | 0
|
|
OUTPUTMC | 2 | 14 | 16 | 7 | 8
|
|
INPUTS | 5 | RESET | D<8>.PIN | LAN_BASEADR_0__or0001/LAN_BASEADR_0__or0001_D2 | LAN_BASEADR<0> | SHUT_UP<2>/SHUT_UP<2>_CLKF
|
|
INPUTMC | 3 | 11 | 15 | 14 | 16 | 10 | 15
|
|
INPUTP | 2 | 263 | 32
|
|
EQ | 5 |
|
|
!LAN_BASEADR<0>.D = RESET & !LAN_BASEADR<0> &
|
|
!LAN_BASEADR_0__or0001/LAN_BASEADR_0__or0001_D2
|
|
# RESET & !D<8>.PIN &
|
|
LAN_BASEADR_0__or0001/LAN_BASEADR_0__or0001_D2;
|
|
LAN_BASEADR<0>.CLK = SHUT_UP<2>/SHUT_UP<2>_CLKF;
|
|
|
|
MACROCELL | 12 | 12 | LAN_BASEADR<1>
|
|
ATTRIBUTES | 8520480 | 0
|
|
OUTPUTMC | 2 | 7 | 5 | 12 | 12
|
|
INPUTS | 5 | RESET | D<9>.PIN | LAN_BASEADR_0__or0001/LAN_BASEADR_0__or0001_D2 | LAN_BASEADR<1> | SHUT_UP<2>/SHUT_UP<2>_CLKF
|
|
INPUTMC | 3 | 11 | 15 | 12 | 12 | 10 | 15
|
|
INPUTP | 2 | 263 | 73
|
|
EQ | 5 |
|
|
!LAN_BASEADR<1>.D = RESET & !LAN_BASEADR<1> &
|
|
!LAN_BASEADR_0__or0001/LAN_BASEADR_0__or0001_D2
|
|
# RESET & !D<9>.PIN &
|
|
LAN_BASEADR_0__or0001/LAN_BASEADR_0__or0001_D2;
|
|
LAN_BASEADR<1>.CLK = SHUT_UP<2>/SHUT_UP<2>_CLKF;
|
|
|
|
MACROCELL | 12 | 11 | LAN_BASEADR<2>
|
|
ATTRIBUTES | 8520480 | 0
|
|
OUTPUTMC | 2 | 12 | 11 | 7 | 9
|
|
INPUTS | 5 | RESET | D<10>.PIN | LAN_BASEADR_0__or0001/LAN_BASEADR_0__or0001_D2 | LAN_BASEADR<2> | SHUT_UP<2>/SHUT_UP<2>_CLKF
|
|
INPUTMC | 3 | 11 | 15 | 12 | 11 | 10 | 15
|
|
INPUTP | 2 | 263 | 74
|
|
EQ | 5 |
|
|
!LAN_BASEADR<2>.D = RESET & !LAN_BASEADR<2> &
|
|
!LAN_BASEADR_0__or0001/LAN_BASEADR_0__or0001_D2
|
|
# RESET & !D<10>.PIN &
|
|
LAN_BASEADR_0__or0001/LAN_BASEADR_0__or0001_D2;
|
|
LAN_BASEADR<2>.CLK = SHUT_UP<2>/SHUT_UP<2>_CLKF;
|
|
|
|
MACROCELL | 12 | 10 | LAN_BASEADR<3>
|
|
ATTRIBUTES | 8520480 | 0
|
|
OUTPUTMC | 2 | 7 | 6 | 12 | 10
|
|
INPUTS | 5 | RESET | D<11>.PIN | LAN_BASEADR_0__or0001/LAN_BASEADR_0__or0001_D2 | LAN_BASEADR<3> | SHUT_UP<2>/SHUT_UP<2>_CLKF
|
|
INPUTMC | 3 | 11 | 15 | 12 | 10 | 10 | 15
|
|
INPUTP | 2 | 263 | 77
|
|
EQ | 5 |
|
|
!LAN_BASEADR<3>.D = RESET & !LAN_BASEADR<3> &
|
|
!LAN_BASEADR_0__or0001/LAN_BASEADR_0__or0001_D2
|
|
# RESET & !D<11>.PIN &
|
|
LAN_BASEADR_0__or0001/LAN_BASEADR_0__or0001_D2;
|
|
LAN_BASEADR<3>.CLK = SHUT_UP<2>/SHUT_UP<2>_CLKF;
|
|
|
|
MACROCELL | 12 | 9 | LAN_BASEADR<4>
|
|
ATTRIBUTES | 8520480 | 0
|
|
OUTPUTMC | 2 | 7 | 7 | 12 | 9
|
|
INPUTS | 5 | RESET | D<12>.PIN | LAN_BASEADR_0__or0001/LAN_BASEADR_0__or0001_D2 | LAN_BASEADR<4> | SHUT_UP<2>/SHUT_UP<2>_CLKF
|
|
INPUTMC | 3 | 11 | 15 | 12 | 9 | 10 | 15
|
|
INPUTP | 2 | 263 | 78
|
|
EQ | 5 |
|
|
!LAN_BASEADR<4>.D = RESET & !LAN_BASEADR<4> &
|
|
!LAN_BASEADR_0__or0001/LAN_BASEADR_0__or0001_D2
|
|
# RESET & !D<12>.PIN &
|
|
LAN_BASEADR_0__or0001/LAN_BASEADR_0__or0001_D2;
|
|
LAN_BASEADR<4>.CLK = SHUT_UP<2>/SHUT_UP<2>_CLKF;
|
|
|
|
MACROCELL | 14 | 15 | LAN_BASEADR<5>
|
|
ATTRIBUTES | 8520480 | 0
|
|
OUTPUTMC | 2 | 7 | 6 | 14 | 15
|
|
INPUTS | 5 | RESET | D<13>.PIN | LAN_BASEADR_0__or0001/LAN_BASEADR_0__or0001_D2 | LAN_BASEADR<5> | SHUT_UP<2>/SHUT_UP<2>_CLKF
|
|
INPUTMC | 3 | 11 | 15 | 14 | 15 | 10 | 15
|
|
INPUTP | 2 | 263 | 80
|
|
EQ | 5 |
|
|
!LAN_BASEADR<5>.D = RESET & !LAN_BASEADR<5> &
|
|
!LAN_BASEADR_0__or0001/LAN_BASEADR_0__or0001_D2
|
|
# RESET & !D<13>.PIN &
|
|
LAN_BASEADR_0__or0001/LAN_BASEADR_0__or0001_D2;
|
|
LAN_BASEADR<5>.CLK = SHUT_UP<2>/SHUT_UP<2>_CLKF;
|
|
|
|
MACROCELL | 14 | 14 | LAN_BASEADR<6>
|
|
ATTRIBUTES | 8520480 | 0
|
|
OUTPUTMC | 2 | 14 | 14 | 7 | 8
|
|
INPUTS | 5 | RESET | D<14>.PIN | LAN_BASEADR_0__or0001/LAN_BASEADR_0__or0001_D2 | LAN_BASEADR<6> | SHUT_UP<2>/SHUT_UP<2>_CLKF
|
|
INPUTMC | 3 | 11 | 15 | 14 | 14 | 10 | 15
|
|
INPUTP | 2 | 263 | 81
|
|
EQ | 5 |
|
|
!LAN_BASEADR<6>.D = RESET & !LAN_BASEADR<6> &
|
|
!LAN_BASEADR_0__or0001/LAN_BASEADR_0__or0001_D2
|
|
# RESET & !D<14>.PIN &
|
|
LAN_BASEADR_0__or0001/LAN_BASEADR_0__or0001_D2;
|
|
LAN_BASEADR<6>.CLK = SHUT_UP<2>/SHUT_UP<2>_CLKF;
|
|
|
|
MACROCELL | 14 | 13 | LAN_BASEADR<7>
|
|
ATTRIBUTES | 8520480 | 0
|
|
OUTPUTMC | 3 | 7 | 6 | 14 | 13 | 7 | 8
|
|
INPUTS | 5 | RESET | D<15>.PIN | LAN_BASEADR_0__or0001/LAN_BASEADR_0__or0001_D2 | LAN_BASEADR<7> | SHUT_UP<2>/SHUT_UP<2>_CLKF
|
|
INPUTMC | 3 | 11 | 15 | 14 | 13 | 10 | 15
|
|
INPUTP | 2 | 263 | 89
|
|
EQ | 5 |
|
|
!LAN_BASEADR<7>.D = RESET & !LAN_BASEADR<7> &
|
|
!LAN_BASEADR_0__or0001/LAN_BASEADR_0__or0001_D2
|
|
# RESET & !D<15>.PIN &
|
|
LAN_BASEADR_0__or0001/LAN_BASEADR_0__or0001_D2;
|
|
LAN_BASEADR<7>.CLK = SHUT_UP<2>/SHUT_UP<2>_CLKF;
|
|
|
|
MACROCELL | 9 | 2 | DQ_0_IOBUFE$BUF0
|
|
ATTRIBUTES | 265986 | 0
|
|
INPUTS | 3 | D<0>.PIN | RW | $OpTx$FX_DC$6
|
|
INPUTMC | 1 | 15 | 15
|
|
INPUTP | 2 | 4 | 158
|
|
EQ | 2 |
|
|
DQ<0> = D<0>.PIN;
|
|
DQ<0>.OE = !RW & !$OpTx$FX_DC$6;
|
|
|
|
MACROCELL | 9 | 16 | DQ_10_IOBUFE$BUF0
|
|
ATTRIBUTES | 265986 | 0
|
|
INPUTS | 3 | D<10>.PIN | RW | $OpTx$FX_DC$6
|
|
INPUTMC | 1 | 15 | 15
|
|
INPUTP | 2 | 74 | 158
|
|
EQ | 2 |
|
|
DQ<10> = D<10>.PIN;
|
|
DQ<10>.OE = !RW & !$OpTx$FX_DC$6;
|
|
|
|
MACROCELL | 11 | 9 | DQ_11_IOBUFE$BUF0
|
|
ATTRIBUTES | 265986 | 0
|
|
INPUTS | 3 | D<11>.PIN | RW | $OpTx$FX_DC$6
|
|
INPUTMC | 1 | 15 | 15
|
|
INPUTP | 2 | 77 | 158
|
|
EQ | 2 |
|
|
DQ<11> = D<11>.PIN;
|
|
DQ<11>.OE = !RW & !$OpTx$FX_DC$6;
|
|
|
|
MACROCELL | 7 | 1 | DQ_12_IOBUFE$BUF0
|
|
ATTRIBUTES | 265986 | 0
|
|
INPUTS | 3 | D<12>.PIN | RW | $OpTx$FX_DC$6
|
|
INPUTMC | 1 | 15 | 15
|
|
INPUTP | 2 | 78 | 158
|
|
EQ | 2 |
|
|
DQ<12> = D<12>.PIN;
|
|
DQ<12>.OE = !RW & !$OpTx$FX_DC$6;
|
|
|
|
MACROCELL | 11 | 7 | DQ_13_IOBUFE$BUF0
|
|
ATTRIBUTES | 265986 | 0
|
|
INPUTS | 3 | D<13>.PIN | RW | $OpTx$FX_DC$6
|
|
INPUTMC | 1 | 15 | 15
|
|
INPUTP | 2 | 80 | 158
|
|
EQ | 2 |
|
|
DQ<13> = D<13>.PIN;
|
|
DQ<13>.OE = !RW & !$OpTx$FX_DC$6;
|
|
|
|
MACROCELL | 7 | 2 | DQ_14_IOBUFE$BUF0
|
|
ATTRIBUTES | 265986 | 0
|
|
INPUTS | 3 | D<14>.PIN | RW | $OpTx$FX_DC$6
|
|
INPUTMC | 1 | 15 | 15
|
|
INPUTP | 2 | 81 | 158
|
|
EQ | 2 |
|
|
DQ<14> = D<14>.PIN;
|
|
DQ<14>.OE = !RW & !$OpTx$FX_DC$6;
|
|
|
|
MACROCELL | 11 | 4 | DQ_15_IOBUFE$BUF0
|
|
ATTRIBUTES | 265986 | 0
|
|
INPUTS | 3 | D<15>.PIN | RW | $OpTx$FX_DC$6
|
|
INPUTMC | 1 | 15 | 15
|
|
INPUTP | 2 | 89 | 158
|
|
EQ | 2 |
|
|
DQ<15> = D<15>.PIN;
|
|
DQ<15>.OE = !RW & !$OpTx$FX_DC$6;
|
|
|
|
MACROCELL | 9 | 1 | DQ_1_IOBUFE$BUF0
|
|
ATTRIBUTES | 265986 | 0
|
|
INPUTS | 3 | D<1>.PIN | RW | $OpTx$FX_DC$6
|
|
INPUTMC | 1 | 15 | 15
|
|
INPUTP | 2 | 30 | 158
|
|
EQ | 2 |
|
|
DQ<1> = D<1>.PIN;
|
|
DQ<1>.OE = !RW & !$OpTx$FX_DC$6;
|
|
|
|
MACROCELL | 10 | 11 | DQ_2_IOBUFE$BUF0
|
|
ATTRIBUTES | 265986 | 0
|
|
INPUTS | 3 | D<2>.PIN | RW | $OpTx$FX_DC$6
|
|
INPUTMC | 1 | 15 | 15
|
|
INPUTP | 2 | 71 | 158
|
|
EQ | 2 |
|
|
DQ<2> = D<2>.PIN;
|
|
DQ<2>.OE = !RW & !$OpTx$FX_DC$6;
|
|
|
|
MACROCELL | 9 | 4 | DQ_3_IOBUFE$BUF0
|
|
ATTRIBUTES | 265986 | 0
|
|
INPUTS | 3 | D<3>.PIN | RW | $OpTx$FX_DC$6
|
|
INPUTMC | 1 | 15 | 15
|
|
INPUTP | 2 | 28 | 158
|
|
EQ | 2 |
|
|
DQ<3> = D<3>.PIN;
|
|
DQ<3>.OE = !RW & !$OpTx$FX_DC$6;
|
|
|
|
MACROCELL | 9 | 9 | DQ_4_IOBUFE$BUF0
|
|
ATTRIBUTES | 265986 | 0
|
|
INPUTS | 3 | D<4>.PIN | RW | $OpTx$FX_DC$6
|
|
INPUTMC | 1 | 15 | 15
|
|
INPUTP | 2 | 38 | 158
|
|
EQ | 2 |
|
|
DQ<4> = D<4>.PIN;
|
|
DQ<4>.OE = !RW & !$OpTx$FX_DC$6;
|
|
|
|
MACROCELL | 4 | 7 | DQ_5_IOBUFE$BUF0
|
|
ATTRIBUTES | 265986 | 0
|
|
INPUTS | 3 | D<5>.PIN | RW | $OpTx$FX_DC$6
|
|
INPUTMC | 1 | 15 | 15
|
|
INPUTP | 2 | 37 | 158
|
|
EQ | 2 |
|
|
DQ<5> = D<5>.PIN;
|
|
DQ<5>.OE = !RW & !$OpTx$FX_DC$6;
|
|
|
|
MACROCELL | 9 | 11 | DQ_6_IOBUFE$BUF0
|
|
ATTRIBUTES | 265986 | 0
|
|
INPUTS | 3 | D<6>.PIN | RW | $OpTx$FX_DC$6
|
|
INPUTMC | 1 | 15 | 15
|
|
INPUTP | 2 | 26 | 158
|
|
EQ | 2 |
|
|
DQ<6> = D<6>.PIN;
|
|
DQ<6>.OE = !RW & !$OpTx$FX_DC$6;
|
|
|
|
MACROCELL | 9 | 10 | DQ_7_IOBUFE$BUF0
|
|
ATTRIBUTES | 265986 | 0
|
|
INPUTS | 3 | D<7>.PIN | RW | $OpTx$FX_DC$6
|
|
INPUTMC | 1 | 15 | 15
|
|
INPUTP | 2 | 29 | 158
|
|
EQ | 2 |
|
|
DQ<7> = D<7>.PIN;
|
|
DQ<7>.OE = !RW & !$OpTx$FX_DC$6;
|
|
|
|
MACROCELL | 9 | 13 | DQ_8_IOBUFE$BUF0
|
|
ATTRIBUTES | 265986 | 0
|
|
INPUTS | 3 | D<8>.PIN | RW | $OpTx$FX_DC$6
|
|
INPUTMC | 1 | 15 | 15
|
|
INPUTP | 2 | 32 | 158
|
|
EQ | 2 |
|
|
DQ<8> = D<8>.PIN;
|
|
DQ<8>.OE = !RW & !$OpTx$FX_DC$6;
|
|
|
|
MACROCELL | 11 | 11 | DQ_9_IOBUFE$BUF0
|
|
ATTRIBUTES | 265986 | 0
|
|
INPUTS | 3 | D<9>.PIN | RW | $OpTx$FX_DC$6
|
|
INPUTMC | 1 | 15 | 15
|
|
INPUTP | 2 | 73 | 158
|
|
EQ | 2 |
|
|
DQ<9> = D<9>.PIN;
|
|
DQ<9>.OE = !RW & !$OpTx$FX_DC$6;
|
|
|
|
MACROCELL | 1 | 15 | CP_RD_S
|
|
ATTRIBUTES | 8520480 | 0
|
|
OUTPUTMC | 1 | 12 | 1
|
|
INPUTS | 5 | RW | RESET | CP_CS | $OpTx$FX_DC$6 | SHUT_UP<2>/SHUT_UP<2>_CLKF
|
|
INPUTMC | 3 | 4 | 1 | 15 | 15 | 10 | 15
|
|
INPUTP | 2 | 158 | 263
|
|
EQ | 2 |
|
|
!CP_RD_S.D = RW & RESET & !CP_CS & !$OpTx$FX_DC$6;
|
|
CP_RD_S.CLK = SHUT_UP<2>/SHUT_UP<2>_CLKF;
|
|
|
|
MACROCELL | 1 | 12 | CP_WE_S
|
|
ATTRIBUTES | 8520480 | 0
|
|
OUTPUTMC | 1 | 10 | 16
|
|
INPUTS | 5 | RW | RESET | CP_CS | $OpTx$FX_DC$6 | SHUT_UP<2>/SHUT_UP<2>_CLKF
|
|
INPUTMC | 3 | 4 | 1 | 15 | 15 | 10 | 15
|
|
INPUTP | 2 | 158 | 263
|
|
EQ | 2 |
|
|
!CP_WE_S.D = !RW & RESET & !CP_CS & !$OpTx$FX_DC$6;
|
|
CP_WE_S.CLK = SHUT_UP<2>/SHUT_UP<2>_CLKF;
|
|
|
|
MACROCELL | 0 | 12 | IDE_R_S
|
|
ATTRIBUTES | 8520480 | 0
|
|
OUTPUTMC | 1 | 0 | 16
|
|
INPUTS | 6 | AS | RW | RESET | ide | IDE_ENABLE | SHUT_UP<2>/SHUT_UP<2>_CLKF
|
|
INPUTMC | 3 | 8 | 16 | 0 | 15 | 10 | 15
|
|
INPUTP | 3 | 152 | 158 | 263
|
|
EQ | 2 |
|
|
!IDE_R_S.D = !AS & RW & RESET & ide & !IDE_ENABLE;
|
|
IDE_R_S.CLK = SHUT_UP<2>/SHUT_UP<2>_CLKF;
|
|
|
|
MACROCELL | 0 | 10 | IDE_W_S
|
|
ATTRIBUTES | 8520480 | 0
|
|
OUTPUTMC | 1 | 2 | 1
|
|
INPUTS | 5 | AS | RW | RESET | ide | SHUT_UP<2>/SHUT_UP<2>_CLKF
|
|
INPUTMC | 2 | 8 | 16 | 10 | 15
|
|
INPUTP | 3 | 152 | 158 | 263
|
|
EQ | 2 |
|
|
!IDE_W_S.D = !AS & !RW & RESET & ide;
|
|
IDE_W_S.CLK = SHUT_UP<2>/SHUT_UP<2>_CLKF;
|
|
|
|
MACROCELL | 1 | 6 | LAN_RD_S
|
|
ATTRIBUTES | 8520480 | 0
|
|
OUTPUTMC | 1 | 7 | 9
|
|
INPUTS | 5 | RW | RESET | LAN_CS | $OpTx$FX_DC$6 | SHUT_UP<2>/SHUT_UP<2>_CLKF
|
|
INPUTMC | 3 | 7 | 7 | 15 | 15 | 10 | 15
|
|
INPUTP | 2 | 158 | 263
|
|
EQ | 2 |
|
|
LAN_RD_S.D = RW & RESET & LAN_CS & !$OpTx$FX_DC$6;
|
|
LAN_RD_S.CLK = SHUT_UP<2>/SHUT_UP<2>_CLKF;
|
|
|
|
MACROCELL | 1 | 3 | LAN_WRH_S
|
|
ATTRIBUTES | 8520480 | 0
|
|
OUTPUTMC | 1 | 7 | 4
|
|
INPUTS | 5 | RW | RESET | LAN_CS | UDS | SHUT_UP<2>/SHUT_UP<2>_CLKF
|
|
INPUTMC | 2 | 7 | 7 | 10 | 15
|
|
INPUTP | 3 | 158 | 263 | 155
|
|
EQ | 2 |
|
|
LAN_WRH_S.D = !RW & RESET & LAN_CS & !UDS;
|
|
LAN_WRH_S.CLK = SHUT_UP<2>/SHUT_UP<2>_CLKF;
|
|
|
|
MACROCELL | 1 | 0 | LAN_WRL_S
|
|
ATTRIBUTES | 8520480 | 0
|
|
OUTPUTMC | 1 | 12 | 13
|
|
INPUTS | 5 | RW | RESET | LAN_CS | LDS | SHUT_UP<2>/SHUT_UP<2>_CLKF
|
|
INPUTMC | 2 | 7 | 7 | 10 | 15
|
|
INPUTP | 3 | 158 | 263 | 157
|
|
EQ | 2 |
|
|
LAN_WRL_S.D = !RW & RESET & LAN_CS & !LDS;
|
|
LAN_WRL_S.CLK = SHUT_UP<2>/SHUT_UP<2>_CLKF;
|
|
|
|
MACROCELL | 0 | 8 | ROM_OE_S
|
|
ATTRIBUTES | 8520480 | 0
|
|
OUTPUTMC | 1 | 4 | 4
|
|
INPUTS | 6 | AS | RW | RESET | ide | IDE_ENABLE | SHUT_UP<2>/SHUT_UP<2>_CLKF
|
|
INPUTMC | 3 | 8 | 16 | 0 | 15 | 10 | 15
|
|
INPUTP | 3 | 152 | 158 | 263
|
|
EQ | 2 |
|
|
!ROM_OE_S.D = !AS & RW & RESET & ide & IDE_ENABLE;
|
|
ROM_OE_S.CLK = SHUT_UP<2>/SHUT_UP<2>_CLKF;
|
|
|
|
MACROCELL | 12 | 1 | CP_RD_OBUF
|
|
ATTRIBUTES | 264962 | 0
|
|
INPUTS | 2 | AS | CP_RD_S
|
|
INPUTMC | 1 | 1 | 15
|
|
INPUTP | 1 | 152
|
|
EQ | 1 |
|
|
!CP_RD = !AS & !CP_RD_S;
|
|
|
|
MACROCELL | 10 | 16 | CP_WE_OBUF
|
|
ATTRIBUTES | 264962 | 0
|
|
INPUTS | 2 | AS | CP_WE_S
|
|
INPUTMC | 1 | 1 | 12
|
|
INPUTP | 1 | 152
|
|
EQ | 1 |
|
|
!CP_WE = !AS & !CP_WE_S;
|
|
|
|
MACROCELL | 0 | 16 | IDE_R_OBUF
|
|
ATTRIBUTES | 264962 | 0
|
|
INPUTS | 2 | AS | IDE_R_S
|
|
INPUTMC | 1 | 0 | 12
|
|
INPUTP | 1 | 152
|
|
EQ | 1 |
|
|
!IDE_R = !AS & !IDE_R_S;
|
|
|
|
MACROCELL | 2 | 1 | IDE_W_OBUF
|
|
ATTRIBUTES | 264962 | 0
|
|
INPUTS | 2 | AS | IDE_W_S
|
|
INPUTMC | 1 | 0 | 10
|
|
INPUTP | 1 | 152
|
|
EQ | 1 |
|
|
!IDE_W = !AS & !IDE_W_S;
|
|
|
|
MACROCELL | 4 | 4 | ROM_OE_OBUF
|
|
ATTRIBUTES | 264962 | 0
|
|
INPUTS | 2 | AS | ROM_OE_S
|
|
INPUTMC | 1 | 0 | 8
|
|
INPUTP | 1 | 152
|
|
EQ | 1 |
|
|
!ROM_OE = !AS & !ROM_OE_S;
|
|
|
|
MACROCELL | 7 | 9 | LAN_RD_OBUF
|
|
ATTRIBUTES | 264962 | 0
|
|
OUTPUTMC | 1 | 7 | 8
|
|
INPUTS | 4 | AS | LAN_RD_S | LAN_BASEADR<2> | A<18>
|
|
INPUTMC | 2 | 1 | 6 | 12 | 11
|
|
INPUTP | 2 | 152 | 171
|
|
EXPORTS | 1 | 7 | 8
|
|
EQ | 3 |
|
|
LAN_RD = !AS & LAN_RD_S;
|
|
LAN_RD_OBUF.EXP = LAN_BASEADR<2> & !A<18>
|
|
# !LAN_BASEADR<2> & A<18>
|
|
|
|
MACROCELL | 7 | 4 | LAN_WRH_OBUF
|
|
ATTRIBUTES | 264962 | 0
|
|
INPUTS | 2 | AS | LAN_WRH_S
|
|
INPUTMC | 1 | 1 | 3
|
|
INPUTP | 1 | 152
|
|
EQ | 1 |
|
|
LAN_WRH = !AS & LAN_WRH_S;
|
|
|
|
MACROCELL | 12 | 13 | LAN_WRL_OBUF
|
|
ATTRIBUTES | 264962 | 0
|
|
INPUTS | 2 | AS | LAN_WRL_S
|
|
INPUTMC | 1 | 1 | 0
|
|
INPUTP | 1 | 152
|
|
EQ | 1 |
|
|
LAN_WRL = !AS & LAN_WRL_S;
|
|
|
|
MACROCELL | 13 | 14 | ROM_B_0_OBUF$BUF1
|
|
ATTRIBUTES | 265986 | 0
|
|
INPUTS | 1 | SLAVE
|
|
INPUTMC | 1 | 13 | 13
|
|
EQ | 2 |
|
|
OWN = Gnd;
|
|
OWN.OE = !SLAVE;
|
|
|
|
MACROCELL | 13 | 2 | ROM_B_0_OBUF$BUF2
|
|
ATTRIBUTES | 265986 | 0
|
|
INPUTS | 2 | AS | ide
|
|
INPUTMC | 1 | 8 | 16
|
|
INPUTP | 1 | 152
|
|
EQ | 2 |
|
|
OVR = Gnd;
|
|
OVR.OE = !AS & ide;
|
|
|
|
MACROCELL | 2 | 13 | ROM_B_0_OBUF$BUF7
|
|
ATTRIBUTES | 265986 | 0
|
|
INPUTS | 1 | CP_IRQ
|
|
INPUTP | 1 | 59
|
|
EQ | 2 |
|
|
INT_OUT = Gnd;
|
|
INT_OUT.OE = !CP_IRQ;
|
|
|
|
MACROCELL | 14 | 11 | ROM_B_0_OBUF$BUF8
|
|
ATTRIBUTES | 265986 | 0
|
|
INPUTS | 3 | AS | ide | IDE_WAIT
|
|
INPUTMC | 1 | 8 | 16
|
|
INPUTP | 2 | 152 | 61
|
|
EQ | 2 |
|
|
DTACK = Gnd;
|
|
DTACK.OE = !AS & ide & IDE_WAIT;
|
|
|
|
MACROCELL | 3 | 5 | A_LAN_0_OBUF$BUF0
|
|
ATTRIBUTES | 264962 | 0
|
|
INPUTS | 1 | A<1>
|
|
INPUTP | 1 | 107
|
|
EQ | 1 |
|
|
A_LAN<0> = A<1>;
|
|
|
|
MACROCELL | 0 | 13 | A_LAN_10_OBUF$BUF0
|
|
ATTRIBUTES | 264962 | 0
|
|
INPUTS | 1 | A<11>
|
|
INPUTP | 1 | 114
|
|
EQ | 1 |
|
|
IDE_A<2> = A<11>;
|
|
|
|
MACROCELL | 5 | 5 | A_LAN_10_OBUF$BUF1
|
|
ATTRIBUTES | 264962 | 0
|
|
INPUTS | 1 | A<11>
|
|
INPUTP | 1 | 114
|
|
EQ | 1 |
|
|
A_LAN<10> = A<11>;
|
|
|
|
MACROCELL | 5 | 7 | A_LAN_11_OBUF$BUF0
|
|
ATTRIBUTES | 264962 | 0
|
|
INPUTS | 1 | A<12>
|
|
INPUTP | 1 | 115
|
|
EQ | 1 |
|
|
A_LAN<11> = A<12>;
|
|
|
|
MACROCELL | 5 | 4 | A_LAN_12_OBUF$BUF0
|
|
ATTRIBUTES | 264962 | 0
|
|
INPUTS | 1 | A<13>
|
|
INPUTP | 1 | 123
|
|
EQ | 1 |
|
|
A_LAN<12> = A<13>;
|
|
|
|
MACROCELL | 5 | 2 | A_LAN_13_OBUF$BUF0
|
|
ATTRIBUTES | 264962 | 0
|
|
INPUTS | 1 | A<14>
|
|
INPUTP | 1 | 125
|
|
EQ | 1 |
|
|
A_LAN<13> = A<14>;
|
|
|
|
MACROCELL | 3 | 4 | A_LAN_1_OBUF$BUF0
|
|
ATTRIBUTES | 264962 | 0
|
|
INPUTS | 1 | A<2>
|
|
INPUTP | 1 | 101
|
|
EQ | 1 |
|
|
A_LAN<1> = A<2>;
|
|
|
|
MACROCELL | 3 | 11 | A_LAN_2_OBUF$BUF0
|
|
ATTRIBUTES | 264962 | 0
|
|
INPUTS | 1 | A<3>
|
|
INPUTP | 1 | 99
|
|
EQ | 1 |
|
|
A_LAN<2> = A<3>;
|
|
|
|
MACROCELL | 3 | 7 | A_LAN_3_OBUF$BUF0
|
|
ATTRIBUTES | 264962 | 0
|
|
INPUTS | 1 | A<4>
|
|
INPUTP | 1 | 97
|
|
EQ | 1 |
|
|
A_LAN<3> = A<4>;
|
|
|
|
MACROCELL | 1 | 1 | A_LAN_4_OBUF$BUF0
|
|
ATTRIBUTES | 264962 | 0
|
|
INPUTS | 1 | A<5>
|
|
INPUTP | 1 | 91
|
|
EQ | 1 |
|
|
A_LAN<4> = A<5>;
|
|
|
|
MACROCELL | 3 | 13 | A_LAN_5_OBUF$BUF0
|
|
ATTRIBUTES | 264962 | 0
|
|
INPUTS | 1 | A<6>
|
|
INPUTP | 1 | 98
|
|
EQ | 1 |
|
|
A_LAN<5> = A<6>;
|
|
|
|
MACROCELL | 1 | 4 | A_LAN_6_OBUF$BUF0
|
|
ATTRIBUTES | 264962 | 0
|
|
INPUTS | 1 | A<7>
|
|
INPUTP | 1 | 100
|
|
EQ | 1 |
|
|
A_LAN<6> = A<7>;
|
|
|
|
MACROCELL | 1 | 2 | A_LAN_7_OBUF$BUF0
|
|
ATTRIBUTES | 264962 | 0
|
|
INPUTS | 1 | A<8>
|
|
INPUTP | 1 | 106
|
|
EQ | 1 |
|
|
A_LAN<7> = A<8>;
|
|
|
|
MACROCELL | 0 | 11 | A_LAN_8_OBUF$BUF0
|
|
ATTRIBUTES | 264962 | 0
|
|
INPUTS | 1 | A<9>
|
|
INPUTP | 1 | 108
|
|
EQ | 1 |
|
|
IDE_A<0> = A<9>;
|
|
|
|
MACROCELL | 5 | 9 | A_LAN_8_OBUF$BUF1
|
|
ATTRIBUTES | 264962 | 0
|
|
INPUTS | 1 | A<9>
|
|
INPUTP | 1 | 108
|
|
EQ | 1 |
|
|
A_LAN<8> = A<9>;
|
|
|
|
MACROCELL | 0 | 14 | A_LAN_9_OBUF$BUF0
|
|
ATTRIBUTES | 264962 | 0
|
|
INPUTS | 1 | A<10>
|
|
INPUTP | 1 | 112
|
|
EQ | 1 |
|
|
IDE_A<1> = A<10>;
|
|
|
|
MACROCELL | 5 | 13 | A_LAN_9_OBUF$BUF1
|
|
ATTRIBUTES | 264962 | 0
|
|
INPUTS | 1 | A<10>
|
|
INPUTP | 1 | 112
|
|
EQ | 1 |
|
|
A_LAN<9> = A<10>;
|
|
|
|
MACROCELL | 4 | 1 | CP_CS_OBUF
|
|
ATTRIBUTES | 8782758 | 0
|
|
OUTPUTMC | 4 | 1 | 15 | 1 | 12 | 13 | 13 | 1 | 17
|
|
INPUTS | 7 | SHUT_UP<1> | CP_BASEADR<4> | A<20> | EXP21_.EXP | EXP22_.EXP | SHUT_UP<2>/SHUT_UP<2>_CLKF | lan/lan_RSTF
|
|
INPUTMC | 6 | 14 | 10 | 6 | 14 | 4 | 0 | 4 | 2 | 10 | 15 | 5 | 11
|
|
INPUTP | 1 | 167
|
|
IMPORTS | 2 | 4 | 0 | 4 | 2
|
|
EQ | 22 |
|
|
CP_CS.D = SHUT_UP<1>
|
|
# CP_BASEADR<4> & !A<20>
|
|
# !CP_BASEADR<4> & A<20>
|
|
;Imported pterms FB5_1
|
|
# CP_BASEADR<3> & !A<19>
|
|
# !CP_BASEADR<3> & A<19>
|
|
# CP_BASEADR<5> & !A<21>
|
|
# !CP_BASEADR<5> & A<21>
|
|
# CP_BASEADR<6> & !A<22>
|
|
;Imported pterms FB5_3
|
|
# CP_BASEADR<0> & !A<16>
|
|
# !CP_BASEADR<0> & A<16>
|
|
# !CP_BASEADR<6> & A<22>
|
|
# CP_BASEADR<7> & !A<23>
|
|
# !CP_BASEADR<7> & A<23>
|
|
;Imported pterms FB5_4
|
|
# CP_BASEADR<1> & !A<17>
|
|
# !CP_BASEADR<1> & A<17>
|
|
# CP_BASEADR<2> & !A<18>
|
|
# !CP_BASEADR<2> & A<18>;
|
|
CP_CS.CLK = !SHUT_UP<2>/SHUT_UP<2>_CLKF;
|
|
CP_CS.AP = !lan/lan_RSTF;
|
|
|
|
MACROCELL | 0 | 7 | IDE_CS_0_OBUF
|
|
ATTRIBUTES | 264962 | 0
|
|
INPUTS | 1 | A<12>
|
|
INPUTP | 1 | 115
|
|
EQ | 1 |
|
|
IDE_CS<0> = !A<12>;
|
|
|
|
MACROCELL | 0 | 9 | IDE_CS_1_OBUF
|
|
ATTRIBUTES | 264962 | 0
|
|
INPUTS | 1 | A<13>
|
|
INPUTP | 1 | 123
|
|
EQ | 1 |
|
|
IDE_CS<1> = !A<13>;
|
|
|
|
MACROCELL | 13 | 13 | SLAVE_OBUF
|
|
ATTRIBUTES | 396034 | 0
|
|
OUTPUTMC | 1 | 13 | 14
|
|
INPUTS | 5 | AS | LAN_CS | ide | autoconfig | CP_CS
|
|
INPUTMC | 4 | 7 | 7 | 8 | 16 | 15 | 16 | 4 | 1
|
|
INPUTP | 1 | 152
|
|
EQ | 2 |
|
|
SLAVE = AS
|
|
# !LAN_CS & !ide & !autoconfig & CP_CS;
|
|
|
|
MACROCELL | 11 | 1 | ROM_B_0_OBUF$BUF3
|
|
ATTRIBUTES | 265986 | 0
|
|
INPUTS | 0
|
|
EQ | 2 |
|
|
LAN_CFG<4> = Gnd;
|
|
LAN_CFG<4>.OE = Gnd;
|
|
|
|
MACROCELL | 1 | 7 | ROM_B_0_OBUF$BUF4
|
|
ATTRIBUTES | 265986 | 0
|
|
INPUTS | 0
|
|
EQ | 2 |
|
|
LAN_CFG<3> = Gnd;
|
|
LAN_CFG<3>.OE = Gnd;
|
|
|
|
MACROCELL | 5 | 1 | ROM_B_0_OBUF$BUF5
|
|
ATTRIBUTES | 265986 | 0
|
|
INPUTS | 0
|
|
EQ | 2 |
|
|
LAN_CFG<2> = Gnd;
|
|
LAN_CFG<2>.OE = Gnd;
|
|
|
|
MACROCELL | 1 | 5 | ROM_B_0_OBUF$BUF6
|
|
ATTRIBUTES | 265986 | 0
|
|
INPUTS | 0
|
|
EQ | 2 |
|
|
LAN_CFG<1> = Gnd;
|
|
LAN_CFG<1>.OE = Gnd;
|
|
|
|
MACROCELL | 13 | 10 | CFOUT_OBUF
|
|
ATTRIBUTES | 264962 | 0
|
|
INPUTS | 0
|
|
EQ | 1 |
|
|
CFOUT = Vcc;
|
|
|
|
MACROCELL | 10 | 13 | ROM_B_0_OBUF
|
|
ATTRIBUTES | 264962 | 0
|
|
INPUTS | 0
|
|
EQ | 1 |
|
|
ROM_B<1> = Gnd;
|
|
|
|
MACROCELL | 12 | 7 | ROM_B_0_OBUF$BUF0
|
|
ATTRIBUTES | 264962 | 0
|
|
INPUTS | 0
|
|
EQ | 1 |
|
|
ROM_B<0> = Gnd;
|
|
|
|
MACROCELL | 10 | 15 | SHUT_UP<2>/SHUT_UP<2>_CLKF
|
|
ATTRIBUTES | 133888 | 0
|
|
OUTPUTMC | 48 | 7 | 7 | 6 | 17 | 0 | 17 | 6 | 16 | 8 | 16 | 6 | 15 | 14 | 12 | 14 | 10 | 13 | 17 | 15 | 16 | 0 | 15 | 9 | 17 | 9 | 15 | 9 | 14 | 9 | 12 | 6 | 14 | 5 | 17 | 5 | 16 | 5 | 15 | 2 | 16 | 3 | 17 | 3 | 0 | 3 | 15 | 15 | 17 | 12 | 17 | 12 | 16 | 12 | 15 | 12 | 14 | 5 | 14 | 5 | 12 | 14 | 17 | 14 | 16 | 12 | 12 | 12 | 11 | 12 | 10 | 12 | 9 | 14 | 15 | 14 | 14 | 14 | 13 | 1 | 15 | 1 | 12 | 0 | 12 | 0 | 10 | 1 | 6 | 1 | 3 | 1 | 0 | 0 | 8 | 4 | 1
|
|
INPUTS | 2 | C1 | C3
|
|
INPUTP | 2 | 188 | 187
|
|
EQ | 2 |
|
|
SHUT_UP<2>/SHUT_UP<2>_CLKF = C1
|
|
$ C3;
|
|
|
|
MACROCELL | 5 | 11 | lan/lan_RSTF
|
|
ATTRIBUTES | 133888 | 0
|
|
OUTPUTMC | 4 | 7 | 7 | 8 | 16 | 15 | 16 | 4 | 1
|
|
INPUTS | 2 | RESET | BERR
|
|
INPUTP | 2 | 263 | 176
|
|
EQ | 1 |
|
|
lan/lan_RSTF = RESET & BERR;
|
|
|
|
MACROCELL | 1 | 10 | D_8_IOBUFE/D_8_IOBUFE_TRST
|
|
ATTRIBUTES | 133888 | 0
|
|
OUTPUTMC | 15 | 3 | 1 | 4 | 13 | 4 | 14 | 4 | 16 | 6 | 2 | 6 | 4 | 6 | 11 | 1 | 14 | 4 | 9 | 1 | 11 | 0 | 5 | 0 | 4 | 1 | 9 | 1 | 13 | 1 | 16
|
|
INPUTS | 4 | $OpTx$INV$5 | RW | autoconfig | $OpTx$FX_DC$6
|
|
INPUTMC | 3 | 1 | 17 | 15 | 16 | 15 | 15
|
|
INPUTP | 1 | 158
|
|
EQ | 2 |
|
|
D_8_IOBUFE/D_8_IOBUFE_TRST = $OpTx$INV$5
|
|
# RW & autoconfig & !$OpTx$FX_DC$6;
|
|
|
|
MACROCELL | 15 | 15 | $OpTx$FX_DC$6
|
|
ATTRIBUTES | 133888 | 0
|
|
OUTPUTMC | 26 | 9 | 2 | 9 | 16 | 11 | 9 | 7 | 1 | 11 | 7 | 7 | 2 | 11 | 4 | 9 | 1 | 10 | 11 | 9 | 4 | 9 | 9 | 4 | 7 | 9 | 11 | 9 | 10 | 9 | 13 | 11 | 11 | 1 | 15 | 1 | 12 | 1 | 6 | 1 | 10 | 1 | 17 | 1 | 8 | 11 | 17 | 11 | 15 | 11 | 16 | 13 | 16
|
|
INPUTS | 2 | UDS | LDS
|
|
INPUTP | 2 | 155 | 157
|
|
EQ | 1 |
|
|
$OpTx$FX_DC$6 = UDS & LDS;
|
|
|
|
MACROCELL | 1 | 17 | $OpTx$INV$5
|
|
ATTRIBUTES | 133888 | 0
|
|
OUTPUTMC | 18 | 3 | 1 | 4 | 13 | 4 | 14 | 4 | 16 | 6 | 2 | 6 | 4 | 6 | 11 | 1 | 14 | 4 | 9 | 1 | 11 | 0 | 5 | 0 | 4 | 1 | 9 | 1 | 13 | 1 | 16 | 4 | 11 | 1 | 10 | 1 | 8
|
|
INPUTS | 4 | RW | CP_CS | $OpTx$FX_DC$6 | LAN_CS
|
|
INPUTMC | 3 | 4 | 1 | 15 | 15 | 7 | 7
|
|
INPUTP | 1 | 158
|
|
EQ | 2 |
|
|
$OpTx$INV$5 = RW & LAN_CS & !$OpTx$FX_DC$6
|
|
# RW & !CP_CS & !$OpTx$FX_DC$6;
|
|
|
|
MACROCELL | 1 | 8 | D_9_IOBUFE/D_9_IOBUFE_TRST
|
|
ATTRIBUTES | 133888 | 0
|
|
OUTPUTMC | 1 | 4 | 11
|
|
INPUTS | 4 | $OpTx$INV$5 | RW | autoconfig | $OpTx$FX_DC$6
|
|
INPUTMC | 3 | 1 | 17 | 15 | 16 | 15 | 15
|
|
INPUTP | 1 | 158
|
|
EQ | 2 |
|
|
D_9_IOBUFE/D_9_IOBUFE_TRST = $OpTx$INV$5
|
|
# RW & autoconfig & !$OpTx$FX_DC$6;
|
|
|
|
MACROCELL | 11 | 17 | AUTO_CONFIG_DONE_CYCLE_0__or0000/AUTO_CONFIG_DONE_CYCLE_0__or0000_D2
|
|
ATTRIBUTES | 133888 | 0
|
|
OUTPUTMC | 11 | 6 | 16 | 6 | 15 | 2 | 16 | 3 | 17 | 3 | 0 | 3 | 15 | 3 | 14 | 2 | 15 | 2 | 17 | 3 | 1 | 3 | 16
|
|
INPUTS | 4 | RESET | AS | autoconfig | $OpTx$FX_DC$6
|
|
INPUTMC | 2 | 15 | 16 | 15 | 15
|
|
INPUTP | 2 | 263 | 152
|
|
EQ | 2 |
|
|
AUTO_CONFIG_DONE_CYCLE_0__or0000/AUTO_CONFIG_DONE_CYCLE_0__or0000_D2 = !RESET
|
|
# !AS & autoconfig & !$OpTx$FX_DC$6;
|
|
|
|
MACROCELL | 10 | 17 | N32/N32_D2
|
|
ATTRIBUTES | 133888 | 0
|
|
OUTPUTMC | 2 | 6 | 16 | 6 | 15
|
|
INPUTS | 13 | RW | A<6> | A<5> | A<3> | A<4> | A<1> | A<2> | $OpTx$FX_DC$8 | AUTO_CONFIG_DONE<1> | AUTO_CONFIG_DONE<0> | SHUT_UP<0> | SHUT_UP<1> | SHUT_UP<2>
|
|
INPUTMC | 6 | 0 | 3 | 6 | 17 | 0 | 17 | 14 | 12 | 14 | 10 | 13 | 17
|
|
INPUTP | 7 | 158 | 98 | 91 | 99 | 97 | 107 | 101
|
|
EQ | 8 |
|
|
N32/N32_D2 = !RW & A<6> & !A<5> & A<3> & !A<4> & !A<1> & A<2> &
|
|
!$OpTx$FX_DC$8
|
|
# !RW & AUTO_CONFIG_DONE<1> & !AUTO_CONFIG_DONE<0> &
|
|
SHUT_UP<2> & A<6> & !A<5> & A<3> & !A<4> & !A<1>
|
|
# !RW & !AUTO_CONFIG_DONE<1> & AUTO_CONFIG_DONE<0> &
|
|
SHUT_UP<1> & A<6> & !A<5> & A<3> & !A<4> & !A<1>
|
|
# !RW & !AUTO_CONFIG_DONE<1> & !AUTO_CONFIG_DONE<0> &
|
|
SHUT_UP<0> & A<6> & !A<5> & A<3> & !A<4> & !A<1>;
|
|
|
|
MACROCELL | 0 | 3 | $OpTx$FX_DC$8
|
|
ATTRIBUTES | 133888 | 0
|
|
OUTPUTMC | 2 | 15 | 16 | 10 | 17
|
|
INPUTS | 2 | AUTO_CONFIG_DONE<1> | AUTO_CONFIG_DONE<0>
|
|
INPUTMC | 2 | 6 | 17 | 0 | 17
|
|
EQ | 1 |
|
|
$OpTx$FX_DC$8 = AUTO_CONFIG_DONE<1> & AUTO_CONFIG_DONE<0>;
|
|
|
|
MACROCELL | 11 | 15 | LAN_BASEADR_0__or0001/LAN_BASEADR_0__or0001_D2
|
|
ATTRIBUTES | 133888 | 0
|
|
OUTPUTMC | 9 | 14 | 12 | 14 | 16 | 12 | 12 | 12 | 11 | 12 | 10 | 12 | 9 | 14 | 15 | 14 | 14 | 14 | 13
|
|
INPUTS | 14 | RESET | AS | RW | AUTO_CONFIG_DONE<1> | AUTO_CONFIG_DONE<0> | SHUT_UP<0> | autoconfig | A<6> | A<5> | A<3> | A<4> | A<1> | A<2> | $OpTx$FX_DC$6
|
|
INPUTMC | 5 | 6 | 17 | 0 | 17 | 14 | 12 | 15 | 16 | 15 | 15
|
|
INPUTP | 9 | 263 | 152 | 158 | 98 | 91 | 99 | 97 | 107 | 101
|
|
EQ | 4 |
|
|
LAN_BASEADR_0__or0001/LAN_BASEADR_0__or0001_D2 = !RESET
|
|
# !AS & !RW & !AUTO_CONFIG_DONE<1> &
|
|
!AUTO_CONFIG_DONE<0> & SHUT_UP<0> & autoconfig & A<6> & !A<5> & A<3> &
|
|
!A<4> & !A<1> & !A<2> & !$OpTx$FX_DC$6;
|
|
|
|
MACROCELL | 11 | 16 | CP_BASEADR_0__or0001/CP_BASEADR_0__or0001_D2
|
|
ATTRIBUTES | 133888 | 0
|
|
OUTPUTMC | 9 | 14 | 10 | 9 | 17 | 9 | 15 | 9 | 14 | 9 | 12 | 6 | 14 | 5 | 17 | 5 | 16 | 5 | 15
|
|
INPUTS | 14 | RESET | AS | RW | AUTO_CONFIG_DONE<1> | AUTO_CONFIG_DONE<0> | SHUT_UP<1> | autoconfig | A<6> | A<5> | A<3> | A<4> | A<1> | A<2> | $OpTx$FX_DC$6
|
|
INPUTMC | 5 | 6 | 17 | 0 | 17 | 14 | 10 | 15 | 16 | 15 | 15
|
|
INPUTP | 9 | 263 | 152 | 158 | 98 | 91 | 99 | 97 | 107 | 101
|
|
EQ | 4 |
|
|
CP_BASEADR_0__or0001/CP_BASEADR_0__or0001_D2 = !RESET
|
|
# !AS & !RW & !AUTO_CONFIG_DONE<1> &
|
|
AUTO_CONFIG_DONE<0> & SHUT_UP<1> & autoconfig & A<6> & !A<5> & A<3> &
|
|
!A<4> & !A<1> & !A<2> & !$OpTx$FX_DC$6;
|
|
|
|
MACROCELL | 13 | 16 | IDE_BASEADR_0__or0001/IDE_BASEADR_0__or0001_D2
|
|
ATTRIBUTES | 133888 | 0
|
|
OUTPUTMC | 9 | 13 | 17 | 15 | 17 | 12 | 17 | 12 | 16 | 12 | 15 | 12 | 14 | 5 | 14 | 5 | 12 | 14 | 17
|
|
INPUTS | 13 | RESET | AS | RW | SHUT_UP<2> | autoconfig | A<6> | A<5> | A<3> | A<4> | A<1> | A<2> | $OpTx$FX_DC$6 | $OpTx$FX_DC$28
|
|
INPUTMC | 4 | 13 | 17 | 15 | 16 | 15 | 15 | 0 | 6
|
|
INPUTP | 9 | 263 | 152 | 158 | 98 | 91 | 99 | 97 | 107 | 101
|
|
EQ | 4 |
|
|
IDE_BASEADR_0__or0001/IDE_BASEADR_0__or0001_D2 = !RESET
|
|
# !AS & !RW & SHUT_UP<2> & autoconfig & A<6> &
|
|
!A<5> & A<3> & !A<4> & !A<1> & !A<2> & !$OpTx$FX_DC$6 &
|
|
$OpTx$FX_DC$28;
|
|
|
|
MACROCELL | 0 | 6 | $OpTx$FX_DC$28
|
|
ATTRIBUTES | 133888 | 0
|
|
OUTPUTMC | 2 | 13 | 16 | 2 | 17
|
|
INPUTS | 2 | AUTO_CONFIG_DONE<1> | AUTO_CONFIG_DONE<0>
|
|
INPUTMC | 2 | 6 | 17 | 0 | 17
|
|
EQ | 1 |
|
|
$OpTx$FX_DC$28 = AUTO_CONFIG_DONE<1> & !AUTO_CONFIG_DONE<0>;
|
|
|
|
MACROCELL | 3 | 10 | $OpTx$FX_DC$33
|
|
ATTRIBUTES | 133888 | 0
|
|
OUTPUTMC | 1 | 2 | 16
|
|
INPUTS | 2 | A<1> | A<2>
|
|
INPUTP | 2 | 107 | 101
|
|
EQ | 1 |
|
|
$OpTx$FX_DC$33 = !A<1> & A<2>;
|
|
|
|
MACROCELL | 3 | 12 | $OpTx$FX_DC$19
|
|
ATTRIBUTES | 133888 | 0
|
|
OUTPUTMC | 2 | 2 | 16 | 3 | 14
|
|
INPUTS | 5 | RESET | A<6> | A<5> | A<4> | A<2>
|
|
INPUTP | 5 | 263 | 98 | 91 | 97 | 101
|
|
EQ | 3 |
|
|
$OpTx$FX_DC$19 = RESET & !A<6> & !A<5>
|
|
# RESET & !A<6> & !A<4> & A<2>
|
|
# RESET & !A<5> & !A<4> & !A<2>;
|
|
|
|
MACROCELL | 3 | 14 | $OpTx$FX_DC$36
|
|
ATTRIBUTES | 133888 | 0
|
|
OUTPUTMC | 2 | 3 | 17 | 3 | 15
|
|
INPUTS | 8 | AUTO_CONFIG_DONE_CYCLE_0__or0000/AUTO_CONFIG_DONE_CYCLE_0__or0000_D2 | $OpTx$FX_DC$19 | A<5> | A<1> | A<3> | A<4> | A<2> | AUTO_CONFIG_DONE<1>
|
|
INPUTMC | 3 | 11 | 17 | 3 | 12 | 6 | 17
|
|
INPUTP | 5 | 91 | 107 | 99 | 97 | 101
|
|
EXPORTS | 1 | 3 | 15
|
|
EQ | 10 |
|
|
$OpTx$FX_DC$36 =
|
|
AUTO_CONFIG_DONE_CYCLE_0__or0000/AUTO_CONFIG_DONE_CYCLE_0__or0000_D2 & !$OpTx$FX_DC$19
|
|
# A<5> & A<1> &
|
|
AUTO_CONFIG_DONE_CYCLE_0__or0000/AUTO_CONFIG_DONE_CYCLE_0__or0000_D2
|
|
# A<3> & !A<4> &
|
|
AUTO_CONFIG_DONE_CYCLE_0__or0000/AUTO_CONFIG_DONE_CYCLE_0__or0000_D2
|
|
# A<3> & A<1> & !A<2> &
|
|
AUTO_CONFIG_DONE_CYCLE_0__or0000/AUTO_CONFIG_DONE_CYCLE_0__or0000_D2;
|
|
$OpTx$FX_DC$36.EXP = AUTO_CONFIG_DONE<1> & !A<5> & !A<4> & A<2> &
|
|
AUTO_CONFIG_DONE_CYCLE_0__or0000/AUTO_CONFIG_DONE_CYCLE_0__or0000_D2
|
|
|
|
MACROCELL | 2 | 15 | EXP18_
|
|
ATTRIBUTES | 2048 | 0
|
|
OUTPUTMC | 1 | 2 | 16
|
|
INPUTS | 4 | A<5> | A<3> | A<4> | AUTO_CONFIG_DONE_CYCLE_0__or0000/AUTO_CONFIG_DONE_CYCLE_0__or0000_D2
|
|
INPUTMC | 1 | 11 | 17
|
|
INPUTP | 3 | 91 | 99 | 97
|
|
EXPORTS | 1 | 2 | 16
|
|
EQ | 2 |
|
|
EXP18_.EXP = !A<5> & A<3> & !A<4> &
|
|
AUTO_CONFIG_DONE_CYCLE_0__or0000/AUTO_CONFIG_DONE_CYCLE_0__or0000_D2
|
|
|
|
MACROCELL | 2 | 17 | EXP19_
|
|
ATTRIBUTES | 2048 | 0
|
|
OUTPUTMC | 1 | 2 | 16
|
|
INPUTS | 11 | A<3> | A<4> | AUTO_CONFIG_DONE_CYCLE_0__or0000/AUTO_CONFIG_DONE_CYCLE_0__or0000_D2 | $OpTx$FX_DC$28 | AUTO_CONFIG_DONE<1> | A<5> | A<2> | A<6> | A<1> | AUTOBOOT_OFF | AUTO_CONFIG_DONE<0>
|
|
INPUTMC | 4 | 11 | 17 | 0 | 6 | 6 | 17 | 0 | 17
|
|
INPUTP | 7 | 99 | 97 | 91 | 101 | 98 | 107 | 142
|
|
EXPORTS | 1 | 2 | 16
|
|
EQ | 12 |
|
|
EXP19_.EXP = A<3> & !A<4> &
|
|
AUTO_CONFIG_DONE_CYCLE_0__or0000/AUTO_CONFIG_DONE_CYCLE_0__or0000_D2 & !$OpTx$FX_DC$28
|
|
# AUTO_CONFIG_DONE<1> & !A<5> & !A<3> & A<2> &
|
|
AUTO_CONFIG_DONE_CYCLE_0__or0000/AUTO_CONFIG_DONE_CYCLE_0__or0000_D2
|
|
# !A<6> & !A<3> & A<1> & !A<2> &
|
|
AUTO_CONFIG_DONE_CYCLE_0__or0000/AUTO_CONFIG_DONE_CYCLE_0__or0000_D2
|
|
# AUTO_CONFIG_DONE<1> & !A<6> & !A<3> & !A<2> &
|
|
!AUTOBOOT_OFF &
|
|
AUTO_CONFIG_DONE_CYCLE_0__or0000/AUTO_CONFIG_DONE_CYCLE_0__or0000_D2
|
|
# AUTO_CONFIG_DONE<0> & !A<6> & !A<5> & !A<3> &
|
|
A<1> &
|
|
AUTO_CONFIG_DONE_CYCLE_0__or0000/AUTO_CONFIG_DONE_CYCLE_0__or0000_D2
|
|
|
|
MACROCELL | 3 | 16 | EXP20_
|
|
ATTRIBUTES | 2048 | 0
|
|
OUTPUTMC | 1 | 3 | 17
|
|
INPUTS | 8 | AUTO_CONFIG_DONE<1> | A<3> | A<4> | A<1> | AUTO_CONFIG_DONE_CYCLE_0__or0000/AUTO_CONFIG_DONE_CYCLE_0__or0000_D2 | A<2> | A<5> | AUTO_CONFIG_DONE<0>
|
|
INPUTMC | 3 | 6 | 17 | 11 | 17 | 0 | 17
|
|
INPUTP | 5 | 99 | 97 | 107 | 101 | 91
|
|
EXPORTS | 1 | 3 | 17
|
|
EQ | 12 |
|
|
EXP20_.EXP = AUTO_CONFIG_DONE<1> & !A<3> & A<4> & A<1> &
|
|
AUTO_CONFIG_DONE_CYCLE_0__or0000/AUTO_CONFIG_DONE_CYCLE_0__or0000_D2
|
|
# !AUTO_CONFIG_DONE<1> & !A<3> & A<4> & A<2> &
|
|
AUTO_CONFIG_DONE_CYCLE_0__or0000/AUTO_CONFIG_DONE_CYCLE_0__or0000_D2
|
|
# !A<3> & A<4> & !A<1> & !A<2> &
|
|
AUTO_CONFIG_DONE_CYCLE_0__or0000/AUTO_CONFIG_DONE_CYCLE_0__or0000_D2
|
|
# AUTO_CONFIG_DONE<1> & !A<5> & !A<4> & !A<1> &
|
|
A<2> &
|
|
AUTO_CONFIG_DONE_CYCLE_0__or0000/AUTO_CONFIG_DONE_CYCLE_0__or0000_D2
|
|
# !AUTO_CONFIG_DONE<1> & AUTO_CONFIG_DONE<0> & !A<4> &
|
|
A<1> & A<2> &
|
|
AUTO_CONFIG_DONE_CYCLE_0__or0000/AUTO_CONFIG_DONE_CYCLE_0__or0000_D2
|
|
|
|
MACROCELL | 4 | 0 | EXP21_
|
|
ATTRIBUTES | 2048 | 0
|
|
OUTPUTMC | 1 | 4 | 1
|
|
INPUTS | 6 | CP_BASEADR<3> | A<19> | CP_BASEADR<5> | A<21> | CP_BASEADR<6> | A<22>
|
|
INPUTMC | 3 | 9 | 12 | 5 | 17 | 5 | 16
|
|
INPUTP | 3 | 169 | 163 | 162
|
|
EXPORTS | 1 | 4 | 1
|
|
EQ | 5 |
|
|
EXP21_.EXP = CP_BASEADR<3> & !A<19>
|
|
# !CP_BASEADR<3> & A<19>
|
|
# CP_BASEADR<5> & !A<21>
|
|
# !CP_BASEADR<5> & A<21>
|
|
# CP_BASEADR<6> & !A<22>
|
|
|
|
MACROCELL | 4 | 2 | EXP22_
|
|
ATTRIBUTES | 2048 | 0
|
|
OUTPUTMC | 1 | 4 | 1
|
|
INPUTS | 7 | CP_BASEADR<0> | A<16> | CP_BASEADR<6> | A<22> | CP_BASEADR<7> | A<23> | EXP23_.EXP
|
|
INPUTMC | 4 | 9 | 17 | 5 | 16 | 5 | 15 | 4 | 3
|
|
INPUTP | 3 | 175 | 162 | 161
|
|
EXPORTS | 1 | 4 | 1
|
|
IMPORTS | 1 | 4 | 3
|
|
EQ | 10 |
|
|
EXP22_.EXP = CP_BASEADR<0> & !A<16>
|
|
# !CP_BASEADR<0> & A<16>
|
|
# !CP_BASEADR<6> & A<22>
|
|
# CP_BASEADR<7> & !A<23>
|
|
# !CP_BASEADR<7> & A<23>
|
|
;Imported pterms FB5_4
|
|
# CP_BASEADR<1> & !A<17>
|
|
# !CP_BASEADR<1> & A<17>
|
|
# CP_BASEADR<2> & !A<18>
|
|
# !CP_BASEADR<2> & A<18>
|
|
|
|
MACROCELL | 4 | 3 | EXP23_
|
|
ATTRIBUTES | 2048 | 0
|
|
OUTPUTMC | 1 | 4 | 2
|
|
INPUTS | 4 | CP_BASEADR<1> | A<17> | CP_BASEADR<2> | A<18>
|
|
INPUTMC | 2 | 9 | 15 | 9 | 14
|
|
INPUTP | 2 | 172 | 171
|
|
EXPORTS | 1 | 4 | 2
|
|
EQ | 4 |
|
|
EXP23_.EXP = CP_BASEADR<1> & !A<17>
|
|
# !CP_BASEADR<1> & A<17>
|
|
# CP_BASEADR<2> & !A<18>
|
|
# !CP_BASEADR<2> & A<18>
|
|
|
|
MACROCELL | 7 | 5 | EXP24_
|
|
ATTRIBUTES | 2048 | 0
|
|
OUTPUTMC | 1 | 7 | 6
|
|
INPUTS | 2 | LAN_BASEADR<1> | A<17>
|
|
INPUTMC | 1 | 12 | 12
|
|
INPUTP | 1 | 172
|
|
EXPORTS | 1 | 7 | 6
|
|
EQ | 2 |
|
|
EXP24_.EXP = LAN_BASEADR<1> & !A<17>
|
|
# !LAN_BASEADR<1> & A<17>
|
|
|
|
MACROCELL | 7 | 6 | EXP25_
|
|
ATTRIBUTES | 2048 | 0
|
|
OUTPUTMC | 1 | 7 | 7
|
|
INPUTS | 7 | LAN_BASEADR<3> | A<19> | LAN_BASEADR<5> | A<21> | LAN_BASEADR<7> | A<23> | EXP24_.EXP
|
|
INPUTMC | 4 | 12 | 10 | 14 | 15 | 14 | 13 | 7 | 5
|
|
INPUTP | 3 | 169 | 163 | 161
|
|
EXPORTS | 1 | 7 | 7
|
|
IMPORTS | 1 | 7 | 5
|
|
EQ | 8 |
|
|
EXP25_.EXP = LAN_BASEADR<3> & !A<19>
|
|
# !LAN_BASEADR<3> & A<19>
|
|
# LAN_BASEADR<5> & !A<21>
|
|
# !LAN_BASEADR<5> & A<21>
|
|
# LAN_BASEADR<7> & !A<23>
|
|
;Imported pterms FB8_6
|
|
# LAN_BASEADR<1> & !A<17>
|
|
# !LAN_BASEADR<1> & A<17>
|
|
|
|
MACROCELL | 7 | 8 | EXP26_
|
|
ATTRIBUTES | 2048 | 0
|
|
OUTPUTMC | 1 | 7 | 7
|
|
INPUTS | 7 | LAN_BASEADR<0> | A<16> | LAN_BASEADR<6> | A<22> | LAN_BASEADR<7> | A<23> | LAN_RD_OBUF.EXP
|
|
INPUTMC | 4 | 14 | 16 | 14 | 14 | 14 | 13 | 7 | 9
|
|
INPUTP | 3 | 175 | 162 | 161
|
|
EXPORTS | 1 | 7 | 7
|
|
IMPORTS | 1 | 7 | 9
|
|
EQ | 8 |
|
|
EXP26_.EXP = LAN_BASEADR<0> & !A<16>
|
|
# !LAN_BASEADR<0> & A<16>
|
|
# LAN_BASEADR<6> & !A<22>
|
|
# !LAN_BASEADR<6> & A<22>
|
|
# !LAN_BASEADR<7> & A<23>
|
|
;Imported pterms FB8_10
|
|
# LAN_BASEADR<2> & !A<18>
|
|
# !LAN_BASEADR<2> & A<18>
|
|
|
|
MACROCELL | 8 | 14 | EXP27_
|
|
ATTRIBUTES | 2048 | 0
|
|
OUTPUTMC | 1 | 8 | 15
|
|
INPUTS | 4 | IDE_BASEADR<1> | A<17> | IDE_BASEADR<2> | A<18>
|
|
INPUTMC | 2 | 12 | 17 | 12 | 16
|
|
INPUTP | 2 | 172 | 171
|
|
EXPORTS | 1 | 8 | 15
|
|
EQ | 4 |
|
|
EXP27_.EXP = IDE_BASEADR<1> & !A<17>
|
|
# !IDE_BASEADR<1> & A<17>
|
|
# IDE_BASEADR<2> & !A<18>
|
|
# !IDE_BASEADR<2> & A<18>
|
|
|
|
MACROCELL | 8 | 15 | EXP28_
|
|
ATTRIBUTES | 2048 | 0
|
|
OUTPUTMC | 1 | 8 | 16
|
|
INPUTS | 7 | IDE_BASEADR<3> | A<19> | IDE_BASEADR<5> | A<21> | IDE_BASEADR<6> | A<22> | EXP27_.EXP
|
|
INPUTMC | 4 | 12 | 15 | 5 | 14 | 5 | 12 | 8 | 14
|
|
INPUTP | 3 | 169 | 163 | 162
|
|
EXPORTS | 1 | 8 | 16
|
|
IMPORTS | 1 | 8 | 14
|
|
EQ | 10 |
|
|
EXP28_.EXP = IDE_BASEADR<3> & !A<19>
|
|
# !IDE_BASEADR<3> & A<19>
|
|
# IDE_BASEADR<5> & !A<21>
|
|
# !IDE_BASEADR<5> & A<21>
|
|
# IDE_BASEADR<6> & !A<22>
|
|
;Imported pterms FB9_15
|
|
# IDE_BASEADR<1> & !A<17>
|
|
# !IDE_BASEADR<1> & A<17>
|
|
# IDE_BASEADR<2> & !A<18>
|
|
# !IDE_BASEADR<2> & A<18>
|
|
|
|
MACROCELL | 8 | 17 | EXP29_
|
|
ATTRIBUTES | 2048 | 0
|
|
OUTPUTMC | 1 | 8 | 16
|
|
INPUTS | 6 | IDE_BASEADR<0> | A<16> | IDE_BASEADR<6> | A<22> | IDE_BASEADR<7> | A<23>
|
|
INPUTMC | 3 | 15 | 17 | 5 | 12 | 14 | 17
|
|
INPUTP | 3 | 175 | 162 | 161
|
|
EXPORTS | 1 | 8 | 16
|
|
EQ | 5 |
|
|
EXP29_.EXP = IDE_BASEADR<0> & !A<16>
|
|
# !IDE_BASEADR<0> & A<16>
|
|
# !IDE_BASEADR<6> & A<22>
|
|
# IDE_BASEADR<7> & !A<23>
|
|
# !IDE_BASEADR<7> & A<23>
|
|
|
|
PIN | AS | 64 | 0 | N/A | 152 | 21 | 6 | 17 | 0 | 17 | 0 | 15 | 0 | 12 | 0 | 10 | 0 | 8 | 12 | 1 | 10 | 16 | 0 | 16 | 2 | 1 | 4 | 4 | 7 | 9 | 7 | 4 | 12 | 13 | 13 | 2 | 14 | 11 | 13 | 13 | 11 | 17 | 11 | 15 | 11 | 16 | 13 | 16
|
|
PIN | RW | 64 | 0 | N/A | 158 | 32 | 0 | 15 | 9 | 2 | 9 | 16 | 11 | 9 | 7 | 1 | 11 | 7 | 7 | 2 | 11 | 4 | 9 | 1 | 10 | 11 | 9 | 4 | 9 | 9 | 4 | 7 | 9 | 11 | 9 | 10 | 9 | 13 | 11 | 11 | 1 | 15 | 1 | 12 | 0 | 12 | 0 | 10 | 1 | 6 | 1 | 3 | 1 | 0 | 0 | 8 | 1 | 10 | 1 | 17 | 1 | 8 | 10 | 17 | 11 | 15 | 11 | 16 | 13 | 16
|
|
PIN | RESET | 64 | 0 | N/A | 263 | 49 | 6 | 17 | 0 | 17 | 6 | 16 | 6 | 15 | 14 | 12 | 14 | 10 | 13 | 17 | 0 | 15 | 9 | 17 | 9 | 15 | 9 | 14 | 9 | 12 | 6 | 14 | 5 | 17 | 5 | 16 | 5 | 15 | 3 | 0 | 15 | 17 | 12 | 17 | 12 | 16 | 12 | 15 | 12 | 14 | 5 | 14 | 5 | 12 | 14 | 17 | 14 | 16 | 12 | 12 | 12 | 11 | 12 | 10 | 12 | 9 | 14 | 15 | 14 | 14 | 14 | 13 | 1 | 15 | 1 | 12 | 0 | 12 | 0 | 10 | 1 | 6 | 1 | 3 | 1 | 0 | 0 | 8 | 5 | 11 | 11 | 17 | 11 | 15 | 11 | 16 | 13 | 16 | 3 | 12 | 3 | 1 | 3 | 17
|
|
PIN | A<20> | 64 | 0 | N/A | 167 | 4 | 7 | 7 | 8 | 16 | 15 | 16 | 4 | 1
|
|
PIN | A<21> | 64 | 0 | N/A | 163 | 4 | 7 | 6 | 8 | 15 | 15 | 16 | 4 | 0
|
|
PIN | A<19> | 64 | 0 | N/A | 169 | 4 | 7 | 6 | 8 | 15 | 15 | 16 | 4 | 0
|
|
PIN | A<23> | 64 | 0 | N/A | 161 | 5 | 7 | 6 | 7 | 8 | 15 | 16 | 4 | 2 | 8 | 17
|
|
PIN | A<22> | 64 | 0 | N/A | 162 | 6 | 4 | 2 | 8 | 15 | 15 | 16 | 4 | 0 | 7 | 8 | 8 | 17
|
|
PIN | A<16> | 64 | 0 | N/A | 175 | 4 | 4 | 2 | 7 | 8 | 15 | 16 | 8 | 17
|
|
PIN | A<17> | 64 | 0 | N/A | 172 | 4 | 7 | 5 | 8 | 14 | 15 | 16 | 4 | 3
|
|
PIN | A<18> | 64 | 0 | N/A | 171 | 4 | 4 | 3 | 8 | 14 | 15 | 16 | 7 | 9
|
|
PIN | CFIN | 64 | 0 | N/A | 190 | 1 | 15 | 16
|
|
PIN | A<3> | 64 | 0 | N/A | 99 | 14 | 2 | 16 | 3 | 16 | 3 | 0 | 3 | 15 | 3 | 11 | 10 | 17 | 11 | 15 | 11 | 16 | 13 | 16 | 3 | 14 | 2 | 15 | 2 | 17 | 3 | 1 | 3 | 17
|
|
PIN | A<4> | 64 | 0 | N/A | 97 | 14 | 2 | 16 | 3 | 16 | 3 | 0 | 3 | 1 | 3 | 7 | 10 | 17 | 11 | 15 | 11 | 16 | 13 | 16 | 3 | 12 | 3 | 14 | 2 | 15 | 2 | 17 | 3 | 17
|
|
PIN | A<5> | 64 | 0 | N/A | 91 | 14 | 2 | 15 | 3 | 16 | 3 | 0 | 3 | 15 | 1 | 1 | 10 | 17 | 11 | 15 | 11 | 16 | 13 | 16 | 3 | 12 | 3 | 14 | 2 | 17 | 3 | 1 | 3 | 17
|
|
PIN | A<2> | 64 | 0 | N/A | 101 | 14 | 3 | 14 | 3 | 16 | 3 | 0 | 3 | 15 | 3 | 4 | 10 | 17 | 11 | 15 | 11 | 16 | 13 | 16 | 3 | 10 | 3 | 12 | 2 | 17 | 3 | 1 | 3 | 17
|
|
PIN | A<1> | 64 | 0 | N/A | 107 | 13 | 3 | 14 | 3 | 16 | 3 | 0 | 3 | 15 | 3 | 5 | 10 | 17 | 11 | 15 | 11 | 16 | 13 | 16 | 3 | 10 | 2 | 17 | 3 | 1 | 3 | 17
|
|
PIN | A<6> | 64 | 0 | N/A | 98 | 11 | 3 | 12 | 3 | 0 | 3 | 15 | 3 | 13 | 10 | 17 | 11 | 15 | 11 | 16 | 13 | 16 | 2 | 17 | 3 | 1 | 3 | 17
|
|
PIN | AUTOBOOT_OFF | 64 | 0 | N/A | 142 | 1 | 2 | 17
|
|
PIN | C3 | 64 | 0 | N/A | 187 | 1 | 10 | 15
|
|
PIN | C1 | 64 | 0 | N/A | 188 | 1 | 10 | 15
|
|
PIN | BERR | 64 | 0 | N/A | 176 | 1 | 5 | 11
|
|
PIN | UDS | 64 | 0 | N/A | 155 | 2 | 1 | 3 | 15 | 15
|
|
PIN | LDS | 64 | 0 | N/A | 157 | 2 | 1 | 0 | 15 | 15
|
|
PIN | IDE_WAIT | 64 | 0 | N/A | 61 | 1 | 14 | 11
|
|
PIN | CP_IRQ | 64 | 0 | N/A | 59 | 1 | 2 | 13
|
|
PIN | A<11> | 64 | 0 | N/A | 114 | 2 | 0 | 13 | 5 | 5
|
|
PIN | A<12> | 64 | 0 | N/A | 115 | 2 | 5 | 7 | 0 | 7
|
|
PIN | A<13> | 64 | 0 | N/A | 123 | 2 | 5 | 4 | 0 | 9
|
|
PIN | A<14> | 64 | 0 | N/A | 125 | 1 | 5 | 2
|
|
PIN | A<7> | 64 | 0 | N/A | 100 | 1 | 1 | 4
|
|
PIN | A<8> | 64 | 0 | N/A | 106 | 1 | 1 | 2
|
|
PIN | A<9> | 64 | 0 | N/A | 108 | 2 | 0 | 11 | 5 | 9
|
|
PIN | A<10> | 64 | 0 | N/A | 112 | 2 | 0 | 14 | 5 | 13
|
|
PIN | LAN_CS | 536871040 | 0 | N/A | 240
|
|
PIN | CP_RD | 536871040 | 0 | N/A | 132
|
|
PIN | CP_WE | 536871040 | 0 | N/A | 131
|
|
PIN | IDE_R | 536871040 | 0 | N/A | 46
|
|
PIN | IDE_W | 536871040 | 0 | N/A | 47
|
|
PIN | ROM_OE | 536871040 | 0 | N/A | 65
|
|
PIN | LAN_RD | 536871040 | 0 | N/A | 242
|
|
PIN | LAN_WRH | 536871040 | 0 | N/A | 237
|
|
PIN | LAN_WRL | 536871040 | 0 | N/A | 145
|
|
PIN | OWN | 536871040 | 0 | N/A | 195
|
|
PIN | OVR | 536871040 | 0 | N/A | 185
|
|
PIN | INT_OUT | 536871040 | 0 | N/A | 60
|
|
PIN | DTACK | 536871040 | 0 | N/A | 160
|
|
PIN | A_LAN<0> | 536871040 | 0 | N/A | 7
|
|
PIN | IDE_A<2> | 536871040 | 0 | N/A | 44
|
|
PIN | A_LAN<10> | 536871040 | 0 | N/A | 255
|
|
PIN | A_LAN<11> | 536871040 | 0 | N/A | 256
|
|
PIN | A_LAN<12> | 536871040 | 0 | N/A | 254
|
|
PIN | A_LAN<13> | 536871040 | 0 | N/A | 253
|
|
PIN | A_LAN<1> | 536871040 | 0 | N/A | 6
|
|
PIN | A_LAN<2> | 536871040 | 0 | N/A | 12
|
|
PIN | A_LAN<3> | 536871040 | 0 | N/A | 8
|
|
PIN | A_LAN<4> | 536871040 | 0 | N/A | 20
|
|
PIN | A_LAN<5> | 536871040 | 0 | N/A | 13
|
|
PIN | A_LAN<6> | 536871040 | 0 | N/A | 22
|
|
PIN | A_LAN<7> | 536871040 | 0 | N/A | 21
|
|
PIN | IDE_A<0> | 536871040 | 0 | N/A | 43
|
|
PIN | A_LAN<8> | 536871040 | 0 | N/A | 258
|
|
PIN | IDE_A<1> | 536871040 | 0 | N/A | 45
|
|
PIN | A_LAN<9> | 536871040 | 0 | N/A | 262
|
|
PIN | CP_CS | 536871040 | 0 | N/A | 63
|
|
PIN | IDE_CS<0> | 536871040 | 0 | N/A | 39
|
|
PIN | IDE_CS<1> | 536871040 | 0 | N/A | 41
|
|
PIN | SLAVE | 536871040 | 0 | N/A | 193
|
|
PIN | LAN_CFG<4> | 536871040 | 0 | N/A | 199
|
|
PIN | LAN_CFG<3> | 536871040 | 0 | N/A | 24
|
|
PIN | LAN_CFG<2> | 536871040 | 0 | N/A | 251
|
|
PIN | LAN_CFG<1> | 536871040 | 0 | N/A | 23
|
|
PIN | CFOUT | 536871040 | 0 | N/A | 191
|
|
PIN | ROM_B<1> | 536871040 | 0 | N/A | 129
|
|
PIN | ROM_B<0> | 536871040 | 0 | N/A | 139
|
|
PIN | D<0> | 536870976 | 0 | N/A | 4 | 1 | 9 | 2
|
|
PIN | D<10> | 536870976 | 0 | N/A | 74 | 4 | 9 | 14 | 12 | 16 | 12 | 11 | 9 | 16
|
|
PIN | D<11> | 536870976 | 0 | N/A | 77 | 4 | 9 | 12 | 12 | 15 | 12 | 10 | 11 | 9
|
|
PIN | D<12> | 536870976 | 0 | N/A | 78 | 4 | 6 | 14 | 12 | 14 | 12 | 9 | 7 | 1
|
|
PIN | D<13> | 536870976 | 0 | N/A | 80 | 4 | 5 | 17 | 5 | 14 | 14 | 15 | 11 | 7
|
|
PIN | D<14> | 536870976 | 0 | N/A | 81 | 4 | 5 | 16 | 5 | 12 | 14 | 14 | 7 | 2
|
|
PIN | D<15> | 536870976 | 0 | N/A | 89 | 4 | 5 | 15 | 14 | 17 | 14 | 13 | 11 | 4
|
|
PIN | D<1> | 536870976 | 0 | N/A | 30 | 1 | 9 | 1
|
|
PIN | D<2> | 536870976 | 0 | N/A | 71 | 1 | 10 | 11
|
|
PIN | D<3> | 536870976 | 0 | N/A | 28 | 1 | 9 | 4
|
|
PIN | D<4> | 536870976 | 0 | N/A | 38 | 1 | 9 | 9
|
|
PIN | D<5> | 536870976 | 0 | N/A | 37 | 1 | 4 | 7
|
|
PIN | D<6> | 536870976 | 0 | N/A | 26 | 1 | 9 | 11
|
|
PIN | D<7> | 536870976 | 0 | N/A | 29 | 1 | 9 | 10
|
|
PIN | D<8> | 536870976 | 0 | N/A | 32 | 4 | 9 | 17 | 15 | 17 | 14 | 16 | 9 | 13
|
|
PIN | D<9> | 536870976 | 0 | N/A | 73 | 4 | 9 | 15 | 12 | 17 | 12 | 12 | 11 | 11
|
|
PIN | DQ<0> | 536870976 | 0 | N/A | 217 | 1 | 3 | 1
|
|
PIN | DQ<10> | 536870976 | 0 | N/A | 234 | 1 | 4 | 13
|
|
PIN | DQ<11> | 536870976 | 0 | N/A | 207 | 1 | 4 | 14
|
|
PIN | DQ<12> | 536870976 | 0 | N/A | 235 | 1 | 4 | 16
|
|
PIN | DQ<13> | 536870976 | 0 | N/A | 204 | 1 | 6 | 2
|
|
PIN | DQ<14> | 536870976 | 0 | N/A | 236 | 1 | 6 | 4
|
|
PIN | DQ<15> | 536870976 | 0 | N/A | 202 | 1 | 6 | 11
|
|
PIN | DQ<1> | 536870976 | 0 | N/A | 216 | 1 | 1 | 14
|
|
PIN | DQ<2> | 536870976 | 0 | N/A | 127 | 1 | 4 | 9
|
|
PIN | DQ<3> | 536870976 | 0 | N/A | 219 | 1 | 1 | 11
|
|
PIN | DQ<4> | 536870976 | 0 | N/A | 225 | 1 | 0 | 5
|
|
PIN | DQ<5> | 536870976 | 0 | N/A | 69 | 1 | 0 | 4
|
|
PIN | DQ<6> | 536870976 | 0 | N/A | 227 | 1 | 1 | 9
|
|
PIN | DQ<7> | 536870976 | 0 | N/A | 226 | 1 | 1 | 13
|
|
PIN | DQ<8> | 536870976 | 0 | N/A | 231 | 1 | 1 | 16
|
|
PIN | DQ<9> | 536870976 | 0 | N/A | 209 | 1 | 4 | 11
|