603 lines
15 KiB
OpenEdge ABL
603 lines
15 KiB
OpenEdge ABL
; ------------------------------------------------------------------------------
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; | Lowlevel Access to memory mapped ENC624J600 in PSP mode |
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; | Henryk Richter <henryk.richter@gmx.net> |
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; ------------------------------------------------------------------------------
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; register definition section
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; set/clr register offsets
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SET_OFFSET EQU $0100
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CLR_OFFSET EQU $0180
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; Register definitions
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; SPI Bank 0 registers --------
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ETXST EQU $7E00
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ETXSTL EQU $7E00
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ETXSTH EQU $7E01
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ETXLEN EQU $7E02
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ETXLENL EQU $7E02
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ETXLENH EQU $7E03
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ERXST EQU $7E04
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ERXSTL EQU $7E04
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ERXSTH EQU $7E05
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ERXTAIL EQU $7E06
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ERXTAILL EQU $7E06
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ERXTAILH EQU $7E07
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ERXHEAD EQU $7E08
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ERXHEADL EQU $7E08
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ERXHEADH EQU $7E09
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EDMAST EQU $7E0A
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EDMASTL EQU $7E0A
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EDMASTH EQU $7E0B
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EDMALEN EQU $7E0C
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EDMALENL EQU $7E0C
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EDMALENH EQU $7E0D
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EDMADST EQU $7E0E
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EDMADSTL EQU $7E0E
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EDMADSTH EQU $7E0F
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EDMACS EQU $7E10
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EDMACSL EQU $7E10
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EDMACSH EQU $7E11
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ETXSTAT EQU $7E12
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ETXSTATL EQU $7E12
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ETXSTATH EQU $7E13
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ETXWIRE EQU $7E14
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ETXWIREL EQU $7E14
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ETXWIREH EQU $7E15
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; SPI all bank registers
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EUDAST EQU $7E16
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EUDASTL EQU $7E16
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EUDASTH EQU $7E17
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EUDAND EQU $7E18
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EUDANDL EQU $7E18
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EUDANDH EQU $7E19
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ESTAT EQU $7E1A
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ESTATL EQU $7E1A
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ESTATH EQU $7E1B
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EIR EQU $7E1C
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EIRL EQU $7E1C
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EIRH EQU $7E1D
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ECON1 EQU $7E1E
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ECON1L EQU $7E1E
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ECON1H EQU $7E1F
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; SPI Bank 1 registers -----
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EHT1 EQU $7E20
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EHT1L EQU $7E20
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EHT1H EQU $7E21
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EHT2 EQU $7E22
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EHT2L EQU $7E22
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EHT2H EQU $7E23
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EHT3 EQU $7E24
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EHT3L EQU $7E24
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EHT3H EQU $7E25
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EHT4 EQU $7E26
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EHT4L EQU $7E26
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EHT4H EQU $7E27
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EPMM1 EQU $7E28
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EPMM1L EQU $7E28
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EPMM1H EQU $7E29
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EPMM2 EQU $7E2A
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EPMM2L EQU $7E2A
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EPMM2H EQU $7E2B
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EPMM3 EQU $7E2C
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EPMM3L EQU $7E2C
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EPMM3H EQU $7E2D
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EPMM4 EQU $7E2E
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EPMM4L EQU $7E2E
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EPMM4H EQU $7E2F
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EPMCS EQU $7E30
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EPMCSL EQU $7E30
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EPMCSH EQU $7E31
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EPMO EQU $7E32
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EPMOL EQU $7E32
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EPMOH EQU $7E33
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ERXFCON EQU $7E34
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ERXFCONL EQU $7E34
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ERXFCONH EQU $7E35
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; SPI all bank registers from 0x36 to 0x3F
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; SPI Bank 2 registers -----
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MACON1 EQU $7E40
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MACON1L EQU $7E40
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MACON1H EQU $7E41
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MACON2 EQU $7E42
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MACON2L EQU $7E42
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MACON2H EQU $7E43
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MABBIPG EQU $7E44
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MABBIPGL EQU $7E44
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MABBIPGH EQU $7E45
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MAIPG EQU $7E46
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MAIPGL EQU $7E46
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MAIPGH EQU $7E47
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MACLCON EQU $7E48
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MACLCONL EQU $7E48
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MACLCONH EQU $7E49
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MAMXFL EQU $7E4A
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MAMXFLL EQU $7E4A
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MAMXFLH EQU $7E4B
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MICMD EQU $7E52
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MICMDL EQU $7E52
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MICMDH EQU $7E53
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MIREGADR EQU $7E54
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MIREGADRL EQU $7E54
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MIREGADRH EQU $7E55
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; SPI all bank registers from 0x56 to 0x5F
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; SPI Bank 3 registers -----
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MAADR3 EQU $7E60
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MAADR3L EQU $7E60
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MAADR3H EQU $7E61
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MAADR2 EQU $7E62
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MAADR2L EQU $7E62
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MAADR2H EQU $7E63
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MAADR1 EQU $7E64
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MAADR1L EQU $7E64
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MAADR1H EQU $7E65
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MIWR EQU $7E66
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MIWRL EQU $7E66
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MIWRH EQU $7E67
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MIRD EQU $7E68
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MIRDL EQU $7E68
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MIRDH EQU $7E69
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MISTAT EQU $7E6A
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MISTATL EQU $7E6A
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MISTATH EQU $7E6B
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EPAUS EQU $7E6C
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EPAUSL EQU $7E6C
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EPAUSH EQU $7E6D
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ECON2 EQU $7E6E
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ECON2L EQU $7E6E
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ECON2H EQU $7E6F
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ERXWM EQU $7E70
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ERXWML EQU $7E70
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ERXWMH EQU $7E71
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EIE EQU $7E72
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EIEL EQU $7E72
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EIEH EQU $7E73
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EIDLED EQU $7E74
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EIDLEDL EQU $7E74
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EIDLEDH EQU $7E75
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; SPI all bank registers from 0x66 to 0x6F
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; SPI Non-banked Special Function Registers
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EGPDATA EQU $7E80
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EGPDATAL EQU $7E80
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ERXDATA EQU $7E82
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ERXDATAL EQU $7E82
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EUDADATA EQU $7E84
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EUDADATAL EQU $7E84
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EGPRDPT EQU $7E86
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EGPRDPTL EQU $7E86
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EGPRDPTH EQU $7E87
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EGPWRPT EQU $7E88
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EGPWRPTL EQU $7E88
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EGPWRPTH EQU $7E89
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ERXRDPT EQU $7E8A
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ERXRDPTL EQU $7E8A
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ERXRDPTH EQU $7E8B
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ERXWRPT EQU $7E8C
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ERXWRPTL EQU $7E8C
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ERXWRPTH EQU $7E8D
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EUDARDPT EQU $7E8E
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EUDARDPTL EQU $7E8E
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EUDARDPTH EQU $7E8F
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EUDAWRPT EQU $7E90
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EUDAWRPTL EQU $7E90
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EUDAWRPTH EQU $7E91
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;;;;;;;;;;;;;;;;;;;;;;;;;;
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; ENC424J600/624J600 register bits
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;;;;;;;;;;;;;;;;;;;;;;;;;;
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; ESTAT bits ----------
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ESTAT_INT EQU (1<<15)
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ESTAT_FCIDLE EQU (1<<14)
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ESTAT_RXBUSY EQU (1<<13)
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ESTAT_CLKRDY EQU (1<<12)
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ESTAT_RSTDONE EQU (1<<11)
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ESTAT_PHYDPX EQU (1<<10)
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ESTAT_PHYRDY EQU (1<<9)
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ESTAT_PHYLNK EQU (1<<8)
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ESTAT_PKTCNT7 EQU (1<<7)
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ESTAT_PKTCNT6 EQU (1<<6)
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ESTAT_PKTCNT5 EQU (1<<5)
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ESTAT_PKTCNT4 EQU (1<<4)
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ESTAT_PKTCNT3 EQU (1<<3)
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ESTAT_PKTCNT2 EQU (1<<2)
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ESTAT_PKTCNT1 EQU (1<<1)
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ESTAT_PKTCNT0 EQU (1)
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; EIR bits ------------
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EIR_CRYPTEN EQU (1<<15)
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EIR_MODEXIF EQU (1<<14)
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EIR_HASHIF EQU (1<<13)
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EIR_AESIF EQU (1<<12)
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EIR_LINKIF EQU (1<<11)
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EIR_PRDYIF EQU (1<<10)
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EIR_r9 EQU (1<<9)
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EIR_r8 EQU (1<<8)
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EIR_r7 EQU (1<<7)
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EIR_PKTIF EQU (1<<6)
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EIR_DMAIF EQU (1<<5)
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EIR_r4 EQU (1<<4)
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EIR_TXIF EQU (1<<3)
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EIR_TXABTIF EQU (1<<2)
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EIR_RXABTIF EQU (1<<1)
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EIR_PCFULIF EQU (1)
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; ECON1 bits ----------
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ECON1_MODEXST EQU (1<<15)
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ECON1_HASHEN EQU (1<<14)
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ECON1_HASHOP EQU (1<<13)
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ECON1_HASHLST EQU (1<<12)
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ECON1_AESST EQU (1<<11)
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ECON1_AESOP1 EQU (1<<10)
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ECON1_AESOP0 EQU (1<<9)
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ECON1_PKTDEC EQU (1<<8)
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ECON1_FCOP1 EQU (1<<7)
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ECON1_FCOP0 EQU (1<<6)
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ECON1_DMAST EQU (1<<5)
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ECON1_DMACPY EQU (1<<4)
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ECON1_DMACSSD EQU (1<<3)
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ECON1_DMANOCS EQU (1<<2)
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ECON1_TXRTS EQU (1<<1)
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ECON1_RXEN EQU (1)
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; ETXSTAT bits --------
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ETXSTAT_r12 EQU (1<<12)
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ETXSTAT_r11 EQU (1<<11)
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ETXSTAT_LATECOL EQU (1<<10)
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ETXSTAT_MAXCOL EQU (1<<9)
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ETXSTAT_EXDEFER EQU (1<<8)
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ETXSTAT_DEFER EQU (1<<7)
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ETXSTAT_r6 EQU (1<<6)
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ETXSTAT_r5 EQU (1<<5)
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ETXSTAT_CRCBAD EQU (1<<4)
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ETXSTAT_COLCNT3 EQU (1<<3)
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ETXSTAT_COLCNT2 EQU (1<<2)
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ETXSTAT_COLCNT1 EQU (1<<1)
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ETXSTAT_COLCNT0 EQU (1)
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; ERXFCON bits --------
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ERXFCON_HTEN EQU (1<<15)
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ERXFCON_MPEN EQU (1<<14)
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ERXFCON_NOTPM EQU (1<<12)
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ERXFCON_PMEN3 EQU (1<<11)
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ERXFCON_PMEN2 EQU (1<<10)
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ERXFCON_PMEN1 EQU (1<<9)
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ERXFCON_PMEN0 EQU (1<<8)
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ERXFCON_CRCEEN EQU (1<<7)
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ERXFCON_CRCEN EQU (1<<6)
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ERXFCON_RUNTEEN EQU (1<<5)
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ERXFCON_RUNTEN EQU (1<<4)
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ERXFCON_UCEN EQU (1<<3)
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ERXFCON_NOTMEEN EQU (1<<2)
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ERXFCON_MCEN EQU (1<<1)
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ERXFCON_BCEN EQU (1)
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; MACON1 bits ---------
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MACON1_r15 EQU (1<<15)
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MACON1_r14 EQU (1<<14)
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MACON1_r11 EQU (1<<11)
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MACON1_r10 EQU (1<<10)
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MACON1_r9 EQU (1<<9)
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MACON1_r8 EQU (1<<8)
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MACON1_LOOPBK EQU (1<<4)
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MACON1_r3 EQU (1<<3)
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MACON1_RXPAUS EQU (1<<2)
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MACON1_PASSALL EQU (1<<1)
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MACON1_r0 EQU (1)
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; MACON2 bits ---------
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MACON2_DEFER EQU (1<<14)
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MACON2_BPEN EQU (1<<13)
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MACON2_NOBKOFF EQU (1<<12)
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MACON2_r9 EQU (1<<9)
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MACON2_r8 EQU (1<<8)
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MACON2_PADCFG2 EQU (1<<7)
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MACON2_PADCFG1 EQU (1<<6)
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MACON2_PADCFG0 EQU (1<<5)
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MACON2_TXCRCEN EQU (1<<4)
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MACON2_PHDREN EQU (1<<3)
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MACON2_HFRMEN EQU (1<<2)
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MACON2_r1 EQU (1<<1)
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MACON2_FULDPX EQU (1)
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; MABBIPG bits --------
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MABBIPG_BBIPG6 EQU (1<<6)
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MABBIPG_BBIPG5 EQU (1<<5)
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MABBIPG_BBIPG4 EQU (1<<4)
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MABBIPG_BBIPG3 EQU (1<<3)
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MABBIPG_BBIPG2 EQU (1<<2)
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MABBIPG_BBIPG1 EQU (1<<1)
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MABBIPG_BBIPG0 EQU (1)
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; MAIPG bits ----------
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MAIPG_r14 EQU (1<<14)
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MAIPG_r13 EQU (1<<13)
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MAIPG_r12 EQU (1<<12)
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MAIPG_r11 EQU (1<<11)
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MAIPG_r10 EQU (1<<10)
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MAIPG_r9 EQU (1<<9)
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MAIPG_r8 EQU (1<<8)
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MAIPG_IPG6 EQU (1<<6)
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MAIPG_IPG5 EQU (1<<5)
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MAIPG_IPG4 EQU (1<<4)
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MAIPG_IPG3 EQU (1<<3)
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MAIPG_IPG2 EQU (1<<2)
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MAIPG_IPG1 EQU (1<<1)
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MAIPG_IPG0 EQU (1)
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; MACLCON bits --------
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MACLCON_r13 EQU (1<<13)
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MACLCON_r12 EQU (1<<12)
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MACLCON_r11 EQU (1<<11)
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MACLCON_r10 EQU (1<<10)
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MACLCON_r9 EQU (1<<9)
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MACLCON_r8 EQU (1<<8)
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MACLCON_MAXRET3 EQU (1<<3)
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MACLCON_MAXRET2 EQU (1<<2)
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MACLCON_MAXRET1 EQU (1<<1)
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MACLCON_MAXRET0 EQU (1)
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; MICMD bits ----------
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MICMD_MIISCAN EQU (1<<1)
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MICMD_MIIRD EQU (1)
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; MIREGADR bits -------
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MIREGADR_r12 EQU (1<<12)
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MIREGADR_r11 EQU (1<<11)
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MIREGADR_r10 EQU (1<<10)
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MIREGADR_r9 EQU (1<<9)
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MIREGADR_r8 EQU (1<<8)
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MIREGADR_PHREG4 EQU (1<<4)
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MIREGADR_PHREG3 EQU (1<<3)
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MIREGADR_PHREG2 EQU (1<<2)
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MIREGADR_PHREG1 EQU (1<<1)
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MIREGADR_PHREG0 EQU (1)
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; MISTAT bits ---------
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MISTAT_r3 EQU (1<<3)
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MISTAT_NVALID EQU (1<<2)
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MISTAT_SCAN EQU (1<<1)
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MISTAT_BUSY EQU (1)
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; ECON2 bits ----------
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ECON2_ETHEN EQU (1<<15)
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ECON2_STRCH EQU (1<<14)
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ECON2_TXMAC EQU (1<<13)
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ECON2_SHA1MD5 EQU (1<<12)
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ECON2_COCON3 EQU (1<<11)
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ECON2_COCON2 EQU (1<<10)
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ECON2_COCON1 EQU (1<<9)
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ECON2_COCON0 EQU (1<<8)
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ECON2_AUTOFC EQU (1<<7)
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ECON2_TXRST EQU (1<<6)
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ECON2_RXRST EQU (1<<5)
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ECON2_ETHRST EQU (1<<4)
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ECON2_MODLEN1 EQU (1<<3)
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ECON2_MODLEN0 EQU (1<<2)
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ECON2_AESLEN1 EQU (1<<1)
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ECON2_AESLEN0 EQU (1)
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; ERXWM bits ----------
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ERXWM_RXFWM7 EQU (1<<15)
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ERXWM_RXFWM6 EQU (1<<14)
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ERXWM_RXFWM5 EQU (1<<13)
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ERXWM_RXFWM4 EQU (1<<12)
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ERXWM_RXFWM3 EQU (1<<11)
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ERXWM_RXFWM2 EQU (1<<10)
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ERXWM_RXFWM1 EQU (1<<9)
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ERXWM_RXFWM0 EQU (1<<8)
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ERXWM_RXEWM7 EQU (1<<7)
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ERXWM_RXEWM6 EQU (1<<6)
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ERXWM_RXEWM5 EQU (1<<5)
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ERXWM_RXEWM4 EQU (1<<4)
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ERXWM_RXEWM3 EQU (1<<3)
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ERXWM_RXEWM2 EQU (1<<2)
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ERXWM_RXEWM1 EQU (1<<1)
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ERXWM_RXEWM0 EQU (1)
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; EIE bits ------------
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EIE_INTIE EQU (1<<15)
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EIE_MODEXIE EQU (1<<14)
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EIE_HASHIE EQU (1<<13)
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EIE_AESIE EQU (1<<12)
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EIE_LINKIE EQU (1<<11)
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EIE_PRDYIE EQU (1<<10)
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EIE_r9 EQU (1<<9)
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EIE_r8 EQU (1<<8)
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EIE_r7 EQU (1<<7)
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EIE_PKTIE EQU (1<<6)
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EIE_DMAIE EQU (1<<5)
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EIE_r4 EQU (1<<4)
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EIE_TXIE EQU (1<<3)
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EIE_TXABTIE EQU (1<<2)
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EIE_RXABTIE EQU (1<<1)
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EIE_PCFULIE EQU (1)
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; EIDLED bits ---------
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EIDLED_LACFG3 EQU (1<<15)
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EIDLED_LACFG2 EQU (1<<14)
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EIDLED_LACFG1 EQU (1<<13)
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EIDLED_LACFG0 EQU (1<<12)
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EIDLED_LBCFG3 EQU (1<<11)
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EIDLED_LBCFG2 EQU (1<<10)
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EIDLED_LBCFG1 EQU (1<<9)
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EIDLED_LBCFG0 EQU (1<<8)
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EIDLED_DEVID2 EQU (1<<7)
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EIDLED_DEVID1 EQU (1<<6)
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EIDLED_DEVID0 EQU (1<<5)
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EIDLED_REVID4 EQU (1<<4)
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EIDLED_REVID3 EQU (1<<3)
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EIDLED_REVID2 EQU (1<<2)
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EIDLED_REVID1 EQU (1<<1)
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EIDLED_REVID0 EQU (1)
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; PHCON1 bits ---------
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PHCON1_PRST EQU (1<<15)
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PHCON1_PLOOPBK EQU (1<<14)
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PHCON1_SPD100 EQU (1<<13)
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PHCON1_ANEN EQU (1<<12)
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PHCON1_PSLEEP EQU (1<<11)
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PHCON1_r10 EQU (1<<10)
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PHCON1_RENEG EQU (1<<9)
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PHCON1_PFULDPX EQU (1<<8)
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PHCON1_r7 EQU (1<<7)
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PHCON1_r6 EQU (1<<6)
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PHCON1_r5 EQU (1<<5)
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PHCON1_r4 EQU (1<<4)
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PHCON1_r3 EQU (1<<3)
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PHCON1_r2 EQU (1<<2)
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PHCON1_r1 EQU (1<<1)
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PHCON1_r0 EQU (1)
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|
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; PHSTAT1 bits --------
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PHSTAT1_r15 EQU (1<<15)
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PHSTAT1_FULL100 EQU (1<<14)
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PHSTAT1_HALF100 EQU (1<<13)
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PHSTAT1_FULL10 EQU (1<<12)
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PHSTAT1_HALF10 EQU (1<<11)
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PHSTAT1_r10 EQU (1<<10)
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PHSTAT1_r9 EQU (1<<9)
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PHSTAT1_r8 EQU (1<<8)
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PHSTAT1_r7 EQU (1<<7)
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PHSTAT1_r6 EQU (1<<6)
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PHSTAT1_ANDONE EQU (1<<5)
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PHSTAT1_LRFAULT EQU (1<<4)
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PHSTAT1_ANABLE EQU (1<<3)
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PHSTAT1_LLSTAT EQU (1<<2)
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PHSTAT1_r1 EQU (1<<1)
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PHSTAT1_EXTREGS EQU (1)
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|
|
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; PHANA bits ----------
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PHANA_ADNP EQU (1<<15)
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PHANA_r14 EQU (1<<14)
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PHANA_ADFAULT EQU (1<<13)
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PHANA_r12 EQU (1<<12)
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PHANA_ADPAUS1 EQU (1<<11)
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PHANA_ADPAUS0 EQU (1<<10)
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PHANA_r9 EQU (1<<9)
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PHANA_AD100FD EQU (1<<8)
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PHANA_AD100 EQU (1<<7)
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PHANA_AD10FD EQU (1<<6)
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PHANA_AD10 EQU (1<<5)
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PHANA_ADIEEE4 EQU (1<<4)
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PHANA_ADIEEE3 EQU (1<<3)
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PHANA_ADIEEE2 EQU (1<<2)
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PHANA_ADIEEE1 EQU (1<<1)
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PHANA_ADIEEE0 EQU (1)
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|
|
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; PHANLPA bits --------
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PHANLPA_LPNP EQU (1<<15)
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PHANLPA_LPACK EQU (1<<14)
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PHANLPA_LPFAULT EQU (1<<13)
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PHANLPA_r12 EQU (1<<12)
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PHANLPA_LPPAUS1 EQU (1<<11)
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PHANLPA_LPPAUS0 EQU (1<<10)
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PHANLPA_LP100T4 EQU (1<<9)
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PHANLPA_LP100FD EQU (1<<8)
|
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PHANLPA_LP100 EQU (1<<7)
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PHANLPA_LP10FD EQU (1<<6)
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PHANLPA_LP10 EQU (1<<5)
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PHANLPA_LPIEEE4 EQU (1<<4)
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PHANLPA_LPIEEE3 EQU (1<<3)
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PHANLPA_LPIEEE2 EQU (1<<2)
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PHANLPA_LPIEEE1 EQU (1<<1)
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PHANLPA_LPIEEE0 EQU (1)
|
|
|
|
; PHANE bits ----------
|
|
PHANE_r15 EQU (1<<15)
|
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PHANE_r14 EQU (1<<14)
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PHANE_r13 EQU (1<<13)
|
|
PHANE_r12 EQU (1<<12)
|
|
PHANE_r11 EQU (1<<11)
|
|
PHANE_r10 EQU (1<<10)
|
|
PHANE_r9 EQU (1<<9)
|
|
PHANE_r8 EQU (1<<8)
|
|
PHANE_r7 EQU (1<<7)
|
|
PHANE_r6 EQU (1<<6)
|
|
PHANE_r5 EQU (1<<5)
|
|
PHANE_PDFLT EQU (1<<4)
|
|
PHANE_r3 EQU (1<<3)
|
|
PHANE_r2 EQU (1<<2)
|
|
PHANE_LPARCD EQU (1<<1)
|
|
PHANA_LPANABL EQU (1)
|
|
|
|
; PHCON2 bits ---------
|
|
PHCON2_r15 EQU (1<<15)
|
|
PHCON2_r14 EQU (1<<14)
|
|
PHCON2_EDPWRDN EQU (1<<13)
|
|
PHCON2_r12 EQU (1<<12)
|
|
PHCON2_EDTHRES EQU (1<<11)
|
|
PHCON2_r10 EQU (1<<10)
|
|
PHCON2_r9 EQU (1<<9)
|
|
PHCON2_r8 EQU (1<<8)
|
|
PHCON2_r7 EQU (1<<7)
|
|
PHCON2_r6 EQU (1<<6)
|
|
PHCON2_r5 EQU (1<<5)
|
|
PHCON2_r4 EQU (1<<4)
|
|
PHCON2_r3 EQU (1<<3)
|
|
PHCON2_FRCLNK EQU (1<<2)
|
|
PHCON2_EDSTAT EQU (1<<1)
|
|
PHCON2_r0 EQU (1)
|
|
|
|
; PHSTAT2 bits ---------
|
|
PHSTAT2_r15 EQU (1<<15)
|
|
PHSTAT2_r14 EQU (1<<14)
|
|
PHSTAT2_r13 EQU (1<<13)
|
|
PHSTAT2_r12 EQU (1<<12)
|
|
PHSTAT2_r11 EQU (1<<11)
|
|
PHSTAT2_r10 EQU (1<<10)
|
|
PHSTAT2_r9 EQU (1<<9)
|
|
PHSTAT2_r8 EQU (1<<8)
|
|
PHSTAT2_r7 EQU (1<<7)
|
|
PHSTAT2_r6 EQU (1<<6)
|
|
PHSTAT2_r5 EQU (1<<5)
|
|
PHSTAT2_PLRITY EQU (1<<4)
|
|
PHSTAT2_r3 EQU (1<<3)
|
|
PHSTAT2_r2 EQU (1<<2)
|
|
PHSTAT2_r1 EQU (1<<1)
|
|
PHSTAT2_r0 EQU (1)
|
|
|
|
; PHSTAT3 bits --------
|
|
PHSTAT3_r15 EQU (1<<15)
|
|
PHSTAT3_r14 EQU (1<<14)
|
|
PHSTAT3_r13 EQU (1<<13)
|
|
PHSTAT3_r12 EQU (1<<12)
|
|
PHSTAT3_r11 EQU (1<<11)
|
|
PHSTAT3_r10 EQU (1<<10)
|
|
PHSTAT3_r9 EQU (1<<9)
|
|
PHSTAT3_r8 EQU (1<<8)
|
|
PHSTAT3_r7 EQU (1<<7)
|
|
PHSTAT3_r6 EQU (1<<6)
|
|
PHSTAT3_r5 EQU (1<<5)
|
|
PHSTAT3_SPDDPX2 EQU (1<<4)
|
|
PHSTAT3_SPDDPX1 EQU (1<<3)
|
|
PHSTAT3_SPDDPX0 EQU (1<<2)
|
|
PHSTAT3_r1 EQU (1<<1)
|
|
PHSTAT3_r0 EQU (1)
|
|
|
|
;------------------------------ internal defaults ----------------------------------
|
|
;33.333Mhz clock out frequency
|
|
CLOCK_33_CLR EQU (ECON2_COCON3|ECON2_COCON2|ECON2_COCON1) ;clr mask
|
|
CLOCK_33_SET EQU (ECON2_COCON0) ;set mask
|
|
;25 MHz
|
|
CLOCK_25_CLR EQU (ECON2_COCON3|ECON2_COCON2|ECON2_COCON0) ;clr mask
|
|
CLOCK_25_SET EQU (ECON2_COCON1) ;set mask
|
|
;20 MHz
|
|
CLOCK_20_CLR EQU (ECON2_COCON3|ECON2_COCON2) ;clr mask
|
|
CLOCK_20_SET EQU (ECON2_COCON1|ECON2_COCON0) ;set mask
|
|
;16 MHz
|
|
CLOCK_16_CLR EQU (ECON2_COCON3|ECON2_COCON0|ECON2_COCON1) ;clr mask
|
|
CLOCK_16_SET EQU (ECON2_COCON2) ;set mask
|
|
;4 MHz (after reset)
|
|
CLOCK_4_CLR EQU (ECON2_COCON2) ;clr mask
|
|
CLOCK_4_SET EQU (ECON2_COCON3|ECON2_COCON0|ECON2_COCON1) ;set mask
|
|
|
|
CLOCK_DEF_CLR EQU CLOCK_33_CLR
|
|
CLOCK_DEF_SET EQU CLOCK_33_SET
|