34 lines
2.6 KiB
XML
34 lines
2.6 KiB
XML
<?xml version="1.0" encoding="UTF-8"?>
|
|
<!-- IMPORTANT: This is an internal file that has been generated
|
|
by the Xilinx ISE software. Any direct editing or
|
|
changes made to this file may result in unpredictable
|
|
behavior or data corruption. It is strongly advised that
|
|
users do not edit the contents of this file. -->
|
|
<messages>
|
|
<msg type="warning" file="Cpld" num="0" delta="new" >Unable to retrieve the path to the iSE Project Repository. Will use the default filename of '<arg fmt="%s" index="1">LAN_IDE_CP.ise</arg>'.
|
|
</msg>
|
|
|
|
<msg type="info" file="Cpld" num="0" delta="new" >Inferring BUFG constraint for signal '<arg fmt="%s" index="1">CLK_EXT</arg>' based upon the LOC constraint '<arg fmt="%s" index="2">P30</arg>'. It is recommended that you declare this BUFG explicitedly in your design. Note that for certain device families the output of a BUFG constraint can not drive a gated clock, and the BUFG constraint will be ignored.
|
|
</msg>
|
|
|
|
<msg type="warning" file="Cpld" num="1007" delta="old" >Removing unused input(s) '<arg fmt="%s" index="1">BERR</arg>'. The input(s) are unused after optimization. Please verify functionality via simulation.
|
|
</msg>
|
|
|
|
<msg type="warning" file="Cpld" num="1007" delta="old" >Removing unused input(s) '<arg fmt="%s" index="1">IDE_WAIT</arg>'. The input(s) are unused after optimization. Please verify functionality via simulation.
|
|
</msg>
|
|
|
|
<msg type="warning" file="Cpld" num="1007" delta="old" >Removing unused input(s) '<arg fmt="%s" index="1">MTCR</arg>'. The input(s) are unused after optimization. Please verify functionality via simulation.
|
|
</msg>
|
|
|
|
<msg type="warning" file="Cpld" num="896" delta="old" >Unable to map all desired signals into function block, FB<arg fmt="%d" index="1">5</arg>, because too many function block product terms are required. Buffering output signal <arg fmt="%s" index="2">CP_CS</arg> to allow all signals assigned to this function block to be placed.
|
|
</msg>
|
|
|
|
<msg type="error" file="Cpld" num="886" delta="old" >Function block <arg fmt="%s" index="1">FB1</arg> was too congested to route successfully. This occurs due to excessive (>= 50) product term input fanins to this function block. Consider moving output signals in this function block to less congested function blocks, buffering output signals that must remain in this function block, or selecting a larger package.
|
|
</msg>
|
|
|
|
<msg type="error" file="Cpld" num="868" delta="old" >Cannot fit the design into any of the specified devices with the selected implementation options.
|
|
</msg>
|
|
|
|
</messages>
|
|
|