449 lines
26 KiB
Plaintext
449 lines
26 KiB
Plaintext
Release 14.7 - xst P.20131013 (nt64)
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Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
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--> Parameter TMPDIR set to xst/projnav.tmp
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Total REAL time to Xst completion: 0.00 secs
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Total CPU time to Xst completion: 0.13 secs
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--> Parameter xsthdpdir set to xst
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Total REAL time to Xst completion: 0.00 secs
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Total CPU time to Xst completion: 0.13 secs
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--> Reading design: LAN_IDE_CP.prj
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TABLE OF CONTENTS
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1) Synthesis Options Summary
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2) HDL Compilation
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3) Design Hierarchy Analysis
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4) HDL Analysis
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5) HDL Synthesis
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5.1) HDL Synthesis Report
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6) Advanced HDL Synthesis
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6.1) Advanced HDL Synthesis Report
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7) Low Level Synthesis
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8) Partition Report
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9) Final Report
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=========================================================================
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* Synthesis Options Summary *
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=========================================================================
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---- Source Parameters
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Input File Name : "LAN_IDE_CP.prj"
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Input Format : mixed
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Ignore Synthesis Constraint File : NO
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---- Target Parameters
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Output File Name : "LAN_IDE_CP"
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Output Format : NGC
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Target Device : XC9500XL CPLDs
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---- Source Options
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Top Module Name : LAN_IDE_CP
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Automatic FSM Extraction : YES
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FSM Encoding Algorithm : Johnson
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Safe Implementation : No
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CASE Implementation Style : Full
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Mux Extraction : Yes
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Resource Sharing : YES
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---- Target Options
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Add IO Buffers : YES
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MACRO Preserve : YES
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XOR Preserve : YES
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Equivalent register Removal : YES
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---- General Options
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Optimization Goal : Speed
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Optimization Effort : 2
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Keep Hierarchy : Yes
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Netlist Hierarchy : As_Optimized
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RTL Output : Yes
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Hierarchy Separator : /
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Bus Delimiter : <>
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Case Specifier : Maintain
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Verilog 2001 : YES
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---- Other Options
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Clock Enable : YES
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wysiwyg : NO
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=========================================================================
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Setting FSM Encoding Algorithm to : JOHN
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=========================================================================
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* HDL Compilation *
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=========================================================================
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Compiling vhdl file "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.vhd" in Library work.
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Architecture behavioral of Entity lan_ide_cp is up to date.
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=========================================================================
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* Design Hierarchy Analysis *
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=========================================================================
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Analyzing hierarchy for entity <LAN_IDE_CP> in library <work> (architecture <behavioral>).
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=========================================================================
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* HDL Analysis *
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=========================================================================
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Analyzing Entity <LAN_IDE_CP> in library <work> (Architecture <behavioral>).
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Entity <LAN_IDE_CP> analyzed. Unit <LAN_IDE_CP> generated.
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=========================================================================
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* HDL Synthesis *
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=========================================================================
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Performing bidirectional port resolution...
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INFO:Xst:2561 - Always blocking tristate driving signal <A> in unit <LAN_IDE_CP> is removed.
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INFO:Xst:2561 - Always blocking tristate driving signal <A> in unit <LAN_IDE_CP> is removed.
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INFO:Xst:2561 - Always blocking tristate driving signal <A> in unit <LAN_IDE_CP> is removed.
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INFO:Xst:2561 - Always blocking tristate driving signal <A> in unit <LAN_IDE_CP> is removed.
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INFO:Xst:2561 - Always blocking tristate driving signal <A> in unit <LAN_IDE_CP> is removed.
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INFO:Xst:2561 - Always blocking tristate driving signal <A> in unit <LAN_IDE_CP> is removed.
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INFO:Xst:2561 - Always blocking tristate driving signal <A> in unit <LAN_IDE_CP> is removed.
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Synthesizing Unit <LAN_IDE_CP>.
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Related source file is "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.vhd".
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WARNING:Xst:647 - Input <IDE_WAIT> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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WARNING:Xst:647 - Input <BERR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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WARNING:Xst:647 - Input <MTCR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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WARNING:Xst:1780 - Signal <LAN_SM_RST> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
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WARNING:Xst:1780 - Signal <LAN_IRQ_OUT> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
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WARNING:Xst:1780 - Signal <LAN_IRQ_D0> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
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WARNING:Xst:1780 - Signal <CP_WE_QUIRK> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
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INFO:Xst:1799 - State start_read_upper is never reached in FSM <LAN_SM>.
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Found finite state machine <FSM_0> for signal <LAN_SM>.
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-----------------------------------------------------------------------
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| States | 15 |
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| Transitions | 29 |
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| Inputs | 9 |
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| Outputs | 16 |
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| Clock | CLK_EXT (rising_edge) |
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| Reset | RESET (negative) |
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| Reset type | asynchronous |
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| Reset State | nop |
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| Power Up State | nop |
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| Encoding | johnson |
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| Implementation | automatic |
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-----------------------------------------------------------------------
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Found finite state machine <FSM_1> for signal <LAN_RST_SM>.
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-----------------------------------------------------------------------
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| States | 8 |
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| Transitions | 8 |
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| Inputs | 0 |
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| Outputs | 30 |
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| Clock | CLK_EXT (rising_edge) |
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| Reset | RESET (positive) |
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| Reset type | asynchronous |
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| Reset State | nop |
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| Power Up State | nop |
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| Encoding | johnson |
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| Implementation | automatic |
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-----------------------------------------------------------------------
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Found 16-bit tristate buffer for signal <D>.
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Found 16-bit tristate buffer for signal <DQ>.
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Found 1-bit tristate buffer for signal <OWN>.
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Found 1-bit tristate buffer for signal <OVR>.
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Found 1-bit tristate buffer for signal <MTACK>.
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Found 1-bit tristate buffer for signal <DTACK>.
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Found 1-bit tristate buffer for signal <INT2_OUT>.
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Found 1-bit tristate buffer for signal <INT6_OUT>.
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Found 4-bit tristate buffer for signal <LAN_CFG>.
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Found 1-bit tristate buffer for signal <A<23>>.
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Found 1-bit tristate buffer for signal <A<22>>.
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Found 1-bit tristate buffer for signal <A<21>>.
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Found 1-bit tristate buffer for signal <A<20>>.
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Found 1-bit tristate buffer for signal <A<19>>.
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Found 1-bit tristate buffer for signal <A<18>>.
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Found 1-bit tristate buffer for signal <A<17>>.
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Found 1-bit tristate buffer for signal <A<16>>.
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Found 1-bit tristate buffer for signal <A<15>>.
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Found 1-bit tristate buffer for signal <A<14>>.
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Found 1-bit tristate buffer for signal <A<13>>.
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Found 1-bit tristate buffer for signal <A<12>>.
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Found 1-bit tristate buffer for signal <A<11>>.
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Found 1-bit tristate buffer for signal <A<10>>.
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Found 1-bit tristate buffer for signal <A<9>>.
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Found 1-bit tristate buffer for signal <A<8>>.
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Found 1-bit xor2 for signal <AMIGA_CLK$xor0000> created at line 180.
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Found 3-bit register for signal <AUTO_CONFIG_Z2_DONE>.
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Found 3-bit register for signal <AUTO_CONFIG_Z2_DONE_CYCLE>.
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Found 1-bit register for signal <AUTOCONFIG_Z2_ACCESS>.
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Found 1-bit register for signal <CP_ACCESS>.
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Found 16-bit comparator equal for signal <CP_ACCESS$cmp_eq0000> created at line 276.
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Found 16-bit register for signal <CP_BASEADR>.
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Found 1-bit register for signal <CP_RD_S>.
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Found 4-bit up counter for signal <CP_WAIT>.
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Found 1-bit register for signal <CP_WE_S>.
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Found 4-bit register for signal <D_Z2_OUT>.
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Found 16-bit register for signal <DQ_DATA>.
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Found 1-bit register for signal <DQ_SWAP>.
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Found 2-bit comparator less for signal <DQ_SWAP$cmp_lt0000> created at line 264.
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Found 1-bit register for signal <IDE_ACCESS>.
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Found 8-bit comparator equal for signal <IDE_ACCESS$cmp_eq0000> created at line 303.
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Found 8-bit register for signal <IDE_BASEADR>.
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Found 1-bit register for signal <IDE_ENABLE>.
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Found 1-bit register for signal <IDE_R_S>.
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Found 1-bit register for signal <IDE_W_S>.
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Found 14-bit register for signal <LAN_A_INIT>.
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Found 1-bit register for signal <LAN_ACCESS>.
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Found 16-bit comparator equal for signal <LAN_ACCESS$cmp_eq0000> created at line 263.
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Found 16-bit register for signal <LAN_BASEADR>.
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Found 1-bit register for signal <LAN_CS_RST>.
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Found 16-bit register for signal <LAN_D_INIT>.
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Found 1-bit register for signal <LAN_INT_ENABLE>.
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Found 1-bit register for signal <LAN_RD_S>.
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Found 1-bit register for signal <LAN_READY>.
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Found 4-bit comparator less for signal <LAN_SM$cmp_lt0000> created at line 489.
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Found 2-bit comparator less for signal <LAN_SM$cmp_lt0001> created at line 494.
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Found 1-bit register for signal <LAN_WR_RST>.
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Found 1-bit register for signal <LAN_WRH_S>.
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Found 1-bit register for signal <LAN_WRL_S>.
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Found 1-bit register for signal <ROM_OE_S>.
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Found 3-bit register for signal <SHUT_UP_Z2>.
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Found 1-bit register for signal <Z3_A_LOW>.
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Found 14-bit register for signal <Z3_ADR>.
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Found 32-bit register for signal <Z3_DATA>.
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Summary:
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inferred 2 Finite State Machine(s).
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inferred 1 Counter(s).
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inferred 89 D-type flip-flop(s).
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inferred 6 Comparator(s).
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inferred 1 Xor(s).
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inferred 58 Tristate(s).
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Unit <LAN_IDE_CP> synthesized.
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=========================================================================
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HDL Synthesis Report
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Macro Statistics
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# Counters : 1
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4-bit up counter : 1
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# Registers : 96
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1-bit register : 89
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14-bit register : 2
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16-bit register : 2
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3-bit register : 1
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4-bit register : 1
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8-bit register : 1
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# Comparators : 6
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16-bit comparator equal : 2
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2-bit comparator less : 2
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4-bit comparator less : 1
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8-bit comparator equal : 1
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# Tristates : 28
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1-bit tristate buffer : 26
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16-bit tristate buffer : 2
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# Xors : 1
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1-bit xor2 : 1
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=========================================================================
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=========================================================================
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* Advanced HDL Synthesis *
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=========================================================================
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Optimizing FSM <LAN_RST_SM/FSM> on signal <LAN_RST_SM[1:4]> with johnson encoding.
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------------------------
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State | Encoding
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------------------------
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nop | 0000
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wait0 | 0001
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clr | 0011
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clr_commit | 0111
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wait1 | 1111
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set | 1110
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set_commit | 1100
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done | 1000
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------------------------
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Optimizing FSM <LAN_SM/FSM> on signal <LAN_SM[1:8]> with johnson encoding.
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-------------------------------
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State | Encoding
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-------------------------------
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nop | 00000000
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start_read_upper | unreached
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wait_read_upper | 00000011
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end_read_upper | 11111111
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start_read_lower | 11111100
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wait_read_lower | 00000111
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end_read_lower | 11111000
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start_write_upper | 00001111
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wait_write_upper | 11110000
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end_write_upper | 11100000
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start_write_lower | 00011111
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wait_write_lower | 11000000
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wait_cycle_end | 11111110
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config_rw | 00000001
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cp_read | 00111111
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cp_write_wait | 01111111
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-------------------------------
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WARNING:Xst:1293 - FF/Latch <0> has a constant value of 1 in block <13>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1293 - FF/Latch <0> has a constant value of 1 in block <12>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1293 - FF/Latch <0> has a constant value of 1 in block <11>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1293 - FF/Latch <0> has a constant value of 1 in block <10>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1293 - FF/Latch <0> has a constant value of 1 in block <9>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1293 - FF/Latch <0> has a constant value of 1 in block <8>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1293 - FF/Latch <0> has a constant value of 1 in block <7>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1293 - FF/Latch <0> has a constant value of 1 in block <5>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1293 - FF/Latch <0> has a constant value of 1 in block <4>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1293 - FF/Latch <0> has a constant value of 1 in block <2>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1293 - FF/Latch <0> has a constant value of 1 in block <1>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1293 - FF/Latch <0> has a constant value of 1 in block <0>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <15>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <14>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <13>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <12>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <7>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <6>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <5>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <3>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <2>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <0>. This FF/Latch will be trimmed during the optimization process.
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=========================================================================
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Advanced HDL Synthesis Report
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Macro Statistics
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# FSMs : 2
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# Counters : 1
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4-bit up counter : 1
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# Registers : 89
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Flip-Flops : 89
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# Comparators : 3
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16-bit comparator equal : 2
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8-bit comparator equal : 1
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=========================================================================
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=========================================================================
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* Low Level Synthesis *
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=========================================================================
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WARNING:Xst:1293 - FF/Latch <LAN_D_INIT_15> has a constant value of 0 in block <LAN_IDE_CP>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <LAN_D_INIT_14> has a constant value of 0 in block <LAN_IDE_CP>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <LAN_D_INIT_13> has a constant value of 0 in block <LAN_IDE_CP>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <LAN_D_INIT_12> has a constant value of 0 in block <LAN_IDE_CP>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <LAN_D_INIT_7> has a constant value of 0 in block <LAN_IDE_CP>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <LAN_D_INIT_6> has a constant value of 0 in block <LAN_IDE_CP>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <LAN_D_INIT_5> has a constant value of 0 in block <LAN_IDE_CP>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <LAN_D_INIT_3> has a constant value of 0 in block <LAN_IDE_CP>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <LAN_D_INIT_2> has a constant value of 0 in block <LAN_IDE_CP>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <LAN_D_INIT_0> has a constant value of 0 in block <LAN_IDE_CP>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <LAN_A_INIT_13> has a constant value of 1 in block <LAN_IDE_CP>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <LAN_A_INIT_12> has a constant value of 1 in block <LAN_IDE_CP>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <LAN_A_INIT_11> has a constant value of 1 in block <LAN_IDE_CP>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <LAN_A_INIT_10> has a constant value of 1 in block <LAN_IDE_CP>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <LAN_A_INIT_9> has a constant value of 1 in block <LAN_IDE_CP>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <LAN_A_INIT_8> has a constant value of 1 in block <LAN_IDE_CP>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <LAN_A_INIT_7> has a constant value of 1 in block <LAN_IDE_CP>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <LAN_A_INIT_5> has a constant value of 1 in block <LAN_IDE_CP>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <LAN_A_INIT_4> has a constant value of 1 in block <LAN_IDE_CP>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <LAN_A_INIT_2> has a constant value of 1 in block <LAN_IDE_CP>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <LAN_A_INIT_1> has a constant value of 1 in block <LAN_IDE_CP>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <LAN_A_INIT_0> has a constant value of 1 in block <LAN_IDE_CP>. This FF/Latch will be trimmed during the optimization process.
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INFO:Xst:2261 - The FF/Latch <LAN_D_INIT_8> in Unit <LAN_IDE_CP> is equivalent to the following 3 FFs/Latches, which will be removed : <LAN_D_INIT_10> <LAN_D_INIT_11> <LAN_RST_SM_FSM_FFd4>
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INFO:Xst:2261 - The FF/Latch <LAN_D_INIT_1> in Unit <LAN_IDE_CP> is equivalent to the following 2 FFs/Latches, which will be removed : <LAN_D_INIT_4> <LAN_D_INIT_9>
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Optimizing unit <LAN_IDE_CP> ...
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implementation constraint: INIT=r : AUTO_CONFIG_Z2_DONE_0
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implementation constraint: INIT=s : SHUT_UP_Z2_0
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implementation constraint: INIT=s : SHUT_UP_Z2_1
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implementation constraint: INIT=s : SHUT_UP_Z2_2
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implementation constraint: INIT=s : D_Z2_OUT_2
|
|
implementation constraint: INIT=r : LAN_INT_ENABLE
|
|
implementation constraint: INIT=r : LAN_SM_FSM_FFd8
|
|
implementation constraint: INIT=r : LAN_SM_FSM_FFd7
|
|
implementation constraint: INIT=r : LAN_SM_FSM_FFd6
|
|
implementation constraint: INIT=s : LAN_A_INIT_3
|
|
implementation constraint: INIT=r : LAN_SM_FSM_FFd5
|
|
implementation constraint: INIT=r : LAN_SM_FSM_FFd4
|
|
implementation constraint: INIT=s : LAN_A_INIT_6
|
|
implementation constraint: INIT=r : LAN_SM_FSM_FFd3
|
|
implementation constraint: INIT=r : LAN_SM_FSM_FFd2
|
|
implementation constraint: INIT=r : LAN_SM_FSM_FFd1
|
|
implementation constraint: INIT=s : D_Z2_OUT_3
|
|
implementation constraint: INIT=r : AUTO_CONFIG_Z2_DONE_CYCLE_1
|
|
implementation constraint: INIT=r : AUTO_CONFIG_Z2_DONE_CYCLE_0
|
|
implementation constraint: INIT=r : AUTO_CONFIG_Z2_DONE_CYCLE_2
|
|
implementation constraint: INIT=r : LAN_D_INIT_1
|
|
implementation constraint: INIT=s : D_Z2_OUT_1
|
|
implementation constraint: INIT=s : D_Z2_OUT_0
|
|
implementation constraint: INIT=r : AUTO_CONFIG_Z2_DONE_2
|
|
implementation constraint: INIT=r : LAN_D_INIT_8
|
|
implementation constraint: INIT=r : AUTO_CONFIG_Z2_DONE_1
|
|
implementation constraint: INIT=r : LAN_RST_SM_FSM_FFd1
|
|
implementation constraint: INIT=r : LAN_RST_SM_FSM_FFd2
|
|
implementation constraint: INIT=r : LAN_RST_SM_FSM_FFd3
|
|
|
|
=========================================================================
|
|
* Partition Report *
|
|
=========================================================================
|
|
|
|
Partition Implementation Status
|
|
-------------------------------
|
|
|
|
No Partitions were found in this design.
|
|
|
|
-------------------------------
|
|
|
|
=========================================================================
|
|
* Final Report *
|
|
=========================================================================
|
|
Final Results
|
|
RTL Top Level Output File Name : LAN_IDE_CP.ngr
|
|
Top Level Output File Name : LAN_IDE_CP
|
|
Output Format : NGC
|
|
Optimization Goal : Speed
|
|
Keep Hierarchy : Yes
|
|
Target Technology : XC9500XL CPLDs
|
|
Macro Preserve : YES
|
|
XOR Preserve : YES
|
|
Clock Enable : YES
|
|
wysiwyg : NO
|
|
|
|
Design Statistics
|
|
# IOs : 117
|
|
|
|
Cell Usage :
|
|
# BELS : 2318
|
|
# AND2 : 681
|
|
# AND3 : 94
|
|
# AND4 : 9
|
|
# AND5 : 2
|
|
# AND8 : 5
|
|
# GND : 1
|
|
# INV : 894
|
|
# OR2 : 412
|
|
# OR3 : 149
|
|
# OR4 : 26
|
|
# XOR2 : 45
|
|
# FlipFlops/Latches : 153
|
|
# FDC : 29
|
|
# FDCE : 7
|
|
# FDP : 73
|
|
# FDPE : 44
|
|
# IO Buffers : 114
|
|
# IBUF : 23
|
|
# IOBUFE : 48
|
|
# OBUF : 33
|
|
# OBUFE : 10
|
|
=========================================================================
|
|
|
|
|
|
Total REAL time to Xst completion: 9.00 secs
|
|
Total CPU time to Xst completion: 9.20 secs
|
|
|
|
-->
|
|
|
|
Total memory usage is 4534800 kilobytes
|
|
|
|
Number of errors : 0 ( 0 filtered)
|
|
Number of warnings : 51 ( 0 filtered)
|
|
Number of infos : 10 ( 0 filtered)
|
|
|