3126 lines
163 KiB
Plaintext
3126 lines
163 KiB
Plaintext
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cpldfit: version P.20131013 Xilinx Inc.
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Fitter Report
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Design Name: LAN_IDE_CP Date: 12-18-2018, 10:54PM
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Device Used: XC95288XL-10-TQ144
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Fitting Status: Successful
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************************* Mapped Resource Summary **************************
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Macrocells Product Terms Function Block Registers Pins
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Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot
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194/288 ( 67%) 958 /1440 ( 67%) 449/864 ( 52%) 115/288 ( 40%) 109/117 ( 93%)
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** Function Block Resources **
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Function Mcells FB Inps Pterms IO
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Block Used/Tot Used/Tot Used/Tot Used/Tot
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FB1 18/18* 22/54 42/90 8/ 8*
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FB2 15/18 33/54 74/90 10/10*
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FB3 2/18 2/54 1/90 3/ 5
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FB4 15/18 33/54 90/90* 6/ 6*
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FB5 12/18 33/54 77/90 7/ 8
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FB6 15/18 34/54 42/90 8/ 8*
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FB7 11/18 29/54 90/90* 4/ 4*
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FB8 11/18 34/54 66/90 5/ 5*
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FB9 10/18 31/54 88/90 8/ 9
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FB10 15/18 33/54 48/90 10/10*
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FB11 14/18 30/54 75/90 7/ 7*
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FB12 11/18 33/54 22/90 6/ 6*
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FB13 9/18 33/54 65/90 6/ 6*
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FB14 8/18 11/54 17/90 5/ 8
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FB15 11/18 32/54 83/90 8/ 9
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FB16 17/18 26/54 78/90 8/ 8*
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----- ----- ----- -----
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194/288 449/864 958/1440 109/117
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* - Resource is exhausted
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** Global Control Resources **
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Signal 'CLK_EXT' mapped onto global clock net GCK1.
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Global output enable net(s) unused.
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Global set/reset net(s) unused.
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** Pin Resources **
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Signal Type Required Mapped | Pin Type Used Total
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------------------------------------|------------------------------------
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Input : 18 18 | I/O : 102 109
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Output : 42 42 | GCK/IO : 2 3
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Bidirectional : 48 48 | GTS/IO : 4 4
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GCK : 1 1 | GSR/IO : 1 1
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GTS : 0 0 |
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GSR : 0 0 |
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---- ----
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Total 109 109
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** Power Data **
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There are 194 macrocells in high performance mode (MCHP).
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There are 0 macrocells in low power mode (MCLP).
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End of Mapped Resource Summary
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************************** Errors and Warnings ***************************
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WARNING:Cpld - Unable to retrieve the path to the iSE Project Repository. Will
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use the default filename of 'LAN_IDE_CP.ise'.
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INFO:Cpld - Inferring BUFG constraint for signal 'CLK_EXT' based upon the LOC
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constraint 'P30'. It is recommended that you declare this BUFG explicitedly
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in your design. Note that for certain device families the output of a BUFG
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constraint can not drive a gated clock, and the BUFG constraint will be
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ignored.
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WARNING:Cpld:1007 - Removing unused input(s) 'A<1>'. The input(s) are unused
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after optimization. Please verify functionality via simulation.
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WARNING:Cpld:1007 - Removing unused input(s) 'AS'. The input(s) are unused
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after optimization. Please verify functionality via simulation.
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WARNING:Cpld:1007 - Removing unused input(s) 'C1'. The input(s) are unused
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after optimization. Please verify functionality via simulation.
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WARNING:Cpld:1007 - Removing unused input(s) 'C3'. The input(s) are unused
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after optimization. Please verify functionality via simulation.
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WARNING:Cpld:1007 - Removing unused input(s) 'CP_IRQ'. The input(s) are unused
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after optimization. Please verify functionality via simulation.
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WARNING:Cpld:1007 - Removing unused input(s) 'IDE_WAIT'. The input(s) are
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unused after optimization. Please verify functionality via simulation.
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WARNING:Cpld:1007 - Removing unused input(s) 'MTCR'. The input(s) are unused
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after optimization. Please verify functionality via simulation.
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************************* Summary of Mapped Logic ************************
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** 90 Outputs **
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Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init
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Name Pts Inps No. Type Use Mode Rate State
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D<5> 5 9 FB1_5 20 I/O I/O STD FAST
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D<4> 5 9 FB1_6 21 I/O I/O STD FAST
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IDE_CS<0> 0 0 FB1_8 22 I/O O STD FAST
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IDE_CS<1> 0 0 FB1_10 23 I/O O STD FAST
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IDE_A<0> 0 0 FB1_12 24 I/O O STD FAST
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IDE_A<2> 0 0 FB1_14 25 I/O O STD FAST
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IDE_A<1> 0 0 FB1_15 26 I/O O STD FAST
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IDE_R 0 0 FB1_17 27 I/O O STD FAST
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A_LAN<4> 1 2 FB2_2 9 I/O O STD FAST
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A_LAN<7> 1 2 FB2_3 10 I/O O STD FAST
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A_LAN<6> 2 3 FB2_5 11 I/O O STD FAST
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LAN_CFG<1> 0 0 FB2_6 12 I/O O STD FAST
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LAN_CFG<3> 0 0 FB2_8 13 I/O O STD FAST
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D<6> 5 9 FB2_10 14 I/O I/O STD FAST
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D<3> 5 9 FB2_12 15 I/O I/O STD FAST
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D<7> 5 9 FB2_14 16 I/O I/O STD FAST
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D<1> 5 9 FB2_15 17 I/O I/O STD FAST
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D<8> 9 10 FB2_17 19 I/O I/O STD FAST
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IDE_W 0 0 FB3_2 28 I/O O STD FAST
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INT_OUT 1 2 FB3_14 32 GCK/I/O O STD FAST
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D<0> 5 9 FB4_2 2 GTS/I/O I/O STD FAST
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A_LAN<1> 1 2 FB4_5 3 GTS/I/O O STD FAST
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A_LAN<0> 1 2 FB4_6 4 I/O O STD FAST
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A_LAN<3> 2 3 FB4_8 5 GTS/I/O O STD FAST
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A_LAN<2> 1 2 FB4_12 6 GTS/I/O O STD FAST
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A_LAN<5> 1 2 FB4_14 7 I/O O STD FAST
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CP_CS 0 0 FB5_2 34 I/O O STD FAST
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ROM_OE 0 0 FB5_5 35 I/O O STD FAST
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D<2> 5 9 FB5_10 39 I/O I/O STD FAST
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D<9> 9 10 FB5_12 40 I/O I/O STD FAST
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D<10> 9 10 FB5_14 41 I/O I/O STD FAST
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D<11> 9 10 FB5_15 43 I/O I/O STD FAST
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D<12> 9 10 FB5_17 44 I/O I/O STD FAST
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LAN_CFG<2> 0 0 FB6_2 135 I/O O STD FAST
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A_LAN<12> 1 2 FB6_3 136 I/O O STD FAST
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A_LAN<13> 1 2 FB6_5 137 I/O O STD FAST
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A_LAN<10> 1 2 FB6_6 138 I/O O STD FAST
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A_LAN<11> 1 2 FB6_8 139 I/O O STD FAST
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A_LAN<8> 1 2 FB6_10 140 I/O O STD FAST
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A_LAN<9> 1 2 FB6_14 142 I/O O STD FAST
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Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init
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Name Pts Inps No. Type Use Mode Rate State
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D<13> 9 10 FB7_3 45 I/O I/O STD FAST
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D<14> 9 10 FB7_5 46 I/O I/O STD FAST
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D<15> 9 10 FB7_12 48 I/O I/O STD FAST
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DQ<12> 2 3 FB8_2 130 I/O I/O STD FAST
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DQ<14> 2 3 FB8_3 131 I/O I/O STD FAST
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LAN_WRH 3 4 FB8_5 132 I/O O STD FAST
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LAN_CS 2 3 FB8_8 133 I/O O STD FAST
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LAN_RD 1 3 FB8_10 134 I/O O STD FAST
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A<8> 5 11 FB9_11 56 I/O I/O STD FAST RESET
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A<9> 5 11 FB9_14 58 I/O I/O STD FAST RESET
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A<10> 5 11 FB9_17 59 I/O I/O STD FAST RESET
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DQ<1> 3 4 FB10_2 117 I/O I/O STD FAST
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DQ<0> 2 3 FB10_3 118 I/O I/O STD FAST
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DQ<3> 2 3 FB10_5 119 I/O I/O STD FAST
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DQ<2> 2 3 FB10_6 120 I/O I/O STD FAST
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DQ<5> 2 3 FB10_8 121 I/O I/O STD FAST
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DQ<4> 3 4 FB10_10 124 I/O I/O STD FAST
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DQ<7> 2 3 FB10_11 125 I/O I/O STD FAST
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DQ<6> 2 3 FB10_12 126 I/O I/O STD FAST
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DQ<8> 3 4 FB10_14 128 I/O I/O STD FAST
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DQ<10> 3 4 FB10_17 129 I/O I/O STD FAST
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A<11> 5 11 FB11_3 60 I/O I/O STD FAST RESET
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A<12> 5 11 FB11_5 61 I/O I/O STD FAST RESET
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A<13> 5 11 FB11_10 64 I/O I/O STD FAST RESET
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A<14> 5 11 FB11_11 66 I/O I/O STD FAST RESET
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ROM_B<0> 0 0 FB11_12 68 I/O O STD FAST
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ROM_B<1> 0 0 FB11_14 69 I/O O STD FAST
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CP_WE 0 0 FB11_17 70 I/O O STD FAST
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LAN_CFG<4> 0 0 FB12_2 110 I/O O STD FAST
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DQ<15> 2 3 FB12_5 112 I/O I/O STD FAST
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DQ<13> 2 3 FB12_8 113 I/O I/O STD FAST
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DQ<11> 3 4 FB12_10 115 I/O I/O STD FAST
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DQ<9> 3 4 FB12_12 116 I/O I/O STD FAST
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CP_RD 0 0 FB13_2 71 I/O O STD FAST
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A<15> 5 11 FB13_8 74 I/O I/O STD FAST RESET
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LAN_WRL 3 4 FB13_14 76 I/O O STD FAST
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OVR 0 0 FB14_3 100 I/O O STD FAST
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CFOUT 3 4 FB14_11 105 I/O O STD FAST SET
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SLAVE 2 3 FB14_14 106 I/O O STD FAST
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OWN 0 0 FB14_15 107 I/O O STD FAST
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Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init
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Name Pts Inps No. Type Use Mode Rate State
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DTACK 1 1 FB15_12 85 I/O O STD FAST
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A<23> 5 11 FB15_14 86 I/O I/O STD FAST RESET
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A<22> 5 11 FB15_15 87 I/O I/O STD FAST RESET
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A<21> 5 11 FB15_17 88 I/O I/O STD FAST RESET
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A<20> 5 11 FB16_2 91 I/O I/O STD FAST RESET
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A<19> 5 11 FB16_3 92 I/O I/O STD FAST RESET
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A<18> 5 11 FB16_6 94 I/O I/O STD FAST RESET
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A<17> 5 11 FB16_8 95 I/O I/O STD FAST RESET
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MTACK 0 0 FB16_10 96 I/O O STD FAST
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A<16> 5 11 FB16_11 97 I/O I/O STD FAST RESET
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** 104 Buried Nodes **
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Signal Total Total Loc Pwr Reg Init
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Name Pts Inps Mode State
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LAN_RST_SM_FSM_FFd1 2 4 FB1_1 STD RESET
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LAN_IRQ_D0 2 2 FB1_2 STD RESET
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LAN_CS_RST 2 3 FB1_3 STD RESET
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LAN_WRL_S 3 7 FB1_4 STD RESET
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LAN_WRH_S 3 7 FB1_7 STD RESET
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LAN_RST_SM_FSM_FFd3 3 3 FB1_9 STD RESET
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LAN_RST_SM_FSM_FFd2 3 4 FB1_11 STD RESET
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LAN_IRQ_OUT 3 4 FB1_13 STD RESET
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LAN_SM_FSM_FFd1 4 6 FB1_16 STD RESET
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LAN_READY 7 7 FB1_18 STD RESET
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LAN_BASEADR<0> 9 17 FB2_1 STD RESET
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LAN_BASEADR<11> 9 17 FB2_4 STD RESET
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LAN_BASEADR<12> 9 17 FB2_7 STD RESET
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SHUT_UP 5 16 FB2_9 STD RESET
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LAN_BASEADR<10> 9 17 FB2_16 STD RESET
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CONFIG_READY 2 5 FB4_3 STD RESET
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LAN_BASEADR<6> 9 17 FB4_4 STD RESET
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LAN_BASEADR<5> 9 17 FB4_7 STD RESET
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LAN_BASEADR<3> 9 17 FB4_9 STD RESET
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LAN_BASEADR<4> 9 17 FB4_10 STD RESET
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LAN_BASEADR<2> 9 17 FB4_13 STD RESET
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LAN_BASEADR<1> 9 17 FB4_15 STD RESET
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D_OUT<5> 12 14 FB4_17 STD SET
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D_OUT<4> 11 14 FB4_18 STD SET
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AUTO_CONFIG_DONE_CYCLE 5 15 FB5_1 STD RESET
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LAN_BASEADR<13> 9 17 FB5_4 STD RESET
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LAN_BASEADR<14> 9 17 FB5_7 STD RESET
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LAN_BASEADR<15> 9 17 FB5_8 STD RESET
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$OpTx$FX_DC$118__$INT 4 8 FB5_18 STD
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$OpTx$INV$205 16 16 FB6_1 STD
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N0$BUF7/N0$BUF7_TRST__$INT 2 4 FB6_9 STD
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Z3_ADR<7> 3 3 FB6_11 STD RESET
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Z3_ADR<6> 3 3 FB6_12 STD RESET
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Z3_ADR<5> 3 3 FB6_13 STD RESET
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Z3_ADR<4> 3 3 FB6_15 STD RESET
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Z3_ADR<3> 3 3 FB6_16 STD RESET
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Z3_ADR<2> 3 3 FB6_17 STD RESET
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D_OUT<6> 11 14 FB7_1 STD SET
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$OpTx$FX_DC$112 2 5 FB7_2 STD
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$OpTx$FX_SC$119__$INT 4 8 FB7_7 STD
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Signal Total Total Loc Pwr Reg Init
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Name Pts Inps Mode State
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LAN_BASEADR<9> 9 17 FB7_9 STD RESET
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LAN_BASEADR<8> 9 17 FB7_11 STD RESET
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LAN_BASEADR<7> 9 17 FB7_13 STD RESET
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D_OUT<2> 9 13 FB7_16 STD SET
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D_OUT<1> 10 13 FB7_18 STD SET
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Z3_ADR<13> 3 3 FB8_4 STD RESET
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Z3_ADR<12> 3 3 FB8_7 STD RESET
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Z3_ADR<11> 3 3 FB8_9 STD RESET
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Z3_ADR<10> 3 3 FB8_11 STD RESET
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LAN_ACCESS 21 21 FB8_13 STD RESET
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DQ_SWAP 23 23 FB8_18 STD RESET
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DQ_DATA<7> 13 13 FB9_4 STD RESET
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LAN_SM_FSM_FFd2 5 8 FB9_6 STD RESET
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LAN_SM_FSM_FFd4 7 8 FB9_8 STD RESET
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DQ_DATA<6> 13 13 FB9_9 STD RESET
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Z3_A_LOW 9 9 FB9_13 STD RESET
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DQ_DATA<15> 13 13 FB9_16 STD RESET
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DQ_DATA<14> 13 13 FB9_18 STD RESET
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LAN_SM_RST 4 8 FB10_9 STD RESET
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LAN_INT_ENABLE 5 10 FB10_13 STD RESET
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D_OUT<7> 5 12 FB10_15 STD SET
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D_OUT<3> 5 11 FB10_16 STD SET
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D_OUT<0> 5 13 FB10_18 STD SET
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DQ_DATA<10> 13 13 FB11_1 STD RESET
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Z3_DATA<30> 4 8 FB11_6 STD RESET
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Z3_DATA<29> 4 8 FB11_7 STD RESET
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Z3_DATA<22> 4 8 FB11_8 STD RESET
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Z3_DATA<21> 4 8 FB11_9 STD RESET
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DQ_DATA<2> 13 13 FB11_13 STD RESET
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DQ_DATA<11> 13 13 FB11_16 STD RESET
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Z3_ADR_1/Z3_ADR_1_SETF__$INT 1 2 FB12_13 STD
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LAN_WR_RST 2 3 FB12_14 STD RESET
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LAN_D_INIT<8> 2 2 FB12_15 STD RESET
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LAN_D_INIT<1> 2 2 FB12_16 STD RESET
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LAN_A_INIT<6> 2 2 FB12_17 STD SET
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AUTOCONFIG_ACCESS 3 21 FB12_18 STD RESET
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DQ_DATA<1> 13 13 FB13_1 STD RESET
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DQ_DATA<3> 13 13 FB13_6 STD RESET
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DQ_DATA<8> 13 13 FB13_12 STD RESET
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LAN_RD_S 4 6 FB13_15 STD RESET
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Signal Total Total Loc Pwr Reg Init
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Name Pts Inps Mode State
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DQ_DATA<9> 13 13 FB13_16 STD RESET
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LAN_A_INIT<3> 1 1 FB13_18 STD SET
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Z3_ADR_1 3 3 FB14_13 STD RESET
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Z3_ADR_0 3 3 FB14_16 STD RESET
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Z3_ADR<9> 3 3 FB14_17 STD RESET
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Z3_ADR<8> 3 3 FB14_18 STD RESET
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DQ_DATA<12> 13 13 FB15_1 STD RESET
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LAN_SM_FSM_FFd3 7 10 FB15_2 STD RESET
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Z3_DATA<31> 4 8 FB15_4 STD RESET
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DQ_DATA<4> 13 13 FB15_6 STD RESET
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DQ_DATA<5> 13 13 FB15_7 STD RESET
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DQ_DATA<13> 13 13 FB15_11 STD RESET
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Z3_DATA<23> 4 8 FB15_13 STD RESET
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Z3_DATA<28> 4 8 FB16_1 STD RESET
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Z3_DATA<27> 4 8 FB16_4 STD RESET
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Z3_DATA<26> 4 8 FB16_5 STD RESET
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Z3_DATA<25> 4 8 FB16_7 STD RESET
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Z3_DATA<24> 4 8 FB16_9 STD RESET
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Z3_DATA<19> 4 8 FB16_12 STD RESET
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Z3_DATA<18> 4 8 FB16_13 STD RESET
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Z3_DATA<17> 4 8 FB16_14 STD RESET
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Z3_DATA<16> 4 8 FB16_15 STD RESET
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DQ_DATA<0> 13 13 FB16_16 STD RESET
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Z3_DATA<20> 4 8 FB16_18 STD RESET
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** 19 Inputs **
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Signal Loc Pin Pin Pin
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Name No. Type Use
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CLK_EXT FB3_10 30 GCK/I/O GCK
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RESET FB6_15 143 GSR/I/O I
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A<5> FB7_15 49 I/O I
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A<4> FB9_2 50 I/O I
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A<6> FB9_3 51 I/O I
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A<3> FB9_5 52 I/O I
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A<7> FB9_6 53 I/O I
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A<2> FB9_8 54 I/O I
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LAN_INT FB12_3 111 I/O I
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AUTOBOOT_OFF FB13_11 75 I/O I
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FCS FB13_15 77 I/O I
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DS1 FB13_17 78 I/O I
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CFIN FB14_10 104 I/O I
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Z3 FB15_2 79 I/O I
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UDS FB15_8 81 I/O I
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LDS FB15_10 82 I/O I
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RW FB15_11 83 I/O I
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DS0 FB16_5 93 I/O I
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BERR FB16_12 98 I/O I
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Legend:
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Pin No. - ~ - User Assigned
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************************** Function Block Details ************************
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Legend:
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Total Pt - Total product terms used by the macrocell signal
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Imp Pt - Product terms imported from other macrocells
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Exp Pt - Product terms exported to other macrocells
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in direction shown
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Unused Pt - Unused local product terms remaining in macrocell
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Loc - Location where logic was mapped in device
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Pin Type/Use - I - Input GCK - Global Clock
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O - Output GTS - Global Output Enable
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(b) - Buried macrocell GSR - Global Set/Reset
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X - Signal used as input to the macrocell logic.
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Pin No. - ~ - User Assigned
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*********************************** FB1 ***********************************
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Number of function block inputs used/remaining: 22/32
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Number of signals used by logic mapping into function block: 22
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Signal Total Imp Exp Unused Loc Pin Pin Pin
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Name Pt Pt Pt Pt # Type Use
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LAN_RST_SM_FSM_FFd1 2 0 0 3 FB1_1 (b) (b)
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LAN_IRQ_D0 2 0 0 3 FB1_2 (b) (b)
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LAN_CS_RST 2 0 0 3 FB1_3 (b) (b)
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LAN_WRL_S 3 0 0 2 FB1_4 (b) (b)
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D<5> 5 0 0 0 FB1_5 20 I/O I/O
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|
D<4> 5 0 0 0 FB1_6 21 I/O I/O
|
|
LAN_WRH_S 3 0 0 2 FB1_7 (b) (b)
|
|
IDE_CS<0> 0 0 0 5 FB1_8 22 I/O O
|
|
LAN_RST_SM_FSM_FFd3 3 0 0 2 FB1_9 (b) (b)
|
|
IDE_CS<1> 0 0 0 5 FB1_10 23 I/O O
|
|
LAN_RST_SM_FSM_FFd2 3 0 0 2 FB1_11 (b) (b)
|
|
IDE_A<0> 0 0 0 5 FB1_12 24 I/O O
|
|
LAN_IRQ_OUT 3 0 0 2 FB1_13 (b) (b)
|
|
IDE_A<2> 0 0 0 5 FB1_14 25 I/O O
|
|
IDE_A<1> 0 0 0 5 FB1_15 26 I/O O
|
|
LAN_SM_FSM_FFd1 4 0 0 1 FB1_16 (b) (b)
|
|
IDE_R 0 0 \/2 3 FB1_17 27 I/O O
|
|
LAN_READY 7 2<- 0 0 FB1_18 (b) (b)
|
|
|
|
Signals Used by Logic in Function Block
|
|
1: $OpTx$FX_SC$119__$INT 9: LAN_RST_SM_FSM_FFd1 16: LAN_SM_RST
|
|
2: DS0 10: LAN_RST_SM_FSM_FFd2 17: LDS
|
|
3: DS1 11: LAN_RST_SM_FSM_FFd3 18: RESET
|
|
4: FCS 12: LAN_SM_FSM_FFd1 19: RW
|
|
5: LAN_ACCESS 13: LAN_SM_FSM_FFd2 20: UDS
|
|
6: LAN_INT 14: LAN_SM_FSM_FFd3 21: Z3_DATA<20>
|
|
7: LAN_IRQ_D0 15: LAN_SM_FSM_FFd4 22: Z3_DATA<21>
|
|
8: LAN_IRQ_OUT
|
|
|
|
Signal 1 2 3 4 FB
|
|
Name 0----+----0----+----0----+----0----+----0 Inputs
|
|
LAN_RST_SM_FSM_FFd1 ........XXX......X...................... 4
|
|
LAN_IRQ_D0 .....X...........X...................... 2
|
|
LAN_CS_RST .........XX......X...................... 3
|
|
LAN_WRL_S ..X........XXXXX...X.................... 7
|
|
D<5> XXXXX...........X.XX.X.................. 9
|
|
D<4> XXXXX...........X.XXX................... 9
|
|
LAN_WRH_S .X.........XXXXXX....................... 7
|
|
IDE_CS<0> ........................................ 0
|
|
LAN_RST_SM_FSM_FFd3 ........XX.......X...................... 3
|
|
IDE_CS<1> ........................................ 0
|
|
LAN_RST_SM_FSM_FFd2 ........XXX......X...................... 4
|
|
IDE_A<0> ........................................ 0
|
|
LAN_IRQ_OUT .....XXX.........X...................... 4
|
|
IDE_A<2> ........................................ 0
|
|
IDE_A<1> ........................................ 0
|
|
LAN_SM_FSM_FFd1 .XX........X.XXX........................ 6
|
|
IDE_R ........................................ 0
|
|
LAN_READY .XX........XXXXX........................ 7
|
|
0----+----1----+----2----+----3----+----4
|
|
0 0 0 0
|
|
*********************************** FB2 ***********************************
|
|
Number of function block inputs used/remaining: 33/21
|
|
Number of signals used by logic mapping into function block: 33
|
|
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
|
Name Pt Pt Pt Pt # Type Use
|
|
LAN_BASEADR<0> 9 4<- 0 0 FB2_1 (b) (b)
|
|
A_LAN<4> 1 0 /\4 0 FB2_2 9 I/O O
|
|
A_LAN<7> 1 0 \/4 0 FB2_3 10 I/O O
|
|
LAN_BASEADR<11> 9 4<- 0 0 FB2_4 (b) (b)
|
|
A_LAN<6> 2 0 0 3 FB2_5 11 I/O O
|
|
LAN_CFG<1> 0 0 0 5 FB2_6 12 I/O O
|
|
LAN_BASEADR<12> 9 4<- 0 0 FB2_7 (b) (b)
|
|
LAN_CFG<3> 0 0 /\4 1 FB2_8 13 I/O O
|
|
SHUT_UP 5 0 0 0 FB2_9 (b) (b)
|
|
D<6> 5 0 0 0 FB2_10 14 I/O I/O
|
|
(unused) 0 0 0 5 FB2_11 (b)
|
|
D<3> 5 0 0 0 FB2_12 15 I/O I/O
|
|
(unused) 0 0 \/3 2 FB2_13 (b) (b)
|
|
D<7> 5 3<- \/3 0 FB2_14 16 I/O I/O
|
|
D<1> 5 3<- \/3 0 FB2_15 17 I/O I/O
|
|
LAN_BASEADR<10> 9 4<- 0 0 FB2_16 (b) (b)
|
|
D<8> 9 5<- /\1 0 FB2_17 19 I/O I/O
|
|
(unused) 0 0 /\5 0 FB2_18 (b) (b)
|
|
|
|
Signals Used by Logic in Function Block
|
|
1: $OpTx$FX_SC$119__$INT 12: LAN_BASEADR<12> 23: Z3_ADR<3>
|
|
2: AUTOCONFIG_ACCESS 13: LDS 24: Z3_ADR<4>
|
|
3: DS0 14: D<12>.PIN 25: Z3_ADR<5>
|
|
4: DS1 15: D<11>.PIN 26: Z3_ADR<6>
|
|
5: D_OUT<0> 16: D<10>.PIN 27: Z3_ADR_0
|
|
6: FCS 17: D<0>.PIN 28: Z3_ADR_1
|
|
7: LAN_ACCESS 18: RESET 29: Z3_DATA<17>
|
|
8: LAN_A_INIT<6> 19: RW 30: Z3_DATA<19>
|
|
9: LAN_BASEADR<0> 20: SHUT_UP 31: Z3_DATA<22>
|
|
10: LAN_BASEADR<10> 21: UDS 32: Z3_DATA<23>
|
|
11: LAN_BASEADR<11> 22: Z3_ADR<2> 33: Z3_DATA<24>
|
|
|
|
Signal 1 2 3 4 FB
|
|
Name 0----+----0----+----0----+----0----+----0 Inputs
|
|
LAN_BASEADR<0> .XXX.X..X...X...XXX.XXXXXXXX............ 17
|
|
A_LAN<4> .................X....X................. 2
|
|
A_LAN<7> .................X.......X.............. 2
|
|
LAN_BASEADR<11> .XXX.X....X.X.X..XX.XXXXXXXX............ 17
|
|
A_LAN<6> .......X.........X......X............... 3
|
|
LAN_CFG<1> ........................................ 0
|
|
LAN_BASEADR<12> .XXX.X.....XXX...XX.XXXXXXXX............ 17
|
|
LAN_CFG<3> ........................................ 0
|
|
SHUT_UP .XXX.X......X....XXXXXXXXXXX............ 16
|
|
D<6> X.XX.XX.....X.....X.X.........X......... 9
|
|
D<3> X.XX.XX.....X.....X.X........X.......... 9
|
|
D<7> X.XX.XX.....X.....X.X..........X........ 9
|
|
D<1> X.XX.XX.....X.....X.X.......X........... 9
|
|
LAN_BASEADR<10> .XXX.X...X..X..X.XX.XXXXXXXX............ 17
|
|
D<8> X.XXXXX.....X.....X.X...........X....... 10
|
|
0----+----1----+----2----+----3----+----4
|
|
0 0 0 0
|
|
*********************************** FB3 ***********************************
|
|
Number of function block inputs used/remaining: 2/52
|
|
Number of signals used by logic mapping into function block: 2
|
|
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
|
Name Pt Pt Pt Pt # Type Use
|
|
(unused) 0 0 0 5 FB3_1 (b)
|
|
IDE_W 0 0 0 5 FB3_2 28 I/O O
|
|
(unused) 0 0 0 5 FB3_3 (b)
|
|
(unused) 0 0 0 5 FB3_4 (b)
|
|
(unused) 0 0 0 5 FB3_5 (b)
|
|
(unused) 0 0 0 5 FB3_6 (b)
|
|
(unused) 0 0 0 5 FB3_7 (b)
|
|
(unused) 0 0 0 5 FB3_8 (b)
|
|
(unused) 0 0 0 5 FB3_9 (b)
|
|
(unused) 0 0 0 5 FB3_10 30 GCK/I/O GCK
|
|
(unused) 0 0 0 5 FB3_11 (b)
|
|
(unused) 0 0 0 5 FB3_12 31 I/O
|
|
(unused) 0 0 0 5 FB3_13 (b)
|
|
INT_OUT 1 0 0 4 FB3_14 32 GCK/I/O O
|
|
(unused) 0 0 0 5 FB3_15 33 I/O
|
|
(unused) 0 0 0 5 FB3_16 (b)
|
|
(unused) 0 0 0 5 FB3_17 (b)
|
|
(unused) 0 0 0 5 FB3_18 (b)
|
|
|
|
Signals Used by Logic in Function Block
|
|
1: LAN_INT_ENABLE 2: LAN_IRQ_OUT
|
|
|
|
Signal 1 2 3 4 FB
|
|
Name 0----+----0----+----0----+----0----+----0 Inputs
|
|
IDE_W ........................................ 0
|
|
INT_OUT XX...................................... 2
|
|
0----+----1----+----2----+----3----+----4
|
|
0 0 0 0
|
|
*********************************** FB4 ***********************************
|
|
Number of function block inputs used/remaining: 33/21
|
|
Number of signals used by logic mapping into function block: 33
|
|
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
|
Name Pt Pt Pt Pt # Type Use
|
|
(unused) 0 0 /\5 0 FB4_1 (b) (b)
|
|
D<0> 5 3<- /\3 0 FB4_2 2 GTS/I/O I/O
|
|
CONFIG_READY 2 0 /\3 0 FB4_3 (b) (b)
|
|
LAN_BASEADR<6> 9 4<- 0 0 FB4_4 (b) (b)
|
|
A_LAN<1> 1 0 /\4 0 FB4_5 3 GTS/I/O O
|
|
A_LAN<0> 1 0 \/4 0 FB4_6 4 I/O O
|
|
LAN_BASEADR<5> 9 4<- 0 0 FB4_7 (b) (b)
|
|
A_LAN<3> 2 0 \/3 0 FB4_8 5 GTS/I/O O
|
|
LAN_BASEADR<3> 9 4<- 0 0 FB4_9 (b) (b)
|
|
LAN_BASEADR<4> 9 5<- /\1 0 FB4_10 (b) (b)
|
|
(unused) 0 0 /\5 0 FB4_11 (b) (b)
|
|
A_LAN<2> 1 0 \/4 0 FB4_12 6 GTS/I/O O
|
|
LAN_BASEADR<2> 9 4<- 0 0 FB4_13 (b) (b)
|
|
A_LAN<5> 1 0 \/4 0 FB4_14 7 I/O O
|
|
LAN_BASEADR<1> 9 4<- 0 0 FB4_15 (b) (b)
|
|
(unused) 0 0 \/5 0 FB4_16 (b) (b)
|
|
D_OUT<5> 12 7<- 0 0 FB4_17 (b) (b)
|
|
D_OUT<4> 11 8<- /\2 0 FB4_18 (b) (b)
|
|
|
|
Signals Used by Logic in Function Block
|
|
1: $OpTx$FX_SC$119__$INT 12: LAN_BASEADR<5> 23: UDS
|
|
2: AUTOCONFIG_ACCESS 13: LAN_BASEADR<6> 24: Z3_ADR<13>
|
|
3: DS0 14: LDS 25: Z3_ADR<2>
|
|
4: DS1 15: D<6>.PIN 26: Z3_ADR<3>
|
|
5: FCS 16: D<5>.PIN 27: Z3_ADR<4>
|
|
6: LAN_ACCESS 17: D<4>.PIN 28: Z3_ADR<5>
|
|
7: LAN_A_INIT<3> 18: D<3>.PIN 29: Z3_ADR<6>
|
|
8: LAN_BASEADR<1> 19: D<2>.PIN 30: Z3_ADR_0
|
|
9: LAN_BASEADR<2> 20: D<1>.PIN 31: Z3_ADR_1
|
|
10: LAN_BASEADR<3> 21: RESET 32: Z3_A_LOW
|
|
11: LAN_BASEADR<4> 22: RW 33: Z3_DATA<16>
|
|
|
|
Signal 1 2 3 4 FB
|
|
Name 0----+----0----+----0----+----0----+----0 Inputs
|
|
D<0> X.XXXX.......X.......XX.........X....... 9
|
|
CONFIG_READY ....XX..............XX.X................ 5
|
|
LAN_BASEADR<6> .XXXX.......XXX.....XXX.XXXXXXX......... 17
|
|
A_LAN<1> ....................X........X.......... 2
|
|
A_LAN<0> ....................X..........X........ 2
|
|
LAN_BASEADR<5> .XXXX......X.X.X....XXX.XXXXXXX......... 17
|
|
A_LAN<3> ......X.............X...X............... 3
|
|
LAN_BASEADR<3> .XXXX....X...X...X..XXX.XXXXXXX......... 17
|
|
LAN_BASEADR<4> .XXXX.....X..X..X...XXX.XXXXXXX......... 17
|
|
A_LAN<2> ....................X.........X......... 2
|
|
LAN_BASEADR<2> .XXXX...X....X....X.XXX.XXXXXXX......... 17
|
|
A_LAN<5> ....................X.....X............. 2
|
|
LAN_BASEADR<1> .XXXX..X.....X.....XXXX.XXXXXXX......... 17
|
|
D_OUT<5> .XXXX........X......X.X.XXXXXXX......... 14
|
|
D_OUT<4> .XXXX........X......X.X.XXXXXXX......... 14
|
|
0----+----1----+----2----+----3----+----4
|
|
0 0 0 0
|
|
*********************************** FB5 ***********************************
|
|
Number of function block inputs used/remaining: 33/21
|
|
Number of signals used by logic mapping into function block: 33
|
|
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
|
Name Pt Pt Pt Pt # Type Use
|
|
AUTO_CONFIG_DONE_CYCLE
|
|
5 3<- /\3 0 FB5_1 (b) (b)
|
|
CP_CS 0 0 /\3 2 FB5_2 34 I/O O
|
|
(unused) 0 0 \/2 3 FB5_3 (b) (b)
|
|
LAN_BASEADR<13> 9 4<- 0 0 FB5_4 (b) (b)
|
|
ROM_OE 0 0 /\2 3 FB5_5 35 I/O O
|
|
(unused) 0 0 \/4 1 FB5_6 (b) (b)
|
|
LAN_BASEADR<14> 9 4<- 0 0 FB5_7 (b) (b)
|
|
LAN_BASEADR<15> 9 4<- 0 0 FB5_8 38 GCK/I/O (b)
|
|
(unused) 0 0 /\4 1 FB5_9 (b) (b)
|
|
D<2> 5 0 0 0 FB5_10 39 I/O I/O
|
|
(unused) 0 0 \/4 1 FB5_11 (b) (b)
|
|
D<9> 9 4<- 0 0 FB5_12 40 I/O I/O
|
|
(unused) 0 0 \/4 1 FB5_13 (b) (b)
|
|
D<10> 9 4<- 0 0 FB5_14 41 I/O I/O
|
|
D<11> 9 4<- 0 0 FB5_15 43 I/O I/O
|
|
(unused) 0 0 /\4 1 FB5_16 (b) (b)
|
|
D<12> 9 4<- 0 0 FB5_17 44 I/O I/O
|
|
$OpTx$FX_DC$118__$INT
|
|
4 3<- /\4 0 FB5_18 (b) (b)
|
|
|
|
Signals Used by Logic in Function Block
|
|
1: $OpTx$FX_SC$119__$INT 12: LAN_BASEADR<13> 23: Z3_ADR<3>
|
|
2: AUTOCONFIG_ACCESS 13: LAN_BASEADR<14> 24: Z3_ADR<4>
|
|
3: AUTO_CONFIG_DONE_CYCLE 14: LAN_BASEADR<15> 25: Z3_ADR<5>
|
|
4: DS0 15: LDS 26: Z3_ADR<6>
|
|
5: DS1 16: D<15>.PIN 27: Z3_ADR_0
|
|
6: D_OUT<1> 17: D<14>.PIN 28: Z3_ADR_1
|
|
7: D_OUT<2> 18: D<13>.PIN 29: Z3_DATA<18>
|
|
8: D_OUT<3> 19: RESET 30: Z3_DATA<25>
|
|
9: D_OUT<4> 20: RW 31: Z3_DATA<26>
|
|
10: FCS 21: UDS 32: Z3_DATA<27>
|
|
11: LAN_ACCESS 22: Z3_ADR<2> 33: Z3_DATA<28>
|
|
|
|
Signal 1 2 3 4 FB
|
|
Name 0----+----0----+----0----+----0----+----0 Inputs
|
|
AUTO_CONFIG_DONE_CYCLE
|
|
.XXXX....X....X...XXXXXXXXX............. 15
|
|
CP_CS ........................................ 0
|
|
LAN_BASEADR<13> .X.XX....X.X..X..XXXXXXXXXXX............ 17
|
|
ROM_OE ........................................ 0
|
|
LAN_BASEADR<14> .X.XX....X..X.X.X.XXXXXXXXXX............ 17
|
|
LAN_BASEADR<15> .X.XX....X...XXX..XXXXXXXXXX............ 17
|
|
D<2> X..XX....XX...X....XX.......X........... 9
|
|
D<9> X..XXX...XX...X....XX........X.......... 10
|
|
D<10> X..XX.X..XX...X....XX.........X......... 10
|
|
D<11> X..XX..X.XX...X....XX..........X........ 10
|
|
D<12> X..XX...XXX...X....XX...........X....... 10
|
|
$OpTx$FX_DC$118__$INT
|
|
...XX....XX...X...XXX................... 8
|
|
0----+----1----+----2----+----3----+----4
|
|
0 0 0 0
|
|
*********************************** FB6 ***********************************
|
|
Number of function block inputs used/remaining: 34/20
|
|
Number of signals used by logic mapping into function block: 34
|
|
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
|
Name Pt Pt Pt Pt # Type Use
|
|
$OpTx$INV$205 16 11<- 0 0 FB6_1 (b) (b)
|
|
LAN_CFG<2> 0 0 /\4 1 FB6_2 135 I/O O
|
|
A_LAN<12> 1 0 0 4 FB6_3 136 I/O O
|
|
(unused) 0 0 0 5 FB6_4 (b)
|
|
A_LAN<13> 1 0 0 4 FB6_5 137 I/O O
|
|
A_LAN<10> 1 0 0 4 FB6_6 138 I/O O
|
|
(unused) 0 0 0 5 FB6_7 (b)
|
|
A_LAN<11> 1 0 0 4 FB6_8 139 I/O O
|
|
N0$BUF7/N0$BUF7_TRST__$INT
|
|
2 0 0 3 FB6_9 (b) (b)
|
|
A_LAN<8> 1 0 0 4 FB6_10 140 I/O O
|
|
Z3_ADR<7> 3 0 0 2 FB6_11 (b) (b)
|
|
Z3_ADR<6> 3 0 0 2 FB6_12 (b) (b)
|
|
Z3_ADR<5> 3 0 0 2 FB6_13 (b) (b)
|
|
A_LAN<9> 1 0 0 4 FB6_14 142 I/O O
|
|
Z3_ADR<4> 3 0 0 2 FB6_15 143 GSR/I/O I
|
|
Z3_ADR<3> 3 0 0 2 FB6_16 (b) (b)
|
|
Z3_ADR<2> 3 0 \/2 0 FB6_17 (b) (b)
|
|
(unused) 0 0 \/5 0 FB6_18 (b) (b)
|
|
|
|
Signals Used by Logic in Function Block
|
|
1: AUTOCONFIG_ACCESS 13: LAN_BASEADR<4> 24: A<20>.PIN
|
|
2: A<4> 14: LAN_BASEADR<5> 25: A<21>.PIN
|
|
3: A<5> 15: LAN_BASEADR<7> 26: A<16>.PIN
|
|
4: A<6> 16: LAN_READY 27: RESET
|
|
5: A<7> 17: A<17>.PIN 28: Z3_ADR<10>
|
|
6: CONFIG_READY 18: A<23>.PIN 29: Z3_ADR<11>
|
|
7: FCS 19: A<18>.PIN 30: Z3_ADR<12>
|
|
8: LAN_BASEADR<0> 20: A<19>.PIN 31: Z3_ADR<7>
|
|
9: LAN_BASEADR<14> 21: A<8>.PIN 32: Z3_ADR<8>
|
|
10: LAN_BASEADR<1> 22: A<9>.PIN 33: Z3_ADR<9>
|
|
11: LAN_BASEADR<2> 23: D<14>.PIN 34: Z3_ADR_1/Z3_ADR_1_SETF__$INT
|
|
12: LAN_BASEADR<3>
|
|
|
|
Signal 1 2 3 4 FB
|
|
Name 0----+----0----+----0----+----0----+----0 Inputs
|
|
$OpTx$INV$205 .......XXXXXXXX.XXXX..XXXX.............. 16
|
|
LAN_CFG<2> ........................................ 0
|
|
A_LAN<12> ..........................X.X........... 2
|
|
A_LAN<13> ..........................X..X.......... 2
|
|
A_LAN<10> ..........................X.....X....... 2
|
|
A_LAN<11> ..........................XX............ 2
|
|
N0$BUF7/N0$BUF7_TRST__$INT
|
|
X....XX........X........................ 4
|
|
A_LAN<8> ..........................X...X......... 2
|
|
Z3_ADR<7> ......X..............X...........X...... 3
|
|
Z3_ADR<6> ......X.............X............X...... 3
|
|
Z3_ADR<5> ....X.X..........................X...... 3
|
|
A_LAN<9> ..........................X....X........ 2
|
|
Z3_ADR<4> ...X..X..........................X...... 3
|
|
Z3_ADR<3> ..X...X..........................X...... 3
|
|
Z3_ADR<2> .X....X..........................X...... 3
|
|
0----+----1----+----2----+----3----+----4
|
|
0 0 0 0
|
|
*********************************** FB7 ***********************************
|
|
Number of function block inputs used/remaining: 29/25
|
|
Number of signals used by logic mapping into function block: 29
|
|
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
|
Name Pt Pt Pt Pt # Type Use
|
|
D_OUT<6> 11 6<- 0 0 FB7_1 (b) (b)
|
|
$OpTx$FX_DC$112 2 2<- /\5 0 FB7_2 (b) (b)
|
|
D<13> 9 6<- /\2 0 FB7_3 45 I/O I/O
|
|
(unused) 0 0 /\5 0 FB7_4 (b) (b)
|
|
D<14> 9 5<- /\1 0 FB7_5 46 I/O I/O
|
|
(unused) 0 0 /\5 0 FB7_6 (b) (b)
|
|
$OpTx$FX_SC$119__$INT
|
|
4 0 \/1 0 FB7_7 (b) (b)
|
|
(unused) 0 0 \/5 0 FB7_8 (b) (b)
|
|
LAN_BASEADR<9> 9 6<- \/2 0 FB7_9 (b) (b)
|
|
(unused) 0 0 \/5 0 FB7_10 (b) (b)
|
|
LAN_BASEADR<8> 9 7<- \/3 0 FB7_11 (b) (b)
|
|
D<15> 9 4<- 0 0 FB7_12 48 I/O I/O
|
|
LAN_BASEADR<7> 9 5<- /\1 0 FB7_13 (b) (b)
|
|
(unused) 0 0 /\5 0 FB7_14 (b) (b)
|
|
(unused) 0 0 \/5 0 FB7_15 49 I/O I
|
|
D_OUT<2> 9 5<- \/1 0 FB7_16 (b) (b)
|
|
(unused) 0 0 \/5 0 FB7_17 (b) (b)
|
|
D_OUT<1> 10 6<- \/1 0 FB7_18 (b) (b)
|
|
|
|
Signals Used by Logic in Function Block
|
|
1: $OpTx$FX_SC$119__$INT 11: LAN_BASEADR<8> 21: Z3_ADR<3>
|
|
2: AUTOCONFIG_ACCESS 12: LAN_BASEADR<9> 22: Z3_ADR<4>
|
|
3: DS0 13: LDS 23: Z3_ADR<5>
|
|
4: DS1 14: D<9>.PIN 24: Z3_ADR<6>
|
|
5: D_OUT<5> 15: D<8>.PIN 25: Z3_ADR_0
|
|
6: D_OUT<6> 16: D<7>.PIN 26: Z3_ADR_1
|
|
7: D_OUT<7> 17: RESET 27: Z3_DATA<29>
|
|
8: FCS 18: RW 28: Z3_DATA<30>
|
|
9: LAN_ACCESS 19: UDS 29: Z3_DATA<31>
|
|
10: LAN_BASEADR<7> 20: Z3_ADR<2>
|
|
|
|
Signal 1 2 3 4 FB
|
|
Name 0----+----0----+----0----+----0----+----0 Inputs
|
|
D_OUT<6> .XXX...X....X...X.XXXXXXXX.............. 14
|
|
$OpTx$FX_DC$112 ..XX...X....X.....X..................... 5
|
|
D<13> X.XXX..XX...X....XX.......X............. 10
|
|
D<14> X.XX.X.XX...X....XX........X............ 10
|
|
$OpTx$FX_SC$119__$INT
|
|
.XXX...XX...X....XX..................... 8
|
|
LAN_BASEADR<9> .XXX...X...XXX..XXXXXXXXXX.............. 17
|
|
LAN_BASEADR<8> .XXX...X..X.X.X.XXXXXXXXXX.............. 17
|
|
D<15> X.XX..XXX...X....XX.........X........... 10
|
|
LAN_BASEADR<7> .XXX...X.X..X..XXXXXXXXXXX.............. 17
|
|
D_OUT<2> .XXX...X....X...X.XXXXX.XX.............. 13
|
|
D_OUT<1> .XXX...X....X...X.XXXXX.XX.............. 13
|
|
0----+----1----+----2----+----3----+----4
|
|
0 0 0 0
|
|
*********************************** FB8 ***********************************
|
|
Number of function block inputs used/remaining: 34/20
|
|
Number of signals used by logic mapping into function block: 34
|
|
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
|
Name Pt Pt Pt Pt # Type Use
|
|
(unused) 0 0 /\5 0 FB8_1 (b) (b)
|
|
DQ<12> 2 0 /\3 0 FB8_2 130 I/O I/O
|
|
DQ<14> 2 0 0 3 FB8_3 131 I/O I/O
|
|
Z3_ADR<13> 3 0 0 2 FB8_4 (b) (b)
|
|
LAN_WRH 3 0 0 2 FB8_5 132 I/O O
|
|
(unused) 0 0 0 5 FB8_6 (b)
|
|
Z3_ADR<12> 3 0 0 2 FB8_7 (b) (b)
|
|
LAN_CS 2 0 0 3 FB8_8 133 I/O O
|
|
Z3_ADR<11> 3 0 0 2 FB8_9 (b) (b)
|
|
LAN_RD 1 0 0 4 FB8_10 134 I/O O
|
|
Z3_ADR<10> 3 0 \/1 1 FB8_11 (b) (b)
|
|
(unused) 0 0 \/5 0 FB8_12 (b) (b)
|
|
LAN_ACCESS 21 16<- 0 0 FB8_13 (b) (b)
|
|
(unused) 0 0 /\5 0 FB8_14 (b) (b)
|
|
(unused) 0 0 /\5 0 FB8_15 (b) (b)
|
|
(unused) 0 0 \/5 0 FB8_16 (b) (b)
|
|
(unused) 0 0 \/5 0 FB8_17 (b) (b)
|
|
DQ_SWAP 23 18<- 0 0 FB8_18 (b) (b)
|
|
|
|
Signals Used by Logic in Function Block
|
|
1: $OpTx$FX_DC$118__$INT 13: LAN_BASEADR<8> 24: D<11>.PIN
|
|
2: $OpTx$INV$205 14: LAN_BASEADR<9> 25: D<10>.PIN
|
|
3: DQ_DATA<12> 15: LAN_CS_RST 26: D<9>.PIN
|
|
4: DQ_DATA<14> 16: LAN_RD_S 27: D<8>.PIN
|
|
5: FCS 17: LAN_WRH_S 28: A<14>.PIN
|
|
6: LAN_ACCESS 18: LAN_WR_RST 29: A<15>.PIN
|
|
7: LAN_BASEADR<10> 19: A<12>.PIN 30: A<22>.PIN
|
|
8: LAN_BASEADR<11> 20: A<13>.PIN 31: RESET
|
|
9: LAN_BASEADR<12> 21: D<15>.PIN 32: SHUT_UP
|
|
10: LAN_BASEADR<13> 22: D<13>.PIN 33: Z3_ADR_1/Z3_ADR_1_SETF__$INT
|
|
11: LAN_BASEADR<15> 23: D<12>.PIN 34: Z3
|
|
12: LAN_BASEADR<6>
|
|
|
|
Signal 1 2 3 4 FB
|
|
Name 0----+----0----+----0----+----0----+----0 Inputs
|
|
DQ<12> X.X...........................X......... 3
|
|
DQ<14> X..X..........................X......... 3
|
|
Z3_ADR<13> ....X.......................X...X....... 3
|
|
LAN_WRH ....X...........XX............X......... 4
|
|
Z3_ADR<12> ....X......................X....X....... 3
|
|
LAN_CS .....X........X...............X......... 3
|
|
Z3_ADR<11> ....X..............X............X....... 3
|
|
LAN_RD ....X..........X..............X......... 3
|
|
Z3_ADR<10> ....X.............X.............X....... 3
|
|
LAN_ACCESS .X..X.XXXXXXXX......XXXXXXX..X.XXX...... 21
|
|
DQ_SWAP .X..X.XXXXXXXX.....XXXXXXXXX.X.XXX...... 23
|
|
0----+----1----+----2----+----3----+----4
|
|
0 0 0 0
|
|
*********************************** FB9 ***********************************
|
|
Number of function block inputs used/remaining: 31/23
|
|
Number of signals used by logic mapping into function block: 31
|
|
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
|
Name Pt Pt Pt Pt # Type Use
|
|
(unused) 0 0 /\5 0 FB9_1 (b) (b)
|
|
(unused) 0 0 /\5 0 FB9_2 50 I/O I
|
|
(unused) 0 0 \/3 2 FB9_3 51 I/O I
|
|
DQ_DATA<7> 13 8<- 0 0 FB9_4 (b) (b)
|
|
(unused) 0 0 /\5 0 FB9_5 52 I/O I
|
|
LAN_SM_FSM_FFd2 5 0 0 0 FB9_6 53 I/O I
|
|
(unused) 0 0 \/5 0 FB9_7 (b) (b)
|
|
LAN_SM_FSM_FFd4 7 5<- \/3 0 FB9_8 54 I/O I
|
|
DQ_DATA<6> 13 8<- 0 0 FB9_9 (b) (b)
|
|
(unused) 0 0 /\5 0 FB9_10 (b) (b)
|
|
A<8> 5 0 0 0 FB9_11 56 I/O I/O
|
|
(unused) 0 0 \/5 0 FB9_12 57 I/O (b)
|
|
Z3_A_LOW 9 5<- \/1 0 FB9_13 (b) (b)
|
|
A<9> 5 1<- \/1 0 FB9_14 58 I/O I/O
|
|
(unused) 0 0 \/5 0 FB9_15 (b) (b)
|
|
DQ_DATA<15> 13 8<- 0 0 FB9_16 (b) (b)
|
|
A<10> 5 2<- /\2 0 FB9_17 59 I/O I/O
|
|
DQ_DATA<14> 13 10<- /\2 0 FB9_18 (b) (b)
|
|
|
|
Signals Used by Logic in Function Block
|
|
1: $OpTx$FX_DC$112 12: LAN_SM_FSM_FFd3 22: DQ<0>.PIN
|
|
2: DQ_DATA<14> 13: LAN_SM_FSM_FFd4 23: D<15>.PIN
|
|
3: DQ_DATA<15> 14: LAN_SM_RST 24: D<14>.PIN
|
|
4: DQ_DATA<6> 15: LDS 25: A<14>.PIN
|
|
5: DQ_DATA<7> 16: A<23>.PIN 26: D<7>.PIN
|
|
6: DQ_SWAP 17: DQ<10>.PIN 27: D<6>.PIN
|
|
7: DS0 18: DQ<9>.PIN 28: A<15>.PIN
|
|
8: DS1 19: DQ<8>.PIN 29: A<22>.PIN
|
|
9: LAN_ACCESS 20: DQ<2>.PIN 30: RW
|
|
10: LAN_SM_FSM_FFd1 21: DQ<1>.PIN 31: UDS
|
|
11: LAN_SM_FSM_FFd2
|
|
|
|
Signal 1 2 3 4 FB
|
|
Name 0----+----0----+----0----+----0----+----0 Inputs
|
|
DQ_DATA<7> ....XX...XXXXXXX......X..X.X..X......... 13
|
|
LAN_SM_FSM_FFd2 .........XXXXXX..............XX......... 8
|
|
LAN_SM_FSM_FFd4 ......XX.XXXXX...............X.......... 8
|
|
DQ_DATA<6> ...X.X...XXXXXX........XX.X.X.X......... 13
|
|
A<8> X....X..XXXXXX....X..X.......X.......... 11
|
|
Z3_A_LOW ......XX.XXXXXX...............X......... 9
|
|
A<9> X....X..XXXXXX...X..X........X.......... 11
|
|
DQ_DATA<15> ..X..X...XXXXXXX......X..X.X..X......... 13
|
|
A<10> X....X..XXXXXX..X..X.........X.......... 11
|
|
DQ_DATA<14> .X...X...XXXXXX........XX.X.X.X......... 13
|
|
0----+----1----+----2----+----3----+----4
|
|
0 0 0 0
|
|
*********************************** FB10 ***********************************
|
|
Number of function block inputs used/remaining: 33/21
|
|
Number of signals used by logic mapping into function block: 33
|
|
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
|
Name Pt Pt Pt Pt # Type Use
|
|
(unused) 0 0 0 5 FB10_1 (b)
|
|
DQ<1> 3 0 0 2 FB10_2 117 I/O I/O
|
|
DQ<0> 2 0 0 3 FB10_3 118 I/O I/O
|
|
(unused) 0 0 0 5 FB10_4 (b)
|
|
DQ<3> 2 0 0 3 FB10_5 119 I/O I/O
|
|
DQ<2> 2 0 0 3 FB10_6 120 I/O I/O
|
|
(unused) 0 0 0 5 FB10_7 (b)
|
|
DQ<5> 2 0 0 3 FB10_8 121 I/O I/O
|
|
LAN_SM_RST 4 0 0 1 FB10_9 (b) (b)
|
|
DQ<4> 3 0 0 2 FB10_10 124 I/O I/O
|
|
DQ<7> 2 0 0 3 FB10_11 125 I/O I/O
|
|
DQ<6> 2 0 0 3 FB10_12 126 I/O I/O
|
|
LAN_INT_ENABLE 5 0 0 0 FB10_13 (b) (b)
|
|
DQ<8> 3 0 0 2 FB10_14 128 I/O I/O
|
|
D_OUT<7> 5 0 0 0 FB10_15 (b) (b)
|
|
D_OUT<3> 5 0 0 0 FB10_16 (b) (b)
|
|
DQ<10> 3 0 0 2 FB10_17 129 I/O I/O
|
|
D_OUT<0> 5 0 0 0 FB10_18 (b) (b)
|
|
|
|
Signals Used by Logic in Function Block
|
|
1: $OpTx$FX_DC$118__$INT 12: DQ_DATA<8> 23: RESET
|
|
2: AUTOCONFIG_ACCESS 13: DS0 24: RW
|
|
3: DQ_DATA<0> 14: DS1 25: UDS
|
|
4: DQ_DATA<10> 15: FCS 26: Z3_ADR<13>
|
|
5: DQ_DATA<1> 16: LAN_ACCESS 27: Z3_ADR<2>
|
|
6: DQ_DATA<2> 17: LAN_D_INIT<1> 28: Z3_ADR<3>
|
|
7: DQ_DATA<3> 18: LAN_D_INIT<8> 29: Z3_ADR<4>
|
|
8: DQ_DATA<4> 19: LAN_INT_ENABLE 30: Z3_ADR<5>
|
|
9: DQ_DATA<5> 20: LDS 31: Z3_ADR<6>
|
|
10: DQ_DATA<6> 21: A<23>.PIN 32: Z3_ADR_0
|
|
11: DQ_DATA<7> 22: D<15>.PIN 33: Z3_ADR_1
|
|
|
|
Signal 1 2 3 4 FB
|
|
Name 0----+----0----+----0----+----0----+----0 Inputs
|
|
DQ<1> X...X...........X.....X................. 4
|
|
DQ<0> X.X...................X................. 3
|
|
DQ<3> X.....X...............X................. 3
|
|
DQ<2> X....X................X................. 3
|
|
DQ<5> X.......X.............X................. 3
|
|
LAN_SM_RST ............XXXX...X..X.XX.............. 8
|
|
DQ<4> X......X........X.....X................. 4
|
|
DQ<7> X.........X...........X................. 3
|
|
DQ<6> X........X............X................. 3
|
|
LAN_INT_ENABLE .............XXX..X.XXXXXX.............. 10
|
|
DQ<8> X..........X.....X....X................. 4
|
|
D_OUT<7> .X..........XXX....X..X.X..XXXX.X....... 12
|
|
D_OUT<3> .X..........XXX....X..X.X..XXX..X....... 11
|
|
DQ<10> X..X.............X....X................. 4
|
|
D_OUT<0> .X..........XXX....X..X.X.XXXX.XX....... 13
|
|
0----+----1----+----2----+----3----+----4
|
|
0 0 0 0
|
|
*********************************** FB11 ***********************************
|
|
Number of function block inputs used/remaining: 30/24
|
|
Number of signals used by logic mapping into function block: 30
|
|
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
|
Name Pt Pt Pt Pt # Type Use
|
|
DQ_DATA<10> 13 8<- 0 0 FB11_1 (b) (b)
|
|
(unused) 0 0 /\3 2 FB11_2 (b) (b)
|
|
A<11> 5 0 0 0 FB11_3 60 I/O I/O
|
|
(unused) 0 0 0 5 FB11_4 (b)
|
|
A<12> 5 0 0 0 FB11_5 61 I/O I/O
|
|
Z3_DATA<30> 4 0 0 1 FB11_6 (b) (b)
|
|
Z3_DATA<29> 4 0 0 1 FB11_7 (b) (b)
|
|
Z3_DATA<22> 4 0 0 1 FB11_8 (b) (b)
|
|
Z3_DATA<21> 4 0 0 1 FB11_9 (b) (b)
|
|
A<13> 5 0 0 0 FB11_10 64 I/O I/O
|
|
A<14> 5 0 0 0 FB11_11 66 I/O I/O
|
|
ROM_B<0> 0 0 \/4 1 FB11_12 68 I/O O
|
|
DQ_DATA<2> 13 8<- 0 0 FB11_13 (b) (b)
|
|
ROM_B<1> 0 0 /\4 1 FB11_14 69 I/O O
|
|
(unused) 0 0 \/4 1 FB11_15 (b) (b)
|
|
DQ_DATA<11> 13 8<- 0 0 FB11_16 (b) (b)
|
|
CP_WE 0 0 /\4 1 FB11_17 70 I/O O
|
|
(unused) 0 0 \/5 0 FB11_18 (b) (b)
|
|
|
|
Signals Used by Logic in Function Block
|
|
1: $OpTx$FX_DC$112 11: LAN_SM_RST 21: DQ<6>.PIN
|
|
2: DQ_DATA<10> 12: LDS 22: DQ<5>.PIN
|
|
3: DQ_DATA<11> 13: A<10>.PIN 23: DQ<4>.PIN
|
|
4: DQ_DATA<2> 14: A<11>.PIN 24: DQ<3>.PIN
|
|
5: DQ_SWAP 15: A<18>.PIN 25: D<11>.PIN
|
|
6: LAN_ACCESS 16: A<19>.PIN 26: D<10>.PIN
|
|
7: LAN_SM_FSM_FFd1 17: DQ<14>.PIN 27: D<3>.PIN
|
|
8: LAN_SM_FSM_FFd2 18: DQ<13>.PIN 28: D<2>.PIN
|
|
9: LAN_SM_FSM_FFd3 19: DQ<12>.PIN 29: RW
|
|
10: LAN_SM_FSM_FFd4 20: DQ<11>.PIN 30: UDS
|
|
|
|
Signal 1 2 3 4 FB
|
|
Name 0----+----0----+----0----+----0----+----0 Inputs
|
|
DQ_DATA<10> .X..X.XXXXXXX.X..........X.X.X.......... 13
|
|
A<11> X...XXXXXXX........X...X....X........... 11
|
|
A<12> X...XXXXXXX.......X...X.....X........... 11
|
|
Z3_DATA<30> ....X.XXXXX.....X...X................... 8
|
|
Z3_DATA<29> ....X.XXXXX......X...X.................. 8
|
|
Z3_DATA<22> ....X.XXXXX.....X...X................... 8
|
|
Z3_DATA<21> ....X.XXXXX......X...X.................. 8
|
|
A<13> X...XXXXXXX......X...X......X........... 11
|
|
A<14> X...XXXXXXX.....X...X.......X........... 11
|
|
ROM_B<0> ........................................ 0
|
|
DQ_DATA<2> ...XX.XXXXXXX.X..........X.X.X.......... 13
|
|
ROM_B<1> ........................................ 0
|
|
DQ_DATA<11> ..X.X.XXXXXX.X.X........X.X..X.......... 13
|
|
CP_WE ........................................ 0
|
|
0----+----1----+----2----+----3----+----4
|
|
0 0 0 0
|
|
*********************************** FB12 ***********************************
|
|
Number of function block inputs used/remaining: 33/21
|
|
Number of signals used by logic mapping into function block: 33
|
|
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
|
Name Pt Pt Pt Pt # Type Use
|
|
(unused) 0 0 0 5 FB12_1 (b)
|
|
LAN_CFG<4> 0 0 0 5 FB12_2 110 I/O O
|
|
(unused) 0 0 0 5 FB12_3 111 I/O I
|
|
(unused) 0 0 0 5 FB12_4 (b)
|
|
DQ<15> 2 0 0 3 FB12_5 112 I/O I/O
|
|
(unused) 0 0 0 5 FB12_6 (b)
|
|
(unused) 0 0 0 5 FB12_7 (b)
|
|
DQ<13> 2 0 0 3 FB12_8 113 I/O I/O
|
|
(unused) 0 0 0 5 FB12_9 (b)
|
|
DQ<11> 3 0 0 2 FB12_10 115 I/O I/O
|
|
(unused) 0 0 0 5 FB12_11 (b)
|
|
DQ<9> 3 0 0 2 FB12_12 116 I/O I/O
|
|
Z3_ADR_1/Z3_ADR_1_SETF__$INT
|
|
1 0 0 4 FB12_13 (b) (b)
|
|
LAN_WR_RST 2 0 0 3 FB12_14 (b) (b)
|
|
LAN_D_INIT<8> 2 0 0 3 FB12_15 (b) (b)
|
|
LAN_D_INIT<1> 2 0 0 3 FB12_16 (b) (b)
|
|
LAN_A_INIT<6> 2 0 0 3 FB12_17 (b) (b)
|
|
AUTOCONFIG_ACCESS 3 0 0 2 FB12_18 (b) (b)
|
|
|
|
Signals Used by Logic in Function Block
|
|
1: $OpTx$FX_DC$118__$INT 12: LAN_RST_SM_FSM_FFd1 23: D<11>.PIN
|
|
2: BERR 13: LAN_RST_SM_FSM_FFd2 24: D<10>.PIN
|
|
3: CFIN 14: LAN_RST_SM_FSM_FFd3 25: D<9>.PIN
|
|
4: CFOUT 15: A<17>.PIN 26: D<8>.PIN
|
|
5: DQ_DATA<11> 16: A<23>.PIN 27: A<20>.PIN
|
|
6: DQ_DATA<13> 17: A<18>.PIN 28: A<21>.PIN
|
|
7: DQ_DATA<15> 18: A<19>.PIN 29: A<16>.PIN
|
|
8: DQ_DATA<9> 19: D<15>.PIN 30: A<22>.PIN
|
|
9: FCS 20: D<14>.PIN 31: RESET
|
|
10: LAN_D_INIT<1> 21: D<13>.PIN 32: Z3_ADR_1/Z3_ADR_1_SETF__$INT
|
|
11: LAN_D_INIT<8> 22: D<12>.PIN 33: Z3
|
|
|
|
Signal 1 2 3 4 FB
|
|
Name 0----+----0----+----0----+----0----+----0 Inputs
|
|
LAN_CFG<4> ........................................ 0
|
|
DQ<15> X.....X.......................X......... 3
|
|
DQ<13> X....X........................X......... 3
|
|
DQ<11> X...X.....X...................X......... 4
|
|
DQ<9> X......X.X....................X......... 4
|
|
Z3_ADR_1/Z3_ADR_1_SETF__$INT
|
|
.X............................X......... 2
|
|
LAN_WR_RST ............XX................X......... 3
|
|
LAN_D_INIT<8> ...........X..................X......... 2
|
|
LAN_D_INIT<1> ...........X..................X......... 2
|
|
LAN_A_INIT<6> ...........X..................X......... 2
|
|
AUTOCONFIG_ACCESS ..XX....X.....XXXXXXXXXXXXXXXX.XX....... 21
|
|
0----+----1----+----2----+----3----+----4
|
|
0 0 0 0
|
|
*********************************** FB13 ***********************************
|
|
Number of function block inputs used/remaining: 33/21
|
|
Number of signals used by logic mapping into function block: 33
|
|
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
|
Name Pt Pt Pt Pt # Type Use
|
|
DQ_DATA<1> 13 8<- 0 0 FB13_1 (b) (b)
|
|
CP_RD 0 0 /\4 1 FB13_2 71 I/O O
|
|
(unused) 0 0 0 5 FB13_3 (b)
|
|
(unused) 0 0 0 5 FB13_4 (b)
|
|
(unused) 0 0 \/3 2 FB13_5 (b) (b)
|
|
DQ_DATA<3> 13 8<- 0 0 FB13_6 (b) (b)
|
|
(unused) 0 0 /\5 0 FB13_7 (b) (b)
|
|
A<15> 5 0 0 0 FB13_8 74 I/O I/O
|
|
(unused) 0 0 0 5 FB13_9 (b)
|
|
(unused) 0 0 0 5 FB13_10 (b)
|
|
(unused) 0 0 \/3 2 FB13_11 75 I/O I
|
|
DQ_DATA<8> 13 8<- 0 0 FB13_12 (b) (b)
|
|
(unused) 0 0 /\5 0 FB13_13 (b) (b)
|
|
LAN_WRL 3 0 \/2 0 FB13_14 76 I/O O
|
|
LAN_RD_S 4 2<- \/3 0 FB13_15 77 I/O I
|
|
DQ_DATA<9> 13 8<- 0 0 FB13_16 (b) (b)
|
|
(unused) 0 0 /\5 0 FB13_17 78 I/O I
|
|
LAN_A_INIT<3> 1 0 \/4 0 FB13_18 (b) (b)
|
|
|
|
Signals Used by Logic in Function Block
|
|
1: $OpTx$FX_DC$112 12: LAN_SM_FSM_FFd4 23: DQ<7>.PIN
|
|
2: DQ_DATA<1> 13: LAN_SM_RST 24: D<11>.PIN
|
|
3: DQ_DATA<3> 14: LAN_WRL_S 25: D<9>.PIN
|
|
4: DQ_DATA<8> 15: LAN_WR_RST 26: D<8>.PIN
|
|
5: DQ_DATA<9> 16: LDS 27: D<3>.PIN
|
|
6: DQ_SWAP 17: A<11>.PIN 28: D<1>.PIN
|
|
7: FCS 18: A<17>.PIN 29: D<0>.PIN
|
|
8: LAN_ACCESS 19: A<19>.PIN 30: A<16>.PIN
|
|
9: LAN_SM_FSM_FFd1 20: A<8>.PIN 31: RESET
|
|
10: LAN_SM_FSM_FFd2 21: A<9>.PIN 32: RW
|
|
11: LAN_SM_FSM_FFd3 22: DQ<15>.PIN 33: UDS
|
|
|
|
Signal 1 2 3 4 FB
|
|
Name 0----+----0----+----0----+----0----+----0 Inputs
|
|
DQ_DATA<1> .X...X..XXXXX..X.X..X...X..X....X....... 13
|
|
CP_RD ........................................ 0
|
|
DQ_DATA<3> ..X..X..XXXXX..XX.X....X..X.....X....... 13
|
|
A<15> X....X.XXXXXX........XX........X........ 11
|
|
DQ_DATA<8> ...X.X..XXXXX..X...X.....X..XX..X....... 13
|
|
LAN_WRL ......X......XX...............X......... 4
|
|
LAN_RD_S ........XXXXX..................X........ 6
|
|
DQ_DATA<9> ....XX..XXXXX..X.X..X...X..X....X....... 13
|
|
LAN_A_INIT<3> ..............................X......... 1
|
|
0----+----1----+----2----+----3----+----4
|
|
0 0 0 0
|
|
*********************************** FB14 ***********************************
|
|
Number of function block inputs used/remaining: 11/43
|
|
Number of signals used by logic mapping into function block: 11
|
|
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
|
Name Pt Pt Pt Pt # Type Use
|
|
(unused) 0 0 0 5 FB14_1 (b)
|
|
(unused) 0 0 0 5 FB14_2 (b)
|
|
OVR 0 0 0 5 FB14_3 100 I/O O
|
|
(unused) 0 0 0 5 FB14_4 (b)
|
|
(unused) 0 0 0 5 FB14_5 101 I/O
|
|
(unused) 0 0 0 5 FB14_6 102 I/O
|
|
(unused) 0 0 0 5 FB14_7 (b)
|
|
(unused) 0 0 0 5 FB14_8 103 I/O
|
|
(unused) 0 0 0 5 FB14_9 (b)
|
|
(unused) 0 0 0 5 FB14_10 104 I/O I
|
|
CFOUT 3 0 0 2 FB14_11 105 I/O O
|
|
(unused) 0 0 0 5 FB14_12 (b)
|
|
Z3_ADR_1 3 0 0 2 FB14_13 (b) (b)
|
|
SLAVE 2 0 0 3 FB14_14 106 I/O O
|
|
OWN 0 0 0 5 FB14_15 107 I/O O
|
|
Z3_ADR_0 3 0 0 2 FB14_16 (b) (b)
|
|
Z3_ADR<9> 3 0 0 2 FB14_17 (b) (b)
|
|
Z3_ADR<8> 3 0 0 2 FB14_18 (b) (b)
|
|
|
|
Signals Used by Logic in Function Block
|
|
1: AUTOBOOT_OFF 5: A<3> 9: A<11>.PIN
|
|
2: AUTOCONFIG_ACCESS 6: FCS 10: RESET
|
|
3: AUTO_CONFIG_DONE_CYCLE 7: LAN_ACCESS 11: Z3_ADR_1/Z3_ADR_1_SETF__$INT
|
|
4: A<2> 8: A<10>.PIN
|
|
|
|
Signal 1 2 3 4 FB
|
|
Name 0----+----0----+----0----+----0----+----0 Inputs
|
|
OVR ........................................ 0
|
|
CFOUT X.X..X...X.............................. 4
|
|
Z3_ADR_1 ....XX....X............................. 3
|
|
SLAVE .X...XX................................. 3
|
|
OWN ........................................ 0
|
|
Z3_ADR_0 ...X.X....X............................. 3
|
|
Z3_ADR<9> .....X..X.X............................. 3
|
|
Z3_ADR<8> .....X.X..X............................. 3
|
|
0----+----1----+----2----+----3----+----4
|
|
0 0 0 0
|
|
*********************************** FB15 ***********************************
|
|
Number of function block inputs used/remaining: 32/22
|
|
Number of signals used by logic mapping into function block: 32
|
|
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
|
Name Pt Pt Pt Pt # Type Use
|
|
DQ_DATA<12> 13 8<- 0 0 FB15_1 (b) (b)
|
|
LAN_SM_FSM_FFd3 7 5<- /\3 0 FB15_2 79 I/O I
|
|
(unused) 0 0 /\5 0 FB15_3 80 I/O (b)
|
|
Z3_DATA<31> 4 0 \/1 0 FB15_4 (b) (b)
|
|
(unused) 0 0 \/5 0 FB15_5 (b) (b)
|
|
DQ_DATA<4> 13 8<- 0 0 FB15_6 (b) (b)
|
|
DQ_DATA<5> 13 10<- /\2 0 FB15_7 (b) (b)
|
|
(unused) 0 0 /\5 0 FB15_8 81 I/O I
|
|
(unused) 0 0 /\5 0 FB15_9 (b) (b)
|
|
(unused) 0 0 \/4 1 FB15_10 82 I/O I
|
|
DQ_DATA<13> 13 8<- 0 0 FB15_11 83 I/O I
|
|
DTACK 1 0 /\4 0 FB15_12 85 I/O O
|
|
Z3_DATA<23> 4 0 0 1 FB15_13 (b) (b)
|
|
A<23> 5 0 0 0 FB15_14 86 I/O I/O
|
|
A<22> 5 0 0 0 FB15_15 87 I/O I/O
|
|
(unused) 0 0 0 5 FB15_16 (b)
|
|
A<21> 5 0 0 0 FB15_17 88 I/O I/O
|
|
(unused) 0 0 \/5 0 FB15_18 (b) (b)
|
|
|
|
Signals Used by Logic in Function Block
|
|
1: $OpTx$FX_DC$112 12: LAN_SM_FSM_FFd3 23: DQ<5>.PIN
|
|
2: DQ_DATA<12> 13: LAN_SM_FSM_FFd4 24: A<13>.PIN
|
|
3: DQ_DATA<13> 14: LAN_SM_RST 25: D<13>.PIN
|
|
4: DQ_DATA<4> 15: LDS 26: D<12>.PIN
|
|
5: DQ_DATA<5> 16: N0$BUF7/N0$BUF7_TRST__$INT 27: D<5>.PIN
|
|
6: DQ_SWAP 17: DQ<15>.PIN 28: D<4>.PIN
|
|
7: DS0 18: DQ<14>.PIN 29: A<20>.PIN
|
|
8: DS1 19: DQ<13>.PIN 30: A<21>.PIN
|
|
9: LAN_ACCESS 20: A<12>.PIN 31: RW
|
|
10: LAN_SM_FSM_FFd1 21: DQ<7>.PIN 32: UDS
|
|
11: LAN_SM_FSM_FFd2 22: DQ<6>.PIN
|
|
|
|
Signal 1 2 3 4 FB
|
|
Name 0----+----0----+----0----+----0----+----0 Inputs
|
|
DQ_DATA<12> .X...X...XXXXXX....X.....X.XX..X........ 13
|
|
LAN_SM_FSM_FFd3 ......XX.XXXXXX...............XX........ 10
|
|
Z3_DATA<31> .....X...XXXXX..X...X................... 8
|
|
DQ_DATA<4> ...X.X...XXXXXX....X.....X.XX..X........ 13
|
|
DQ_DATA<5> ....XX...XXXXXX........XX.X..X.X........ 13
|
|
DQ_DATA<13> ..X..X...XXXXXX........XX.X..X.X........ 13
|
|
DTACK ...............X........................ 1
|
|
Z3_DATA<23> .....X...XXXXX..X...X................... 8
|
|
A<23> X....X..XXXXXX..X...X.........X......... 11
|
|
A<22> X....X..XXXXXX...X...X........X......... 11
|
|
A<21> X....X..XXXXXX....X...X.......X......... 11
|
|
0----+----1----+----2----+----3----+----4
|
|
0 0 0 0
|
|
*********************************** FB16 ***********************************
|
|
Number of function block inputs used/remaining: 26/28
|
|
Number of signals used by logic mapping into function block: 26
|
|
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
|
Name Pt Pt Pt Pt # Type Use
|
|
Z3_DATA<28> 4 0 0 1 FB16_1 (b) (b)
|
|
A<20> 5 0 0 0 FB16_2 91 I/O I/O
|
|
A<19> 5 0 0 0 FB16_3 92 I/O I/O
|
|
Z3_DATA<27> 4 0 0 1 FB16_4 (b) (b)
|
|
Z3_DATA<26> 4 0 0 1 FB16_5 93 I/O I
|
|
A<18> 5 0 0 0 FB16_6 94 I/O I/O
|
|
Z3_DATA<25> 4 0 0 1 FB16_7 (b) (b)
|
|
A<17> 5 0 0 0 FB16_8 95 I/O I/O
|
|
Z3_DATA<24> 4 0 0 1 FB16_9 (b) (b)
|
|
MTACK 0 0 0 5 FB16_10 96 I/O O
|
|
A<16> 5 0 0 0 FB16_11 97 I/O I/O
|
|
Z3_DATA<19> 4 0 0 1 FB16_12 98 I/O I
|
|
Z3_DATA<18> 4 0 0 1 FB16_13 (b) (b)
|
|
Z3_DATA<17> 4 0 \/1 0 FB16_14 (b) (b)
|
|
Z3_DATA<16> 4 1<- \/2 0 FB16_15 (b) (b)
|
|
DQ_DATA<0> 13 8<- 0 0 FB16_16 (b) (b)
|
|
(unused) 0 0 /\5 0 FB16_17 (b) (b)
|
|
Z3_DATA<20> 4 0 /\1 0 FB16_18 (b) (b)
|
|
|
|
Signals Used by Logic in Function Block
|
|
1: $OpTx$FX_DC$112 10: LDS 19: DQ<2>.PIN
|
|
2: DQ_DATA<0> 11: A<8>.PIN 20: DQ<1>.PIN
|
|
3: DQ_SWAP 12: DQ<12>.PIN 21: DQ<0>.PIN
|
|
4: LAN_ACCESS 13: DQ<11>.PIN 22: D<8>.PIN
|
|
5: LAN_SM_FSM_FFd1 14: DQ<10>.PIN 23: D<0>.PIN
|
|
6: LAN_SM_FSM_FFd2 15: DQ<9>.PIN 24: A<16>.PIN
|
|
7: LAN_SM_FSM_FFd3 16: DQ<8>.PIN 25: RW
|
|
8: LAN_SM_FSM_FFd4 17: DQ<4>.PIN 26: UDS
|
|
9: LAN_SM_RST 18: DQ<3>.PIN
|
|
|
|
Signal 1 2 3 4 FB
|
|
Name 0----+----0----+----0----+----0----+----0 Inputs
|
|
Z3_DATA<28> ..X.XXXXX..X....X....................... 8
|
|
A<20> X.XXXXXXX..X....X.......X............... 11
|
|
A<19> X.XXXXXXX...X....X......X............... 11
|
|
Z3_DATA<27> ..X.XXXXX...X....X...................... 8
|
|
Z3_DATA<26> ..X.XXXXX....X....X..................... 8
|
|
A<18> X.XXXXXXX....X....X.....X............... 11
|
|
Z3_DATA<25> ..X.XXXXX.....X....X.................... 8
|
|
A<17> X.XXXXXXX.....X....X....X............... 11
|
|
Z3_DATA<24> ..X.XXXXX......X....X................... 8
|
|
MTACK ........................................ 0
|
|
A<16> X.XXXXXXX......X....X...X............... 11
|
|
Z3_DATA<19> ..X.XXXXX...X....X...................... 8
|
|
Z3_DATA<18> ..X.XXXXX....X....X..................... 8
|
|
Z3_DATA<17> ..X.XXXXX.....X....X.................... 8
|
|
Z3_DATA<16> ..X.XXXXX......X....X................... 8
|
|
DQ_DATA<0> .XX.XXXXXXX..........XXX.X.............. 13
|
|
Z3_DATA<20> ..X.XXXXX..X....X....................... 8
|
|
0----+----1----+----2----+----3----+----4
|
|
0 0 0 0
|
|
******************************* Equations ********************************
|
|
|
|
********** Mapped Logic **********
|
|
|
|
|
|
$OpTx$FX_DC$112 <= ((FCS)
|
|
OR (UDS AND LDS AND DS1 AND DS0));
|
|
|
|
|
|
$OpTx$FX_DC$118__$INT <= ((RW AND RESET)
|
|
OR (RESET AND NOT LAN_ACCESS)
|
|
OR (UDS AND LDS AND DS1 AND DS0 AND RESET)
|
|
OR (FCS AND RESET));
|
|
|
|
|
|
$OpTx$FX_SC$119__$INT <= ((NOT RW)
|
|
OR (FCS)
|
|
OR (NOT LAN_ACCESS AND NOT AUTOCONFIG_ACCESS)
|
|
OR (UDS AND LDS AND DS1 AND DS0));
|
|
|
|
|
|
$OpTx$INV$205 <= ((A(20).PIN AND NOT LAN_BASEADR(4))
|
|
OR (NOT A(20).PIN AND LAN_BASEADR(4))
|
|
OR (A(16).PIN AND NOT LAN_BASEADR(0))
|
|
OR (NOT A(16).PIN AND LAN_BASEADR(0))
|
|
OR (Z3_ADR(2).EXP)
|
|
OR (D(14).PIN AND NOT LAN_BASEADR(14))
|
|
OR (NOT D(14).PIN AND LAN_BASEADR(14))
|
|
OR (A(18).PIN AND NOT LAN_BASEADR(2))
|
|
OR (NOT A(18).PIN AND LAN_BASEADR(2))
|
|
OR (LAN_BASEADR(7) AND NOT A(23).PIN)
|
|
OR (A(17).PIN AND NOT LAN_BASEADR(1))
|
|
OR (NOT A(17).PIN AND LAN_BASEADR(1))
|
|
OR (LAN_BASEADR(5) AND NOT A(21).PIN)
|
|
OR (NOT LAN_BASEADR(5) AND A(21).PIN)
|
|
OR (NOT LAN_BASEADR(7) AND A(23).PIN));
|
|
|
|
FDCPE_A8: FDCPE port map (A_I(8),A(8),CLK_EXT,'0',LAN_SM_RST,A_CE(8));
|
|
A(8) <= ((DQ_SWAP AND DQ(8).PIN)
|
|
OR (NOT DQ_SWAP AND DQ(0).PIN));
|
|
A_CE(8) <= (NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
|
|
NOT LAN_SM_FSM_FFd1 AND NOT LAN_SM_FSM_FFd3);
|
|
A(8) <= A_I(8) when A_OE(8) = '1' else 'Z';
|
|
A_OE(8) <= (RW AND LAN_ACCESS AND NOT $OpTx$FX_DC$112);
|
|
|
|
FDCPE_A9: FDCPE port map (A_I(9),A(9),CLK_EXT,'0',LAN_SM_RST,A_CE(9));
|
|
A(9) <= ((DQ_SWAP AND DQ(9).PIN)
|
|
OR (NOT DQ_SWAP AND DQ(1).PIN));
|
|
A_CE(9) <= (NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
|
|
NOT LAN_SM_FSM_FFd1 AND NOT LAN_SM_FSM_FFd3);
|
|
A(9) <= A_I(9) when A_OE(9) = '1' else 'Z';
|
|
A_OE(9) <= (RW AND LAN_ACCESS AND NOT $OpTx$FX_DC$112);
|
|
|
|
FDCPE_A10: FDCPE port map (A_I(10),A(10),CLK_EXT,'0',LAN_SM_RST,A_CE(10));
|
|
A(10) <= ((DQ_SWAP AND DQ(10).PIN)
|
|
OR (NOT DQ_SWAP AND DQ(2).PIN));
|
|
A_CE(10) <= (NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
|
|
NOT LAN_SM_FSM_FFd1 AND NOT LAN_SM_FSM_FFd3);
|
|
A(10) <= A_I(10) when A_OE(10) = '1' else 'Z';
|
|
A_OE(10) <= (RW AND LAN_ACCESS AND NOT $OpTx$FX_DC$112);
|
|
|
|
FDCPE_A11: FDCPE port map (A_I(11),A(11),CLK_EXT,'0',LAN_SM_RST,A_CE(11));
|
|
A(11) <= ((DQ_SWAP AND DQ(11).PIN)
|
|
OR (NOT DQ_SWAP AND DQ(3).PIN));
|
|
A_CE(11) <= (NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
|
|
NOT LAN_SM_FSM_FFd1 AND NOT LAN_SM_FSM_FFd3);
|
|
A(11) <= A_I(11) when A_OE(11) = '1' else 'Z';
|
|
A_OE(11) <= (RW AND LAN_ACCESS AND NOT $OpTx$FX_DC$112);
|
|
|
|
FDCPE_A12: FDCPE port map (A_I(12),A(12),CLK_EXT,'0',LAN_SM_RST,A_CE(12));
|
|
A(12) <= ((DQ_SWAP AND DQ(12).PIN)
|
|
OR (NOT DQ_SWAP AND DQ(4).PIN));
|
|
A_CE(12) <= (NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
|
|
NOT LAN_SM_FSM_FFd1 AND NOT LAN_SM_FSM_FFd3);
|
|
A(12) <= A_I(12) when A_OE(12) = '1' else 'Z';
|
|
A_OE(12) <= (RW AND LAN_ACCESS AND NOT $OpTx$FX_DC$112);
|
|
|
|
FDCPE_A13: FDCPE port map (A_I(13),A(13),CLK_EXT,'0',LAN_SM_RST,A_CE(13));
|
|
A(13) <= ((DQ_SWAP AND DQ(13).PIN)
|
|
OR (NOT DQ_SWAP AND DQ(5).PIN));
|
|
A_CE(13) <= (NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
|
|
NOT LAN_SM_FSM_FFd1 AND NOT LAN_SM_FSM_FFd3);
|
|
A(13) <= A_I(13) when A_OE(13) = '1' else 'Z';
|
|
A_OE(13) <= (RW AND LAN_ACCESS AND NOT $OpTx$FX_DC$112);
|
|
|
|
FDCPE_A14: FDCPE port map (A_I(14),A(14),CLK_EXT,'0',LAN_SM_RST,A_CE(14));
|
|
A(14) <= ((DQ_SWAP AND DQ(14).PIN)
|
|
OR (NOT DQ_SWAP AND DQ(6).PIN));
|
|
A_CE(14) <= (NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
|
|
NOT LAN_SM_FSM_FFd1 AND NOT LAN_SM_FSM_FFd3);
|
|
A(14) <= A_I(14) when A_OE(14) = '1' else 'Z';
|
|
A_OE(14) <= (RW AND LAN_ACCESS AND NOT $OpTx$FX_DC$112);
|
|
|
|
FDCPE_A15: FDCPE port map (A_I(15),A(15),CLK_EXT,'0',LAN_SM_RST,A_CE(15));
|
|
A(15) <= ((DQ_SWAP AND DQ(15).PIN)
|
|
OR (NOT DQ_SWAP AND DQ(7).PIN));
|
|
A_CE(15) <= (NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
|
|
NOT LAN_SM_FSM_FFd1 AND NOT LAN_SM_FSM_FFd3);
|
|
A(15) <= A_I(15) when A_OE(15) = '1' else 'Z';
|
|
A_OE(15) <= (RW AND LAN_ACCESS AND NOT $OpTx$FX_DC$112);
|
|
|
|
FDCPE_A16: FDCPE port map (A_I(16),A(16),CLK_EXT,'0',LAN_SM_RST,A_CE(16));
|
|
A(16) <= ((DQ_SWAP AND DQ(0).PIN)
|
|
OR (NOT DQ_SWAP AND DQ(8).PIN));
|
|
A_CE(16) <= (NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
|
|
NOT LAN_SM_FSM_FFd1 AND NOT LAN_SM_FSM_FFd3);
|
|
A(16) <= A_I(16) when A_OE(16) = '1' else 'Z';
|
|
A_OE(16) <= (RW AND LAN_ACCESS AND NOT $OpTx$FX_DC$112);
|
|
|
|
FDCPE_A17: FDCPE port map (A_I(17),A(17),CLK_EXT,'0',LAN_SM_RST,A_CE(17));
|
|
A(17) <= ((DQ_SWAP AND DQ(1).PIN)
|
|
OR (NOT DQ_SWAP AND DQ(9).PIN));
|
|
A_CE(17) <= (NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
|
|
NOT LAN_SM_FSM_FFd1 AND NOT LAN_SM_FSM_FFd3);
|
|
A(17) <= A_I(17) when A_OE(17) = '1' else 'Z';
|
|
A_OE(17) <= (RW AND LAN_ACCESS AND NOT $OpTx$FX_DC$112);
|
|
|
|
FDCPE_A18: FDCPE port map (A_I(18),A(18),CLK_EXT,'0',LAN_SM_RST,A_CE(18));
|
|
A(18) <= ((DQ_SWAP AND DQ(2).PIN)
|
|
OR (NOT DQ_SWAP AND DQ(10).PIN));
|
|
A_CE(18) <= (NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
|
|
NOT LAN_SM_FSM_FFd1 AND NOT LAN_SM_FSM_FFd3);
|
|
A(18) <= A_I(18) when A_OE(18) = '1' else 'Z';
|
|
A_OE(18) <= (RW AND LAN_ACCESS AND NOT $OpTx$FX_DC$112);
|
|
|
|
FDCPE_A19: FDCPE port map (A_I(19),A(19),CLK_EXT,'0',LAN_SM_RST,A_CE(19));
|
|
A(19) <= ((DQ_SWAP AND DQ(3).PIN)
|
|
OR (NOT DQ_SWAP AND DQ(11).PIN));
|
|
A_CE(19) <= (NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
|
|
NOT LAN_SM_FSM_FFd1 AND NOT LAN_SM_FSM_FFd3);
|
|
A(19) <= A_I(19) when A_OE(19) = '1' else 'Z';
|
|
A_OE(19) <= (RW AND LAN_ACCESS AND NOT $OpTx$FX_DC$112);
|
|
|
|
FDCPE_A20: FDCPE port map (A_I(20),A(20),CLK_EXT,'0',LAN_SM_RST,A_CE(20));
|
|
A(20) <= ((DQ_SWAP AND DQ(4).PIN)
|
|
OR (NOT DQ_SWAP AND DQ(12).PIN));
|
|
A_CE(20) <= (NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
|
|
NOT LAN_SM_FSM_FFd1 AND NOT LAN_SM_FSM_FFd3);
|
|
A(20) <= A_I(20) when A_OE(20) = '1' else 'Z';
|
|
A_OE(20) <= (RW AND LAN_ACCESS AND NOT $OpTx$FX_DC$112);
|
|
|
|
FDCPE_A21: FDCPE port map (A_I(21),A(21),CLK_EXT,'0',LAN_SM_RST,A_CE(21));
|
|
A(21) <= ((DQ_SWAP AND DQ(5).PIN)
|
|
OR (NOT DQ_SWAP AND DQ(13).PIN));
|
|
A_CE(21) <= (NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
|
|
NOT LAN_SM_FSM_FFd1 AND NOT LAN_SM_FSM_FFd3);
|
|
A(21) <= A_I(21) when A_OE(21) = '1' else 'Z';
|
|
A_OE(21) <= (RW AND LAN_ACCESS AND NOT $OpTx$FX_DC$112);
|
|
|
|
FDCPE_A22: FDCPE port map (A_I(22),A(22),CLK_EXT,'0',LAN_SM_RST,A_CE(22));
|
|
A(22) <= ((DQ_SWAP AND DQ(6).PIN)
|
|
OR (NOT DQ_SWAP AND DQ(14).PIN));
|
|
A_CE(22) <= (NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
|
|
NOT LAN_SM_FSM_FFd1 AND NOT LAN_SM_FSM_FFd3);
|
|
A(22) <= A_I(22) when A_OE(22) = '1' else 'Z';
|
|
A_OE(22) <= (RW AND LAN_ACCESS AND NOT $OpTx$FX_DC$112);
|
|
|
|
FDCPE_A23: FDCPE port map (A_I(23),A(23),CLK_EXT,'0',LAN_SM_RST,A_CE(23));
|
|
A(23) <= ((DQ_SWAP AND DQ(7).PIN)
|
|
OR (NOT DQ_SWAP AND DQ(15).PIN));
|
|
A_CE(23) <= (NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
|
|
NOT LAN_SM_FSM_FFd1 AND NOT LAN_SM_FSM_FFd3);
|
|
A(23) <= A_I(23) when A_OE(23) = '1' else 'Z';
|
|
A_OE(23) <= (RW AND LAN_ACCESS AND NOT $OpTx$FX_DC$112);
|
|
|
|
FDCPE_AUTOCONFIG_ACCESS: FDCPE port map (AUTOCONFIG_ACCESS,AUTOCONFIG_ACCESS_D,NOT FCS,NOT Z3_ADR_1/Z3_ADR_1_SETF__$INT,'0');
|
|
AUTOCONFIG_ACCESS_D <= (Z3 AND D(9).PIN AND D(8).PIN AND D(14).PIN AND
|
|
D(13).PIN AND D(12).PIN AND D(11).PIN AND D(10).PIN AND D(15).PIN AND
|
|
NOT CFIN AND NOT A(20).PIN AND NOT A(19).PIN AND NOT A(18).PIN AND NOT A(17).PIN AND
|
|
NOT A(16).PIN AND NOT A(23).PIN AND NOT A(22).PIN AND NOT A(21).PIN AND CFOUT);
|
|
|
|
FTCPE_AUTO_CONFIG_DONE_CYCLE: FTCPE port map (AUTO_CONFIG_DONE_CYCLE,AUTO_CONFIG_DONE_CYCLE_T,CLK_EXT,NOT RESET,'0');
|
|
AUTO_CONFIG_DONE_CYCLE_T <= ((NOT RW AND NOT FCS AND NOT UDS AND NOT AUTO_CONFIG_DONE_CYCLE AND
|
|
NOT Z3_ADR(2) AND Z3_ADR_0 AND NOT Z3_ADR(6) AND AUTOCONFIG_ACCESS AND
|
|
NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
|
|
OR (NOT RW AND NOT FCS AND NOT LDS AND NOT AUTO_CONFIG_DONE_CYCLE AND
|
|
NOT Z3_ADR(2) AND Z3_ADR_0 AND NOT Z3_ADR(6) AND AUTOCONFIG_ACCESS AND
|
|
NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
|
|
OR (NOT RW AND NOT FCS AND NOT DS0 AND NOT AUTO_CONFIG_DONE_CYCLE AND
|
|
NOT Z3_ADR(2) AND Z3_ADR_0 AND NOT Z3_ADR(6) AND AUTOCONFIG_ACCESS AND
|
|
NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
|
|
OR (NOT RW AND NOT FCS AND NOT DS1 AND NOT AUTO_CONFIG_DONE_CYCLE AND
|
|
NOT Z3_ADR(2) AND Z3_ADR_0 AND NOT Z3_ADR(6) AND AUTOCONFIG_ACCESS AND
|
|
NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5)));
|
|
|
|
|
|
A_LAN(0) <= NOT ((RESET AND NOT Z3_A_LOW));
|
|
|
|
|
|
A_LAN(1) <= NOT ((RESET AND NOT Z3_ADR_0));
|
|
|
|
|
|
A_LAN(2) <= NOT ((RESET AND NOT Z3_ADR_1));
|
|
|
|
|
|
A_LAN(3) <= ((RESET AND Z3_ADR(2))
|
|
OR (NOT RESET AND LAN_A_INIT(3)));
|
|
|
|
|
|
A_LAN(4) <= NOT ((RESET AND NOT Z3_ADR(3)));
|
|
|
|
|
|
A_LAN(5) <= NOT ((RESET AND NOT Z3_ADR(4)));
|
|
|
|
|
|
A_LAN(6) <= ((RESET AND Z3_ADR(5))
|
|
OR (NOT RESET AND LAN_A_INIT(6)));
|
|
|
|
|
|
A_LAN(7) <= NOT ((RESET AND NOT Z3_ADR(6)));
|
|
|
|
|
|
A_LAN(8) <= NOT ((RESET AND NOT Z3_ADR(7)));
|
|
|
|
|
|
A_LAN(9) <= NOT ((RESET AND NOT Z3_ADR(8)));
|
|
|
|
|
|
A_LAN(10) <= NOT ((RESET AND NOT Z3_ADR(9)));
|
|
|
|
|
|
A_LAN(11) <= NOT ((RESET AND NOT Z3_ADR(10)));
|
|
|
|
|
|
A_LAN(12) <= NOT ((RESET AND NOT Z3_ADR(11)));
|
|
|
|
|
|
A_LAN(13) <= NOT ((RESET AND NOT Z3_ADR(12)));
|
|
|
|
FDCPE_CFOUT: FDCPE port map (CFOUT,CFOUT_D,CLK_EXT,'0',NOT RESET,FCS);
|
|
CFOUT_D <= (NOT AUTO_CONFIG_DONE_CYCLE AND AUTOBOOT_OFF);
|
|
|
|
FDCPE_CONFIG_READY: FDCPE port map (CONFIG_READY,'1',CLK_EXT,NOT RESET,'0',CONFIG_READY_CE);
|
|
CONFIG_READY_CE <= (NOT RW AND NOT FCS AND LAN_ACCESS AND Z3_ADR(13));
|
|
|
|
|
|
CP_CS <= '1';
|
|
|
|
|
|
CP_RD <= '1';
|
|
|
|
|
|
CP_WE <= '1';
|
|
|
|
|
|
D_I(0) <= NOT (((RW AND NOT FCS AND NOT UDS AND NOT Z3_DATA(16) AND LAN_ACCESS)
|
|
OR (RW AND NOT FCS AND NOT LDS AND NOT Z3_DATA(16) AND LAN_ACCESS)
|
|
OR (RW AND NOT FCS AND NOT DS0 AND NOT Z3_DATA(16) AND LAN_ACCESS)
|
|
OR (RW AND NOT FCS AND NOT DS1 AND NOT Z3_DATA(16) AND LAN_ACCESS)));
|
|
D(0) <= D_I(0) when D_OE(0) = '1' else 'Z';
|
|
D_OE(0) <= NOT $OpTx$FX_SC$119__$INT;
|
|
|
|
|
|
D_I(1) <= NOT (((RW AND NOT FCS AND NOT UDS AND NOT Z3_DATA(17) AND LAN_ACCESS)
|
|
OR (RW AND NOT FCS AND NOT LDS AND NOT Z3_DATA(17) AND LAN_ACCESS)
|
|
OR (RW AND NOT FCS AND NOT DS0 AND NOT Z3_DATA(17) AND LAN_ACCESS)
|
|
OR (RW AND NOT FCS AND NOT DS1 AND NOT Z3_DATA(17) AND LAN_ACCESS)));
|
|
D(1) <= D_I(1) when D_OE(1) = '1' else 'Z';
|
|
D_OE(1) <= NOT $OpTx$FX_SC$119__$INT;
|
|
|
|
|
|
D_I(2) <= NOT (((RW AND NOT FCS AND NOT UDS AND NOT Z3_DATA(18) AND LAN_ACCESS)
|
|
OR (RW AND NOT FCS AND NOT LDS AND NOT Z3_DATA(18) AND LAN_ACCESS)
|
|
OR (RW AND NOT FCS AND NOT DS1 AND NOT Z3_DATA(18) AND LAN_ACCESS)
|
|
OR (RW AND NOT FCS AND NOT DS0 AND NOT Z3_DATA(18) AND LAN_ACCESS)));
|
|
D(2) <= D_I(2) when D_OE(2) = '1' else 'Z';
|
|
D_OE(2) <= NOT $OpTx$FX_SC$119__$INT;
|
|
|
|
|
|
D_I(3) <= NOT (((RW AND NOT FCS AND NOT UDS AND NOT Z3_DATA(19) AND LAN_ACCESS)
|
|
OR (RW AND NOT FCS AND NOT LDS AND NOT Z3_DATA(19) AND LAN_ACCESS)
|
|
OR (RW AND NOT FCS AND NOT DS1 AND NOT Z3_DATA(19) AND LAN_ACCESS)
|
|
OR (RW AND NOT FCS AND NOT DS0 AND NOT Z3_DATA(19) AND LAN_ACCESS)));
|
|
D(3) <= D_I(3) when D_OE(3) = '1' else 'Z';
|
|
D_OE(3) <= NOT $OpTx$FX_SC$119__$INT;
|
|
|
|
|
|
D_I(4) <= NOT (((RW AND NOT FCS AND NOT UDS AND NOT Z3_DATA(20) AND LAN_ACCESS)
|
|
OR (RW AND NOT FCS AND NOT LDS AND NOT Z3_DATA(20) AND LAN_ACCESS)
|
|
OR (RW AND NOT FCS AND NOT DS1 AND NOT Z3_DATA(20) AND LAN_ACCESS)
|
|
OR (RW AND NOT FCS AND NOT DS0 AND NOT Z3_DATA(20) AND LAN_ACCESS)));
|
|
D(4) <= D_I(4) when D_OE(4) = '1' else 'Z';
|
|
D_OE(4) <= NOT $OpTx$FX_SC$119__$INT;
|
|
|
|
|
|
D_I(5) <= NOT (((RW AND NOT FCS AND NOT UDS AND NOT Z3_DATA(21) AND LAN_ACCESS)
|
|
OR (RW AND NOT FCS AND NOT LDS AND NOT Z3_DATA(21) AND LAN_ACCESS)
|
|
OR (RW AND NOT FCS AND NOT DS1 AND NOT Z3_DATA(21) AND LAN_ACCESS)
|
|
OR (RW AND NOT FCS AND NOT DS0 AND NOT Z3_DATA(21) AND LAN_ACCESS)));
|
|
D(5) <= D_I(5) when D_OE(5) = '1' else 'Z';
|
|
D_OE(5) <= NOT $OpTx$FX_SC$119__$INT;
|
|
|
|
|
|
D_I(6) <= NOT (((RW AND NOT FCS AND NOT UDS AND NOT Z3_DATA(22) AND LAN_ACCESS)
|
|
OR (RW AND NOT FCS AND NOT LDS AND NOT Z3_DATA(22) AND LAN_ACCESS)
|
|
OR (RW AND NOT FCS AND NOT DS1 AND NOT Z3_DATA(22) AND LAN_ACCESS)
|
|
OR (RW AND NOT FCS AND NOT DS0 AND NOT Z3_DATA(22) AND LAN_ACCESS)));
|
|
D(6) <= D_I(6) when D_OE(6) = '1' else 'Z';
|
|
D_OE(6) <= NOT $OpTx$FX_SC$119__$INT;
|
|
|
|
|
|
D_I(7) <= NOT (((RW AND NOT FCS AND NOT UDS AND NOT Z3_DATA(23) AND LAN_ACCESS)
|
|
OR (RW AND NOT FCS AND NOT LDS AND NOT Z3_DATA(23) AND LAN_ACCESS)
|
|
OR (RW AND NOT FCS AND NOT DS0 AND NOT Z3_DATA(23) AND LAN_ACCESS)
|
|
OR (RW AND NOT FCS AND NOT DS1 AND NOT Z3_DATA(23) AND LAN_ACCESS)));
|
|
D(7) <= D_I(7) when D_OE(7) = '1' else 'Z';
|
|
D_OE(7) <= NOT $OpTx$FX_SC$119__$INT;
|
|
|
|
|
|
D_I(8) <= ((RW AND NOT FCS AND NOT UDS AND Z3_DATA(24) AND LAN_ACCESS)
|
|
OR (RW AND NOT FCS AND NOT LDS AND Z3_DATA(24) AND LAN_ACCESS)
|
|
OR (RW AND NOT FCS AND NOT DS1 AND Z3_DATA(24) AND LAN_ACCESS)
|
|
OR (RW AND NOT FCS AND NOT DS0 AND Z3_DATA(24) AND LAN_ACCESS)
|
|
OR (UDS AND LDS AND DS1 AND DS0 AND D_OUT(0))
|
|
OR (NOT RW AND D_OUT(0))
|
|
OR (FCS AND D_OUT(0))
|
|
OR (NOT LAN_ACCESS AND D_OUT(0)));
|
|
D(8) <= D_I(8) when D_OE(8) = '1' else 'Z';
|
|
D_OE(8) <= NOT $OpTx$FX_SC$119__$INT;
|
|
|
|
|
|
D_I(9) <= ((RW AND NOT FCS AND NOT UDS AND Z3_DATA(25) AND LAN_ACCESS)
|
|
OR (RW AND NOT FCS AND NOT LDS AND Z3_DATA(25) AND LAN_ACCESS)
|
|
OR (RW AND NOT FCS AND NOT DS0 AND Z3_DATA(25) AND LAN_ACCESS)
|
|
OR (UDS AND LDS AND DS1 AND DS0 AND D_OUT(1))
|
|
OR (NOT RW AND D_OUT(1))
|
|
OR (FCS AND D_OUT(1))
|
|
OR (NOT LAN_ACCESS AND D_OUT(1))
|
|
OR (RW AND NOT FCS AND NOT DS1 AND Z3_DATA(25) AND LAN_ACCESS));
|
|
D(9) <= D_I(9) when D_OE(9) = '1' else 'Z';
|
|
D_OE(9) <= NOT $OpTx$FX_SC$119__$INT;
|
|
|
|
|
|
D_I(10) <= ((RW AND NOT FCS AND NOT UDS AND Z3_DATA(26) AND LAN_ACCESS)
|
|
OR (RW AND NOT FCS AND NOT LDS AND Z3_DATA(26) AND LAN_ACCESS)
|
|
OR (RW AND NOT FCS AND NOT DS0 AND Z3_DATA(26) AND LAN_ACCESS)
|
|
OR (UDS AND LDS AND DS1 AND DS0 AND D_OUT(2))
|
|
OR (NOT RW AND D_OUT(2))
|
|
OR (FCS AND D_OUT(2))
|
|
OR (NOT LAN_ACCESS AND D_OUT(2))
|
|
OR (RW AND NOT FCS AND NOT DS1 AND Z3_DATA(26) AND LAN_ACCESS));
|
|
D(10) <= D_I(10) when D_OE(10) = '1' else 'Z';
|
|
D_OE(10) <= NOT $OpTx$FX_SC$119__$INT;
|
|
|
|
|
|
D_I(11) <= ((RW AND NOT FCS AND NOT UDS AND Z3_DATA(27) AND LAN_ACCESS)
|
|
OR (RW AND NOT FCS AND NOT LDS AND Z3_DATA(27) AND LAN_ACCESS)
|
|
OR (RW AND NOT FCS AND NOT DS0 AND Z3_DATA(27) AND LAN_ACCESS)
|
|
OR (UDS AND LDS AND DS1 AND DS0 AND D_OUT(3))
|
|
OR (NOT RW AND D_OUT(3))
|
|
OR (FCS AND D_OUT(3))
|
|
OR (NOT LAN_ACCESS AND D_OUT(3))
|
|
OR (RW AND NOT FCS AND NOT DS1 AND Z3_DATA(27) AND LAN_ACCESS));
|
|
D(11) <= D_I(11) when D_OE(11) = '1' else 'Z';
|
|
D_OE(11) <= NOT $OpTx$FX_SC$119__$INT;
|
|
|
|
|
|
D_I(12) <= ((RW AND NOT FCS AND NOT UDS AND Z3_DATA(28) AND LAN_ACCESS)
|
|
OR (RW AND NOT FCS AND NOT LDS AND Z3_DATA(28) AND LAN_ACCESS)
|
|
OR (RW AND NOT FCS AND NOT DS0 AND Z3_DATA(28) AND LAN_ACCESS)
|
|
OR (UDS AND LDS AND DS1 AND DS0 AND D_OUT(4))
|
|
OR (NOT RW AND D_OUT(4))
|
|
OR (FCS AND D_OUT(4))
|
|
OR (NOT LAN_ACCESS AND D_OUT(4))
|
|
OR (RW AND NOT FCS AND NOT DS1 AND Z3_DATA(28) AND LAN_ACCESS));
|
|
D(12) <= D_I(12) when D_OE(12) = '1' else 'Z';
|
|
D_OE(12) <= NOT $OpTx$FX_SC$119__$INT;
|
|
|
|
|
|
D_I(13) <= ((D_14_IOBUFE.EXP)
|
|
OR (NOT RW AND D_OUT(5))
|
|
OR (RW AND NOT FCS AND NOT UDS AND Z3_DATA(29) AND LAN_ACCESS)
|
|
OR (RW AND NOT FCS AND NOT LDS AND Z3_DATA(29) AND LAN_ACCESS)
|
|
OR (RW AND NOT FCS AND NOT DS1 AND Z3_DATA(29) AND LAN_ACCESS)
|
|
OR (RW AND NOT FCS AND NOT DS0 AND Z3_DATA(29) AND LAN_ACCESS)
|
|
OR (FCS AND D_OUT(5))
|
|
OR (NOT LAN_ACCESS AND D_OUT(5)));
|
|
D(13) <= D_I(13) when D_OE(13) = '1' else 'Z';
|
|
D_OE(13) <= NOT $OpTx$FX_SC$119__$INT;
|
|
|
|
|
|
D_I(14) <= ((RW AND NOT FCS AND NOT UDS AND Z3_DATA(30) AND LAN_ACCESS)
|
|
OR (RW AND NOT FCS AND NOT LDS AND Z3_DATA(30) AND LAN_ACCESS)
|
|
OR (RW AND NOT FCS AND NOT DS1 AND Z3_DATA(30) AND LAN_ACCESS)
|
|
OR (RW AND NOT FCS AND NOT DS0 AND Z3_DATA(30) AND LAN_ACCESS)
|
|
OR (UDS AND LDS AND DS1 AND DS0 AND D_OUT(6))
|
|
OR (NOT RW AND D_OUT(6))
|
|
OR (FCS AND D_OUT(6))
|
|
OR (NOT LAN_ACCESS AND D_OUT(6)));
|
|
D(14) <= D_I(14) when D_OE(14) = '1' else 'Z';
|
|
D_OE(14) <= NOT $OpTx$FX_SC$119__$INT;
|
|
|
|
|
|
D_I(15) <= ((RW AND NOT FCS AND NOT UDS AND Z3_DATA(31) AND LAN_ACCESS)
|
|
OR (RW AND NOT FCS AND NOT LDS AND Z3_DATA(31) AND LAN_ACCESS)
|
|
OR (RW AND NOT FCS AND NOT DS0 AND Z3_DATA(31) AND LAN_ACCESS)
|
|
OR (UDS AND LDS AND DS1 AND DS0 AND D_OUT(7))
|
|
OR (NOT RW AND D_OUT(7))
|
|
OR (FCS AND D_OUT(7))
|
|
OR (NOT LAN_ACCESS AND D_OUT(7))
|
|
OR (RW AND NOT FCS AND NOT DS1 AND Z3_DATA(31) AND LAN_ACCESS));
|
|
D(15) <= D_I(15) when D_OE(15) = '1' else 'Z';
|
|
D_OE(15) <= NOT $OpTx$FX_SC$119__$INT;
|
|
|
|
|
|
DQ_I(0) <= (RESET AND DQ_DATA(0));
|
|
DQ(0) <= DQ_I(0) when DQ_OE(0) = '1' else 'Z';
|
|
DQ_OE(0) <= NOT $OpTx$FX_DC$118__$INT;
|
|
|
|
|
|
DQ_I(1) <= ((RESET AND DQ_DATA(1))
|
|
OR (NOT RESET AND LAN_D_INIT(1)));
|
|
DQ(1) <= DQ_I(1) when DQ_OE(1) = '1' else 'Z';
|
|
DQ_OE(1) <= NOT $OpTx$FX_DC$118__$INT;
|
|
|
|
|
|
DQ_I(2) <= (RESET AND DQ_DATA(2));
|
|
DQ(2) <= DQ_I(2) when DQ_OE(2) = '1' else 'Z';
|
|
DQ_OE(2) <= NOT $OpTx$FX_DC$118__$INT;
|
|
|
|
|
|
DQ_I(3) <= (RESET AND DQ_DATA(3));
|
|
DQ(3) <= DQ_I(3) when DQ_OE(3) = '1' else 'Z';
|
|
DQ_OE(3) <= NOT $OpTx$FX_DC$118__$INT;
|
|
|
|
|
|
DQ_I(4) <= ((RESET AND DQ_DATA(4))
|
|
OR (NOT RESET AND LAN_D_INIT(1)));
|
|
DQ(4) <= DQ_I(4) when DQ_OE(4) = '1' else 'Z';
|
|
DQ_OE(4) <= NOT $OpTx$FX_DC$118__$INT;
|
|
|
|
|
|
DQ_I(5) <= (RESET AND DQ_DATA(5));
|
|
DQ(5) <= DQ_I(5) when DQ_OE(5) = '1' else 'Z';
|
|
DQ_OE(5) <= NOT $OpTx$FX_DC$118__$INT;
|
|
|
|
|
|
DQ_I(6) <= (RESET AND DQ_DATA(6));
|
|
DQ(6) <= DQ_I(6) when DQ_OE(6) = '1' else 'Z';
|
|
DQ_OE(6) <= NOT $OpTx$FX_DC$118__$INT;
|
|
|
|
|
|
DQ_I(7) <= (RESET AND DQ_DATA(7));
|
|
DQ(7) <= DQ_I(7) when DQ_OE(7) = '1' else 'Z';
|
|
DQ_OE(7) <= NOT $OpTx$FX_DC$118__$INT;
|
|
|
|
|
|
DQ_I(8) <= ((RESET AND DQ_DATA(8))
|
|
OR (NOT RESET AND LAN_D_INIT(8)));
|
|
DQ(8) <= DQ_I(8) when DQ_OE(8) = '1' else 'Z';
|
|
DQ_OE(8) <= NOT $OpTx$FX_DC$118__$INT;
|
|
|
|
|
|
DQ_I(9) <= ((RESET AND DQ_DATA(9))
|
|
OR (NOT RESET AND LAN_D_INIT(1)));
|
|
DQ(9) <= DQ_I(9) when DQ_OE(9) = '1' else 'Z';
|
|
DQ_OE(9) <= NOT $OpTx$FX_DC$118__$INT;
|
|
|
|
|
|
DQ_I(10) <= ((RESET AND DQ_DATA(10))
|
|
OR (NOT RESET AND LAN_D_INIT(8)));
|
|
DQ(10) <= DQ_I(10) when DQ_OE(10) = '1' else 'Z';
|
|
DQ_OE(10) <= NOT $OpTx$FX_DC$118__$INT;
|
|
|
|
|
|
DQ_I(11) <= ((RESET AND DQ_DATA(11))
|
|
OR (NOT RESET AND LAN_D_INIT(8)));
|
|
DQ(11) <= DQ_I(11) when DQ_OE(11) = '1' else 'Z';
|
|
DQ_OE(11) <= NOT $OpTx$FX_DC$118__$INT;
|
|
|
|
|
|
DQ_I(12) <= (RESET AND DQ_DATA(12));
|
|
DQ(12) <= DQ_I(12) when DQ_OE(12) = '1' else 'Z';
|
|
DQ_OE(12) <= NOT $OpTx$FX_DC$118__$INT;
|
|
|
|
|
|
DQ_I(13) <= (RESET AND DQ_DATA(13));
|
|
DQ(13) <= DQ_I(13) when DQ_OE(13) = '1' else 'Z';
|
|
DQ_OE(13) <= NOT $OpTx$FX_DC$118__$INT;
|
|
|
|
|
|
DQ_I(14) <= (RESET AND DQ_DATA(14));
|
|
DQ(14) <= DQ_I(14) when DQ_OE(14) = '1' else 'Z';
|
|
DQ_OE(14) <= NOT $OpTx$FX_DC$118__$INT;
|
|
|
|
|
|
DQ_I(15) <= (RESET AND DQ_DATA(15));
|
|
DQ(15) <= DQ_I(15) when DQ_OE(15) = '1' else 'Z';
|
|
DQ_OE(15) <= NOT $OpTx$FX_DC$118__$INT;
|
|
|
|
FDCPE_DQ_DATA0: FDCPE port map (DQ_DATA(0),DQ_DATA_D(0),CLK_EXT,'0',LAN_SM_RST);
|
|
DQ_DATA_D(0) <= ((A(16).PIN AND LAN_SM_FSM_FFd4 AND DQ_SWAP AND
|
|
LAN_SM_FSM_FFd1 AND NOT LAN_SM_FSM_FFd3)
|
|
OR (LAN_SM_FSM_FFd4 AND NOT DQ_SWAP AND LAN_SM_FSM_FFd1 AND
|
|
NOT LAN_SM_FSM_FFd3 AND A(8).PIN)
|
|
OR (Z3_DATA(20).EXP)
|
|
OR (D(8).PIN AND NOT UDS AND NOT LAN_SM_FSM_FFd4 AND DQ_SWAP AND
|
|
NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3)
|
|
OR (D(8).PIN AND NOT LDS AND NOT LAN_SM_FSM_FFd4 AND DQ_SWAP AND
|
|
NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3)
|
|
OR (NOT UDS AND D(0).PIN AND NOT LAN_SM_FSM_FFd4 AND NOT DQ_SWAP AND
|
|
NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3)
|
|
OR (NOT LDS AND D(0).PIN AND NOT LAN_SM_FSM_FFd4 AND NOT DQ_SWAP AND
|
|
NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3)
|
|
OR (A(16).PIN AND UDS AND LDS AND NOT LAN_SM_FSM_FFd4 AND
|
|
DQ_SWAP AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3)
|
|
OR (LAN_SM_FSM_FFd3 AND DQ_DATA(0))
|
|
OR (LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND DQ_DATA(0))
|
|
OR (NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd1 AND DQ_DATA(0))
|
|
OR (LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1 AND DQ_DATA(0)));
|
|
|
|
FDCPE_DQ_DATA1: FDCPE port map (DQ_DATA(1),DQ_DATA_D(1),CLK_EXT,'0',LAN_SM_RST);
|
|
DQ_DATA_D(1) <= ((D(9).PIN AND NOT UDS AND NOT LAN_SM_FSM_FFd4 AND DQ_SWAP AND
|
|
NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3)
|
|
OR (D(9).PIN AND NOT LDS AND NOT LAN_SM_FSM_FFd4 AND DQ_SWAP AND
|
|
NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3)
|
|
OR (A(17).PIN AND UDS AND LDS AND NOT LAN_SM_FSM_FFd4 AND
|
|
DQ_SWAP AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3)
|
|
OR (UDS AND LDS AND NOT LAN_SM_FSM_FFd4 AND NOT DQ_SWAP AND
|
|
NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3 AND A(9).PIN)
|
|
OR (A(17).PIN AND LAN_SM_FSM_FFd4 AND DQ_SWAP AND
|
|
LAN_SM_FSM_FFd1 AND NOT LAN_SM_FSM_FFd3)
|
|
OR (LAN_SM_FSM_FFd4 AND NOT DQ_SWAP AND LAN_SM_FSM_FFd1 AND
|
|
NOT LAN_SM_FSM_FFd3 AND A(9).PIN)
|
|
OR (NOT UDS AND D(1).PIN AND NOT LAN_SM_FSM_FFd4 AND NOT DQ_SWAP AND
|
|
NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3)
|
|
OR (NOT LDS AND D(1).PIN AND NOT LAN_SM_FSM_FFd4 AND NOT DQ_SWAP AND
|
|
NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3)
|
|
OR (LAN_SM_FSM_FFd3 AND DQ_DATA(1))
|
|
OR (LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND DQ_DATA(1))
|
|
OR (NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd1 AND DQ_DATA(1))
|
|
OR (LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1 AND DQ_DATA(1)));
|
|
|
|
FDCPE_DQ_DATA2: FDCPE port map (DQ_DATA(2),DQ_DATA_D(2),CLK_EXT,'0',LAN_SM_RST);
|
|
DQ_DATA_D(2) <= ((A(18).PIN AND LAN_SM_FSM_FFd4 AND DQ_SWAP AND
|
|
LAN_SM_FSM_FFd1 AND NOT LAN_SM_FSM_FFd3)
|
|
OR (LAN_SM_FSM_FFd4 AND NOT DQ_SWAP AND LAN_SM_FSM_FFd1 AND
|
|
NOT LAN_SM_FSM_FFd3 AND A(10).PIN)
|
|
OR (D(10).PIN AND NOT UDS AND NOT LAN_SM_FSM_FFd4 AND DQ_SWAP AND
|
|
NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3)
|
|
OR (D(10).PIN AND NOT LDS AND NOT LAN_SM_FSM_FFd4 AND DQ_SWAP AND
|
|
NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3)
|
|
OR (NOT UDS AND D(2).PIN AND NOT LAN_SM_FSM_FFd4 AND NOT DQ_SWAP AND
|
|
NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3)
|
|
OR (NOT LDS AND D(2).PIN AND NOT LAN_SM_FSM_FFd4 AND NOT DQ_SWAP AND
|
|
NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3)
|
|
OR (A(18).PIN AND UDS AND LDS AND NOT LAN_SM_FSM_FFd4 AND
|
|
DQ_SWAP AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3)
|
|
OR (UDS AND LDS AND NOT LAN_SM_FSM_FFd4 AND NOT DQ_SWAP AND
|
|
NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3 AND A(10).PIN)
|
|
OR (LAN_SM_FSM_FFd3 AND DQ_DATA(2))
|
|
OR (LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND DQ_DATA(2))
|
|
OR (NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd1 AND DQ_DATA(2))
|
|
OR (LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1 AND DQ_DATA(2)));
|
|
|
|
FDCPE_DQ_DATA3: FDCPE port map (DQ_DATA(3),DQ_DATA_D(3),CLK_EXT,'0',LAN_SM_RST);
|
|
DQ_DATA_D(3) <= ((A(19).PIN AND LAN_SM_FSM_FFd4 AND DQ_SWAP AND
|
|
LAN_SM_FSM_FFd1 AND NOT LAN_SM_FSM_FFd3)
|
|
OR (LAN_SM_FSM_FFd4 AND NOT DQ_SWAP AND LAN_SM_FSM_FFd1 AND
|
|
NOT LAN_SM_FSM_FFd3 AND A(11).PIN)
|
|
OR (D(11).PIN AND NOT UDS AND NOT LAN_SM_FSM_FFd4 AND DQ_SWAP AND
|
|
NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3)
|
|
OR (D(11).PIN AND NOT LDS AND NOT LAN_SM_FSM_FFd4 AND DQ_SWAP AND
|
|
NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3)
|
|
OR (NOT UDS AND D(3).PIN AND NOT LAN_SM_FSM_FFd4 AND NOT DQ_SWAP AND
|
|
NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3)
|
|
OR (NOT LDS AND D(3).PIN AND NOT LAN_SM_FSM_FFd4 AND NOT DQ_SWAP AND
|
|
NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3)
|
|
OR (A(19).PIN AND UDS AND LDS AND NOT LAN_SM_FSM_FFd4 AND
|
|
DQ_SWAP AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3)
|
|
OR (UDS AND LDS AND NOT LAN_SM_FSM_FFd4 AND NOT DQ_SWAP AND
|
|
NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3 AND A(11).PIN)
|
|
OR (LAN_SM_FSM_FFd3 AND DQ_DATA(3))
|
|
OR (LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND DQ_DATA(3))
|
|
OR (NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd1 AND DQ_DATA(3))
|
|
OR (LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1 AND DQ_DATA(3)));
|
|
|
|
FDCPE_DQ_DATA4: FDCPE port map (DQ_DATA(4),DQ_DATA_D(4),CLK_EXT,'0',LAN_SM_RST);
|
|
DQ_DATA_D(4) <= ((Z3_DATA(31).EXP)
|
|
OR (A(20).PIN AND LAN_SM_FSM_FFd4 AND DQ_SWAP AND
|
|
LAN_SM_FSM_FFd1 AND NOT LAN_SM_FSM_FFd3)
|
|
OR (LAN_SM_FSM_FFd4 AND NOT DQ_SWAP AND LAN_SM_FSM_FFd1 AND
|
|
NOT LAN_SM_FSM_FFd3 AND A(12).PIN)
|
|
OR (D(12).PIN AND NOT UDS AND NOT LAN_SM_FSM_FFd4 AND DQ_SWAP AND
|
|
NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3)
|
|
OR (D(12).PIN AND NOT LDS AND NOT LAN_SM_FSM_FFd4 AND DQ_SWAP AND
|
|
NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3)
|
|
OR (NOT UDS AND D(4).PIN AND NOT LAN_SM_FSM_FFd4 AND NOT DQ_SWAP AND
|
|
NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3)
|
|
OR (NOT LDS AND D(4).PIN AND NOT LAN_SM_FSM_FFd4 AND NOT DQ_SWAP AND
|
|
NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3)
|
|
OR (UDS AND LDS AND NOT LAN_SM_FSM_FFd4 AND NOT DQ_SWAP AND
|
|
NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3 AND A(12).PIN)
|
|
OR (LAN_SM_FSM_FFd3 AND DQ_DATA(4))
|
|
OR (LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND DQ_DATA(4))
|
|
OR (NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd1 AND DQ_DATA(4))
|
|
OR (LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1 AND DQ_DATA(4)));
|
|
|
|
FDCPE_DQ_DATA5: FDCPE port map (DQ_DATA(5),DQ_DATA_D(5),CLK_EXT,'0',LAN_SM_RST);
|
|
DQ_DATA_D(5) <= ((EXP66_.EXP)
|
|
OR (LAN_SM_FSM_FFd3 AND DQ_DATA(5))
|
|
OR (LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND DQ_DATA(5))
|
|
OR (LAN_SM_FSM_FFd4 AND DQ_SWAP AND LAN_SM_FSM_FFd1 AND
|
|
NOT LAN_SM_FSM_FFd3 AND A(21).PIN)
|
|
OR (LAN_SM_FSM_FFd4 AND NOT DQ_SWAP AND LAN_SM_FSM_FFd1 AND
|
|
NOT LAN_SM_FSM_FFd3 AND A(13).PIN)
|
|
OR (D(13).PIN AND NOT UDS AND NOT LAN_SM_FSM_FFd4 AND DQ_SWAP AND
|
|
NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3)
|
|
OR (NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd1 AND DQ_DATA(5))
|
|
OR (LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1 AND DQ_DATA(5)));
|
|
|
|
FDCPE_DQ_DATA6: FDCPE port map (DQ_DATA(6),DQ_DATA_D(6),CLK_EXT,'0',LAN_SM_RST);
|
|
DQ_DATA_D(6) <= ((LAN_SM_FSM_FFd4 AND DQ_SWAP AND LAN_SM_FSM_FFd1 AND
|
|
NOT LAN_SM_FSM_FFd3 AND A(22).PIN)
|
|
OR (LAN_SM_FSM_FFd4 AND NOT DQ_SWAP AND LAN_SM_FSM_FFd1 AND
|
|
NOT LAN_SM_FSM_FFd3 AND A(14).PIN)
|
|
OR (D(14).PIN AND NOT UDS AND NOT LAN_SM_FSM_FFd4 AND DQ_SWAP AND
|
|
NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3)
|
|
OR (D(14).PIN AND NOT LDS AND NOT LAN_SM_FSM_FFd4 AND DQ_SWAP AND
|
|
NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3)
|
|
OR (NOT UDS AND D(6).PIN AND NOT LAN_SM_FSM_FFd4 AND NOT DQ_SWAP AND
|
|
NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3)
|
|
OR (NOT LDS AND D(6).PIN AND NOT LAN_SM_FSM_FFd4 AND NOT DQ_SWAP AND
|
|
NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3)
|
|
OR (UDS AND LDS AND NOT LAN_SM_FSM_FFd4 AND DQ_SWAP AND
|
|
NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3 AND A(22).PIN)
|
|
OR (UDS AND LDS AND NOT LAN_SM_FSM_FFd4 AND NOT DQ_SWAP AND
|
|
NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3 AND A(14).PIN)
|
|
OR (LAN_SM_FSM_FFd3 AND DQ_DATA(6))
|
|
OR (LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND DQ_DATA(6))
|
|
OR (NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd1 AND DQ_DATA(6))
|
|
OR (LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1 AND DQ_DATA(6)));
|
|
|
|
FDCPE_DQ_DATA7: FDCPE port map (DQ_DATA(7),DQ_DATA_D(7),CLK_EXT,'0',LAN_SM_RST);
|
|
DQ_DATA_D(7) <= ((LAN_SM_FSM_FFd4 AND DQ_SWAP AND LAN_SM_FSM_FFd1 AND
|
|
NOT LAN_SM_FSM_FFd3 AND A(23).PIN)
|
|
OR (LAN_SM_FSM_FFd4 AND NOT DQ_SWAP AND LAN_SM_FSM_FFd1 AND
|
|
NOT LAN_SM_FSM_FFd3 AND A(15).PIN)
|
|
OR (D(15).PIN AND NOT UDS AND NOT LAN_SM_FSM_FFd4 AND DQ_SWAP AND
|
|
NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3)
|
|
OR (D(15).PIN AND NOT LDS AND NOT LAN_SM_FSM_FFd4 AND DQ_SWAP AND
|
|
NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3)
|
|
OR (NOT UDS AND D(7).PIN AND NOT LAN_SM_FSM_FFd4 AND NOT DQ_SWAP AND
|
|
NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3)
|
|
OR (NOT LDS AND D(7).PIN AND NOT LAN_SM_FSM_FFd4 AND NOT DQ_SWAP AND
|
|
NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3)
|
|
OR (UDS AND LDS AND NOT LAN_SM_FSM_FFd4 AND DQ_SWAP AND
|
|
NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3 AND A(23).PIN)
|
|
OR (UDS AND LDS AND NOT LAN_SM_FSM_FFd4 AND NOT DQ_SWAP AND
|
|
NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3 AND A(15).PIN)
|
|
OR (LAN_SM_FSM_FFd3 AND DQ_DATA(7))
|
|
OR (LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND DQ_DATA(7))
|
|
OR (NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd1 AND DQ_DATA(7))
|
|
OR (LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1 AND DQ_DATA(7)));
|
|
|
|
FDCPE_DQ_DATA8: FDCPE port map (DQ_DATA(8),DQ_DATA_D(8),CLK_EXT,'0',LAN_SM_RST);
|
|
DQ_DATA_D(8) <= ((A(16).PIN AND LAN_SM_FSM_FFd4 AND NOT DQ_SWAP AND
|
|
LAN_SM_FSM_FFd1 AND NOT LAN_SM_FSM_FFd3)
|
|
OR (LAN_SM_FSM_FFd4 AND DQ_SWAP AND LAN_SM_FSM_FFd1 AND
|
|
NOT LAN_SM_FSM_FFd3 AND A(8).PIN)
|
|
OR (NOT UDS AND D(0).PIN AND NOT LAN_SM_FSM_FFd4 AND DQ_SWAP AND
|
|
NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3)
|
|
OR (D(8).PIN AND NOT UDS AND NOT LAN_SM_FSM_FFd4 AND NOT DQ_SWAP AND
|
|
NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3)
|
|
OR (D(8).PIN AND NOT LDS AND NOT LAN_SM_FSM_FFd4 AND NOT DQ_SWAP AND
|
|
NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3)
|
|
OR (NOT LDS AND D(0).PIN AND NOT LAN_SM_FSM_FFd4 AND DQ_SWAP AND
|
|
NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3)
|
|
OR (A(16).PIN AND UDS AND LDS AND NOT LAN_SM_FSM_FFd4 AND
|
|
NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3)
|
|
OR (UDS AND LDS AND NOT LAN_SM_FSM_FFd4 AND DQ_SWAP AND
|
|
NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3 AND A(8).PIN)
|
|
OR (LAN_SM_FSM_FFd3 AND DQ_DATA(8))
|
|
OR (LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND DQ_DATA(8))
|
|
OR (NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd1 AND DQ_DATA(8))
|
|
OR (LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1 AND DQ_DATA(8)));
|
|
|
|
FDCPE_DQ_DATA9: FDCPE port map (DQ_DATA(9),DQ_DATA_D(9),CLK_EXT,'0',LAN_SM_RST);
|
|
DQ_DATA_D(9) <= ((A(17).PIN AND LAN_SM_FSM_FFd4 AND NOT DQ_SWAP AND
|
|
LAN_SM_FSM_FFd1 AND NOT LAN_SM_FSM_FFd3)
|
|
OR (LAN_SM_FSM_FFd4 AND DQ_SWAP AND LAN_SM_FSM_FFd1 AND
|
|
NOT LAN_SM_FSM_FFd3 AND A(9).PIN)
|
|
OR (NOT UDS AND D(1).PIN AND NOT LAN_SM_FSM_FFd4 AND DQ_SWAP AND
|
|
NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3)
|
|
OR (D(9).PIN AND NOT UDS AND NOT LAN_SM_FSM_FFd4 AND NOT DQ_SWAP AND
|
|
NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3)
|
|
OR (D(9).PIN AND NOT LDS AND NOT LAN_SM_FSM_FFd4 AND NOT DQ_SWAP AND
|
|
NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3)
|
|
OR (NOT LDS AND D(1).PIN AND NOT LAN_SM_FSM_FFd4 AND DQ_SWAP AND
|
|
NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3)
|
|
OR (A(17).PIN AND UDS AND LDS AND NOT LAN_SM_FSM_FFd4 AND
|
|
NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3)
|
|
OR (UDS AND LDS AND NOT LAN_SM_FSM_FFd4 AND DQ_SWAP AND
|
|
NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3 AND A(9).PIN)
|
|
OR (LAN_SM_FSM_FFd3 AND DQ_DATA(9))
|
|
OR (LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND DQ_DATA(9))
|
|
OR (NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd1 AND DQ_DATA(9))
|
|
OR (LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1 AND DQ_DATA(9)));
|
|
|
|
FDCPE_DQ_DATA10: FDCPE port map (DQ_DATA(10),DQ_DATA_D(10),CLK_EXT,'0',LAN_SM_RST);
|
|
DQ_DATA_D(10) <= ((NOT LDS AND D(2).PIN AND NOT LAN_SM_FSM_FFd4 AND DQ_SWAP AND
|
|
NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3)
|
|
OR (A(18).PIN AND UDS AND LDS AND NOT LAN_SM_FSM_FFd4 AND
|
|
NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3)
|
|
OR (UDS AND LDS AND NOT LAN_SM_FSM_FFd4 AND DQ_SWAP AND
|
|
NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3 AND A(10).PIN)
|
|
OR (A(18).PIN AND LAN_SM_FSM_FFd4 AND NOT DQ_SWAP AND
|
|
LAN_SM_FSM_FFd1 AND NOT LAN_SM_FSM_FFd3)
|
|
OR (LAN_SM_FSM_FFd4 AND DQ_SWAP AND LAN_SM_FSM_FFd1 AND
|
|
NOT LAN_SM_FSM_FFd3 AND A(10).PIN)
|
|
OR (D(10).PIN AND NOT UDS AND NOT LAN_SM_FSM_FFd4 AND NOT DQ_SWAP AND
|
|
NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3)
|
|
OR (D(10).PIN AND NOT LDS AND NOT LAN_SM_FSM_FFd4 AND NOT DQ_SWAP AND
|
|
NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3)
|
|
OR (NOT UDS AND D(2).PIN AND NOT LAN_SM_FSM_FFd4 AND DQ_SWAP AND
|
|
NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3)
|
|
OR (LAN_SM_FSM_FFd3 AND DQ_DATA(10))
|
|
OR (LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND DQ_DATA(10))
|
|
OR (NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd1 AND DQ_DATA(10))
|
|
OR (LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1 AND DQ_DATA(10)));
|
|
|
|
FDCPE_DQ_DATA11: FDCPE port map (DQ_DATA(11),DQ_DATA_D(11),CLK_EXT,'0',LAN_SM_RST);
|
|
DQ_DATA_D(11) <= ((A(19).PIN AND LAN_SM_FSM_FFd4 AND NOT DQ_SWAP AND
|
|
LAN_SM_FSM_FFd1 AND NOT LAN_SM_FSM_FFd3)
|
|
OR (LAN_SM_FSM_FFd4 AND DQ_SWAP AND LAN_SM_FSM_FFd1 AND
|
|
NOT LAN_SM_FSM_FFd3 AND A(11).PIN)
|
|
OR (D(11).PIN AND NOT UDS AND NOT LAN_SM_FSM_FFd4 AND NOT DQ_SWAP AND
|
|
NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3)
|
|
OR (D(11).PIN AND NOT LDS AND NOT LAN_SM_FSM_FFd4 AND NOT DQ_SWAP AND
|
|
NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3)
|
|
OR (NOT UDS AND D(3).PIN AND NOT LAN_SM_FSM_FFd4 AND DQ_SWAP AND
|
|
NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3)
|
|
OR (NOT LDS AND D(3).PIN AND NOT LAN_SM_FSM_FFd4 AND DQ_SWAP AND
|
|
NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3)
|
|
OR (A(19).PIN AND UDS AND LDS AND NOT LAN_SM_FSM_FFd4 AND
|
|
NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3)
|
|
OR (UDS AND LDS AND NOT LAN_SM_FSM_FFd4 AND DQ_SWAP AND
|
|
NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3 AND A(11).PIN)
|
|
OR (LAN_SM_FSM_FFd3 AND DQ_DATA(11))
|
|
OR (LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND DQ_DATA(11))
|
|
OR (NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd1 AND DQ_DATA(11))
|
|
OR (LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1 AND DQ_DATA(11)));
|
|
|
|
FDCPE_DQ_DATA12: FDCPE port map (DQ_DATA(12),DQ_DATA_D(12),CLK_EXT,'0',LAN_SM_RST);
|
|
DQ_DATA_D(12) <= ((NOT LDS AND D(4).PIN AND NOT LAN_SM_FSM_FFd4 AND DQ_SWAP AND
|
|
NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3)
|
|
OR (A(20).PIN AND UDS AND LDS AND NOT LAN_SM_FSM_FFd4 AND
|
|
NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3)
|
|
OR (UDS AND LDS AND NOT LAN_SM_FSM_FFd4 AND DQ_SWAP AND
|
|
NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3 AND A(12).PIN)
|
|
OR (A(20).PIN AND LAN_SM_FSM_FFd4 AND NOT DQ_SWAP AND
|
|
LAN_SM_FSM_FFd1 AND NOT LAN_SM_FSM_FFd3)
|
|
OR (LAN_SM_FSM_FFd4 AND DQ_SWAP AND LAN_SM_FSM_FFd1 AND
|
|
NOT LAN_SM_FSM_FFd3 AND A(12).PIN)
|
|
OR (D(12).PIN AND NOT UDS AND NOT LAN_SM_FSM_FFd4 AND NOT DQ_SWAP AND
|
|
NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3)
|
|
OR (D(12).PIN AND NOT LDS AND NOT LAN_SM_FSM_FFd4 AND NOT DQ_SWAP AND
|
|
NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3)
|
|
OR (NOT UDS AND D(4).PIN AND NOT LAN_SM_FSM_FFd4 AND DQ_SWAP AND
|
|
NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3)
|
|
OR (LAN_SM_FSM_FFd3 AND DQ_DATA(12))
|
|
OR (LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND DQ_DATA(12))
|
|
OR (NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd1 AND DQ_DATA(12))
|
|
OR (LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1 AND DQ_DATA(12)));
|
|
|
|
FDCPE_DQ_DATA13: FDCPE port map (DQ_DATA(13),DQ_DATA_D(13),CLK_EXT,'0',LAN_SM_RST);
|
|
DQ_DATA_D(13) <= ((LAN_SM_FSM_FFd4 AND DQ_SWAP AND LAN_SM_FSM_FFd1 AND
|
|
NOT LAN_SM_FSM_FFd3 AND A(13).PIN)
|
|
OR (LAN_SM_FSM_FFd4 AND NOT DQ_SWAP AND LAN_SM_FSM_FFd1 AND
|
|
NOT LAN_SM_FSM_FFd3 AND A(21).PIN)
|
|
OR (D(13).PIN AND NOT UDS AND NOT LAN_SM_FSM_FFd4 AND NOT DQ_SWAP AND
|
|
NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3)
|
|
OR (D(13).PIN AND NOT LDS AND NOT LAN_SM_FSM_FFd4 AND NOT DQ_SWAP AND
|
|
NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3)
|
|
OR (NOT UDS AND D(5).PIN AND NOT LAN_SM_FSM_FFd4 AND DQ_SWAP AND
|
|
NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3)
|
|
OR (NOT LDS AND D(5).PIN AND NOT LAN_SM_FSM_FFd4 AND DQ_SWAP AND
|
|
NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3)
|
|
OR (UDS AND LDS AND NOT LAN_SM_FSM_FFd4 AND DQ_SWAP AND
|
|
NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3 AND A(13).PIN)
|
|
OR (UDS AND LDS AND NOT LAN_SM_FSM_FFd4 AND NOT DQ_SWAP AND
|
|
NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3 AND A(21).PIN)
|
|
OR (LAN_SM_FSM_FFd3 AND DQ_DATA(13))
|
|
OR (LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND DQ_DATA(13))
|
|
OR (NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd1 AND DQ_DATA(13))
|
|
OR (LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1 AND DQ_DATA(13)));
|
|
|
|
FDCPE_DQ_DATA14: FDCPE port map (DQ_DATA(14),DQ_DATA_D(14),CLK_EXT,'0',LAN_SM_RST);
|
|
DQ_DATA_D(14) <= ((EXP48_.EXP)
|
|
OR (LAN_SM_FSM_FFd3 AND DQ_DATA(14))
|
|
OR (LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND DQ_DATA(14))
|
|
OR (LAN_SM_FSM_FFd4 AND DQ_SWAP AND LAN_SM_FSM_FFd1 AND
|
|
NOT LAN_SM_FSM_FFd3 AND A(14).PIN)
|
|
OR (LAN_SM_FSM_FFd4 AND NOT DQ_SWAP AND LAN_SM_FSM_FFd1 AND
|
|
NOT LAN_SM_FSM_FFd3 AND A(22).PIN)
|
|
OR (D(14).PIN AND NOT UDS AND NOT LAN_SM_FSM_FFd4 AND NOT DQ_SWAP AND
|
|
NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3)
|
|
OR (NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd1 AND DQ_DATA(14))
|
|
OR (LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1 AND DQ_DATA(14)));
|
|
|
|
FDCPE_DQ_DATA15: FDCPE port map (DQ_DATA(15),DQ_DATA_D(15),CLK_EXT,'0',LAN_SM_RST);
|
|
DQ_DATA_D(15) <= ((Z3_DATA(1).EXP)
|
|
OR (LAN_SM_FSM_FFd4 AND DQ_SWAP AND LAN_SM_FSM_FFd1 AND
|
|
NOT LAN_SM_FSM_FFd3 AND A(15).PIN)
|
|
OR (LAN_SM_FSM_FFd4 AND NOT DQ_SWAP AND LAN_SM_FSM_FFd1 AND
|
|
NOT LAN_SM_FSM_FFd3 AND A(23).PIN)
|
|
OR (D(15).PIN AND NOT UDS AND NOT LAN_SM_FSM_FFd4 AND NOT DQ_SWAP AND
|
|
NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3)
|
|
OR (D(15).PIN AND NOT LDS AND NOT LAN_SM_FSM_FFd4 AND NOT DQ_SWAP AND
|
|
NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3)
|
|
OR (NOT UDS AND D(7).PIN AND NOT LAN_SM_FSM_FFd4 AND DQ_SWAP AND
|
|
NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3)
|
|
OR (NOT LDS AND D(7).PIN AND NOT LAN_SM_FSM_FFd4 AND DQ_SWAP AND
|
|
NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3)
|
|
OR (UDS AND LDS AND NOT LAN_SM_FSM_FFd4 AND DQ_SWAP AND
|
|
NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3 AND A(15).PIN)
|
|
OR (LAN_SM_FSM_FFd3 AND DQ_DATA(15))
|
|
OR (LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND DQ_DATA(15))
|
|
OR (NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd1 AND DQ_DATA(15))
|
|
OR (LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1 AND DQ_DATA(15)));
|
|
|
|
FDCPE_DQ_SWAP: FDCPE port map (DQ_SWAP,DQ_SWAP_D,NOT FCS,'0',NOT Z3_ADR_1/Z3_ADR_1_SETF__$INT);
|
|
DQ_SWAP_D <= ((NOT Z3)
|
|
OR (SHUT_UP)
|
|
OR ($OpTx$INV$205)
|
|
OR (DQ_12_IOBUFE.EXP)
|
|
OR (NOT D(11).PIN AND LAN_BASEADR(11))
|
|
OR (D(10).PIN AND NOT LAN_BASEADR(10))
|
|
OR (NOT D(10).PIN AND LAN_BASEADR(10))
|
|
OR (D(15).PIN AND NOT LAN_BASEADR(15))
|
|
OR (NOT D(15).PIN AND LAN_BASEADR(15))
|
|
OR (NOT A(13).PIN)
|
|
OR (NOT A(14).PIN)
|
|
OR (EXP45_.EXP)
|
|
OR (D(9).PIN AND NOT LAN_BASEADR(9))
|
|
OR (NOT D(9).PIN AND LAN_BASEADR(9))
|
|
OR (D(11).PIN AND NOT LAN_BASEADR(11)));
|
|
|
|
|
|
DTACK_I <= '0';
|
|
DTACK <= DTACK_I when DTACK_OE = '1' else 'Z';
|
|
DTACK_OE <= NOT N0$BUF7/N0$BUF7_TRST__$INT;
|
|
|
|
FDCPE_D_OUT0: FDCPE port map (D_OUT(0),D_OUT_D(0),CLK_EXT,'0',NOT RESET);
|
|
D_OUT_D(0) <= ((NOT FCS AND NOT UDS AND NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND
|
|
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND NOT Z3_ADR(4) AND NOT Z3_ADR(5))
|
|
OR (NOT FCS AND NOT LDS AND NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND
|
|
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND NOT Z3_ADR(4) AND NOT Z3_ADR(5))
|
|
OR (NOT FCS AND NOT DS1 AND NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND
|
|
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND NOT Z3_ADR(4) AND NOT Z3_ADR(5))
|
|
OR (NOT FCS AND NOT DS0 AND NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND
|
|
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND NOT Z3_ADR(4) AND NOT Z3_ADR(5)));
|
|
|
|
FDCPE_D_OUT1: FDCPE port map (D_OUT(1),D_OUT_D(1),CLK_EXT,'0',NOT RESET);
|
|
D_OUT_D(1) <= ((Z3_ADR(3))
|
|
OR (Z3_ADR(4))
|
|
OR (Z3_ADR(5))
|
|
OR (FCS)
|
|
OR (NOT AUTOCONFIG_ACCESS)
|
|
OR (D_OUT(2).EXP)
|
|
OR (Z3_ADR(2) AND Z3_ADR_1)
|
|
OR (Z3_ADR(2) AND Z3_ADR_0)
|
|
OR (Z3_ADR_1 AND Z3_ADR_0));
|
|
|
|
FDCPE_D_OUT2: FDCPE port map (D_OUT(2),D_OUT_D(2),CLK_EXT,'0',NOT RESET);
|
|
D_OUT_D(2) <= ((NOT FCS AND NOT UDS AND NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND NOT Z3_ADR_0 AND
|
|
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND NOT Z3_ADR(4) AND NOT Z3_ADR(5))
|
|
OR (NOT FCS AND NOT LDS AND Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND
|
|
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND NOT Z3_ADR(4) AND NOT Z3_ADR(5))
|
|
OR (NOT FCS AND NOT LDS AND NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND NOT Z3_ADR_0 AND
|
|
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND NOT Z3_ADR(4) AND NOT Z3_ADR(5))
|
|
OR (NOT FCS AND NOT DS0 AND Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND
|
|
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND NOT Z3_ADR(4) AND NOT Z3_ADR(5))
|
|
OR (NOT FCS AND NOT DS0 AND NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND NOT Z3_ADR_0 AND
|
|
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND NOT Z3_ADR(4) AND NOT Z3_ADR(5))
|
|
OR (NOT FCS AND NOT UDS AND Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND
|
|
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND NOT Z3_ADR(4) AND NOT Z3_ADR(5))
|
|
OR (NOT FCS AND NOT DS1 AND Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND
|
|
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND NOT Z3_ADR(4) AND NOT Z3_ADR(5))
|
|
OR (NOT FCS AND NOT DS1 AND NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND NOT Z3_ADR_0 AND
|
|
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND NOT Z3_ADR(4) AND NOT Z3_ADR(5)));
|
|
|
|
FDCPE_D_OUT3: FDCPE port map (D_OUT(3),D_OUT_D(3),CLK_EXT,'0',NOT RESET);
|
|
D_OUT_D(3) <= ((NOT FCS AND NOT UDS AND NOT Z3_ADR_1 AND AUTOCONFIG_ACCESS AND
|
|
NOT Z3_ADR(3) AND NOT Z3_ADR(4) AND NOT Z3_ADR(5))
|
|
OR (NOT FCS AND NOT LDS AND NOT Z3_ADR_1 AND AUTOCONFIG_ACCESS AND
|
|
NOT Z3_ADR(3) AND NOT Z3_ADR(4) AND NOT Z3_ADR(5))
|
|
OR (NOT FCS AND NOT DS1 AND NOT Z3_ADR_1 AND AUTOCONFIG_ACCESS AND
|
|
NOT Z3_ADR(3) AND NOT Z3_ADR(4) AND NOT Z3_ADR(5))
|
|
OR (NOT FCS AND NOT DS0 AND NOT Z3_ADR_1 AND AUTOCONFIG_ACCESS AND
|
|
NOT Z3_ADR(3) AND NOT Z3_ADR(4) AND NOT Z3_ADR(5)));
|
|
|
|
FDCPE_D_OUT4: FDCPE port map (D_OUT(4),D_OUT_D(4),CLK_EXT,'0',NOT RESET);
|
|
D_OUT_D(4) <= ((FCS)
|
|
OR (Z3_ADR(3))
|
|
OR (NOT AUTOCONFIG_ACCESS)
|
|
OR (Z3_ADR(4))
|
|
OR (Z3_ADR(5))
|
|
OR (D_0_IOBUFE.EXP)
|
|
OR (Z3_ADR(2) AND NOT Z3_ADR_0)
|
|
OR (Z3_ADR(2) AND Z3_ADR(6)));
|
|
|
|
FDCPE_D_OUT5: FDCPE port map (D_OUT(5),D_OUT_D(5),CLK_EXT,'0',NOT RESET);
|
|
D_OUT_D(5) <= ((FCS)
|
|
OR (Z3_ADR(3))
|
|
OR (Z3_ADR(4))
|
|
OR (Z3_ADR(5))
|
|
OR (NOT AUTOCONFIG_ACCESS)
|
|
OR (Z3_ADR(2) AND Z3_ADR_1)
|
|
OR (Z3_ADR(2) AND Z3_ADR_0)
|
|
OR (Z3_ADR(2) AND NOT Z3_ADR(6))
|
|
OR (Z3_ADR_1 AND NOT Z3_ADR(6))
|
|
OR (Z3_ADR_1 AND Z3_ADR_0)
|
|
OR (UDS AND LDS AND DS1 AND DS0));
|
|
|
|
FDCPE_D_OUT6: FDCPE port map (D_OUT(6),D_OUT_D(6),CLK_EXT,'0',NOT RESET);
|
|
D_OUT_D(6) <= ((FCS)
|
|
OR (Z3_ADR_1)
|
|
OR (Z3_ADR(3))
|
|
OR (Z3_ADR(4))
|
|
OR (NOT AUTOCONFIG_ACCESS)
|
|
OR (Z3_ADR(2) AND NOT Z3_ADR_0)
|
|
OR (Z3_ADR(2) AND NOT Z3_ADR(6))
|
|
OR (NOT Z3_ADR(2) AND Z3_ADR_0 AND Z3_ADR(6))
|
|
OR (UDS AND LDS AND DS1 AND DS0)
|
|
OR (Z3_ADR(5)));
|
|
|
|
FDCPE_D_OUT7: FDCPE port map (D_OUT(7),D_OUT_D(7),CLK_EXT,'0',NOT RESET);
|
|
D_OUT_D(7) <= ((NOT FCS AND NOT UDS AND NOT Z3_ADR_1 AND Z3_ADR(6) AND
|
|
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND NOT Z3_ADR(4) AND NOT Z3_ADR(5))
|
|
OR (NOT FCS AND NOT LDS AND NOT Z3_ADR_1 AND Z3_ADR(6) AND
|
|
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND NOT Z3_ADR(4) AND NOT Z3_ADR(5))
|
|
OR (NOT FCS AND NOT DS1 AND NOT Z3_ADR_1 AND Z3_ADR(6) AND
|
|
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND NOT Z3_ADR(4) AND NOT Z3_ADR(5))
|
|
OR (NOT FCS AND NOT DS0 AND NOT Z3_ADR_1 AND Z3_ADR(6) AND
|
|
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND NOT Z3_ADR(4) AND NOT Z3_ADR(5)));
|
|
|
|
|
|
|
|
|
|
|
|
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|
|
|
|
|
IDE_A(0) <= '1';
|
|
|
|
|
|
IDE_A(1) <= '1';
|
|
|
|
|
|
IDE_A(2) <= '1';
|
|
|
|
|
|
IDE_CS(0) <= '1';
|
|
|
|
|
|
IDE_CS(1) <= '1';
|
|
|
|
|
|
IDE_R <= '1';
|
|
|
|
|
|
IDE_W <= '1';
|
|
|
|
|
|
INT_OUT_I <= '0';
|
|
INT_OUT <= INT_OUT_I when INT_OUT_OE = '1' else 'Z';
|
|
INT_OUT_OE <= (LAN_INT_ENABLE AND NOT LAN_IRQ_OUT);
|
|
|
|
FDCPE_LAN_ACCESS: FDCPE port map (LAN_ACCESS,LAN_ACCESS_D,NOT FCS,NOT Z3_ADR_1/Z3_ADR_1_SETF__$INT,'0');
|
|
LAN_ACCESS_D <= ((NOT Z3)
|
|
OR (SHUT_UP)
|
|
OR ($OpTx$INV$205)
|
|
OR (Z3_ADR(10).EXP)
|
|
OR (D(9).PIN AND NOT LAN_BASEADR(9))
|
|
OR (NOT D(9).PIN AND LAN_BASEADR(9))
|
|
OR (D(11).PIN AND NOT LAN_BASEADR(11))
|
|
OR (NOT D(11).PIN AND LAN_BASEADR(11))
|
|
OR (D(15).PIN AND NOT LAN_BASEADR(15))
|
|
OR (EXP44_.EXP)
|
|
OR (D(12).PIN AND NOT LAN_BASEADR(12))
|
|
OR (NOT D(12).PIN AND LAN_BASEADR(12))
|
|
OR (D(10).PIN AND NOT LAN_BASEADR(10))
|
|
OR (NOT D(10).PIN AND LAN_BASEADR(10))
|
|
OR (NOT D(15).PIN AND LAN_BASEADR(15)));
|
|
|
|
FDCPE_LAN_A_INIT3: FDCPE port map (LAN_A_INIT(3),'0',CLK_EXT,'0',RESET);
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FDCPE_LAN_A_INIT6: FDCPE port map (LAN_A_INIT(6),NOT LAN_RST_SM_FSM_FFd1,CLK_EXT,'0',RESET);
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FTCPE_LAN_BASEADR0: FTCPE port map (LAN_BASEADR(0),LAN_BASEADR_T(0),CLK_EXT,'0',NOT RESET);
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LAN_BASEADR_T(0) <= ((NOT RW AND NOT FCS AND NOT UDS AND D(0).PIN AND NOT LAN_BASEADR(0) AND
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NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
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AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
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OR (NOT RW AND NOT FCS AND NOT LDS AND D(0).PIN AND NOT LAN_BASEADR(0) AND
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NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
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AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
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OR (NOT RW AND NOT FCS AND NOT DS1 AND D(0).PIN AND NOT LAN_BASEADR(0) AND
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NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
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AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
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OR (NOT RW AND NOT FCS AND NOT DS0 AND D(0).PIN AND NOT LAN_BASEADR(0) AND
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NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
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AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
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OR (NOT RW AND NOT FCS AND NOT UDS AND NOT D(0).PIN AND LAN_BASEADR(0) AND
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NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
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AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
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OR (NOT RW AND NOT FCS AND NOT LDS AND NOT D(0).PIN AND LAN_BASEADR(0) AND
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NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
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AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
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OR (NOT RW AND NOT FCS AND NOT DS1 AND NOT D(0).PIN AND LAN_BASEADR(0) AND
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NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
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AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
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OR (NOT RW AND NOT FCS AND NOT DS0 AND NOT D(0).PIN AND LAN_BASEADR(0) AND
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NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
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AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5)));
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FTCPE_LAN_BASEADR1: FTCPE port map (LAN_BASEADR(1),LAN_BASEADR_T(1),CLK_EXT,'0',NOT RESET);
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LAN_BASEADR_T(1) <= ((NOT RW AND NOT FCS AND NOT UDS AND D(1).PIN AND NOT LAN_BASEADR(1) AND
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NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
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AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
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OR (NOT RW AND NOT FCS AND NOT LDS AND D(1).PIN AND NOT LAN_BASEADR(1) AND
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NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
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AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
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OR (NOT RW AND NOT FCS AND NOT DS1 AND D(1).PIN AND NOT LAN_BASEADR(1) AND
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NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
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AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
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OR (NOT RW AND NOT FCS AND NOT DS0 AND D(1).PIN AND NOT LAN_BASEADR(1) AND
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NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
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AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
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OR (NOT RW AND NOT FCS AND NOT UDS AND NOT D(1).PIN AND LAN_BASEADR(1) AND
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NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
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AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
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OR (NOT RW AND NOT FCS AND NOT LDS AND NOT D(1).PIN AND LAN_BASEADR(1) AND
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NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
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AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
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OR (NOT RW AND NOT FCS AND NOT DS1 AND NOT D(1).PIN AND LAN_BASEADR(1) AND
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NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
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AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
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OR (NOT RW AND NOT FCS AND NOT DS0 AND NOT D(1).PIN AND LAN_BASEADR(1) AND
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NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
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AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5)));
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FTCPE_LAN_BASEADR2: FTCPE port map (LAN_BASEADR(2),LAN_BASEADR_T(2),CLK_EXT,'0',NOT RESET);
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LAN_BASEADR_T(2) <= ((NOT RW AND NOT FCS AND NOT UDS AND D(2).PIN AND NOT LAN_BASEADR(2) AND
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NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
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AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
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OR (NOT RW AND NOT FCS AND NOT LDS AND D(2).PIN AND NOT LAN_BASEADR(2) AND
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NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
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AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
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OR (NOT RW AND NOT FCS AND NOT DS1 AND D(2).PIN AND NOT LAN_BASEADR(2) AND
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NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
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AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
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OR (NOT RW AND NOT FCS AND NOT DS0 AND D(2).PIN AND NOT LAN_BASEADR(2) AND
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NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
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AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
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OR (NOT RW AND NOT FCS AND NOT UDS AND NOT D(2).PIN AND LAN_BASEADR(2) AND
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NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
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AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
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OR (NOT RW AND NOT FCS AND NOT LDS AND NOT D(2).PIN AND LAN_BASEADR(2) AND
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NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
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AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
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OR (NOT RW AND NOT FCS AND NOT DS1 AND NOT D(2).PIN AND LAN_BASEADR(2) AND
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NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
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AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
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OR (NOT RW AND NOT FCS AND NOT DS0 AND NOT D(2).PIN AND LAN_BASEADR(2) AND
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NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
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AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5)));
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FTCPE_LAN_BASEADR3: FTCPE port map (LAN_BASEADR(3),LAN_BASEADR_T(3),CLK_EXT,'0',NOT RESET);
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LAN_BASEADR_T(3) <= ((NOT RW AND NOT FCS AND NOT UDS AND D(3).PIN AND NOT LAN_BASEADR(3) AND
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NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
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AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
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OR (NOT RW AND NOT FCS AND NOT DS1 AND D(3).PIN AND NOT LAN_BASEADR(3) AND
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NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
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AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
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OR (NOT RW AND NOT FCS AND NOT DS0 AND D(3).PIN AND NOT LAN_BASEADR(3) AND
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NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
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AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
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OR (NOT RW AND NOT FCS AND NOT LDS AND D(3).PIN AND NOT LAN_BASEADR(3) AND
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NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
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AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
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OR (NOT RW AND NOT FCS AND NOT UDS AND NOT D(3).PIN AND LAN_BASEADR(3) AND
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NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
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AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
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OR (NOT RW AND NOT FCS AND NOT LDS AND NOT D(3).PIN AND LAN_BASEADR(3) AND
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NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
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AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
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OR (NOT RW AND NOT FCS AND NOT DS1 AND NOT D(3).PIN AND LAN_BASEADR(3) AND
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NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
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AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
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OR (NOT RW AND NOT FCS AND NOT DS0 AND NOT D(3).PIN AND LAN_BASEADR(3) AND
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NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
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AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5)));
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FTCPE_LAN_BASEADR4: FTCPE port map (LAN_BASEADR(4),LAN_BASEADR_T(4),CLK_EXT,'0',NOT RESET);
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LAN_BASEADR_T(4) <= ((NOT RW AND NOT FCS AND NOT UDS AND D(4).PIN AND NOT LAN_BASEADR(4) AND
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NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
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AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
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OR (NOT RW AND NOT FCS AND NOT LDS AND D(4).PIN AND NOT LAN_BASEADR(4) AND
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NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
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AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
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OR (NOT RW AND NOT FCS AND NOT LDS AND NOT D(4).PIN AND LAN_BASEADR(4) AND
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NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
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AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
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OR (NOT RW AND NOT FCS AND NOT DS1 AND D(4).PIN AND NOT LAN_BASEADR(4) AND
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NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
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AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
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OR (NOT RW AND NOT FCS AND NOT DS0 AND D(4).PIN AND NOT LAN_BASEADR(4) AND
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NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
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AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
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OR (NOT RW AND NOT FCS AND NOT UDS AND NOT D(4).PIN AND LAN_BASEADR(4) AND
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NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
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AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
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OR (NOT RW AND NOT FCS AND NOT DS1 AND NOT D(4).PIN AND LAN_BASEADR(4) AND
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NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
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AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
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OR (NOT RW AND NOT FCS AND NOT DS0 AND NOT D(4).PIN AND LAN_BASEADR(4) AND
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NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
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AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5)));
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FTCPE_LAN_BASEADR5: FTCPE port map (LAN_BASEADR(5),LAN_BASEADR_T(5),CLK_EXT,'0',NOT RESET);
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LAN_BASEADR_T(5) <= ((NOT RW AND NOT FCS AND NOT UDS AND D(5).PIN AND NOT LAN_BASEADR(5) AND
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NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
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AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
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OR (NOT RW AND NOT FCS AND NOT LDS AND D(5).PIN AND NOT LAN_BASEADR(5) AND
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NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
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AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
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OR (NOT RW AND NOT FCS AND NOT DS1 AND D(5).PIN AND NOT LAN_BASEADR(5) AND
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NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
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AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
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OR (NOT RW AND NOT FCS AND NOT DS0 AND D(5).PIN AND NOT LAN_BASEADR(5) AND
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NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
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AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
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OR (NOT RW AND NOT FCS AND NOT UDS AND NOT D(5).PIN AND LAN_BASEADR(5) AND
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NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
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AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
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OR (NOT RW AND NOT FCS AND NOT LDS AND NOT D(5).PIN AND LAN_BASEADR(5) AND
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NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
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AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
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OR (NOT RW AND NOT FCS AND NOT DS1 AND NOT D(5).PIN AND LAN_BASEADR(5) AND
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NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
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AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
|
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OR (NOT RW AND NOT FCS AND NOT DS0 AND NOT D(5).PIN AND LAN_BASEADR(5) AND
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NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
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AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5)));
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FTCPE_LAN_BASEADR6: FTCPE port map (LAN_BASEADR(6),LAN_BASEADR_T(6),CLK_EXT,'0',NOT RESET);
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LAN_BASEADR_T(6) <= ((NOT RW AND NOT FCS AND NOT UDS AND D(6).PIN AND NOT LAN_BASEADR(6) AND
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NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
|
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AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
|
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OR (NOT RW AND NOT FCS AND NOT LDS AND D(6).PIN AND NOT LAN_BASEADR(6) AND
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NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
|
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AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
|
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OR (NOT RW AND NOT FCS AND NOT DS1 AND D(6).PIN AND NOT LAN_BASEADR(6) AND
|
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NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
|
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AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
|
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OR (NOT RW AND NOT FCS AND NOT DS0 AND D(6).PIN AND NOT LAN_BASEADR(6) AND
|
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NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
|
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AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
|
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OR (NOT RW AND NOT FCS AND NOT UDS AND NOT D(6).PIN AND LAN_BASEADR(6) AND
|
|
NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
|
|
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
|
|
OR (NOT RW AND NOT FCS AND NOT LDS AND NOT D(6).PIN AND LAN_BASEADR(6) AND
|
|
NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
|
|
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
|
|
OR (NOT RW AND NOT FCS AND NOT DS1 AND NOT D(6).PIN AND LAN_BASEADR(6) AND
|
|
NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
|
|
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
|
|
OR (NOT RW AND NOT FCS AND NOT DS0 AND NOT D(6).PIN AND LAN_BASEADR(6) AND
|
|
NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
|
|
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5)));
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FTCPE_LAN_BASEADR7: FTCPE port map (LAN_BASEADR(7),LAN_BASEADR_T(7),CLK_EXT,'0',NOT RESET);
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LAN_BASEADR_T(7) <= ((NOT RW AND NOT FCS AND NOT UDS AND D(7).PIN AND NOT LAN_BASEADR(7) AND
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NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
|
|
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
|
|
OR (NOT RW AND NOT FCS AND NOT LDS AND D(7).PIN AND NOT LAN_BASEADR(7) AND
|
|
NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
|
|
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
|
|
OR (NOT RW AND NOT FCS AND NOT LDS AND NOT D(7).PIN AND LAN_BASEADR(7) AND
|
|
NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
|
|
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
|
|
OR (NOT RW AND NOT FCS AND NOT DS1 AND D(7).PIN AND NOT LAN_BASEADR(7) AND
|
|
NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
|
|
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
|
|
OR (NOT RW AND NOT FCS AND NOT DS0 AND D(7).PIN AND NOT LAN_BASEADR(7) AND
|
|
NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
|
|
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
|
|
OR (NOT RW AND NOT FCS AND NOT UDS AND NOT D(7).PIN AND LAN_BASEADR(7) AND
|
|
NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
|
|
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
|
|
OR (NOT RW AND NOT FCS AND NOT DS1 AND NOT D(7).PIN AND LAN_BASEADR(7) AND
|
|
NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
|
|
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
|
|
OR (NOT RW AND NOT FCS AND NOT DS0 AND NOT D(7).PIN AND LAN_BASEADR(7) AND
|
|
NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
|
|
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5)));
|
|
|
|
FTCPE_LAN_BASEADR8: FTCPE port map (LAN_BASEADR(8),LAN_BASEADR_T(8),CLK_EXT,'0',NOT RESET);
|
|
LAN_BASEADR_T(8) <= ((LAN_BASEADR(9).EXP)
|
|
OR (D(8).PIN AND NOT RW AND NOT FCS AND NOT UDS AND NOT LAN_BASEADR(8) AND
|
|
NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
|
|
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
|
|
OR (D(8).PIN AND NOT RW AND NOT FCS AND NOT DS1 AND NOT LAN_BASEADR(8) AND
|
|
NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
|
|
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
|
|
OR (NOT D(8).PIN AND NOT RW AND NOT FCS AND NOT UDS AND LAN_BASEADR(8) AND
|
|
NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
|
|
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
|
|
OR (NOT D(8).PIN AND NOT RW AND NOT FCS AND NOT LDS AND LAN_BASEADR(8) AND
|
|
NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
|
|
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
|
|
OR (NOT D(8).PIN AND NOT RW AND NOT FCS AND NOT DS0 AND LAN_BASEADR(8) AND
|
|
NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
|
|
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
|
|
OR (NOT D(8).PIN AND NOT RW AND NOT FCS AND NOT DS1 AND LAN_BASEADR(8) AND
|
|
NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
|
|
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5)));
|
|
|
|
FTCPE_LAN_BASEADR9: FTCPE port map (LAN_BASEADR(9),LAN_BASEADR_T(9),CLK_EXT,'0',NOT RESET);
|
|
LAN_BASEADR_T(9) <= (($OpTx$FX_SC$119__$INT.EXP)
|
|
OR (D(9).PIN AND NOT RW AND NOT FCS AND NOT UDS AND NOT LAN_BASEADR(9) AND
|
|
NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
|
|
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
|
|
OR (D(9).PIN AND NOT RW AND NOT FCS AND NOT DS1 AND NOT LAN_BASEADR(9) AND
|
|
NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
|
|
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
|
|
OR (D(9).PIN AND NOT RW AND NOT FCS AND NOT DS0 AND NOT LAN_BASEADR(9) AND
|
|
NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
|
|
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
|
|
OR (NOT D(9).PIN AND NOT RW AND NOT FCS AND NOT LDS AND LAN_BASEADR(9) AND
|
|
NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
|
|
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
|
|
OR (NOT D(9).PIN AND NOT RW AND NOT FCS AND NOT DS0 AND LAN_BASEADR(9) AND
|
|
NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
|
|
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
|
|
OR (NOT D(9).PIN AND NOT RW AND NOT FCS AND NOT UDS AND LAN_BASEADR(9) AND
|
|
NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
|
|
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
|
|
OR (NOT D(9).PIN AND NOT RW AND NOT FCS AND NOT DS1 AND LAN_BASEADR(9) AND
|
|
NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
|
|
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5)));
|
|
|
|
FTCPE_LAN_BASEADR10: FTCPE port map (LAN_BASEADR(10),LAN_BASEADR_T(10),CLK_EXT,'0',NOT RESET);
|
|
LAN_BASEADR_T(10) <= ((D(10).PIN AND NOT RW AND NOT FCS AND NOT UDS AND NOT LAN_BASEADR(10) AND
|
|
NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
|
|
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
|
|
OR (D(10).PIN AND NOT RW AND NOT FCS AND NOT DS1 AND NOT LAN_BASEADR(10) AND
|
|
NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
|
|
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
|
|
OR (D(10).PIN AND NOT RW AND NOT FCS AND NOT DS0 AND NOT LAN_BASEADR(10) AND
|
|
NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
|
|
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
|
|
OR (D(10).PIN AND NOT RW AND NOT FCS AND NOT LDS AND NOT LAN_BASEADR(10) AND
|
|
NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
|
|
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
|
|
OR (NOT D(10).PIN AND NOT RW AND NOT FCS AND NOT UDS AND LAN_BASEADR(10) AND
|
|
NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
|
|
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
|
|
OR (NOT D(10).PIN AND NOT RW AND NOT FCS AND NOT LDS AND LAN_BASEADR(10) AND
|
|
NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
|
|
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
|
|
OR (NOT D(10).PIN AND NOT RW AND NOT FCS AND NOT DS1 AND LAN_BASEADR(10) AND
|
|
NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
|
|
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
|
|
OR (NOT D(10).PIN AND NOT RW AND NOT FCS AND NOT DS0 AND LAN_BASEADR(10) AND
|
|
NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
|
|
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5)));
|
|
|
|
FTCPE_LAN_BASEADR11: FTCPE port map (LAN_BASEADR(11),LAN_BASEADR_T(11),CLK_EXT,'0',NOT RESET);
|
|
LAN_BASEADR_T(11) <= ((D(11).PIN AND NOT RW AND NOT FCS AND NOT UDS AND NOT LAN_BASEADR(11) AND
|
|
NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
|
|
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
|
|
OR (D(11).PIN AND NOT RW AND NOT FCS AND NOT LDS AND NOT LAN_BASEADR(11) AND
|
|
NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
|
|
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
|
|
OR (D(11).PIN AND NOT RW AND NOT FCS AND NOT DS1 AND NOT LAN_BASEADR(11) AND
|
|
NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
|
|
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
|
|
OR (D(11).PIN AND NOT RW AND NOT FCS AND NOT DS0 AND NOT LAN_BASEADR(11) AND
|
|
NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
|
|
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
|
|
OR (NOT D(11).PIN AND NOT RW AND NOT FCS AND NOT UDS AND LAN_BASEADR(11) AND
|
|
NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
|
|
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
|
|
OR (NOT D(11).PIN AND NOT RW AND NOT FCS AND NOT LDS AND LAN_BASEADR(11) AND
|
|
NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
|
|
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
|
|
OR (NOT D(11).PIN AND NOT RW AND NOT FCS AND NOT DS1 AND LAN_BASEADR(11) AND
|
|
NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
|
|
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
|
|
OR (NOT D(11).PIN AND NOT RW AND NOT FCS AND NOT DS0 AND LAN_BASEADR(11) AND
|
|
NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
|
|
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5)));
|
|
|
|
FTCPE_LAN_BASEADR12: FTCPE port map (LAN_BASEADR(12),LAN_BASEADR_T(12),CLK_EXT,'0',NOT RESET);
|
|
LAN_BASEADR_T(12) <= ((D(12).PIN AND NOT RW AND NOT FCS AND NOT UDS AND NOT LAN_BASEADR(12) AND
|
|
NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
|
|
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
|
|
OR (D(12).PIN AND NOT RW AND NOT FCS AND NOT LDS AND NOT LAN_BASEADR(12) AND
|
|
NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
|
|
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
|
|
OR (D(12).PIN AND NOT RW AND NOT FCS AND NOT DS1 AND NOT LAN_BASEADR(12) AND
|
|
NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
|
|
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
|
|
OR (D(12).PIN AND NOT RW AND NOT FCS AND NOT DS0 AND NOT LAN_BASEADR(12) AND
|
|
NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
|
|
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
|
|
OR (NOT D(12).PIN AND NOT RW AND NOT FCS AND NOT UDS AND LAN_BASEADR(12) AND
|
|
NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
|
|
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
|
|
OR (NOT D(12).PIN AND NOT RW AND NOT FCS AND NOT LDS AND LAN_BASEADR(12) AND
|
|
NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
|
|
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
|
|
OR (NOT D(12).PIN AND NOT RW AND NOT FCS AND NOT DS1 AND LAN_BASEADR(12) AND
|
|
NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
|
|
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
|
|
OR (NOT D(12).PIN AND NOT RW AND NOT FCS AND NOT DS0 AND LAN_BASEADR(12) AND
|
|
NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
|
|
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5)));
|
|
|
|
FTCPE_LAN_BASEADR13: FTCPE port map (LAN_BASEADR(13),LAN_BASEADR_T(13),CLK_EXT,'0',NOT RESET);
|
|
LAN_BASEADR_T(13) <= ((D(13).PIN AND NOT RW AND NOT FCS AND NOT UDS AND NOT LAN_BASEADR(13) AND
|
|
NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
|
|
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
|
|
OR (D(13).PIN AND NOT RW AND NOT FCS AND NOT DS1 AND NOT LAN_BASEADR(13) AND
|
|
NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
|
|
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
|
|
OR (D(13).PIN AND NOT RW AND NOT FCS AND NOT LDS AND NOT LAN_BASEADR(13) AND
|
|
NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
|
|
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
|
|
OR (D(13).PIN AND NOT RW AND NOT FCS AND NOT DS0 AND NOT LAN_BASEADR(13) AND
|
|
NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
|
|
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
|
|
OR (NOT D(13).PIN AND NOT RW AND NOT FCS AND NOT UDS AND LAN_BASEADR(13) AND
|
|
NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
|
|
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
|
|
OR (NOT D(13).PIN AND NOT RW AND NOT FCS AND NOT LDS AND LAN_BASEADR(13) AND
|
|
NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
|
|
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
|
|
OR (NOT D(13).PIN AND NOT RW AND NOT FCS AND NOT DS1 AND LAN_BASEADR(13) AND
|
|
NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
|
|
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
|
|
OR (NOT D(13).PIN AND NOT RW AND NOT FCS AND NOT DS0 AND LAN_BASEADR(13) AND
|
|
NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
|
|
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5)));
|
|
|
|
FTCPE_LAN_BASEADR14: FTCPE port map (LAN_BASEADR(14),LAN_BASEADR_T(14),CLK_EXT,'0',NOT RESET);
|
|
LAN_BASEADR_T(14) <= ((D(14).PIN AND NOT RW AND NOT FCS AND NOT UDS AND NOT LAN_BASEADR(14) AND
|
|
NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
|
|
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
|
|
OR (D(14).PIN AND NOT RW AND NOT FCS AND NOT LDS AND NOT LAN_BASEADR(14) AND
|
|
NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
|
|
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
|
|
OR (D(14).PIN AND NOT RW AND NOT FCS AND NOT DS1 AND NOT LAN_BASEADR(14) AND
|
|
NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
|
|
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
|
|
OR (D(14).PIN AND NOT RW AND NOT FCS AND NOT DS0 AND NOT LAN_BASEADR(14) AND
|
|
NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
|
|
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
|
|
OR (NOT D(14).PIN AND NOT RW AND NOT FCS AND NOT UDS AND LAN_BASEADR(14) AND
|
|
NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
|
|
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
|
|
OR (NOT D(14).PIN AND NOT RW AND NOT FCS AND NOT LDS AND LAN_BASEADR(14) AND
|
|
NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
|
|
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
|
|
OR (NOT D(14).PIN AND NOT RW AND NOT FCS AND NOT DS1 AND LAN_BASEADR(14) AND
|
|
NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
|
|
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
|
|
OR (NOT D(14).PIN AND NOT RW AND NOT FCS AND NOT DS0 AND LAN_BASEADR(14) AND
|
|
NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
|
|
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5)));
|
|
|
|
FTCPE_LAN_BASEADR15: FTCPE port map (LAN_BASEADR(15),LAN_BASEADR_T(15),CLK_EXT,'0',NOT RESET);
|
|
LAN_BASEADR_T(15) <= ((D(15).PIN AND NOT RW AND NOT FCS AND NOT UDS AND NOT LAN_BASEADR(15) AND
|
|
NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
|
|
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
|
|
OR (D(15).PIN AND NOT RW AND NOT FCS AND NOT LDS AND NOT LAN_BASEADR(15) AND
|
|
NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
|
|
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
|
|
OR (D(15).PIN AND NOT RW AND NOT FCS AND NOT DS1 AND NOT LAN_BASEADR(15) AND
|
|
NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
|
|
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
|
|
OR (D(15).PIN AND NOT RW AND NOT FCS AND NOT DS0 AND NOT LAN_BASEADR(15) AND
|
|
NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
|
|
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
|
|
OR (NOT D(15).PIN AND NOT RW AND NOT FCS AND NOT UDS AND LAN_BASEADR(15) AND
|
|
NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
|
|
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
|
|
OR (NOT D(15).PIN AND NOT RW AND NOT FCS AND NOT LDS AND LAN_BASEADR(15) AND
|
|
NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
|
|
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
|
|
OR (NOT D(15).PIN AND NOT RW AND NOT FCS AND NOT DS1 AND LAN_BASEADR(15) AND
|
|
NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
|
|
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5))
|
|
OR (NOT D(15).PIN AND NOT RW AND NOT FCS AND NOT DS0 AND LAN_BASEADR(15) AND
|
|
NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
|
|
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5)));
|
|
|
|
|
|
LAN_CFG_I(1) <= '0';
|
|
LAN_CFG(1) <= LAN_CFG_I(1) when LAN_CFG_OE(1) = '1' else 'Z';
|
|
LAN_CFG_OE(1) <= '0';
|
|
|
|
|
|
LAN_CFG_I(2) <= '0';
|
|
LAN_CFG(2) <= LAN_CFG_I(2) when LAN_CFG_OE(2) = '1' else 'Z';
|
|
LAN_CFG_OE(2) <= '0';
|
|
|
|
|
|
LAN_CFG_I(3) <= '0';
|
|
LAN_CFG(3) <= LAN_CFG_I(3) when LAN_CFG_OE(3) = '1' else 'Z';
|
|
LAN_CFG_OE(3) <= '0';
|
|
|
|
|
|
LAN_CFG_I(4) <= '0';
|
|
LAN_CFG(4) <= LAN_CFG_I(4) when LAN_CFG_OE(4) = '1' else 'Z';
|
|
LAN_CFG_OE(4) <= '0';
|
|
|
|
|
|
LAN_CS <= ((RESET AND LAN_ACCESS)
|
|
OR (NOT RESET AND LAN_CS_RST));
|
|
|
|
FDCPE_LAN_CS_RST: FDCPE port map (LAN_CS_RST,LAN_CS_RST_D,CLK_EXT,RESET,'0');
|
|
LAN_CS_RST_D <= (NOT LAN_RST_SM_FSM_FFd2 AND NOT LAN_RST_SM_FSM_FFd3);
|
|
|
|
FDCPE_LAN_D_INIT1: FDCPE port map (LAN_D_INIT(1),LAN_RST_SM_FSM_FFd1,CLK_EXT,RESET,'0');
|
|
|
|
FDCPE_LAN_D_INIT8: FDCPE port map (LAN_D_INIT(8),NOT LAN_RST_SM_FSM_FFd1,CLK_EXT,RESET,'0');
|
|
|
|
FTCPE_LAN_INT_ENABLE: FTCPE port map (LAN_INT_ENABLE,LAN_INT_ENABLE_T,CLK_EXT,NOT RESET,'0');
|
|
LAN_INT_ENABLE_T <= ((D(15).PIN AND NOT RW AND NOT FCS AND NOT UDS AND NOT LAN_INT_ENABLE AND
|
|
LAN_ACCESS AND Z3_ADR(13))
|
|
OR (NOT D(15).PIN AND NOT RW AND NOT FCS AND NOT UDS AND LAN_INT_ENABLE AND
|
|
LAN_ACCESS AND Z3_ADR(13))
|
|
OR (NOT RW AND NOT FCS AND UDS AND NOT DS1 AND LAN_INT_ENABLE AND
|
|
LAN_ACCESS AND Z3_ADR(13) AND NOT A(23).PIN)
|
|
OR (NOT RW AND NOT FCS AND UDS AND NOT DS1 AND NOT LAN_INT_ENABLE AND
|
|
LAN_ACCESS AND Z3_ADR(13) AND A(23).PIN));
|
|
|
|
FDCPE_LAN_IRQ_D0: FDCPE port map (LAN_IRQ_D0,LAN_INT,CLK_EXT,'0',NOT RESET);
|
|
|
|
FDCPE_LAN_IRQ_OUT: FDCPE port map (LAN_IRQ_OUT,LAN_IRQ_OUT_D,CLK_EXT,'0',NOT RESET);
|
|
LAN_IRQ_OUT_D <= ((LAN_INT)
|
|
OR (LAN_IRQ_OUT AND NOT LAN_IRQ_D0));
|
|
|
|
|
|
LAN_RD <= (NOT FCS AND RESET AND LAN_RD_S);
|
|
|
|
FDCPE_LAN_RD_S: FDCPE port map (LAN_RD_S,LAN_RD_S_D,CLK_EXT,LAN_SM_RST,'0');
|
|
LAN_RD_S_D <= ((RW AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3)
|
|
OR (LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd1 AND
|
|
NOT LAN_SM_FSM_FFd3)
|
|
OR (LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2));
|
|
|
|
FDCPE_LAN_READY: FDCPE port map (LAN_READY,LAN_READY_D,CLK_EXT,LAN_SM_RST,'0');
|
|
LAN_READY_D <= ((DS1 AND DS0 AND LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2)
|
|
OR (DS1 AND DS0 AND LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd3)
|
|
OR (LAN_SM_FSM_FFd1 AND LAN_SM_FSM_FFd3)
|
|
OR (DS1 AND DS0 AND LAN_SM_FSM_FFd1)
|
|
OR (LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND
|
|
LAN_SM_FSM_FFd3)
|
|
OR (NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
|
|
NOT LAN_SM_FSM_FFd1 AND NOT LAN_SM_FSM_FFd3));
|
|
|
|
FTCPE_LAN_RST_SM_FSM_FFd1: FTCPE port map (LAN_RST_SM_FSM_FFd1,LAN_RST_SM_FSM_FFd1_T,CLK_EXT,RESET,'0');
|
|
LAN_RST_SM_FSM_FFd1_T <= (NOT LAN_RST_SM_FSM_FFd1 AND LAN_RST_SM_FSM_FFd2 AND
|
|
NOT LAN_RST_SM_FSM_FFd3);
|
|
|
|
FDCPE_LAN_RST_SM_FSM_FFd2: FDCPE port map (LAN_RST_SM_FSM_FFd2,LAN_RST_SM_FSM_FFd2_D,CLK_EXT,RESET,'0');
|
|
LAN_RST_SM_FSM_FFd2_D <= ((NOT LAN_RST_SM_FSM_FFd1 AND LAN_RST_SM_FSM_FFd3)
|
|
OR (LAN_RST_SM_FSM_FFd2 AND NOT LAN_RST_SM_FSM_FFd3));
|
|
|
|
FDCPE_LAN_RST_SM_FSM_FFd3: FDCPE port map (LAN_RST_SM_FSM_FFd3,LAN_RST_SM_FSM_FFd3_D,CLK_EXT,RESET,'0');
|
|
LAN_RST_SM_FSM_FFd3_D <= LAN_RST_SM_FSM_FFd1
|
|
XOR
|
|
LAN_RST_SM_FSM_FFd3_D <= LAN_RST_SM_FSM_FFd2;
|
|
|
|
FTCPE_LAN_SM_FSM_FFd1: FTCPE port map (LAN_SM_FSM_FFd1,LAN_SM_FSM_FFd1_T,CLK_EXT,LAN_SM_RST,'0');
|
|
LAN_SM_FSM_FFd1_T <= ((NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd1 AND
|
|
LAN_SM_FSM_FFd3)
|
|
OR (NOT DS1 AND LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd1 AND
|
|
NOT LAN_SM_FSM_FFd3)
|
|
OR (NOT DS0 AND LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd1 AND
|
|
NOT LAN_SM_FSM_FFd3));
|
|
|
|
FDCPE_LAN_SM_FSM_FFd2: FDCPE port map (LAN_SM_FSM_FFd2,LAN_SM_FSM_FFd2_D,CLK_EXT,LAN_SM_RST,'0');
|
|
LAN_SM_FSM_FFd2_D <= ((LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
|
|
NOT LAN_SM_FSM_FFd1 AND NOT LAN_SM_FSM_FFd3)
|
|
OR (RW AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND
|
|
NOT LAN_SM_FSM_FFd1 AND NOT LAN_SM_FSM_FFd3)
|
|
OR (NOT UDS AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND
|
|
NOT LAN_SM_FSM_FFd1 AND NOT LAN_SM_FSM_FFd3)
|
|
OR (NOT LDS AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND
|
|
NOT LAN_SM_FSM_FFd1 AND NOT LAN_SM_FSM_FFd3));
|
|
|
|
FTCPE_LAN_SM_FSM_FFd3: FTCPE port map (LAN_SM_FSM_FFd3,LAN_SM_FSM_FFd3_T,CLK_EXT,LAN_SM_RST,'0');
|
|
LAN_SM_FSM_FFd3_T <= ((LAN_SM_FSM_FFd1 AND LAN_SM_FSM_FFd3)
|
|
OR (RW AND NOT UDS AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd3)
|
|
OR (RW AND NOT LDS AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd3)
|
|
OR (DS1 AND DS0 AND LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd1)
|
|
OR (DS1 AND DS0 AND LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd3)
|
|
OR (NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2));
|
|
|
|
FDCPE_LAN_SM_FSM_FFd4: FDCPE port map (LAN_SM_FSM_FFd4,LAN_SM_FSM_FFd4_D,CLK_EXT,LAN_SM_RST,'0');
|
|
LAN_SM_FSM_FFd4_D <= ((RW AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3)
|
|
OR (LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND
|
|
NOT LAN_SM_FSM_FFd3)
|
|
OR (NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd1 AND
|
|
NOT LAN_SM_FSM_FFd3)
|
|
OR (LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1 AND
|
|
LAN_SM_FSM_FFd3)
|
|
OR (DS1 AND DS0 AND LAN_SM_FSM_FFd1 AND NOT LAN_SM_FSM_FFd3)
|
|
OR (LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
|
|
NOT LAN_SM_FSM_FFd1));
|
|
|
|
FDCPE_LAN_SM_RST: FDCPE port map (LAN_SM_RST,LAN_SM_RST_D,CLK_EXT,'0','0');
|
|
LAN_SM_RST_D <= ((NOT FCS AND NOT UDS AND RESET AND LAN_ACCESS AND NOT Z3_ADR(13))
|
|
OR (NOT FCS AND NOT LDS AND RESET AND LAN_ACCESS AND NOT Z3_ADR(13))
|
|
OR (NOT FCS AND NOT DS1 AND RESET AND LAN_ACCESS AND NOT Z3_ADR(13))
|
|
OR (NOT FCS AND NOT DS0 AND RESET AND LAN_ACCESS AND NOT Z3_ADR(13)));
|
|
|
|
|
|
LAN_WRH <= ((FCS AND LAN_WR_RST)
|
|
OR (NOT RESET AND LAN_WR_RST)
|
|
OR (NOT FCS AND RESET AND LAN_WRH_S));
|
|
|
|
FDCPE_LAN_WRH_S: FDCPE port map (LAN_WRH_S,LAN_WRH_S_D,CLK_EXT,LAN_SM_RST,'0');
|
|
LAN_WRH_S_D <= ((NOT LDS AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND
|
|
LAN_SM_FSM_FFd3)
|
|
OR (NOT DS0 AND NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
|
|
NOT LAN_SM_FSM_FFd1 AND LAN_SM_FSM_FFd3));
|
|
|
|
|
|
LAN_WRL <= ((FCS AND LAN_WR_RST)
|
|
OR (NOT RESET AND LAN_WR_RST)
|
|
OR (NOT FCS AND RESET AND LAN_WRL_S));
|
|
|
|
FDCPE_LAN_WRL_S: FDCPE port map (LAN_WRL_S,LAN_WRL_S_D,CLK_EXT,LAN_SM_RST,'0');
|
|
LAN_WRL_S_D <= ((NOT UDS AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND
|
|
LAN_SM_FSM_FFd3)
|
|
OR (NOT DS1 AND NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
|
|
NOT LAN_SM_FSM_FFd1 AND LAN_SM_FSM_FFd3));
|
|
|
|
FDCPE_LAN_WR_RST: FDCPE port map (LAN_WR_RST,LAN_WR_RST_D,CLK_EXT,RESET,'0');
|
|
LAN_WR_RST_D <= (LAN_RST_SM_FSM_FFd2 AND LAN_RST_SM_FSM_FFd3);
|
|
|
|
|
|
MTACK_I <= '0';
|
|
MTACK <= MTACK_I when MTACK_OE = '1' else 'Z';
|
|
MTACK_OE <= '0';
|
|
|
|
|
|
N0$BUF7/N0$BUF7_TRST__$INT <= ((FCS)
|
|
OR (NOT AUTOCONFIG_ACCESS AND NOT CONFIG_READY AND NOT LAN_READY));
|
|
|
|
|
|
OVR_I <= '0';
|
|
OVR <= OVR_I when OVR_OE = '1' else 'Z';
|
|
OVR_OE <= '0';
|
|
|
|
|
|
OWN_I <= '0';
|
|
OWN <= OWN_I when OWN_OE = '1' else 'Z';
|
|
OWN_OE <= '0';
|
|
|
|
|
|
ROM_B(0) <= '1';
|
|
|
|
|
|
ROM_B(1) <= '1';
|
|
|
|
|
|
ROM_OE <= '1';
|
|
|
|
FTCPE_SHUT_UP: FTCPE port map (SHUT_UP,SHUT_UP_T,CLK_EXT,'0',NOT RESET);
|
|
SHUT_UP_T <= ((NOT RW AND NOT FCS AND NOT UDS AND NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND
|
|
Z3_ADR_0 AND NOT Z3_ADR(6) AND AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND
|
|
Z3_ADR(4) AND NOT Z3_ADR(5) AND SHUT_UP)
|
|
OR (NOT RW AND NOT FCS AND NOT LDS AND NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND
|
|
Z3_ADR_0 AND NOT Z3_ADR(6) AND AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND
|
|
Z3_ADR(4) AND NOT Z3_ADR(5) AND SHUT_UP)
|
|
OR (NOT RW AND NOT FCS AND NOT DS1 AND NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND
|
|
Z3_ADR_0 AND NOT Z3_ADR(6) AND AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND
|
|
Z3_ADR(4) AND NOT Z3_ADR(5) AND SHUT_UP)
|
|
OR (NOT RW AND NOT FCS AND NOT DS0 AND NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND
|
|
Z3_ADR_0 AND NOT Z3_ADR(6) AND AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND
|
|
Z3_ADR(4) AND NOT Z3_ADR(5) AND SHUT_UP));
|
|
|
|
|
|
SLAVE <= ((FCS)
|
|
OR (NOT LAN_ACCESS AND NOT AUTOCONFIG_ACCESS));
|
|
|
|
FDCPE_Z3_ADR2: FDCPE port map (Z3_ADR(2),A(4),NOT FCS,'0',NOT Z3_ADR_1/Z3_ADR_1_SETF__$INT);
|
|
|
|
FDCPE_Z3_ADR3: FDCPE port map (Z3_ADR(3),A(5),NOT FCS,'0',NOT Z3_ADR_1/Z3_ADR_1_SETF__$INT);
|
|
|
|
FDCPE_Z3_ADR4: FDCPE port map (Z3_ADR(4),A(6),NOT FCS,'0',NOT Z3_ADR_1/Z3_ADR_1_SETF__$INT);
|
|
|
|
FDCPE_Z3_ADR5: FDCPE port map (Z3_ADR(5),A(7),NOT FCS,'0',NOT Z3_ADR_1/Z3_ADR_1_SETF__$INT);
|
|
|
|
FDCPE_Z3_ADR6: FDCPE port map (Z3_ADR(6),A(8).PIN,NOT FCS,'0',NOT Z3_ADR_1/Z3_ADR_1_SETF__$INT);
|
|
|
|
FDCPE_Z3_ADR7: FDCPE port map (Z3_ADR(7),A(9).PIN,NOT FCS,'0',NOT Z3_ADR_1/Z3_ADR_1_SETF__$INT);
|
|
|
|
FDCPE_Z3_ADR8: FDCPE port map (Z3_ADR(8),A(10).PIN,NOT FCS,'0',NOT Z3_ADR_1/Z3_ADR_1_SETF__$INT);
|
|
|
|
FDCPE_Z3_ADR9: FDCPE port map (Z3_ADR(9),A(11).PIN,NOT FCS,'0',NOT Z3_ADR_1/Z3_ADR_1_SETF__$INT);
|
|
|
|
FDCPE_Z3_ADR10: FDCPE port map (Z3_ADR(10),A(12).PIN,NOT FCS,'0',NOT Z3_ADR_1/Z3_ADR_1_SETF__$INT);
|
|
|
|
FDCPE_Z3_ADR11: FDCPE port map (Z3_ADR(11),A(13).PIN,NOT FCS,'0',NOT Z3_ADR_1/Z3_ADR_1_SETF__$INT);
|
|
|
|
FDCPE_Z3_ADR12: FDCPE port map (Z3_ADR(12),A(14).PIN,NOT FCS,'0',NOT Z3_ADR_1/Z3_ADR_1_SETF__$INT);
|
|
|
|
FDCPE_Z3_ADR13: FDCPE port map (Z3_ADR(13),A(15).PIN,NOT FCS,'0',NOT Z3_ADR_1/Z3_ADR_1_SETF__$INT);
|
|
|
|
FDCPE_Z3_ADR_0: FDCPE port map (Z3_ADR_0,A(2),NOT FCS,'0',NOT Z3_ADR_1/Z3_ADR_1_SETF__$INT);
|
|
|
|
FDCPE_Z3_ADR_1: FDCPE port map (Z3_ADR_1,A(3),NOT FCS,'0',NOT Z3_ADR_1/Z3_ADR_1_SETF__$INT);
|
|
|
|
|
|
Z3_ADR_1/Z3_ADR_1_SETF__$INT <= (RESET AND BERR);
|
|
|
|
FDCPE_Z3_A_LOW: FDCPE port map (Z3_A_LOW,Z3_A_LOW_D,CLK_EXT,LAN_SM_RST,'0');
|
|
Z3_A_LOW_D <= ((NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
|
|
NOT LAN_SM_FSM_FFd3)
|
|
OR (NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND
|
|
LAN_SM_FSM_FFd3)
|
|
OR (LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND
|
|
NOT LAN_SM_FSM_FFd1 AND NOT LAN_SM_FSM_FFd3)
|
|
OR (DS1 AND DS0 AND LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd1 AND
|
|
NOT LAN_SM_FSM_FFd3)
|
|
OR (DS1 AND DS0 AND LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
|
|
NOT LAN_SM_FSM_FFd1 AND LAN_SM_FSM_FFd3)
|
|
OR (NOT UDS AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd3)
|
|
OR (NOT LDS AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd3)
|
|
OR (NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd1 AND
|
|
LAN_SM_FSM_FFd3));
|
|
|
|
FDCPE_Z3_DATA16: FDCPE port map (Z3_DATA(16),Z3_DATA_D(16),CLK_EXT,'0',LAN_SM_RST,Z3_DATA_CE(16));
|
|
Z3_DATA_D(16) <= ((DQ_SWAP AND DQ(8).PIN)
|
|
OR (NOT DQ_SWAP AND DQ(0).PIN));
|
|
Z3_DATA_CE(16) <= (LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
|
|
NOT LAN_SM_FSM_FFd1 AND LAN_SM_FSM_FFd3);
|
|
|
|
FDCPE_Z3_DATA17: FDCPE port map (Z3_DATA(17),Z3_DATA_D(17),CLK_EXT,'0',LAN_SM_RST,Z3_DATA_CE(17));
|
|
Z3_DATA_D(17) <= ((DQ_SWAP AND DQ(9).PIN)
|
|
OR (NOT DQ_SWAP AND DQ(1).PIN));
|
|
Z3_DATA_CE(17) <= (LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
|
|
NOT LAN_SM_FSM_FFd1 AND LAN_SM_FSM_FFd3);
|
|
|
|
FDCPE_Z3_DATA18: FDCPE port map (Z3_DATA(18),Z3_DATA_D(18),CLK_EXT,'0',LAN_SM_RST,Z3_DATA_CE(18));
|
|
Z3_DATA_D(18) <= ((DQ_SWAP AND DQ(10).PIN)
|
|
OR (NOT DQ_SWAP AND DQ(2).PIN));
|
|
Z3_DATA_CE(18) <= (LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
|
|
NOT LAN_SM_FSM_FFd1 AND LAN_SM_FSM_FFd3);
|
|
|
|
FDCPE_Z3_DATA19: FDCPE port map (Z3_DATA(19),Z3_DATA_D(19),CLK_EXT,'0',LAN_SM_RST,Z3_DATA_CE(19));
|
|
Z3_DATA_D(19) <= ((DQ_SWAP AND DQ(11).PIN)
|
|
OR (NOT DQ_SWAP AND DQ(3).PIN));
|
|
Z3_DATA_CE(19) <= (LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
|
|
NOT LAN_SM_FSM_FFd1 AND LAN_SM_FSM_FFd3);
|
|
|
|
FDCPE_Z3_DATA20: FDCPE port map (Z3_DATA(20),Z3_DATA_D(20),CLK_EXT,'0',LAN_SM_RST,Z3_DATA_CE(20));
|
|
Z3_DATA_D(20) <= ((DQ_SWAP AND DQ(12).PIN)
|
|
OR (NOT DQ_SWAP AND DQ(4).PIN));
|
|
Z3_DATA_CE(20) <= (LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
|
|
NOT LAN_SM_FSM_FFd1 AND LAN_SM_FSM_FFd3);
|
|
|
|
FDCPE_Z3_DATA21: FDCPE port map (Z3_DATA(21),Z3_DATA_D(21),CLK_EXT,'0',LAN_SM_RST,Z3_DATA_CE(21));
|
|
Z3_DATA_D(21) <= ((DQ_SWAP AND DQ(13).PIN)
|
|
OR (NOT DQ_SWAP AND DQ(5).PIN));
|
|
Z3_DATA_CE(21) <= (LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
|
|
NOT LAN_SM_FSM_FFd1 AND LAN_SM_FSM_FFd3);
|
|
|
|
FDCPE_Z3_DATA22: FDCPE port map (Z3_DATA(22),Z3_DATA_D(22),CLK_EXT,'0',LAN_SM_RST,Z3_DATA_CE(22));
|
|
Z3_DATA_D(22) <= ((DQ_SWAP AND DQ(14).PIN)
|
|
OR (NOT DQ_SWAP AND DQ(6).PIN));
|
|
Z3_DATA_CE(22) <= (LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
|
|
NOT LAN_SM_FSM_FFd1 AND LAN_SM_FSM_FFd3);
|
|
|
|
FDCPE_Z3_DATA23: FDCPE port map (Z3_DATA(23),Z3_DATA_D(23),CLK_EXT,'0',LAN_SM_RST,Z3_DATA_CE(23));
|
|
Z3_DATA_D(23) <= ((DQ_SWAP AND DQ(15).PIN)
|
|
OR (NOT DQ_SWAP AND DQ(7).PIN));
|
|
Z3_DATA_CE(23) <= (LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
|
|
NOT LAN_SM_FSM_FFd1 AND LAN_SM_FSM_FFd3);
|
|
|
|
FDCPE_Z3_DATA24: FDCPE port map (Z3_DATA(24),Z3_DATA_D(24),CLK_EXT,'0',LAN_SM_RST,Z3_DATA_CE(24));
|
|
Z3_DATA_D(24) <= ((DQ_SWAP AND DQ(0).PIN)
|
|
OR (NOT DQ_SWAP AND DQ(8).PIN));
|
|
Z3_DATA_CE(24) <= (LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
|
|
NOT LAN_SM_FSM_FFd1 AND LAN_SM_FSM_FFd3);
|
|
|
|
FDCPE_Z3_DATA25: FDCPE port map (Z3_DATA(25),Z3_DATA_D(25),CLK_EXT,'0',LAN_SM_RST,Z3_DATA_CE(25));
|
|
Z3_DATA_D(25) <= ((DQ_SWAP AND DQ(1).PIN)
|
|
OR (NOT DQ_SWAP AND DQ(9).PIN));
|
|
Z3_DATA_CE(25) <= (LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
|
|
NOT LAN_SM_FSM_FFd1 AND LAN_SM_FSM_FFd3);
|
|
|
|
FDCPE_Z3_DATA26: FDCPE port map (Z3_DATA(26),Z3_DATA_D(26),CLK_EXT,'0',LAN_SM_RST,Z3_DATA_CE(26));
|
|
Z3_DATA_D(26) <= ((DQ_SWAP AND DQ(2).PIN)
|
|
OR (NOT DQ_SWAP AND DQ(10).PIN));
|
|
Z3_DATA_CE(26) <= (LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
|
|
NOT LAN_SM_FSM_FFd1 AND LAN_SM_FSM_FFd3);
|
|
|
|
FDCPE_Z3_DATA27: FDCPE port map (Z3_DATA(27),Z3_DATA_D(27),CLK_EXT,'0',LAN_SM_RST,Z3_DATA_CE(27));
|
|
Z3_DATA_D(27) <= ((DQ_SWAP AND DQ(3).PIN)
|
|
OR (NOT DQ_SWAP AND DQ(11).PIN));
|
|
Z3_DATA_CE(27) <= (LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
|
|
NOT LAN_SM_FSM_FFd1 AND LAN_SM_FSM_FFd3);
|
|
|
|
FDCPE_Z3_DATA28: FDCPE port map (Z3_DATA(28),Z3_DATA_D(28),CLK_EXT,'0',LAN_SM_RST,Z3_DATA_CE(28));
|
|
Z3_DATA_D(28) <= ((DQ_SWAP AND DQ(4).PIN)
|
|
OR (NOT DQ_SWAP AND DQ(12).PIN));
|
|
Z3_DATA_CE(28) <= (LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
|
|
NOT LAN_SM_FSM_FFd1 AND LAN_SM_FSM_FFd3);
|
|
|
|
FDCPE_Z3_DATA29: FDCPE port map (Z3_DATA(29),Z3_DATA_D(29),CLK_EXT,'0',LAN_SM_RST,Z3_DATA_CE(29));
|
|
Z3_DATA_D(29) <= ((DQ_SWAP AND DQ(5).PIN)
|
|
OR (NOT DQ_SWAP AND DQ(13).PIN));
|
|
Z3_DATA_CE(29) <= (LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
|
|
NOT LAN_SM_FSM_FFd1 AND LAN_SM_FSM_FFd3);
|
|
|
|
FDCPE_Z3_DATA30: FDCPE port map (Z3_DATA(30),Z3_DATA_D(30),CLK_EXT,'0',LAN_SM_RST,Z3_DATA_CE(30));
|
|
Z3_DATA_D(30) <= ((DQ_SWAP AND DQ(6).PIN)
|
|
OR (NOT DQ_SWAP AND DQ(14).PIN));
|
|
Z3_DATA_CE(30) <= (LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
|
|
NOT LAN_SM_FSM_FFd1 AND LAN_SM_FSM_FFd3);
|
|
|
|
FDCPE_Z3_DATA31: FDCPE port map (Z3_DATA(31),Z3_DATA_D(31),CLK_EXT,'0',LAN_SM_RST,Z3_DATA_CE(31));
|
|
Z3_DATA_D(31) <= ((DQ_SWAP AND DQ(7).PIN)
|
|
OR (NOT DQ_SWAP AND DQ(15).PIN));
|
|
Z3_DATA_CE(31) <= (LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
|
|
NOT LAN_SM_FSM_FFd1 AND LAN_SM_FSM_FFd3);
|
|
|
|
Register Legend:
|
|
FDCPE (Q,D,C,CLR,PRE,CE);
|
|
FTCPE (Q,D,C,CLR,PRE,CE);
|
|
LDCP (Q,D,G,CLR,PRE);
|
|
|
|
****************************** Device Pin Out *****************************
|
|
|
|
Device : XC95288XL-10-TQ144
|
|
|
|
|
|
Pin Signal Pin Signal
|
|
No. Name No. Name
|
|
1 VCC 73 VCC
|
|
2 D<0> 74 A<15>
|
|
3 A_LAN<1> 75 AUTOBOOT_OFF
|
|
4 A_LAN<0> 76 LAN_WRL
|
|
5 A_LAN<3> 77 FCS
|
|
6 A_LAN<2> 78 DS1
|
|
7 A_LAN<5> 79 Z3
|
|
8 VCC 80 KPR
|
|
9 A_LAN<4> 81 UDS
|
|
10 A_LAN<7> 82 LDS
|
|
11 A_LAN<6> 83 RW
|
|
12 LAN_CFG<1> 84 VCC
|
|
13 LAN_CFG<3> 85 DTACK
|
|
14 D<6> 86 A<23>
|
|
15 D<3> 87 A<22>
|
|
16 D<7> 88 A<21>
|
|
17 D<1> 89 GND
|
|
18 GND 90 GND
|
|
19 D<8> 91 A<20>
|
|
20 D<5> 92 A<19>
|
|
21 D<4> 93 DS0
|
|
22 IDE_CS<0> 94 A<18>
|
|
23 IDE_CS<1> 95 A<17>
|
|
24 IDE_A<0> 96 MTACK
|
|
25 IDE_A<2> 97 A<16>
|
|
26 IDE_A<1> 98 BERR
|
|
27 IDE_R 99 GND
|
|
28 IDE_W 100 OVR
|
|
29 GND 101 KPR
|
|
30 CLK_EXT 102 KPR
|
|
31 KPR 103 KPR
|
|
32 INT_OUT 104 CFIN
|
|
33 KPR 105 CFOUT
|
|
34 CP_CS 106 SLAVE
|
|
35 ROM_OE 107 OWN
|
|
36 GND 108 GND
|
|
37 VCC 109 VCC
|
|
38 KPR 110 LAN_CFG<4>
|
|
39 D<2> 111 LAN_INT
|
|
40 D<9> 112 DQ<15>
|
|
41 D<10> 113 DQ<13>
|
|
42 VCC 114 GND
|
|
43 D<11> 115 DQ<11>
|
|
44 D<12> 116 DQ<9>
|
|
45 D<13> 117 DQ<1>
|
|
46 D<14> 118 DQ<0>
|
|
47 GND 119 DQ<3>
|
|
48 D<15> 120 DQ<2>
|
|
49 A<5> 121 DQ<5>
|
|
50 A<4> 122 TDO
|
|
51 A<6> 123 GND
|
|
52 A<3> 124 DQ<4>
|
|
53 A<7> 125 DQ<7>
|
|
54 A<2> 126 DQ<6>
|
|
55 VCC 127 VCC
|
|
56 A<8> 128 DQ<8>
|
|
57 KPR 129 DQ<10>
|
|
58 A<9> 130 DQ<12>
|
|
59 A<10> 131 DQ<14>
|
|
60 A<11> 132 LAN_WRH
|
|
61 A<12> 133 LAN_CS
|
|
62 GND 134 LAN_RD
|
|
63 TDI 135 LAN_CFG<2>
|
|
64 A<13> 136 A_LAN<12>
|
|
65 TMS 137 A_LAN<13>
|
|
66 A<14> 138 A_LAN<10>
|
|
67 TCK 139 A_LAN<11>
|
|
68 ROM_B<0> 140 A_LAN<8>
|
|
69 ROM_B<1> 141 VCC
|
|
70 CP_WE 142 A_LAN<9>
|
|
71 CP_RD 143 RESET
|
|
72 GND 144 GND
|
|
|
|
|
|
Legend : NC = Not Connected, unbonded pin
|
|
PGND = Unused I/O configured as additional Ground pin
|
|
TIE = Unused I/O floating -- must tie to VCC, GND or other signal
|
|
KPR = Unused I/O with weak keeper (leave unconnected)
|
|
VCC = Dedicated Power Pin
|
|
GND = Dedicated Ground Pin
|
|
TDI = Test Data In, JTAG pin
|
|
TDO = Test Data Out, JTAG pin
|
|
TCK = Test Clock, JTAG pin
|
|
TMS = Test Mode Select, JTAG pin
|
|
PROHIBITED = User reserved pin
|
|
**************************** Compiler Options ****************************
|
|
|
|
Following is a list of all global compiler options used by the fitter run.
|
|
|
|
Device(s) Specified : xc95288xl-10-TQ144
|
|
Optimization Method : SPEED
|
|
Multi-Level Logic Optimization : ON
|
|
Ignore Timing Specifications : OFF
|
|
Default Register Power Up Value : LOW
|
|
Keep User Location Constraints : ON
|
|
What-You-See-Is-What-You-Get : OFF
|
|
Exhaustive Fitting : OFF
|
|
Keep Unused Inputs : OFF
|
|
Slew Rate : FAST
|
|
Power Mode : STD
|
|
Ground on Unused IOs : OFF
|
|
Set I/O Pin Termination : KEEPER
|
|
Global Clock Optimization : ON
|
|
Global Set/Reset Optimization : ON
|
|
Global Ouput Enable Optimization : ON
|
|
Input Limit : 54
|
|
Pterm Limit : 25
|