85 lines
2.5 KiB
VHDL
85 lines
2.5 KiB
VHDL
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-- Company:
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-- Engineer:
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--
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-- Create Date: 22:08:29 12/13/2016
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-- Design Name:
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-- Module Name: LAN_IDE_CP - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity LAN_IDE_CP is
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Port ( A : inout STD_LOGIC_VECTOR (23 downto 0);
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D : inout STD_LOGIC_VECTOR (15 downto 0);
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DQ : inout STD_LOGIC_VECTOR (15 downto 0);
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A_LAN : out STD_LOGIC_VECTOR (13 downto 0);
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OWN : out STD_LOGIC;
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SLAVE : out STD_LOGIC;
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CFOUT : out STD_LOGIC;
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CFIN : in STD_LOGIC;
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C1 : in STD_LOGIC;
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C3 : in STD_LOGIC;
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MTCR : in STD_LOGIC;
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OVR : out STD_LOGIC;
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BERR : in STD_LOGIC;
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MTACK : out STD_LOGIC;
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DS0 : in STD_LOGIC;
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DTACK : out STD_LOGIC;
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UDS : in STD_LOGIC;
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LDS : in STD_LOGIC;
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AS : in STD_LOGIC;
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Z3 : in STD_LOGIC;
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DS1 : in STD_LOGIC;
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FCS : in STD_LOGIC;
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LAN_EN : out STD_LOGIC;
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AUTOBOOT_OFF : in STD_LOGIC;
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CP_RD : out STD_LOGIC;
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CP_WE : out STD_LOGIC;
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ROM_B : out STD_LOGIC_VECTOR (1 downto 0);
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ROM_OE : out STD_LOGIC;
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CP_CS : out STD_LOGIC;
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IDE_WAIT : in STD_LOGIC;
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INT_OUT : out STD_LOGIC;
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CP_IRQ : in STD_LOGIC;
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CLK_EXT : in STD_LOGIC;
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IDE_W : out STD_LOGIC;
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IDE_R : out STD_LOGIC;
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IDE_A : out STD_LOGIC_VECTOR (2 downto 0);
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IDE_CS : out STD_LOGIC_VECTOR (1 downto 0);
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LAN_CFG : out STD_LOGIC_VECTOR (4 downto 1);
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RESET : in STD_LOGIC;
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LAN_RD : out STD_LOGIC;
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LAN_CS : out STD_LOGIC;
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LAN_WRH : out STD_LOGIC;
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LAN_INT : in STD_LOGIC);
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end LAN_IDE_CP;
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architecture Behavioral of LAN_IDE_CP is
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begin
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end Behavioral;
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