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Author SHA1 Message Date
yannick c50dc04cb0 Replace legacy LAN design with Pico 2 W Clockport project 2026-10-05 22:46:10 +02:00
266 changed files with 784353 additions and 189801 deletions
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.gitattributes
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# Auto detect text files and perform LF normalization
* text=auto
# Custom for Visual Studio
*.cs diff=csharp
# Standard to msysgit
*.doc diff=astextplain
*.DOC diff=astextplain
*.docx diff=astextplain
*.DOCX diff=astextplain
*.dot diff=astextplain
*.DOT diff=astextplain
*.pdf diff=astextplain
*.PDF diff=astextplain
*.rtf diff=astextplain
*.RTF diff=astextplain
.gitignore
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@@ -187,3 +187,9 @@ Logic/LAN_IDE/LAN_IDE\.zip
/Logic/LAN_IDE_V2/LAN_IDE_CP.vm6
/Logic/LAN_IDE_V2/LAN_IDEz2v2.gise
/Logic/LAN_IDE_V2/LAN_IDEz3v2.gise
# Local routing tools and generated working state for the Pico 2 W project
/Pico2W-Clockport-Version/tools/
/Pico2W-Clockport-Version/autorouter/
/Pico2W-Clockport-Version/kicad/*-backups/
*.kicad_prl
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COPYING
-339
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GNU GENERAL PUBLIC LICENSE
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Driver/Init/Compiler.h
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/*********************************************************************
*
* Compiler and hardware specific definitions
*
*********************************************************************
* FileName: Compiler.h
* Dependencies: None
* Processor: PIC18, PIC24F, PIC24H, dsPIC30F, dsPIC33F, PIC32
* Compiler: Microchip C32 v1.00 or higher
* Microchip C30 v3.01 or higher
* Microchip C18 v3.13 or higher
* HI-TECH PICC-18 STD 9.50PL3 or higher
* Company: Microchip Technology, Inc.
*
* Software License Agreement
*
* Copyright (C) 2002-2008 Microchip Technology Inc. All rights
* reserved.
*
* Microchip licenses to you the right to use, modify, copy, and
* distribute:
* (i) the Software when embedded on a Microchip microcontroller or
* digital signal controller product ("Device") which is
* integrated into Licensee's product; or
* (ii) ONLY the Software driver source files ENC28J60.c and
* ENC28J60.h ported to a non-Microchip device used in
* conjunction with a Microchip ethernet controller for the
* sole purpose of interfacing with the ethernet controller.
*
* You should refer to the license agreement accompanying this
* Software for additional information regarding your rights and
* obligations.
*
* THE SOFTWARE AND DOCUMENTATION ARE PROVIDED "AS IS" WITHOUT
* WARRANTY OF ANY KIND, EITHER EXPRESS OR IMPLIED, INCLUDING WITHOUT
* LIMITATION, ANY WARRANTY OF MERCHANTABILITY, FITNESS FOR A
* PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT SHALL
* MICROCHIP BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR
* CONSEQUENTIAL DAMAGES, LOST PROFITS OR LOST DATA, COST OF
* PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS
* BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE
* THEREOF), ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER
* SIMILAR COSTS, WHETHER ASSERTED ON THE BASIS OF CONTRACT, TORT
* (INCLUDING NEGLIGENCE), BREACH OF WARRANTY, OR OTHERWISE.
*
*
* Author Date Comment
*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
* Howard Schlunder 10/03/2006 Original, copied from old Compiler.h
* Howard Schlunder 11/07/2007 Reorganized and simplified
********************************************************************/
#ifndef __COMPILER_H
#define __COMPILER_H
#endif
Driver/Init/E
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Driver/Init/ENCX24J600.h
-701
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/*********************************************************************
*
* ENC424J600/624J600 Registers and Bits
*
*********************************************************************
* FileName: ENCX24J600.h
* Dependencies: None
* Processor: PIC18, PIC24F, PIC24H, dsPIC30F, dsPIC33F, PIC32
* Compiler: Microchip C32 v1.05 or higher
* Microchip C30 v3.12 or higher
* Microchip C18 v3.30 or higher
* HI-TECH PICC-18 PRO 9.63PL2 or higher
* Company: Microchip Technology, Inc.
*
* Software License Agreement
*
* Copyright (C) 2002-2009 Microchip Technology Inc. All rights
* reserved.
*
* Microchip licenses to you the right to use, modify, copy, and
* distribute:
* (i) the Software when embedded on a Microchip microcontroller or
* digital signal controller product ("Device") which is
* integrated into Licensee's product; or
* (ii) ONLY the Software driver source files ENC28J60.c, ENC28J60.h,
* ENCX24J600.c and ENCX24J600.h ported to a non-Microchip device
* used in conjunction with a Microchip ethernet controller for
* the sole purpose of interfacing with the ethernet controller.
*
* You should refer to the license agreement accompanying this
* Software for additional information regarding your rights and
* obligations.
*
* THE SOFTWARE AND DOCUMENTATION ARE PROVIDED "AS IS" WITHOUT
* WARRANTY OF ANY KIND, EITHER EXPRESS OR IMPLIED, INCLUDING WITHOUT
* LIMITATION, ANY WARRANTY OF MERCHANTABILITY, FITNESS FOR A
* PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT SHALL
* MICROCHIP BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR
* CONSEQUENTIAL DAMAGES, LOST PROFITS OR LOST DATA, COST OF
* PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS
* BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE
* THEREOF), ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER
* SIMILAR COSTS, WHETHER ASSERTED ON THE BASIS OF CONTRACT, TORT
* (INCLUDING NEGLIGENCE), BREACH OF WARRANTY, OR OTHERWISE.
*
*
* Author Date Comment
*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
* Howard Schlunder 11/30/07 Original
********************************************************************/
#ifndef __ENCX24J600_H
#define __ENCX24J600_H
//#include "GenericTypeDefs.h"
//#include "HardwareProfile.h"
#define ENC100_INTERFACE_MODE 3
// Define macro for 8-bit PSP SFR address translation to SPI addresses
#define ENC100_TRANSLATE_TO_PIN_ADDR(a) (a)
#define ENC100_RAM_SIZE (24*1024)
//read/write macros
#define WRITEREG(a,b,c) (*(volatile WORD *)((volatile BYTE *)(a)+(b)))=(WORD)(c)//;printf("Write 0x%x at register 0x%lx\n",(WORD)(c),((volatile BYTE *)(a)+(b)))
#define READREG(a,b) (*(volatile WORD *)((volatile BYTE *)(a)+(b)))//;printf("Read from register 0x%lx\n",((volatile BYTE *)(a)+(b)))
//set/clear register bit macros
#define SETREG(a,b,c) (*(volatile WORD *)((volatile BYTE *)(a)+((b)+(SET_OFFSET))))=((WORD)(c))//;printf("Set register 0x%x at register 0x%lx\n",(WORD)(c),(volatile WORD *)((volatile BYTE *)(a)+((b)+(SET_OFFSET))));
#define CLRREG(a,b,c) (*(volatile WORD *)((volatile BYTE *)(a)+((b)+(CLR_OFFSET))))=((WORD)(c))//;printf("Clear register 0x%x at register 0x%lx\n",(WORD)(c),(volatile WORD *)((volatile BYTE *)(a)+((b)+(CLR_OFFSET))))
// Crypto memory addresses. These are accessible by the DMA only and therefore
// have the same addresses no matter what MCU interface is being used (SPI,
// 8-bit PSP, or 16-bit PSP)
#define ENC100_MODEX_Y (0x7880)
#define ENC100_MODEX_E (0x7800)
#define ENC100_MODEX_X (0x7880)
#define ENC100_MODEX_M (0x7900)
#define ENC100_HASH_DATA_IN (0x7A00)
#define ENC100_HASH_IV_IN (0x7A40)
#define ENC100_HASH_LEN_IN (0x7A54)
#define ENC100_HASH_DIGEST_OUT (0x7A70)
#define ENC100_HASH_LEN_OUT (0x7A84)
#define ENC100_HASH_BASE_ADDR (0x7A00)
#define ENC100_AES_KEY (0x7C00)
#define ENC100_AES_TEXTA (0x7C20)
#define ENC100_AES_TEXTB (0x7C30)
#define ENC100_AES_XOROUT (0x7C40)
#define SET_OFFSET ENC100_TRANSLATE_TO_PIN_ADDR(0x0100)
#define CLR_OFFSET ENC100_TRANSLATE_TO_PIN_ADDR(0x0180)
////////////////////////////////////////////////////
// ENC424J600/624J600 register addresses //
////////////////////////////////////////////////////
// SPI Bank 0 registers --------
#define ETXST ENC100_TRANSLATE_TO_PIN_ADDR(0x7E00)
#define ETXSTL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E00)
#define ETXSTH ENC100_TRANSLATE_TO_PIN_ADDR(0x7E01)
#define ETXLEN ENC100_TRANSLATE_TO_PIN_ADDR(0x7E02)
#define ETXLENL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E02)
#define ETXLENH ENC100_TRANSLATE_TO_PIN_ADDR(0x7E03)
#define ERXST ENC100_TRANSLATE_TO_PIN_ADDR(0x7E04)
#define ERXSTL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E04)
#define ERXSTH ENC100_TRANSLATE_TO_PIN_ADDR(0x7E05)
#define ERXTAIL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E06)
#define ERXTAILL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E06)
#define ERXTAILH ENC100_TRANSLATE_TO_PIN_ADDR(0x7E07)
#define ERXHEAD ENC100_TRANSLATE_TO_PIN_ADDR(0x7E08)
#define ERXHEADL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E08)
#define ERXHEADH ENC100_TRANSLATE_TO_PIN_ADDR(0x7E09)
#define EDMAST ENC100_TRANSLATE_TO_PIN_ADDR(0x7E0A)
#define EDMASTL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E0A)
#define EDMASTH ENC100_TRANSLATE_TO_PIN_ADDR(0x7E0B)
#define EDMALEN ENC100_TRANSLATE_TO_PIN_ADDR(0x7E0C)
#define EDMALENL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E0C)
#define EDMALENH ENC100_TRANSLATE_TO_PIN_ADDR(0x7E0D)
#define EDMADST ENC100_TRANSLATE_TO_PIN_ADDR(0x7E0E)
#define EDMADSTL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E0E)
#define EDMADSTH ENC100_TRANSLATE_TO_PIN_ADDR(0x7E0F)
#define EDMACS ENC100_TRANSLATE_TO_PIN_ADDR(0x7E10)
#define EDMACSL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E10)
#define EDMACSH ENC100_TRANSLATE_TO_PIN_ADDR(0x7E11)
#define ETXSTAT ENC100_TRANSLATE_TO_PIN_ADDR(0x7E12)
#define ETXSTATL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E12)
#define ETXSTATH ENC100_TRANSLATE_TO_PIN_ADDR(0x7E13)
#define ETXWIRE ENC100_TRANSLATE_TO_PIN_ADDR(0x7E14)
#define ETXWIREL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E14)
#define ETXWIREH ENC100_TRANSLATE_TO_PIN_ADDR(0x7E15)
// SPI all bank registers
#define EUDAST ENC100_TRANSLATE_TO_PIN_ADDR(0x7E16)
#define EUDASTL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E16)
#define EUDASTH ENC100_TRANSLATE_TO_PIN_ADDR(0x7E17)
#define EUDAND ENC100_TRANSLATE_TO_PIN_ADDR(0x7E18)
#define EUDANDL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E18)
#define EUDANDH ENC100_TRANSLATE_TO_PIN_ADDR(0x7E19)
#define ESTAT ENC100_TRANSLATE_TO_PIN_ADDR(0x7E1A)
#define ESTATL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E1A)
#define ESTATH ENC100_TRANSLATE_TO_PIN_ADDR(0x7E1B)
#define EIR ENC100_TRANSLATE_TO_PIN_ADDR(0x7E1C)
#define EIRL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E1C)
#define EIRH ENC100_TRANSLATE_TO_PIN_ADDR(0x7E1D)
#define ECON1 ENC100_TRANSLATE_TO_PIN_ADDR(0x7E1E)
#define ECON1L ENC100_TRANSLATE_TO_PIN_ADDR(0x7E1E)
#define ECON1H ENC100_TRANSLATE_TO_PIN_ADDR(0x7E1F)
// SPI Bank 1 registers -----
#define EHT1 ENC100_TRANSLATE_TO_PIN_ADDR(0x7E20)
#define EHT1L ENC100_TRANSLATE_TO_PIN_ADDR(0x7E20)
#define EHT1H ENC100_TRANSLATE_TO_PIN_ADDR(0x7E21)
#define EHT2 ENC100_TRANSLATE_TO_PIN_ADDR(0x7E22)
#define EHT2L ENC100_TRANSLATE_TO_PIN_ADDR(0x7E22)
#define EHT2H ENC100_TRANSLATE_TO_PIN_ADDR(0x7E23)
#define EHT3 ENC100_TRANSLATE_TO_PIN_ADDR(0x7E24)
#define EHT3L ENC100_TRANSLATE_TO_PIN_ADDR(0x7E24)
#define EHT3H ENC100_TRANSLATE_TO_PIN_ADDR(0x7E25)
#define EHT4 ENC100_TRANSLATE_TO_PIN_ADDR(0x7E26)
#define EHT4L ENC100_TRANSLATE_TO_PIN_ADDR(0x7E26)
#define EHT4H ENC100_TRANSLATE_TO_PIN_ADDR(0x7E27)
#define EPMM1 ENC100_TRANSLATE_TO_PIN_ADDR(0x7E28)
#define EPMM1L ENC100_TRANSLATE_TO_PIN_ADDR(0x7E28)
#define EPMM1H ENC100_TRANSLATE_TO_PIN_ADDR(0x7E29)
#define EPMM2 ENC100_TRANSLATE_TO_PIN_ADDR(0x7E2A)
#define EPMM2L ENC100_TRANSLATE_TO_PIN_ADDR(0x7E2A)
#define EPMM2H ENC100_TRANSLATE_TO_PIN_ADDR(0x7E2B)
#define EPMM3 ENC100_TRANSLATE_TO_PIN_ADDR(0x7E2C)
#define EPMM3L ENC100_TRANSLATE_TO_PIN_ADDR(0x7E2C)
#define EPMM3H ENC100_TRANSLATE_TO_PIN_ADDR(0x7E2D)
#define EPMM4 ENC100_TRANSLATE_TO_PIN_ADDR(0x7E2E)
#define EPMM4L ENC100_TRANSLATE_TO_PIN_ADDR(0x7E2E)
#define EPMM4H ENC100_TRANSLATE_TO_PIN_ADDR(0x7E2F)
#define EPMCS ENC100_TRANSLATE_TO_PIN_ADDR(0x7E30)
#define EPMCSL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E30)
#define EPMCSH ENC100_TRANSLATE_TO_PIN_ADDR(0x7E31)
#define EPMO ENC100_TRANSLATE_TO_PIN_ADDR(0x7E32)
#define EPMOL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E32)
#define EPMOH ENC100_TRANSLATE_TO_PIN_ADDR(0x7E33)
#define ERXFCON ENC100_TRANSLATE_TO_PIN_ADDR(0x7E34)
#define ERXFCONL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E34)
#define ERXFCONH ENC100_TRANSLATE_TO_PIN_ADDR(0x7E35)
// SPI all bank registers from 0x36 to 0x3F
// SPI Bank 2 registers -----
#define MACON1 ENC100_TRANSLATE_TO_PIN_ADDR(0x7E40)
#define MACON1L ENC100_TRANSLATE_TO_PIN_ADDR(0x7E40)
#define MACON1H ENC100_TRANSLATE_TO_PIN_ADDR(0x7E41)
#define MACON2 ENC100_TRANSLATE_TO_PIN_ADDR(0x7E42)
#define MACON2L ENC100_TRANSLATE_TO_PIN_ADDR(0x7E42)
#define MACON2H ENC100_TRANSLATE_TO_PIN_ADDR(0x7E43)
#define MABBIPG ENC100_TRANSLATE_TO_PIN_ADDR(0x7E44)
#define MABBIPGL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E44)
#define MABBIPGH ENC100_TRANSLATE_TO_PIN_ADDR(0x7E45)
#define MAIPG ENC100_TRANSLATE_TO_PIN_ADDR(0x7E46)
#define MAIPGL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E46)
#define MAIPGH ENC100_TRANSLATE_TO_PIN_ADDR(0x7E47)
#define MACLCON ENC100_TRANSLATE_TO_PIN_ADDR(0x7E48)
#define MACLCONL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E48)
#define MACLCONH ENC100_TRANSLATE_TO_PIN_ADDR(0x7E49)
#define MAMXFL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E4A)
#define MAMXFLL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E4A)
#define MAMXFLH ENC100_TRANSLATE_TO_PIN_ADDR(0x7E4B)
//#define r ENC100_TRANSLATE_TO_PIN_ADDR(0x7E4C)
//#define r ENC100_TRANSLATE_TO_PIN_ADDR(0x7E4D)
//#define r ENC100_TRANSLATE_TO_PIN_ADDR(0x7E4E)
//#define r ENC100_TRANSLATE_TO_PIN_ADDR(0x7E4F)
//#define r ENC100_TRANSLATE_TO_PIN_ADDR(0x7E50)
//#define r ENC100_TRANSLATE_TO_PIN_ADDR(0x7E51)
#define MICMD ENC100_TRANSLATE_TO_PIN_ADDR(0x7E52)
#define MICMDL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E52)
#define MICMDH ENC100_TRANSLATE_TO_PIN_ADDR(0x7E53)
#define MIREGADR ENC100_TRANSLATE_TO_PIN_ADDR(0x7E54)
#define MIREGADRL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E54)
#define MIREGADRH ENC100_TRANSLATE_TO_PIN_ADDR(0x7E55)
// SPI all bank registers from 0x56 to 0x5F
// SPI Bank 3 registers -----
#define MAADR3 ENC100_TRANSLATE_TO_PIN_ADDR(0x7E60)
#define MAADR3L ENC100_TRANSLATE_TO_PIN_ADDR(0x7E60)
#define MAADR3H ENC100_TRANSLATE_TO_PIN_ADDR(0x7E61)
#define MAADR2 ENC100_TRANSLATE_TO_PIN_ADDR(0x7E62)
#define MAADR2L ENC100_TRANSLATE_TO_PIN_ADDR(0x7E62)
#define MAADR2H ENC100_TRANSLATE_TO_PIN_ADDR(0x7E63)
#define MAADR1 ENC100_TRANSLATE_TO_PIN_ADDR(0x7E64)
#define MAADR1L ENC100_TRANSLATE_TO_PIN_ADDR(0x7E64)
#define MAADR1H ENC100_TRANSLATE_TO_PIN_ADDR(0x7E65)
#define MIWR ENC100_TRANSLATE_TO_PIN_ADDR(0x7E66)
#define MIWRL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E66)
#define MIWRH ENC100_TRANSLATE_TO_PIN_ADDR(0x7E67)
#define MIRD ENC100_TRANSLATE_TO_PIN_ADDR(0x7E68)
#define MIRDL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E68)
#define MIRDH ENC100_TRANSLATE_TO_PIN_ADDR(0x7E69)
#define MISTAT ENC100_TRANSLATE_TO_PIN_ADDR(0x7E6A)
#define MISTATL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E6A)
#define MISTATH ENC100_TRANSLATE_TO_PIN_ADDR(0x7E6B)
#define EPAUS ENC100_TRANSLATE_TO_PIN_ADDR(0x7E6C)
#define EPAUSL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E6C)
#define EPAUSH ENC100_TRANSLATE_TO_PIN_ADDR(0x7E6D)
#define ECON2 ENC100_TRANSLATE_TO_PIN_ADDR(0x7E6E)
#define ECON2L ENC100_TRANSLATE_TO_PIN_ADDR(0x7E6E)
#define ECON2H ENC100_TRANSLATE_TO_PIN_ADDR(0x7E6F)
#define ERXWM ENC100_TRANSLATE_TO_PIN_ADDR(0x7E70)
#define ERXWML ENC100_TRANSLATE_TO_PIN_ADDR(0x7E70)
#define ERXWMH ENC100_TRANSLATE_TO_PIN_ADDR(0x7E71)
#define EIE ENC100_TRANSLATE_TO_PIN_ADDR(0x7E72)
#define EIEL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E72)
#define EIEH ENC100_TRANSLATE_TO_PIN_ADDR(0x7E73)
#define EIDLED ENC100_TRANSLATE_TO_PIN_ADDR(0x7E74)
#define EIDLEDL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E74)
#define EIDLEDH ENC100_TRANSLATE_TO_PIN_ADDR(0x7E75)
// SPI all bank registers from 0x66 to 0x6F
// SPI Non-banked Special Function Registers
#define EGPDATA ENC100_TRANSLATE_TO_PIN_ADDR(0x7E80)
#define EGPDATAL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E80)
//#define r ENC100_TRANSLATE_TO_PIN_ADDR(0x7E81)
#define ERXDATA ENC100_TRANSLATE_TO_PIN_ADDR(0x7E82)
#define ERXDATAL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E82)
//#define r ENC100_TRANSLATE_TO_PIN_ADDR(0x7E83)
#define EUDADATA ENC100_TRANSLATE_TO_PIN_ADDR(0x7E84)
#define EUDADATAL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E84)
//#define r ENC100_TRANSLATE_TO_PIN_ADDR(0x7E85)
#define EGPRDPT ENC100_TRANSLATE_TO_PIN_ADDR(0x7E86)
#define EGPRDPTL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E86)
#define EGPRDPTH ENC100_TRANSLATE_TO_PIN_ADDR(0x7E87)
#define EGPWRPT ENC100_TRANSLATE_TO_PIN_ADDR(0x7E88)
#define EGPWRPTL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E88)
#define EGPWRPTH ENC100_TRANSLATE_TO_PIN_ADDR(0x7E89)
#define ERXRDPT ENC100_TRANSLATE_TO_PIN_ADDR(0x7E8A)
#define ERXRDPTL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E8A)
#define ERXRDPTH ENC100_TRANSLATE_TO_PIN_ADDR(0x7E8B)
#define ERXWRPT ENC100_TRANSLATE_TO_PIN_ADDR(0x7E8C)
#define ERXWRPTL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E8C)
#define ERXWRPTH ENC100_TRANSLATE_TO_PIN_ADDR(0x7E8D)
#define EUDARDPT ENC100_TRANSLATE_TO_PIN_ADDR(0x7E8E)
#define EUDARDPTL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E8E)
#define EUDARDPTH ENC100_TRANSLATE_TO_PIN_ADDR(0x7E8F)
#define EUDAWRPT ENC100_TRANSLATE_TO_PIN_ADDR(0x7E90)
#define EUDAWRPTL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E90)
#define EUDAWRPTH ENC100_TRANSLATE_TO_PIN_ADDR(0x7E91)
////////////////////////////////////////////////////
// ENC424J600/624J600 PHY Register Addresses //
////////////////////////////////////////////////////
#define PHCON1 0x00
#define PHSTAT1 0x01
#define PHANA 0x04
#define PHANLPA 0x05
#define PHANE 0x06
#define PHCON2 0x11
#define PHSTAT2 0x1B
#define PHSTAT3 0x1F
////////////////////////////////////////////////////
// ENC424J600/624J600 register bits //
////////////////////////////////////////////////////
// ESTAT bits ----------
#define ESTAT_INT ((WORD)1<<15)
#define ESTAT_FCIDLE ((WORD)1<<14)
#define ESTAT_RXBUSY ((WORD)1<<13)
#define ESTAT_CLKRDY ((WORD)1<<12)
#define ESTAT_RSTDONE ((WORD)1<<11)
#define ESTAT_PHYDPX ((WORD)1<<10)
#define ESTAT_PHYRDY ((WORD)1<<9)
#define ESTAT_PHYLNK ((WORD)1<<8)
#define ESTAT_PKTCNT7 (1<<7)
#define ESTAT_PKTCNT6 (1<<6)
#define ESTAT_PKTCNT5 (1<<5)
#define ESTAT_PKTCNT4 (1<<4)
#define ESTAT_PKTCNT3 (1<<3)
#define ESTAT_PKTCNT2 (1<<2)
#define ESTAT_PKTCNT1 (1<<1)
#define ESTAT_PKTCNT0 (1)
// EIR bits ------------
#define EIR_CRYPTEN ((WORD)1<<15)
#define EIR_MODEXIF ((WORD)1<<14)
#define EIR_HASHIF ((WORD)1<<13)
#define EIR_AESIF ((WORD)1<<12)
#define EIR_LINKIF ((WORD)1<<11)
#define EIR_PRDYIF ((WORD)1<<10)
#define EIR_r9 ((WORD)1<<9)
#define EIR_r8 ((WORD)1<<8)
#define EIR_r7 (1<<7)
#define EIR_PKTIF (1<<6)
#define EIR_DMAIF (1<<5)
#define EIR_r4 (1<<4)
#define EIR_TXIF (1<<3)
#define EIR_TXABTIF (1<<2)
#define EIR_RXABTIF (1<<1)
#define EIR_PCFULIF (1)
// ECON1 bits ----------
#define ECON1_MODEXST ((WORD)1<<15)
#define ECON1_HASHEN ((WORD)1<<14)
#define ECON1_HASHOP ((WORD)1<<13)
#define ECON1_HASHLST ((WORD)1<<12)
#define ECON1_AESST ((WORD)1<<11)
#define ECON1_AESOP1 ((WORD)1<<10)
#define ECON1_AESOP0 ((WORD)1<<9)
#define ECON1_PKTDEC ((WORD)1<<8)
#define ECON1_FCOP1 (1<<7)
#define ECON1_FCOP0 (1<<6)
#define ECON1_DMAST (1<<5)
#define ECON1_DMACPY (1<<4)
#define ECON1_DMACSSD (1<<3)
#define ECON1_DMANOCS (1<<2)
#define ECON1_TXRTS (1<<1)
#define ECON1_RXEN (1)
// ETXSTAT bits --------
#define ETXSTAT_r12 ((WORD)1<<12)
#define ETXSTAT_r11 ((WORD)1<<11)
#define ETXSTAT_LATECOL ((WORD)1<<10)
#define ETXSTAT_MAXCOL ((WORD)1<<9)
#define ETXSTAT_EXDEFER ((WORD)1<<8)
#define ETXSTAT_DEFER (1<<7)
#define ETXSTAT_r6 (1<<6)
#define ETXSTAT_r5 (1<<5)
#define ETXSTAT_CRCBAD (1<<4)
#define ETXSTAT_COLCNT3 (1<<3)
#define ETXSTAT_COLCNT2 (1<<2)
#define ETXSTAT_COLCNT1 (1<<1)
#define ETXSTAT_COLCNT0 (1)
// ERXFCON bits --------
#define ERXFCON_HTEN ((WORD)1<<15)
#define ERXFCON_MPEN ((WORD)1<<14)
#define ERXFCON_NOTPM ((WORD)1<<12)
#define ERXFCON_PMEN3 ((WORD)1<<11)
#define ERXFCON_PMEN2 ((WORD)1<<10)
#define ERXFCON_PMEN1 ((WORD)1<<9)
#define ERXFCON_PMEN0 ((WORD)1<<8)
#define ERXFCON_CRCEEN (1<<7)
#define ERXFCON_CRCEN (1<<6)
#define ERXFCON_RUNTEEN (1<<5)
#define ERXFCON_RUNTEN (1<<4)
#define ERXFCON_UCEN (1<<3)
#define ERXFCON_NOTMEEN (1<<2)
#define ERXFCON_MCEN (1<<1)
#define ERXFCON_BCEN (1)
// MACON1 bits ---------
#define MACON1_r15 ((WORD)1<<15)
#define MACON1_r14 ((WORD)1<<14)
#define MACON1_r11 ((WORD)1<<11)
#define MACON1_r10 ((WORD)1<<10)
#define MACON1_r9 ((WORD)1<<9)
#define MACON1_r8 ((WORD)1<<8)
#define MACON1_LOOPBK (1<<4)
#define MACON1_r3 (1<<3)
#define MACON1_RXPAUS (1<<2)
#define MACON1_PASSALL (1<<1)
#define MACON1_r0 (1)
// MACON2 bits ---------
#define MACON2_DEFER ((WORD)1<<14)
#define MACON2_BPEN ((WORD)1<<13)
#define MACON2_NOBKOFF ((WORD)1<<12)
#define MACON2_r9 ((WORD)1<<9)
#define MACON2_r8 ((WORD)1<<8)
#define MACON2_PADCFG2 (1<<7)
#define MACON2_PADCFG1 (1<<6)
#define MACON2_PADCFG0 (1<<5)
#define MACON2_TXCRCEN (1<<4)
#define MACON2_PHDREN (1<<3)
#define MACON2_HFRMEN (1<<2)
#define MACON2_r1 (1<<1)
#define MACON2_FULDPX (1)
// MABBIPG bits --------
#define MABBIPG_BBIPG6 (1<<6)
#define MABBIPG_BBIPG5 (1<<5)
#define MABBIPG_BBIPG4 (1<<4)
#define MABBIPG_BBIPG3 (1<<3)
#define MABBIPG_BBIPG2 (1<<2)
#define MABBIPG_BBIPG1 (1<<1)
#define MABBIPG_BBIPG0 (1)
// MAIPG bits ----------
#define MAIPG_r14 ((WORD)1<<14)
#define MAIPG_r13 ((WORD)1<<13)
#define MAIPG_r12 ((WORD)1<<12)
#define MAIPG_r11 ((WORD)1<<11)
#define MAIPG_r10 ((WORD)1<<10)
#define MAIPG_r9 ((WORD)1<<9)
#define MAIPG_r8 ((WORD)1<<8)
#define MAIPG_IPG6 (1<<6)
#define MAIPG_IPG5 (1<<5)
#define MAIPG_IPG4 (1<<4)
#define MAIPG_IPG3 (1<<3)
#define MAIPG_IPG2 (1<<2)
#define MAIPG_IPG1 (1<<1)
#define MAIPG_IPG0 (1)
// MACLCON bits --------
#define MACLCON_r13 ((WORD)1<<13)
#define MACLCON_r12 ((WORD)1<<12)
#define MACLCON_r11 ((WORD)1<<11)
#define MACLCON_r10 ((WORD)1<<10)
#define MACLCON_r9 ((WORD)1<<9)
#define MACLCON_r8 ((WORD)1<<8)
#define MACLCON_MAXRET3 (1<<3)
#define MACLCON_MAXRET2 (1<<2)
#define MACLCON_MAXRET1 (1<<1)
#define MACLCON_MAXRET0 (1)
// MICMD bits ----------
#define MICMD_MIISCAN (1<<1)
#define MICMD_MIIRD (1)
// MIREGADR bits -------
#define MIREGADR_r12 ((WORD)1<<12)
#define MIREGADR_r11 ((WORD)1<<11)
#define MIREGADR_r10 ((WORD)1<<10)
#define MIREGADR_r9 ((WORD)1<<9)
#define MIREGADR_r8 ((WORD)1<<8)
#define MIREGADR_PHREG4 (1<<4)
#define MIREGADR_PHREG3 (1<<3)
#define MIREGADR_PHREG2 (1<<2)
#define MIREGADR_PHREG1 (1<<1)
#define MIREGADR_PHREG0 (1)
// MISTAT bits ---------
#define MISTAT_r3 (1<<3)
#define MISTAT_NVALID (1<<2)
#define MISTAT_SCAN (1<<1)
#define MISTAT_BUSY (1)
// ECON2 bits ----------
#define ECON2_ETHEN ((WORD)1<<15)
#define ECON2_STRCH ((WORD)1<<14)
#define ECON2_TXMAC ((WORD)1<<13)
#define ECON2_SHA1MD5 ((WORD)1<<12)
#define ECON2_COCON3 ((WORD)1<<11)
#define ECON2_COCON2 ((WORD)1<<10)
#define ECON2_COCON1 ((WORD)1<<9)
#define ECON2_COCON0 ((WORD)1<<8)
#define ECON2_AUTOFC (1<<7)
#define ECON2_TXRST (1<<6)
#define ECON2_RXRST (1<<5)
#define ECON2_ETHRST (1<<4)
#define ECON2_MODLEN1 (1<<3)
#define ECON2_MODLEN0 (1<<2)
#define ECON2_AESLEN1 (1<<1)
#define ECON2_AESLEN0 (1)
// ERXWM bits ----------
#define ERXWM_RXFWM7 ((WORD)1<<15)
#define ERXWM_RXFWM6 ((WORD)1<<14)
#define ERXWM_RXFWM5 ((WORD)1<<13)
#define ERXWM_RXFWM4 ((WORD)1<<12)
#define ERXWM_RXFWM3 ((WORD)1<<11)
#define ERXWM_RXFWM2 ((WORD)1<<10)
#define ERXWM_RXFWM1 ((WORD)1<<9)
#define ERXWM_RXFWM0 ((WORD)1<<8)
#define ERXWM_RXEWM7 (1<<7)
#define ERXWM_RXEWM6 (1<<6)
#define ERXWM_RXEWM5 (1<<5)
#define ERXWM_RXEWM4 (1<<4)
#define ERXWM_RXEWM3 (1<<3)
#define ERXWM_RXEWM2 (1<<2)
#define ERXWM_RXEWM1 (1<<1)
#define ERXWM_RXEWM0 (1)
// EIE bits ------------
#define EIE_INTIE ((WORD)1<<15)
#define EIE_MODEXIE ((WORD)1<<14)
#define EIE_HASHIE ((WORD)1<<13)
#define EIE_AESIE ((WORD)1<<12)
#define EIE_LINKIE ((WORD)1<<11)
#define EIE_PRDYIE ((WORD)1<<10)
#define EIE_r9 ((WORD)1<<9)
#define EIE_r8 ((WORD)1<<8)
#define EIE_r7 (1<<7)
#define EIE_PKTIE (1<<6)
#define EIE_DMAIE (1<<5)
#define EIE_r4 (1<<4)
#define EIE_TXIE (1<<3)
#define EIE_TXABTIE (1<<2)
#define EIE_RXABTIE (1<<1)
#define EIE_PCFULIE (1)
// EIDLED bits ---------
#define EIDLED_LACFG3 ((WORD)1<<15)
#define EIDLED_LACFG2 ((WORD)1<<14)
#define EIDLED_LACFG1 ((WORD)1<<13)
#define EIDLED_LACFG0 ((WORD)1<<12)
#define EIDLED_LBCFG3 ((WORD)1<<11)
#define EIDLED_LBCFG2 ((WORD)1<<10)
#define EIDLED_LBCFG1 ((WORD)1<<9)
#define EIDLED_LBCFG0 ((WORD)1<<8)
#define EIDLED_DEVID2 (1<<7)
#define EIDLED_DEVID1 (1<<6)
#define EIDLED_DEVID0 (1<<5)
#define EIDLED_REVID4 (1<<4)
#define EIDLED_REVID3 (1<<3)
#define EIDLED_REVID2 (1<<2)
#define EIDLED_REVID1 (1<<1)
#define EIDLED_REVID0 (1)
// PHCON1 bits ---------
#define PHCON1_PRST ((WORD)1<<15)
#define PHCON1_PLOOPBK ((WORD)1<<14)
#define PHCON1_SPD100 ((WORD)1<<13)
#define PHCON1_ANEN ((WORD)1<<12)
#define PHCON1_PSLEEP ((WORD)1<<11)
#define PHCON1_r10 ((WORD)1<<10)
#define PHCON1_RENEG ((WORD)1<<9)
#define PHCON1_PFULDPX ((WORD)1<<8)
#define PHCON1_r7 (1<<7)
#define PHCON1_r6 (1<<6)
#define PHCON1_r5 (1<<5)
#define PHCON1_r4 (1<<4)
#define PHCON1_r3 (1<<3)
#define PHCON1_r2 (1<<2)
#define PHCON1_r1 (1<<1)
#define PHCON1_r0 (1)
// PHSTAT1 bits --------
#define PHSTAT1_r15 ((WORD)1<<15)
#define PHSTAT1_FULL100 ((WORD)1<<14)
#define PHSTAT1_HALF100 ((WORD)1<<13)
#define PHSTAT1_FULL10 ((WORD)1<<12)
#define PHSTAT1_HALF10 ((WORD)1<<11)
#define PHSTAT1_r10 ((WORD)1<<10)
#define PHSTAT1_r9 ((WORD)1<<9)
#define PHSTAT1_r8 ((WORD)1<<8)
#define PHSTAT1_r7 (1<<7)
#define PHSTAT1_r6 (1<<6)
#define PHSTAT1_ANDONE (1<<5)
#define PHSTAT1_LRFAULT (1<<4)
#define PHSTAT1_ANABLE (1<<3)
#define PHSTAT1_LLSTAT (1<<2)
#define PHSTAT1_r1 (1<<1)
#define PHSTAT1_EXTREGS (1)
// PHANA bits ----------
#define PHANA_ADNP ((WORD)1<<15)
#define PHANA_r14 ((WORD)1<<14)
#define PHANA_ADFAULT ((WORD)1<<13)
#define PHANA_r12 ((WORD)1<<12)
#define PHANA_ADPAUS1 ((WORD)1<<11)
#define PHANA_ADPAUS0 ((WORD)1<<10)
#define PHANA_r9 ((WORD)1<<9)
#define PHANA_AD100FD ((WORD)1<<8)
#define PHANA_AD100 (1<<7)
#define PHANA_AD10FD (1<<6)
#define PHANA_AD10 (1<<5)
#define PHANA_ADIEEE4 (1<<4)
#define PHANA_ADIEEE3 (1<<3)
#define PHANA_ADIEEE2 (1<<2)
#define PHANA_ADIEEE1 (1<<1)
#define PHANA_ADIEEE0 (1)
// PHANLPA bits --------
#define PHANLPA_LPNP ((WORD)1<<15)
#define PHANLPA_LPACK ((WORD)1<<14)
#define PHANLPA_LPFAULT ((WORD)1<<13)
#define PHANLPA_r12 ((WORD)1<<12)
#define PHANLPA_LPPAUS1 ((WORD)1<<11)
#define PHANLPA_LPPAUS0 ((WORD)1<<10)
#define PHANLPA_LP100T4 ((WORD)1<<9)
#define PHANLPA_LP100FD ((WORD)1<<8)
#define PHANLPA_LP100 (1<<7)
#define PHANLPA_LP10FD (1<<6)
#define PHANLPA_LP10 (1<<5)
#define PHANLPA_LPIEEE4 (1<<4)
#define PHANLPA_LPIEEE3 (1<<3)
#define PHANLPA_LPIEEE2 (1<<2)
#define PHANLPA_LPIEEE1 (1<<1)
#define PHANLPA_LPIEEE0 (1)
// PHANE bits ----------
#define PHANE_r15 ((WORD)1<<15)
#define PHANE_r14 ((WORD)1<<14)
#define PHANE_r13 ((WORD)1<<13)
#define PHANE_r12 ((WORD)1<<12)
#define PHANE_r11 ((WORD)1<<11)
#define PHANE_r10 ((WORD)1<<10)
#define PHANE_r9 ((WORD)1<<9)
#define PHANE_r8 ((WORD)1<<8)
#define PHANE_r7 (1<<7)
#define PHANE_r6 (1<<6)
#define PHANE_r5 (1<<5)
#define PHANE_PDFLT (1<<4)
#define PHANE_r3 (1<<3)
#define PHANE_r2 (1<<2)
#define PHANE_LPARCD (1<<1)
#define PHANA_LPANABL (1)
// PHCON2 bits ---------
#define PHCON2_r15 ((WORD)1<<15)
#define PHCON2_r14 ((WORD)1<<14)
#define PHCON2_EDPWRDN ((WORD)1<<13)
#define PHCON2_r12 ((WORD)1<<12)
#define PHCON2_EDTHRES ((WORD)1<<11)
#define PHCON2_r10 ((WORD)1<<10)
#define PHCON2_r9 ((WORD)1<<9)
#define PHCON2_r8 ((WORD)1<<8)
#define PHCON2_r7 (1<<7)
#define PHCON2_r6 (1<<6)
#define PHCON2_r5 (1<<5)
#define PHCON2_r4 (1<<4)
#define PHCON2_r3 (1<<3)
#define PHCON2_FRCLNK (1<<2)
#define PHCON2_EDSTAT (1<<1)
#define PHCON2_r0 (1)
// PHSTAT2 bits ---------
#define PHSTAT2_r15 ((WORD)1<<15)
#define PHSTAT2_r14 ((WORD)1<<14)
#define PHSTAT2_r13 ((WORD)1<<13)
#define PHSTAT2_r12 ((WORD)1<<12)
#define PHSTAT2_r11 ((WORD)1<<11)
#define PHSTAT2_r10 ((WORD)1<<10)
#define PHSTAT2_r9 ((WORD)1<<9)
#define PHSTAT2_r8 ((WORD)1<<8)
#define PHSTAT2_r7 (1<<7)
#define PHSTAT2_r6 (1<<6)
#define PHSTAT2_r5 (1<<5)
#define PHSTAT2_PLRITY (1<<4)
#define PHSTAT2_r3 (1<<3)
#define PHSTAT2_r2 (1<<2)
#define PHSTAT2_r1 (1<<1)
#define PHSTAT2_r0 (1)
// PHSTAT3 bits --------
#define PHSTAT3_r15 ((WORD)1<<15)
#define PHSTAT3_r14 ((WORD)1<<14)
#define PHSTAT3_r13 ((WORD)1<<13)
#define PHSTAT3_r12 ((WORD)1<<12)
#define PHSTAT3_r11 ((WORD)1<<11)
#define PHSTAT3_r10 ((WORD)1<<10)
#define PHSTAT3_r9 ((WORD)1<<9)
#define PHSTAT3_r8 ((WORD)1<<8)
#define PHSTAT3_r7 (1<<7)
#define PHSTAT3_r6 (1<<6)
#define PHSTAT3_r5 (1<<5)
#define PHSTAT3_SPDDPX2 (1<<4)
#define PHSTAT3_SPDDPX1 (1<<3)
#define PHSTAT3_SPDDPX0 (1<<2)
#define PHSTAT3_r1 (1<<1)
#define PHSTAT3_r0 (1)
#endif
Driver/Init/GenericTypeDefs.h
-281
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@@ -1,281 +0,0 @@
/*********************************************************************
*
* Generic Type Definitions
*
*********************************************************************
* FileName: GenericTypeDefs.h
* Dependencies: None
* Processor: PIC18, PIC24, dsPIC, PIC32
* Compiler: Microchip C18, C30, C32
* Company: Microchip Technology, Inc.
*
* Software License Agreement
*
* The software supplied herewith by Microchip Technology Incorporated
* (the "Company") is intended and supplied to you, the Company's
* customer, for use solely and exclusively with products manufactured
* by the Company.
*
* The software is owned by the Company and/or its supplier, and is
* protected under applicable copyright laws. All rights are reserved.
* Any use in violation of the foregoing restrictions may subject the
* user to criminal sanctions under applicable laws, as well as to
* civil liability for the breach of the terms and conditions of this
* license.
*
* THIS SOFTWARE IS PROVIDED IN AN "AS IS" CONDITION. NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED
* TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
* PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. THE COMPANY SHALL NOT,
* IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
*********************************************************************
* File Description:
*
* Change History:
* Rev Date Description
* 1.1 09/11/06 Add base signed types
* 1.2 02/28/07 Add QWORD, LONGLONG, QWORD_VAL
* 1.3 02/06/08 Add def's for PIC32
* 1.4 08/08/08 Remove LSB/MSB Macros, adopted by Peripheral lib
* 1.5 08/14/08 Simplify file header
********************************************************************/
#ifndef __GENERIC_TYPE_DEFS_H_
#define __GENERIC_TYPE_DEFS_H_
typedef enum _BOOL { FALSE = 0, TRUE } BOOL; // Undefined size
#ifndef NULL
#define NULL 0//((void *)0)
#endif
#define PUBLIC // Function attributes
#define PROTECTED
#define PRIVATE static
typedef unsigned char BYTE; // 8-bit unsigned
typedef unsigned short int WORD; // 16-bit unsigned
typedef unsigned long DWORD; // 32-bit unsigned
typedef unsigned long long QWORD; // 64-bit unsigned
typedef signed char CHAR; // 8-bit signed
typedef signed short int SHORT; // 16-bit signed
typedef signed long LONG; // 32-bit signed
typedef signed long long LONGLONG; // 64-bit signed
/* Alternate definitions */
typedef void VOID;
typedef char CHAR8;
typedef unsigned char UCHAR8;
/* Processor & Compiler independent, size specific definitions */
// To Do: We need to verify the sizes on each compiler. These
// may be compiler specific, we should either move them
// to "compiler.h" or #ifdef them for compiler type.
typedef signed int INT;
typedef signed char INT8;
typedef signed short int INT16;
typedef signed long int INT32;
typedef signed long long INT64;
typedef unsigned int UINT;
typedef unsigned char UINT8;
typedef unsigned short int UINT16;
typedef unsigned long int UINT32; // other name for 32-bit integer
typedef unsigned long long UINT64;
typedef union _BYTE_VAL
{
BYTE Val;
struct
{
unsigned char b0:1;
unsigned char b1:1;
unsigned char b2:1;
unsigned char b3:1;
unsigned char b4:1;
unsigned char b5:1;
unsigned char b6:1;
unsigned char b7:1;
} bits;
} BYTE_VAL, BYTE_BITS;
typedef union _WORD_VAL
{
WORD Val;
BYTE v[2];
struct
{
BYTE LB;
BYTE HB;
} byte;
struct
{
unsigned char b0:1;
unsigned char b1:1;
unsigned char b2:1;
unsigned char b3:1;
unsigned char b4:1;
unsigned char b5:1;
unsigned char b6:1;
unsigned char b7:1;
unsigned char b8:1;
unsigned char b9:1;
unsigned char b10:1;
unsigned char b11:1;
unsigned char b12:1;
unsigned char b13:1;
unsigned char b14:1;
unsigned char b15:1;
} bits;
} WORD_VAL, WORD_BITS;
typedef union _DWORD_VAL
{
DWORD Val;
WORD w[2];
BYTE v[4];
struct
{
WORD LW;
WORD HW;
} word;
struct
{
BYTE LB;
BYTE HB;
BYTE UB;
BYTE MB;
} byte;
struct
{
WORD_VAL low;
WORD_VAL high;
}wordUnion;
struct
{
unsigned char b0:1;
unsigned char b1:1;
unsigned char b2:1;
unsigned char b3:1;
unsigned char b4:1;
unsigned char b5:1;
unsigned char b6:1;
unsigned char b7:1;
unsigned char b8:1;
unsigned char b9:1;
unsigned char b10:1;
unsigned char b11:1;
unsigned char b12:1;
unsigned char b13:1;
unsigned char b14:1;
unsigned char b15:1;
unsigned char b16:1;
unsigned char b17:1;
unsigned char b18:1;
unsigned char b19:1;
unsigned char b20:1;
unsigned char b21:1;
unsigned char b22:1;
unsigned char b23:1;
unsigned char b24:1;
unsigned char b25:1;
unsigned char b26:1;
unsigned char b27:1;
unsigned char b28:1;
unsigned char b29:1;
unsigned char b30:1;
unsigned char b31:1;
} bits;
} DWORD_VAL;
typedef union _QWORD_VAL
{
QWORD Val;
DWORD d[2];
WORD w[4];
BYTE v[8];
struct
{
DWORD LD;
DWORD HD;
} dword;
struct
{
WORD LW;
WORD HW;
WORD UW;
WORD MW;
} word;
struct
{
unsigned char b0:1;
unsigned char b1:1;
unsigned char b2:1;
unsigned char b3:1;
unsigned char b4:1;
unsigned char b5:1;
unsigned char b6:1;
unsigned char b7:1;
unsigned char b8:1;
unsigned char b9:1;
unsigned char b10:1;
unsigned char b11:1;
unsigned char b12:1;
unsigned char b13:1;
unsigned char b14:1;
unsigned char b15:1;
unsigned char b16:1;
unsigned char b17:1;
unsigned char b18:1;
unsigned char b19:1;
unsigned char b20:1;
unsigned char b21:1;
unsigned char b22:1;
unsigned char b23:1;
unsigned char b24:1;
unsigned char b25:1;
unsigned char b26:1;
unsigned char b27:1;
unsigned char b28:1;
unsigned char b29:1;
unsigned char b30:1;
unsigned char b31:1;
unsigned char b32:1;
unsigned char b33:1;
unsigned char b34:1;
unsigned char b35:1;
unsigned char b36:1;
unsigned char b37:1;
unsigned char b38:1;
unsigned char b39:1;
unsigned char b40:1;
unsigned char b41:1;
unsigned char b42:1;
unsigned char b43:1;
unsigned char b44:1;
unsigned char b45:1;
unsigned char b46:1;
unsigned char b47:1;
unsigned char b48:1;
unsigned char b49:1;
unsigned char b50:1;
unsigned char b51:1;
unsigned char b52:1;
unsigned char b53:1;
unsigned char b54:1;
unsigned char b55:1;
unsigned char b56:1;
unsigned char b57:1;
unsigned char b58:1;
unsigned char b59:1;
unsigned char b60:1;
unsigned char b61:1;
unsigned char b62:1;
unsigned char b63:1;
} bits;
} QWORD_VAL;
#endif //__GENERIC_TYPE_DEFS_H_
Driver/Init/HardwareProfile.h
-227
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@@ -1,227 +0,0 @@
/*********************************************************************
*
* Hardware specific definitions for PIC32 Starter Kit (GP or USB) +
* PIC32 I/O Expansion Board + Ethernet PICtail Plus (ENC28J60) or
* Fast 100Mbps Ethernet PICtail Plus (ENC624J600)
*
*********************************************************************
* FileName: HardwareProfile.h
* Dependencies: None
* Processor: PIC32
* Compiler: Microchip C32 v1.05 or higher
* Company: Microchip Technology, Inc.
*
* Software License Agreement
*
* Copyright (C) 2002-2009 Microchip Technology Inc. All rights
* reserved.
*
* Microchip licenses to you the right to use, modify, copy, and
* distribute:
* (i) the Software when embedded on a Microchip microcontroller or
* digital signal controller product ("Device") which is
* integrated into Licensee's product; or
* (ii) ONLY the Software driver source files ENC28J60.c, ENC28J60.h,
* ENCX24J600.c and ENCX24J600.h ported to a non-Microchip device
* used in conjunction with a Microchip ethernet controller for
* the sole purpose of interfacing with the ethernet controller.
*
* You should refer to the license agreement accompanying this
* Software for additional information regarding your rights and
* obligations.
*
* THE SOFTWARE AND DOCUMENTATION ARE PROVIDED "AS IS" WITHOUT
* WARRANTY OF ANY KIND, EITHER EXPRESS OR IMPLIED, INCLUDING WITHOUT
* LIMITATION, ANY WARRANTY OF MERCHANTABILITY, FITNESS FOR A
* PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT SHALL
* MICROCHIP BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR
* CONSEQUENTIAL DAMAGES, LOST PROFITS OR LOST DATA, COST OF
* PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS
* BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE
* THEREOF), ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER
* SIMILAR COSTS, WHETHER ASSERTED ON THE BASIS OF CONTRACT, TORT
* (INCLUDING NEGLIGENCE), BREACH OF WARRANTY, OR OTHERWISE.
*
*
* Author Date Comment
*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
* Aseem swalah 02/03/09 Copied from the TCPIP Demo App
********************************************************************/
#ifndef __HARDWARE_PROFILE_H
#define __HARDWARE_PROFILE_H
#include "GenericTypeDefs.h"
#include "Compiler.h"
// Set configuration fuses (but only once)
#if defined(THIS_IS_STACK_APPLICATION)
#pragma config FPLLODIV = DIV_1, FPLLMUL = MUL_20, FPLLIDIV = DIV_2, FWDTEN = OFF, FPBDIV = DIV_1, POSCMOD = XT, FNOSC = PRIPLL, CP = OFF
#endif
// Clock frequency value.
// This value is used to calculate Tick Counter value
#define GetSystemClock() (80000000ul) // Hz
#define GetInstructionClock() (GetSystemClock()/1)
#define GetPeripheralClock() (GetInstructionClock()/1) // Set your divider according to your Peripheral Bus Frequency configuration fuse setting
// Specify which SPI to use for the ENC624J600.
#define ENC_IN_SPI2
// Hardware mappings
#define LED0_TRIS (TRISDbits.TRISD0) // Ref LED1
#define LED0_IO (LATDbits.LATD0)
#define LED1_TRIS (TRISDbits.TRISD1) // Ref LED2
#define LED1_IO (LATDbits.LATD1)
#define LED2_TRIS (TRISDbits.TRISD2) // Ref LED3
#define LED2_IO (LATDbits.LATD2)
#define LED3_TRIS (LED2_TRIS) // No such LED
#define LED3_IO (LATDbits.LATD6)
#define LED4_TRIS (LED2_TRIS) // No such LED
#define LED4_IO (LATDbits.LATD6)
#define LED5_TRIS (LED2_TRIS) // No such LED
#define LED5_IO (LATDbits.LATD6)
#define LED6_TRIS (LED2_TRIS) // No such LED
#define LED6_IO (LATDbits.LATD6)
#define LED7_TRIS (LED2_TRIS) // No such LED
#define LED7_IO (LATDbits.LATD6)
#define LED_GET() ((BYTE)LATD & 0x07)
#define LED_PUT(a) do{LATD = (LATD & 0xFFF8) | ((a)&0x07);}while(0)
#define BUTTON0_TRIS (TRISDbits.TRISD6) // Ref SW1
#define BUTTON0_IO (PORTDbits.RD6)
#define BUTTON1_TRIS (TRISDbits.TRISD7) // Ref SW2
#define BUTTON1_IO (PORTDbits.RD7)
#define BUTTON2_TRIS (TRISDbits.TRISD13) // Ref SW3
#define BUTTON2_IO (PORTDbits.RD13)
#define BUTTON3_TRIS (TRISDbits.TRISD13) // No BUTTON3 on this board
#define BUTTON3_IO (1)
// ENC624J600 Interface Configuration
// Comment out ENC100_INTERFACE_MODE if you don't have an ENC624J600 or
// ENC424J600. Otherwise, choose the correct setting for the interface you
// are using. Legal values are:
// - Commented out: No ENC424J600/624J600 present or used. All other
// ENC100_* macros are ignored.
// - 0: SPI mode using CS, SCK, SI, and SO pins
// - 1: 8-bit demultiplexed PSP Mode 1 with RD and WR pins
// - 2: 8-bit demultiplexed PSP Mode 2 with R/Wbar and EN pins
// - 3: 16-bit demultiplexed PSP Mode 3 with RD, WRL, and WRH pins
// - 4: 16-bit demultiplexed PSP Mode 4 with R/Wbar, B0SEL, and B1SEL pins
// - 5: 8-bit multiplexed PSP Mode 5 with RD and WR pins
// - 6: 8-bit multiplexed PSP Mode 6 with R/Wbar and EN pins
// - 9: 16-bit multiplexed PSP Mode 9 with AL, RD, WRL, and WRH pins
// - 10: 16-bit multiplexed PSP Mode 10 with AL, R/Wbar, B0SEL, and B1SEL
// pins
#define ENC100_INTERFACE_MODE 3
// If using a parallel interface, direct RAM addressing can be used (if all
// addresses wires are connected), or a reduced number of pins can be used
// for indirect addressing. If using an SPI interface or PSP Mode 9 or 10
// (multiplexed 16-bit modes), which require all address lines to always be
// connected, then this option is ignored. Comment out or uncomment this
// macro to match your hardware connections.
#define ENC100_PSP_USE_INDIRECT_RAM_ADDRESSING
// ENC424J600/624J600 parallel indirect address remapping macro function.
// This section translates SFR and RAM addresses presented to the
// ReadMemory() and WriteMemory() APIs in ENCX24J600.c to the actual
// addresses that must be presented on the parallel interface. This macro
// must be modified to match your hardware if you are using an indirect PSP
// addressing mode (ENC100_PSP_USE_INDIRECT_RAM_ADDRESSING is defined) and
// have some of your address lines tied off to Vdd. If you are using the
// SPI interface, then this section can be ignored or deleted.
#if (ENC100_INTERFACE_MODE == 1) || (ENC100_INTERFACE_MODE == 2) || (ENC100_INTERFACE_MODE == 5) || (ENC100_INTERFACE_MODE == 6) // 8-bit PSP
#define ENC100_TRANSLATE_TO_PIN_ADDR(a) ((((a)&0x0100)<<6) | ((a)&0x00FF))
#elif (ENC100_INTERFACE_MODE == 3) || (ENC100_INTERFACE_MODE == 4) // 16-bit PSP
#define ENC100_TRANSLATE_TO_PIN_ADDR(a) (a)
#endif
// Auto-crossover pins on Fast 100Mbps Ethernet PICtail/PICtail Plus. If
// your circuit doesn't have such a feature, delete these two defines.
#define ENC100_MDIX_TRIS (TRISBbits.TRISB3)
#define ENC100_MDIX_IO (LATBbits.LATB3)
// ENC624J600 I/O control and status pins
// If a pin is not required for your selected ENC100_INTERFACE_MODE
// interface selection (ex: WRH/B1SEL for PSP modes 1, 2, 5, and 6), then
// you can ignore, delete, or put anything for the pin definition. Also,
// the INT and POR pins are entirely optional. If not connected, comment
// them out.
#define ENC100_INT_TRIS (TRISEbits.TRISE9) // INT signal is optional and currently unused in the Microchip TCP/IP Stack. Leave this pin disconnected and comment out this pin definition if you don't want it.
#define ENC100_INT_IO (PORTEbits.RE9)
#if (ENC100_INTERFACE_MODE >= 1) // Parallel mode
// PSP control signal pinout
#define ENC100_CS_TRIS (TRISAbits.TRISA5) // CS is optional in PSP mode. If you are not sharing the parallel bus with another device, tie CS to Vdd and comment out this pin definition.
#define ENC100_CS_IO (LATAbits.LATA5)
#define ENC100_POR_TRIS (TRISCbits.TRISC1) // POR signal is optional. If your application doesn't have a power disconnect feature, comment out this pin definition.
#define ENC100_POR_IO (LATCbits.LATC1)
#define ENC100_SO_WR_B0SEL_EN_TRIS (TRISDbits.TRISD4)
#define ENC100_SO_WR_B0SEL_EN_IO (LATDbits.LATD4)
#define ENC100_SI_RD_RW_TRIS (TRISDbits.TRISD5)
#define ENC100_SI_RD_RW_IO (LATDbits.LATD5)
#define ENC100_SCK_AL_TRIS (TRISBbits.TRISB15)
#define ENC100_SCK_AL_IO (LATBbits.LATB15)
#else
// SPI pinout
#if defined ENC_IN_SPI1
#define ENC100_CS_TRIS (TRISDbits.TRISD14) // CS is mandatory when using the SPI interface
#define ENC100_CS_IO (LATDbits.LATD14)
#define ENC100_POR_TRIS (TRISDbits.TRISD15) // POR signal is optional. If your application doesn't have a power disconnect feature, comment out this pin definition.
#define ENC100_POR_IO (LATDbits.LATD15)
#define ENC100_SO_WR_B0SEL_EN_TRIS (TRISFbits.TRISF7) // SO is ENCX24J600 Serial Out, which needs to connect to the PIC SDI pin for SPI mode
#define ENC100_SO_WR_B0SEL_EN_IO (PORTFbits.RF7)
#define ENC100_SI_RD_RW_TRIS (TRISFbits.TRISF8) // SI is ENCX24J600 Serial In, which needs to connect to the PIC SDO pin for SPI mode
#define ENC100_SI_RD_RW_IO (LATFbits.LATF8)
#define ENC100_SCK_AL_TRIS (TRISFbits.TRISF6)
#elif defined ENC_IN_SPI2
#define ENC100_CS_TRIS (TRISFbits.TRISF12)
#define ENC100_CS_IO (LATFbits.LATF12)
#define ENC100_POR_TRIS (TRISFbits.TRISF13)
#define ENC100_POR_IO (LATFbits.LATF13)
#define ENC100_SO_WR_B0SEL_EN_TRIS (TRISGbits.TRISG7) // NOTE: SO is ENC624J600 Serial Out, which needs to connect to the PIC SDI pin for SPI mode
#define ENC100_SO_WR_B0SEL_EN_IO (PORTGbits.RG7)
#define ENC100_SI_RD_RW_TRIS (TRISGbits.TRISG8) // NOTE: SI is ENC624J600 Serial In, which needs to connect to the PIC SDO pin for SPI mode
#define ENC100_SI_RD_RW_IO (LATGbits.LATG8)
#define ENC100_SCK_AL_TRIS (TRISGbits.TRISG6)
#define ENC100_SCK_AL_IO (PORTGbits.RG6) // NOTE: This must be the PORT, not the LATch like it is for the PSP interface.
#endif
#endif
// ENC624J600 SPI SFR register selection (controls which SPI peripheral to
// use on PICs with multiple SPI peripherals). If a parallel interface is
// used (ENC100_INTERFACE_MODE is >= 1), then the SPI is not used and this
// section can be ignored or deleted.
#if defined ENC_IN_SPI1
#define ENC100_ISR_ENABLE (IEC0bits.INT2IE)
#define ENC100_ISR_FLAG (IFS0bits.INT2IF)
#define ENC100_ISR_POLARITY (INTCONbits.INT2EP)
#define ENC100_ISR_PRIORITY (IPC2bits.INT2IP)
#define ENC100_SPI_ENABLE (ENC100_SPICON1bits.ON)
#define ENC100_SPI_IF (IFS0bits.SPI1RXIF)
#define ENC100_SSPBUF (SPI1BUF)
#define ENC100_SPICON1 (SPI1CON)
#define ENC100_SPISTATbits (SPI1STATbits)
#define ENC100_SPICON1bits (SPI1CONbits)
#define ENC100_SPIBRG (SPI1BRG)
#elif defined ENC_IN_SPI2
#define ENC100_ISR_ENABLE (IEC0bits.INT4IE)
#define ENC100_ISR_FLAG (IFS0bits.INT4IF)
#define ENC100_ISR_POLARITY (INTCONbits.INT4EP)
#define ENC100_ISR_PRIORITY (IPC2bits.INT4IP)
#define ENC100_SPI_ENABLE (ENC100_SPICON1bits.ON)
#define ENC100_SPI_IF (IFS1bits.SPI2RXIF)
#define ENC100_SSPBUF (SPI2BUF)
#define ENC100_SPICON1 (SPI2CON)
#define ENC100_SPISTATbits (SPI2STATbits)
#define ENC100_SPICON1bits (SPI2CONbits)
#define ENC100_SPIBRG (SPI2BRG)
#endif
#endif //__HARDWARE_PROFILE_H
Driver/Init/InitLAN
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Driver/Init/InitLAN-l
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Driver/Init/InitLAN-protos.h
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/* MACHINE GENERATED */
/* InitLAN.c */
Driver/Init/InitLAN.c
-254
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@@ -1,254 +0,0 @@
#include "InitLAN.h"
unsigned long hex2int(char *a)
{
int i,len=0;
unsigned long val = 0;
while(a[len])
len++;
for(i=0;i<len;i++)
if(a[i] <= 57)
val += (a[i]-48)*(1<<(4*(len-1-i)));
else
val += (a[i]-55)*(1<<(4*(len-1-i)));
return val;
}
BYTE delayCIA(){ //one CIA acces: 1.4 micro sec
return (CIA_TST);
}
WORD delayShort(){
return (CHP_TST);
}
int TestMemory(APTR *BaseAddress){
int i;
WORD w=0;
WORD wTestWriteData, wTestReadData;
// Generate and write pattern
for(w = 0; w < ENC100_RAM_SIZE; w += sizeof(wTestWriteData))
{
wTestWriteData = w;
WRITEREG(BaseAddress, w, w);
}
// Read back and verify random pattern
i=0;
for(w = 0; w < ENC100_RAM_SIZE; w += sizeof(wTestWriteData))
{
wTestWriteData = w;
wTestReadData = READREG(BaseAddress,w);
// See if the data matches. If your application gets stuck here,
// it means you have a hardware failure. Check all of your PSP
// address and data lines.
if(wTestWriteData != wTestReadData){
printf("Error checking memory at adress x%lx! Expected x%x - got x%x\n",((volatile BYTE *)BaseAddress+w),wTestWriteData,wTestReadData);
++i;
}
}
return i;
}
int SetClock(APTR *BaseAddress,int Clock){
WORD s=0,c=0;
switch(Clock){
case 0:
//disable clock
c=(ECON2_COCON3|ECON2_COCON2|ECON2_COCON1|ECON2_COCON0);
s=0;
break;
case 3:
//3.125Mhz
c=(ECON2_COCON1|ECON2_COCON0);
s=(ECON2_COCON3|ECON2_COCON2);
break;
case 4:
//4Mhz
c=(ECON2_COCON2);
s=(ECON2_COCON3|ECON2_COCON1|ECON2_COCON0);
break;
case 5:
//5Mhz
c=(ECON2_COCON2|ECON2_COCON0);
s=(ECON2_COCON3|ECON2_COCON1);
break;
case 6:
//6.25Mhz
c=(ECON2_COCON2|ECON2_COCON1);
s=(ECON2_COCON3|ECON2_COCON0);
break;
case 8:
//8.333Mhz
c=(ECON2_COCON3);
s=(ECON2_COCON2|ECON2_COCON1|ECON2_COCON0);
break;
case 10:
//10Mhz
c=(ECON2_COCON3|ECON2_COCON0);
s=(ECON2_COCON2|ECON2_COCON1);
break;
case 12:
//12.5Mhz
c=(ECON2_COCON3|ECON2_COCON1);
s=(ECON2_COCON2|ECON2_COCON0);
break;
case 16:
//16.667Mhz
c=(ECON2_COCON3|ECON2_COCON1|ECON2_COCON0);
s=(ECON2_COCON2);
break;
case 20:
//20Mhz
c=(ECON2_COCON3|ECON2_COCON2);
s=(ECON2_COCON1|ECON2_COCON0);
break;
case 25:
//25Mhz
c=(ECON2_COCON3|ECON2_COCON2|ECON2_COCON0);
s=(ECON2_COCON1);
break;
case 33:
//33.333Mhz
c=(ECON2_COCON3|ECON2_COCON2|ECON2_COCON1);
s=(ECON2_COCON0);
break;
default:
//disable clock
c=(ECON2_COCON3|ECON2_COCON2|ECON2_COCON1|ECON2_COCON0);
s=0;
break;
}
CLRREG(BaseAddress,ECON2, c);
SETREG(BaseAddress,ECON2, s);
return 0;
}
int SoftReset(APTR *BaseAddress){
int i;
WORD w,v=0;
// Perform a reset via the PSP interface
do
{
// Set and clear a few bits that clears themselves upon reset.
// If EUDAST cannot be written to and your code gets stuck in this
// loop, you have a hardware problem of some sort (SPI or PMP not
// initialized correctly, I/O pins aren't connected or are
// shorted to something, power isn't available, etc.)
w= 0x1234;
do
{
WRITEREG(BaseAddress,EUDAST, w);
v=READREG(BaseAddress, EUDAST);
printf("Read 0x%x at register 0x%lx (should be 0x%x)\n",v,(volatile BYTE *)(BaseAddress)+(EUDAST),w);
} while(v != w);
// Issue a reset and wait for it to complete
SETREG(BaseAddress,ECON2, ECON2_ETHRST);
w = (WORD)(ESTAT_CLKRDY | ESTAT_RSTDONE | ESTAT_PHYRDY);
do{
delayCIA();
v = (WORD) READREG(BaseAddress,ESTAT);
v &= (WORD) w;
printf("Read 0x%x at register 0x%x (should be 0x%x)\n",v,ESTAT,w);
}while(v != w);
/*
In software, wait at least 25 µs for the Reset to
take place and the SPI/PSP interface to begin
operating again.
*/
for(i=0; i<25; ++i){
delayCIA();
}
// Check to see if the reset operation was successful by
// checking if EUDAST went back to its reset default. This test
// should always pass, but certain special conditions might make
// this test fail, such as a PSP pin shorted to logic high.
w=READREG(BaseAddress,EUDAST);
printf("Read 0x%x at register 0x%x\n",w,EUDAST);
} while(w != 0);
/*
Wait at least 256 µs for the PHY registers and PHY status bits to become available.
*/
for(i=0; i<256; ++i){
delayCIA();
}
return v;
}
/*
** **********************************************
** LocateBoard()
** **********************************************
**
** Locates Host Controller hardware
**
*/
APTR LocateBoard(int manufactor, int product)
{
APTR board;
board = NULL; // Board not found (yet)
if ( ExpansionBase = OpenLibrary( "expansion.library", 36 ) ) {
struct ConfigDev *cfg;
// *** Find board
if (cfg = FindConfigDev( NULL, manufactor, product ))
{
board = cfg->cd_BoardAddr; // Get board base adr.
}
CloseLibrary( ExpansionBase );
}
return( board ); // Return board ptr (or NULL)
}
main(int argc, char *argv[])
{
int manufactor = 2588;
int product = 123;
int v =0;
if(argc==2){
product =atoi(argv[1]);
}
if(argc==3){
manufactor =atoi(argv[1]);
product =atoi(argv[2]);
}
APTR board = LocateBoard(manufactor,product);
if(board){
printf("Found board for manufactor/product %d/%d at address 0x%lx.\n",manufactor,product, board);
SetClock(board,33);
v=SoftReset(board);
printf("SoftReset returned %X\n",v);
v=TestMemory(board);
printf("Memory passed with %d errors\n",v);
}else{
printf("No board found for manufactor/product %d/%d.\n",manufactor,product);
}
}
Driver/Init/InitLAN.c.info
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Driver/Init/InitLAN.dice
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PROJECT= InitLAN
DIR=
SRCS= InitLAN.c
HDRS=
EXTRAS=
PDEFAULT= InitLAN.h
EXEDIR=
OD=
PRECOMP=
TYPE= Normal
RUN=
CLIARGS=
CFLAGS= -3.1 -R -// -f
#### AUTOMATICALLY GENERATED - DO NOT EDIT BELOW THIS LINE
# $VER: Normal.DMakefile 3.2 (2.11.94)
PROTOS= $(OD)$(PROJECT)-protos.h
EXE= $(EXEDIR)$(PROJECT)
COMPFLAGS = -no-env $(CFLAGS) $(OD:"*":-I*) $(PRECOMP:"*.h":"-HT:%1.m=%1.h") $(VMAKEPORT:"*":"-R0 *")
PCOMPFILE = $(PRECOMP:"*.h":"T:*.m")
OBJS= $(SRCS:"*.c":"$(OD)*.o") $(SRCS:"*.a":"$(OD)*.o")
all: $(PCOMPFILE) $(PROTOS) $(EXE)
nopro: $(EXE)
$(EXE): $(OBJS)
fwrite $(OD)$(PROJECT).lnktmp $(OBJS)
dcc $(COMPFLAGS) @$(OD)$(PROJECT).lnktmp -o %(left)
$(OBJS) : $(SRCS)
dcc %(right) -o %(left) -c $(COMPFLAGS)
$(PROTOS) : $(SRCS)
-delete %(left)
makeproto -o %(left) %(right)
$(PCOMPFILE:"":"CANT.EXIST.RULE") : $(HDRS)
-delete %(left)
clean:
-delete $(OBJS) $(PROTOS) $(PCOMPFILE)
relink: rmexe $(EXE)
rmexe:
-delete $(EXE)
Driver/Init/InitLAN.dice.info
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Driver/Init/InitLAN.h
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#include <exec/memory.h>
#include <exec/lists.h>
#include <exec/nodes.h>
#include <stdlib.h>
#include <stdio.h>
#include <libraries/expansion.h>
#include <libraries/expansionbase.h>
#include <libraries/configvars.h>
#include <libraries/configregs.h>
#include <dos/filehandler.h>
#include <resources/filesysres.h>
#include <clib/exec_protos.h>
#include <clib/expansion_protos.h>
#include "ENCX24J600.h"
#define VERSION_STRING "1.1"
#define CIA_TST (*(volatile BYTE *)(0XBFE301)) //cia call 1.4micro sec
#define CHP_TST (*(volatile WORD *)(0X000004)) //chip mem call 400ns
struct Library *ExpansionBase=NULL;
unsigned long hex2int(char *a);
int SetClock(APTR *BaseAddress,int Clock);
int SoftReset(APTR *BaseAddress);
int TestMemory(APTR *BaseAddress);
APTR LocateBoard(int manufactor, int product);
/**
Function to wait for 1.4ms
*/
BYTE delayCIA();
/**
Function to wait for 400ns
*/
WORD delayShort();
Driver/Init/InitLAN.lnktmp
-2
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InitLAN.o
Driver/Init/InitLAN.o
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Driver/Init/VMake
-3
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-2.0
-dice
-000
Driver/Init/VMake.info
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Driver/Init/log.txt
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Exit code 20
Driver/Init/unnamed
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Driver/baxnet/GPL
-620
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GNU GENERAL PUBLIC LICENSE
Version 3, 29 June 2007
Copyright (C) 2007 Free Software Foundation, Inc. <https://fsf.org/>
Everyone is permitted to copy and distribute verbatim copies
of this license document, but changing it is not allowed.
Preamble
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The licenses for most software and other practical works are designed
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Driver/baxnet/README
-29
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Short: V2.15, SANA-II network drivers for several adapters
Author: Henryk Richter
Uploader: henryk.richter@gmx.net
Type: driver/net
Architecture: m68k-amigaos
Requires: OS 2.04+
This package contains network drivers and test utilities for the
following hardware:
- ZII LAN IDE CP (matze and buggs @a1k.org)
OSS Zorro-II card with ENC624J600 ethernet controller, autoboot
IDE and Clockport (see https://gitlab.com/MHeinrichs/Zorro-LAN-IDE)
- Vampire500/600 with ENC28J60 module connected to the SD-card slot
(sdnet.device)
- Vampire500V2+ or Vampire1200V2 with ENC28J60 module connected to
the expansion port (v2expeth.device)
- Vampire500V2+ with Wiznet W5500 module connected to the expansion
port (requires adapter PCB)
- VampireV4 (assumes HW registers didn't change since the time of my
initial implementation, YMMV)
Full source code (GPL V3) is included. Please refer to README.sdnet
and README.enc for installation and operation instructions.
Driver/baxnet/README.enc
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ENC624J6Net - A SANA-II driver for the Zorro-LAN-IDE card
ENC624J6Net Copyright (C) 2018 Henryk Richter <henryk.richter@gmx.net>
This driver is supposed to support ENC624J600 based ethernet on the
ZII LAN IDE CP card designed by Matze (a1k.org) and Buggs (a1k.org).
Please see at the end of the file for information about licensing
conditions.
Installation:
-------------
Installation of the driver is straightforward.
Just copy the enc624j6net.device to devs:networks and enable
the interface in your favorite TCP/IP stack as usual. There is a version
for MC68020 or later (enc624j6net.device) and another version for
68000 (enc624j6net.device_68000). Choose the right one. Please rename
the 68000/68010 version to enc624j6net.device before use.
So far, successful tests have been done with the free AmiTCP/IP 3.0b2,
AmiTCP4.0-4.2, Genesis, MiamiDX and RoadShow.
The Zorro board itself should be visible in Early Startup and ShowConfig
with manufacturer ID 2588 and card ID 123.
Configuration options
---------------------
No special configuration of the driver is necessary for normal operation.
The configuration options outlined below are documented for tuning purposes.
The config is to be placed in ENVARC:sana2/enc624j6net.config and consists
of a single line with parameters (much like CLI parameters).
PRIORITY=PRI/K/N,BPS/K/N,MTU/K/N,FULLDUPLEX/S,FLOWCONTROL/S,TIMER/K/N,MULTICAST/S,MAC/K
FULLDUPLEX - change Ethernet module into full duplex mode,
caution: requires manual configuration of duplex mode
on the switch, too.
note: this switch should not be enabled in normal cases.
The module features autoconfiguration that determines
speed and duplex automatically.
note(2): see miitool for changing speed/duplex
settings at runtime.
PRIORITY - server task priority (default 1)
BPS - bit per seconds for statistics purposes
MTU - maximum transmission unit (default 1500)
MULTICAST - (V2.3+) override fine-grained automatic multicast filtering
and accept all multicast frames (default: off)
FLOWCONTROL - enable automatic flow control that throttles incoming
data when the hardware buffer gets full
MAC - explicitly set MAC address (default: read from hardware),
use hexadecimal notation like AA:BB:CC:DD:EE:FF
example (useful for DSL via PPPoE with AmiTCP):
echo "MTU=1492 PRIORITY=6" >ENVARC:sana2/enc624j6net.config
Troubleshooting:
----------------
It has been reported that the MMU.library marked the LAN part
of the card as invalid in at least one Zorro-III configuration
such that the respective I/O space got inaccessible to the driver.
Should "muscan" report "I/O space Invalid" for the slot assigned
to the card (compare with "showConfig" or "Scout->Expansions"),then
an additional line in the MMU configuration file might help. Add
the following to the MMU-Configuration:
For 2588 123 SetCacheMode {base} 0x10000 Valid CacheInhibit IOSpace
Changelog:
----------
2.15 - fixed multicast mapping code
- added recent Microchip OUIs to MAC address validation list
(2020 and later)
- disabled automatic MMU configuration as commonly redundant
2.13 - explicit MMU parameters for LAN address space, if mmu.library
is present in the system
2.11 - try to finish up auto neg and duplex setup when going online
- improved startup/shutdown of the server process
2.10 - option to set MAC address for first board explicitly
2.9 - better support for Envoy: automatically select a higher
task priority in presence of Envoy services
2.8 - some workarounds for Fusion
2.7 - fixed MuForce hit
2.4 - added second semaphore, specifically for the write list
- recompiled using GCC 2.95 for slightly smaller binary
- avoid full ethernet chip reset on startup when the
registers seem to be in a sane state (faster init, especially
with DHCP)
- additional checks for properly built hardware:
verify data bus bits before accepting card by
a simple short mem test
2.3 - implemented fine grained multicast filter hashes
2.2 - some more tuning to RX/TX scheduling
- added optional debug code to lowlevel routines
- removed some obsolete bus transfers
- uses DMACopyFromBuffer for IP-stacks supporting
this capability
- explicit 32 bit alignment for RX/TX to speed up
ZIII transfers
- added experimental support for MII interface to
poll and modify speed and duplex settings on the
fly
- miitool added (see README.miitool)
2.00 - improved RX speed for buffer wraparound cases
- some more safety checks for boards with unresponsive
ENC chips (explicit card bus clear before verification of
chip presence)
- version bump
1.99 - fixed soft reset for ZIII firmware
- re-enabled 32 Bit Buffer copies (unless Miami is active)
- default server task priority for AmiTCP=6 (otherwise 0)
- tuned RX/TX balancing to make RoadShow happy
- added Packet Filter hook processing (needs testing)
1.98 - improved TX speed
- precaution: soft-reset cards in detection loop to make
sure that no bogus settings are left over after reset
- optional: disable length check in Sana-II Device Query
1.97 - added New Style Device (NSD) commands
- implemented SANA-II Device Query Extension
1.93 - recompiled using SAS/C, now 1kB smaller
1.91 - first Beta of completely rewritten driver
- support for concurrent IP stacks
- faster handling of statistics
- multiple board support where applicable
- workaround for Shapeshifter network plugin bug
- GCC or VBCC as compiler (cross or native compilation)
- faster lowlevel read/write
Compilation / Development Notes
-------------------------------
Either VBCC or GCC (tested with version 2.95 only) can be used for
cross-compiles. General options for compiler usage can be found in
Common.mk. Also, you might want to adapt the paths to your setup
(PREFX,SYSINC). In addition to the regular NDK, the sana2.h is expected
in the devices/ subdir of the includes. sana2.h may be found in the
AmiTCP or Roadshow SDK, respectively.
Call
make -f Makefile.enc
for building the device.
VBCC note: When calling the GNU Make port supplied with ADE/GG natively on AmigaOS3,
please make sure that "vc" is within the search path of "/bin/sh".
Native compilation is also supported for GCC and VBCC. In addition, SAS/C
smakefiles are provided for the hardware targets.
Call
smake -f smakefile.enc
for native building with SAS/C.
Conceptually, the driver was meant to support multiple hardware targets. Therefore,
it features a SANA-II frontend (device.c,deviceheader.c,deviceinit.c), a main
server running in a task (server.c) and several hardware backends. A new hardware
backend requires customized implementation of hw.c and hwprivate.h, along with
additional hardware-specfic code, if needed. The device unit structure reserves
three LONGS and three pointers for exclusive use by the hardware instance. Additional
data for the hardware can be auto-allocated at device initialization time, if necessary.
See "struct HWData" in hwprivate.h of existing backends.
License:
--------
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <https://www.gnu.org/licenses/>.
Driver/baxnet/README.miitool
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MIITool
-------
This utility allows to observe and change the physical parameters
of Ethernet NICs on AmigaOS. The parameters include autonegotiation
settings and forced speed/duplex combinations. While it is expected
that autonegotiation "just works" with modern equipment, there still
are people with some interest in retro-computing who might or might
not experience link-related problems or are just curious about some
inner workings of everyday hardware.
A modern switch ("link partner") should advertise it`s capabilities
properly such that the Ethernet hardware can select the optimal mode
out of the supported set. If that is not the case, you can narrow down
the list of advertised modes such that the link partners come to a
working agreement. The last resort is to set a fixed speed/duplex
combination. Please note that fixed parameters must be set at both
ends of the link. Otherwise the link will work slowly or not at all.
None of the settings this tool applies is permanent. Changed parameters
are only valid until the next reset of the NIC.
This utility is able to detect an active Ethernet interface in case that
the RoadShow TCP/IP stack is active. Otherwise, the device needs to be
passed as commandline option explicitly.
Examples for usage are given at the end of this text.
Prerequisites:
- AmigaOS 2.04 on 68k
- active Ethernet SANA-II driver, i.e. after starting the IP-Stack
Invocation:
- MIITool is supposed to be run from CLI/Shell.
Arguments template:
DEVICE/K,UNIT/K/N,V/S,FORCEMEDIA/K,ADVERTISE/K,RENEG/S,RESET/S,VV/S
Detailed description of arguments:
keyword - description
------------------------
DEVICE/K - device name corresponding to active ethernet interface
DEV/K example: DEVICE=enc624j6net.device
UNIT/K/N - unit number of device to be opened (default: 0)
example: UNIT=0
FORCEMEDIA - speed/duplex combination to set unconditionally,
see below for a list of valid speed or duplex modes
ADVERTISE - speed/duplex combinations to announce by autonegotiation,
implicitly restart autonegotiation,
see below for a list of valid speed or duplex modes
RENEG - restart autonegotiation, please allow a couple of seconds
RESTART until the negotiation is finished
RESET - reset PHY to power-on state
VERBOSE - more detailed outputs
V
VERYVERBOSE- even more detailed outputs
VV
Valid Speed/Duplex combinations (not case sensitive):
10baseT-HD - 10 Mbit/s half duplex
10baseT-FD - 10 Mbit/s full duplex
100baseTx-HD - 100 Mbit/s half duplex over two wire pairs
100baseTx-FD - 100 Mbit/s full duplex over two wire pairs (common)
100baseT4 - 100 Mbit/s full duplex over 4 wire pairs (rare)
10baseT - 10 Mbit/s half or full duplex
10bT - 10 Mbit/s half or full duplex
100baseTx - 100 Mbit/s half or full duplex
100bTx - 100 Mbit/s half or full duplex
Examples:
current status (detailed, autodetect)
miitool v
current status (detailed):
miitool DEV=enc624j6net.device v
negotiate 10 Mbit/s only
miitool DEV=enc624j6net.device ADVERTISE=10bT
negotiate 100baseTx and 10baseT half duplex only:
miitool DEV=enc624j6net.device ADVERTISE=100bTx,10baseT-HD
force 100 Mbit/s full duplex
miitool DEV=enc624j6net.device FORCEMEDIA=100baseTx-FD
Driver/baxnet/README.sdnet
-327
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SDNet - A SANA-II driver for ENC28J60 10BaseT ethernet modules
Copyright (C) 2016-2018 Henryk Richter <henryk.richter@gmx.net>
This driver is supposed to support ENC28J60 modules hooked up to the
MicroSD slot of Vampire 500/600 cards (sdnet.device) or the
expansion port of Vampire 500V2+ cards (v2expeth.device).
Installation:
-------------
Installation of the driver is straightforward.
Just copy the sdnet.device and v2expeth.device to devs:networks and enable
the interface in your favorite TCP/IP stack as usual. So far, successful
tests have been done with the free AmiTCP/IP 3.0b2, AmiTCP4.0-4.2, Genesis,
MiamiDX and RoadShow.
devs:networks/sdnet.device - SD card slot of V600/V500
devs:networks/v2expeth.device - expansion port of V500V2+
From version 0.8, the driver will require vampire.resource which is included
in the ROM of Vampire Cards since the Gold2.5 release.
Also, make sure that the Vampire SD Card driver (sagasd.device) is not present
in the system or at least inactive when using sdnet.device. Both pieces of
software bang the same hardware registers. v2expeth.device may be used safely
in conjunction with the SD card driver.
Vampire500 Expansion port Hardware
-----------------------------------
Please see http://wiki.apollo-accelerators.com/doku.php/expansionport for
cabling guidance.
MicroSD Slot Hardware:
----------------------
In terms of required hardware, you need the following:
- ready-to-use ENC28J60 module (a 3.3V part, DON'T USE an _unmodified_ 5V
module!)
- MicroSD breakout, e.g.
- a TF to SD extension cable where you rip off the full size SD slot and
solder on short extension cables towards the ENC28J60 module
- MicroSD breakout board (that comes directly with pin headers)
!!ATTENTION!!
Be extremely careful with your SD breakout board. Many conveniently looking
breakouts are made of thick and/or sharp edged PCB material that will likely
damage your Vampire SD slot. Such breakouts could be made working - but only
after patient sanding. Some people in the beta test team have destroyed
their SD slot already. If you don't have the required mechanical skills and
patience, I'd advise against DIY building.
!!ATTENTION!!
You need to connect the SD breakout pins as follows (microSD card sketch
looking at the connectors) to the ENC28J60 module:
----------------------- ENC28J60
| 8 ----
| 7 ---- SO -------------------- SO
| 6 ----- GND -------------------- GND
| 5 ---- SCK -------------------- SCK
| 4 ----- +3.3V ------ +3.3V ----- VCC (see below)
| 3 ---- SI -------------------- SI
| 2 ---- /CS -------------------- /CS
| 1 ---- /INT -- __________ -- /INT
------ ------------- \_| 3.3 kOhm |_/
\___| `----------´
As there is a myriad of ENC28J60 modules available, the naming scheme on
a particular board might differ. Please be aware the some of the boards
have a "CLK" pin as well as an "SCK" pin. Use the latter.
My test setup uses a separate 5V to 3.3V DC-DC converter. I got confirmation
from Igor Majstorovic (majsta) that the 3.3V line on his V500 Vampire designs
should be able to handle the max. 200 mA required by the module. To be on the
safe side, I recommend to use a conveniently placed 5V to 3.3V converter
(hint: the Floppy power connector is easily accessible).
Speaking of power: the reason why I didn't recommend 5V ENC28J60 boards
is that at least some of them have pullups from /CS and /RST to +5V. Your 3.3V
Vampire SD slot will quite likely not be happy with that.
Please put a 3.3 kOhm resistor into the connection from /INT of the ENC28J60 to
pin 1 of the MicroSD breakout.
Testing a new module:
---------------------
I've included two small test programs: sdnettest and v2expethtest. Both will
require the TCP/IP stack to be off(!) The program will perform a series of tests
to check for module presence and communication results at various clock rates. Don't
be alarmed when the slowest (biggest clock divider) mode is commented with a "fail".
This is intentional. What matters is that SPI clock dividers 1, 2 and 3 are working
properly. In case that sdnettest shows a failure for divider 1, see below how
to set a higher clock divider.
Use sdnettest for the SD slot and v2expethtest for the V500 expansion connector.
Software notes:
---------------
- The SD slot doesn't feature an interrupt. I had to implement polling
for incoming data. The current default interval is 10ms. (configurable via
echo "TIMER=20000" >ENVARC:sana2/sdnet.config, value in microseconds,
don't forget Makedir ENVARC:Sana2 if it didn't exist yet, you may also
consider "setenv")
- SPI speed is set to a safe level supporting higher core speeds than
x11 (see released x12 cores). Therefore this default of "SPISPEED=2"
is not providing maximum performance on x10 or x11 cores. For max
speed you may set echo "SPISPEED=1" >ENVARC:sana2/sdnet.config or
echo "SPISPEED=1" >ENVARC:sana2/v2expeth.config, respectively. I'd
suggest to run the test tool to determine the maximum reliable
speed setting.
- The required vampire.resource is unavailable with older versions of the
Vampire Kick Rom (anything before Gold2.5).
To load vampire.resource manually, copy the file to SYS:devs/ and
add the following near the top of your startup-sequence
C:VERSION >nil: vampire.resource 42
IF WARN
LoadModule >nil: DEVS:vampire.resource
ENDIF
In case of OS3.9, you can add the "noreboot" keyword to the loadmodule
line if you call the sniplet above before setpatch.
- If you want to use multiple options in the SANA-II config, concatenate them
in the "echo" command (alternatively "setenv") or use a text editor.
Options
-------
Below you find the options accepted by the drivers. Please note that no special
configuration is necessary for normal operation. What you find documented below
is available for tuning purposes.
The options template for the config files
ENVARC:sana2/sdnet.config
ENVARC:sana2/v2expeth.config
is as follows:
NOSPECIALSTATS/S,PRIORITY=PRI/K/N,BPS/K/N,MTU/K/N,FULLDUPLEX/S,SPISPEED/K/N,
TIMER/K/N,MULTICAST/S
SPISPEED - SPI clock divider (1-10, default 2), controls maximum
clock of SPI bus. Actual I/O clock is Core_Clock/(2+SPISPEED).
FULLDUPLEX - change Ethernet module into full duplex mode,
caution: requires MANUAL configuration of duplex mode
on the SWITCH, TOO! Otherwise you get a heavy
amount of collisions and bad performance!
PRIORITY - server task priority (default 1). It depends on the TCP/IP stack
whether a priority higher than 1 gives performance benefits. I'd
suggest to leave the setting at default, at least for Roadshow.
BPS - bit per seconds for statistics purposes
MTU - maximum transmission unit (default 1500)
NOSPECIALSTATS - obsolete, kept for config file backwards compatibility with
old driver
MULTICAST - obsolete, kept for config file backwards compatibility with
old driver
INTERRUPT - (V2EXPETH ONLY!), from Gold 2.10 release and v2expeth.device
1.94 onwards, you can enable the interrupts and avoid polling.
It is suggested to disable the timer in that case.
See below for an example
example1 (useful for DSL via PPPoE on x11 core with AmiTCP):
echo "MTU=1492 SPISPEED=1 PRIORITY=6" >ENVARC:sana2/sdnet.config
example2 (V500 expansion port, Gold 2.10 or later, interrupt driven):
echo "TIMER=0 INTERRUPT SPISPEED=1" >ENVARC:sana2/v2expeth.config
Changelog:
----------
2.8 - some workarounds for Fusion
2.7 - fixed Enforcer hit
2.6 - more sanity checks to avoid a hanging driver in situations
where the chip communication fails (i.e. with ENC28J60
resetting itself or losing power)
2.5 - added support for larger V1200 flash type (for UUID)
- better test for Vampire V4 standalone
2.4 - version bump (aligned with other hardware targets)
2.0 - parse Vampire 4 UUID for MAC auto-assignment
- version bump
1.99 - re-enabled 32 Bit Buffer copies (unless Miami is active)
- default server task priority for AmiTCP=6 (otherwise 0)
- tuned RX/TX balancing to make RoadShow happy
- added Packet Filter hook processing (needs testing)
1.95 - workaround for MiamiDX bugs, 32 Bit Buffer copy routines could not be
used safely with it.
1.94 - implemented interrupts for modules connected to V500v2+ expansion port
1.93 - minor restructuring, SAS/C makefile added
- smaller binaries (functionally identical)
1.92 - workaround for linker issue, version bump
1.91 - minor cleanups
1.90 - first Beta of completely rewritten driver
- support for concurrent IP stacks
- faster handling of statistics
- multiple board support where applicable (not for sdnet)
- workaround for Shapeshifter network plugin bug
- GCC or VBCC as compiler
- faster lowlevel read/write
1.03 - small fixes in sdnettest/v2expethtest, graceful exit when not run
on Vampire Gold 2.5 or later core
- fixed a minor bug in signal handling
1.02 - added build variant for V500V2+ expansion port, same config options
but distinct config file (ENV:SANA2/v2expeth.config), see
http://wiki.apollo-accelerators.com/doku.php/expansionport for pinout
- some more work on robustness (TX robustness and more error handling
this time)
- reworked test utilities to send valid BOOTP/DHCP requests while
doing TX/RX testing, increases chance of received frames within
testing interval
1.01 - some more fine tuning
- adjustments for Gold 2.7 x12, i.e. SPISPEED=2 by default
(see above for reverting to clock divider 1)
1.0 - some modest performance improvements
- reworked lowlevel code for higher robustness
- LED blinking modified: green LED will blink on RX,
orange LED blinks on TX
0.81 - sdnettest added
0.8 - proper hardware allocation by means of vampire.resource
- check for ENC28J60 hardware presence
0.7 - cleanups
0.6 - SPI speed setting support
- removal of spi.c,spi.h
0.5 - auto-generated MAC address, based on the Vampire FPGA serial
- busy waiting moved entirely to lowlevel asm source
- optimized compilation now produces working binaries
- more cleanups
0.4 - cleanups, config variables added
0.3 - first version shared with the Apollo team
Compilation / Development Notes
-------------------------------
Either VBCC or GCC (tested with version 2.95 only) can be used. General
options for compiler usage can be found in Common.mk. Also, you might want
to adapt the paths to your setup (PREFX,SYSINC). In addition to the regular
NDK, the sana2.h is expected in the devices/ subdir of the includes. sana2.h
may be found in the AmiTCP or Roadshow SDK, respectively.
Call
make -f Makefile.sdnet
for building the device.
VBCC note: When calling the GNU Make port supplied with ADE/GG natively on AmigaOS3,
please make sure that "vc" is within the search path of "/bin/sh".
Conceptually, the driver was meant to support multiple hardware targets. Therefore,
it features a SANA-II frontend (device.c,deviceheader.c,deviceinit.c), a main
server running in a task (server.c) and several hardware backends. A new hardware
backend requires customized implementation of hw.c and hwprivate.h, along with
additional hardware-specfic code, if needed. The device unit structure reserves
three LONGS and three pointers for exclusive use by the hardware instance. Additional
data for the hardware can be auto-allocated at device initialization time, if necessary.
See "struct HWData" in hwprivate.h of existing backends.
Copyrights / License:
---------------------
Up to version 1.03, the driver was heavily based on PlipBox, which is in turn based
on the magPLIP driver found on aminet.net.
Versions 1.90Beta and beyond are the result of a complete rewrite. I felt that I couldn't
incorporate desired features and changes with a reasonable amount of work into the old
codebase. This resulting package is made available as free software and contributions are
welcome.
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <https://www.gnu.org/licenses/>.
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Driver/baxnet/source/Common.mk
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###############################################################################
#
# Common.mk
#
# author: Henryk Richter <henryk.richter@gmx.net>
#
# note: when switching between different hardware targets, don`t forget
# "make clean" in between
#
# tools required:
# GNU Make, either VBCC or GCC for AmigaOS/68k, VASM
# recent sana2.h , e.g. from RoadShow SDK
#
# porting:
# you might need to adapt the paths (prefix for Compiler/Includes)
# Some installations have ADE: instead of GG: on Amigaos
# Recent work on AmigaOS cross toolchains suggest /opt/m68k-amigaos/sys-include
# instead of the traditional os-include
#
###############################################################################
# debug = 1 will include string debugging for terminal/sushi/sashimi
debug = 0
# compiler_vcc = 1 will trigger VBCC, else GCC
compiler_vcc = 0
###############################################################################
# prefix for system includes (ASM)
# native AmigaOS compilation: set PREFX=GG: or PREFX=ADE:, depending on toolchain
###############################################################################
PREFX = /opt/amigaos-68k/
#PREFX = gg:
SYSINC = $(PREFX)os-include
###############################################################################
#
# compiler executables (choice of gcc or vbcc)
#
###############################################################################
ifeq ($(compiler_vcc),1)
# VBCC (use explicit vlink line for LINK= if complaints about R_PC happen)
# -Rshort
CCX = vc
LINK = vlink -bamigahunk -x -s -mrel -Cvbcc -Bstatic -nostdlib -Rshort
LINKEXE = vlink -bamigahunk -x -s -mrel -Cvbcc -Bstatic
#LINK = $(CCX) -nostdlib
CFLAGS = -Os -+ -sc -c99 -cpu=$(CPU)
CFLAGS2 = -Os -+ -sc -c99 -cpu=$(CPU2)
VASMFORMAT = -m$(CPU) -Fhunk -nowarn=2064 -quiet -I$(SYSINC)
VASMFORMAT2 = -m$(CPU2) -Fhunk -nowarn=2064 -quiet -I$(SYSINC)
else
# GCC
CCX = m68k-amigaos-gcc
LINK = $(CCX) -nostartfiles -s
LINKEXE = $(CCX) -s -noixemul
#$(CPU)
CFLAGS = -Os -s -m$(CPU) -Wall -noixemul -mregparm=4 -fomit-frame-pointer -msoft-float -noixemul
CFLAGS2 = -Os -s -m$(CPU2) -Wall -noixemul -mregparm=4 -fomit-frame-pointer -msoft-float -noixemul
VASMFORMAT = -m$(CPU) -Faout -nowarn=2064 -quiet -I$(SYSINC)
VASMFORMAT2 = -m$(CPU2) -Faout -nowarn=2064 -quiet -I$(SYSINC)
endif
VASM = vasmm68k_mot
# unused here
#HOST = $(shell uname)
###############################################################################
#
# paths to the local includes
#
###############################################################################
IPATH =
###############################################################################
#
# compile-level feature definitions
#
###############################################################################
ifeq ($(compiler_vcc),1)
# skip quotes with VCC, the AmigaOS native version doesn't like them
#DEFINES += -DDEVICEVERSION=$(DEVICEVERSION) -DDEVICEREVISION=$(DEVICEREVISION)
#DEFINES += -DDEVICEDATE=$(DEVICEDATE)
#DEFINES += -DDEVICEEXTRA=$(DEVICEEXTRA)
DEFINES += -DDEVICENAME="$(DEVICEID)"
DEFINES += -DHAVE_VERSION_H=1
DEFINES += -DNEWSTYLE
#ASMDEFS += -DDEVICEVERSION=$(DEVICEVERSION) -DDEVICEREVISION=$(DEVICEREVISION)
#ASMDEFS += -DDEVICEDATE=$(DEVICEDATE) -DDEVICENAME=$(DEVICEID)
#DEFINES2 += -DDEVICEVERSION=$(DEVICEVERSION) -DDEVICEREVISION=$(DEVICEREVISION)
#DEFINES2 += -DDEVICEDATE=$(DEVICEDATE)
#DEFINES2 += -DDEVICEEXTRA=$(DEVICEEXTRA)
ifeq ($(SAME_DEVNAME),1)
DEFINES2 += -DDEVICENAME="$(DEVICEID)"
else
DEFINES2 += -DDEVICENAME="$(DEVICEID2)"
endif
DEFINES2 += -DHAVE_VERSION_H=1
DEFINES2 += -DNEWSTYLE
#ASMDEFS2 += -DDEVICEVERSION=$(DEVICEVERSION) -DDEVICEREVISION=$(DEVICEREVISION)
else
#DEFINES += -D"DEVICEVERSION=$(DEVICEVERSION)" -D"DEVICEREVISION=$(DEVICEREVISION)"
#DEFINES += -D"DEVICEDATE=$(DEVICEDATE)"
#DEFINES += -D"DEVICEEXTRA=$(DEVICEEXTRA)"
DEFINES += -D"DEVICENAME="$(DEVICEID)""
DEFINES += -DHAVE_VERSION_H=1
DEFINES += -DNEWSTYLE
#ASMDEFS += -DDEVICEVERSION=$(DEVICEVERSION) -DDEVICEREVISION=$(DEVICEREVISION)
#ASMDEFS += -DDEVICEDATE=$(DEVICEDATE) -DDEVICENAME=$(DEVICEID)
#DEFINES2 += -D"DEVICEVERSION=$(DEVICEVERSION)" -D"DEVICEREVISION=$(DEVICEREVISION)"
#DEFINES2 += -D"DEVICEDATE=$(DEVICEDATE)" -D"DEVICENAME="$(DEVICEID2)""
#DEFINES2 += -D"DEVICEEXTRA=$(DEVICEEXTRA)"
ifeq ($(SAME_DEVNAME),1)
DEFINES2 += -D"DEVICENAME="$(DEVICEID)""
else
DEFINES2 += -D"DEVICENAME="$(DEVICEID2)""
endif
DEFINES2 += -DHAVE_VERSION_H=1
DEFINES2 += -DNEWSTYLE
#ASMDEFS2 += -DDEVICEVERSION=$(DEVICEVERSION) -DDEVICEREVISION=$(DEVICEREVISION)
endif
###############################################################################
#
# debug
#
###############################################################################
ifeq ($(debug),1)
CFLAGS += -DDEBUG -g
CFLAGS2 += -DDEBUG -g
#LINKLIBS = -L$(PREFX)/lib -ldebug
#ASMOBJECTS += kprintf.o
endif
###############################################################################
#
# compiler flags and optimization levels
#
###############################################################################
CFLAGS += -I. -I$(SUBDIR)
CFLAGS2 += -I. -I$(SUBDIR)
LDFLAGS =
###############################################################################
#
# objects to build
#
###############################################################################
# ASM based alternative to deviceheader.o would be romtag.o
OBJECTS = deviceheader.o deviceinit.o device.o server.o $(SUBDIR)/hw.o
OBJECTS += $(ASMOBJECTS)
# used for secondary build
OBJECTS2 = $(patsubst %.o,%.2o,$(OBJECTS))
###############################################################################
#
# rules and commands
#
###############################################################################
all: $(DEVICEID) $(DEVICEID2) $(TESTTOOL) $(TESTTOOL2)
clean:
rm -f $(OBJECTS) $(OBJECTS2)
rm -f $(DEVICEID) $(DEVICEID2) $(EXTRACLEAN)
# not for cross compile :-)
install: $(DEVICEID) $(DEVICEID2)
copy $(DEVICEID) $(DEVICEID2) DEVS:Networks
#sdnet: $(DEVICEID)
#expnet: $(DEVICEID2)
$(DEVICEID) : $(OBJECTS)
$(LINK) $(LDFLAGS) -o $@ $(OBJECTS) $(LINKLIBS) $(LINKOPTS)
# separate ruleset for each subdirectory, ./src overrides all other paths for priority
# of platform-optimized routines
%.o : %.c
$(CCX) -c $(CFLAGS) $(DEFINES) $(IPATH) $< -o $@
%.o : %.asm
${VASM} $(VASMFORMAT) $(ASMDEFS) -o $@ $<
# secondary ruleset (used for expnet, will be ignored if DEVICEID2 is empty)
$(DEVICEID2) : $(OBJECTS2)
$(LINK) $(LDFLAGS) -o $@ $(OBJECTS2) $(LINKLIBS)
%.2o : %.c
$(CCX) -c $(CFLAGS2) $(DEFINES2) $(IPATH) $< -o $@
%.2o : %.asm
${VASM} $(VASMFORMAT2) $(ASMDEFS2) -o $@ $<
Driver/baxnet/source/Makefile.enc
-51
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@@ -1,51 +0,0 @@
###############################################################################
#
# VAMPIREGFX makefile for vbcc
#
# author: Henryk Richter <henryk.richter@gmx.net>
#
# concept:
#
# tools required:
# - vbcc, defaulting to m68k-amigaos
# - vlink
# - vasm
#
# porting:
#
###############################################################################
###############################################################################
# Date, version, extra objects to build
#
###############################################################################
#DEVICEVERSION=1
#DEVICEREVISION=95
#DEVICEDATE=08.09.2018
SUBDIR=enc624j6net
ASMOBJECTS = $(SUBDIR)/enc624j6l.o $(SUBDIR)/intervaltimer.o kprintf.o #mmustuff.o
###############################################################################
# Devices to build (1 or 2, keep DEVICEID2 empty if only one build is desired)
#
###############################################################################
DEVICEID=enc624j6net.device
DEFINES = -DHW_DMA_TX #-DUSEMMU #
ASMDEFS = -DHW_DMA_TX #
CPU = 68060
DEVICEID2=enc624j6net.device_68000
DEFINES2 = #
ASMDEFS2 = #
CPU2 = 68000
SAME_DEVNAME=1
###############################################################################
# import generic ruleset
#
###############################################################################
include Common.mk
Driver/baxnet/source/Makefile.sdnet
-68
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@@ -1,68 +0,0 @@
###############################################################################
#
# SDNet and V2EXPETH build instructions
#
# author: Henryk Richter <henryk.richter@gmx.net>
#
# concept:
# this makefile is intended mainly for cross compilation,
# although building on AmigaOS works (see Common.mk)
#
# tools required:
# - vbcc or m68k-amigaos-gcc (Default: gcc)
# - vlink or GNU ld
# - vasm (vasmm68k_mot)
# - system headers (default: /opt/amigaos-68k/os-include, see Common.mk)
#
# porting:
# see smakefile for native building using SAS/C
#
###############################################################################
###############################################################################
# Name, version
#
###############################################################################
#DEVICEVERSION=1
#DEVICEREVISION=95
#DEVICEDATE=08.09.2018
#DEVICEEXTRA=Beta
ASMOBJECTS = $(SUBDIR)/vampuuid.o $(SUBDIR)/intervaltimer.o $(SUBDIR)/enc28j60.o $(SUBDIR)/enc28j60l.o
SUBDIR=sdnet
# two flavours of the same code base may be build with this setup
# leave DEVICEID2 empty to disable second build
DEVICEID=sdnet.device
DEFINES = -DALLREADREQS=1 # -DPROTO_V2EXPNET
ASMDEFS = -DALLREADREQS=1 # -DPROTO_V2EXPNET
CPU = 68060
TESTTOOL = sdnettest
DEVICEID2=v2expeth.device
DEFINES2 = -DPROTO_V2EXPNET -DALLREADREQS=1
ASMDEFS2 = -DPROTO_V2EXPNET -DALLREADREQS=1
CPU2 = 68060
TESTTOOL2 = v2expethtest
# additional housekeeping
EXTRACLEAN = $(SUBDIR)/sdnettest.o $(SUBDIR)/sdnettest.2o
###############################################################################
# import generic ruleset
#
###############################################################################
include Common.mk
###############################################################################
# ruleset for test tools
#
###############################################################################
$(TESTTOOL) : $(ASMOBJECTS) $(SUBDIR)/sdnettest.o
$(LINKEXE) $(LDFLAGS) -o $@ $(SUBDIR)/sdnettest.o $(ASMOBJECTS)
$(TESTTOOL2) : $(ASMOBJECTS) $(SUBDIR)/sdnettest.2o
$(LINKEXE) $(LDFLAGS) -o $@ $(SUBDIR)/sdnettest.2o $(ASMOBJECTS)
Driver/baxnet/source/Makefile.v4
-50
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@@ -1,50 +0,0 @@
###############################################################################
#
# VAMPIREGFX makefile for vbcc
#
# author: Henryk Richter <henryk.richter@gmx.net>
#
# concept:
#
# tools required:
# - vbcc, defaulting to m68k-amigaos
# - vlink
# - vasm
#
# porting:
#
###############################################################################
###############################################################################
# Date, version, extra objects to build
#
###############################################################################
#DEVICEVERSION=1
#DEVICEREVISION=95
#DEVICEDATE=08.09.2018
SUBDIR=v4net
ASMOBJECTS = $(SUBDIR)/vampuuid.o $(SUBDIR)/v4l.o $(SUBDIR)/intervaltimer.o kprintf.o
###############################################################################
# Devices to build (1 or 2, keep DEVICEID2 empty if only one build is desired)
#
###############################################################################
DEVICEID=v4net.device
DEFINES = #-DHW_DMA_TX # -DPROTO_V2EXPNET
ASMDEFS = #-DHW_DMA_TX # -DPROTO_V2EXPNET
CPU = 68060
#DEVICEID2=v4net.device_68000
#DEFINES2 = # -DPROTO_V2EXPNET
#ASMDEFS2 = # -DPROTO_V2EXPNET
#CPU2 = 68000
#SAME_DEVNAME=1
###############################################################################
# import generic ruleset
#
###############################################################################
include Common.mk
Driver/baxnet/source/Makefile.vwiz
-51
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@@ -1,51 +0,0 @@
###############################################################################
#
# VWiznet build instructions
#
# author: Henryk Richter <henryk.richter@gmx.net>
#
# concept:
# this makefile is intended mainly for cross compilation,
# although building on AmigaOS works (see Common.mk)
#
# tools required:
# - vbcc or m68k-amigaos-gcc (Default: gcc)
# - vlink or GNU ld
# - vasm (vasmm68k_mot)
# - system headers (default: /opt/amigaos-68k/os-include, see Common.mk)
#
# porting:
# see smakefile for native building using SAS/C
#
###############################################################################
###############################################################################
# Name, version
#
###############################################################################
#DEVICEVERSION=1
#DEVICEREVISION=95
#DEVICEDATE=09.09.2018
#DEVICEEXTRA=Beta
ASMOBJECTS = $(SUBDIR)/vampuuid.o $(SUBDIR)/intervaltimer.o $(SUBDIR)/w5500l.o
SUBDIR=qwiznet
# two flavours of the same code base may be build with this setup
# leave DEVICEID2 empty to disable second build
DEVICEID=vwiznet600sd.device
DEFINES = # -DPROTO_V2EXPNET
ASMDEFS = # -DPROTO_V2EXPNET
CPU = 68060
DEVICEID2=vwiznet500ex.device
DEFINES2 = -DPROTO_V2EXPNET
ASMDEFS2 = -DPROTO_V2EXPNET
CPU2 = 68020
###############################################################################
# import generic ruleset
#
###############################################################################
include Common.mk
Driver/baxnet/source/compiler.h
-68
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@@ -1,68 +0,0 @@
/*
compiler.h
(C) 2018 Henryk Richter <henryk.richter@gmx.net>
Interface macros for ASM subroutines for VBCC, GCC and SAS/C
syntax:
ASM SAVEDS int some_asm_subroutine(
ASMR(d3) unsigned int some_data ASMREG(d3),
ASMR(a0) unsigned char *some_address ASMREG(a0)
);
Reason for the double spec of An/Dn: some compilers (SAS) require the register
on the left hand side, gcc on the right hand side. I wanted to avoid a big macro
for the whole argument and moved the stuff into two macros per argument.
*/
#ifndef _INC_ASMINTERFACE_H
#define _INC_ASMINTERFACE_H
#ifdef __SASC
#define ASM __asm
#define ASMR(x) register __ ## x
#define ASMREG(x)
#define SAVEDS __saveds
#define STRUCTOFFSET OFFSET /* exec/initializers.h */
#define INLINE __inline static
#define STDARGS __stdargs
#else /* __SASC */
#ifdef __GNUC__
#define ASM
#define ASMR(x) register
#define ASMREG(x) __asm("" #x "")
//#define SAVEDS __saveds
#define SAVEDS
#define STRUCTOFFSET OFFSET /* exec/initializers.h */
#define INLINE static inline
#define STDARGS __stdargs
#else /* __GNUC__ */
#ifdef __VBCC__
#define ASM
#define ASMR(x) __reg("" #x "")
#define ASMREG(x)
#define SAVEDS __saveds
#define STRUCTOFFSET(_a_,_b_) offsetof(struct _a_, _b_) /* stddef.h */
#include <stddef.h>
/* sorry, I ran into some issues inlining stuff with VBCC, disabling it */
#define INLINE
#define STDARGS __stdargs
#else /* __VBCC__ */
#error "Compiler not supported yet in compiler.h"
#endif /* __VBCC__ */
#endif /* __GNUC__ */
#endif /* __SASC */
#endif /* _INC_ASMINTERFACE_H */
Driver/baxnet/source/debug.h
-26
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@@ -1,26 +0,0 @@
/*
debug.h
(C) 2018 Henryk Richter <henryk.richter@gmx.net>
Debugging Macros
*/
#ifndef _INC_DEBUG_H
#define _INC_DEBUG_H
#ifdef DEBUG
extern void STDARGS KPrintF(char *, ...);
extern void KGetChar(void);
#define D(_x_) do { KPrintF("%s:%ld:",__FILE__,__LINE__); KPrintF _x_; } while(0)
#else /* DEBUG */
#define D(x)
#endif /* DEBUG */
#endif /* _INC_DEBUG_H */
Driver/baxnet/source/debug.i
-188
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@@ -1,188 +0,0 @@
; ifd DEBUG
; XDEF _AbsExecBase
; XDEF _LVORawDoFmt
; XDEF _LVORawPutChar
; XDEF _LVORawMayGetChar
; XDEF _AbsExecBase
; endif
ifnd _LVORawDoFmt
_LVORawDoFmt equ -$20a
endc
ifnd _LVORawPutChar
_LVORawPutChar equ -$204
_LVORawIOInit equ -$1f8
_LVORawMayGetChar equ -$1fe
endc
;
;
;
ifne DEBUG
; XREF _KPrintFa0a1
; XREF _KPrintF
WRITEDEBUG macro
movem.l d0/d1/a0/a1,-(sp)
ifnb \9
move.l \9,-(sp)
endif
ifnb \8
move.l \8,-(sp)
endif
ifnb \7
move.l \7,-(sp)
endif
ifnb \6
move.l \6,-(sp)
endif
ifnb \5
move.l \5,-(sp)
endif
ifnb \4
move.l \4,-(sp)
endif
ifnb \3
move.l \3,-(sp)
endif
ifnb \2
move.l \2,-(sp)
endif
lea.l (\1),a0
move.l sp,a1
jsr _KPrintFa0a1
ifnb \2
add.l #4,sp
endif
ifnb \3
add.l #4,sp
endif
ifnb \4
add.l #4,sp
endif
ifnb \5
add.l #4,sp
endif
ifnb \6
add.l #4,sp
endif
ifnb \7
add.l #4,sp
endif
ifnb \8
add.l #4,sp
endif
ifnb \9
add.l #4,sp
endif
movem.l (sp)+,d0/d1/a0/a1
endm
else
WRITEDEBUG macro
;
endm
endc
;
;
;
WRITEOUT macro
movem.l d0/d1/d2/a0/a1/a6,-(sp)
ifnb \9
move.l \9,-(sp)
endif
ifnb \8
move.l \8,-(sp)
endif
ifnb \7
move.l \7,-(sp)
endif
ifnb \6
move.l \6,-(sp)
endif
ifnb \5
move.l \5,-(sp)
endif
ifnb \4
move.l \4,-(sp)
endif
ifnb \3
move.l \3,-(sp)
endif
ifnb \2
move.l \2,-(sp)
endif
ifd DEBUG
move.l \1,a0
move.l sp,a1
jsr _KPrintFa0a1
endif
move.l \1,d1
move.l sp,d2
movea.l DOSBase,a6
jsr _LVOVPrintf(a6)
ifnb \2
add.l #4,sp
endif
ifnb \3
add.l #4,sp
endif
ifnb \4
add.l #4,sp
endif
ifnb \5
add.l #4,sp
endif
ifnb \6
add.l #4,sp
endif
ifnb \7
add.l #4,sp
endif
ifnb \8
add.l #4,sp
endif
ifnb \9
add.l #4,sp
endif
movem.l (sp)+,d0/d1/d2/a0/a1/a6
endm
;COUNTERS only when DEBUG is on
ifd DEBUG
ifne DEBUG
DEBUG_COUNTERS EQU 1
endc
endc
ifd DEBUG_COUNTERS
COUNTER_INC macro
addq.l #1,\1
endm
else
COUNTER_INC macro
nop
endm
endc
; write usage of all emulated instructions if DEBUG is 1 to RAWIO (sushi/sashimi/serial)
ifd DEBUG
ifne DEBUG
HAVE_DEBUGINSTR EQU 1
DEBUGINSTR macro
ifnb \3
WRITEDEBUG \1,\2,\3
else
WRITEDEBUG \1,\2
endc
endm
endc
endc
ifnd HAVE_DEBUGINSTR
DEBUGINSTR macro
endm
endc
Driver/baxnet/source/device.c
-1296
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File diff suppressed because it is too large Load Diff
Driver/baxnet/source/device.h
-275
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@@ -1,275 +0,0 @@
/*
device.h
(C) 2018 Henryk Richter <henryk.richter@gmx.net>
Device Functions and Definitions
*/
#ifndef _INC_DEVICE_H
#define _INC_DEVICE_H
/* defaults */
#define MAX_UNITS 4
#define DEF_BPS 10000000
#define DEF_MTU 1500
/* includes */
#include "compiler.h"
#include <dos/dos.h>
#include <exec/lists.h>
#include <exec/libraries.h>
#include <exec/devices.h>
#include <exec/semaphores.h>
#include <devices/sana2.h>
#include "hw.h"
#include "debug.h"
/* reassign Library bases from global definitions to own struct */
#define SysBase db->db_SysBase
#define DOSBase db->db_DOSBase
#define UtilityBase db->db_UtilityBase
#define MMUBase db->db_MMUBase
//#define VampireBase db->db_VampireBase
/* old sana2.h ? */
#ifndef S2_CopyToBuff32
#define S2_CopyToBuff32 (S2_Dummy + 6)
#endif
#ifndef S2_CopyFromBuff32
#define S2_CopyFromBuff32 (S2_Dummy + 7)
#endif
struct ServerData {
ULONG sv_flags;
UBYTE *sv_frame; /* temporary frame for rx/tx */
ULONG sv_framesize; /* allocated bytes */
struct List sv_mclist; /* list of multicast addresses to accept */
};
#define DUB_OPEN 0
#define DUB_EXCLUSIVE 1
#define DUB_ONLINE 2
#define DUB_TYPETRACK 3
#define DUB_PROMISC 4
#define DUF_OPEN (1<<DUB_OPEN)
#define DUF_EXCLUSIVE (1<<DUB_EXCLUSIVE)
#define DUF_ONLINE (1<<DUB_ONLINE)
#define DUF_TYPETRACK (1<<DUB_TYPETRACK)
#define DUF_PROMISC (1<<DUB_PROMISC)
struct DevUnit {
volatile struct List du_ReadTypes; /* RX queues are sorted by type: find RX buffers
by type, afterwards traverse active readers =
networking stacks */
volatile struct List du_ReadOrphans; /* not claimed by RX types or no buffers available -> orphan */
volatile struct List du_WriteQueue; /* TX queue */
volatile struct List du_EventQueue; /* Event queue */
struct SignalSemaphore du_Sem; /* list locking (global per unit) */
struct SignalSemaphore du_WrSem; /* experimental: separate Sempaphore for write list */
ULONG du_OpenCount; /* unit openers */
ULONG du_Flags; /* unit flags */
ULONG du_MTU; /* maximum transmission unit (1500 for regular Ethernet) */
ULONG du_BitPerSec; /* speed in BPS */
UBYTE du_HWAddr[6]; /* default MAC address */
UBYTE du_CFGAddr[6]; /* configured MAC address */
struct Sana2DeviceStats du_DevStats; /* collect device stats per unit */
/* HW Data (generic for now) */
ULONG du_hwl0;
ULONG du_hwl1;
ULONG du_hwl2;
APTR du_hwp0;
APTR du_hwp1;
APTR du_hwp2;
};
struct devbase {
struct Library db_Lib;
BPTR db_SegList; /* from Device Init */
ULONG db_Flags; /* misc */
struct Library *db_SysBase; /* Exec Base */
struct Library *db_DOSBase;
struct Library *db_UtilityBase;
struct Library *db_MMUBase;
ULONG db_NBoards;
ULONG db_ID; /* device opener ID enumeration */
struct DevUnit db_Units[MAX_UNITS]; /* don't bother with lists, who's gonna have more
than 1 network card of the same type, anyway ? */
/* server process data */
struct SignalSemaphore db_Sem; /* lock server state communication to one caller */
/* (see per-unit Semaphore for queue stuff) */
volatile struct Process *db_ServerProc; /* process of main queue server */
struct Task *db_Task; /* server shutdown task address (non permanently available) */
ULONG db_ServerSigMask; /* shutdown signal */
struct MsgPort *db_ServerPort; /* request forwarding (initialized by server) */
/* housekeeping */
struct List db_BufferManagement; /* remember allocated instances */
/* services for other instances (server task, hw.c) */
struct ServerData db_svdat; /* private data for main server */
struct HWData db_hwdat; /* private data for hardware interface */
};
typedef LONG (* ASM BMCALL)( ASMR(a0) void * ASMREG(a0), ASMR(a1) void * ASMREG(a1), ASMR(d0) LONG ASMREG(d0) );
struct db_BufferManagement {
struct MinNode dbm_n;
BMCALL dbm_CopyFromBuffer32;
BMCALL dbm_CopyToBuffer32;
BMCALL dbm_CopyFromBuffer;
BMCALL dbm_CopyToBuffer;
BMCALL dbm_CopyFromBufferDMA; /* this buffering method requires additional support from lowlevel HW implementation */
BMCALL dbm_CopyToBufferDMA; /* usage of this pointer requires additional checks */
APTR dbm_PacketFilter; /* this is actually a Hook */
ULONG dbm_ID;
};
#ifndef DEVBASETYPE
#define DEVBASETYPE struct devbase
#endif
#ifndef DEVBASEP
#define DEVBASEP DEVBASETYPE *db
#endif
struct ServerMsg {
struct Message sm_msg;
DEVBASETYPE *sm_devbase;
LONG sm_result;
};
/* frame type management:
- every network stack who is interested in a specific type gets a "reader" assigned to
that type. The ID tracked here is the same that is assigned on OpenDevice and stored
in the buffer management
-
*/
struct SanaReader
{
struct MinNode snr_Node;
ULONG snr_ID; /* assigned to any reader on Device open */
struct List snr_Requests;
};
/*
read list(s)
- multiple readers supported (i.e. multiple active Networking stacks)
- one read list per type (shouldn't be too many)
- two major thoughts behind this
- track type statistics without additional search
- received frame copy to additional reader(s) without searching through
their read request lists
+ avoid long searches for orphans (unexpected received frames)
*/
struct SanaReadType
{
struct MinNode srt_Node;
ULONG srt_Type; /* Type ID - matches Ethernet Types */
ULONG srt_Flags; /* Flags: multiple reader mode, do track type */
struct List srt_Readers; /* active readers */
/* SANA-II Type statistics */
struct Sana2PacketTypeStats srt_Sana2PacketTypeStats;
ULONG srt_FramesSent;
ULONG srt_FramesRcvd;
ULONG srt_BytesSent;
ULONG srt_BytesRcvd;
ULONG srt_FramesDropped;
};
/* SanaReadList flags */
#define SRTB_ONEREADER 0 /* at least one reader present ? */
#define SRTB_MULTREADER 1 /* more than one reader */
#define SRTB_TRACKTYPE 2 /* perform track type statistics */
#define SRTF_ONEREADER (1<<SRTB_ONEREADER)
#define SRTF_MULTREADER (1<<SRTB_MULTREADER)
#define SRTF_TRACKTYPE (1<<SRTB_TRACKTYPE)
/* server maintains list of multicast addresses */
struct MCastEntry
{
struct MinNode mce_Node;
UBYTE mce_start[6];
UBYTE mce_stop[6];
ULONG mce_refcount; /* ok, this is poor. Proper would mean "track by caller". */
/* But hey, how much multicast do you encounter on Amiga? */
};
/* PROTOS */
//ASM LONG LibNull( void );
ASM SAVEDS struct Device *DevInit(ASMR(d0) DEVBASEP ASMREG(d0),
ASMR(a0) BPTR seglist ASMREG(a0),
ASMR(a6) struct Library *_SysBase ASMREG(a6) );
ASM SAVEDS LONG DevOpen( ASMR(a1) struct IOSana2Req *ios2 ASMREG(a1),
ASMR(d0) ULONG unit ASMREG(d0),
ASMR(d1) ULONG flags ASMREG(d1),
ASMR(a6) DEVBASEP ASMREG(a6) );
ASM SAVEDS BPTR DevClose( ASMR(a1) struct IOSana2Req *ios2 ASMREG(a1),
ASMR(a6) DEVBASEP ASMREG(a6) );
ASM SAVEDS BPTR DevExpunge( ASMR(a6) DEVBASEP ASMREG(a6) );
ASM SAVEDS VOID DevBeginIO( ASMR(a1) struct IOSana2Req *ios2 ASMREG(a1),
ASMR(a6) DEVBASEP ASMREG(a6) );
ASM SAVEDS LONG DevAbortIO( ASMR(a1) struct IOSana2Req *ios2 ASMREG(a1),
ASMR(a6) DEVBASEP ASMREG(a6) );
void dbTermIO( DEVBASETYPE*, struct IOSana2Req * );
/* server.c */
VOID SAVEDS ServerTask(void);
/* private functions */
#ifdef DEVICE_MAIN
static void dbNewList( struct List * );
static LONG dbIsInList( struct List *, struct Node * );
static LONG dbStartServer( DEVBASETYPE*, LONG );
static LONG dbStopServer( DEVBASETYPE*, LONG );
static LONG dbSignalServer( DEVBASETYPE*, ULONG, ULONG );
static void dbDeleteBuffers( DEVBASETYPE*, struct IOSana2Req * );
static void dbAddReadReq( DEVBASETYPE*, ULONG , struct IOSana2Req * );
static struct SanaReader*dbAddReader( DEVBASETYPE*, ULONG, ULONG, struct SanaReadType *, ULONG );
static void dbDeleteReader( DEVBASETYPE*, ULONG, ULONG );
static struct SanaReadType *dbAddType( DEVBASETYPE*, ULONG, ULONG );
static void dbDeleteType( DEVBASETYPE*, ULONG, ULONG );
static void dbForwardIO( DEVBASETYPE*, struct IOSana2Req * );
static LONG dbTrackType(DEVBASETYPE*, ULONG, ULONG, ULONG );
static LONG dbTrackTypeStats( DEVBASETYPE*, ULONG, ULONG, struct Sana2PacketTypeStats *);
#endif /* DEVICE_MAIN */
#endif /* _INC_DEVICE_H */
Driver/baxnet/source/device.i
-139
View File
@@ -1,139 +0,0 @@
;
; device.i
;
; (C) 2018 Henryk Richter <henryk.richter@gmx.net>
;
; Device Functions and Definitions
;
;Note(1): structures are defined only partially at the moment
;Note(2): keep this in sync with device.h
;
ifnd _INC_DEVICE_I
_INC_DEVICE_I EQU 1
; defaults
MAX_UNITS EQU 4
DEF_BPS EQU 10000000
DEF_MTU EQU 1500
; includes
include "exec/lists.i"
include "exec/libraries.i"
include "exec/devices.i"
include "exec/semaphores.i"
include "devices/timer.i"
include "hw.i"
;
; this would belong in sana2.i
;
STRUCTURE Sana2DeviceStats,0
ULONG sds_PacketsReceived ;received count
ULONG sds_PacketsSent ;transmitted count
ULONG sds_BadData ;bad packets received
ULONG sds_Overruns ;hardware miss count
ULONG sds_Unused ;Unused field
ULONG sds_UnknownTypesReceived ;orphan count
ULONG sds_Reconfigurations ;network reconfigurations
STRUCT sds_LastStart,TV_SIZE ;
LABEL sds_SIZEOF
;
;
;
STRUCTURE ServerData,0
ULONG sv_flags
APTR sv_frame ;temporary frame for rx/tx
ULONG sv_framesize ;allocated bytes
STRUCT sv_mclist,LH_SIZE ;list of multicast addresses to accept
LABEL sv_SIZEOF
;
; Unit flags
;
DUB_OPEN EQU 0
DUB_EXCLUSIVE EQU 1
DUB_ONLINE EQU 2
DUB_TYPETRACK EQU 3
DUB_PROMISC EQU 4
DUF_OPEN EQU (1<<DUB_OPEN)
DUF_EXCLUSIVE EQU (1<<DUB_EXCLUSIVE)
DUF_ONLINE EQU (1<<DUB_ONLINE)
DUF_TYPETRACK EQU (1<<DUB_TYPETRACK)
DUF_PROMISC EQU (1<<DUB_PROMISC)
;
;local to each unit of the device
;
STRUCTURE DevUnit,0
STRUCT du_ReadTypes,LH_SIZE ;RX queues are sorted by type: find RX buffers
;by type, afterwards traverse active readers = networking stacks
STRUCT du_ReadOrphans,LH_SIZE ;not claimed by RX types or no buffers available -> orphan
STRUCT du_WriteQueue,LH_SIZE ;TX queue
STRUCT du_EventQueue,LH_SIZE ;Event queue
STRUCT du_Sem,SS_SIZE ;list locking (global per unit)
STRUCT du_WrSem,SS_SIZE ;write list locking
ULONG du_OpenCount ;unit openers
ULONG du_Flags ;unit flags
ULONG du_MTU ;maximum transmission unit (1500 for regular Ethernet)
ULONG du_BitPerSec ;speed in BPS
STRUCT du_HWAddr,6 ;default MAC address
STRUCT du_CFGAddr,6 ;configured MAC address
STRUCT du_DevStats,sds_SIZEOF ;collect device stats per unit
; HW Data (generic for now)
ULONG du_hwl0 ;
ULONG du_hwl1 ;
ULONG du_hwl2 ;
APTR du_hwp0 ;
APTR du_hwp1 ;
APTR du_hwp2 ;
LABEL du_SIZEOF
;
; Device Base
;
STRUCT devbase,LIB_SIZE
APTR db_SegList ;from Device Init, actually a BPTR
ULONG db_Flags ;misc
APTR db_SysBase ;Exec Base
APTR db_DOSBase ;
APTR db_UtilityBase ;
ULONG db_NBoards ;
ULONG db_ID ;device opener ID enumeration
STRUCT db_Units,du_SIZEOF*MAX_UNITS ;don't bother with lists, who's gonna have more
;than 1 network card of the same type, anyway ?
; server process data
STRUCT db_Sem,SS_SIZE ;list locking (global per unit)
APTR db_ServerProc ;process of main queue server
APTR db_Task ;server shutdown task address (non permanently available)
ULONG db_ServerSigMask ;shutdown signal
APTR db_ServerPort ;request forwarding (initialized by server)
STRUCT db_BufferManagement,LH_SIZE ;remember allocated instances
;services for other instances (server task, hw.c)
STRUCT db_svdat,sv_SIZEOF ;private data for main server
;from hwprivate.i
STRUCT db_hwdat,4 ;TODO: implement hwprivate.i
LABEL db_SIZEOF
;TODO:
;struct db_BufferManagement
;struct ServerMsg
;struct SanaReader
;struct SanaReadType
;struct MCastEntry
endc ;_INC_DEVICE_I
Driver/baxnet/source/deviceheader.c
-81
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@@ -1,81 +0,0 @@
/*
Device Header - ROMTAG
(C) 2018 Henryk Richter <henryk.richter@gmx.net>
taken from commandline (compiler options)
-DDEVICENAME=blah.device
-DDEVICEVERSION=45
-DDEVICEREVISION=36
-DDEVICEDATE=2.12.2012
*/
#include <exec/resident.h>
#include <exec/nodes.h>
#include <exec/initializers.h>
#include <exec/libraries.h>
#ifdef HAVE_VERSION_H
#include "version.h"
#endif
#include "compiler.h"
#include "device.h"
/* Enable this if you want pure C for the device. (disable compilation of romtag.asm in that case)
I personally prefer a small ASM blob to steer away from linking challenges.
*/
#if 1
extern const char DeviceName[];
extern const char DeviceVersionString[];
extern const APTR DeviceInitTab[];
/* force moveq #0,d0;rts in front of the ROMTAG */
#if 1
struct myrt0 {
ULONG ret0;
struct Resident rt;
};
/* There is a trick here:
LibNull() is actually a function returning 0
*/
const struct myrt0 LibNull =
{
0x70004E75,
{
RTC_MATCHWORD,
( struct Resident* ) ((char *)&LibNull+sizeof(ULONG)),
( struct Resident* ) ((char *)&LibNull+sizeof(ULONG)+sizeof(struct Resident)),
RTF_AUTOINIT,
DEVICEVERSION,
NT_DEVICE,
0,
(char*)DeviceName,
(char*)DeviceVersionString+6,
(APTR)DeviceInitTab
}
};
#else
/* hope that the compiler will put LibNull first */
ASM LONG LibNull( void )
{
return 0;
}
static const struct Resident _00RomTag = {
RTC_MATCHWORD,
( struct Resident* ) &_00RomTag,
( struct Resident* ) &_00RomTag + 1,
RTF_AUTOINIT,
DEVICEVERSION,
NT_DEVICE,
0,
(char*)DeviceName,
(char*)DeviceVersionString+6,
(APTR)DeviceInitTab
};
#endif
#endif
Driver/baxnet/source/deviceinit.c
-78
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@@ -1,78 +0,0 @@
/*
devinit.c
(C) 2018 Henryk Richter <henryk.richter@gmx.net>
initialization structures and data
*/
#include <proto/exec.h>
#include <proto/utility.h>
#include <proto/dos.h>
#include <dos/dostags.h>
#include <utility/tagitem.h>
#include <exec/lists.h>
#ifdef HAVE_VERSION_H
#include "version.h"
#endif
#include "device.h"
#include "hw.h"
#include "macros.h"
#include <exec/initializers.h>
#define xstr(a) str(a)
#define str(a) #a
#ifndef DEVICEEXTRA
#define DEVICEEXTRA
#endif
static const char _DeviceVersionString[] = "$VER: " xstr(DEVICENAME) " " xstr(DEVICEVERSION) "." xstr(DEVICEREVISION) xstr(DEVICEEXTRA) " (" xstr(DEVICEDATE) ")";
const char *DeviceVersionString = (const char *)_DeviceVersionString;
const char DeviceName[] = xstr(DEVICENAME);
ASM LONG LibNull( void );
const APTR DeviceFunctions[] = {
(APTR) DevOpen,
(APTR) DevClose,
(APTR) DevExpunge,
(APTR) LibNull,
(APTR) DevBeginIO,
(APTR) DevAbortIO,
(APTR) -1
};
#define WORDINIT(_a_) UWORD _a_ ##W1; UWORD _a_ ##W2; UWORD _a_ ##ARG;
#define LONGINIT(_a_) UBYTE _a_ ##A1; UBYTE _a_ ##A2; ULONG _a_ ##ARG;
struct DeviceInitData
{
WORDINIT(w1)
LONGINIT(l1)
WORDINIT(w2)
WORDINIT(w3)
WORDINIT(w4)
LONGINIT(l2)
ULONG end_initlist;
} DeviceInitializers =
{
INITBYTE( STRUCTOFFSET( Node, ln_Type), NT_DEVICE),
0x80, (UBYTE) ((LONG)STRUCTOFFSET( Node, ln_Name)), (ULONG) &DeviceName[0],
INITBYTE( STRUCTOFFSET(Library,lib_Flags), LIBF_SUMUSED|LIBF_CHANGED ),
INITWORD( STRUCTOFFSET(Library,lib_Version), DEVICEVERSION ),
INITWORD( STRUCTOFFSET(Library,lib_Revision), DEVICEREVISION ),
0x80, (UBYTE) ((LONG)STRUCTOFFSET(Library,lib_IdString)), (ULONG) &_DeviceVersionString[6],
(ULONG) 0
};
const APTR DeviceInitTab[] = {
(APTR) sizeof( DEVBASETYPE ),
(APTR) &DeviceFunctions,
(APTR) &DeviceInitializers,
(APTR) DevInit
};
Driver/baxnet/source/enc624j6net/enc624j6l.asm
-2275
View File
File diff suppressed because it is too large Load Diff
Driver/baxnet/source/enc624j6net/enc624j6l.h
-367
View File
@@ -1,367 +0,0 @@
/*
enc624j6l.h
author: Henryk Richter <henryk.richter@gmx.net>
purpose: header for low-level board access
to memory mapped ENC624J600 networking
device
note: all functions are relative to the base pointer,
determine IO space by a respective expansion.library
call
*/
#ifndef _INC_ENC624J6L_H
#define _INC_ENC624J6L_H
#include "compiler.h"
/*
Defines: flags copied from PlipBox
*/
/* result values */
#define PIO_OK 0
#define PIO_NOT_FOUND 1
#define PIO_TOO_LARGE 2
#define PIO_IO_ERR 3
/* init flags */
#define PIO_INIT_FULL_DUPLEX 1
#define PIO_INIT_LOOP_BACK 2
#define PIO_INIT_BROAD_CAST 4
#define PIO_INIT_FLOW_CONTROL 8
#define PIO_INIT_MULTI_CAST 16
#define PIO_INIT_PROMISC 32
/* status flags */
#define PIO_STATUS_VERSION 0
#define PIO_STATUS_LINK_UP 1
/* control ids */
#define PIO_CONTROL_FLOW 0
/*-- --*/
/*------------- <DANGER! APPLY CHANGES IN HERE ALSO TO enc624j6l.asm !!> ----------*/
/*-- --*/
/* buffers and locations */
#define PSTART_INIT 0x0BF0 /* 16 Bytes private storage for driver */
#define PSTOP_INIT 0x0BFF /* (see below for definitions) */
#define RXSTART_INIT 0x2000 /* start of RX buffer, room for 14 packets */
#define RXSTOP_INIT 0x5fff /* end of RX buffer */
#define TXSTART_INIT 0x0000 /* start of TX buffer, room for 2 packets */
#define TXSTOP_INIT 0x0BEF /* end of TX buffer (1536+1520 bytes) */
/* max frame length which the conroller will accept:
(note: maximum ethernet frame length would be 1518 w/o 802.1Q) */
#define MAX_FRAMELEN 1518
/* ------------ driver private storage ------------------------------ */
#define PNextPacket PSTART_INIT /* 2 Bytes - private "next packet" pointer for RX */
#define PNextTX PSTART_INIT+2 /* 2 Bytes - private "next packet" pointer for TX (init as 0) */
#define PSigBit PSTART_INIT+4 /* 2 Bytes interrupt bit */
#define PSigTask PSTART_INIT+6 /* 4 Bytes signaled task */
#define PLinkChange PSTART_INIT+10 /* 2 Bytes Link Change (Bit0 used right now) */
#define Punused PSTART_INIT+12 /* */
/* ------------- TX: double buffering -------------------------------- */
#define PSwapTX 0x600 /* swap between two TX buffers (one active, one activated after last TX done) */
/*-- --*/
/*------------- </DANGER! APPLY CHANGES IN HERE ALSO TO enc624j6l.asm !!> ---------*/
/*-- --*/
/*
Purpose: check whether the board is operating as needed
input: board - mmapped board base address
output: success/failure
>0 - all fine
<=0 - problem (codes undefined yet)
notes: The Olimex module on the Matze/Scrat ZII IDE LAN CP prototype
tends to boot in SPI mode instead of PSP (parallel) mode.
That case is detected by writing/reading data. If both bytes
of the words are equal to the last written byte, the board is likely
showing this issue.
Please note that this call will overwrite Board registers and
buffer memory. Call before initialization.
*/
ASM SAVEDS int enc624j6l_CheckBoard( ASMR(a0) void *board ASMREG(a0) );
/*
Purpose: obtain current MAC address
input: board - mmapped board base address
buffer - 6 bytes space to write into (network notation, big endian)
output: success/failure
>0 - all fine
<=0 - problem (codes undefined yet)
*/
ASM SAVEDS int enc624j6l_GetMAC( ASMR(a0) void *board ASMREG(a0),
ASMR(a1) unsigned char *buffer ASMREG(a1) );
/*
Purpose: change current MAC address
input: board - mmapped board base address
buffer - 6 bytes space to read from (network notation, big endian)
output: success/failure
>0 - all fine
<=0 - problem (codes undefined yet)
*/
ASM SAVEDS int enc624j6l_SetMAC( ASMR(a0) void *board ASMREG(a0),
ASMR(a1) unsigned char *buffer ASMREG(a1) );
/*
Purpose: delay at least the given amount of microseconds
input: delay time in microseconds
output: -
*/
ASM SAVEDS void enc28j60l_UMinDelay(
ASMR(d0) unsigned long udelay ASMREG(d0) );
/*
Purpose: initialize a board
input: board - mmapped board base address
flags - init flags (0 if in doubt)
output: success/failure
>0 - all fine
<=0 - problem (codes undefined yet)
notes:
*/
ASM SAVEDS int enc624j6l_Init( ASMR(a0) void *board ASMREG(a0),
ASMR(d1) unsigned long flags ASMREG(d1) );
/*
Purpose: stop a board
input: board - mmapped board base address
output: success/failure
>0 - all fine
<=0 - problem (codes undefined yet)
notes: Shutdown means to disconnect the PHY, put the chip
into low power mode and disable interrupts
*/
ASM SAVEDS int enc624j6l_Shutdown( ASMR(a0) void *board ASMREG(a0) );
/*
Purpose: check for pending receive frames
input: board - mmapped board base address
output: <0 - error
0 - no pending frames
>0 - number of pending frames
notes:
*/
ASM SAVEDS int enc624j6l_HaveRecv( ASMR(a0) void *board ASMREG(a0) );
/*
Purpose: copy received frame to supplied buffer
input: board - mmapped board base address
buffer - output buffer (should have >=1514 bytes)
buffersize - size of buffer
output: <0 - error
0 - nothing in receive buffer
>0 - size of received frame
notes:
*/
ASM SAVEDS int enc624j6l_RecvFrame( ASMR(a0) void *board ASMREG(a0),
ASMR(a1) unsigned char* buffer ASMREG(a1),
ASMR(d0) short buffersize ASMREG(d0) );
/*
Purpose: send single frame out
input: board - mmapped board base address
buffer - output buffer (should have >=1514 bytes)
sendsize - size of buffer in bytes ( no CRC appended (!) )
header - 14 Bytes Ethernet header
(total frame transmit size = sendsize+14)
output: <0 - error
0 - nothing in receive buffer
>0 - size of received frame
notes:
"header" argument valid only when "HW_DMA_TX" is defined (Makefile)
*/
ASM SAVEDS int enc624j6l_TransmitFrame( ASMR(a0) void *board ASMREG(a0),
ASMR(a1) unsigned char* buffer ASMREG(a1),
ASMR(d0) short sendsize ASMREG(d0)
#ifdef HW_DMA_TX
,ASMR(a2) unsigned char* header ASMREG(a2)
#endif
);
/*
Purpose: enable RX/TX, perform autonegotiation etc.
input: board - mmapped board base address
output: <0 - error
>=0 - OK
notes: in current implementation, enc624j6l_Init() will
also attach the card to the line. So this
call is not exactly needed in the init phase.
*/
ASM SAVEDS int enc624j6l_SetOnline( ASMR(a0) void *board ASMREG(a0) );
/*
Purpose: set up RX filtering
input: board - mmapped board base address
flags - broadcast,promiscous, multicast
output: <0 - error
>=0 - OK
*/
ASM SAVEDS int enc624j6l_bc_mc_filter(
ASMR(a0) void *board ASMREG(a0),
ASMR(d1) unsigned long flags ASMREG(d1),
ASMR(a1) unsigned short *mc_hashes ASMREG(a1));
/*
Purpose: disable RX/TX, power down
input: board - mmapped board base address
output: <0 - error
>=0 - OK
notes:
*/
ASM SAVEDS int enc624j6l_SetOffline( ASMR(a0) void *board ASMREG(a0) );
/*
Purpose: enable HW interrupt
input: board - mmapped board base address
SigTask - task to signal upon interrupt (or NULL)
SigBit - Signal bit to send upon interrupt (or -1)
IntMask - ENC HW interrupts to enable (set 0, for now) = RX PACKET only
output: <0 - error
>=0 - OK
notes:
*/
ASM SAVEDS int enc624j6l_EnableInterrupt( ASMR(a0) void *board ASMREG(a0),
ASMR(a1) void* SigTask ASMREG(a1),
ASMR(d0) int SigBit ASMREG(d0),
ASMR(d1) unsigned int IntMask ASMREG(d1) );
/*
Purpose: disable HW interrupt
input: board - mmapped board base address
output: <0 - error
>=0 - OK
notes:
*/
ASM SAVEDS int enc624j6l_DisableInterrupt( ASMR(a0) void *board ASMREG(a0) );
/*
Purpose: enable global HW interrupt flag on the LAN-Chip
input: board - mmapped board base address
notes:
*/
ASM SAVEDS void enc624j6l_EnableGlobalInterrupt( ASMR(a0) void *board ASMREG(a0) );
/*
Purpose: disable global HW interrupt flag on the LAN-Chip
input: board - mmapped board base address
notes:
*/
ASM SAVEDS void enc624j6l_DisableGlobalInterrupt( ASMR(a0) void *board ASMREG(a0) );
/*
Purpose: interrupt service routine ( after EnableInterrupt() )
This function will signal the task passed at EnableInterrupt time with
the given sigbit when at least one frame is pending.
input: -
output: -
*/
ASM SAVEDS void enc624j6l_IntServer_List( void );
/*
Purpose: check for link change events
input: board - mmapped board base address
output: <0 - error
0 - ok, no link change handled
>0 - ok, link change handled
notes:
*/
ASM SAVEDS int enc624j6l_CheckLinkChange( ASMR(a0) void *board ASMREG(a0) );
/*
Purpose: read PHY register
input: board - mmapped board base address
phyreg - PHY register to read
output: <0 - error
>=0 - OK
*/
ASM SAVEDS int enc624j6l_ReadPHY(
ASMR(a0) void *board ASMREG(a0),
ASMR(d0) unsigned long phyreg ASMREG(d0) );
/*
Purpose: write PHY register
input: board - mmapped board base address
phyreg - PHY register to read
value - value written into PHY reg
output: <0 - error
>=0 - OK
*/
ASM SAVEDS int enc624j6l_WritePHY(
ASMR(a0) void *board ASMREG(a0),
ASMR(d0) unsigned long phyreg ASMREG(d0),
ASMR(d1) unsigned short data ASMREG(d1) );
extern unsigned long enc624j6l_Z2Mode;
#endif /* _INC_ENC624J6L_H */
Driver/baxnet/source/enc624j6net/enc624test.c
-110
View File
@@ -1,110 +0,0 @@
/*
enc624test.c
(C) 2018 Henryk Richter <henryk.richter@gmx.net>
Matze-Scrat-Buggs ZII card hardware test
*/
#include <exec/libraries.h>
#include <proto/exec.h>
#define ENC_MANUFACTURER 2588
#define ENC_BOARD 123
#include <proto/expansion.h>
#include <proto/dos.h>
#include <libraries/configvars.h>
#include <hardware/intbits.h>
#if 0
#include "device.h"
#include "hw.h"
#include "enc624j6l.h"
#endif
#include "registers.h"
#define READREG(_x_,_off_) *( (volatile USHORT*)( (volatile UBYTE*)(_x_) + (_off_)) )
#define WRITEREG(_x_,_off_,_y_) *( (volatile USHORT*)( (volatile UBYTE*)(_x_) + (_off_)) ) = (_y_);
#define SETREG(_x_,_off_,_y_) *( (volatile USHORT*)( (volatile UBYTE*)(_x_) + (_off_) + SET_OFFSET )) = (_y_);
#define CLRREG(_x_,_off_,_y_) *( (volatile USHORT*)( (volatile UBYTE*)(_x_) + (_off_) + CLR_OFFSET )) = (_y_);
const BYTE exp_name[] = "expansion.library";
int main( int argc, char **argv )
{
LONG ret = 0;
ULONG ul;
volatile APTR board = (0);
volatile UBYTE *uboard;
struct Library *ExpansionBase;
struct ConfigDev *cfg = (0);
ExpansionBase = OpenLibrary( (BYTE*)exp_name, 37 );
if( !ExpansionBase )
{
Printf("Cannot open Expansion. quitting\n");
goto quit;
}
cfg = FindConfigDev( cfg, ENC_MANUFACTURER, ENC_BOARD );
if( cfg )
{
board = (volatile APTR)cfg->cd_BoardAddr;
}
if( !board )
{
Printf("Board %ld / %ld not found in expansions\n",(ULONG)ENC_MANUFACTURER,(ULONG)ENC_BOARD);
goto quit;
}
Printf("Board found at 0x%lx\n",(ULONG)board);
/* 16 Bit R/W Test */
Printf("16 Bit reg test\n",(ULONG)board);
WRITEREG( board, EUDAST, 0x1234 );
ul = READREG( board, EUDAST );
if( ul != 0x1234 )
{
Printf("Board error: wrote 0x1234, got 0x%lx\n",ul);
ret = 1;
}
WRITEREG( board, EUDAST, 0x0000 );
/* Byte R/W tests */
Printf("8 Bit buffer tests\n",(ULONG)board);
WRITEREG( board, 0xBFE, 0x0000 );
uboard = (volatile UBYTE*)board;
*(uboard+0xBFE) = 0xda;
ul = READREG( board, 0xBFE );
if( ul != 0xda00 )
{
Printf("Board error: expected 0xDA00, got 0x%lx on upper byte test\n",ul);
ret = 1;
}
WRITEREG( board, 0xBFE, 0x0000 );
*(uboard+0xBFF) = 0xbf;
ul = READREG( board, 0xBFE );
if( ul != 0x00bf )
{
Printf("Board error: expected 0x00BF, got 0x%lx on lower byte test\n",ul);
ret = 1;
}
if( ret )
Printf("Error(s) encountered\n");
else
Printf("Board looking good as far as tested\n");
quit:
if( ExpansionBase )
CloseLibrary(ExpansionBase);
return ret;
}
Driver/baxnet/source/enc624j6net/hw.c
-794
View File
@@ -1,794 +0,0 @@
/*
hw.c
(C) 2018 Henryk Richter <henryk.richter@gmx.net>
Matze-Scrat-Buggs ZII card hardware interface to device
*/
#include <exec/libraries.h>
#include <proto/exec.h>
#include <exec/execbase.h>
/*#include <clib/expansion_protos.h>
#include <pragmas/expansion_pragmas.h>*/
#include <proto/expansion.h>
#include <libraries/configvars.h>
#include <hardware/intbits.h>
#include "device.h"
#include "hw.h"
#include "enc624j6l.h"
#include "registers.h"
#include "mmustuff.h"
extern const BYTE DeviceName[];
#ifndef AFF_68060
#define AFF_68060 (1<<10)
#endif
#define ENC_MANUFACTURER 2588
#define ENC_BOARD 123
/* use generic board fields in current unit */
#define duh_online du_hwl0
#define duh_BASE du_hwp0
#define duh_RefCount du_hwl1
#define HW_INTERVALDEF 100000L
/* this is a BIG TODO! Make plipbox source multi-board aware */
#define BOARD hwb->hwb_boards[0]
/* interrupt (choice here is INTB_EXTER or INTB_PORTS, depending on solder blob */
/*#define HW_INTSOURCE INTB_EXTER */ /* Int 6 */
#define HW_INTSOURCE INTB_PORTS /* Int 2 */
#define READREG(_x_,_off_) *( (volatile USHORT*)( (volatile UBYTE*)(_x_) + (_off_)) )
#define WRITEREG(_x_,_off_,_y_) *( (volatile USHORT*)( (volatile UBYTE*)(_x_) + (_off_)) ) = (_y_);
#define SETREG(_x_,_off_,_y_) *( (volatile USHORT*)( (volatile UBYTE*)(_x_) + (_off_) + SET_OFFSET )) = (_y_);
#define CLRREG(_x_,_off_,_y_) *( (volatile USHORT*)( (volatile UBYTE*)(_x_) + (_off_) + CLR_OFFSET )) = (_y_);
void myhw_ControlInterrupts( DEVBASEP );
void myhw_ControlIntervalTimer( DEVBASEP );
/* these calls might not run within the context of a process and
will be called from varying tasks and without prior init:
hw_Find_Boards() - this one just identifies available HW and returns #boards
hw_AllocBoard()
hw_ReleaseBoard()
hw_GetMacAddress() - get default MAC address from board
these calls are in the context of the server task:
hw_Setup() - general init (board allocated already)
hw_Shutdown() - general shutdown (board still allocated)
hw_Attach() - make hardware ready for action (online)
hw_Detach() - put hardware into sleep mode (offline)
hw_recv_sigmask() - get signals for hardware (if any, i.e. signal on interrupt)
hw_recv_pending() - check for pending receive frames
hw_recv_frame() - receive one frame
hw_send_frame() - send one frame
hw_check_link_change() - check if HW link parameters need update
and apply them (called only when no RX/TX
in progress)
hw_ConfigInit() - set defaults for HW
hw_ConfigUpdate() - update config of HW
hw_change_multicast - re-initialize multicast filter for new address list
hw_get_mac_status() - running parameters (optional), S2_DEVICEQUERYEXT
*/
const BYTE exp_name[] = "expansion.library";
const BYTE intname[] = "enc264j6net SanaII driver";
/* return number of boards present in system */
ASM SAVEDS LONG hw_Find_Boards( ASMR(a0) DEVBASEP ASMREG(a0) )
{
LONG i,ret = 0;
struct Library *ExpansionBase;
struct ConfigDev *cfg = (0);
APTR boardbase;
if( (ExpansionBase = OpenLibrary( (STRPTR)exp_name, 37 )) )
{
/* TODO: actually verify that we have a module here */
/* ret = 1; */
enc624j6l_Z2Mode = 0;
for( i=0 ; i < MAX_UNITS ; i++ )
{
cfg = FindConfigDev( cfg, ENC_MANUFACTURER, ENC_BOARD );
if( !cfg )
break;
boardbase = (APTR)cfg->cd_BoardAddr;
db->db_Units[i].duh_BASE = boardbase;
D(("Board at %lx\n",(ULONG)cfg->cd_BoardAddr ));
/* on Z2 ? */
if( boardbase <= (APTR)0x40000000 )
{
struct ExecBase *EB = (struct ExecBase *)SysBase;
/* 68000-68030 ? */
if( !(EB->AttnFlags & (AFF_68040|AFF_68060) ))
enc624j6l_Z2Mode = 1;
}
#ifdef USEMMU
if( MMUBase )
{
/* sometimes (A3000 with SuperKickstart), the MMU table is just wrong, fix "Invalid" bit, if necessary */
setupMMU( boardbase, 0x10000, 0, db );
}
#endif
/* bring board to sane state (i.e. perform soft reset) */
/* if( boardbase < (APTR)0x40000000 ) */ /* debug only */
enc624j6l_CheckBoard( boardbase );
}
ret = i;
D(("%ld boards found\n",ret));
CloseLibrary( ExpansionBase );
}
return ret;
}
ASM SAVEDS LONG hw_AllocBoard( ASMR(a0) DEVBASEP ASMREG(a0),
ASMR(d0) ULONG unit ASMREG(d0) )
{
#if 0
LONG i;
struct ConfigDev *cfg = (0);
if( unit > db->db_NBoards )
return 0;
for( i=0 ; i < db->db_NBoards ; i++ )
{
cfg = FindConfigDev( cfg, ENC_MANUFACTURER, ENC_BOARD );
if( !cfg )
return 0;
if( (APTR)cfg->cd_BoardAddr == db->db_Units[unit].duh_BASE )
break;
}
if( (APTR)cfg->cd_BoardAddr != db->db_Units[unit].duh_BASE )
return 0;
if( db->db_Units[unit].duh_RefCount == 0 )
{
ObtainConfigBinding();
ReleaseConfigBinding();
}
db->db_Units[unit].duh_RefCount++;
#endif
return 1;
}
ASM SAVEDS LONG hw_ReleaseBoard( ASMR(a0) DEVBASEP ASMREG(a0),
ASMR(d0) ULONG unit ASMREG(d0) )
{
#if 0
if( unit > db->db_NBoards )
return 0;
for( i=0 ; i < db->db_NBoards ; i++ )
{
cfg = FindConfigDev( cfg, ENC_MANUFACTURER, ENC_BOARD );
if( !cfg )
return 0;
if( (APTR)cfg->cd_BoardAddr == db->db_Units[unit].duh_BASE )
break;
}
#endif
return 1;
}
/* store MAC address at "mac", 6 Bytes */
ASM SAVEDS LONG hw_GetMacAddress( ASMR(a0) DEVBASEP ASMREG(a0),
ASMR(d0) ULONG unit ASMREG(d0),
ASMR(a1) UBYTE *mac ASMREG(a1)
)
{
APTR boardbase = db->db_Units[unit].duh_BASE;
enc624j6l_GetMAC( boardbase, mac );
return 1;
}
/* prepare all boards such that a hw_attach() will succeed */
ASM SAVEDS LONG hw_Setup( ASMR(a0) DEVBASEP ASMREG(a0) )
{
LONG ret = 0;
struct HWData *hwd = &db->db_hwdat;
InitSemaphore( &hwd->hwd_Sem );
hwd->hwd_IntSig = AllocSignal(-1);
hwd->hwd_Interrupt.is_Data = (0);
if( InitIntervalTimer( &hwd->ivtimer ) > 0 )
{
hwd->hwd_SigMask = hwd->ivtimer.IVT_SigMask | (1<<(hwd->hwd_IntSig)) ;
ret = 1;
}
return ret;
}
/* free resources, server is quitting */
ASM SAVEDS void hw_Shutdown( ASMR(a0) DEVBASEP ASMREG(a0) )
{
struct HWData *hwd = &db->db_hwdat;
LONG i;
/* safety measure */
for( i=0 ; i < db->db_NBoards ; i++ )
db->db_Units[i].duh_online = 0;
myhw_ControlInterrupts( db );
myhw_ControlIntervalTimer( db );
if( hwd->hwd_IntSig >= 0 )
FreeSignal( hwd->hwd_IntSig );
ExitIntervalTimer( &hwd->ivtimer );
}
/* bring hardware online */
ASM SAVEDS LONG hw_Attach( ASMR(a0) DEVBASEP ASMREG(a0),
ASMR(d0) ULONG unit ASMREG(d0))
{
struct HWData *hwd = &db->db_hwdat;
APTR boardbase = db->db_Units[unit].duh_BASE;
LONG ret = 1;
ULONG flags;
flags = PIO_INIT_BROAD_CAST;
if( hwd->multicast )
flags |= PIO_INIT_MULTI_CAST;
if( hwd->fullduplex )
flags |= PIO_INIT_FULL_DUPLEX;
if( hwd->flowcontrol )
flags |= PIO_INIT_FLOW_CONTROL;
if( enc624j6l_Init( boardbase, flags ) <= 0 )
ret = 0; /* ERROR IN CASE OF DEVICE NOT FOUND */
else
{
enc624j6l_SetMAC( boardbase, db->db_Units[unit].du_CFGAddr );
enc624j6l_SetOnline( boardbase );
db->db_Units[unit].duh_online = 1; /* used for int server and interval timer setup */
myhw_ControlInterrupts( db ); /* start and/or stop (based on duh_online) */
myhw_ControlIntervalTimer( db ); /* start and/or stop timer (based on duh_online) */
}
return ret;
}
/* put hardware into sleep mode (offline) */
ASM SAVEDS void hw_Detach( ASMR(a0) DEVBASEP ASMREG(a0),
ASMR(d0) ULONG unit ASMREG(d0))
{
APTR boardbase = db->db_Units[unit].duh_BASE;
db->db_Units[unit].duh_online = 0; /* used for int server and interval timer setup */
myhw_ControlInterrupts( db ); /* start and/or stop (based on duh_online) */
myhw_ControlIntervalTimer( db ); /* start and/or stop timer (based on duh_online) */
enc624j6l_SetOffline( boardbase );
enc624j6l_Shutdown( boardbase );
}
ASM SAVEDS void hw_ConfigInit( ASMR(a0) DEVBASEP ASMREG(a0) )
{
struct HWData *hwd = &db->db_hwdat;
hwd->timervalue = HW_INTERVALDEF;
hwd->fullduplex = 0;
hwd->flowcontrol = 0;
hwd->multicast = 0;
#if 0
USHORT i;
for( i=0 ; i < (USHORT)db->db_NBoards ; i++ )
{ /* no need, these are defaults */
db->db_Units[i].du_MTU = 1500;
db->db_Units[i].du_BitPerSec = 10000000;
}
#endif
}
UBYTE hex2char( STRPTR src )
{
UBYTE cur = 0;
cur = *src;
if( cur >= 'a' )
cur &= ~32;
if( (cur < '0') || (cur>'F') )
return 0;
cur = ( cur < 'A' ) ? cur-'0' : cur-'A'+10;
return cur;
}
ASM SAVEDS void hw_ConfigUpdate( ASMR(a0) DEVBASEP ASMREG(a0),
ASMR(a1) void*argsv ASMREG(a1))
{
struct HWConfig *args = (struct HWConfig *)argsv; /* see hwprivate.h */
struct HWData *hwd = &db->db_hwdat;
D(("hw_ConfigUpdate\n"));
if( args->timervalue )
hwd->timervalue = *args->timervalue;
if( args->fullduplex )
hwd->fullduplex = 1;
if( args->flowcontrol )
hwd->flowcontrol = 1;
if( args->multicast )
hwd->multicast = 1;
if( args->conf_mac ) /* user-configured MAC address */
{
int i=0,val;
STRPTR src = args->conf_mac;
while( i < 6 )
{
val = hex2char( src++ ) << 4;
val |= hex2char( src++ );
if( (*src++ != ':') && (i<5) )
break;
db->db_Units[0].du_CFGAddr[i] = val;
/* db->db_Units[0].du_HWAddr[i] = val; */
i++;
}
D(("Configured MAC %s (-> %02lx%02lx%02lx%02lx%02lx%02lx\n",\
args->conf_mac, \
db->db_Units[0].du_CFGAddr[0], db->db_Units[0].du_CFGAddr[1],\
db->db_Units[0].du_CFGAddr[2], db->db_Units[0].du_CFGAddr[3],\
db->db_Units[0].du_CFGAddr[4], db->db_Units[0].du_CFGAddr[5] ));
enc624j6l_SetMAC( db->db_Units[0].duh_BASE, db->db_Units[0].du_CFGAddr );
}
}
/*
send a single frame to the hardware:
- either fully assembled frame (14 bytes DMAC,SMAC,TYPE followed by payload
- or payload in "frame" and 14 byte header in "header"
- provide Makefile-level definition of HW_DMA_TX in the latter case
- note: if you pass "header==NULL" with active HW_DMA_TX definition,
the hw_send_frame assumes the header to be present (SANA-II RAW frames) and
is handling "frame" as fully assembled frame
*/
ASM SAVEDS LONG hw_send_frame( ASMR(a0) DEVBASEP ASMREG(a0),
ASMR(d0) ULONG unit ASMREG(d0),
ASMR(a1) UBYTE *frame ASMREG(a1),
ASMR(d1) ULONG framesize ASMREG(d1)
#ifdef HW_DMA_TX
,ASMR(a2) UBYTE *header ASMREG(a2)
#endif
)
{
/* TX with separate header support ? (optional) */
enc624j6l_TransmitFrame( db->db_Units[unit].duh_BASE, frame, framesize
#ifdef HW_DMA_TX
,header
#endif
);
return 1;
}
ASM SAVEDS LONG hw_recv_pending( ASMR(a0) DEVBASEP ASMREG(a0),
ASMR(d0) ULONG unit ASMREG(d0) )
{
APTR board = db->db_Units[unit].duh_BASE;
return enc624j6l_HaveRecv( board );
}
ASM SAVEDS LONG hw_recv_frame( ASMR(a0) DEVBASEP ASMREG(a0),
ASMR(d0) ULONG unit ASMREG(d0),
ASMR(a1) UBYTE *frame ASMREG(a1))
{
LONG len;
APTR board = db->db_Units[unit].duh_BASE;
len = enc624j6l_RecvFrame( board, frame, 1522 );
return len;
}
ASM SAVEDS ULONG hw_recv_sigmask( ASMR(a0) DEVBASEP ASMREG(a0) )
{
struct HWData *hwd = &db->db_hwdat;
return hwd->hwd_SigMask;
}
/* check if HW link parameters need update -> only when board is idle otherwise (no RX/TX) */
/* re-enables hardware interrupt */
ASM SAVEDS LONG hw_check_link_change( ASMR(a0) DEVBASEP ASMREG(a0),
ASMR(d0) ULONG unit ASMREG(d0) )
{
APTR boardbase = db->db_Units[unit].duh_BASE;
enc624j6l_CheckLinkChange( boardbase ); /* somewhere $e90000 and beyond */
if( db->db_Units[unit].duh_online )
enc624j6l_EnableGlobalInterrupt( boardbase );
return 1; /* don't signal panic to the outside, everything is under control */
}
/* obtain running parameters of Ethernet MAC: link up/down, Speed, Duplex for
SANA-II DeviceQueryExtension (general parameters)
*/
ASM SAVEDS LONG hw_get_mac_status( ASMR(a0) DEVBASEP ASMREG(a0),
ASMR(d0) ULONG unit ASMREG(d0) )
{
struct HWData *hwd = &db->db_hwdat;
APTR boardbase = db->db_Units[unit].duh_BASE;
LONG ret;
LONG phstat3;
LONG phstat1;
LONG phcon1;
enc624j6l_ReadPHY( boardbase, PHSTAT1 );
phstat3 = enc624j6l_ReadPHY( boardbase, PHSTAT3 );
phcon1 = enc624j6l_ReadPHY( boardbase, PHCON1 );
phstat1 = enc624j6l_ReadPHY( boardbase, PHSTAT1 ); /* read again to see whether link is established */
if( ( phstat1 < 0 ) || ( phstat3 < 0 ) )
{
return HW_MAC_INVALID; /* no valid data found */
}
/* a) check Link */
ret = 0;
if( phstat1 & PHSTAT1_LLSTAT )
{
ret |= HW_MAC_LINK_UP;
/* if( phstat1 & PHSTAT1_ANDONE ) */ /* autonegotiation successful */
if( phcon1 & PHCON1_ANEN ) /* autonegotiation enabled */
ret |= HW_MAC_AUTONEGOTIATION;
phstat3 = (phstat3>>2)&7; /* get active Speed/Duplex */
switch( phstat3 )
{
case 6:
if( hwd->flowcontrol )
ret |= (HW_MAC_ON_FDX_FC<<HW_MACB_SPEED100);
else
ret |= (HW_MAC_ON_FDX<<HW_MACB_SPEED100);
break;
case 5:
if( hwd->flowcontrol )
ret |= (HW_MAC_ON_FDX_FC<<HW_MACB_SPEED10);
else
ret |= (HW_MAC_ON_FDX<<HW_MACB_SPEED10);
break;
case 2: ret |= (HW_MAC_ON<<HW_MACB_SPEED100);
break;
case 1: ret |= (HW_MAC_ON<<HW_MACB_SPEED10);
break;
default: break;
}
}
return ret;
}
/* read PHY register */
ASM SAVEDS LONG hw_read_phy( ASMR(a0) DEVBASEP ASMREG(a0),
ASMR(d0) ULONG unit ASMREG(d0),
ASMR(d1) ULONG reg ASMREG(d1) )
{
APTR boardbase = db->db_Units[unit].duh_BASE;
return enc624j6l_ReadPHY( boardbase, reg );
}
/* write PHY register (return -1 in case of error) */
ASM SAVEDS LONG hw_write_phy( ASMR(a0) DEVBASEP ASMREG(a0),
ASMR(d0) ULONG unit ASMREG(d0),
ASMR(d1) ULONG reg ASMREG(d1),
ASMR(d2) ULONG value ASMREG(d2) )
{
APTR boardbase = db->db_Units[unit].duh_BASE;
return enc624j6l_WritePHY( boardbase, reg, value );
}
/*
calculate CRC32 for MAC address hashing
slow but relatively short (and can be adapted to other
polynoms easily)
*/
ASM ULONG myhw_CRC32( ASMR(a0) UBYTE *buffer ASMREG(a0),
ASMR(d0) ULONG nbytes ASMREG(d0) )
{
UWORD i,j;
ULONG t,crc = 0xffffffff;
ULONG poly = 0x04c11db7;
for( j = 0 ; j < nbytes ; j++ )
{
for( i = 0 ; i < 8 ; i++ )
{
t = crc>>31;
crc <<= 1;
if( ( t ^ ( buffer[j] >> i ) ) & 0x01 )
crc ^= poly;
}
}
return crc;
}
#if 0
ASM ULONG CMPgeMAC( ASMR(a0) UBYTE *cur ASMREG(a0),
ASMR(a1) UBYTE *cmp ASMREG(a1) )
{
USHORT i;
ULONG res = 1;
for( i = 0 ; i < 6 ; i++ )
{
if( cur[i] > cmp[i] )
break;
if( cur[i] < cmp[i] )
{
res = 0;
break;
}
}
return res;
}
#endif
ASM ULONG CMPleMAC( ASMR(a0) UBYTE *cur ASMREG(a0),
ASMR(a1) UBYTE *cmp ASMREG(a1) )
{
USHORT i;
ULONG res = 1;
for( i = 0 ; i < 6 ; i++ )
{
if( cur[i] < cmp[i] )
break;
if( cur[i] > cmp[i] )
{
res = 0;
break;
}
}
return res;
}
ASM void INCMAC( ASMR(a0) UBYTE *curmc ASMREG(a0) )
{
SHORT i;
for( i=5 ; i >= 0 ; i-- )
{
curmc[i]++;
if( curmc[i] != 0 )
{
break;
}
}
}
ASM void COPYMAC( ASMR(a0) UBYTE *dest ASMREG(a0),
ASMR(a1) UBYTE *src ASMREG(a1) )
{
dest[0] = src[0];
dest[1] = src[1];
dest[2] = src[2];
dest[3] = src[3];
dest[4] = src[4];
dest[5] = src[5];
}
/* TODO: implement Multicast hashing */
ASM SAVEDS LONG hw_change_multicast( ASMR(a0) DEVBASEP ASMREG(a0),
ASMR(d0) ULONG unit ASMREG(d0),
ASMR(a1) struct List *mcastlist ASMREG(a1) )
{
APTR boardbase = db->db_Units[unit].duh_BASE;
struct HWData *hwd = &db->db_hwdat;
ULONG flags;
ULONG crc,curhash;
USHORT mc_hashes[4] = {0,0,0,0}; /* EHT1, EHT2, EHT3, EHT4 */
USHORT *hash_tab;
struct MCastEntry *mc;
UBYTE curmc[6];
flags = PIO_INIT_BROAD_CAST;
if( db->db_Units[0].du_Flags & DUF_PROMISC )
flags |= PIO_INIT_PROMISC;
if( hwd->multicast ) /* accept ALL multicast ? (config option) */
flags |= PIO_INIT_MULTI_CAST;
/* list non-empty ? */
hash_tab = NULL;
if( mcastlist->lh_Head->ln_Succ )
{
/* flags |= PIO_INIT_MULTI_CAST; */ /* see above */
hash_tab = mc_hashes;
for( mc = (struct MCastEntry *)mcastlist->lh_Head;
mc->mce_Node.mln_Succ ;
mc=(struct MCastEntry*)mc->mce_Node.mln_Succ )
{
COPYMAC( curmc, mc->mce_start );
while( CMPleMAC( curmc, mc->mce_stop ) )
{
D(("CMPleMAC %ld %02lx%02lx%02lx%02lx%02lx%02lx - %02lx%02lx%02lx%02lx%02lx%02lx\n",\
CMPleMAC( curmc, mc->mce_stop ),\
(ULONG)curmc[0],(ULONG)curmc[1],\
(ULONG)curmc[2],(ULONG)curmc[3],\
(ULONG)curmc[4],(ULONG)curmc[5],\
(ULONG)mc->mce_stop[0],(ULONG)mc->mce_stop[1],\
(ULONG)mc->mce_stop[2],(ULONG)mc->mce_stop[3],\
(ULONG)mc->mce_stop[4],(ULONG)mc->mce_stop[5] \
));
crc = myhw_CRC32( curmc, 6 );
curhash = (crc & 0x1f800000)>>23; /* 2 bit reg, 4 bit hash pos in reg */
mc_hashes[ ((curhash >> 4)&3) ] |= 1<<(curhash&0xf);
INCMAC( curmc );
}
}
}
D(("hw_change_multicast board %lx flags %lx hashtab %lx\n",(ULONG)boardbase,(ULONG)flags,(ULONG)hash_tab));
enc624j6l_bc_mc_filter(boardbase, flags, hash_tab );/* flags & (PIO_INIT_BROAD_CAST|PIO_INIT_MULTI_CAST) ); */
return 1;
}
/* global for all boards (relies on hwd_online) */
void myhw_ControlInterrupts( DEVBASEP )
{
struct HWData *hwd = &db->db_hwdat;
LONG i,flag;
ObtainSemaphore( &hwd->hwd_Sem ); /* redundant here: server is a single task -> but it looks good :-) */
flag = 0;
for( i=0 ; i < db->db_NBoards ; i++ )
{
if( db->db_Units[i].duh_online )
{
hwd->hwd_act_boards[flag] = db->db_Units[i].duh_BASE;
flag++;
}
}
hwd->hwd_act_boards[flag] = (0); /* NULL-terminate */
hwd->hwd_act_boards[flag+1] = (APTR)FindTask(0); /* append task */
hwd->hwd_act_boards[flag+2] = (APTR)hwd->hwd_IntSig; /* append sigbit */
hwd->hwd_act_boards[flag+3] = (APTR)db->db_SysBase; /* append ExecBase *((APTR*)0x4); */
if( flag ) /* determine on/off switch */
{
/* at least 1 board is online */
if( hwd->hwd_Interrupt.is_Data )
flag = 0; /* no change */
else flag = 1; /* start timer */
}
else
{
if( hwd->hwd_Interrupt.is_Data )
flag = -1; /* stop timer */
else flag = 0; /* no change */
}
/* flag is >0 = start, <0 = stop or 0 = no change */
if( flag > 0 )
{
hwd->hwd_Interrupt.is_Code = (void(*)())enc624j6l_IntServer_List;
hwd->hwd_Interrupt.is_Data = &hwd->hwd_act_boards[0];
hwd->hwd_Interrupt.is_Node.ln_Type = NT_INTERRUPT;
hwd->hwd_Interrupt.is_Node.ln_Pri = 126; /* 51; */
hwd->hwd_Interrupt.is_Node.ln_Name = (char*)intname;
AddIntServer( HW_INTSOURCE, &hwd->hwd_Interrupt );
}
for( i=0 ; i < db->db_NBoards ; i++ )
{
if( db->db_Units[i].duh_online )
enc624j6l_EnableInterrupt( db->db_Units[i].duh_BASE, FindTask(0), (int)hwd->hwd_IntSig, 0 );
else
enc624j6l_DisableInterrupt( db->db_Units[i].duh_BASE );
}
if( flag < 0 )
{
hwd->hwd_Interrupt.is_Data = (0);
RemIntServer( HW_INTSOURCE, &hwd->hwd_Interrupt );
hwd->hwd_Interrupt.is_Code = (0);
}
ReleaseSemaphore( &hwd->hwd_Sem );
}
/* global for all boards (relies on hwd_online) */
void myhw_ControlIntervalTimer( DEVBASEP )
{
struct HWData *hwd = &db->db_hwdat;
LONG i,flag;
ObtainSemaphore( &hwd->hwd_Sem );
flag = 0;
for( i=0 ; i < db->db_NBoards ; i++ )
{
if( db->db_Units[i].duh_online )
flag = 1;
}
if( flag )
{
/* at least 1 board is online */
if( hwd->ivtimer.IVT_Runflag )
flag = 0; /* no change */
else flag = 1; /* start timer */
}
else
{
if( hwd->ivtimer.IVT_Runflag )
flag = -1; /* stop timer */
else flag = 0; /* no change */
}
if( hwd->timervalue < 1000 )
flag = -1;
if( flag > 0 )
StartIntervalTimer( &hwd->ivtimer, hwd->timervalue );
if( flag < 0 )
StopIntervalTimer( &hwd->ivtimer );
ReleaseSemaphore( &hwd->hwd_Sem );
}
Driver/baxnet/source/enc624j6net/hwprivate.h
-57
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@@ -1,57 +0,0 @@
/*
hwprivate.h
(C) 2018 Henryk Richter <henryk.richter@gmx.net>
private structures for hardware instance
*/
#ifndef _INC_HWPRIVATE_H
#define _INC_HWPRIVATE_H
#include "compiler.h"
#include <libraries/configvars.h>
/* sdnet/v2expnet specific: polling timer */
#include "intervaltimer.h"
#define HW_VENDOR "a1k.org Matze Buggs Scrat"
#define HW_PRODUCT "Zorro LAN IDE CP"
/* this struct is available in devicebase and should carry global information */
struct HWData {
struct Interrupt hwd_Interrupt; /* keep the interrupt at top of HWData !! */
struct SignalSemaphore hwd_Sem; /* list locking (global per unit) */
APTR hwd_act_boards[MAX_UNITS+1+3]; /* poll all active boards by ptr in interrupt, NULL terminated, followed by SigTask,Sigbit,ExecBase */
ULONG hwd_SigMask; /* signal mask to wait for in server main instance */
struct IVT_TimerStruct ivtimer; /* Timer interval handling (via Interrupt) */
LONG TimerUsed; /* number of instances running */
LONG hwd_IntSig;
/* config options */
ULONG timervalue; /* polling interval in ms */
ULONG fullduplex; /* force full duplex */
ULONG multicast; /* multicast recv enable */
ULONG flowcontrol; /* enable RX flow control */
};
#define HW_CONFIGFILE "ENV:SANA2/enc624j6net.config"
/* appended to COMMON_TEMPLATE */
#define HW_CONFIGTEMPLATE "TIMER/K/N,FULLDUPLEX/S,MULTICAST/S,FLOWCONTROL/S,MAC/K"
/* referenced by server.c, hw.c */
struct HWConfig
{
struct CommonConfig common; /* import from hw.h, expected in server.c */
ULONG *timervalue;
ULONG fullduplex;
ULONG multicast;
ULONG flowcontrol;
STRPTR conf_mac; /* user config MAC address */
};
#endif /* _INC_HWPRIVATE_H */
Driver/baxnet/source/enc624j6net/intervaltimer.asm
-341
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@@ -1,341 +0,0 @@
******************************************************************************
* Name: intervaltimer.s *
* Date: $Date: 2016-12-18 22:20:04 +0100 (So, 18. Dez 2016) $ *
* Authors: Henryk Richter *
******************************************************************************
;MACHINE MC68040
include exec/types.i
include lvo/exec_lib.i
include lvo/dos_lib.i
include lvo/timer_lib.i
include exec/exec.i
include dos/dos.i
include dos/dostags.i
include exec/io.i
include dos/dosextens.i
include exec/lists.i
DO_TEST EQU 0
ifne 1
include "intervaltimer.i"
else
STRUCTURE IVT_TimerStruct,0
ULONG IVT_Interval ;<1e6 in microseconds
LONG IVT_Signal ;Signal that is sent back to task from interrupt
ULONG IVT_SigMask
APTR IVT_SigTask ;Task that is signaled
APTR IVT_Port
APTR IVT_IORequest
APTR IVT_Device
STRUCT IVT_Int,IS_SIZE ;
BYTE IVT_Init ; !=0 - initialized
BYTE IVT_Runflag ; current status ( !=0 = running )
BYTE IVT_Stopflag ; stop request if != 0
BYTE IVT_Unused ;
ULONG IVT_Counter ; Counter (statistics)
LABEL IVT_Size
endc
xdef _InterruptIntervalTimer
xdef _InitIntervalTimer
xdef _ExitIntervalTimer
xdef _StartIntervalTimer
xdef _StopIntervalTimer
CALLEXEC macro
move.l 4.w,a6
jsr _LVO\1(a6)
endm
;section code,text
ifne DO_TEST
TestTimer:
lea dos_name,a1 ;string base
moveq #0,d0
move.l 4.w,a6
jsr _LVOOpenLibrary(a6)
move.l d0,dosbase
beq .nodos
move.l dosbase,a6
jsr _LVOOutput(a6) ;get stdout
move.l d0,stdout
lea timerbase,a1
bsr _InitIntervalTimer
tst.l d0
bge .ok
move.l stdout,d0
move.l #failtimer,d1
move.l dosbase,16
jsr _LVOPutStr(a6)
bra .error
.ok
lea timerbase,a1
move.l #10000,d1
bsr _StartIntervalTimer
moveq #0,d3
.loop
cmp.l #10,d3
bgt.s .exitloop
move.l dosbase,A6
moveq #10,d1
jsr _LVODelay(a6)
addq.l #1,d3
lea timerbase,a1
cmp.l #100,IVT_Counter(a1)
blt.s .loop
.exitloop:
move.l #succname,d1
cmp.l #10,d3
ble.s .succ
move.l #failname,d1
.succ:
jsr _LVOVPrintf(a6)
lea timerbase,a1
bsr _StopIntervalTimer
.error
lea timerbase,a1
bsr _ExitIntervalTimer
move.l dosbase,d0
beq.s .nodos
move.l d0,a1
move.l 4.w,a6
jsr _LVOCloseLibrary(a6)
.nodos:
rts
ENDC ;DO_TEST
; A1 = IVT_TimerStruct
_InterruptIntervalTimer:
movem.l d1-a6,-(sp)
;<- basic Timer.device ops ->
move.l a1,a2
move.l IVT_Port(a2),a0
CALLEXEC GetMsg
tst.l d0
beq.s .error
move.l IVT_SigMask(a2),d0 ;move.l IVT_Signal(a2),d0
move.l IVT_SigTask(a2),a1
CALLEXEC Signal
tst.b IVT_Stopflag(a2)
bne.s .error ;not exactly an error but same consequence
move.l a2,a1
bsr _RestartIntervalTimer
;<- end basic Timer.device ops ->
;<- useful stuff ->
addq.l #1,IVT_Counter(a2)
;<- useful stuff ->
bra.s .endintroutine
.error:
clr.b IVT_Runflag(a2)
.endintroutine:
movem.l (sp)+,d1-a6
rts
_InitIntervalTimer: ;prepare timer.device for buffer swap interrupt
movem.l d1-a6,-(sp)
move.l a1,a2
move #IVT_Size-1,d0
.clr
clr.b (a1)+ ;
dbf d0,.clr
sf IVT_Init(a2)
sf IVT_Runflag(a2)
;signal to wait for from timer output if output queue full
moveq #-1,d0
CALLEXEC AllocSignal
move.l d0,IVT_Signal(a2) ; <0 ? error, valid are 0..31
blt .error ; error: have to go (shouldn't happen)
moveq #0,d1
bset d0,d1
move.l d1,IVT_SigMask(a2)
suba.l a1,a1
CALLEXEC FindTask
move.l d0,IVT_SigTask(a2)
CALLEXEC CreateMsgPort ;Create MsgPort for timing...
move.l d0,IVT_Port(a2)
beq .error ;0=error
move.l IVT_Port(a2),a0
move.l #IOTV_SIZE,d0
CALLEXEC CreateIORequest
move.l d0,IVT_IORequest(a2)
beq .error ;0=error
lea.l IVT_Int(a2),a0
lea _InterruptIntervalTimer(pc),a1
move.l a1,IS_CODE(a0)
move.l a2,IS_DATA(a0)
move.b #NT_INTERRUPT,LN_TYPE(a0)
move.b #0,LN_PRI(a0) ;-32,-16,0,16,32
move.l IVT_Port(a2),a1
;move.b #NT_MSGPORT,LN_TYPE(a1)
move.b #PA_SOFTINT,MP_FLAGS(a1)
move.l a0,MP_SIGTASK(a1) ;Softint eintragen
lea VBtimer_name,a0
moveq #UNIT_MICROHZ,d0
move.l IVT_IORequest(a2),a1
moveq #0,d1
CALLEXEC OpenDevice
tst.l d0
beq.s .ok
moveq #0,d0
bra.s .error
.ok ;OK, timer device is ready
st IVT_Init(a2)
moveq #1,d0 ;OK
.error
movem.l (sp)+,d1-a6
;ret 0 <= err, >0 = ok
rts
_ExitIntervalTimer:
;stop timer.device
movem.l d0-a6,-(sp)
move.l a1,a2
sf IVT_Init(a2)
move.l IVT_IORequest(a2),d5
beq.s .noIO
tst.b IVT_Runflag(a2)
beq.s .noAbort
st IVT_Stopflag(a2)
ifne 0
move.l d5,a1
CALLEXEC WaitIO
else
move.l d5,a1
move.l IO_DEVICE(a1),a6
jsr DEV_ABORTIO(A6) ;clear pending requests
endc
.noAbort:
move.l d5,a1
CALLEXEC CloseDevice
move.l d5,a0
CALLEXEC DeleteIORequest
clr.l IVT_IORequest(a2)
.noIO:
move.l IVT_Port(a2),d0
beq.s .noPort
move.l d0,a0
CALLEXEC DeleteMsgPort
clr.l IVT_Port(a2)
.noPort:
move.l IVT_Signal(a2),d0
not.l d0 ;if( d0 == -1 ) d0 = 0
beq.s .nosig
not.l d0 ; swap back
CALLEXEC FreeSignal
moveq #-1,d0
move.l d0,IVT_Signal(a2)
.nosig:
movem.l (sp)+,d0-a6
rts
; input:
; A1 = IVT Structure (after init)
; D1 = Number of Microseconds
_StartIntervalTimer:
movem.l d0/a1/a2/a6,-(Sp)
move.l a1,a2
move.l d1,IVT_Interval(A2)
sf IVT_Stopflag(a2)
tst.b IVT_Runflag(a2) ;running already ? -> keep it running
bne.s .notimer
move.l a2,a1
bsr _RestartIntervalTimer
.notimer
movem.l (sp)+,d0/a1/a2/a6
rts
; Non-Public
; A1 - IVT Structure
_RestartIntervalTimer:
movem.l d0/a1/a2/a6,-(sp)
move.l a1,a2
move.l IVT_IORequest(a2),d0
beq.s .notimer
move.l d0,a1
move.w #TR_ADDREQUEST,IO_COMMAND(a1)
clr.b IO_FLAGS(a1)
clr.l IOTV_TIME+EV_HI(a1)
move.l IVT_Interval(A2),IOTV_TIME+EV_LO(a1)
move.l IO_DEVICE(a1),a6
jsr DEV_BEGINIO(A6)
st IVT_Runflag(a2)
.notimer
movem.l (sp)+,d0/a1/a2/a6
rts
_StopIntervalTimer:
movem.l d0-a6,-(Sp)
move.l a1,a2
st IVT_Stopflag(a2)
tst.b IVT_Runflag(a2)
beq.s .noIO
move.l IVT_IORequest(a2),d5
beq.s .noIO
move.l d5,a1
move.l IO_DEVICE(a1),a6
jsr DEV_ABORTIO(A6) ;clear pending requests
sf IVT_Runflag(a2)
.noIO:
movem.l (sp)+,d0-a6
rts
;section data,data
dosbase: dc.l 0
stdout: dc.l 0
timerbase: ds.b IVT_Size
VBtimer_name: dc.b "timer.device",0
ifne DO_TEST
dos_name: dc.b "dos.library",0
succname: dc.b "success: timer worked",10,0
failname: dc.b "failure: timer didn't work",10,0
failtimer: dc.b "timer open failure",10,0
ENDC ;DO_TEST
END
Driver/baxnet/source/enc624j6net/intervaltimer.h
-57
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@@ -1,57 +0,0 @@
/*
******************************************************************************
* Name: intervaltimer.h *
* Date: $Date: 2016-12-18 22:20:04 +0100 (So, 18. Dez 2016) $ *
* Authors: Henryk Richter *
******************************************************************************
*/
#ifndef _INC_INTERVALTIMER_H
#define _INC_INTERVALTIMER_H
#include <exec/memory.h>
#include <exec/interrupts.h>
#include <exec/tasks.h>
#include <exec/ports.h>
#include <devices/timer.h>
struct IVT_TimerStruct {
unsigned long IVT_Interval;
long IVT_Signal;
unsigned long IVT_SigMask;
struct Task *IVT_SigTask;
struct MsgPort *IVT_Port;
struct IORequest *IVT_IORequest;
struct Device *IVT_Device;
struct Interrupt IVT_Int;
unsigned char IVT_Init;
unsigned char IVT_Runflag;
unsigned char IVT_Stopflag;
unsigned char IVT_Unused;
unsigned long IVT_Counter;
};
#if 1
#include "compiler.h"
#else
/* self-contained in here as well */
#ifdef __SASC
#define ASM __asm
#define ASMR(x) register __ ## x
#define ASMREG(x)
#define SAVEDS __saveds
#else
#define ASM
#define ASMR(x) register
#define ASMREG(x) __asm("" #x "")
#define SAVEDS __saveds
#endif
#endif
ASM SAVEDS int InitIntervalTimer( ASMR(a1) struct IVT_TimerStruct* IntervalTimer ASMREG(a1) );
ASM SAVEDS int StartIntervalTimer( ASMR(a1) struct IVT_TimerStruct* IntervalTimer ASMREG(a1),
ASMR(d1) unsigned long Microsecs ASMREG(d1) );
ASM SAVEDS int StopIntervalTimer( ASMR(a1) struct IVT_TimerStruct* IntervalTimer ASMREG(a1) );
ASM SAVEDS int ExitIntervalTimer( ASMR(a1) struct IVT_TimerStruct* IntervalTimer ASMREG(a1) );
#endif /* _INC_INTERVALTIMER_H */
Driver/baxnet/source/enc624j6net/intervaltimer.i
-27
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@@ -1,27 +0,0 @@
******************************************************************************
* Name: intervaltimer.i *
* Date: $Date: 2016-12-18 22:20:04 +0100 (So, 18. Dez 2016) $ *
* Authors: Henryk Richter *
******************************************************************************
ifnd _INC_INTERVALTIMER_I
_INC_INTERVALTIMER_I EQU 1
include exec/types.i
STRUCTURE IVT_TimerStruct,0
ULONG IVT_Interval ;<1e6 in microseconds
LONG IVT_Signal ;Signal that is sent back to task from interrupt
ULONG IVT_SigMask ;signal mask
APTR IVT_SigTask ;Task that is signaled
APTR IVT_Port
APTR IVT_IORequest
APTR IVT_Device
STRUCT IVT_Int,IS_SIZE ;
BYTE IVT_Init ; !=0 - initialized
BYTE IVT_Runflag ; current status ( !=0 = running )
BYTE IVT_Stopflag ; stop request if != 0
BYTE IVT_Unused ;
ULONG IVT_Counter ; Counter (statistics)
LABEL IVT_Size
endc ;_INC_TIMERTEST_I
Driver/baxnet/source/enc624j6net/macros.i
-126
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@@ -1,126 +0,0 @@
; ------------------------------------------------------------------------------
; | Lowlevel Access to memory mapped ENC624J600 in PSP mode |
; | Henryk Richter <henryk.richter@gmx.net> |
; ------------------------------------------------------------------------------
; macro section
;------------------ options, some depend on hardware (CPLD) configuration -------------------------
_OPT_BUFFER_SWAP EQU 0 ;perform byte swap on buffer ops (1) or assume native endian (0)
_OPT_REG_SWAP EQU 0 ;perform byte swap on register ops (1) or assume native endian (0)
_OPT_ADR_QUIRK EQU 0 ;address lines 12/13 are swapped (1) or linear addressing (0)
_OPT_FLOWCONTROL EQU 0 ;perform flow control on RX (1) or not (0), obsolete (runtime option now)
_OPT_RECV EQU 1 ;faster recv (1) or generic (0)
_OPT_CHECKLINK_TX EQU 0 ;check for link changes in TX (1) or expect from outside (0) -> see server.c
;\1 register offset (without CLEAR offset)
;\2 address register of board I/O base
;\3 register with clear mask
ifne _OPT_REG_SWAP
CLRREG macro
rol.w #8,\3
move.w \3,\1+CLR_OFFSET(\2)
rol.w #8,\3
endm
;\1 register offset (without SET offset)
;\2 address register of board I/O base
;\3 register with set mask
SETREG macro
rol.w #8,\3
move.w \3,\1+SET_OFFSET(\2)
rol.w #8,\3
endm
;\1 register offset (e.g. ESTAT)
;\2 address register of board I/O base (e.g. a0)
;\3 destination register to be written (e.g. d0)
;
;important: when changing this, make sure the flags
;are set according to the return value
READREG macro
rol.w #8,\3
move.w \1(\2),\3
rol.w #8,\3
endm
;\1 register offset (e.g. ESTAT)
;\2 address register of board I/O base (e.g. a0)
;\3 soure register copied to HW register (e.g. d0)
WRITEREG macro
rol.w #8,\3
move.w \3,\1(\2)
rol.w #8,\3
endm
else
CLRREG macro
move.w \3,\1+CLR_OFFSET(\2)
endm
;\1 register offset (without SET offset)
;\2 address register of board I/O base
;\3 register with set mask
SETREG macro
move.w \3,\1+SET_OFFSET(\2)
endm
;\1 register offset (e.g. ESTAT)
;\2 address register of board I/O base (e.g. a0)
;\3 destination register to be written (e.g. d0)
;
;important: when changing this, make sure the flags
;are set according to the return value
READREG macro
move.w \1(\2),\3
endm
;\1 register offset (e.g. ESTAT)
;\2 address register of board I/O base (e.g. a0)
;\3 soure register copied to HW register (e.g. d0)
WRITEREG macro
move.w \3,\1(\2)
endm
endc
;read with address shuffling or direct from SRAM (affects $2000-$5000)
ifne _OPT_ADR_QUIRK
;\1 = address register
;\2 = data register, offset
;\3 = destination
READSRAM macro
eor.w #$6000,\2
move.w (\1,\2.w),\3
eor.w #$6000,\2
endm
else
READSRAM macro
move.w (\1,\2),\3
endm
endc
;read with address shuffling or direct from SRAM (affects $2000-$5000)
ifne _OPT_ADR_QUIRK
;\1 = address register
;\2 = data register, offset
;\3 = destination
READSRAM_LONG macro
eor.w #$6000,\2
move.l (\1,\2.w),\3
eor.w #$6000,\2
endm
else
READSRAM_LONG macro
move.l (\1,\2),\3
endm
endc
; wrap position index (in bytes) \1 (data register .w)
;
; if position >RXSTOP_INIT-1
; position = (position-RXSTOP_INIT+RXSTART_INIT)
; endif
WRAPINDEX macro
cmp.w #RXSTOP_INIT&$fffe,\1 ;wrap Dn if beyond buffer
ble.s .nowrap\0\@
add.w #RXSTART_INIT-RXSTOP_INIT-1,\1
.nowrap\0\@
endm
Driver/baxnet/source/enc624j6net/registers.h
-617
View File
@@ -1,617 +0,0 @@
/* ------------------------------------------------------------------------------ */
/* | Lowlevel Access to memory mapped ENC624J600 in PSP mode | */
/* | Henryk Richter <henryk.richter@gmx.net> | */
/* ------------------------------------------------------------------------------ */
/* register definition section */
#ifndef _REGISTERS_H_
#define _REGISTERS_H_
/* set/clr register offsets */
#define SET_OFFSET 0x0100
#define CLR_OFFSET 0x0180
/* Register definitions */
/* SPI Bank 0 registers -------- */
#define ETXST 0x7E00
#define ETXSTL 0x7E00
#define ETXSTH 0x7E01
#define ETXLEN 0x7E02
#define ETXLENL 0x7E02
#define ETXLENH 0x7E03
#define ERXST 0x7E04
#define ERXSTL 0x7E04
#define ERXSTH 0x7E05
#define ERXTAIL 0x7E06
#define ERXTAILL 0x7E06
#define ERXTAILH 0x7E07
#define ERXHEAD 0x7E08
#define ERXHEADL 0x7E08
#define ERXHEADH 0x7E09
#define EDMAST 0x7E0A
#define EDMASTL 0x7E0A
#define EDMASTH 0x7E0B
#define EDMALEN 0x7E0C
#define EDMALENL 0x7E0C
#define EDMALENH 0x7E0D
#define EDMADST 0x7E0E
#define EDMADSTL 0x7E0E
#define EDMADSTH 0x7E0F
#define EDMACS 0x7E10
#define EDMACSL 0x7E10
#define EDMACSH 0x7E11
#define ETXSTAT 0x7E12
#define ETXSTATL 0x7E12
#define ETXSTATH 0x7E13
#define ETXWIRE 0x7E14
#define ETXWIREL 0x7E14
#define ETXWIREH 0x7E15
/* SPI all bank registers */
#define EUDAST 0x7E16
#define EUDASTL 0x7E16
#define EUDASTH 0x7E17
#define EUDAND 0x7E18
#define EUDANDL 0x7E18
#define EUDANDH 0x7E19
#define ESTAT 0x7E1A
#define ESTATL 0x7E1A
#define ESTATH 0x7E1B
#define EIR 0x7E1C
#define EIRL 0x7E1C
#define EIRH 0x7E1D
#define ECON1 0x7E1E
#define ECON1L 0x7E1E
#define ECON1H 0x7E1F
/* SPI Bank 1 registers ----- */
#define EHT1 0x7E20
#define EHT1L 0x7E20
#define EHT1H 0x7E21
#define EHT2 0x7E22
#define EHT2L 0x7E22
#define EHT2H 0x7E23
#define EHT3 0x7E24
#define EHT3L 0x7E24
#define EHT3H 0x7E25
#define EHT4 0x7E26
#define EHT4L 0x7E26
#define EHT4H 0x7E27
#define EPMM1 0x7E28
#define EPMM1L 0x7E28
#define EPMM1H 0x7E29
#define EPMM2 0x7E2A
#define EPMM2L 0x7E2A
#define EPMM2H 0x7E2B
#define EPMM3 0x7E2C
#define EPMM3L 0x7E2C
#define EPMM3H 0x7E2D
#define EPMM4 0x7E2E
#define EPMM4L 0x7E2E
#define EPMM4H 0x7E2F
#define EPMCS 0x7E30
#define EPMCSL 0x7E30
#define EPMCSH 0x7E31
#define EPMO 0x7E32
#define EPMOL 0x7E32
#define EPMOH 0x7E33
#define ERXFCON 0x7E34
#define ERXFCONL 0x7E34
#define ERXFCONH 0x7E35
/* SPI all bank registers from 0x36 to 0x3F */
/* SPI Bank 2 registers ----- */
#define MACON1 0x7E40
#define MACON1L 0x7E40
#define MACON1H 0x7E41
#define MACON2 0x7E42
#define MACON2L 0x7E42
#define MACON2H 0x7E43
#define MABBIPG 0x7E44
#define MABBIPGL 0x7E44
#define MABBIPGH 0x7E45
#define MAIPG 0x7E46
#define MAIPGL 0x7E46
#define MAIPGH 0x7E47
#define MACLCON 0x7E48
#define MACLCONL 0x7E48
#define MACLCONH 0x7E49
#define MAMXFL 0x7E4A
#define MAMXFLL 0x7E4A
#define MAMXFLH 0x7E4B
#define MICMD 0x7E52
#define MICMDL 0x7E52
#define MICMDH 0x7E53
#define MIREGADR 0x7E54
#define MIREGADRL 0x7E54
#define MIREGADRH 0x7E55
/* SPI all bank registers from 0x56 to 0x5F */
/* SPI Bank 3 registers ----- */
#define MAADR3 0x7E60
#define MAADR3L 0x7E60
#define MAADR3H 0x7E61
#define MAADR2 0x7E62
#define MAADR2L 0x7E62
#define MAADR2H 0x7E63
#define MAADR1 0x7E64
#define MAADR1L 0x7E64
#define MAADR1H 0x7E65
#define MIWR 0x7E66
#define MIWRL 0x7E66
#define MIWRH 0x7E67
#define MIRD 0x7E68
#define MIRDL 0x7E68
#define MIRDH 0x7E69
#define MISTAT 0x7E6A
#define MISTATL 0x7E6A
#define MISTATH 0x7E6B
#define EPAUS 0x7E6C
#define EPAUSL 0x7E6C
#define EPAUSH 0x7E6D
#define ECON2 0x7E6E
#define ECON2L 0x7E6E
#define ECON2H 0x7E6F
#define ERXWM 0x7E70
#define ERXWML 0x7E70
#define ERXWMH 0x7E71
#define EIE 0x7E72
#define EIEL 0x7E72
#define EIEH 0x7E73
#define EIDLED 0x7E74
#define EIDLEDL 0x7E74
#define EIDLEDH 0x7E75
/* SPI all bank registers from 0x66 to 0x6F */
/* SPI Non-banked Special Function Registers */
#define EGPDATA 0x7E80
#define EGPDATAL 0x7E80
#define ERXDATA 0x7E82
#define ERXDATAL 0x7E82
#define EUDADATA 0x7E84
#define EUDADATAL 0x7E84
#define EGPRDPT 0x7E86
#define EGPRDPTL 0x7E86
#define EGPRDPTH 0x7E87
#define EGPWRPT 0x7E88
#define EGPWRPTL 0x7E88
#define EGPWRPTH 0x7E89
#define ERXRDPT 0x7E8A
#define ERXRDPTL 0x7E8A
#define ERXRDPTH 0x7E8B
#define ERXWRPT 0x7E8C
#define ERXWRPTL 0x7E8C
#define ERXWRPTH 0x7E8D
#define EUDARDPT 0x7E8E
#define EUDARDPTL 0x7E8E
#define EUDARDPTH 0x7E8F
#define EUDAWRPT 0x7E90
#define EUDAWRPTL 0x7E90
#define EUDAWRPTH 0x7E91
/* ;;;;;;;;;;;;;;;;;;;;;;;;; */
/* ENC424J600/624J600 register bits */
/* ;;;;;;;;;;;;;;;;;;;;;;;;; */
/* ESTAT bits ---------- */
#define ESTAT_INT (1<<15)
#define ESTAT_FCIDLE (1<<14)
#define ESTAT_RXBUSY (1<<13)
#define ESTAT_CLKRDY (1<<12)
#define ESTAT_RSTDONE (1<<11)
#define ESTAT_PHYDPX (1<<10)
#define ESTAT_PHYRDY (1<<9)
#define ESTAT_PHYLNK (1<<8)
#define ESTAT_PKTCNT7 (1<<7)
#define ESTAT_PKTCNT6 (1<<6)
#define ESTAT_PKTCNT5 (1<<5)
#define ESTAT_PKTCNT4 (1<<4)
#define ESTAT_PKTCNT3 (1<<3)
#define ESTAT_PKTCNT2 (1<<2)
#define ESTAT_PKTCNT1 (1<<1)
#define ESTAT_PKTCNT0 (1)
/* EIR bits ------------ */
#define EIR_CRYPTEN (1<<15)
#define EIR_MODEXIF (1<<14)
#define EIR_HASHIF (1<<13)
#define EIR_AESIF (1<<12)
#define EIR_LINKIF (1<<11)
#define EIR_PRDYIF (1<<10)
#define EIR_r9 (1<<9)
#define EIR_r8 (1<<8)
#define EIR_r7 (1<<7)
#define EIR_PKTIF (1<<6)
#define EIR_DMAIF (1<<5)
#define EIR_r4 (1<<4)
#define EIR_TXIF (1<<3)
#define EIR_TXABTIF (1<<2)
#define EIR_RXABTIF (1<<1)
#define EIR_PCFULIF (1)
/* ECON1 bits ---------- */
#define ECON1_MODEXST (1<<15)
#define ECON1_HASHEN (1<<14)
#define ECON1_HASHOP (1<<13)
#define ECON1_HASHLST (1<<12)
#define ECON1_AESST (1<<11)
#define ECON1_AESOP1 (1<<10)
#define ECON1_AESOP0 (1<<9)
#define ECON1_PKTDEC (1<<8)
#define ECON1_FCOP1 (1<<7)
#define ECON1_FCOP0 (1<<6)
#define ECON1_DMAST (1<<5)
#define ECON1_DMACPY (1<<4)
#define ECON1_DMACSSD (1<<3)
#define ECON1_DMANOCS (1<<2)
#define ECON1_TXRTS (1<<1)
#define ECON1_RXEN (1)
/* ETXSTAT bits -------- */
#define ETXSTAT_r12 (1<<12)
#define ETXSTAT_r11 (1<<11)
#define ETXSTAT_LATECOL (1<<10)
#define ETXSTAT_MAXCOL (1<<9)
#define ETXSTAT_EXDEFER (1<<8)
#define ETXSTAT_DEFER (1<<7)
#define ETXSTAT_r6 (1<<6)
#define ETXSTAT_r5 (1<<5)
#define ETXSTAT_CRCBAD (1<<4)
#define ETXSTAT_COLCNT3 (1<<3)
#define ETXSTAT_COLCNT2 (1<<2)
#define ETXSTAT_COLCNT1 (1<<1)
#define ETXSTAT_COLCNT0 (1)
/* ERXFCON bits -------- */
#define ERXFCON_HTEN (1<<15)
#define ERXFCON_MPEN (1<<14)
#define ERXFCON_NOTPM (1<<12)
#define ERXFCON_PMEN3 (1<<11)
#define ERXFCON_PMEN2 (1<<10)
#define ERXFCON_PMEN1 (1<<9)
#define ERXFCON_PMEN0 (1<<8)
#define ERXFCON_CRCEEN (1<<7)
#define ERXFCON_CRCEN (1<<6)
#define ERXFCON_RUNTEEN (1<<5)
#define ERXFCON_RUNTEN (1<<4)
#define ERXFCON_UCEN (1<<3)
#define ERXFCON_NOTMEEN (1<<2)
#define ERXFCON_MCEN (1<<1)
#define ERXFCON_BCEN (1)
/* MACON1 bits --------- */
#define MACON1_r15 (1<<15)
#define MACON1_r14 (1<<14)
#define MACON1_r11 (1<<11)
#define MACON1_r10 (1<<10)
#define MACON1_r9 (1<<9)
#define MACON1_r8 (1<<8)
#define MACON1_LOOPBK (1<<4)
#define MACON1_r3 (1<<3)
#define MACON1_RXPAUS (1<<2)
#define MACON1_PASSALL (1<<1)
#define MACON1_r0 (1)
/* MACON2 bits --------- */
#define MACON2_DEFER (1<<14)
#define MACON2_BPEN (1<<13)
#define MACON2_NOBKOFF (1<<12)
#define MACON2_r9 (1<<9)
#define MACON2_r8 (1<<8)
#define MACON2_PADCFG2 (1<<7)
#define MACON2_PADCFG1 (1<<6)
#define MACON2_PADCFG0 (1<<5)
#define MACON2_TXCRCEN (1<<4)
#define MACON2_PHDREN (1<<3)
#define MACON2_HFRMEN (1<<2)
#define MACON2_r1 (1<<1)
#define MACON2_FULDPX (1)
/* MABBIPG bits -------- */
#define MABBIPG_BBIPG6 (1<<6)
#define MABBIPG_BBIPG5 (1<<5)
#define MABBIPG_BBIPG4 (1<<4)
#define MABBIPG_BBIPG3 (1<<3)
#define MABBIPG_BBIPG2 (1<<2)
#define MABBIPG_BBIPG1 (1<<1)
#define MABBIPG_BBIPG0 (1)
/* MAIPG bits ---------- */
#define MAIPG_r14 (1<<14)
#define MAIPG_r13 (1<<13)
#define MAIPG_r12 (1<<12)
#define MAIPG_r11 (1<<11)
#define MAIPG_r10 (1<<10)
#define MAIPG_r9 (1<<9)
#define MAIPG_r8 (1<<8)
#define MAIPG_IPG6 (1<<6)
#define MAIPG_IPG5 (1<<5)
#define MAIPG_IPG4 (1<<4)
#define MAIPG_IPG3 (1<<3)
#define MAIPG_IPG2 (1<<2)
#define MAIPG_IPG1 (1<<1)
#define MAIPG_IPG0 (1)
/* MACLCON bits -------- */
#define MACLCON_r13 (1<<13)
#define MACLCON_r12 (1<<12)
#define MACLCON_r11 (1<<11)
#define MACLCON_r10 (1<<10)
#define MACLCON_r9 (1<<9)
#define MACLCON_r8 (1<<8)
#define MACLCON_MAXRET3 (1<<3)
#define MACLCON_MAXRET2 (1<<2)
#define MACLCON_MAXRET1 (1<<1)
#define MACLCON_MAXRET0 (1)
/* MICMD bits ---------- */
#define MICMD_MIISCAN (1<<1)
#define MICMD_MIIRD (1)
/* MIREGADR bits ------- */
#define MIREGADR_r12 (1<<12)
#define MIREGADR_r11 (1<<11)
#define MIREGADR_r10 (1<<10)
#define MIREGADR_r9 (1<<9)
#define MIREGADR_r8 (1<<8)
#define MIREGADR_PHREG4 (1<<4)
#define MIREGADR_PHREG3 (1<<3)
#define MIREGADR_PHREG2 (1<<2)
#define MIREGADR_PHREG1 (1<<1)
#define MIREGADR_PHREG0 (1)
/* MISTAT bits --------- */
#define MISTAT_r3 (1<<3)
#define MISTAT_NVALID (1<<2)
#define MISTAT_SCAN (1<<1)
#define MISTAT_BUSY (1)
/* ECON2 bits ---------- */
#define ECON2_ETHEN (1<<15)
#define ECON2_STRCH (1<<14)
#define ECON2_TXMAC (1<<13)
#define ECON2_SHA1MD5 (1<<12)
#define ECON2_COCON3 (1<<11)
#define ECON2_COCON2 (1<<10)
#define ECON2_COCON1 (1<<9)
#define ECON2_COCON0 (1<<8)
#define ECON2_AUTOFC (1<<7)
#define ECON2_TXRST (1<<6)
#define ECON2_RXRST (1<<5)
#define ECON2_ETHRST (1<<4)
#define ECON2_MODLEN1 (1<<3)
#define ECON2_MODLEN0 (1<<2)
#define ECON2_AESLEN1 (1<<1)
#define ECON2_AESLEN0 (1)
/* ERXWM bits ---------- */
#define ERXWM_RXFWM7 (1<<15)
#define ERXWM_RXFWM6 (1<<14)
#define ERXWM_RXFWM5 (1<<13)
#define ERXWM_RXFWM4 (1<<12)
#define ERXWM_RXFWM3 (1<<11)
#define ERXWM_RXFWM2 (1<<10)
#define ERXWM_RXFWM1 (1<<9)
#define ERXWM_RXFWM0 (1<<8)
#define ERXWM_RXEWM7 (1<<7)
#define ERXWM_RXEWM6 (1<<6)
#define ERXWM_RXEWM5 (1<<5)
#define ERXWM_RXEWM4 (1<<4)
#define ERXWM_RXEWM3 (1<<3)
#define ERXWM_RXEWM2 (1<<2)
#define ERXWM_RXEWM1 (1<<1)
#define ERXWM_RXEWM0 (1)
/* EIE bits ------------ */
#define EIE_INTIE (1<<15)
#define EIE_MODEXIE (1<<14)
#define EIE_HASHIE (1<<13)
#define EIE_AESIE (1<<12)
#define EIE_LINKIE (1<<11)
#define EIE_PRDYIE (1<<10)
#define EIE_r9 (1<<9)
#define EIE_r8 (1<<8)
#define EIE_r7 (1<<7)
#define EIE_PKTIE (1<<6)
#define EIE_DMAIE (1<<5)
#define EIE_r4 (1<<4)
#define EIE_TXIE (1<<3)
#define EIE_TXABTIE (1<<2)
#define EIE_RXABTIE (1<<1)
#define EIE_PCFULIE (1)
/* EIDLED bits --------- */
#define EIDLED_LACFG3 (1<<15)
#define EIDLED_LACFG2 (1<<14)
#define EIDLED_LACFG1 (1<<13)
#define EIDLED_LACFG0 (1<<12)
#define EIDLED_LBCFG3 (1<<11)
#define EIDLED_LBCFG2 (1<<10)
#define EIDLED_LBCFG1 (1<<9)
#define EIDLED_LBCFG0 (1<<8)
#define EIDLED_DEVID2 (1<<7)
#define EIDLED_DEVID1 (1<<6)
#define EIDLED_DEVID0 (1<<5)
#define EIDLED_REVID4 (1<<4)
#define EIDLED_REVID3 (1<<3)
#define EIDLED_REVID2 (1<<2)
#define EIDLED_REVID1 (1<<1)
#define EIDLED_REVID0 (1)
/* ; PHY REGISTERS */
#define PHCON1 0
#define PHSTAT1 1
#define PHANA 4
#define PHANLPA 5
#define PHANE 6
#define PHCON2 0x11
#define PHSTAT2 0x1b
#define PHSTAT3 0x1f
/* PHCON1 bits --------- */
#define PHCON1_PRST (1<<15)
#define PHCON1_PLOOPBK (1<<14)
#define PHCON1_SPD100 (1<<13)
#define PHCON1_ANEN (1<<12)
#define PHCON1_PSLEEP (1<<11)
#define PHCON1_r10 (1<<10)
#define PHCON1_RENEG (1<<9)
#define PHCON1_PFULDPX (1<<8)
#define PHCON1_r7 (1<<7)
#define PHCON1_r6 (1<<6)
#define PHCON1_r5 (1<<5)
#define PHCON1_r4 (1<<4)
#define PHCON1_r3 (1<<3)
#define PHCON1_r2 (1<<2)
#define PHCON1_r1 (1<<1)
#define PHCON1_r0 (1)
/* PHSTAT1 bits -------- */
#define PHSTAT1_r15 (1<<15)
#define PHSTAT1_FULL100 (1<<14)
#define PHSTAT1_HALF100 (1<<13)
#define PHSTAT1_FULL10 (1<<12)
#define PHSTAT1_HALF10 (1<<11)
#define PHSTAT1_r10 (1<<10)
#define PHSTAT1_r9 (1<<9)
#define PHSTAT1_r8 (1<<8)
#define PHSTAT1_r7 (1<<7)
#define PHSTAT1_r6 (1<<6)
#define PHSTAT1_ANDONE (1<<5)
#define PHSTAT1_LRFAULT (1<<4)
#define PHSTAT1_ANABLE (1<<3)
#define PHSTAT1_LLSTAT (1<<2)
#define PHSTAT1_r1 (1<<1)
#define PHSTAT1_EXTREGS (1)
/* PHANA bits ---------- */
#define PHANA_ADNP (1<<15)
#define PHANA_r14 (1<<14)
#define PHANA_ADFAULT (1<<13)
#define PHANA_r12 (1<<12)
#define PHANA_ADPAUS1 (1<<11)
#define PHANA_ADPAUS0 (1<<10)
#define PHANA_r9 (1<<9)
#define PHANA_AD100FD (1<<8)
#define PHANA_AD100 (1<<7)
#define PHANA_AD10FD (1<<6)
#define PHANA_AD10 (1<<5)
#define PHANA_ADIEEE4 (1<<4)
#define PHANA_ADIEEE3 (1<<3)
#define PHANA_ADIEEE2 (1<<2)
#define PHANA_ADIEEE1 (1<<1)
#define PHANA_ADIEEE0 (1)
/* PHANLPA bits -------- */
#define PHANLPA_LPNP (1<<15)
#define PHANLPA_LPACK (1<<14)
#define PHANLPA_LPFAULT (1<<13)
#define PHANLPA_r12 (1<<12)
#define PHANLPA_LPPAUS1 (1<<11)
#define PHANLPA_LPPAUS0 (1<<10)
#define PHANLPA_LP100T4 (1<<9)
#define PHANLPA_LP100FD (1<<8)
#define PHANLPA_LP100 (1<<7)
#define PHANLPA_LP10FD (1<<6)
#define PHANLPA_LP10 (1<<5)
#define PHANLPA_LPIEEE4 (1<<4)
#define PHANLPA_LPIEEE3 (1<<3)
#define PHANLPA_LPIEEE2 (1<<2)
#define PHANLPA_LPIEEE1 (1<<1)
#define PHANLPA_LPIEEE0 (1)
/* PHANE bits ---------- */
#define PHANE_r15 (1<<15)
#define PHANE_r14 (1<<14)
#define PHANE_r13 (1<<13)
#define PHANE_r12 (1<<12)
#define PHANE_r11 (1<<11)
#define PHANE_r10 (1<<10)
#define PHANE_r9 (1<<9)
#define PHANE_r8 (1<<8)
#define PHANE_r7 (1<<7)
#define PHANE_r6 (1<<6)
#define PHANE_r5 (1<<5)
#define PHANE_PDFLT (1<<4)
#define PHANE_r3 (1<<3)
#define PHANE_r2 (1<<2)
#define PHANE_LPARCD (1<<1)
#define PHANA_LPANABL (1)
/* PHCON2 bits --------- */
#define PHCON2_r15 (1<<15)
#define PHCON2_r14 (1<<14)
#define PHCON2_EDPWRDN (1<<13)
#define PHCON2_r12 (1<<12)
#define PHCON2_EDTHRES (1<<11)
#define PHCON2_r10 (1<<10)
#define PHCON2_r9 (1<<9)
#define PHCON2_r8 (1<<8)
#define PHCON2_r7 (1<<7)
#define PHCON2_r6 (1<<6)
#define PHCON2_r5 (1<<5)
#define PHCON2_r4 (1<<4)
#define PHCON2_r3 (1<<3)
#define PHCON2_FRCLNK (1<<2)
#define PHCON2_EDSTAT (1<<1)
#define PHCON2_r0 (1)
/* PHSTAT2 bits --------- */
#define PHSTAT2_r15 (1<<15)
#define PHSTAT2_r14 (1<<14)
#define PHSTAT2_r13 (1<<13)
#define PHSTAT2_r12 (1<<12)
#define PHSTAT2_r11 (1<<11)
#define PHSTAT2_r10 (1<<10)
#define PHSTAT2_r9 (1<<9)
#define PHSTAT2_r8 (1<<8)
#define PHSTAT2_r7 (1<<7)
#define PHSTAT2_r6 (1<<6)
#define PHSTAT2_r5 (1<<5)
#define PHSTAT2_PLRITY (1<<4)
#define PHSTAT2_r3 (1<<3)
#define PHSTAT2_r2 (1<<2)
#define PHSTAT2_r1 (1<<1)
#define PHSTAT2_r0 (1)
/* PHSTAT3 bits -------- */
#define PHSTAT3_r15 (1<<15)
#define PHSTAT3_r14 (1<<14)
#define PHSTAT3_r13 (1<<13)
#define PHSTAT3_r12 (1<<12)
#define PHSTAT3_r11 (1<<11)
#define PHSTAT3_r10 (1<<10)
#define PHSTAT3_r9 (1<<9)
#define PHSTAT3_r8 (1<<8)
#define PHSTAT3_r7 (1<<7)
#define PHSTAT3_r6 (1<<6)
#define PHSTAT3_r5 (1<<5)
#define PHSTAT3_SPDDPX2 (1<<4)
#define PHSTAT3_SPDDPX1 (1<<3)
#define PHSTAT3_SPDDPX0 (1<<2)
#define PHSTAT3_r1 (1<<1)
#define PHSTAT3_r0 (1)
/* ------------------------------ internal defaults ---------------------------------- */
/* 33.333Mhz clock out frequency */
#define CLOCK_33_CLR (ECON2_COCON3|ECON2_COCON2|ECON2_COCON1) /* clr mask */
#define CLOCK_33_SET (ECON2_COCON0) /* set mask */
/* 25 MHz */
#define CLOCK_25_CLR (ECON2_COCON3|ECON2_COCON2|ECON2_COCON0) /* clr mask */
#define CLOCK_25_SET (ECON2_COCON1) /* set mask */
/* 20 MHz */
#define CLOCK_20_CLR (ECON2_COCON3|ECON2_COCON2) /* clr mask */
#define CLOCK_20_SET (ECON2_COCON1|ECON2_COCON0) /* set mask */
/* 16 MHz */
#define CLOCK_16_CLR (ECON2_COCON3|ECON2_COCON0|ECON2_COCON1) /* clr mask */
#define CLOCK_16_SET (ECON2_COCON2) /* set mask */
/* 4 MHz (after reset) */
#define CLOCK_4_CLR (ECON2_COCON2) /* clr mask */
#define CLOCK_4_SET (ECON2_COCON3|ECON2_COCON0|ECON2_COCON1) /* set mask */
#define CLOCK_DEF_CLR CLOCK_33_CLR
#define CLOCK_DEF_SET CLOCK_33_SET
#endif /* _REGISTERS_H_ */
Driver/baxnet/source/enc624j6net/registers.i
-613
View File
@@ -1,613 +0,0 @@
; ------------------------------------------------------------------------------
; | Lowlevel Access to memory mapped ENC624J600 in PSP mode |
; | Henryk Richter <henryk.richter@gmx.net> |
; ------------------------------------------------------------------------------
; register definition section
; set/clr register offsets
SET_OFFSET EQU $0100
CLR_OFFSET EQU $0180
; Register definitions
; SPI Bank 0 registers --------
ETXST EQU $7E00
ETXSTL EQU $7E00
ETXSTH EQU $7E01
ETXLEN EQU $7E02
ETXLENL EQU $7E02
ETXLENH EQU $7E03
ERXST EQU $7E04
ERXSTL EQU $7E04
ERXSTH EQU $7E05
ERXTAIL EQU $7E06
ERXTAILL EQU $7E06
ERXTAILH EQU $7E07
ERXHEAD EQU $7E08
ERXHEADL EQU $7E08
ERXHEADH EQU $7E09
EDMAST EQU $7E0A
EDMASTL EQU $7E0A
EDMASTH EQU $7E0B
EDMALEN EQU $7E0C
EDMALENL EQU $7E0C
EDMALENH EQU $7E0D
EDMADST EQU $7E0E
EDMADSTL EQU $7E0E
EDMADSTH EQU $7E0F
EDMACS EQU $7E10
EDMACSL EQU $7E10
EDMACSH EQU $7E11
ETXSTAT EQU $7E12
ETXSTATL EQU $7E12
ETXSTATH EQU $7E13
ETXWIRE EQU $7E14
ETXWIREL EQU $7E14
ETXWIREH EQU $7E15
; SPI all bank registers
EUDAST EQU $7E16
EUDASTL EQU $7E16
EUDASTH EQU $7E17
EUDAND EQU $7E18
EUDANDL EQU $7E18
EUDANDH EQU $7E19
ESTAT EQU $7E1A
ESTATL EQU $7E1A
ESTATH EQU $7E1B
EIR EQU $7E1C
EIRL EQU $7E1C
EIRH EQU $7E1D
ECON1 EQU $7E1E
ECON1L EQU $7E1E
ECON1H EQU $7E1F
; SPI Bank 1 registers -----
EHT1 EQU $7E20
EHT1L EQU $7E20
EHT1H EQU $7E21
EHT2 EQU $7E22
EHT2L EQU $7E22
EHT2H EQU $7E23
EHT3 EQU $7E24
EHT3L EQU $7E24
EHT3H EQU $7E25
EHT4 EQU $7E26
EHT4L EQU $7E26
EHT4H EQU $7E27
EPMM1 EQU $7E28
EPMM1L EQU $7E28
EPMM1H EQU $7E29
EPMM2 EQU $7E2A
EPMM2L EQU $7E2A
EPMM2H EQU $7E2B
EPMM3 EQU $7E2C
EPMM3L EQU $7E2C
EPMM3H EQU $7E2D
EPMM4 EQU $7E2E
EPMM4L EQU $7E2E
EPMM4H EQU $7E2F
EPMCS EQU $7E30
EPMCSL EQU $7E30
EPMCSH EQU $7E31
EPMO EQU $7E32
EPMOL EQU $7E32
EPMOH EQU $7E33
ERXFCON EQU $7E34
ERXFCONL EQU $7E34
ERXFCONH EQU $7E35
; SPI all bank registers from 0x36 to 0x3F
; SPI Bank 2 registers -----
MACON1 EQU $7E40
MACON1L EQU $7E40
MACON1H EQU $7E41
MACON2 EQU $7E42
MACON2L EQU $7E42
MACON2H EQU $7E43
MABBIPG EQU $7E44
MABBIPGL EQU $7E44
MABBIPGH EQU $7E45
MAIPG EQU $7E46
MAIPGL EQU $7E46
MAIPGH EQU $7E47
MACLCON EQU $7E48
MACLCONL EQU $7E48
MACLCONH EQU $7E49
MAMXFL EQU $7E4A
MAMXFLL EQU $7E4A
MAMXFLH EQU $7E4B
MICMD EQU $7E52
MICMDL EQU $7E52
MICMDH EQU $7E53
MIREGADR EQU $7E54
MIREGADRL EQU $7E54
MIREGADRH EQU $7E55
; SPI all bank registers from 0x56 to 0x5F
; SPI Bank 3 registers -----
MAADR3 EQU $7E60
MAADR3L EQU $7E60
MAADR3H EQU $7E61
MAADR2 EQU $7E62
MAADR2L EQU $7E62
MAADR2H EQU $7E63
MAADR1 EQU $7E64
MAADR1L EQU $7E64
MAADR1H EQU $7E65
MIWR EQU $7E66
MIWRL EQU $7E66
MIWRH EQU $7E67
MIRD EQU $7E68
MIRDL EQU $7E68
MIRDH EQU $7E69
MISTAT EQU $7E6A
MISTATL EQU $7E6A
MISTATH EQU $7E6B
EPAUS EQU $7E6C
EPAUSL EQU $7E6C
EPAUSH EQU $7E6D
ECON2 EQU $7E6E
ECON2L EQU $7E6E
ECON2H EQU $7E6F
ERXWM EQU $7E70
ERXWML EQU $7E70
ERXWMH EQU $7E71
EIE EQU $7E72
EIEL EQU $7E72
EIEH EQU $7E73
EIDLED EQU $7E74
EIDLEDL EQU $7E74
EIDLEDH EQU $7E75
; SPI all bank registers from 0x66 to 0x6F
; SPI Non-banked Special Function Registers
EGPDATA EQU $7E80
EGPDATAL EQU $7E80
ERXDATA EQU $7E82
ERXDATAL EQU $7E82
EUDADATA EQU $7E84
EUDADATAL EQU $7E84
EGPRDPT EQU $7E86
EGPRDPTL EQU $7E86
EGPRDPTH EQU $7E87
EGPWRPT EQU $7E88
EGPWRPTL EQU $7E88
EGPWRPTH EQU $7E89
ERXRDPT EQU $7E8A
ERXRDPTL EQU $7E8A
ERXRDPTH EQU $7E8B
ERXWRPT EQU $7E8C
ERXWRPTL EQU $7E8C
ERXWRPTH EQU $7E8D
EUDARDPT EQU $7E8E
EUDARDPTL EQU $7E8E
EUDARDPTH EQU $7E8F
EUDAWRPT EQU $7E90
EUDAWRPTL EQU $7E90
EUDAWRPTH EQU $7E91
;;;;;;;;;;;;;;;;;;;;;;;;;;
; ENC424J600/624J600 register bits
;;;;;;;;;;;;;;;;;;;;;;;;;;
; ESTAT bits ----------
ESTAT_INT EQU (1<<15)
ESTAT_FCIDLE EQU (1<<14)
ESTAT_RXBUSY EQU (1<<13)
ESTAT_CLKRDY EQU (1<<12)
ESTAT_RSTDONE EQU (1<<11)
ESTAT_PHYDPX EQU (1<<10)
ESTAT_PHYRDY EQU (1<<9)
ESTAT_PHYLNK EQU (1<<8)
ESTAT_PKTCNT7 EQU (1<<7)
ESTAT_PKTCNT6 EQU (1<<6)
ESTAT_PKTCNT5 EQU (1<<5)
ESTAT_PKTCNT4 EQU (1<<4)
ESTAT_PKTCNT3 EQU (1<<3)
ESTAT_PKTCNT2 EQU (1<<2)
ESTAT_PKTCNT1 EQU (1<<1)
ESTAT_PKTCNT0 EQU (1)
; EIR bits ------------
EIR_CRYPTEN EQU (1<<15)
EIR_MODEXIF EQU (1<<14)
EIR_HASHIF EQU (1<<13)
EIR_AESIF EQU (1<<12)
EIR_LINKIF EQU (1<<11)
EIR_PRDYIF EQU (1<<10)
EIR_r9 EQU (1<<9)
EIR_r8 EQU (1<<8)
EIR_r7 EQU (1<<7)
EIR_PKTIF EQU (1<<6)
EIR_DMAIF EQU (1<<5)
EIR_r4 EQU (1<<4)
EIR_TXIF EQU (1<<3)
EIR_TXABTIF EQU (1<<2)
EIR_RXABTIF EQU (1<<1)
EIR_PCFULIF EQU (1)
; ECON1 bits ----------
ECON1_MODEXST EQU (1<<15)
ECON1_HASHEN EQU (1<<14)
ECON1_HASHOP EQU (1<<13)
ECON1_HASHLST EQU (1<<12)
ECON1_AESST EQU (1<<11)
ECON1_AESOP1 EQU (1<<10)
ECON1_AESOP0 EQU (1<<9)
ECON1_PKTDEC EQU (1<<8)
ECON1_FCOP1 EQU (1<<7)
ECON1_FCOP0 EQU (1<<6)
ECON1_DMAST EQU (1<<5)
ECON1_DMACPY EQU (1<<4)
ECON1_DMACSSD EQU (1<<3)
ECON1_DMANOCS EQU (1<<2)
ECON1_TXRTS EQU (1<<1)
ECON1_RXEN EQU (1)
; ETXSTAT bits --------
ETXSTAT_r12 EQU (1<<12)
ETXSTAT_r11 EQU (1<<11)
ETXSTAT_LATECOL EQU (1<<10)
ETXSTAT_MAXCOL EQU (1<<9)
ETXSTAT_EXDEFER EQU (1<<8)
ETXSTAT_DEFER EQU (1<<7)
ETXSTAT_r6 EQU (1<<6)
ETXSTAT_r5 EQU (1<<5)
ETXSTAT_CRCBAD EQU (1<<4)
ETXSTAT_COLCNT3 EQU (1<<3)
ETXSTAT_COLCNT2 EQU (1<<2)
ETXSTAT_COLCNT1 EQU (1<<1)
ETXSTAT_COLCNT0 EQU (1)
; ERXFCON bits --------
ERXFCON_HTEN EQU (1<<15)
ERXFCON_MPEN EQU (1<<14)
ERXFCON_NOTPM EQU (1<<12)
ERXFCON_PMEN3 EQU (1<<11)
ERXFCON_PMEN2 EQU (1<<10)
ERXFCON_PMEN1 EQU (1<<9)
ERXFCON_PMEN0 EQU (1<<8)
ERXFCON_CRCEEN EQU (1<<7)
ERXFCON_CRCEN EQU (1<<6)
ERXFCON_RUNTEEN EQU (1<<5)
ERXFCON_RUNTEN EQU (1<<4)
ERXFCON_UCEN EQU (1<<3)
ERXFCON_NOTMEEN EQU (1<<2)
ERXFCON_MCEN EQU (1<<1)
ERXFCON_BCEN EQU (1)
; MACON1 bits ---------
MACON1_r15 EQU (1<<15)
MACON1_r14 EQU (1<<14)
MACON1_r11 EQU (1<<11)
MACON1_r10 EQU (1<<10)
MACON1_r9 EQU (1<<9)
MACON1_r8 EQU (1<<8)
MACON1_LOOPBK EQU (1<<4)
MACON1_r3 EQU (1<<3)
MACON1_RXPAUS EQU (1<<2)
MACON1_PASSALL EQU (1<<1)
MACON1_r0 EQU (1)
; MACON2 bits ---------
MACON2_DEFER EQU (1<<14)
MACON2_BPEN EQU (1<<13)
MACON2_NOBKOFF EQU (1<<12)
MACON2_r9 EQU (1<<9)
MACON2_r8 EQU (1<<8)
MACON2_PADCFG2 EQU (1<<7)
MACON2_PADCFG1 EQU (1<<6)
MACON2_PADCFG0 EQU (1<<5)
MACON2_TXCRCEN EQU (1<<4)
MACON2_PHDREN EQU (1<<3)
MACON2_HFRMEN EQU (1<<2)
MACON2_r1 EQU (1<<1)
MACON2_FULDPX EQU (1)
; MABBIPG bits --------
MABBIPG_BBIPG6 EQU (1<<6)
MABBIPG_BBIPG5 EQU (1<<5)
MABBIPG_BBIPG4 EQU (1<<4)
MABBIPG_BBIPG3 EQU (1<<3)
MABBIPG_BBIPG2 EQU (1<<2)
MABBIPG_BBIPG1 EQU (1<<1)
MABBIPG_BBIPG0 EQU (1)
; MAIPG bits ----------
MAIPG_r14 EQU (1<<14)
MAIPG_r13 EQU (1<<13)
MAIPG_r12 EQU (1<<12)
MAIPG_r11 EQU (1<<11)
MAIPG_r10 EQU (1<<10)
MAIPG_r9 EQU (1<<9)
MAIPG_r8 EQU (1<<8)
MAIPG_IPG6 EQU (1<<6)
MAIPG_IPG5 EQU (1<<5)
MAIPG_IPG4 EQU (1<<4)
MAIPG_IPG3 EQU (1<<3)
MAIPG_IPG2 EQU (1<<2)
MAIPG_IPG1 EQU (1<<1)
MAIPG_IPG0 EQU (1)
; MACLCON bits --------
MACLCON_r13 EQU (1<<13)
MACLCON_r12 EQU (1<<12)
MACLCON_r11 EQU (1<<11)
MACLCON_r10 EQU (1<<10)
MACLCON_r9 EQU (1<<9)
MACLCON_r8 EQU (1<<8)
MACLCON_MAXRET3 EQU (1<<3)
MACLCON_MAXRET2 EQU (1<<2)
MACLCON_MAXRET1 EQU (1<<1)
MACLCON_MAXRET0 EQU (1)
; MICMD bits ----------
MICMD_MIISCAN EQU (1<<1)
MICMD_MIIRD EQU (1)
; MIREGADR bits -------
MIREGADR_r12 EQU (1<<12)
MIREGADR_r11 EQU (1<<11)
MIREGADR_r10 EQU (1<<10)
MIREGADR_r9 EQU (1<<9)
MIREGADR_r8 EQU (1<<8)
MIREGADR_PHREG4 EQU (1<<4)
MIREGADR_PHREG3 EQU (1<<3)
MIREGADR_PHREG2 EQU (1<<2)
MIREGADR_PHREG1 EQU (1<<1)
MIREGADR_PHREG0 EQU (1)
; MISTAT bits ---------
MISTAT_r3 EQU (1<<3)
MISTAT_NVALID EQU (1<<2)
MISTAT_SCAN EQU (1<<1)
MISTAT_BUSY EQU (1)
; ECON2 bits ----------
ECON2_ETHEN EQU (1<<15)
ECON2_STRCH EQU (1<<14)
ECON2_TXMAC EQU (1<<13)
ECON2_SHA1MD5 EQU (1<<12)
ECON2_COCON3 EQU (1<<11)
ECON2_COCON2 EQU (1<<10)
ECON2_COCON1 EQU (1<<9)
ECON2_COCON0 EQU (1<<8)
ECON2_AUTOFC EQU (1<<7)
ECON2_TXRST EQU (1<<6)
ECON2_RXRST EQU (1<<5)
ECON2_ETHRST EQU (1<<4)
ECON2_MODLEN1 EQU (1<<3)
ECON2_MODLEN0 EQU (1<<2)
ECON2_AESLEN1 EQU (1<<1)
ECON2_AESLEN0 EQU (1)
; ERXWM bits ----------
ERXWM_RXFWM7 EQU (1<<15)
ERXWM_RXFWM6 EQU (1<<14)
ERXWM_RXFWM5 EQU (1<<13)
ERXWM_RXFWM4 EQU (1<<12)
ERXWM_RXFWM3 EQU (1<<11)
ERXWM_RXFWM2 EQU (1<<10)
ERXWM_RXFWM1 EQU (1<<9)
ERXWM_RXFWM0 EQU (1<<8)
ERXWM_RXEWM7 EQU (1<<7)
ERXWM_RXEWM6 EQU (1<<6)
ERXWM_RXEWM5 EQU (1<<5)
ERXWM_RXEWM4 EQU (1<<4)
ERXWM_RXEWM3 EQU (1<<3)
ERXWM_RXEWM2 EQU (1<<2)
ERXWM_RXEWM1 EQU (1<<1)
ERXWM_RXEWM0 EQU (1)
; EIE bits ------------
EIE_INTIE EQU (1<<15)
EIE_MODEXIE EQU (1<<14)
EIE_HASHIE EQU (1<<13)
EIE_AESIE EQU (1<<12)
EIE_LINKIE EQU (1<<11)
EIE_PRDYIE EQU (1<<10)
EIE_r9 EQU (1<<9)
EIE_r8 EQU (1<<8)
EIE_r7 EQU (1<<7)
EIE_PKTIE EQU (1<<6)
EIE_DMAIE EQU (1<<5)
EIE_r4 EQU (1<<4)
EIE_TXIE EQU (1<<3)
EIE_TXABTIE EQU (1<<2)
EIE_RXABTIE EQU (1<<1)
EIE_PCFULIE EQU (1)
; EIDLED bits ---------
EIDLED_LACFG3 EQU (1<<15)
EIDLED_LACFG2 EQU (1<<14)
EIDLED_LACFG1 EQU (1<<13)
EIDLED_LACFG0 EQU (1<<12)
EIDLED_LBCFG3 EQU (1<<11)
EIDLED_LBCFG2 EQU (1<<10)
EIDLED_LBCFG1 EQU (1<<9)
EIDLED_LBCFG0 EQU (1<<8)
EIDLED_DEVID2 EQU (1<<7)
EIDLED_DEVID1 EQU (1<<6)
EIDLED_DEVID0 EQU (1<<5)
EIDLED_REVID4 EQU (1<<4)
EIDLED_REVID3 EQU (1<<3)
EIDLED_REVID2 EQU (1<<2)
EIDLED_REVID1 EQU (1<<1)
EIDLED_REVID0 EQU (1)
; PHY REGISTERS
PHCON1 EQU 0
PHSTAT1 EQU 1
PHANA EQU 4
PHANLPA EQU 5
PHANE EQU 6
PHCON2 EQU $11
PHSTAT2 EQU $1b
PHSTAT3 EQU $1f
; PHCON1 bits ---------
PHCON1_PRST EQU (1<<15)
PHCON1_PLOOPBK EQU (1<<14)
PHCON1_SPD100 EQU (1<<13)
PHCON1_ANEN EQU (1<<12)
PHCON1_PSLEEP EQU (1<<11)
PHCON1_r10 EQU (1<<10)
PHCON1_RENEG EQU (1<<9)
PHCON1_PFULDPX EQU (1<<8)
PHCON1_r7 EQU (1<<7)
PHCON1_r6 EQU (1<<6)
PHCON1_r5 EQU (1<<5)
PHCON1_r4 EQU (1<<4)
PHCON1_r3 EQU (1<<3)
PHCON1_r2 EQU (1<<2)
PHCON1_r1 EQU (1<<1)
PHCON1_r0 EQU (1)
; PHSTAT1 bits --------
PHSTAT1_r15 EQU (1<<15)
PHSTAT1_FULL100 EQU (1<<14)
PHSTAT1_HALF100 EQU (1<<13)
PHSTAT1_FULL10 EQU (1<<12)
PHSTAT1_HALF10 EQU (1<<11)
PHSTAT1_r10 EQU (1<<10)
PHSTAT1_r9 EQU (1<<9)
PHSTAT1_r8 EQU (1<<8)
PHSTAT1_r7 EQU (1<<7)
PHSTAT1_r6 EQU (1<<6)
PHSTAT1_ANDONE EQU (1<<5)
PHSTAT1_LRFAULT EQU (1<<4)
PHSTAT1_ANABLE EQU (1<<3)
PHSTAT1_LLSTAT EQU (1<<2)
PHSTAT1_r1 EQU (1<<1)
PHSTAT1_EXTREGS EQU (1)
; PHANA bits ----------
PHANA_ADNP EQU (1<<15)
PHANA_r14 EQU (1<<14)
PHANA_ADFAULT EQU (1<<13)
PHANA_r12 EQU (1<<12)
PHANA_ADPAUS1 EQU (1<<11)
PHANA_ADPAUS0 EQU (1<<10)
PHANA_r9 EQU (1<<9)
PHANA_AD100FD EQU (1<<8)
PHANA_AD100 EQU (1<<7)
PHANA_AD10FD EQU (1<<6)
PHANA_AD10 EQU (1<<5)
PHANA_ADIEEE4 EQU (1<<4)
PHANA_ADIEEE3 EQU (1<<3)
PHANA_ADIEEE2 EQU (1<<2)
PHANA_ADIEEE1 EQU (1<<1)
PHANA_ADIEEE0 EQU (1)
; PHANLPA bits --------
PHANLPA_LPNP EQU (1<<15)
PHANLPA_LPACK EQU (1<<14)
PHANLPA_LPFAULT EQU (1<<13)
PHANLPA_r12 EQU (1<<12)
PHANLPA_LPPAUS1 EQU (1<<11)
PHANLPA_LPPAUS0 EQU (1<<10)
PHANLPA_LP100T4 EQU (1<<9)
PHANLPA_LP100FD EQU (1<<8)
PHANLPA_LP100 EQU (1<<7)
PHANLPA_LP10FD EQU (1<<6)
PHANLPA_LP10 EQU (1<<5)
PHANLPA_LPIEEE4 EQU (1<<4)
PHANLPA_LPIEEE3 EQU (1<<3)
PHANLPA_LPIEEE2 EQU (1<<2)
PHANLPA_LPIEEE1 EQU (1<<1)
PHANLPA_LPIEEE0 EQU (1)
; PHANE bits ----------
PHANE_r15 EQU (1<<15)
PHANE_r14 EQU (1<<14)
PHANE_r13 EQU (1<<13)
PHANE_r12 EQU (1<<12)
PHANE_r11 EQU (1<<11)
PHANE_r10 EQU (1<<10)
PHANE_r9 EQU (1<<9)
PHANE_r8 EQU (1<<8)
PHANE_r7 EQU (1<<7)
PHANE_r6 EQU (1<<6)
PHANE_r5 EQU (1<<5)
PHANE_PDFLT EQU (1<<4)
PHANE_r3 EQU (1<<3)
PHANE_r2 EQU (1<<2)
PHANE_LPARCD EQU (1<<1)
PHANA_LPANABL EQU (1)
; PHCON2 bits ---------
PHCON2_r15 EQU (1<<15)
PHCON2_r14 EQU (1<<14)
PHCON2_EDPWRDN EQU (1<<13)
PHCON2_r12 EQU (1<<12)
PHCON2_EDTHRES EQU (1<<11)
PHCON2_r10 EQU (1<<10)
PHCON2_r9 EQU (1<<9)
PHCON2_r8 EQU (1<<8)
PHCON2_r7 EQU (1<<7)
PHCON2_r6 EQU (1<<6)
PHCON2_r5 EQU (1<<5)
PHCON2_r4 EQU (1<<4)
PHCON2_r3 EQU (1<<3)
PHCON2_FRCLNK EQU (1<<2)
PHCON2_EDSTAT EQU (1<<1)
PHCON2_r0 EQU (1)
; PHSTAT2 bits ---------
PHSTAT2_r15 EQU (1<<15)
PHSTAT2_r14 EQU (1<<14)
PHSTAT2_r13 EQU (1<<13)
PHSTAT2_r12 EQU (1<<12)
PHSTAT2_r11 EQU (1<<11)
PHSTAT2_r10 EQU (1<<10)
PHSTAT2_r9 EQU (1<<9)
PHSTAT2_r8 EQU (1<<8)
PHSTAT2_r7 EQU (1<<7)
PHSTAT2_r6 EQU (1<<6)
PHSTAT2_r5 EQU (1<<5)
PHSTAT2_PLRITY EQU (1<<4)
PHSTAT2_r3 EQU (1<<3)
PHSTAT2_r2 EQU (1<<2)
PHSTAT2_r1 EQU (1<<1)
PHSTAT2_r0 EQU (1)
; PHSTAT3 bits --------
PHSTAT3_r15 EQU (1<<15)
PHSTAT3_r14 EQU (1<<14)
PHSTAT3_r13 EQU (1<<13)
PHSTAT3_r12 EQU (1<<12)
PHSTAT3_r11 EQU (1<<11)
PHSTAT3_r10 EQU (1<<10)
PHSTAT3_r9 EQU (1<<9)
PHSTAT3_r8 EQU (1<<8)
PHSTAT3_r7 EQU (1<<7)
PHSTAT3_r6 EQU (1<<6)
PHSTAT3_r5 EQU (1<<5)
PHSTAT3_SPDDPX2 EQU (1<<4)
PHSTAT3_SPDDPX1 EQU (1<<3)
PHSTAT3_SPDDPX0 EQU (1<<2)
PHSTAT3_r1 EQU (1<<1)
PHSTAT3_r0 EQU (1)
;------------------------------ internal defaults ----------------------------------
;33.333Mhz clock out frequency
CLOCK_33_CLR EQU (ECON2_COCON3|ECON2_COCON2|ECON2_COCON1) ;clr mask
CLOCK_33_SET EQU (ECON2_COCON0) ;set mask
;25 MHz
CLOCK_25_CLR EQU (ECON2_COCON3|ECON2_COCON2|ECON2_COCON0) ;clr mask
CLOCK_25_SET EQU (ECON2_COCON1) ;set mask
;20 MHz
CLOCK_20_CLR EQU (ECON2_COCON3|ECON2_COCON2) ;clr mask
CLOCK_20_SET EQU (ECON2_COCON1|ECON2_COCON0) ;set mask
;16 MHz
CLOCK_16_CLR EQU (ECON2_COCON3|ECON2_COCON0|ECON2_COCON1) ;clr mask
CLOCK_16_SET EQU (ECON2_COCON2) ;set mask
;4 MHz (after reset)
CLOCK_4_CLR EQU (ECON2_COCON2) ;clr mask
CLOCK_4_SET EQU (ECON2_COCON3|ECON2_COCON0|ECON2_COCON1) ;set mask
; changed to 25 MHz for ZIII firmware
CLOCK_DEF_CLR EQU CLOCK_25_CLR
CLOCK_DEF_SET EQU CLOCK_25_SET
Driver/baxnet/source/hw.h
-164
View File
@@ -1,164 +0,0 @@
/*
hw.h
(C) 2018 Henryk Richter <henryk.richter@gmx.net>
Hardware dependent functions
*/
#ifndef _INC_HW_H
#define _INC_HW_H
#include "compiler.h"
#ifndef DEVBASETYPE
struct devbase;
#define DEVBASETYPE struct devbase
#endif
#ifndef DEVBASEP
#define DEVBASEP DEVBASETYPE *db
#endif
/* states for each NIC speed */
#define HW_MAC_ISACTIVE(_status_,_spd_) ( ((_status_)>>(_spd_)) & 3 ) /* returns 0 if inactive, 0...3 if active */
#define HW_MAC_OFF 0 /* this speed is inactive */
#define HW_MAC_ON 1 /* on, half duplex */
#define HW_MAC_ON_FDX 2 /* on, full duplex */
#define HW_MAC_ON_FDX_FC 3 /* on, full duplex, flow-control */
/*
MAC definitions
(flag Mask)
-> conceptually, this layout can be used for current
running mode as well as autonegotiation capabilities
masks for local NIC and peer
-> is fiber optic Ethernet relevant for us Amigans?
*/
#define HW_MAC_INVALID (-1) /* no info available */
#define HW_MAC_LINK_UP 1 /* link is up */
#define HW_MAC_AUTONEGOTIATION 2 /* autonegotiation enabled */
/* two bits each to handle the four different states per speed */
#define HW_MACB_SPEED10 2 /* bit for 10 MBit/s mask */
#define HW_MACB_SPEED100 4 /* bit for 100 MBit/s mask */
#define HW_MACB_SPEED100T2 6 /* bit for 100 MBit/s mask (100BaseT2) */
#define HW_MACB_SPEED100T4 8 /* bit for 100 MBit/s mask (100BaseT4) */
#define HW_MACB_SPEED1000 10 /* ... */
#define HW_MACB_SPEED2500 12
#define HW_MACB_SPEED5000 14
#define HW_MACB_SPEED10000 16 /* Am I optimistic ? */
#define HW_MACB_SPEEDS_END 18 /* this is the next free bit */
#define HW_MAC_SPEEDSMASK ((1<<HW_MACB_SPEEDS_END)-4)
#define HW_MAC_NEXTSPEED(_a_) ( (_a_)+2 )
/* find number of boards (stateless) */
ASM SAVEDS LONG hw_Find_Boards( ASMR(a0) DEVBASEP ASMREG(a0) );
/* allocate / release a board
note: alloc may be called more than once, keep track of number of openings
*/
ASM SAVEDS LONG hw_AllocBoard( ASMR(a0) DEVBASEP ASMREG(a0),
ASMR(d0) ULONG unit ASMREG(d0) );
ASM SAVEDS LONG hw_ReleaseBoard( ASMR(a0) DEVBASEP ASMREG(a0),
ASMR(d0) ULONG unit ASMREG(d0) );
ASM SAVEDS LONG hw_GetMacAddress(ASMR(a0) DEVBASEP ASMREG(a0),
ASMR(d0) ULONG unit ASMREG(d0),
ASMR(a1) UBYTE *mac ASMREG(a1) );
/* initialize global management stuff for hardware (called once on server startup) */
/*
Call order
- hw_Setup
hw_ConfigInit
hw_ConfigUpdate
hw_Attach
main loop: send/recv
hw_Detach
- hw_Shutdown
*/
ASM SAVEDS LONG hw_Setup( ASMR(a0) DEVBASEP ASMREG(a0) );
ASM SAVEDS void hw_Shutdown( ASMR(a0) DEVBASEP ASMREG(a0) );
ASM SAVEDS LONG hw_Attach( ASMR(a0) DEVBASEP ASMREG(a0),
ASMR(d0) ULONG unit ASMREG(d0));
ASM SAVEDS void hw_Detach( ASMR(a0) DEVBASEP ASMREG(a0),
ASMR(d0) ULONG unit ASMREG(d0));
ASM SAVEDS void hw_ConfigInit( ASMR(a0) DEVBASEP ASMREG(a0) );
ASM SAVEDS void hw_ConfigUpdate( ASMR(a0) DEVBASEP ASMREG(a0),
ASMR(a1) void * ASMREG(a1) );
/*
send a single frame to the hardware:
- either fully assembled frame (14 bytes DMAC,SMAC,TYPE followed by payload
- or payload in "frame" and 14 byte header in "header"
- provide Makefile-level definition of HW_DMA_TX in the latter case
- note: if you pass "header==NULL" with active HW_DMA_TX definition,
the hw_send_frame assumes the header to be present (SANA-II RAW frames) and
is handling "frame" as fully assembled frame
*/
ASM SAVEDS LONG hw_send_frame( ASMR(a0) DEVBASEP ASMREG(a0),
ASMR(d0) ULONG unit ASMREG(d0),
ASMR(a1) UBYTE *frame ASMREG(a1),
ASMR(d1) ULONG framesize ASMREG(d1)
#ifdef HW_DMA_TX
,ASMR(a2) UBYTE *header ASMREG(a2)
#endif
);
ASM SAVEDS LONG hw_recv_frame( ASMR(a0) DEVBASEP ASMREG(a0),
ASMR(d0) ULONG unit ASMREG(d0),
ASMR(a1) UBYTE *frame ASMREG(a1) );
ASM SAVEDS LONG hw_recv_pending( ASMR(a0) DEVBASEP ASMREG(a0),
ASMR(d0) ULONG unit ASMREG(d0) );
ASM SAVEDS LONG hw_check_link_change( ASMR(a0) DEVBASEP ASMREG(a0),
ASMR(d0) ULONG unit ASMREG(d0) );
ASM SAVEDS LONG hw_change_multicast( ASMR(a0) DEVBASEP ASMREG(a0),
ASMR(d0) ULONG unit ASMREG(d0),
ASMR(a1) struct List * ASMREG(a1) );
ASM SAVEDS LONG hw_get_mac_status( ASMR(a0) DEVBASEP ASMREG(a0),
ASMR(d0) ULONG unit ASMREG(d0) );
/* read PHY register (return -1 in case of error) */
ASM SAVEDS LONG hw_read_phy( ASMR(a0) DEVBASEP ASMREG(a0),
ASMR(d0) ULONG unit ASMREG(d0),
ASMR(d1) ULONG reg ASMREG(d1) );
/* write PHY register (return -1 in case of error) */
ASM SAVEDS LONG hw_write_phy( ASMR(a0) DEVBASEP ASMREG(a0),
ASMR(d0) ULONG unit ASMREG(d0),
ASMR(d1) ULONG reg ASMREG(d1),
ASMR(d2) ULONG value ASMREG(d2) );
/* kept this global for now: Z-II/Z-III boards share the same interrupt */
ASM SAVEDS ULONG hw_recv_sigmask( ASMR(a0) DEVBASEP ASMREG(a0) );
/* Configuration template: straight replica of Plipbox general options */
struct CommonConfig {
ULONG nospecialstats;
LONG *priority;
ULONG *bps;
ULONG *mtu;
};
#define COMMON_TEMPLATE "NOSPECIALSTATS/S,PRIORITY=PRI/K/N,BPS/K/N,MTU/K/N,"
/* additional definitions */
#include "hwprivate.h"
#endif /* _INC_HW_H */
Driver/baxnet/source/hw.i
-43
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@@ -1,43 +0,0 @@
;
; hw.i
;
; (C) 2018 Henryk Richter <henryk.richter@gmx.net>
;
; Hardware dependent definitions
;
;
;
ifnd _INC_HW_I
_INC_HW_I EQU 1
;/* states for each NIC speed */
HW_MAC_OFF EQU 0 ; this speed is inactive
HW_MAC_ON EQU 1 ; on, half duplex
HW_MAC_ON_FDX EQU 2 ; on, full duplex
HW_MAC_ON_FDX_FC EQU 3 ; on, full duplex, flow-control
;
;
; MAC definitions
; (flag Mask)
; -> conceptually, this layout can be used for current
; running mode as well as autonegotiation capabilities
; masks for local NIC and peer
;
HW_MAC_INVALID EQU -1 ; no info available
HW_MACB_LINK_UP EQU 0
HW_MACB_AUTONEGOTIATION EQU 1
HW_MAC_LINK_UP EQU (1<<HW_MACB_LINK_UP) ; link is up
HW_MAC_AUTONEGOTIATION EQU (1<<HW_MACB_AUTONEGOTIATION) ; autonegotiation enabled
; two bits each to handle the four different states per speed
HW_MACB_SPEED10 EQU 2 ; bit for 10 MBit/s mask
HW_MACB_SPEED100 EQU 4 ; bit for 100 MBit/s mask
HW_MACB_SPEED1000 EQU 6 ; ...
HW_MACB_SPEED2500 EQU 8
HW_MACB_SPEED5000 EQU 10
HW_MACB_SPEED10000 EQU 12 ; Am I optimistic ?
HW_MACB_SPEEDS_END EQU 14 ; this is the next free bit
HW_MAC_SPEEDSMASK EQU ((1<<HW_MACB_SPEEDS_END)-4)
endc ;_INC_HW_I
Driver/baxnet/source/kprintf.asm
-61
View File
@@ -1,61 +0,0 @@
;incdir include:
;ifnd _LVOSupervisor
;include lvo/exec_lib.i
;include exec/exec_lib.i
;endc
;include exec/execbase.i
;include device.i
ifnd _LVORawDoFmt
_LVORawDoFmt equ -$20a
endc
ifnd _LVORawPutChar
_LVORawPutChar equ -$204
_LVORawIOInit equ -$1f8
_LVORawMayGetChar equ -$1fe
endc
XDEF _KPrintF
XDEF _KPrintFa0a1
_KPrintF:
; rts
move.l 4(sp),a0
lea 8(sp),a1
; fall through
;A0 = format
;A1 = arguments
_KPrintFa0a1:
; ifd DEBUG
movem.l d0-d2/a0-a3/a6,-(sp)
move.l 4.w,a6
jsr _LVORawIOInit(a6) ;better safe than sorry
lea .kprintfproc(pc),a2
suba.l a3,a3 ;data pointer (0 here)
jsr _LVORawDoFmt(a6)
movem.l (sp)+,d0-d2/a0-a3/a6
rts
.kprintfproc:
movem.l d0/d1/a0/a1/a6,-(sp)
move.l 4.w,a6
jsr _LVORawPutChar(a6) ; move.b d0,(a3)+
movem.l (sp)+,d0/d1/a0/a1/a6
; endc ;DEBUG
rts
;DEBUG
; dc.l $deadbeef
; dc.l sds_SIZEOF
; dc.l sv_SIZEOF
; dc.l du_SIZEOF
; dc.l db_SIZEOF
Driver/baxnet/source/macros.h
-52
View File
@@ -1,52 +0,0 @@
/*
macros.h
(C) 2018 Henryk Richter <henryk.richter@gmx.net>
useful macros
*/
#ifndef _INC_MACROS_H
#define _INC_MACROS_H
#define GetHead(l) (void *)(((struct List *)l)->lh_Head->ln_Succ \
? ((struct List *)l)->lh_Head \
: (struct Node *)0)
#define GetTail(l) (void *)(((struct List *)l)->lh_TailPred->ln_Pred \
? ((struct List *)l)->lh_TailPred \
: (struct Node *)0)
#define GetSucc(n) (void *)(((struct Node *)n)->ln_Succ->ln_Succ \
? ((struct Node *)n)->ln_Succ \
: (struct Node *)0)
#define GetPred(n) (void *)(((struct Node *)n)->ln_Pred->ln_Pred \
? ((struct Node *)n)->ln_Pred \
: (struct Node *)0)
#define REMOVE(n) ((void)(\
((struct Node *)n)->ln_Pred->ln_Succ = ((struct Node *)n)->ln_Succ,\
((struct Node *)n)->ln_Succ->ln_Pred = ((struct Node *)n)->ln_Pred ))
#define ADDHEAD(l,n) ((void)(\
((struct Node *)n)->ln_Succ = ((struct List *)l)->lh_Head, \
((struct Node *)n)->ln_Pred = (struct Node *)&((struct List *)l)->lh_Head, \
((struct List *)l)->lh_Head->ln_Pred = ((struct Node *)n), \
((struct List *)l)->lh_Head = ((struct Node *)n)))
#define ADDTAIL(l,n) ((void)(\
((struct Node *)n)->ln_Succ = (struct Node *)&((struct List *)l)->lh_Tail, \
((struct Node *)n)->ln_Pred = ((struct List *)l)->lh_TailPred, \
((struct List *)l)->lh_TailPred->ln_Succ = ((struct Node *)n), \
((struct List *)l)->lh_TailPred = ((struct Node *)n) ))
#define NEWLIST(l) (((struct List *)l)->lh_TailPred = (struct Node *)(l), \
((struct List *)l)->lh_Tail = 0, \
((struct List *)l)->lh_Head = (struct Node *)&(((struct List *)l)->lh_Tail))
#define min(_a_,_b_) ( (_a_) > (_b_) ) ? _b_ : _a_
#define max(_a_,_b_) ( (_a_) < (_b_) ) ? _b_ : _a_
#define BOUNDS(_val_,_min_,_max_) ( (_val_) < (_min_) ) ? _min_ : ( (_val_) > (_max_) ) ? _max_ : _val_
#endif /* _INC_MACROS_H */
Driver/baxnet/source/miitool.c
-805
View File
@@ -1,805 +0,0 @@
/*******************************************************************************************/
/** **/
/** miitool.c **/
/** SANA-II extension for access to Ethernet PHY registers over MII interface **/
/** **/
/** Copyright (c) 2019, Henryk Richter, Timm S. Müller **/
/** **/
/** Redistribution and use in source and binary forms, with or without **/
/** modification, are permitted provided that the following conditions are met: **/
/** 1. Redistributions of source code must retain the above copyright **/
/** notice, this list of conditions and the following disclaimer. **/
/** 2. Redistributions in binary form must reproduce the above copyright **/
/** notice, this list of conditions and the following disclaimer in the **/
/** documentation and/or other materials provided with the distribution. **/
/** 3. All advertising materials mentioning features or use of this software **/
/** must display the following acknowledgement: **/
/** This product includes software developed by Henryk Richter. **/
/** **/
/** THIS SOFTWARE IS PROVIDED BY Henryk Richter ''AS IS'' AND ANY **/
/** EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED **/
/** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE **/
/** DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY **/
/** DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES **/
/** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; **/
/** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND **/
/** ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT **/
/** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS **/
/** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. **/
/** **/
/*******************************************************************************************/
/** Acknowledgements: **/
/** text and definitions in "media" table and "miitool.h" file originate from mii-tool.c **/
/** written/copyright 1997-2000 by Donald Becker **/
/*******************************************************************************************/
/*
Notes:
- make sure you have an up-to-date devices/sana2devqueryext.h
- make sure you have devices/newstyle.h
- compilation
sc miitool.c link INCLUDEDIR=sc:netinclude
gcc miitool.c -Igg:netinclude -o miitool
- if you don`t have the Roadshow SDK installed, just comment "RSHOW" out to build
without auto-detection code
*/
#define RSHOW
#include <proto/exec.h>
#include <proto/dos.h>
#include <proto/utility.h>
#include <devices/newstyle.h>
#include <devices/sana2.h>
#include <devices/sana2devqueryext.h>
#include "miitool.h"
#ifdef RSHOW
#include <libraries/bsdsocket.h>
#include <proto/bsdsocket.h>
#endif
#ifdef __GNUC__
struct UtilityBase *UtilityBase;
static USHORT Utility_MY = 0;
#endif
#define OPT_TEMPLATE "DEVICE=DEV/K,UNIT/K/N,VERBOSE=V/S,FORCEMEDIA/K,ADVERTISE/K,RENEG=RESTART/S,RESET/S,VERYVERBOSE=VV/S"
const char opt_template[] = OPT_TEMPLATE;
struct progopts {
BYTE *devname;
LONG *unit; /* unit to open */
ULONG verbose; /* verbose mode enabled */
BYTE *force; /* force media type */
BYTE *advertise; /* advertise specific types */
ULONG renegotiate; /* restart autonegotiation */
ULONG reset; /* reset MII */
ULONG vverbose; /* higher verbosity level */
};
struct prgdata {
struct MsgPort *sana2devport;
struct IOSana2Req *sana2devio;
struct Device *sana2dev;
UBYTE devvalid;
struct progopts opts;
BYTE *auto_devname; /* device name, if auto-detected */
};
void end_prog( struct prgdata *prg )
{
if( prg->auto_devname )
FreeVec( prg->auto_devname );
if( prg->sana2devio )
{
if( prg->devvalid )
CloseDevice( (struct IORequest *)prg->sana2devio );
DeleteIORequest( (struct IORequest *)prg->sana2devio );
}
if( prg->sana2devport )
DeleteMsgPort( prg->sana2devport );
#ifdef __GNUC__
if( (UtilityBase) && (Utility_MY) )
{
CloseLibrary( (struct Library*)UtilityBase );
Utility_MY = 0;
UtilityBase = NULL;
}
#endif /* __GNUC__ */
}
/*
note: call this only once at program startup
*/
LONG start_prog( struct prgdata *prg )
{
SHORT i;
UBYTE *t = (UBYTE*)prg;
for( i=0 ; i < sizeof( struct prgdata ) ; i++ )
*t++ = 0;
prg->sana2devport = CreateMsgPort();
if( !prg->sana2devport )
goto err;
prg->sana2devio = (struct IOSana2Req *) CreateIORequest(
prg->sana2devport, sizeof(struct IOSana2Req));
if( !prg->sana2devio )
goto err;
#ifdef __GNUC__
if( !UtilityBase )
{
UtilityBase = (struct UtilityBase*)OpenLibrary("utility.library",37);
Utility_MY = 1;
}
#endif /* __GNUC__ */
return 1;
err:
end_prog( prg );
return 0;
}
void clr_device( struct prgdata *prg )
{
if( !prg->devvalid )
return;
prg->devvalid = 0;
CloseDevice( (struct IORequest *)prg->sana2devio );
}
LONG get_device(struct prgdata *prg, BYTE *name, LONG unit )
{
if( !name )
return 0;
if( prg->devvalid ) /* close previously opened device */
clr_device( prg );
prg->devvalid = OpenDevice(name,unit,(struct IORequest *)prg->sana2devio,0) == 0;
if( !prg->devvalid )
{
Printf( "Cannot open %s unit %ld\n",(ULONG)name,unit );
return 0;
}
return 1;
}
static BOOL findcmd(struct NSDeviceQueryResult *nsdqr, UWORD cmd)
{
UWORD *p;
for (p = nsdqr->nsdqr_SupportedCommands; (*p); ++p )
if (*p == cmd)
return TRUE;
return FALSE;
}
/*
verify NSD support, SANA-II type, Device Query extension on previously opened device
*/
LONG probe_device( struct prgdata *prg )
{
struct IOStdReq *stdreq;
struct NSDeviceQueryResult nsdqr;
if( !prg )
return 0;
if( !prg->devvalid )
return 0;
stdreq = (struct IOStdReq *)prg->sana2devio;
stdreq->io_Command = NSCMD_DEVICEQUERY;
stdreq->io_Flags = 0;
stdreq->io_Data = &nsdqr;
stdreq->io_Length = sizeof nsdqr;
if (DoIO((struct IORequest *) stdreq) != 0)
{
Printf("I/O error: no NewStyleDevice.\n");
return 0;
}
if ( nsdqr.nsdqr_DeviceType != NSDEVTYPE_SANA2 )
{
Printf("Device is not a SANA-II device (type %ld, needed %ld\n).", (LONG)nsdqr.nsdqr_DeviceType, (LONG) NSDEVTYPE_SANA2 );
return 0;
}
if (!findcmd(&nsdqr, S2_DEVICEQUERYEXT))
{
Printf("Device does not support S2_DEVICEQUERYEXT.\n");
return 0;
}
return 1;
}
const struct {
BYTE *name;
UWORD namelen;
UWORD value;
} mediatypes[] = {
/* these are kept in this order for the dump loop decision about best mode */
{ "10baseT-HD", 10,MII_AN_10BASET_HD },
{ "10baseT-FD", 10,MII_AN_10BASET_FD },
{ "100baseTx-HD", 12,MII_AN_100BASETX_HD },
{ "100baseTx-FD", 12,MII_AN_100BASETX_FD },
{ "100baseT4", 9,MII_AN_100BASET4 },
/* generic mode names where only the speed matters */
{ "100baseTx", 9,MII_AN_100BASETX_FD | MII_AN_100BASETX_HD },
{ "10baseT", 7,MII_AN_10BASET_FD | MII_AN_10BASET_HD },
{ "100bTx", 6,MII_AN_100BASETX_FD | MII_AN_100BASETX_HD },
{ "10bT", 4,MII_AN_10BASET_FD | MII_AN_10BASET_HD },
};
#define NMEDIA (sizeof(mediatypes)/sizeof(mediatypes[0]))
void dump_mii_media( USHORT parms, BOOL bestonly )
{
LONG i;
for( i=9 ; i >= 5 ; i-- )
{
if( parms & (1<<i) )
{
Printf(" %s",(ULONG)mediatypes[i-5].name);
if( bestonly )
break;
}
}
if( parms & (1<<10) )
Printf(" flow-control");
}
LONG parse_speedduplex( BYTE *parameters )
{
LONG i,res = 0;
BYTE *s;
if( !parameters )
return 0;
s = parameters;
while( *s != 0 )
{
for( i=0 ; i < NMEDIA ; i++ )
if( Strnicmp( mediatypes[i].name, s, mediatypes[i].namelen ) == 0 )
break;
if( i==NMEDIA )
goto err;
s += mediatypes[i].namelen;
res |= mediatypes[i].value;
/* skip " " and/or "," */
while( *s != 0 )
{
if( (*s==' ') || (*s==',') )
s++;
else
break;
}
}
return res;
err:
Printf("Invalid media specification %s\n",(ULONG)parameters);
Printf("Valid Arguments:\n");
for( i=0 ; i < NMEDIA ; i++ )
Printf("%s\n",(ULONG)mediatypes[i].name);
return -1;
}
/*
note: this code assumes that "mii" has the register contents in network
byte ordering. Also, the registers themselves shall be consecutive
in memory.
*/
int dump_mii( struct S2DevQueryMIIParam *mii, LONG length, LONG verbose )
{
USHORT bmcr,bmsr,selfad,curlink;
LONG i;
bmcr = mii[MII_BMCR].Content;
bmsr = mii[MII_BMSR].Content;
selfad = mii[MII_ANAR].Content;
curlink = mii[MII_ANLPAR].Content;
if( bmcr == 0xffff )
{
Printf("No MII transceiver found\n");
return 0;
}
if( bmcr & MII_BMCR_AN_ENA)
{
if( bmsr & MII_BMSR_AN_COMPLETE)
{
if( selfad & curlink )
{
/* if( curlink & MII_AN_ACK ) */
Printf("negotiated ");
/* else Printf("no autonegotiation,"); */
dump_mii_media( selfad & curlink, 1 );
Printf(", ");
}
else
{
Printf("autonegotiation failed, ");
}
}
else
if (bmcr & MII_BMCR_RESTART)
{
Printf("autonegotiation restarted, ");
}
}
else
{
Printf("%s Mbit, %s duplex, ",
(bmcr & MII_BMCR_100MBIT) ? (ULONG)"100" : (ULONG)"10",
(bmcr & MII_BMCR_DUPLEX) ? (ULONG)"full" : (ULONG)"half" );
}
if( bmsr & MII_BMSR_LINK_VALID )
Printf("link ok");
else Printf("no link");
Printf("\n");
if( verbose > 1 )
{
Printf("PHY Registers:");
for( i=0 ; i < length/sizeof( struct S2DevQueryMIIParam ) ; i++ )
{
if(!(i%8))
Printf("\n");
if( mii[i].ID == S2_DEVQUERYEXT_MII_INVALID )
Printf("N/A ");
else
Printf("%04lx ",(LONG)(mii[i].Content));
}
Printf("\n");
}
if( verbose )
{
Printf(" vendor %02lx:%02lx:%02lx, model %ld rev %ld\n",
(LONG)mii[2].Content>>10,
(LONG)(mii[2].Content>>2)&0xff,
(LONG)((mii[2].Content<<6)|(mii[3].Content>>10))&0xff,
(LONG)(mii[3].Content>>4)&0x3f,
(LONG)(mii[3].Content&0x0f)
);
Printf(" basic mode: ");
if( bmcr & MII_BMCR_RESET )
Printf("software reset, ");
if( bmcr & MII_BMCR_LOOPBACK )
Printf("loopback, ");
if( bmcr & MII_BMCR_ISOLATE )
Printf("isolate, ");
if( bmcr & MII_BMCR_COLTEST )
Printf("collision test, ");
if( bmcr & MII_BMCR_AN_ENA )
Printf("autonegotiation enabled\n");
else
Printf("%s Mbit, %s duplex\n",
(bmcr & MII_BMCR_100MBIT) ? (ULONG)"100" : (ULONG)"10",
(bmcr & MII_BMCR_DUPLEX) ? (ULONG)"full" : (ULONG)"half");
Printf(" basic status: ");
if( bmsr & MII_BMSR_AN_COMPLETE )
Printf("autonegotiation complete, ");
else if( bmcr & MII_BMCR_RESTART )
Printf("autonegotiation restarted, ");
if( bmsr & MII_BMSR_REMOTE_FAULT )
Printf(" remote fault, ");
Printf( (bmsr & MII_BMSR_LINK_VALID) ? "link ok" : "no link");
Printf("\n capabilities:");
dump_mii_media( bmsr >> 6, 0 );
Printf("\n advertising: ");
dump_mii_media( selfad, 0 );
if( curlink & MII_AN_ABILITY_MASK )
{
Printf("\n link partner:");
dump_mii_media( curlink, 0 );
}
Printf("\n");
}
return 1;
}
/*
Query consecutive set of MII registers from start to end (inclusive)
*/
LONG query_mii( struct prgdata *prg, struct S2DevQueryMIIParam *mii, LONG start, LONG end )
{
struct S2DevQueryMIIParam *miitmp;
struct S2DevQueryExtParam parm_mii;
struct TagItem tags[2];
LONG i;
/* MII specific */
parm_mii.Data = (APTR)mii;
parm_mii.Length = (end-start+1)*sizeof(struct S2DevQueryMIIParam);
parm_mii.Actual = 0;
for( i=start,miitmp=mii ; i <= end ; i++,miitmp++ ) /* MII standard register set: 8 */
{
miitmp->ID = i;
}
tags[i=0].ti_Tag = S2_DevQueryExtGetMII;
tags[i++].ti_Data = (ULONG) &parm_mii;
tags[i ].ti_Tag = TAG_DONE;
prg->sana2devio->ios2_Req.io_Command = S2_DEVICEQUERYEXT;
prg->sana2devio->ios2_Data = tags;
prg->sana2devio->ios2_DataLength = sizeof(tags);
if( DoIO((struct IORequest *) prg->sana2devio ) != 0 )
return 0;
else
return parm_mii.Actual;
}
LONG write_mii( struct prgdata *prg, struct S2DevQueryMIIParam *mii, LONG num )
{
struct S2DevQueryExtParam parm_mii;
struct TagItem tags[2];
LONG i;
/* MII specific */
parm_mii.Data = (APTR)mii;
parm_mii.Length = (num)*sizeof(struct S2DevQueryMIIParam);
parm_mii.Actual = 0;
tags[i=0].ti_Tag = S2_DevQueryExtSetMII;
tags[i++].ti_Data = (ULONG) &parm_mii;
tags[i ].ti_Tag = TAG_DONE;
prg->sana2devio->ios2_Req.io_Command = S2_DEVICEQUERYEXT;
prg->sana2devio->ios2_Data = tags;
prg->sana2devio->ios2_DataLength = sizeof(tags);
if( DoIO((struct IORequest *) prg->sana2devio ) != 0 )
return 0;
else
return parm_mii.Actual;
}
#ifdef RSHOW
/* return string length without closing 0 */
LONG myStrLen( BYTE *str )
{
LONG ret = 0;
if( str )
{
while( *str++ )
ret++;
}
return ret;
}
/* copy string, append 0 */
void myStrNCpy( BYTE *dst, BYTE*src, LONG bytes )
{
if( !dst )
return;
if( src )
{
while( (bytes--) && (*src != 0) )
{
*dst++ = *src++;
}
}
*dst = 0;
}
/* find active interface and its device in RoadShow (optional) */
/* "which" index of Ethernet adapter 0,1,2,... */
/* "unit" is the output unit */
BYTE *find_active_interface(LONG which, LONG *unit )
{
struct Library *SocketBase;
BYTE *ret = NULL;
struct List * interface_list = NULL;
struct Node *n;
BYTE *dev = NULL;
LONG hw = -1;
SocketBase = OpenLibrary("bsdsocket.library",4);
if( !SocketBase )
{
Printf("Cannot open bsdsocket.library version 4 for device auto-detection\n");
return NULL;
}
do
{
LONG have_iface = 0;
if( !(SocketBaseTags(SBTM_GETREF(SBTC_HAVE_INTERFACE_API), &have_iface, TAG_DONE) == 0)
||(!have_iface) )
{
Printf("RoadShow-style interface API not available in IP stack\n");
break;
}
interface_list = ObtainInterfaceList();
if( !interface_list )
{
break;
}
for( n=interface_list->lh_Head ; n->ln_Succ != NULL ; n=n->ln_Succ )
{
/* Printf("Interface %s\n",n->ln_Name); */
/* find Ethernet interface */
if(!QueryInterfaceTags( n->ln_Name, IFQ_HardwareType, &hw,
IFQ_DeviceName, &dev,
IFQ_DeviceUnit, unit ) )
continue;
/* Printf("device %s hwtype %ld\n",dev,hw); */
if( hw == S2WireType_Ethernet )
break;
}
if( hw == S2WireType_Ethernet )
{
if( dev )
{
ret = AllocVec( myStrLen( dev ), 0 );
if( ret )
myStrNCpy( ret, dev, myStrLen(dev) );
}
}
}
while(0);
if( interface_list )
ReleaseInterfaceList(interface_list);
CloseLibrary(SocketBase);
return ret;
}
#endif
/* 8 basic registers, we poll 16 out of curiosity */
#define MII_REGNUM 16
/* two spare registers for write mode */
#define MII_SPARE 2
int main(int argc, char **argv)
{
struct prgdata _prg,*prg=&_prg;
int res = RETURN_FAIL;
char vendorname[128], productname[128];
struct S2DevQueryExtParam parm_productname;
struct S2DevQueryExtParam parm_vendorname;
struct S2DevQueryExtParam parm_mii;
struct S2DevQueryMIIParam mii[MII_REGNUM+MII_SPARE];
struct TagItem tags[3];
int i;
struct RDArgs *rdargs;
BYTE *name;
LONG unit,autoneg,force;
if( !start_prog(prg) )
return res;
if( !(rdargs = ReadArgs( (char*)opt_template,(LONG*)&prg->opts,NULL) ) )
{
Printf("Argument error\n");
end_prog(prg);
return res;
}
unit = (prg->opts.unit) ? *prg->opts.unit : 0;
if( !prg->opts.devname )
{
#ifdef RSHOW
LONG _unit;
prg->auto_devname = find_active_interface( 0, &_unit );
if( prg->auto_devname )
{
unit = _unit;
name = prg->auto_devname;
}
else
{
Printf("cannot auto-determine device, please use DEVICE=... as argument\n");
end_prog(prg);
return res;
}
#else
name = "enc624j6net.device";
Printf("device auto-detect not compiled in, now trying default %s\n",name);
#endif
/* end_prog(prg);
return res; */
}
else
name = prg->opts.devname;
if( prg->opts.vverbose )
prg->opts.verbose = 2;
else
if( prg->opts.verbose )
prg->opts.verbose = 1;
/* parameter check */
if( ( (prg->opts.force) && (prg->opts.renegotiate) ) ||
( (prg->opts.force) && (prg->opts.advertise) )
)
{
Printf("Error: Forced and Autonegotiation parameter mismatch\n");
end_prog(prg);
return RETURN_FAIL;
}
/* convert text to binary mask */
autoneg = parse_speedduplex( prg->opts.advertise );
force = parse_speedduplex( prg->opts.force );
if( (autoneg|force) < 0 )
{
end_prog(prg);
return RETURN_FAIL;
}
if( get_device( prg, name , unit ) )
{
if( probe_device( prg ) )
res = RETURN_OK;
}
if( res != RETURN_OK )
{
end_prog(prg);
return res;
}
/* device open, query extension present, now query it */
{
/* general information */
parm_vendorname.Data = vendorname;
parm_vendorname.Length = sizeof(vendorname);
parm_vendorname.Actual = 0;
parm_productname.Data = productname;
parm_productname.Length = sizeof(productname);
parm_productname.Actual = 0;
tags[i=0].ti_Tag = S2_DevQueryExtVendorName;
tags[i++].ti_Data = (ULONG) &parm_vendorname;
tags[i ].ti_Tag = S2_DevQueryExtProductName;
tags[i++].ti_Data = (ULONG) &parm_productname;
tags[i ].ti_Tag = TAG_DONE;
prg->sana2devio->ios2_Req.io_Command = S2_DEVICEQUERYEXT;
prg->sana2devio->ios2_Data = tags;
prg->sana2devio->ios2_DataLength = sizeof(tags);
DoIO( (struct IORequest *)prg->sana2devio );
/* separate query subroutine in here for MII, though not
absolutely necessary (MII is queried more than once) */
parm_mii.Actual = query_mii( prg, mii, 0, 15 );
if( parm_mii.Actual )
{
/* read BMSR a second time */
query_mii( prg, mii+MII_BMSR, MII_BMSR, MII_BMSR );
res = RETURN_OK;
}
else
{
Printf("Sana2DeviceQueryExtension for MII access not present\n");
res = RETURN_WARN;
}
}
/* out of curiosity: get MAC address */
prg->sana2devio->ios2_Req.io_Command = S2_GETSTATIONADDRESS;
prg->sana2devio->ios2_Data = (0);
prg->sana2devio->ios2_DataLength = 0;
DoIO( (struct IORequest *)prg->sana2devio );
Printf("Device: %s\n",(ULONG)name);
/* general info */
if( parm_vendorname.Actual != 0 )
{
vendorname[parm_vendorname.Actual-1] = 0;
Printf("Vendor: %s\n",(ULONG)vendorname);
}
if( parm_productname.Actual != 0 )
{
productname[parm_productname.Actual-1] = 0;
Printf("Product: %s\n",(ULONG)productname);
}
/* MAC address */
{
unsigned char*p = (unsigned char*)prg->sana2devio->ios2_SrcAddr;
Printf("MAC: %02lx:%02lx:%02lx:%02lx:%02lx:%02lx\n",
(ULONG)p[0],(ULONG)p[1],(ULONG)p[2],(ULONG)p[3],(ULONG)p[4],(ULONG)p[5] );
}
/* after query, see what we've got */
if( res == RETURN_OK )
{
/* MII data */
if( parm_mii.Actual == 0 )
{
Printf("Unable to query MII data.\n");
}
else
{
/* command or query ? */
if( !(prg->opts.renegotiate) && !(prg->opts.reset)
&& !(prg->opts.advertise) && !(prg->opts.force)
)
{
Printf("Active Parameters:\n");
dump_mii( mii, parm_mii.Actual, prg->opts.verbose );
}
}
if( prg->opts.reset )
{
Printf("resetting the transceiver...\n");
mii[MII_REGNUM].ID = MII_BMCR;
mii[MII_REGNUM].Content = MII_BMCR_RESET;
write_mii( prg, &mii[MII_REGNUM], 1 );
}
if( prg->opts.advertise )
{
mii[MII_REGNUM].ID = MII_ANAR;
mii[MII_REGNUM].Content = autoneg|1;
write_mii( prg, &mii[MII_REGNUM], 1 );
prg->opts.renegotiate = 1;
}
if( prg->opts.renegotiate )
{
Printf("restarting autonegotiation...\n");
mii[MII_REGNUM].ID = MII_BMCR;
mii[MII_REGNUM].Content = 0x0000;
write_mii( prg, &mii[MII_REGNUM], 1 );
mii[MII_REGNUM].ID = MII_BMCR;
mii[MII_REGNUM].Content = MII_BMCR_AN_ENA|MII_BMCR_RESTART;
write_mii( prg, &mii[MII_REGNUM], 1 );
}
if( prg->opts.force )
{
UWORD bmcr = 0;
if( force & (MII_AN_100BASETX_FD|MII_AN_100BASETX_HD))
bmcr |= MII_BMCR_100MBIT;
if( force & (MII_AN_100BASETX_FD|MII_AN_10BASET_FD))
bmcr |= MII_BMCR_DUPLEX;
mii[MII_REGNUM].ID = MII_BMCR;
mii[MII_REGNUM].Content = bmcr;
write_mii( prg, &mii[MII_REGNUM], 1 );
}
}
end_prog(prg);
return res;
}
Driver/baxnet/source/miitool.h
-70
View File
@@ -1,70 +0,0 @@
/*******************************************************************************************/
/** **/
/** miitool.h **/
/** definitions for PHY registers **/
/** **/
/** Copyright (C) 2000 David A. Hinds -- dhinds@pcmcia.sourceforge.org **/
/** **/
/** origin: mii.h in net-tools-1.60 **/
/** **/
/*******************************************************************************************/
#ifndef _INC_MIITOOL_H
#define _INC_MIITOOL_H
/* Basic Mode Control Register */
#define MII_BMCR 0x00
#define MII_BMCR_RESET 0x8000
#define MII_BMCR_LOOPBACK 0x4000
#define MII_BMCR_100MBIT 0x2000
#define MII_BMCR_AN_ENA 0x1000
#define MII_BMCR_ISOLATE 0x0400
#define MII_BMCR_RESTART 0x0200
#define MII_BMCR_DUPLEX 0x0100
#define MII_BMCR_COLTEST 0x0080
/* Basic Mode Status Register */
#define MII_BMSR 0x01
#define MII_BMSR_CAP_MASK 0xf800
#define MII_BMSR_100BASET4 0x8000
#define MII_BMSR_100BASETX_FD 0x4000
#define MII_BMSR_100BASETX_HD 0x2000
#define MII_BMSR_10BASET_FD 0x1000
#define MII_BMSR_10BASET_HD 0x0800
#define MII_BMSR_NO_PREAMBLE 0x0040
#define MII_BMSR_AN_COMPLETE 0x0020
#define MII_BMSR_REMOTE_FAULT 0x0010
#define MII_BMSR_AN_ABLE 0x0008
#define MII_BMSR_LINK_VALID 0x0004
#define MII_BMSR_JABBER 0x0002
#define MII_BMSR_EXT_CAP 0x0001
#define MII_PHY_ID1 0x02
#define MII_PHY_ID2 0x03
/* Auto-Negotiation Advertisement Register */
#define MII_ANAR 0x04
/* Auto-Negotiation Link Partner Ability Register */
#define MII_ANLPAR 0x05
#define MII_AN_NEXT_PAGE 0x8000
#define MII_AN_ACK 0x4000
#define MII_AN_REMOTE_FAULT 0x2000
#define MII_AN_ABILITY_MASK 0x07e0
#define MII_AN_FLOW_CONTROL 0x0400
#define MII_AN_100BASET4 0x0200
#define MII_AN_100BASETX_FD 0x0100
#define MII_AN_100BASETX_HD 0x0080
#define MII_AN_10BASET_FD 0x0040
#define MII_AN_10BASET_HD 0x0020
#define MII_AN_PROT_MASK 0x001f
#define MII_AN_PROT_802_3 0x0001
/* Auto-Negotiation Expansion Register */
#define MII_ANER 0x06
#define MII_ANER_MULT_FAULT 0x0010
#define MII_ANER_LP_NP_ABLE 0x0008
#define MII_ANER_NP_ABLE 0x0004
#define MII_ANER_PAGE_RX 0x0002
#define MII_ANER_LP_AN_ABLE 0x0001
#endif /* _INC_MIITOOL_H */
Driver/baxnet/source/mmustuff.c
-109
View File
@@ -1,109 +0,0 @@
/*
set up MMU for flash access using mmu.library
(C) 2022 Henryk Richter
The F0 area (0xF00000-0xF7ffff) is known to be
reserved by Commodore for diagnostic ROMs (or
BootROMs), as well as additional kickstart modules.
Some configurations of the MMU will mark this
area as ROM such that write attempts are inhibited
by the processor itself.
This code will revert any existing remapping (to
RAM) and set up useable cache flags such that the
Flash can be written to.
*/
#define __NOLIBBASE__
#include <proto/mmu.h>
#include <mmu/context.h>
#include <mmu/mmutags.h>
#include "debug.h"
#include "mmustuff.h"
//extern struct Library *MMUBase;
//extern struct DosLibrary *DOSBase;
#define CACHEFLAGS (MAPP_CACHEINHIBIT|MAPP_COPYBACK|MAPP_NONSERIALIZED|MAPP_IMPRECISE)
#define ROMFLAGS (MAPP_CACHEINHIBIT|MAPP_GLOBAL|MAPP_IO|MAPP_USER0)
#define ROMCFLAGS (MAPP_CACHEINHIBIT|MAPP_COPYBACK|MAPP_NONSERIALIZED|MAPP_IMPRECISE|MAPP_GLOBAL|MAPP_IO|MAPP_WRITEPROTECTED|MAPP_ROM|MAPP_INVALID)
#ifdef __VBCC__
#define BCAST
#else
#define BCAST (ULONG)
#endif
/*
set up MMU as I/O space from "base", "size" bytes,
keep flags==0 for now
the device pointer is used to fetch the MMUbase from it, nothing more
*/
ASM SAVEDS LONG setupMMU( ASMR(a0) void *base ASMREG(a0),
ASMR(d0) LONG size ASMREG(d0),
ASMR(d1) ULONG flags ASMREG(d1),
ASMR(a6) DEVBASEP ASMREG(a6) )
{
struct MMUContext *ctx,*sctx; /* default context, supervisor context */
ULONG props;
struct MinList *ctxl,*sctxl;
struct TagItem tgs[2] = {{TAG_DONE,0},{TAG_DONE,0} };
if( !MMUBase )
return 1; /* cannot setup MMU without MMULib */
ctx=DefaultContext();
sctx=SuperContext(ctx);
props = GetPropertiesA(sctx,BCAST base,tgs);
props |= GetPropertiesA(sctx,BCAST base,tgs);
D(( (STRPTR)"Current MMU props on 0x%lx area: 0x%lx\n",(ULONG)base,props));
LockContextList();
LockMMUContext(ctx);
LockMMUContext(sctx);
if( (props & MAPP_REMAPPED) )
{
D(( (STRPTR)"Memory was remapped elsewhere, reverting to physical location\n" ));
if( (ctxl=GetMapping(ctx)))
{
if( (sctxl=GetMapping(sctx)))
{
if( SetPropertiesA(ctx,0,MAPP_REMAPPED|CACHEFLAGS,BCAST base,size,tgs) )
{
if( SetPropertiesA(sctx,0,MAPP_REMAPPED|CACHEFLAGS,BCAST base,size,tgs) )
{
}
}
ReleaseMapping(sctx,sctxl);
}
ReleaseMapping(ctx,ctxl);
}
}
/* set desired flags */
SetPropertiesA(ctx,ROMFLAGS,ROMCFLAGS, BCAST base,size,tgs);
SetPropertiesA(sctx,ROMFLAGS,ROMCFLAGS,BCAST base,size,tgs);
RebuildTrees(ctx,sctx,NULL);
UnlockMMUContext(sctx);
UnlockMMUContext(ctx);
UnlockContextList();
props = GetPropertiesA(sctx,BCAST base,tgs);
props |= GetPropertiesA(sctx,BCAST base,tgs);
D(( (STRPTR)"New MMU props on 0x%lx area: 0x%lx\n",(ULONG)base,props));
return 0;
}
Driver/baxnet/source/mmustuff.h
-30
View File
@@ -1,30 +0,0 @@
/*
set up MMU for flash access using mmu.library
(C) 2022 Henryk Richter
The F0 area (0xF00000-0xF7ffff) is known to be
reserved by Commodore for diagnostic ROMs (or
BootROMs), as well as additional kickstart modules.
Some configurations of the MMU will mark this
area as ROM such that write attempts are inhibited
by the processor itself.
This code will revert any existing remapping (to
RAM) and set up useable cache flags such that the
Flash can be written to.
*/
#ifndef _INC_MMUSTUFF_H
#define _INC_MMUSTUFF_H
#include "compiler.h"
#include "device.h"
ASM SAVEDS LONG setupMMU( ASMR(a0) void *base ASMREG(a0),
ASMR(d0) LONG size ASMREG(d0),
ASMR(d1) ULONG flags ASMREG(d1),
ASMR(a6) DEVBASEP ASMREG(a6) );
#endif
Driver/baxnet/source/newstyle.h
-86
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@@ -1,86 +0,0 @@
#ifndef DEVICES_NEWSTYLE_H
#define DEVICES_NEWSTYLE_H
/*------------------------------------------------------------------------*/
/*
* $Id: newstyle.h 1.1 1997/05/15 18:53:15 heinz Exp $
*
* Support header for the New Style Device standard
*
* (C)1996-1997 by Amiga International, Inc.
*
*/
/*------------------------------------------------------------------------*/
/*
* At the moment there is just a single new style general command:
*/
#define NSCMD_DEVICEQUERY 0x4000
struct NSDeviceQueryResult {
/*
** Standard information, must be reset for every query
*/
ULONG DevQueryFormat; /* this is type 0 */
ULONG SizeAvailable; /* bytes available */
/*
** Common information (READ ONLY!)
*/
UWORD DeviceType; /* what the device does */
UWORD DeviceSubType; /* depends on the main type */
UWORD *SupportedCommands; /* 0 terminated list of cmd's */
/* May be extended in the future! Check SizeAvailable! */
};
#define NSDEVTYPE_UNKNOWN 0 /* No suitable category, anything */
#define NSDEVTYPE_GAMEPORT 1 /* like gameport.device */
#define NSDEVTYPE_TIMER 2 /* like timer.device */
#define NSDEVTYPE_KEYBOARD 3 /* like keyboard.device */
#define NSDEVTYPE_INPUT 4 /* like input.device */
#define NSDEVTYPE_TRACKDISK 5 /* like trackdisk.device */
#define NSDEVTYPE_CONSOLE 6 /* like console.device */
#define NSDEVTYPE_SANA2 7 /* A >=SANA2R2 networking device */
#define NSDEVTYPE_AUDIO 8 /* like audio.device */
#define NSDEVTYPE_CLIPBOARD 9 /* like clipboard.device */
#define NSDEVTYPE_PRINTER 10 /* like printer.device */
#define NSDEVTYPE_SERIAL 11 /* like serial.device */
#define NSDEVTYPE_PARALLEL 12 /* like parallel.device */
/*------------------------------------------------------------------------*/
/* The following defines should really be part of device specific
* includes. So we protect them from being redefined.
*/
#ifndef NSCMD_TD_READ64
/*
* An early new style trackdisk like device can also return this
* new identifier for TD_GETDRIVETYPE. This should no longer
* be the case though for newly written or updated NSD devices.
* This identifier is ***OBSOLETE***
*/
#define DRIVE_NEWSTYLE (0x4E535459L) /* 'NSTY' */
/*
* At the moment, only four new style commands in the device
* specific range and their ETD counterparts may be implemented.
*/
#define NSCMD_TD_READ64 0xC000
#define NSCMD_TD_WRITE64 0xC001
#define NSCMD_TD_SEEK64 0xC002
#define NSCMD_TD_FORMAT64 0xC003
#define NSCMD_ETD_READ64 0xE000
#define NSCMD_ETD_WRITE64 0xE001
#define NSCMD_ETD_SEEK64 0xE002
#define NSCMD_ETD_FORMAT64 0xE003
#endif /* NSCMD_TD_READ64 */
/*------------------------------------------------------------------------*/
#endif /* DEVICES_NEWSTYLE_H */
Driver/baxnet/source/sana2devqueryext.h
-125
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@@ -1,125 +0,0 @@
#ifndef SANA2_SANA2DEVQUERYEXT_H
#define SANA2_SANA2DEVQUERYEXT_H
/*
** $VER: sana2devqueryext.h 0.12 (10-Jun-2018)
** Definitions for SANA-II extended device query
** (c) 2018, Timm S. Mueller and Olaf Barthel
**
** Permission is hereby granted, free of charge, to any person obtaining
** a copy of this file, without limitation the rights to copy, publish,
** and distribute this file in unmodified form, and to use it for the
** creation of software.
** We strongly advise you not to release software into the public based on
** modifications or extensions of the definitions below, without seeking
** prior agreement with the authors regarding your changes.
**
** Application protocol:
** 1. Using NSCMD_DEVICEQUERY, check for availability of S2_DEVICEQUERYEXT.
** 2. For each attribute provide a struct S2DevQueryExtParam. Fill in a
** pointer to your data, its length, and initialize Actual to 0.
** 3. For each attribute requested, supply a tagitem with a pointer to the
** respective S2DevQueryExtParam structure as its value. Pass the taglist
** in ios2_Data. After return from the device and no I/O error,
** 4. check for the expected data size using param.Actual == sizeof(value).
** Check for the presence of any returned data using param.Actual != 0.
** The length of strings include a terminating zero byte, so param.Actual
** for a string of length 0 would be 1.
** 5. To only retrieve the number of bytes that would be written, set
** param.Data to NULL.
** 6. Unless otherwise noted, numerical values are of type ULONG by default.
**
** Driver protocol:
** 1. Support S2_DEVICEQUERYEXT per NSCMD_DEVICEQUERY.
** 2. Iterate supplied tags in ios2_Data. For each tag,
** 3. if param->Data is NULL, write the length that would be written
** into param->Actual. In the case of strings, always include the
** terminating zero byte in this length.
** 4. If param->Data is not NULL, check for
** param->Length >= sizeof(your_data). Copy your data into the
** buffer provided by param->Data. Under no circumstance may the length
** being written exceed param->Length. Write the length actually being
** written into param->Actual. At your discretion, shorten informative,
** non-indexing strings to fit into the user-supplied buffer -- but you
** are not allowed to write strings without a terminating zero byte,
** which must fit into the buffer as indicated by param->Length.
*/
#include <devices/sana2.h>
struct S2DevQueryExtParam
{
APTR Data; /* Ptr to data buffer you provide */
LONG Length; /* Length of data buffer you provide */
LONG Actual; /* Number of bytes actually written */
};
#define S2_DEVICEQUERYEXT (S2_START + 0x100)
#define S2_DevQueryExtTagBase (S2_Dummy + 0x100)
/* ptr to string containing the vendor name: */
#define S2_DevQueryExtVendorName (S2_DevQueryExtTagBase + 1)
/* ptr to string containing the product name: */
#define S2_DevQueryExtProductName (S2_DevQueryExtTagBase + 2)
/* Current physical link status, see definitions below: */
#define S2_DevQueryExtLinkStatus (S2_DevQueryExtTagBase + 3)
/* Current physical link speed, see definitions below: */
#define S2_DevQueryExtLinkSpeed (S2_DevQueryExtTagBase + 4)
/* proposal added by Henryk Richter: access to MII */
/* MII is the standardized ethernet interface to the
PHY registers. It allows to read and modify autonegotiation
settings and status, as well as manual reconfiguration of
link parameters. In order to ease the burden on the
SANA-II driver, this interface is transparent in the sense
that no processing of MII registers is necessary.
Please note that MII read/write is slow. Use with discretion.
The format of the Data APTR is per entry as follows:
UWORD ID
UWORD Content
S2_DevQueryExtGetMII
Please pass a writable Data array of Length=2*NumIDs to the call and
initialize the IDs you are interested in. The driver will initialize
the Content of the IDs it knows about. Should a requested ID be
unsupported by the driver or underlying chipset, the driver will
overwrite the respective IDs with S2_DEVQUERYEXT_MII_INVALID and
clear the associated Content field.
In case of fatal error, the "Actual" field of S2DevQueryExtParam
will be 0. Otherwise, the last successfully updated location + 2
will be returned.
S2_DevQueryExtSetMII
Please pass a Data array of Length=2*NumIDs to the call and initialize
the IDs to write along with their content. The driver will write the
MII registers corresponding with the IDs in the given order.
In case of fatal error, the "Actual" field of S2DevQueryExtParam
will be 0. Otherwise, the last successfully updated location + 2
will be returned.
*/
#define S2_DevQueryExtGetMII (S2_DevQueryExtTagBase + 0x20)
#define S2_DevQueryExtSetMII (S2_DevQueryExtTagBase + 0x21)
struct S2DevQueryMIIParam
{
UWORD ID;
UWORD Content;
};
#define S2_DEVQUERYEXT_MII_INVALID 0xfe
#define S2_DEVQUERYEXT_LINK_UNDEFINED 0xffffffff
#define S2_DEVQUERYEXT_LINK_DOWN 0
#define S2_DEVQUERYEXT_LINK_UP 1
#define S2_DEVQUERYEXT_SPEED_UNDEFINED 0xffffffff
#define S2_DEVQUERYEXT_SPEED_OTHER 0
#define S2_DEVQUERYEXT_SPEED_10M 1
#define S2_DEVQUERYEXT_SPEED_100M 2
#define S2_DEVQUERYEXT_SPEED_1000M 3
#define S2_DEVQUERYEXT_SPEED_10000M 4
#endif
Driver/baxnet/source/sdnet/enc28j60.c
-778
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@@ -1,778 +0,0 @@
/*
Microchip ENC28J60 Ethernet Interface Driver
Author: Henryk Richter
Copyright: GPL V2
Notes: when I ran into timing issues in early development, I moved over to quickly
testable ASM code for SPI communication. I didn't bother porting that stuff
back into C code. So this file now references enc28j60l.asm for lowlevel direct
hardware access.
As a consequence, the only functions needed from spi.c are the spi_init() and
spi_disable_eth().
TODO: - support for power down when unused, i.e. offline
- replace busy waiting loop after reset
Based on work by
Christian Vogelgsaang
Guido Socher
Pascal Stang (see enc28j60.c in AVRlib library for the original file)
*/
#undef _DO_DUMP
/* used for Delay() */
#include <dos/dos.h>
#include <proto/dos.h>
#ifdef _DO_DUMP
#include <stdio.h>
#endif
#include "compiler.h"
#include "enc28j60.h"
#include "enc28j60l.h" /* import lowlevel asm functions */
/* #include "spi.h" */ /* no direct use anymore, just for init purposes) */
#include "device.h"
/*
The RXSTART_INIT must be zero. See Rev. B4 Silicon Errata point 5.
Buffer boundaries applied to internal 8K ram
the entire available packet buffer space is allocated
rx packet layout
6 byte heaader
1518
sum: 1524
*/
#define RXSTART_INIT 0x0000 /* start of RX buffer, room for 4 packets */
#define RXSTOP_INIT 0x19FF /* end of RX buffer */
#define TXSTART_INIT 0x1A00 /* start of TX buffer, room for 1 packet */
#define TXSTOP_INIT 0x1FFF /* end of TX buffer */
/* max frame length which the conroller will accept: */
/* (note: maximum ethernet frame length would be 1518 when VLAN tagging is unused) */
#define MAX_FRAMELEN 1518
/* perform sanity checks if more this amount of "idle" calls to have_recv()
are noted (idle=nothing received)
*/
#define SANITY_CHECK_INTERVAL 32
static u16 gNextPacketPtr;
static u08 is_full_duplex;
static u08 rev;
struct enc28j60_initvars {
u16 have_recv;
u08 last_mac[6];
u08 macon1;
u08 macon2;
u08 macon3;
u08 macon4;
};
static struct enc28j60_initvars initvars;
static void enc28j60_recv_reset( struct enc28j60_initvars *iv, u08 restart );
static int enc28j60_check_config( struct enc28j60_initvars *iv );
static uint8_t readOp (uint8_t op, uint8_t address)
{
return enc28j60l_ReadOp( op, address );
}
static void writeOp (uint8_t op, uint8_t address, uint8_t data)
{
enc28j60l_WriteOp( op, address,data );
}
static void readBuf(uint16_t len, uint8_t* data)
{
enc28j60l_ReadBuffer( data, (unsigned int)len );
}
void SetBank (uint8_t address)
{
enc28j60l_SetBank(address);
}
static uint8_t readRegByte (uint8_t address)
{
return enc28j60l_ReadRegByte( address );
}
#if 0
static uint16_t readReg(uint8_t address) {
return readRegByte(address) + (readRegByte(address+1) << 8);
}
#endif
static void writeRegByte (uint8_t address, uint8_t data)
{
enc28j60l_WriteRegByte( address, data );
}
static void writeReg(uint8_t address, uint16_t data)
{
enc28j60l_WriteReg( address, data );
}
/*
the PHY registers require special care
*/
static uint16_t readPhyByte (uint8_t address)
{
long wtime = 0xffff;
writeRegByte(MIREGADR, address);
writeRegByte(MICMD, MICMD_MIIRD);
while (readRegByte(MISTAT) & MISTAT_BUSY)
{
if( (--wtime) <= 0 )
{
writeRegByte(MICMD, 0x00);
initvars.have_recv = SANITY_CHECK_INTERVAL+1;
return 0xffff;
}
}
writeRegByte(MICMD, 0x00);
return readRegByte(MIRD+1);
}
static void writePhy (uint8_t address, uint16_t data)
{
long wtime = 0xffff;
writeRegByte(MIREGADR, address);
writeReg(MIWR, data);
while (readRegByte(MISTAT) & MISTAT_BUSY)
{
if( (--wtime) <= 0 )
{
initvars.have_recv = SANITY_CHECK_INTERVAL+1;
break;
}
}
}
/* just a pass-through to the lowlevel routines */
void enc28j60_SetSPISpeed( unsigned long clock_divider )
{
enc28j60l_SetSPISpeed( clock_divider );
}
/* ---------- init ---------- */
/* Functions to enable/disable broadcast filter bits */
/* With the bit set, broadcast packets are filtered. */
void enc28j60_broadcast_multicast_filter( u08 flags )
{
u08 val = ERXFCON_UCEN|ERXFCON_CRCEN; /* default: crc check and unicast */
if( flags & PIO_INIT_PROMISC )
{
val = 0;
}
else
{
if( flags & PIO_INIT_BROAD_CAST )
val |= ERXFCON_BCEN;
if( flags & PIO_INIT_MULTI_CAST )
val |= ERXFCON_MCEN;
}
writeRegByte(ERXFCON, val );
}
static void enc28j60_recv_reset( struct enc28j60_initvars *iv, u08 restart )
{
writeOp(ENC28J60_BIT_FIELD_CLR, ECON1, ECON1_RXEN);
writeOp(ENC28J60_BIT_FIELD_SET, ECON1, ECON1_RXRST);
writeOp(ENC28J60_BIT_FIELD_CLR, ECON1, ECON1_RXRST);
writeOp(ENC28J60_BIT_FIELD_CLR, ESTAT, ESTAT_TXABRT);
gNextPacketPtr = RXSTART_INIT;
writeReg(ERXST, RXSTART_INIT);
writeReg(ERXRDPT, RXSTOP_INIT );
writeReg(ERXND, RXSTOP_INIT);
writeOp(ENC28J60_BIT_FIELD_CLR, EIR, EIR_TXERIF|EIR_RXERIF );
writeReg(MAMXFL, MAX_FRAMELEN);
writeRegByte(MACON4, iv->macon4 ); /* DEFER bit */
writeRegByte(MACON3, iv->macon3 );
writeRegByte(MACON2, iv->macon2 );
writeRegByte(MACON1, iv->macon1 );
enc28j60_setMAC( iv->last_mac );
writePhy(PHIE, PHIE_PGEIE|PHIE_LNKIE );
writePhy(PHLCON, 0x3c12 ); /* 3(fixed) C(LinkStat+RX Act) 1(TX Act) 2(Stretch enable) */
/* prepare flow control */
writeReg(EPAUS, 20 * 100); /* 100ms */
if( restart )
writeOp(ENC28J60_BIT_FIELD_SET, ECON1, ECON1_RXEN);
iv->have_recv = 0;
}
static int enc28j60_check_config( struct enc28j60_initvars *iv )
{
int ret = 1; /* def: be optimistic */
/* check RX registers */
if( !(readOp(ENC28J60_READ_CTRL_REG, ECON1) & ECON1_RXEN ) )
ret = 0;
if( (readRegByte(MACON1)&iv->macon1) != iv->macon1 )
ret = 0;
if( (readRegByte(MACON2)&iv->macon2) != iv->macon2 )
ret = 0;
if( (readRegByte(MACON3)&iv->macon3) != iv->macon3 )
ret = 0;
/* check TX problems */
if( readRegByte(ESTAT) & ESTAT_TXABRT )
ret = 0;
if( readRegByte(EIR) & EIR_TXERIF )
ret = 0;
/* Verify MAC */
if( readRegByte(MAADR5) != iv->last_mac[0] )
ret = 0;
if( readRegByte(MAADR4) != iv->last_mac[1] )
ret = 0;
if( readRegByte(MAADR3) != iv->last_mac[2] )
ret = 0;
if( readRegByte(MAADR2) != iv->last_mac[3] )
ret = 0;
if( readRegByte(MAADR1) != iv->last_mac[4] )
ret = 0;
if( readRegByte(MAADR0) != iv->last_mac[5] )
ret = 0;
return ret;
}
u08 enc28j60_init(const u08 macaddr[6], u08 flags)
{
unsigned int count;
u08 mac3val;
struct enc28j60_initvars *iv = &initvars;
enc28j60l_Init(); /* spi_init(); spi_disable_eth(); */
{
int i;
for(i=0 ; i < 6 ; i++ )
iv->last_mac[i] = macaddr[i];
}
is_full_duplex = (flags & PIO_INIT_FULL_DUPLEX) == PIO_INIT_FULL_DUPLEX;
/* soft reset cpu */
writeOp(ENC28J60_SOFT_RESET, 0, ENC28J60_SOFT_RESET);
#if 1
enc28j60l_UMinDelay( 2000 ); /* wait 2 ms */
#else
/* Delay(1);*/ /* _delay_ms(2); // errata B7/2 */
/* hard-coded delay right now (TODO: import timer functions) */
for( count = 0 ; count < 20000 ; count++ )
{
mac3val |= (u08)*((volatile unsigned short*)(0x00DE0004));
}
#endif
/* wait or error */
count = 0;
while (!readOp(ENC28J60_READ_CTRL_REG, ESTAT) & ESTAT_CLKRDY) {
count ++;
if(count == 0xfff) {
return PIO_NOT_FOUND;
}
}
writeOp(ENC28J60_WRITE_CTRL_REG, ECON1, 0);
/* return rev */
rev = readRegByte(EREVID);
/* microchip forgot to step the number on the silcon when they */
/* released the revision B7. 6 is now rev B7. We still have */
/* to see what they do when they release B8. At the moment */
/* there is no B8 out yet */
if ( (rev < 1) || (rev > 10) ) /* I don't expect a rev > 10 (+1), so I use it to check for module presence */
return PIO_NOT_FOUND; /* important: check this before any writePhy -> no module gets us 0xff back */
if (rev > 5) ++rev;
writeReg(ETXST, TXSTART_INIT);
writeReg(ETXND, TXSTOP_INIT);
/* set packet filter */
enc28j60_broadcast_multicast_filter( flags );/* flags & (PIO_INIT_BROAD_CAST|PIO_INIT_MULTI_CAST) ); */
/* BIST pattern generator? */
writeReg(EPMM0, 0x303f);
writeReg(EPMCS, 0xf7f9);
if(is_full_duplex) {
writeRegByte(MABBIPG, 0x15);
writeReg(MAIPG, 0x0012);
} else {
writeRegByte(MABBIPG, 0x12);
writeReg(MAIPG, 0x0C12);
}
/* MAC init (with flow control) */
mac3val = MACON3_PADCFG0|MACON3_TXCRCEN|MACON3_FRMLNEN;
if(is_full_duplex) {
mac3val |= MACON3_FULDPX;
iv->macon4=0;
}
else
{
iv->macon4 = 1<<6; /* DEFER bit */
}
iv->macon3 = mac3val;
iv->macon2 = 0x00;
iv->macon1 = MACON1_MARXEN|MACON1_TXPAUS|MACON1_RXPAUS;
/* set packet pointers */
enc28j60_recv_reset( iv, 0 );
/* PHY init */
if(is_full_duplex) {
writePhy(PHCON1, PHCON1_PDPXMD);
writePhy(PHCON2, 0);
} else {
writePhy(PHCON1, 0);
writePhy(PHCON2, PHCON2_HDLDIS);
}
writePhy(PHLCON, 0x3c12 ); /* 3(fixed) C(LinkStat+RX Act) 1(TX Act) 2(Stretch enable) */
SetBank(EIR);
writeOp(ENC28J60_BIT_FIELD_CLR, EIR, EIR_DMAIF|EIR_LINKIF|EIR_TXIF|EIR_TXERIF|EIR_RXERIF|EIR_PKTIF);
writeOp(ENC28J60_BIT_FIELD_SET, EIE, EIE_INTIE|EIE_PKTIE); /* |EIE_LINKIE|EIE_TXIE|EIE_TXERIE|EIE_RXERIE); */
writeOp(ENC28J60_BIT_FIELD_SET, ECON1, ECON1_RXEN);
/* wait a while for "LINK UP" -> break after 200 ms */
{
unsigned char status;
int runs = 100;
while( runs-- )
{
enc28j60_status( PIO_STATUS_LINK_UP, &status );
if( status )
break;
enc28j60l_UMinDelay( 2000 ); /* wait 2+ ms */
}
}
return PIO_OK;
}
/* ---------- exit ---------- */
void enc28j60_exit(void)
{
enc28j60_setOffline();
enc28j60l_Shutdown();
}
u08 enc28j60_setOnline( void )
{
SetBank(EIR);
writeOp(ENC28J60_BIT_FIELD_SET, ECON1, ECON1_RXEN);
return 1;
}
u08 enc28j60_setOffline( void )
{
SetBank(EIR);
writeOp(ENC28J60_BIT_FIELD_CLR, ECON1, ECON1_RXEN);
return 1;
}
void enc28j60_setMAC( const u08 macaddr[6] )
{
/* set mac */
writeRegByte(MAADR5, macaddr[0]);
writeRegByte(MAADR4, macaddr[1]);
writeRegByte(MAADR3, macaddr[2]);
writeRegByte(MAADR2, macaddr[3]);
writeRegByte(MAADR1, macaddr[4]);
writeRegByte(MAADR0, macaddr[5]);
SetBank(EIR);
}
void enc28j60_getMAC( u08 macaddr[6] ) /* mainly for debug */
{
/* set mac */
macaddr[0] = readRegByte(MAADR5);
macaddr[1] = readRegByte(MAADR4);
macaddr[2] = readRegByte(MAADR3);
macaddr[3] = readRegByte(MAADR2);
macaddr[4] = readRegByte(MAADR1);
macaddr[5] = readRegByte(MAADR0);
}
/* ---------- control ---------- */
u08 enc28j60_control(u08 control_id, u08 value)
{
switch(control_id) {
case PIO_CONTROL_FLOW:
{
u08 flag;
if(is_full_duplex) {
flag = value ? 2 : 3;
} else {
flag = value ? 1 : 0;
}
writeRegByte(EFLOCON, flag);
return PIO_OK;
}
default:
return PIO_NOT_FOUND;
}
}
/* ---------- status ---------- */
u08 enc28j60_status(u08 status_id, u08 *value)
{
switch(status_id) {
case PIO_STATUS_VERSION:
*value = rev;
return PIO_OK;
case PIO_STATUS_LINK_UP:
*value = (readPhyByte(PHSTAT2) >> 2) & 1;
return PIO_OK;
case PIO_STATUS_FULLDPX:
*value = (readRegByte(MACON3) & MACON3_FULDPX) ? 1 : 0;/* + (((u16)readRegByte(MACON1+3))<<8); */
return PIO_OK;
default:
*value = 0;
return PIO_NOT_FOUND;
}
}
/* ---------- send ---------- */
u08 enc28j60_send(const u08 *data, u16 size)
{
/* wait for tx ready */
/* We can't do it here like on ATMEL MCUs, simply because
the Vampire SPI is way faster than 10 MBit/s so that
we would overwrite a frame still being sent out
-> wait first, then fill buffer
*/
long maxwait = 0x1ffff; /* wait patiently */
while (readOp(ENC28J60_READ_CTRL_REG, ECON1) & ECON1_TXRTS)
{
/* errata sheet issue 12 -> TXRTS never becomes 0 */
/* ignores errata issue 13 -> frame loss due to late collision */
/* eworks around errata sheet issue 15 -> ESTAT.LATECOL not set */
if (readRegByte(EIR) & EIR_TXERIF) {
writeOp(ENC28J60_BIT_FIELD_SET, ECON1, ECON1_TXRST);
writeOp(ENC28J60_BIT_FIELD_CLR, ECON1, ECON1_TXRST);
}
if( !(--maxwait) )
return PIO_OK; /* waited long enough: drop frame */
}
/* write buffer */
#if 0
if(0)
{ u08* d = (u08*)data;
d[size]=0;
size=(size+1)&0xfffe;
}
#endif
enc28j60l_WriteBuffer( (u08*)data, size, TXSTART_INIT );
/* initiate send */
writeReg(ETXND, TXSTART_INIT+size);
writeOp(ENC28J60_BIT_FIELD_SET, ECON1, ECON1_TXRTS);
return PIO_OK;
}
/* ---------- recv ---------- */
/*
unrecoverable error in receiving, bad pointer or other causes
- reset the complete receive logic in order to start receiving anew
input: restart - 0 = don't re-enable RX automatically
1 = re-enable RX after resetting
*/
INLINE void next_pkt(void)
{
if (gNextPacketPtr - 1 > RXSTOP_INIT)
{
#if 1
enc28j60_recv_reset( &initvars, 1 );
#else
writeReg(ERXRDPT, RXSTOP_INIT);
gNextPacketPtr = 0;
#endif
}
else
writeReg(ERXRDPT, gNextPacketPtr - 1);
writeOp(ENC28J60_BIT_FIELD_SET, ECON2, ECON2_PKTDEC);
}
/* endian agnostic version of header read */
static u08 read_hdr(u16 *got_size)
{
struct {
uint8_t nextPacketL;
uint8_t nextPacketH;
uint8_t byteCountL;
uint8_t byteCountH;
uint8_t statusL;
uint8_t statusH;
} header;
readBuf(sizeof header, (uint8_t*) &header);
gNextPacketPtr = (u16)header.nextPacketL + (((u16)header.nextPacketH)<<8);
*got_size = (u16)header.byteCountL + (((u16)header.byteCountH)<<8); /* - 4;*//* -4: remove the CRC count */
return header.statusL;
}
u08 enc28j60_recv(u08 *data, u16 max_size, u16 *got_size)
{
u08 status,result;
u16 len;
/* EIR->PKTIF would be faster but errata sheet says "unreliable" */
u08 pcnt = 1+readRegByte(EPKTCNT); /* wraps to 0 for 0xff = unconnected module */
if( pcnt < 2 ) /* 0xff+1=0x00, 0x00+1=0x01, 0x01+1=0x02 */
return PIO_NOT_FOUND;
writeReg(ERDPT, gNextPacketPtr);
/* read chip's packet header */
status = read_hdr(got_size);
/* was a receive error? */
if ((status & 0x80)==0)
{
/* TODO: recv reset ? */
next_pkt();
return PIO_IO_ERR;
}
/* check size */
len = *got_size;
result = PIO_OK;
if(len > max_size) {
len = max_size;
result = PIO_TOO_LARGE;
}
/* read packet */
readBuf(len, data);
#if 0
{
data[len]=0;
data[len+1]=0;
data[len+2]=0;
data[len+3]=0;
}
#endif
next_pkt();
return result;
}
/* ---------- has_recv ---------- */
u08 enc28j60_has_recv(void)
{
u08 ret = readRegByte(EPKTCNT);
if( !ret )
{
initvars.have_recv++;
if( initvars.have_recv > SANITY_CHECK_INTERVAL )
{
/* check for bad config vars and reset hw if that is the case */
if( !enc28j60_check_config( &initvars ) )
{
enc28j60_recv_reset( &initvars, 1 );
}
}
}
else
initvars.have_recv = 0;
return ret;
}
void enc28j60_dump_regs(void)
{
/* this will work only with DOSBase known globally, not when it's redirected to Plipbase */
#ifdef _DO_DUMP
u08 val,eir,eie,econ1,econ2,estat;
u16 erxrdpt,erxwrpt,erxst,erxnd,mamxfll;
u16 macon1,macon3,macon4;
eir = readRegByte(EIR);
eie = readRegByte(EIE);
econ1 = readRegByte(ECON1);
econ2 = readRegByte(ECON2);
estat = readRegByte(ESTAT);
printf("EIR EIE ECON1 ECON2 ESTAT\n");
printf("%02x %02x %02x %02x %02x\n",
eir,eie,econ1,econ2,estat);
erxrdpt = readRegByte(ERXRDPT) + (((u16)readRegByte(ERXRDPT+1))<<8);
erxwrpt = readRegByte(ERXWRPT) + (((u16)readRegByte(ERXWRPT+1))<<8);
erxst = readRegByte(ERXST) + (((u16)readRegByte(ERXST+1))<<8);
erxnd = readRegByte(ERXND) + (((u16)readRegByte(ERXND+1))<<8);
mamxfll = readRegByte(MAMXFL) + (((u16)readRegByte(MAMXFL+1))<<8);
printf("ERXRDPT ERXWRPT ERXST ERXND MAMXFL\n");
printf("%04x %04x %04x %04x %04x\n",
erxrdpt,erxwrpt,erxst,erxnd,mamxfll);
macon1 = readRegByte(MACON1);/* + (((u16)readRegByte(MACON1+1))<<8); */
macon3 = readRegByte(MACON3);/* + (((u16)readRegByte(MACON1+3))<<8); */
macon4 = readRegByte(MACON4);/* + (((u16)readRegByte(MACON1+4))<<8); */
printf("MACON1 MACON3 MACON4\n");
printf("%02x %02x %02x\n",
macon1,macon3,macon4);
printf("MAADR\n");
printf("%02x:%02x:%02x:%02x:%02x:%02x\n",
(int)readRegByte(MAADR5),
(int)readRegByte(MAADR4),
(int)readRegByte(MAADR3),
(int)readRegByte(MAADR2),
(int)readRegByte(MAADR1),
(int)readRegByte(MAADR0) );
val = readRegByte(EIR);
#endif
}
#if 0
/* Contributed by Alex M. Based on code from: http://blog.derouineau.fr */
/* /2011/07/putting-enc28j60-ethernet-controler-in-sleep-mode/ */
void enc28j60_power_down( void )
{
writeOp(ENC28J60_BIT_FIELD_CLR, ECON1, ECON1_RXEN);
while(readRegByte(ESTAT) & ESTAT_RXBUSY);
while(readRegByte(ECON1) & ECON1_TXRTS);
writeOp(ENC28J60_BIT_FIELD_SET, ECON2, ECON2_VRPS);
writeOp(ENC28J60_BIT_FIELD_SET, ECON2, ECON2_PWRSV);
}
void enc28j60_power_up( void )
{
writeOp(ENC28J60_BIT_FIELD_CLR, ECON2, ECON2_PWRSV);
while(!readRegByte(ESTAT) & ESTAT_CLKRDY);
writeOp(ENC28J60_BIT_FIELD_SET, ECON1, ECON1_RXEN);
}
uint8_t enc28j60_do_BIST ( void )
{
#define RANDOM_FILL 0b0000
#define ADDRESS_FILL 0b0100
#define PATTERN_SHIFT 0b1000
#define RANDOM_RACE 0b1100
/* init */
spi_disable_eth();
writeOp(ENC28J60_SOFT_RESET, 0, ENC28J60_SOFT_RESET);
_delay_ms(2); /* errata B7/2 */
while (!readOp(ENC28J60_READ_CTRL_REG, ESTAT) & ESTAT_CLKRDY) ;
/* now we can start the memory test */
uint16_t macResult;
uint16_t bitsResult;
/* clear some of the registers registers */
writeRegByte(ECON1, 0);
writeReg(EDMAST, 0);
/* Set up necessary pointers for the DMA to calculate over the entire memory */
writeReg(EDMAND, 0x1FFFu);
writeReg(ERXND, 0x1FFFu);
/* Enable Test Mode and do an Address Fill */
SetBank(EBSTCON);
writeRegByte(EBSTCON, EBSTCON_TME | EBSTCON_BISTST | ADDRESS_FILL);
/* wait for BISTST to be reset, only after that are we actually ready to */
/* start the test */
/* this was undocumented :( */
while (readOp(ENC28J60_READ_CTRL_REG, EBSTCON) & EBSTCON_BISTST);
writeOp(ENC28J60_BIT_FIELD_CLR, EBSTCON, EBSTCON_TME);
/* now start the actual reading an calculating the checksum until the end is */
/* reached */
writeOp(ENC28J60_BIT_FIELD_SET, ECON1, ECON1_DMAST | ECON1_CSUMEN);
SetBank(EDMACS);
while(readOp(ENC28J60_READ_CTRL_REG, ECON1) & ECON1_DMAST);
macResult = readReg(EDMACS);
bitsResult = readReg(EBSTCS);
/* Compare the results */
/* 0xF807 should always be generated in Address fill mode */
if ((macResult != bitsResult) || (bitsResult != 0xF807)) {
return 0;
}
/* reset test flag */
writeOp(ENC28J60_BIT_FIELD_CLR, EBSTCON, EBSTCON_TME);
/* Now start the BIST with random data test, and also keep on swapping the */
/* DMA/BIST memory ports. */
writeRegByte(EBSTSD, 0b10101010 /* | millis()*/);
writeRegByte(EBSTCON, EBSTCON_TME | EBSTCON_PSEL | EBSTCON_BISTST | RANDOM_FILL);
/* wait for BISTST to be reset, only after that are we actually ready to */
/* start the test */
/* this was undocumented :( */
while (readOp(ENC28J60_READ_CTRL_REG, EBSTCON) & EBSTCON_BISTST);
writeOp(ENC28J60_BIT_FIELD_CLR, EBSTCON, EBSTCON_TME);
/* now start the actual reading an calculating the checksum until the end is */
/* reached */
writeOp(ENC28J60_BIT_FIELD_SET, ECON1, ECON1_DMAST | ECON1_CSUMEN);
SetBank(EDMACS);
while(readOp(ENC28J60_READ_CTRL_REG, ECON1) & ECON1_DMAST);
macResult = readReg(EDMACS);
bitsResult = readReg(EBSTCS);
/* The checksum should be equal */
return macResult == bitsResult;
}
#endif
Driver/baxnet/source/sdnet/enc28j60.h
-72
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/*
* enc28j60.h - Microchip ENC28J60 interface
*
* Written by
* Henryk Richter <henryk.richter@gmx.net>
*
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
* 02111-1307 USA.
*
*/
#ifndef _INC_ENC28J60_H
#define _INC_ENC28J60_H
/* result values */
#define PIO_OK 0
#define PIO_NOT_FOUND 1
#define PIO_TOO_LARGE 2
#define PIO_IO_ERR 3
/* init flags */
#define PIO_INIT_FULL_DUPLEX 1
#define PIO_INIT_LOOP_BACK 2
#define PIO_INIT_BROAD_CAST 4
#define PIO_INIT_FLOW_CONTROL 8
#define PIO_INIT_MULTI_CAST 16
#define PIO_INIT_PROMISC 32
/* status flags */
#define PIO_STATUS_VERSION 0
#define PIO_STATUS_LINK_UP 1
#define PIO_STATUS_FULLDPX 2
/* control ids */
#define PIO_CONTROL_FLOW 0
/* sigh, old gcc does not have stdint.h */
typedef unsigned char u08;
typedef unsigned short u16;
typedef unsigned char uint8_t;
typedef unsigned short uint16_t;
/* API functions */
u08 enc28j60_init(const u08 macaddr[6], u08 flags);
void enc28j60_exit(void);
u08 enc28j60_setOnline( void );
u08 enc28j60_setOffline( void );
void enc28j60_SetSPISpeed( unsigned long clock_divider );
u08 enc28j60_send(const u08 *data, u16 size);
u08 enc28j60_recv(u08 *data, u16 max_size, u16 *got_size);
u08 enc28j60_status( u08 status_id, u08 *value);
u08 enc28j60_has_recv(void);
void enc28j60_setMAC( const u08 macaddr[6] );
void enc28j60_getMAC( u08 macaddr[6] ); /* mainly for debug */
void enc28j60_dump_regs(void);
void enc28j60_broadcast_multicast_filter( u08 flags );
#endif /* _INC_ENC28J60_H */
Driver/baxnet/source/sdnet/enc28j60l.asm
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Driver/baxnet/source/sdnet/enc28j60l.h
-405
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/*
enc28j60l.h
author: Henryk Richter <henryk.richter@gmx.net>
purpose: header for low-level register and SPI access
to ENC28J60 networking device
*/
#ifndef _INC_ENC28J60L_H
#define _INC_ENC28J60L_H
#include "compiler.h"
/*
Purpose: interrupt service routine ( after EnableInterrupt() )
This function will signal the task passed at EnableInterrupt time with
the given sigbit when at least one frame is pending.
input: -
output: -
*/
ASM SAVEDS void enc28j60l_IntServer_List( void );
/*
Purpose: enable HW interrupt
input: board - mmapped board base address
SigTask - task to signal upon interrupt (or NULL)
SigBit - Signal bit to send upon interrupt (or -1)
IntMask - ENC HW interrupts to enable (set 0, for now) = RX PACKET only
output: <0 - error
>=0 - OK
notes:
*/
ASM SAVEDS int enc28j60l_EnableInterrupt( ASMR(a0) void *board ASMREG(a0),
ASMR(a1) void* SigTask ASMREG(a1),
ASMR(d0) int SigBit ASMREG(d0),
ASMR(d1) unsigned int IntMask ASMREG(d1) );
/*
Purpose: disable HW interrupt
input: board - mmapped board base address
output: <0 - error
>=0 - OK
notes:
*/
ASM SAVEDS int enc28j60l_DisableInterrupt( ASMR(a0) void *board ASMREG(a0) );
/*
Purpose: prepare SPI for use
input: -
output: success/failure
>0 - all fine, ready to work
<=0 - init problem (codes undefined yet)
*/
ASM SAVEDS int enc28j60l_Init( void );
/*
Purpose: shutdown SPI
input: -
output: -
*/
ASM SAVEDS void enc28j60l_Shutdown( void );
/*
Purpose: delay at least the given amount of microseconds
input: delay time in microseconds
output: -
*/
ASM SAVEDS void enc28j60l_UMinDelay(
ASMR(d0) unsigned long udelay ASMREG(d0) );
/*
Purpose: set SPI clock divider
input: clock divider 1...n
output: -
*/
ASM SAVEDS void enc28j60l_SetSPISpeed(
ASMR(d0) unsigned long divider ASMREG(d0) );
/*
purpose: read one byte from a custom register
input: op = ENC28J60_READ_CTRL_REG
address = register address, including bits denoting the bank
data = data byte
*/
ASM SAVEDS unsigned char enc28j60l_ReadOp(
ASMR(d3) unsigned char op ASMREG(d3),
ASMR(d0) unsigned char address ASMREG(d0) );
/*
purpose: write one byte to a custom register
input: op = ENC28J60_WRITE_CTRL_REG,
ENC28J60_BIT_FIELD_SET,
ENC28J60_BIT_FIELD_CLR
address = register address, including bits denoting the bank
data = data byte
*/
ASM void enc28j60l_WriteOp( ASMR(d3) unsigned char op ASMREG(d3),
ASMR(d0) unsigned char address ASMREG(d0),
ASMR(d1) unsigned char data ASMREG(d1));
/*
purpose: select register bank based on given address
input:
address = register address, including bits denoting the bank
*/
ASM SAVEDS void enc28j60l_SetBank( ASMR(d0) unsigned char address ASMREG(d0) );
/*
purpose: read one short from a custom register
input: address = register address, including bits denoting the bank
data = data word (unsigned short)
*/
ASM SAVEDS unsigned short enc28j60l_ReadReg( ASMR(d0) unsigned char address ASMREG(d0) );
/*
purpose: write one short to a custom register
input: address = register address, including bits denoting the bank
data = data word (unsigned short)
*/
ASM void enc28j60l_WriteReg( ASMR(d0) unsigned char address ASMREG(d0),
ASMR(d1) unsigned short data ASMREG(d1));
/*
purpose: read one byte from a custom register
input: address = register address, including bits denoting the bank
*/
ASM SAVEDS unsigned char enc28j60l_ReadRegByte(
ASMR(d0) unsigned char address ASMREG(d0));
/*
purpose: write one byte to a custom register
input: address = register address, including bits denoting the bank
data = data word (unsigned short)
*/
ASM void enc28j60l_WriteRegByte( ASMR(d0) unsigned char address ASMREG(d0),
ASMR(d1) unsigned char data ASMREG(d1));
/*
purpose: Read buffer from device to computer
input: buffer = buffer to read into
size = length of buffer
*/
ASM void enc28j60l_ReadBuffer( ASMR(a1) unsigned char *buffer ASMREG(a1),
ASMR(d0) unsigned int size ASMREG(d0));
/*
purpose: Write buffer from computer to device
input: buffer = buffer to write
size = length of buffer
destptr = destination pointer in device
*/
ASM void enc28j60l_WriteBuffer( ASMR(a1) unsigned char *buffer ASMREG(a1),
ASMR(d0) unsigned int size ASMREG(d0),
ASMR(d1) unsigned short destptr ASMREG(d1));
/*
Definitions based on the enc28j60.c file from the AVRlib library by Pascal Stang.
ENC28J60 Control Registers
Control register definitions are a combination of address,
bank number, and Ethernet/MAC/PHY indicator bits.
- Register address (bits 0-4)
- Bank number (bits 5-6)
- MAC/PHY indicator (bit 7)
*/
#define ADDR_MASK 0x1F
#define BANK_MASK 0x60
#define SPRD_MASK 0x80
/* All-bank registers */
#define EIE 0x1B
#define EIR 0x1C
#define ESTAT 0x1D
#define ECON2 0x1E
#define ECON1 0x1F
/* Bank 0 registers */
#define ERDPT (0x00|0x00)
#define EWRPT (0x02|0x00)
#define ETXST (0x04|0x00)
#define ETXND (0x06|0x00)
#define ERXST (0x08|0x00)
#define ERXND (0x0A|0x00)
#define ERXRDPT (0x0C|0x00)
#define ERXWRPT (0x0E|0x00)
#define EDMAST (0x10|0x00)
#define EDMAND (0x12|0x00)
/* #define EDMADST (0x14|0x00) */
#define EDMACS (0x16|0x00)
/* Bank 1 registers */
#define EHT0 (0x00|0x20)
#define EHT1 (0x01|0x20)
#define EHT2 (0x02|0x20)
#define EHT3 (0x03|0x20)
#define EHT4 (0x04|0x20)
#define EHT5 (0x05|0x20)
#define EHT6 (0x06|0x20)
#define EHT7 (0x07|0x20)
#define EPMM0 (0x08|0x20)
#define EPMM1 (0x09|0x20)
#define EPMM2 (0x0A|0x20)
#define EPMM3 (0x0B|0x20)
#define EPMM4 (0x0C|0x20)
#define EPMM5 (0x0D|0x20)
#define EPMM6 (0x0E|0x20)
#define EPMM7 (0x0F|0x20)
#define EPMCS (0x10|0x20)
/* #define EPMO (0x14|0x20) */
#define EWOLIE (0x16|0x20)
#define EWOLIR (0x17|0x20)
#define ERXFCON (0x18|0x20)
#define EPKTCNT (0x19|0x20)
/* Bank 2 registers */
#define MACON1 (0x00|0x40|0x80)
#define MACON2 (0x01|0x40|0x80)
#define MACON3 (0x02|0x40|0x80)
#define MACON4 (0x03|0x40|0x80)
#define MABBIPG (0x04|0x40|0x80)
#define MAIPG (0x06|0x40|0x80)
#define MACLCON1 (0x08|0x40|0x80)
#define MACLCON2 (0x09|0x40|0x80)
#define MAMXFL (0x0A|0x40|0x80)
#define MAPHSUP (0x0D|0x40|0x80)
#define MICON (0x11|0x40|0x80)
#define MICMD (0x12|0x40|0x80)
#define MIREGADR (0x14|0x40|0x80)
#define MIWR (0x16|0x40|0x80)
#define MIRD (0x18|0x40|0x80)
/* Bank 3 registers */
#define MAADR1 (0x00|0x60|0x80)
#define MAADR0 (0x01|0x60|0x80)
#define MAADR3 (0x02|0x60|0x80)
#define MAADR2 (0x03|0x60|0x80)
#define MAADR5 (0x04|0x60|0x80)
#define MAADR4 (0x05|0x60|0x80)
#define EBSTSD (0x06|0x60)
#define EBSTCON (0x07|0x60)
#define EBSTCS (0x08|0x60)
#define MISTAT (0x0A|0x60|0x80)
#define EREVID (0x12|0x60)
#define ECOCON (0x15|0x60)
#define EFLOCON (0x17|0x60)
#define EPAUS (0x18|0x60)
/* ENC28J60 ERXFCON Register Bit Definitions */
#define ERXFCON_UCEN 0x80
#define ERXFCON_ANDOR 0x40
#define ERXFCON_CRCEN 0x20
#define ERXFCON_PMEN 0x10
#define ERXFCON_MPEN 0x08
#define ERXFCON_HTEN 0x04
#define ERXFCON_MCEN 0x02
#define ERXFCON_BCEN 0x01
/* ENC28J60 EIE Register Bit Definitions */
#define EIE_INTIE 0x80
#define EIE_PKTIE 0x40
#define EIE_DMAIE 0x20
#define EIE_LINKIE 0x10
#define EIE_TXIE 0x08
#define EIE_WOLIE 0x04
#define EIE_TXERIE 0x02
#define EIE_RXERIE 0x01
/* ENC28J60 EIR Register Bit Definitions */
#define EIR_PKTIF 0x40
#define EIR_DMAIF 0x20
#define EIR_LINKIF 0x10
#define EIR_TXIF 0x08
#define EIR_WOLIF 0x04
#define EIR_TXERIF 0x02
#define EIR_RXERIF 0x01
/* ENC28J60 ESTAT Register Bit Definitions */
#define ESTAT_INT 0x80
#define ESTAT_LATECOL 0x10
#define ESTAT_RXBUSY 0x04
#define ESTAT_TXABRT 0x02
#define ESTAT_CLKRDY 0x01
/* ENC28J60 ECON2 Register Bit Definitions */
#define ECON2_AUTOINC 0x80
#define ECON2_PKTDEC 0x40
#define ECON2_PWRSV 0x20
#define ECON2_VRPS 0x08
/* ENC28J60 ECON1 Register Bit Definitions */
#define ECON1_TXRST 0x80
#define ECON1_RXRST 0x40
#define ECON1_DMAST 0x20
#define ECON1_CSUMEN 0x10
#define ECON1_TXRTS 0x08
#define ECON1_RXEN 0x04
#define ECON1_BSEL1 0x02
#define ECON1_BSEL0 0x01
/* ENC28J60 MACON1 Register Bit Definitions */
#define MACON1_LOOPBK 0x10
#define MACON1_TXPAUS 0x08
#define MACON1_RXPAUS 0x04
#define MACON1_PASSALL 0x02
#define MACON1_MARXEN 0x01
/* ENC28J60 MACON2 Register Bit Definitions */
#define MACON2_MARST 0x80
#define MACON2_RNDRST 0x40
#define MACON2_MARXRST 0x08
#define MACON2_RFUNRST 0x04
#define MACON2_MATXRST 0x02
#define MACON2_TFUNRST 0x01
/* ENC28J60 MACON3 Register Bit Definitions */
#define MACON3_PADCFG2 0x80
#define MACON3_PADCFG1 0x40
#define MACON3_PADCFG0 0x20
#define MACON3_TXCRCEN 0x10
#define MACON3_PHDRLEN 0x08
#define MACON3_HFRMLEN 0x04
#define MACON3_FRMLNEN 0x02
#define MACON3_FULDPX 0x01
/* ENC28J60 MICMD Register Bit Definitions */
#define MICMD_MIISCAN 0x02
#define MICMD_MIIRD 0x01
/* ENC28J60 MISTAT Register Bit Definitions */
#define MISTAT_NVALID 0x04
#define MISTAT_SCAN 0x02
#define MISTAT_BUSY 0x01
/* ENC28J60 EBSTCON Register Bit Definitions */
#define EBSTCON_PSV2 0x80
#define EBSTCON_PSV1 0x40
#define EBSTCON_PSV0 0x20
#define EBSTCON_PSEL 0x10
#define EBSTCON_TMSEL1 0x08
#define EBSTCON_TMSEL0 0x04
#define EBSTCON_TME 0x02
#define EBSTCON_BISTST 0x01
/* PHY registers */
#define PHCON1 0x00
#define PHSTAT1 0x01
#define PHHID1 0x02
#define PHHID2 0x03
#define PHCON2 0x10
#define PHSTAT2 0x11
#define PHIE 0x12
#define PHIR 0x13
#define PHLCON 0x14
/* ENC28J60 PHY PHCON1 Register Bit Definitions */
#define PHCON1_PRST 0x8000
#define PHCON1_PLOOPBK 0x4000
#define PHCON1_PPWRSV 0x0800
#define PHCON1_PDPXMD 0x0100
/* ENC28J60 PHY PHSTAT1 Register Bit Definitions */
#define PHSTAT1_PFDPX 0x1000
#define PHSTAT1_PHDPX 0x0800
#define PHSTAT1_LLSTAT 0x0004
#define PHSTAT1_JBSTAT 0x0002
/* ENC28J60 PHY PHCON2 Register Bit Definitions */
#define PHCON2_FRCLINK 0x4000
#define PHCON2_TXDIS 0x2000
#define PHCON2_JABBER 0x0400
#define PHCON2_HDLDIS 0x0100
/* PHIE Register */
#define PHIE_PGEIE (1<<1)
#define PHIE_LNKIE (1<<4)
/* ENC28J60 Packet Control Byte Bit Definitions */
#define PKTCTRL_PHUGEEN 0x08
#define PKTCTRL_PPADEN 0x04
#define PKTCTRL_PCRCEN 0x02
#define PKTCTRL_POVERRIDE 0x01
/* SPI operation codes */
#define ENC28J60_READ_CTRL_REG 0x00
#define ENC28J60_READ_BUF_MEM 0x3A
#define ENC28J60_WRITE_CTRL_REG 0x40
#define ENC28J60_WRITE_BUF_MEM 0x7A
#define ENC28J60_BIT_FIELD_SET 0x80
#define ENC28J60_BIT_FIELD_CLR 0xA0
#define ENC28J60_SOFT_RESET 0xFF
#endif /* _INC_ENC28J60L_H */
Driver/baxnet/source/sdnet/hw.c
-549
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/*
hw.c
(C) 2018 Henryk Richter <henryk.richter@gmx.net>
SDNet hardware interface to device
*/
#include <exec/libraries.h>
#include <proto/exec.h>
#include "device.h"
#include "hw.h"
#include <proto/vampire.h>
#include <vampire/vampire.h>
#include "vampuuid.h"
#include "enc28j60.h"
#include <hardware/intbits.h>
#include "enc28j60l.h"
#ifndef PROTO_V2EXPNET
#define PORTID V_SDPORT
#else
#define PORTID V_WIFIPORT
#endif
extern const BYTE DeviceName[];
/* use generic board fields in current unit */
#define hw_allocated du_hwl0
#define duh_online du_hwl1
#define duh_BASE du_hwp0
#define HW_INTERVALDEF 10000
#define HW_DEFSPI 2
/* these calls might not run within the context of a process and
will be called from varying tasks and without prior init:
hw_Find_Boards() - this one just identifies available HW and returns #boards
hw_AllocBoard()
hw_ReleaseBoard()
hw_GetMacAddress() - get default MAC address from board
these calls are in the context of the server task:
hw_Setup() - general init (board allocated already)
hw_Shutdown() - general shutdown (board still allocated)
hw_Attach() - make hardware ready for action (online)
hw_Detach() - put hardware into sleep mode (offline)
hw_recv_sigmask() - get signals for hardware (if any, i.e. signal on interrupt)
hw_recv_pending() - check for pending receive frames
hw_recv_frame() - receive one frame
hw_send_frame() - send one frame
hw_check_link_change() - check if HW link parameters need update
and apply them (called only when no RX/TX
in progress)
hw_ConfigInit() - set defaults for HW
hw_ConfigUpdate() - update config of HW
hw_change_multicast - re-initialize multicast filter for new address list
hw_get_mac_status() - running parameters (optional), S2_DEVICEQUERYEXT
*/
#ifdef PROTO_V2EXPNET
#define USE_INTERRUPT
/* used only if interrupts are in play (currently V2ExpETH) */
void myhw_ControlInterrupts( DEVBASEP );
const BYTE intname[] = "v2expeth SanaII driver";
#define HW_INTSOURCE INTB_PORTS /* Int 2 */
#else
#define myhw_ControlInterrupts( _a_ )
#endif
const BYTE vres_name[] = V_VAMPIRENAME;
/* return number of boards present in system */
ASM SAVEDS LONG hw_Find_Boards( ASMR(a0) DEVBASEP ASMREG(a0) )
{
LONG ret = 0;
struct Library *VampireBase;
if( (VampireBase = OpenResource( (BYTE*)vres_name )) )
{
/* TODO: check for expansion port, i.e. distinguish V500/V600 */
/* TODO: actually verify that we have a module here */
ret = 1;
}
return ret;
}
ASM SAVEDS LONG hw_AllocBoard( ASMR(a0) DEVBASEP ASMREG(a0),
ASMR(d0) ULONG unit ASMREG(d0) )
{
LONG ret = 0;
struct Library *VampireBase;
if( (VampireBase = OpenResource( (BYTE*)vres_name )) ) /* OpenResource is probably redundant */
{
if( unit == 0 )
{
ret = 1; /* def: looks good */
if( db->db_Units[unit].hw_allocated == 0 )
{
if( V_AllocExpansionPort( PORTID, (BYTE*)DeviceName ) )
ret = 0;
}
if( ret )
db->db_Units[unit].hw_allocated++;
}
}
return ret;
}
ASM SAVEDS LONG hw_ReleaseBoard( ASMR(a0) DEVBASEP ASMREG(a0),
ASMR(d0) ULONG unit ASMREG(d0) )
{
LONG ret = 0;
struct Library *VampireBase;
if( (VampireBase = OpenResource( (BYTE*)vres_name )) ) /* OpenResource is probably redundant */
{
if( unit == 0) /* only one device supported */
{
ret = 1; /* def: looks good */
if( db->db_Units[unit].hw_allocated > 0 )
{
db->db_Units[unit].hw_allocated--;
if( !db->db_Units[unit].hw_allocated )
{
V_FreeExpansionPort( PORTID );
}
}
}
}
return ret;
}
/* store MAC address at "mac", 6 Bytes */
ASM SAVEDS LONG hw_GetMacAddress( ASMR(a0) DEVBASEP ASMREG(a0),
ASMR(d0) ULONG unit ASMREG(d0),
ASMR(a1) UBYTE *mac ASMREG(a1)
)
{
static UBYTE addr[6] = { 0x02,0x80,0x10,0x0b,0x0a,0xff};
UBYTE vsn[8];
LONG i;
if( vampire_UUID( vsn ) > 0 )
{
for(i=0 ; i<3 ; i++ )
{
addr[3+i] = vsn[i] ^ vsn[i+5];
}
}
for( i=0 ; i<6 ; i++ )
mac[i] = addr[i];
return 0;
}
/* prepare all boards such that a hw_attach() will succeed */
ASM SAVEDS LONG hw_Setup( ASMR(a0) DEVBASEP ASMREG(a0) )
{
LONG ret = 0;
struct HWData *hwd = &db->db_hwdat;
#ifdef USE_INTERRUPT
hwd->IntSig = AllocSignal(-1);
hwd->hwd_Interrupt.is_Data = (0);
#ifdef PROTO_V2EXPNET
db->db_Units[0].duh_BASE = (void*)0xDE0010;
#else
db->db_Units[0].duh_BASE = (void*)0xDE0000;
#endif
#else
hwd->IntSig = -1;
#endif
if( InitIntervalTimer( &hwd->ivtimer ) > 0 )
{
hwd->SigMask = hwd->ivtimer.IVT_SigMask;
#ifdef USE_INTERRUPT
hwd->SigMask |= (1<<(hwd->IntSig));
#endif
ret = 1;
}
return ret;
}
/* free resources, server is quitting */
ASM SAVEDS void hw_Shutdown( ASMR(a0) DEVBASEP ASMREG(a0) )
{
struct HWData *hwd = &db->db_hwdat;
db->db_Units[0].duh_online = 0;
myhw_ControlInterrupts( db );
if( hwd->IntSig >= 0 )
FreeSignal( hwd->IntSig );
ExitIntervalTimer( &hwd->ivtimer );
}
/* make hardware ready for action (online) */
ASM SAVEDS LONG hw_Attach( ASMR(a0) DEVBASEP ASMREG(a0),
ASMR(d0) ULONG unit ASMREG(d0))
{
struct HWData *hwd = &db->db_hwdat;
LONG ret = 1;
u08 flags;
if( unit > 0 )
return 0;
flags = PIO_INIT_BROAD_CAST;
if( hwd->multicast )
flags |= PIO_INIT_MULTI_CAST;
if( hwd->fullduplex )
flags |= PIO_INIT_FULL_DUPLEX;
if( db->db_Units[0].du_Flags & DUF_PROMISC )
flags |= PIO_INIT_PROMISC;
enc28j60_SetSPISpeed( hwd->spispeed );
if( enc28j60_init( db->db_Units[0].du_CFGAddr, flags ) != PIO_OK )
ret = 0;
else
{
db->db_Units[0].duh_online = 1; /* used for int server and interval timer setup */
enc28j60_SetSPISpeed( hwd->spispeed );
myhw_ControlInterrupts( db );
if( hwd->timervalue > 0 )
StartIntervalTimer( &hwd->ivtimer, hwd->timervalue );
}
return ret;
}
/* put hardware into sleep mode (offline) */
ASM SAVEDS void hw_Detach( ASMR(a0) DEVBASEP ASMREG(a0),
ASMR(d0) ULONG unit ASMREG(d0))
{
if( !unit )
{
struct HWData *hwd = &db->db_hwdat;
db->db_Units[unit].duh_online = 0; /* used for int server and interval timer setup */
myhw_ControlInterrupts( db ); /* start and/or stop (based on duh_online) */
StopIntervalTimer( &hwd->ivtimer );
myhw_ControlInterrupts( db ); /* start and/or stop (based on duh_online) */
enc28j60_exit();
}
}
ASM SAVEDS void hw_ConfigInit( ASMR(a0) DEVBASEP ASMREG(a0) )
{
struct HWData *hwd = &db->db_hwdat;
hwd->timervalue = HW_INTERVALDEF;
hwd->fullduplex = 0;
hwd->spispeed = HW_DEFSPI; /* default (see above) */
hwd->multicast = 0;
hwd->interrupt = 0; /* def: don`t enable interrupt */
#if 0
USHORT i;
for( i=0 ; i < (USHORT)db->db_NBoards ; i++ )
{ /* no need, these are defaults */
db->db_Units[i].du_MTU = 1500;
db->db_Units[i].du_BitPerSec = 10000000;
}
#endif
}
ASM SAVEDS void hw_ConfigUpdate( ASMR(a0) DEVBASEP ASMREG(a0),
ASMR(a1) void*argsv ASMREG(a1))
{
struct HWConfig *args = (struct HWConfig *)argsv; /* see hwprivate.h */
struct HWData *hwd = &db->db_hwdat;
if( args->timervalue )
hwd->timervalue = *args->timervalue;
if( args->fullduplex )
hwd->fullduplex = 1;
if( args->spispeed )
hwd->spispeed = *args->spispeed;
if( args->multicast )
hwd->multicast = 1;
if( args->interrupt )
hwd->interrupt = 1;
}
ASM SAVEDS LONG hw_send_frame( ASMR(a0) DEVBASEP ASMREG(a0),
ASMR(d0) ULONG unit ASMREG(d0),
ASMR(a1) UBYTE *frame ASMREG(a1),
ASMR(d1) ULONG framesize ASMREG(d1) )
{
#ifdef USE_INTERRUPT
struct HWData *hwd = &db->db_hwdat;
hwd->hwd_act_boards[0] = (void*)(0); /* disable interrupt processing */
#endif
enc28j60_send( frame, framesize );
return 1;
}
ASM SAVEDS LONG hw_recv_pending( ASMR(a0) DEVBASEP ASMREG(a0),
ASMR(d0) ULONG unit ASMREG(d0) )
{
#ifdef USE_INTERRUPT
LONG ret;
struct HWData *hwd = &db->db_hwdat;
void *tmp = hwd->hwd_act_boards[0];
hwd->hwd_act_boards[0] = (void*)(0); /* disable interrupt processing */
ret = (LONG)enc28j60_has_recv();
hwd->hwd_act_boards[0] = tmp; /* restore interrupt processing enable flag */
return ret;
#else
return (LONG)enc28j60_has_recv();
#endif
}
ASM SAVEDS LONG hw_recv_frame( ASMR(a0) DEVBASEP ASMREG(a0),
ASMR(d0) ULONG unit ASMREG(d0),
ASMR(a1) UBYTE *frame ASMREG(a1))
{
volatile SHORT sz;
LONG ret;
#ifdef USE_INTERRUPT
struct HWData *hwd = &db->db_hwdat;
hwd->hwd_act_boards[0] = (void*)(0); /* disable interrupt processing */
#endif
/* important: don't call this without enc28j60_has_recv() > 0 check */
if( PIO_OK != enc28j60_recv( frame, 1518, (unsigned short*)&sz ) )
ret = 0;
else
ret = (LONG)sz;
return (LONG)ret;
}
ASM SAVEDS ULONG hw_recv_sigmask( ASMR(a0) DEVBASEP ASMREG(a0) )
{
struct HWData *hwd = &db->db_hwdat;
return hwd->SigMask;
}
/* check if HW link parameters need update */
ASM SAVEDS LONG hw_check_link_change( ASMR(a0) DEVBASEP ASMREG(a0),
ASMR(d0) ULONG unit ASMREG(d0) )
{
#ifdef USE_INTERRUPT
struct HWData *hwd = &db->db_hwdat;
if( hwd->hwd_Interrupt.is_Data ) /* interrupt running ? */
{
hwd->hwd_act_boards[0] = (void*)(1); /* re-enable interrupt processing */
/* re-enable interrupt when server goes to sleep */
enc28j60l_EnableInterrupt( db->db_Units[unit].duh_BASE, FindTask(0), (int)hwd->IntSig, 0 );
}
#endif
return 0;
}
/* obtain running parameters of Ethernet MAC: link up/down, Speed, Duplex */
/* note: */
/* if this call is unsupported then return HW_MAC_INVALID */
ASM SAVEDS LONG hw_get_mac_status( ASMR(a0) DEVBASEP ASMREG(a0),
ASMR(d0) ULONG unit ASMREG(d0) )
{
LONG ret = 0; /* def: link down */
UBYTE status;
enc28j60_status( PIO_STATUS_LINK_UP, &status );
if( status )
{
ret = HW_MAC_LINK_UP; /* LINK_UP may be redundant */
enc28j60_status( PIO_STATUS_FULLDPX, &status );
if( status )
ret |= HW_MAC_ON_FDX<<HW_MACB_SPEED10;
else
ret |= HW_MAC_ON<<HW_MACB_SPEED10;
}
return ret;
}
/* read PHY register */
ASM SAVEDS LONG hw_read_phy( ASMR(a0) DEVBASEP ASMREG(a0),
ASMR(d0) ULONG unit ASMREG(d0),
ASMR(d1) ULONG reg ASMREG(d1) )
{
return -1;
}
/* write PHY register (return -1 in case of error) */
ASM SAVEDS LONG hw_write_phy( ASMR(a0) DEVBASEP ASMREG(a0),
ASMR(d0) ULONG unit ASMREG(d0),
ASMR(d1) ULONG reg ASMREG(d1),
ASMR(d2) ULONG value ASMREG(d2) )
{
return -1;
}
/* process the list of multicast addresses for an appropriate
filtering list on the hardware
the server preprocesses active multicast listeners such that
this call can decide whether to enable multicast altogether,
filter with hashes etc.
*/
ASM SAVEDS LONG hw_change_multicast( ASMR(a0) DEVBASEP ASMREG(a0),
ASMR(d0) ULONG unit ASMREG(d0),
ASMR(a1) struct List *mcastlist ASMREG(a1) )
{
u08 flags;
flags = PIO_INIT_BROAD_CAST;
if( db->db_Units[0].du_Flags & DUF_PROMISC )
flags |= PIO_INIT_PROMISC;
/* list non-empty ? (sufficient for ENC28J60 -> it doesn`t have hashing) */
if( mcastlist->lh_Head->ln_Succ )
flags |= PIO_INIT_MULTI_CAST;
enc28j60_broadcast_multicast_filter( flags );/* flags & (PIO_INIT_BROAD_CAST|PIO_INIT_MULTI_CAST) ); */
return 1;
}
#ifdef USE_INTERRUPT
/* relies on hwd_online */
void myhw_ControlInterrupts( DEVBASEP )
{
struct HWData *hwd = &db->db_hwdat;
LONG i,flag;
if( !hwd->interrupt )
return;
flag = 0;
for( i=0 ; i < db->db_NBoards ; i++ )
{
if( db->db_Units[i].duh_online )
{
hwd->hwd_act_boards[flag+1] = db->db_Units[i].duh_BASE;
flag++;
}
}
hwd->hwd_act_boards[flag+1] = (0); /* NULL-terminate */
hwd->hwd_act_boards[flag+2] = (APTR)FindTask(0); /* append task */
hwd->hwd_act_boards[flag+3] = (APTR)hwd->IntSig; /* append sigbit */
if( flag ) /* determine on/off switch */
{
/* at least 1 board is online */
hwd->hwd_act_boards[0] = (void*)(1); /* enable interrupt processing */
if( hwd->hwd_Interrupt.is_Data )
flag = 0; /* no change */
else flag = 1; /* start interrupt */
}
else
{
hwd->hwd_act_boards[0] = 0; /* disable interrupt processing */
if( hwd->hwd_Interrupt.is_Data )
flag = -1; /* stop interrupt */
else flag = 0; /* no change */
}
/* flag is >0 = start, <0 = stop or 0 = no change */
if( flag > 0 )
{
hwd->hwd_Interrupt.is_Code = (void(*)())enc28j60l_IntServer_List;
hwd->hwd_Interrupt.is_Data = &hwd->hwd_act_boards[0];
hwd->hwd_Interrupt.is_Node.ln_Type = NT_INTERRUPT;
hwd->hwd_Interrupt.is_Node.ln_Pri = 51;
hwd->hwd_Interrupt.is_Node.ln_Name = (char*)intname;
AddIntServer( HW_INTSOURCE, &hwd->hwd_Interrupt );
}
for( i=0 ; i < db->db_NBoards ; i++ )
{
if( db->db_Units[i].duh_online )
{
enc28j60l_EnableInterrupt( db->db_Units[i].duh_BASE, FindTask(0), (int)hwd->IntSig, 0 );
}
else
{
enc28j60l_DisableInterrupt( db->db_Units[i].duh_BASE );
}
}
if( flag < 0 )
{
hwd->hwd_Interrupt.is_Data = (0);
RemIntServer( HW_INTSOURCE, &hwd->hwd_Interrupt );
hwd->hwd_Interrupt.is_Code = (0);
}
}
#endif
Driver/baxnet/source/sdnet/hwprivate.h
-73
View File
@@ -1,73 +0,0 @@
/*
hwprivate.h
(C) 2018 Henryk Richter <henryk.richter@gmx.net>
private structures for hardware instance
*/
#ifndef _INC_HWPRIVATE_H
#define _INC_HWPRIVATE_H
#include "compiler.h"
/* sdnet/v2expnet specific: polling timer */
#include "intervaltimer.h"
#define HW_VENDOR "Henryk Richter"
/* this struct is available in devicebase and should carry global information */
struct HWData {
struct Interrupt hwd_Interrupt; /* keep the interrupt at top of HWData !! */
APTR hwd_act_boards[MAX_UNITS+1+2+1]; /* poll all active boards by ptr in interrupt, NULL terminated, followed by SigTask,Sigbit */
/* contents of hwd_act_boards:
1 ULONG processing ENABLE (1) or DISABLE (0)
n ULONG BOARD LIST, NULL terminated
1 ULONG SigTask
1 ULONG SigBit
*/
struct IVT_TimerStruct ivtimer; /* Timer interval handling (via Interrupt) */
LONG IntSig;
ULONG SigMask; /* signal mask to wait for in server main instance */
/* config options */
ULONG timervalue; /* polling interval in ms */
ULONG fullduplex; /* force full duplex */
ULONG spispeed; /* SPI clock divider (>=1) */
ULONG multicast; /* multicast recv enable */
ULONG interrupt; /* enable interrupt */
};
/* referenced from server.c */
#if (defined PROTO_V2EXPNET)
#define HW_CONFIGFILE "ENV:SANA2/v2expeth.config"
/* appended to COMMON_TEMPLATE */
#define HW_CONFIGTEMPLATE "TIMER/K/N,FULLDUPLEX/S,SPISPEED/K/N,MULTICAST/S,INTERRUPT/S"
#define HW_PRODUCT "VampireV500V2 ENC28J60 ExpansionPort"
#else
#define HW_CONFIGFILE "ENV:SANA2/sdnet.config"
/* appended to COMMON_TEMPLATE */
#define HW_CONFIGTEMPLATE "TIMER/K/N,FULLDUPLEX/S,SPISPEED/K/N,MULTICAST/S"
#define HW_PRODUCT "Vampire SDNet ENC28J60"
/* appended to COMMON_TEMPLATE */
#endif
/* referenced by server.c, hw.c */
struct HWConfig
{
struct CommonConfig common; /* import from hw.h, expected in server.c */
ULONG *timervalue;
ULONG fullduplex;
ULONG *spispeed;
ULONG multicast;
ULONG interrupt;
};
#endif /* _INC_HWPRIVATE_H */
Driver/baxnet/source/sdnet/intervaltimer.asm
-341
View File
@@ -1,341 +0,0 @@
******************************************************************************
* Name: intervaltimer.s *
* Date: $Date: 2016-12-18 22:20:04 +0100 (So, 18. Dez 2016) $ *
* Authors: Henryk Richter *
******************************************************************************
;MACHINE MC68040
include exec/types.i
include lvo/exec_lib.i
include lvo/dos_lib.i
include lvo/timer_lib.i
include exec/exec.i
include dos/dos.i
include dos/dostags.i
include exec/io.i
include dos/dosextens.i
include exec/lists.i
DO_TEST EQU 0
ifne 1
include "intervaltimer.i"
else
STRUCTURE IVT_TimerStruct,0
ULONG IVT_Interval ;<1e6 in microseconds
LONG IVT_Signal ;Signal that is sent back to task from interrupt
ULONG IVT_SigMask
APTR IVT_SigTask ;Task that is signaled
APTR IVT_Port
APTR IVT_IORequest
APTR IVT_Device
STRUCT IVT_Int,IS_SIZE ;
BYTE IVT_Init ; !=0 - initialized
BYTE IVT_Runflag ; current status ( !=0 = running )
BYTE IVT_Stopflag ; stop request if != 0
BYTE IVT_Unused ;
ULONG IVT_Counter ; Counter (statistics)
LABEL IVT_Size
endc
xdef _InterruptIntervalTimer
xdef _InitIntervalTimer
xdef _ExitIntervalTimer
xdef _StartIntervalTimer
xdef _StopIntervalTimer
CALLEXEC macro
move.l 4.w,a6
jsr _LVO\1(a6)
endm
;section code,text
ifne DO_TEST
TestTimer:
lea dos_name,a1 ;string base
moveq #0,d0
move.l 4.w,a6
jsr _LVOOpenLibrary(a6)
move.l d0,dosbase
beq .nodos
move.l dosbase,a6
jsr _LVOOutput(a6) ;get stdout
move.l d0,stdout
lea timerbase,a1
bsr _InitIntervalTimer
tst.l d0
bge .ok
move.l stdout,d0
move.l #failtimer,d1
move.l dosbase,16
jsr _LVOPutStr(a6)
bra .error
.ok
lea timerbase,a1
move.l #10000,d1
bsr _StartIntervalTimer
moveq #0,d3
.loop
cmp.l #10,d3
bgt.s .exitloop
move.l dosbase,A6
moveq #10,d1
jsr _LVODelay(a6)
addq.l #1,d3
lea timerbase,a1
cmp.l #100,IVT_Counter(a1)
blt.s .loop
.exitloop:
move.l #succname,d1
cmp.l #10,d3
ble.s .succ
move.l #failname,d1
.succ:
jsr _LVOVPrintf(a6)
lea timerbase,a1
bsr _StopIntervalTimer
.error
lea timerbase,a1
bsr _ExitIntervalTimer
move.l dosbase,d0
beq.s .nodos
move.l d0,a1
move.l 4.w,a6
jsr _LVOCloseLibrary(a6)
.nodos:
rts
ENDC ;DO_TEST
; A1 = IVT_TimerStruct
_InterruptIntervalTimer:
movem.l d1-a6,-(sp)
;<- basic Timer.device ops ->
move.l a1,a2
move.l IVT_Port(a2),a0
CALLEXEC GetMsg
tst.l d0
beq.s .error
move.l IVT_SigMask(a2),d0 ;move.l IVT_Signal(a2),d0
move.l IVT_SigTask(a2),a1
CALLEXEC Signal
tst.b IVT_Stopflag(a2)
bne.s .error ;not exactly an error but same consequence
move.l a2,a1
bsr _RestartIntervalTimer
;<- end basic Timer.device ops ->
;<- useful stuff ->
addq.l #1,IVT_Counter(a2)
;<- useful stuff ->
bra.s .endintroutine
.error:
clr.b IVT_Runflag(a2)
.endintroutine:
movem.l (sp)+,d1-a6
rts
_InitIntervalTimer: ;prepare timer.device for buffer swap interrupt
movem.l d1-a6,-(sp)
move.l a1,a2
move #IVT_Size-1,d0
.clr
clr.b (a1)+ ;
dbf d0,.clr
sf IVT_Init(a2)
sf IVT_Runflag(a2)
;signal to wait for from timer output if output queue full
moveq #-1,d0
CALLEXEC AllocSignal
move.l d0,IVT_Signal(a2) ; <0 ? error, valid are 0..31
blt .error ; error: have to go (shouldn't happen)
moveq #0,d1
bset d0,d1
move.l d1,IVT_SigMask(a2)
suba.l a1,a1
CALLEXEC FindTask
move.l d0,IVT_SigTask(a2)
CALLEXEC CreateMsgPort ;Create MsgPort for timing...
move.l d0,IVT_Port(a2)
beq .error ;0=error
move.l IVT_Port(a2),a0
move.l #IOTV_SIZE,d0
CALLEXEC CreateIORequest
move.l d0,IVT_IORequest(a2)
beq .error ;0=error
lea.l IVT_Int(a2),a0
lea _InterruptIntervalTimer(pc),a1
move.l a1,IS_CODE(a0)
move.l a2,IS_DATA(a0)
move.b #NT_INTERRUPT,LN_TYPE(a0)
move.b #0,LN_PRI(a0) ;-32,-16,0,16,32
move.l IVT_Port(a2),a1
;move.b #NT_MSGPORT,LN_TYPE(a1)
move.b #PA_SOFTINT,MP_FLAGS(a1)
move.l a0,MP_SIGTASK(a1) ;Softint eintragen
lea VBtimer_name,a0
moveq #UNIT_MICROHZ,d0
move.l IVT_IORequest(a2),a1
moveq #0,d1
CALLEXEC OpenDevice
tst.l d0
beq.s .ok
moveq #0,d0
bra.s .error
.ok ;OK, timer device is ready
st IVT_Init(a2)
moveq #1,d0 ;OK
.error
movem.l (sp)+,d1-a6
;ret 0 <= err, >0 = ok
rts
_ExitIntervalTimer:
;stop timer.device
movem.l d0-a6,-(sp)
move.l a1,a2
sf IVT_Init(a2)
move.l IVT_IORequest(a2),d5
beq.s .noIO
tst.b IVT_Runflag(a2)
beq.s .noAbort
st IVT_Stopflag(a2)
ifne 0
move.l d5,a1
CALLEXEC WaitIO
else
move.l d5,a1
move.l IO_DEVICE(a1),a6
jsr DEV_ABORTIO(A6) ;clear pending requests
endc
.noAbort:
move.l d5,a1
CALLEXEC CloseDevice
move.l d5,a0
CALLEXEC DeleteIORequest
clr.l IVT_IORequest(a2)
.noIO:
move.l IVT_Port(a2),d0
beq.s .noPort
move.l d0,a0
CALLEXEC DeleteMsgPort
clr.l IVT_Port(a2)
.noPort:
move.l IVT_Signal(a2),d0
not.l d0 ;if( d0 == -1 ) d0 = 0
beq.s .nosig
not.l d0 ; swap back
CALLEXEC FreeSignal
moveq #-1,d0
move.l d0,IVT_Signal(a2)
.nosig:
movem.l (sp)+,d0-a6
rts
; input:
; A1 = IVT Structure (after init)
; D1 = Number of Microseconds
_StartIntervalTimer:
movem.l d0/a1/a2/a6,-(Sp)
move.l a1,a2
move.l d1,IVT_Interval(A2)
sf IVT_Stopflag(a2)
tst.b IVT_Runflag(a2) ;running already ? -> keep it running
bne.s .notimer
move.l a2,a1
bsr _RestartIntervalTimer
.notimer
movem.l (sp)+,d0/a1/a2/a6
rts
; Non-Public
; A1 - IVT Structure
_RestartIntervalTimer:
movem.l d0/a1/a2/a6,-(sp)
move.l a1,a2
move.l IVT_IORequest(a2),d0
beq.s .notimer
move.l d0,a1
move.w #TR_ADDREQUEST,IO_COMMAND(a1)
clr.b IO_FLAGS(a1)
clr.l IOTV_TIME+EV_HI(a1)
move.l IVT_Interval(A2),IOTV_TIME+EV_LO(a1)
move.l IO_DEVICE(a1),a6
jsr DEV_BEGINIO(A6)
st IVT_Runflag(a2)
.notimer
movem.l (sp)+,d0/a1/a2/a6
rts
_StopIntervalTimer:
movem.l d0-a6,-(Sp)
move.l a1,a2
st IVT_Stopflag(a2)
tst.b IVT_Runflag(a2)
beq.s .noIO
move.l IVT_IORequest(a2),d5
beq.s .noIO
move.l d5,a1
move.l IO_DEVICE(a1),a6
jsr DEV_ABORTIO(A6) ;clear pending requests
sf IVT_Runflag(a2)
.noIO:
movem.l (sp)+,d0-a6
rts
;section data,data
dosbase: dc.l 0
stdout: dc.l 0
timerbase: ds.b IVT_Size
VBtimer_name: dc.b "timer.device",0
ifne DO_TEST
dos_name: dc.b "dos.library",0
succname: dc.b "success: timer worked",10,0
failname: dc.b "failure: timer didn't work",10,0
failtimer: dc.b "timer open failure",10,0
ENDC ;DO_TEST
END
Driver/baxnet/source/sdnet/intervaltimer.h
-57
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@@ -1,57 +0,0 @@
/*
******************************************************************************
* Name: intervaltimer.h *
* Date: $Date: 2016-12-18 22:20:04 +0100 (So, 18. Dez 2016) $ *
* Authors: Henryk Richter *
******************************************************************************
*/
#ifndef _INC_INTERVALTIMER_H
#define _INC_INTERVALTIMER_H
#include <exec/memory.h>
#include <exec/interrupts.h>
#include <exec/tasks.h>
#include <exec/ports.h>
#include <devices/timer.h>
struct IVT_TimerStruct {
unsigned long IVT_Interval;
long IVT_Signal;
unsigned long IVT_SigMask;
struct Task *IVT_SigTask;
struct MsgPort *IVT_Port;
struct IORequest *IVT_IORequest;
struct Device *IVT_Device;
struct Interrupt IVT_Int;
unsigned char IVT_Init;
unsigned char IVT_Runflag;
unsigned char IVT_Stopflag;
unsigned char IVT_Unused;
unsigned long IVT_Counter;
};
#if 1
#include "compiler.h"
#else
/* self-contained in here as well */
#ifdef __SASC
#define ASM __asm
#define ASMR(x) register __ ## x
#define ASMREG(x)
#define SAVEDS __saveds
#else
#define ASM
#define ASMR(x) register
#define ASMREG(x) __asm("" #x "")
#define SAVEDS __saveds
#endif
#endif
ASM SAVEDS int InitIntervalTimer( ASMR(a1) struct IVT_TimerStruct* IntervalTimer ASMREG(a1) );
ASM SAVEDS int StartIntervalTimer( ASMR(a1) struct IVT_TimerStruct* IntervalTimer ASMREG(a1),
ASMR(d1) unsigned long Microsecs ASMREG(d1) );
ASM SAVEDS int StopIntervalTimer( ASMR(a1) struct IVT_TimerStruct* IntervalTimer ASMREG(a1) );
ASM SAVEDS int ExitIntervalTimer( ASMR(a1) struct IVT_TimerStruct* IntervalTimer ASMREG(a1) );
#endif /* _INC_INTERVALTIMER_H */
Driver/baxnet/source/sdnet/intervaltimer.i
-27
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@@ -1,27 +0,0 @@
******************************************************************************
* Name: intervaltimer.i *
* Date: $Date: 2016-12-18 22:20:04 +0100 (So, 18. Dez 2016) $ *
* Authors: Henryk Richter *
******************************************************************************
ifnd _INC_INTERVALTIMER_I
_INC_INTERVALTIMER_I EQU 1
include exec/types.i
STRUCTURE IVT_TimerStruct,0
ULONG IVT_Interval ;<1e6 in microseconds
LONG IVT_Signal ;Signal that is sent back to task from interrupt
ULONG IVT_SigMask ;signal mask
APTR IVT_SigTask ;Task that is signaled
APTR IVT_Port
APTR IVT_IORequest
APTR IVT_Device
STRUCT IVT_Int,IS_SIZE ;
BYTE IVT_Init ; !=0 - initialized
BYTE IVT_Runflag ; current status ( !=0 = running )
BYTE IVT_Stopflag ; stop request if != 0
BYTE IVT_Unused ;
ULONG IVT_Counter ; Counter (statistics)
LABEL IVT_Size
endc ;_INC_TIMERTEST_I
Driver/baxnet/source/sdnet/sdnettest.c
-679
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@@ -1,679 +0,0 @@
/*
test program for SDNet
author: Henryk Richter <henryk.richter@gmx.net>
Runs a number of essential operations on ENC28J60
modules connected to the SD slot of Vampire V2
(500/600) cards.
*/
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <exec/exec.h>
#include <dos/dos.h>
#include <clib/macros.h>
#include <proto/dos.h>
#include <proto/exec.h>
#include "enc28j60.h"
#include "enc28j60l.h" /* import lowlevel asm functions */
/* #include "crc32.h" */
#include "vampuuid.h"
/*#define __NOLIBBASE__*/
#include <proto/vampire.h>
#include <vampire/vampire.h>
#define INVALID_SDNET_UNIT 0x33
/* delay after changing SPI speed in us */
#define SPEED_DELAY 120
struct Library *VampireBase;
/* */
/*u08 myprog = "sdnettest";*/
/* OUI = Commodore :-) */
u08 macaddr[6] = { 0x00,0x80,0x10,0x0b,0x0a,0xff };
#if 1
#define testlen 300
/* issue a DHCP request to increase the likelihood of received frames throughout the test */
u08 testframe[testlen] = {
/* Ethernet(14) */
0xff,0xff,0xff,0xff,0xff,0xff, /* broadcast */
0x00,0x80,0x10,0x0b,0x0a,0xff, /* own MAC */
0x08,0x00, /* Type IPv4 */
/* IPv4(20) */
/* IPv4 */
0x45,0x00, /* VER/IHL, DSCP */
0x01,0x1e, /* was 0d */ /* length 273 = 245+20 */
0xA0,0x0A, /* id */
0x00,0x00, /* flags, fragment offset */
0xff, /* TTL (255 for DHCP) */
0x11, /* UDP */
0x00,0x00, /* header checksum */
0,0,0,0, /* SRC IP */
255,255,255,255,/* dest IP */
/* UDP(8) */
/* UDP */
0x00,0x44, /* src port 68 */
0x00,0x43, /* dest port 67 */
0x01,0x0a, /* length including UDP header FIXME: CHANGE when payload changes */
0x00,0x00, /* checksum */
/* BOOTP(245) */
/* BOOTP/DHCP */
0x01, /* BOOT Request */
0x01, /* HW Type Ethernet */
0x06, /* HW Address length */
0x00, /* hops */
0xde,0xad,0xbe,0xef, /* transaction ID */
0x00,0x02, /* seconds elapsed */
/* mandatory bootp stuff */
0x00,0x00, /* flags */
0x00,0x00,0x00,0x00, /* client IP */
0x00,0x00,0x00,0x00, /* next server IP */
0x00,0x00,0x00,0x00, /* relay agent IP */
0x00,0x00,0x00,0x00, /* some more stuff */
0x00,0x80,0x10,0x0b,0x0a,0xff, /* own MAC */
0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00, /* 10 bytes padding */
/* server name (64x0) */
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
/* boot file name (128x0) */
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
/* DHCP magic cookie */
0x63,0x82,0x53,0x63,
/* DHCP options */
0x35,0x01,0x01, /* DHCP discover */
0x37,0x04,0x01,0x03,0x06,0x0f, /* we want mask,router,DNS,Domain Name */
0x3d,0x06, /* client identifier (3c would be vendor class) */
0,
's','d','n','e','t',
0xff, /* end */
/* padding */
/* 0x00,0x00,0x00 */
};
#else
#define testlen 98
u08 testframe[testlen] = {
0xff,0xff,0xff,0xff,0xff,0xff, /* broadcast */
0x00,0x80,0x10,0x0b,0x0a,0xff, /* own MAC */
0x08,0x00, /* Type IPv4 */
/* */
0x45,0x00, /* VER, DSCP */
0x00,0x54, /* length */
0xA0,0x0A, /* id */
0x00,0x00, /* flags, fragment offset */
0x40, /* TTL */
0x01, /* ICMP */
0x00,0x00, /* header checksum */
192,168,10,11, /* SRC IP */
192,168,10,255,/* dest IP */
/* */
0x08,0x00, /* Type, Code = ICMP Echo */
0x00,0x00, /* Checksum */
0xDE,0xAD, /* Identifier */
0x00,0x01, /* SeqNum */
0x41,0x41,0x41,0x41,0x41,0x41,0x41,0x41,
0x41,0x41,0x41,0x41,0x41,0x41,0x41,0x41,
0x41,0x41,0x41,0x41,0x41,0x41,0x41,0x41,
0x41,0x41,0x41,0x41,0x41,0x41,0x41,0x41,
0x41,0x41,0x41,0x41,0x41,0x41,0x41,0x41,
0x41,0x41,0x41,0x41,0x41,0x41,0x41,0x41,
0x41,0x41,0x41,0x41,0x41,0x41,0x41,0x41,
}; /* 98 Bytes */
#endif
unsigned char recvbuf[1530];
ULONG vres = (ULONG)-1;
ULONG doquit = 0;
u16 ip_checksum( u08 *, LONG );
u16 udp_checksum( u08 *, LONG );
/* SAS/C abort override */
int CXBRK(void )
{
/* doquit = 1; */
return 0;
}
void __regargs __chkabort(void);
void __regargs __chkabort(void)
{
if( SetSignal( 0, SIGBREAKF_CTRL_C ) & SIGBREAKF_CTRL_C )
{
doquit = 1;
printf("got ctrl-c\n");
}
}
/*
global cleanup
*/
void cleanup(void)
{
if( VampireBase )
V_FreeExpansionPort( vres );
printf("cleaning up\n");
}
/*
communications test: try different clock dividers and poll revision
*/
ULONG sdnt_commtest( void )
{
ULONG ret = 0; /* def: fail */
int speed = 10; /* try different SPI clock dividers */
int wait;
u08 rev,rdy=0;
/* soft reset cpu */
enc28j60_SetSPISpeed( (ULONG)speed );
enc28j60l_UMinDelay( SPEED_DELAY ); /* wait a little, */
enc28j60l_WriteOp(ENC28J60_SOFT_RESET, 0, ENC28J60_SOFT_RESET);
/* enc28j60l_WriteOp(ENC28J60_SOFT_RESET, 0, ENC28J60_SOFT_RESET);
enc28j60l_WriteOp(ENC28J60_SOFT_RESET, 0, ENC28J60_SOFT_RESET);
enc28j60l_WriteOp(ENC28J60_SOFT_RESET, 0, ENC28J60_SOFT_RESET);*/
enc28j60l_UMinDelay( 4000 ); /* wait 4ms */
wait = 0xfff;
while( wait-- > 0 )
{
rdy = ESTAT_CLKRDY & enc28j60l_ReadOp(ENC28J60_READ_CTRL_REG, ESTAT );
if( rdy )
wait = 0;
}
enc28j60l_UMinDelay( 20 ); /* wait a little, */
if( !rdy )
{
printf("Fail. Chip doesn`t respond ready.\n");
}
else
{
rdy = enc28j60l_ReadRegByte(EREVID);
if( rdy > 5 ) rdy++;
}
while( speed >= 0 )
{
enc28j60_SetSPISpeed( (ULONG)speed );
enc28j60l_UMinDelay( SPEED_DELAY ); /* wait a little, */
enc28j60l_ReadRegByte(EREVID);
rev = enc28j60l_ReadRegByte(EREVID);
if( rev > 5 ) rev++;
if( rdy ) /* best case: chip reported "ready" */
{
if( rev != rdy )
{
if( speed >= 2 )
printf("Fail. Different revision register reported by chip (%d vs %d at speed %d)\n",rdy,rev,speed);
else
printf("Note. Speed %d does not work properly with your card (but that was expected)\n",speed);
}
else
{
printf("Ok. Revision %d reported at speed %d\n",rev,speed);
ret |= (1<<speed);
}
}
else /* chip was not "ready" but we`re stubborn */
{
if( (rev > 0) && (rev < 0x10 ) )
{
printf("OK. got Chip rev %d at speed %d\n",rev,speed);
ret |= (1<<speed);
}
else
printf("Fail. Cannot read chip rev at speed %d\n",speed);
}
speed--;
}
if( !ret )
{
printf("Fail. No response from revision command,\n");
printf(" Check ENC28J60 power supply and cabling.\n");
}
else printf("Ok. Speed success mask %x\n",ret );
return ret;
}
/*
communications test: try different clock dividers and copy memory forth and back
input: bit mask of clock dividers to test (between 0 and 31)
*/
#define TXSTART_INIT 0x1A00 /* start of TX buffer, room for 1 packet */
#define TXSTOP_INIT 0x1FFF /* end of TX buffer */
ULONG sdnt_memtest( ULONG speeds, ULONG testsize )
{
u08 *membuf;
int i,j,res;
membuf = AllocVec( testsize*2, MEMF_ANY );
if( !membuf )
{
printf("Fail. Cannot allocate %d Bytes Memory\n",testsize*2);
return 0;
}
/*
fill buffer with something nonzero
*/
for( i=0 ; i < testsize ; i++ )
{
membuf[i] = (u08)( i ^ 0x5a );
}
/* try different speeds */
for( i=31; i >= 0 ; i-- )
{
if( speeds & (1<<i) )
{
enc28j60_SetSPISpeed( (ULONG)i );
enc28j60l_ReadRegByte(EREVID); /* safety */
enc28j60l_UMinDelay( SPEED_DELAY ); /* wait 2 ms */
enc28j60l_ReadRegByte(EREVID);
enc28j60l_WriteBuffer(membuf,(int)testsize,TXSTART_INIT);
/* enc28j60l_WriteReg( ERXRDPT, TXSTART_INIT ); */
enc28j60l_WriteReg(ERDPT, TXSTART_INIT+1 );
enc28j60l_ReadBuffer( membuf + testsize, (int)testsize );
for( j=0, res=0 ; j < (testsize-1) ; j++ )
{
/*if( membuf[j] != membuf[j+testsize] )
printf("%d vs %d\n",membuf[j], membuf[j+testsize] );*/
res |= ( membuf[j] ^ membuf[j+testsize] );
}
if( res )
{
printf("Fail. Memory transfer failure at speed %d\n",i);
speeds &= ~(1<<i);
}
else
printf("Ok. Memory transfer success at speed %d\n",i);
}
}
FreeVec( membuf );
if( !speeds )
{
printf("Fail. Memory transfer test failed. Couldn`t transfer data successfully.\n");
printf(" Check ENC28J60 power supply and cabling.\n");
}
else printf("Ok. Speed success mask %x\n",speeds );
return speeds;
}
#define TEST_MAC (1<<30)
#define TEST_LINK (1<<31)
#define TEST_TXERR (1<<29)
#define TEST_RXERR (1<<28)
#define TEST_HAVERX (1<<27)
int main( int argc, char **argv)
{
u08 res;
int runs;
int ret = 0;
#ifdef PROTO_V2EXPNET
ULONG portid = V_WIFIPORT;
#else
ULONG portid = V_SDPORT;
#endif
ULONG speeds; /* clock divider mask */
ULONG testres = 0; /* bit 31 is used for link status, bit 30 for correct MAC */
ULONG clockdiv;
printf("starting\n");
atexit( cleanup );
/*
verify vampire.resource presence
*/
if( VampireBase = OpenResource( V_VAMPIRENAME ) )
{
printf("Ok. vampire.resource present\n");
{
APTR allocator = V_AllocExpansionPort( portid, argv[0] );
if( allocator )
{
printf("Fail. Port seems to be allocated already by %s\n",allocator);
printf(" Please shut down your IP stack and try again.\n");
exit(1);
}
vres = portid;
printf("Ok. vampire.resource port %d allocated\n",vres);
}
}
else
{
printf("Fail. vampire.resource not found.\n");
printf(" Please install Vampire Gold 2.7 or later core,\n");
printf(" flash an updated ROM or\n");
printf(" loadmodule vampire.resource\n");
#ifdef PROTO_V2EXPNET
printf("Note. v2expeth.device will NOT work without the resource\n");
#else
printf("Note. sdnet.device will NOT work without the resource\n");
#endif
printf("I`ll continue the test without resource allocation...\n");
}
/*
communications test, try to read HW version
*/
speeds = sdnt_commtest();
if( !speeds )
{
printf("Exiting\n");
ret = 2;
goto end;
}
/*
transfer test from/to HW memory
*/
speeds = sdnt_memtest( speeds, 1536 );
if( !speeds )
{
ret = 3;
goto end;
}
/*
initialize Chip
*/
res = enc28j60_init( macaddr, PIO_INIT_MULTI_CAST|PIO_INIT_BROAD_CAST );
/* res = enc28j60_init( macaddr, PIO_INIT_PROMISC ); */
if( res != PIO_OK )
{
printf("init error %d\n",res);
ret = 4;
goto end;
}
{
u08 readmac[6];
int i,res;
enc28j60_getMAC( readmac );
/*readmac[5]=0;*/
for( i=0,res=0 ; i<6 ; i++ )
res |= ( readmac[i] ^ macaddr[i] );
if(res)
{
printf("Fail. Cannot read correct MAC address back: ");
printf("got %02x.%02x.%02x.%02x.%02x.%02x wanted ",
readmac[0],readmac[1],readmac[2],
readmac[3],readmac[4],readmac[5]);
printf("%02x.%02x.%02x.%02x.%02x.%02x\n",
macaddr[0],macaddr[1],macaddr[2],
macaddr[3],macaddr[4],macaddr[5]);
}
else
{
printf("OK. init success. MAC address configured.\n");
testres |= TEST_MAC;
}
}
{
unsigned char status;
/* we checked the chip rev already... */
/* enc28j60_status( PIO_STATUS_VERSION, &status ); printf("Chip Rev %d ",status); */
enc28j60_status( PIO_STATUS_LINK_UP, &status );
if( status != 1 )
printf("Fail. Link status is %d. Check your Ethernet Switch and cabling.\n",status);
else
{
printf("OK. Link status is %d\n",status);
testres |= TEST_LINK;
}
}
/* set best supported speed */
{
for( clockdiv=0 ; clockdiv < 16 ; clockdiv++ )
{
if( speeds & (1<<clockdiv) )
break;
}
printf(" Setting best speed %d (i.e. fastest working SPI clock divider)\n",clockdiv);
enc28j60_SetSPISpeed( clockdiv );
enc28j60l_UMinDelay( SPEED_DELAY ); /* wait a little, */
}
printf("..... Sending 100 frames and log broadcasts/multicasts (~10 seconds) .....\n");
printf(" (Whether something is received in the next 10 seconds depends\n");
printf(" on which and how many devices are present+active in your network)\n");
runs = 100;
ip_checksum( testframe+14, testlen-14 ); /* only the first 20 bytes are relevant */
udp_checksum( testframe+14, testlen-14 ); /* skip Ethernet header */
while( (runs--) && (!doquit) )
{
#if 1
res = enc28j60_send( testframe, testlen );
if( res != PIO_OK )
{
testres |= TEST_TXERR;
printf("send error %d\n",res);
}
#endif
if(0)
{
unsigned char status;
enc28j60_status( PIO_STATUS_LINK_UP, &status );
printf("Link status is %d\n",status);
}
res = enc28j60_has_recv();
/* printf("%d packets\n",res); */
if( res )
{
unsigned short got_size;
printf("%d packets\n",res);
testres |= TEST_HAVERX;
/* u08 enc28j60_recv(u08 *data, u16 max_size, u16 *got_size) */
res = enc28j60_recv( recvbuf,1520,&got_size);
if( res != PIO_IO_ERR )
{
/* printf("recv res %d\n",res); */
if( got_size )
{
unsigned int type = (((unsigned int)recvbuf[12])<<8) + (unsigned int)recvbuf[13];
if(1)/* if( type != 0x800 ) */
{
printf("%d bytes\n",got_size);
printf("%02x.%02x.%02x.%02x.%02x.%02x (%x)\n",
recvbuf[0],recvbuf[1],recvbuf[2],
recvbuf[3],recvbuf[4],recvbuf[5],
type );
}
}
}
}
#if 0
else
{
enc28j60_dump_regs();
}
#endif
Delay(5);
}
printf("Done. Verdict:\n");
if( testres == ( TEST_HAVERX|TEST_LINK|TEST_MAC ) )
{
#ifdef PROTO_V2EXPNET
printf(" This test determined that your expansion net is quite likely in working shape.\n");
#else
printf(" This test determined that your sdnet is quite likely in working shape.\n");
#endif
}
else
{
if( testres == ( TEST_LINK|TEST_MAC ) )
{
printf(" No reception while testing. Either you`ve got a quiet network or further testing might be needed.\n");
}
else
{
if( testres & (TEST_TXERR|TEST_RXERR) )
printf(" RX/TX problems encountered.\n");
if( !(testres & TEST_LINK) )
printf(" Link is not up\n");
if( !(testres & TEST_MAC) )
printf(" MAC address not set correctly\n");
if( testres & TEST_HAVERX )
printf(" Some problems but at least we received data\n");
}
}
if( clockdiv != 1 )
{
printf("Important: your SDNet device was not working in this test with clockdiv=1.\n");
printf(" Please call\n");
printf(" makedir ENVARC:Sana2\n");
#ifdef PROTO_V2EXPNET
printf(" echo \"SPISPEED=%d\" >ENVARC:sana2/v2expeth.config\n",clockdiv);
#else
printf(" echo \"SPISPEED=%d\" >ENVARC:sana2/sdnet.config\n",clockdiv);
#endif
}
end:
return ret;
}
/* IP header checksum
input: IP header
length (min. 20)
output: checksum (also directly in IP header)
*/
u16 ip_checksum( u08 *buffer, LONG length )
{
ULONG csum = 0;
ULONG words,i;
unsigned short *b2,*b3;
if( length < 20 )
return 0; /* no checksum */
/* IPv4 header */
b2 = (unsigned short*)buffer;
b2[5] = 0;
words = ((ULONG)(buffer[0] & 0xf))<<1; /* IHL, def: 5 (32 bit words) */
/* sum up */
for( i=0,b3=b2 ; i < words ; i++ )
{
csum += *b3++;
}
while( csum > 0xffff )
{
csum = (csum&0xffff)+(csum>>16);
}
csum = (~csum)&0xffff;
b2[5] = csum; /* store checksum */
return (u16)csum;
}
/*
calculate UDP checksum
- buffer supplied should point to IP packet, where src/dest/protocol are filled in
length is in octets, including IPv4 header and UDP header
input: IP packet including UDP header and content
output: checksum (also directly in UDP header)
*/
u16 udp_checksum( u08 *buffer, LONG length )
{
ULONG words,i;
ULONG csum = 0;
unsigned short *b2,*b3;
if( length < 28 )
return 0; /* no checksum */
/* IPv4 pseudoheader (see for UDP length below) */
csum += *((unsigned short*)(&buffer[12])); /* src IP */
csum += *((unsigned short*)(&buffer[14])); /* src IP */
csum += *((unsigned short*)(&buffer[16])); /* dest IP */
csum += *((unsigned short*)(&buffer[18])); /* dest IP */
csum += (ULONG)buffer[9]; /* protocol */
/* location of UDP header */
words = ((ULONG)(buffer[0] & 0xf))<<2; /* IHL, def: 5 (32 bit words) */
b2 = (unsigned short*)(&buffer[words]);
b2[3] = 0; /* clear checksum */
b3 = b2;
csum += b2[2]; /* UDP length */
words = (length-words)>>1; /* total length - IP header */
for( i=0 ; i<words ; i++ )
{
csum += (ULONG)*b2++;
}
if( length & 1 )
{
csum += (ULONG)*b2;
}
while( csum > 0xffff )
{
csum = (csum&0xffff)+(csum>>16);
}
csum = csum^0xffff;
b3[3] = (u16)csum; /* store checksum */
return (u16)csum;
}
Driver/baxnet/source/sdnet/vampuuid.asm
-151
View File
@@ -1,151 +0,0 @@
; ------------------------------------------------------------------------------
; | Flash ROM Read Serial Number |
; | Copyright (c) 2016 APOLLO TEAM |
; | Christoph Höhne, modifications by Henryk Richter |
; ------------------------------------------------------------------------------
FLASH_ID EQU $14 ;cmd=0xAB
LARGE_FLASH_ID EQU $16
FLASH_ADR_W EQU $00DFF1F8
FLASH_ADR_R EQU $00DFF1FA
FLASH_MAGIC EQU $42420000
FLASH_CS EQU $1
FLASH_CSn EQU $0
FLASH_CLK EQU $2
FLASH_CLKn EQU $0
FLASH_MOSI EQU $4
FLASH_MOSIn EQU $0
FLASH_MISO EQU $1
FLASH_MISOn EQU $0
;VAMPIRE_MAGIC EQU ascii "Vamp"
VAMPIRE_MAGIC EQU $56616D70
VAMPIDREG EQU $DFF3FC
V4_ID1 EQU $DFF3F4
V4_ID2 EQU $DFF3F0
BOARDID_V600 EQU 1
BOARDID_V500 EQU 2
BOARDID_V4SA EQU 5
BOARDID_V1200 EQU 6
xdef _vampire_UUID
;-------- Get 64 Bit unique ID --------------------
; Input
; A1 - pointer to 8 Bytes storage
; Output
; D0 = 0 - failure
; >0 - success
_vampire_UUID:
movem.l d1-a6,-(sp) ;lazy register store
lea VAMPIDREG,a0
move.w (a0),d0 ;ID reg empty?
blt.s v2$ ;yes, try flash method
lsr.w #8,d0
cmp.b #BOARDID_V4SA,d0
bne.s v2$
; cmp.w #$2FF,d0 ;Core type << 8 | Clock_Multiplier
; ble.s v2$
move.l V4_ID1-VAMPIDREG(a0),d0
move.l V4_ID2-VAMPIDREG(a0),d1
bra.s common$
v2$
bsr flashreadid
cmpi.b #FLASH_ID,d0
beq.s goodflash$
cmpi.b #LARGE_FLASH_ID,d0
bne.s error$
goodflash$
bsr flashuniqueid
common$
move.l d0,(a1)
move.l d1,4(a1)
moveq #1,d0
bra.s return$
error$:
moveq #0,d0
return$
movem.l (sp)+,d1-a6
rts
; uint8_t flashreadid(void)
; D0
flashreadid:
move.b #$AB,d1
bsr flashbyte
bsr flashbyte
bsr flashbyte
bsr flashbyte
bsr flashbyte
bsr flashdeselect
rts
; uint64_t flashuniqueid(void)
; D0/D1
flashuniqueid:
move.b #$5A,d1
bsr flashbyte
clr d1
bsr flashbyte
clr d1
bsr flashbyte
move.b #$F8,d1
bsr flashbyte
bsr flashbyte
bsr flashbyte
lsl.l #8,d1
bsr flashbyte
lsl.l #8,d1
bsr flashbyte
lsl.l #8,d1
bsr flashbyte
move.l d1,d3
bsr flashbyte
lsl.l #8,d1
bsr flashbyte
lsl.l #8,d1
bsr flashbyte
lsl.l #8,d1
bsr flashbyte
move.l d3,d0
bsr flashdeselect
rts
; void flashselect(void)
;flashselect:
; move.l #FLASH_MAGIC+FLASH_CSn+FLASH_CLKn,d0
; move.l d0,FLASH_ADR_W
; rts
; void flashdeselect(void)
flashdeselect:
move.l #FLASH_MAGIC+FLASH_CS+FLASH_CLK,d3
move.l d3,FLASH_ADR_W
rts
; uint8_t flashbyte(uint8_t)
; D0 D1
flashbyte:
moveq #7,d2
;bsr flashselect
move.l #FLASH_MAGIC+FLASH_CSn+FLASH_CLKn,d0
move.l d0,FLASH_ADR_W
flashbyteloop:
lsl.b #1,d1
scs.b d0
andi.w #FLASH_MOSI,d0
move.l d0,FLASH_ADR_W
ori.w #FLASH_CLK,d0
move.l d0,FLASH_ADR_W
or.w FLASH_ADR_R,d1
dbra d2,flashbyteloop
move.b d1,d0
rts
Driver/baxnet/source/sdnet/vampuuid.h
-24
View File
@@ -1,24 +0,0 @@
/*
vampuuid.h
author: Henryk Richter <henryk.richter@gmx.net>
purpose: Vampire UUID reading prototypes
*/
#ifndef _INC_vampuuid_H
#define _INC_vampuuid_H
#include "compiler.h"
/*
Purpose: Read UUID of Vampire cards
input: buffer - storage for the returned UUID (8 Bytes)
output: success/failure
>0 - all fine, ready to work
<=0 - init problem (codes undefined yet)
*/
ASM SAVEDS int vampire_UUID( ASMR(a1) unsigned char *buffer ASMREG(a1) );
#endif /* __INC_vampuuid_H */
Driver/baxnet/source/server.c
-1185
View File
File diff suppressed because it is too large Load Diff
Driver/baxnet/source/server.h
-65
View File
@@ -1,65 +0,0 @@
/*
server.h
(C) 2018 Henryk Richter <henryk.richter@gmx.net>
Main Dispatcher defs and protos
*/
#ifndef _INC_SERVER_H
#define _INC_SERVER_H
#define ETH_MTU 1500
#define MINPRIORITY -120
#define MAXPRIORITY 120
#define SERR_OK 1
#define SERR_ERROR 0
#define SERR_BUFFER_ERROR -1
#define SERR_TX_ERROR -2
#define SERR_RX_ERROR -3
#if (MAX_UNITS > 1)
#define BOARDLOOP( _a_ ) for _a_
#else
#define BOARDLOOP( _a_ )
#endif
static void MemSet( void *a, ULONG val, ULONG size );
static struct ServerMsg *server_startup(void);
static LONG server_init( DEVBASEP );
static void server_up( DEVBASEP , struct ServerMsg *msg, LONG updown );
static LONG server_shutdown( DEVBASEP );
static LONG server_Config( DEVBASEP );
static LONG server_writequeue( DEVBASEP, ULONG unit );
static LONG server_HandleS2Commands( DEVBASEP );
static LONG server_SendEvent( DEVBASEP, ULONG unit, ULONG evtmask );
LONG server_writeerror( DEVBASEP, ULONG unit, struct IOSana2Req *ioreq, LONG code );
#ifdef EXTERNAL_WRITE_FRAME
LONG write_frame( DEVBASEP, ULONG unit, struct IOSana2Req *ioreq );
#else
//static
LONG write_frame( DEVBASEP, ULONG unit, struct IOSana2Req *ioreq );
#endif
static LONG server_writequeue( DEVBASETYPE*, ULONG );
static LONG server_setOnline( DEVBASETYPE* , ULONG, ULONG );
static void server_setOffline( DEVBASETYPE* , ULONG, ULONG );
static void server_CloseDevice_offline( DEVBASETYPE * );
#define svTermIO(_a_,_b_) ReplyMsg( (struct Message*)_b_)
#define COPYMAC( _d_, _s_ ) \
{\
USHORT *dst = (USHORT*)(_d_);\
USHORT *src = (USHORT*)(_s_);\
*dst++ = *src++;\
*dst++ = *src++;\
*dst = *src;\
}
#endif /* _INC_SERVER_H */
Driver/baxnet/source/smakefile
-170
View File
@@ -1,170 +0,0 @@
###############################################################################
#
# SAS/C Makefile for SDNet and V2EXPETH
#
# author: Henryk Richter <henryk.richter@gmx.net>
#
# tools required:
# working SAS/C installation (sc:, sc:include and sc:netinclude assigned,
# "sc", "smake" and "slink in path)
# vasm in path (vasmm68k_mot)
#
###############################################################################
###############################################################################
# Name, version
#
###############################################################################
#DEVICEVERSION=1
#DEVICEREVISION=95
#DEVICEDATE=08.09.2018
#DEVICEEXTRA=Beta
SUBDIR=sdnet
ASMOBJECTS = $(SUBDIR)/vampuuid.o$(TYPE) $(SUBDIR)/intervaltimer.o$(TYPE) \
$(SUBDIR)/enc28j60.o$(TYPE) $(SUBDIR)/enc28j60l.o$(TYPE)
#
# more than one flavour of the same code base may be build with this setup
#
# some arguments are passed down recursively (example):
#DEVICEID=v2expeth.device
#DEFINES1 = -DPROTO_V2EXPNET
#ASMDEFS = -DPROTO_V2EXPNET
#CPU = 68020
###############################################################################
#
# common.smk (SAS/C variant of common.mk)
#
# author: Henryk Richter <henryk.richter@gmx.net>
#
# note: when switching between different hardware targets, don`t forget
# "make clean" in between
###############################################################################
# debug = 1 will include string debugging for terminal/sushi/sashimi
# not enabled yet in SAS/C makefile
debug = 0
###############################################################################
# prefix for system includes (ASM)
#
###############################################################################
PREFX = sc:
SYSINC = $(PREFX)include
###############################################################################
#
# compiler executables and support calls
#
###############################################################################
RM = delete force quiet
CC = sc
LD = slink
MAKE = smake
CFLAGS = NOVER NOICONS nostackcheck math=standard strmerge strsect=code parameters=regs data=near opt optsize
LDFLAGS = NOICONS SC SD ND
VASM = vasmm68k_mot
VASMFORMAT = -m$(CPU) -Fhunk -nowarn=2064 -quiet -I$(SYSINC)
###############################################################################
#
# paths to the local includes
#
###############################################################################
IPATH =
###############################################################################
#
# compile-level feature definitions
#
###############################################################################
# see all: target for defaults in $(DEFINES)
DEFINES = $(DEFINES1) CPU=$(CPU)
DEFINES = $(DEFINES) DEFINE ALLREADREQS=1
#DEFINES = $(DEFINES) DEFINE DEVICEVERSION=$(DEVICEVERSION)
#DEFINES = $(DEFINES) DEFINE DEVICEREVISION=$(DEVICEREVISION)
#DEFINES = $(DEFINES) DEFINE DEVICEDATE=$(DEVICEDATE)
#DEFINES = $(DEFINES) DEFINE DEVICEEXTRA=$(DEVICEEXTRA)
DEFINES = $(DEFINES) DEFINE NEWSTYLE=1
DEFINES = $(DEFINES) DEFINE HAVE_VERSION_H=1
DEFINES = $(DEFINES) DEFINE DEVICENAME=$(DEVICEID)
ASMDEFS = $(ASMDEFS1)
#-DDEVICEVERSION=$(DEVICEVERSION) -DDEVICEREVISION=$(DEVICEREVISION)
###############################################################################
#
# debug
#
###############################################################################
#ifeq ($(debug),1)
#CFLAGS += -DDEBUG -g
#CFLAGS2 += -DDEBUG -g
#LINKLIBS = -L$(PREFX)/lib -ldebug
#endif
###############################################################################
#
# compiler flags and optimization levels
#
###############################################################################
CFLAGS = $(CFLAGS) INCLUDEDIR="" INCLUDEDIR=$(SUBDIR) $(DEFINES)
###############################################################################
#
# objects to build
#
###############################################################################
# ASM based alternative to deviceheader.o would be romtag.o
OBJECTS = deviceheader.o$(TYPE) deviceinit.o$(TYPE) device.o$(TYPE) \
server.o$(TYPE) $(SUBDIR)/hw.o$(TYPE)
OBJECTS = $(OBJECTS) $(ASMOBJECTS)
BUILDDEPS = device.h server.h hw.h macros.h compiler.h
###############################################################################
#
# rules and commands
#
###############################################################################
.asm.o$(TYPE): $(BUILDDEPS) $*.asm
$(VASM) $(VASMFORMAT) $(ASMDEFS) -o $@ $*.asm
.c.o$(TYPE): $(BUILDDEPS) $*.c
$(CC) $(CFLAGS) OBJECTNAME $@ $*.c
all:
$(MAKE) TYPE=sd sdnet.device DEVICEID=sdnet.device CPU=68020
$(MAKE) TYPE=ex v2expeth.device DEVICEID=v2expeth.device CPU=68020 \
"DEFINES1=DEFINE PROTO_V2EXPNET" ASMDEFS1=-DPROTO_V2EXPNET
sdnet.device: $(OBJECTS)
-$(LD) $(OBJECTS) LIB sc:lib/sc.lib $(LDFLAGS) TO $(DEVICEID)
v2expeth.device: $(OBJECTS)
-$(LD) $(OBJECTS) LIB sc:lib/sc.lib $(LDFLAGS) TO $(DEVICEID)
clean:
-$(RM) sdnet.device v2expeth.device \#?.oex \#?.osd $(SUBDIR)/\#?.oex $(SUBDIR)/\#?.osd
install:
copy sdnet.device v2expeth.device DEVS:Networks
# dependencies
device.o$(TYPE): device.c device.h server.h hw.h macros.h compiler.h
server.o$(TYPE): server.c device.h server.h hw.h macros.h compiler.h
deviceinit.o$(TYPE): deviceinit.c device.h server.h hw.h macros.h compiler.h
deviceheader.o$(TYPE): deviceheader.c device.h server.h hw.h macros.h compiler.h
Driver/baxnet/source/smakefile.enc
-172
View File
@@ -1,172 +0,0 @@
###############################################################################
#
# SAS/C Makefile for ENC624J6net
#
# author: Henryk Richter <henryk.richter@gmx.net>
#
# tools required:
# working SAS/C installation (sc:, sc:include and sc:netinclude assigned,
# "sc", "smake" and "slink in path)
# vasm in path (vasmm68k_mot)
#
# call:
# smake -f smakefile.enc
#
###############################################################################
###############################################################################
# Name, version
#
###############################################################################
#DEVICEVERSION=1
#DEVICEREVISION=95
#DEVICEDATE=08.09.2018
#DEVICEEXTRA=Beta
SUBDIR=enc624j6net
ASMOBJECTS = $(SUBDIR)/enc624j6l.o$(TYPE) $(SUBDIR)/intervaltimer.o$(TYPE)
# more than one flavour of the same code base may be build with this setup
# arguments passed down recursively (example):
#DEVICEID=v2expeth.device
DEFINES1 = DEFINE HW_DMA_TX=1
#DEFINES1 = $(DEFINES1) DEFINE USEMMU=1
ASMDEFS1 = -DHW_DMA_TX=1
#CPU = 68020
###############################################################################
#
# common.smk (SAS/C variant of common.mk)
#
# author: Henryk Richter <henryk.richter@gmx.net>
#
# note: when switching between different hardware targets, don`t forget
# "make clean" in between
###############################################################################
# debug = 1 will include string debugging for terminal/sushi/sashimi
# not enabled yet in SAS/C makefile
#debug = 0
###############################################################################
# prefix for system includes (ASM)
#
###############################################################################
PREFX = sc:
SYSINC = $(PREFX)include
###############################################################################
#
# compiler executables and support calls
#
###############################################################################
RM = delete force quiet
CC = sc
LD = slink
MAKE = smake
CFLAGS = NOVER NOICONS nostackcheck math=standard strmerge strsect=code parameters=regs data=near opt optsize
LDFLAGS = NOICONS SC SD ND
VASM = vasmm68k_mot
VASMFORMAT = -m$(CPU) -Fhunk -nowarn=2064 -quiet -I$(SYSINC)
###############################################################################
#
# paths to the local includes
#
###############################################################################
IPATH =
###############################################################################
#
# compile-level feature definitions
#
###############################################################################
# see all: target for defaults in $(DEFINES)
DEFINES = $(DEFINES1) CPU=$(CPU)
#DEFINES = $(DEFINES) DEFINE DEVICEVERSION=$(DEVICEVERSION)
#DEFINES = $(DEFINES) DEFINE DEVICEREVISION=$(DEVICEREVISION)
#DEFINES = $(DEFINES) DEFINE DEVICEDATE=$(DEVICEDATE)
DEFINES = $(DEFINES) DEFINE NEWSTYLE=1
DEFINES = $(DEFINES) DEFINE HAVE_VERSION_H=1
DEFINES = $(DEFINES) DEFINE DEVICENAME=$(DEVICEID)
#DEFINES = $(DEFINES) DEFINE DEVICEEXTRA=$(DEVICEEXTRA)
ASMDEFS = $(ASMDEFS1)
#-DDEVICEVERSION=$(DEVICEVERSION) -DDEVICEREVISION=$(DEVICEREVISION)
###############################################################################
#
# debug
#
###############################################################################
#ifeq ($(debug),1)
#CFLAGS += -DDEBUG -g
#CFLAGS2 += -DDEBUG -g
#LINKLIBS = -L$(PREFX)/lib -ldebug
#endif
###############################################################################
#
# compiler flags and optimization levels
#
###############################################################################
CFLAGS = $(CFLAGS) INCLUDEDIR="" INCLUDEDIR=$(SUBDIR) $(DEFINES)
###############################################################################
#
# objects to build
#
###############################################################################
# ASM based alternative to deviceheader.o would be romtag.o
OBJECTS = deviceheader.o$(TYPE) deviceinit.o$(TYPE) device.o$(TYPE) \
server.o$(TYPE) $(SUBDIR)/hw.o$(TYPE) kprintf.o$(TYPE)
OBJECTS = $(OBJECTS) $(ASMOBJECTS)
BUILDDEPS = device.h server.h hw.h macros.h compiler.h
###############################################################################
#
# rules and commands
#
###############################################################################
.asm.o$(TYPE): $(BUILDDEPS) $*.asm
$(VASM) $(VASMFORMAT) $(ASMDEFS) -o $@ $*.asm
.c.o$(TYPE): $(BUILDDEPS) $*.c
$(CC) $(CFLAGS) OBJECTNAME $@ $*.c
all:
$(MAKE) -f smakefile.enc TYPE=20 enc624j6net.device DEVICEID=enc624j6net.device CPU=68020
$(MAKE) -f smakefile.enc TYPE=00 enc624j6net.device_68000 DEVICEID=enc624j6net.device CPU=68000
enc624j6net.device: $(OBJECTS)
-$(LD) $(OBJECTS) LIB sc:lib/sc.lib $(LDFLAGS) TO $(DEVICEID)
enc624j6net.device_68000: $(OBJECTS)
-$(LD) $(OBJECTS) LIB sc:lib/sc.lib $(LDFLAGS) TO $(DEVICEID)_68000
clean:
-$(RM) enc624j6net.device enc624j6net.device_68000 \#?.o00 \#?.o20 $(SUBDIR)/\#?.o00 $(SUBDIR)/\#?.o20
install:
copy enc624j6net.device DEVS:Networks
# dependencies
device.o$(TYPE): device.c device.h server.h hw.h macros.h compiler.h
server.o$(TYPE): server.c device.h server.h hw.h macros.h compiler.h
deviceinit.o$(TYPE): deviceinit.c device.h server.h hw.h macros.h compiler.h
deviceheader.o$(TYPE): deviceheader.c device.h server.h hw.h macros.h compiler.h
Driver/baxnet/source/smakefile.v4
-165
View File
@@ -1,165 +0,0 @@
###############################################################################
#
# SAS/C Makefile for V4 ETH
#
# author: Henryk Richter <henryk.richter@gmx.net>
#
# tools required:
# working SAS/C installation (sc:, sc:include and sc:netinclude assigned,
# "sc", "smake" and "slink in path)
# vasm in path (vasmm68k_mot)
#
###############################################################################
###############################################################################
# Name, version
#
###############################################################################
#DEVICEVERSION=1
#DEVICEREVISION=95
#DEVICEDATE=08.09.2018
#DEVICEEXTRA=Beta
SUBDIR=v4net
ASMOBJECTS = $(SUBDIR)/vampuuid.o$(TYPE) $(SUBDIR)/intervaltimer.o$(TYPE) \
$(SUBDIR)/v4l.o$(TYPE) kprintf.o$(TYPE)
#
# more than one flavour of the same code base may be build with this setup
#
# some arguments are passed down recursively (example):
#DEVICEID=v4net.device
#DEFINES1 = DEFINE HW_DMA_TX=1
#ASMDEFS1 = -DHW_DMA_TX
#CPU = 68020
###############################################################################
#
# common.smk (SAS/C variant of common.mk)
#
# author: Henryk Richter <henryk.richter@gmx.net>
#
# note: when switching between different hardware targets, don`t forget
# "make clean" in between
###############################################################################
# debug = 1 will include string debugging for terminal/sushi/sashimi
# not enabled yet in SAS/C makefile
debug = 0
###############################################################################
# prefix for system includes (ASM)
#
###############################################################################
PREFX = sc:
SYSINC = $(PREFX)include
###############################################################################
#
# compiler executables and support calls
#
###############################################################################
RM = delete force quiet
CC = sc
LD = slink
MAKE = smake
CFLAGS = NOVER NOICONS nostackcheck math=standard strmerge strsect=code parameters=regs data=near opt optsize
LDFLAGS = NOICONS SC SD ND
VASM = vasmm68k_mot
VASMFORMAT = -m$(CPU) -Fhunk -nowarn=2064 -quiet -I$(SYSINC)
###############################################################################
#
# paths to the local includes
#
###############################################################################
IPATH =
###############################################################################
#
# compile-level feature definitions
#
###############################################################################
# see all: target for defaults in $(DEFINES)
DEFINES = $(DEFINES1) CPU=$(CPU)
DEFINES = $(DEFINES) DEFINE ALLREADREQS=1
#DEFINES = $(DEFINES) DEFINE DEVICEVERSION=$(DEVICEVERSION)
#DEFINES = $(DEFINES) DEFINE DEVICEREVISION=$(DEVICEREVISION)
#DEFINES = $(DEFINES) DEFINE DEVICEDATE=$(DEVICEDATE)
#DEFINES = $(DEFINES) DEFINE DEVICEEXTRA=$(DEVICEEXTRA)
DEFINES = $(DEFINES) DEFINE NEWSTYLE=1
DEFINES = $(DEFINES) DEFINE HAVE_VERSION_H=1
DEFINES = $(DEFINES) DEFINE DEVICENAME=$(DEVICEID)
ASMDEFS = $(ASMDEFS1)
#-DDEVICEVERSION=$(DEVICEVERSION) -DDEVICEREVISION=$(DEVICEREVISION)
###############################################################################
#
# debug
#
###############################################################################
#ifeq ($(debug),1)
#CFLAGS += -DDEBUG -g
#CFLAGS2 += -DDEBUG -g
#LINKLIBS = -L$(PREFX)/lib -ldebug
#endif
###############################################################################
#
# compiler flags and optimization levels
#
###############################################################################
CFLAGS = $(CFLAGS) INCLUDEDIR="" INCLUDEDIR=$(SUBDIR) $(DEFINES)
###############################################################################
#
# objects to build
#
###############################################################################
# ASM based alternative to deviceheader.o would be romtag.o
OBJECTS = deviceheader.o$(TYPE) deviceinit.o$(TYPE) device.o$(TYPE) \
server.o$(TYPE) $(SUBDIR)/hw.o$(TYPE)
OBJECTS = $(OBJECTS) $(ASMOBJECTS)
BUILDDEPS = device.h server.h hw.h macros.h compiler.h
###############################################################################
#
# rules and commands
#
###############################################################################
.asm.o$(TYPE): $(BUILDDEPS) $*.asm
$(VASM) $(VASMFORMAT) $(ASMDEFS) -o $@ $*.asm
.c.o$(TYPE): $(BUILDDEPS) $*.c
$(CC) $(CFLAGS) OBJECTNAME $@ $*.c
all:
$(MAKE) -f smakefile.v4 TYPE=4 v4net.device DEVICEID=v4net.device CPU=68020
v4net.device: $(OBJECTS)
-$(LD) $(OBJECTS) LIB sc:lib/sc.lib $(LDFLAGS) TO $(DEVICEID)
clean:
-$(RM) v4net.device \#?.o4 $(SUBDIR)/\#?.o4
install:
copy v4net.device DEVS:Networks
# dependencies
device.o$(TYPE): device.c device.h server.h hw.h macros.h compiler.h
server.o$(TYPE): server.c device.h server.h hw.h macros.h compiler.h
deviceinit.o$(TYPE): deviceinit.c device.h server.h hw.h macros.h compiler.h
deviceheader.o$(TYPE): deviceheader.c device.h server.h hw.h macros.h compiler.h
Driver/baxnet/source/smakefile.vwiz
-169
View File
@@ -1,169 +0,0 @@
###############################################################################
#
# SAS/C Makefile for VWizNet
#
# author: Henryk Richter <henryk.richter@gmx.net>
#
# tools required:
# working SAS/C installation (sc:, sc:include and sc:netinclude assigned,
# "sc", "smake" and "slink in path)
# vasm in path (vasmm68k_mot)
#
###############################################################################
###############################################################################
# Name, version
#
###############################################################################
#DEVICEVERSION=1
#DEVICEREVISION=95
#DEVICEDATE=08.09.2018
#DEVICEEXTRA=Beta
SUBDIR=qwiznet
ASMOBJECTS = $(SUBDIR)/vampuuid.o$(TYPE) $(SUBDIR)/intervaltimer.o$(TYPE) \
$(SUBDIR)/w5500l.o$(TYPE)
#
# more than one flavour of the same code base may be build with this setup
#
# some arguments are passed down recursively (example):
#DEVICEID=vwiznet500ex.device
#DEFINES1 = -DPROTO_V2EXPNET
#ASMDEFS = -DPROTO_V2EXPNET
#CPU = 68020
###############################################################################
#
# common.smk (SAS/C variant of common.mk)
#
# author: Henryk Richter <henryk.richter@gmx.net>
#
# note: when switching between different hardware targets, don`t forget
# "make clean" in between
###############################################################################
# debug = 1 will include string debugging for terminal/sushi/sashimi
# not enabled yet in SAS/C makefile
debug = 0
###############################################################################
# prefix for system includes (ASM)
#
###############################################################################
PREFX = sc:
SYSINC = $(PREFX)include
###############################################################################
#
# compiler executables and support calls
#
###############################################################################
RM = delete force quiet
CC = sc
LD = slink
MAKE = smake
CFLAGS = NOVER NOICONS nostackcheck math=standard strmerge strsect=code parameters=regs data=near opt optsize
LDFLAGS = NOICONS SC SD ND
VASM = vasmm68k_mot
VASMFORMAT = -m$(CPU) -Fhunk -nowarn=2064 -quiet -I$(SYSINC)
###############################################################################
#
# paths to the local includes
#
###############################################################################
IPATH =
###############################################################################
#
# compile-level feature definitions
#
###############################################################################
# see all: target for defaults in $(DEFINES)
DEFINES = $(DEFINES1) CPU=$(CPU)
#DEFINES = $(DEFINES) DEFINE DEVICEVERSION=$(DEVICEVERSION)
#DEFINES = $(DEFINES) DEFINE DEVICEREVISION=$(DEVICEREVISION)
#DEFINES = $(DEFINES) DEFINE DEVICEDATE=$(DEVICEDATE)
DEFINES = $(DEFINES) DEFINE NEWSTYLE=1
DEFINES = $(DEFINES) DEFINE HAVE_VERSION_H=1
DEFINES = $(DEFINES) DEFINE DEVICENAME=$(DEVICEID)
#DEFINES = $(DEFINES) DEFINE DEVICEEXTRA=$(DEVICEEXTRA)
ASMDEFS = $(ASMDEFS1)
#-DDEVICEVERSION=$(DEVICEVERSION) -DDEVICEREVISION=$(DEVICEREVISION)
###############################################################################
#
# debug
#
###############################################################################
#ifeq ($(debug),1)
#CFLAGS += -DDEBUG -g
#CFLAGS2 += -DDEBUG -g
#LINKLIBS = -L$(PREFX)/lib -ldebug
#endif
###############################################################################
#
# compiler flags and optimization levels
#
###############################################################################
CFLAGS = $(CFLAGS) INCLUDEDIR="" INCLUDEDIR=$(SUBDIR) $(DEFINES)
###############################################################################
#
# objects to build
#
###############################################################################
# ASM based alternative to deviceheader.o would be romtag.o
OBJECTS = deviceheader.o$(TYPE) deviceinit.o$(TYPE) device.o$(TYPE) \
server.o$(TYPE) $(SUBDIR)/hw.o$(TYPE)
OBJECTS = $(OBJECTS) $(ASMOBJECTS)
BUILDDEPS = device.h server.h hw.h macros.h compiler.h
###############################################################################
#
# rules and commands
#
###############################################################################
.asm.o$(TYPE): $(BUILDDEPS) $*.asm
$(VASM) $(VASMFORMAT) $(ASMDEFS) -o $@ $*.asm
.c.o$(TYPE): $(BUILDDEPS) $*.c
$(CC) $(CFLAGS) OBJECTNAME $@ $*.c
all:
$(MAKE) -f smakefile.vwiz TYPE=sd vwiznet600sd.device DEVICEID=vwiznet600sd.device CPU=68020
$(MAKE) -f smakefile.vwiz TYPE=ex vwiznet500ex.device DEVICEID=vwiznet500ex.device CPU=68020 \
"DEFINES1=DEFINE PROTO_V2EXPNET" ASMDEFS1=-DPROTO_V2EXPNET
vwiznet600sd.device: $(OBJECTS)
-$(LD) $(OBJECTS) LIB sc:lib/sc.lib $(LDFLAGS) TO $(DEVICEID)
vwiznet500ex.device: $(OBJECTS)
-$(LD) $(OBJECTS) LIB sc:lib/sc.lib $(LDFLAGS) TO $(DEVICEID)
clean:
-$(RM) vwiznet600sd.device vwiznet500ex.device \#?.oex \#?.osd $(SUBDIR)/\#?.oex $(SUBDIR)/\#?.osd
install:
copy vwiznet600sd.device vwiznet500ex.device DEVS:Networks
# dependencies
device.o$(TYPE): device.c device.h server.h hw.h macros.h compiler.h
server.o$(TYPE): server.c device.h server.h hw.h macros.h compiler.h
deviceinit.o$(TYPE): deviceinit.c device.h server.h hw.h macros.h compiler.h
deviceheader.o$(TYPE): deviceheader.c device.h server.h hw.h macros.h compiler.h
Driver/baxnet/source/version.h
-17
View File
@@ -1,17 +0,0 @@
/*
version.h
(C) 2018 Henryk Richter <henryk.richter@gmx.net>
version and date handling
*/
#ifndef _INC_VERSION_H
#define _INC_VERSION_H
#define DEVICEVERSION 2
#define DEVICEREVISION 15
#define DEVICEEXTRA
/* #define DEVICEEXTRA Beta */
#define DEVICEDATE 1.3.26
#endif

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