Commit Graph
79 Commits
Author SHA1 Message Date
MHeinrichs 88cdb9fb52 Fixed reset issue: The initialisation loop must be performed exactly once!
buffered address
2022-03-08 12:25:56 +01:00
MHeinrichs dc65757a8a Fixed Z"-Firmwarebug: fast accelerators fetched the IDE-Information too fast I buffered the databus and hold the datat longer during a read 2022-03-06 00:12:14 +01:00
MHeinrichs 61a36e326f Fiexd Clockport-bug for >68040 2021-07-30 01:13:50 +02:00
MHeinrichs fdde3273e8 Resolved merge mess 2020-10-09 22:02:01 +02:00
MHeinrichs 74dac57258 Merge branch 'master' of https://gitlab.com/MHeinrichs/Zorro-LAN-IDE
# Conflicts:
#	Logic/LAN_IDE_V2/LAN_IDE_CP-Z2v2.vhd
#	Logic/LAN_IDE_V2/LAN_IDE_CP-z2v2.jed
#	Logic/LAN_IDE_V2/LAN_IDE_CP-z3v2.jed
2020-10-09 00:19:11 +02:00
MHeinrichs 8231b54f78 Improved clock startup and IDE-ROM-timing 2020-10-09 00:17:40 +02:00
Henryk Richter 40c53e75b5 Zorro-II firmware update
- fixed clockport addressing
 - changed IDE_OFF jumper handling to actually disable IDE when the jumper is in
2020-07-15 17:45:55 +02:00
MHeinrichs 02c04ac3c5 unified behavior on address decode 2019-11-19 23:41:25 +01:00
Heinrichs, Matthias a7141792f4 Merge branch 'master' into driverupdate2
# Conflicts: (taken: newer version)
#	Driver/baxnet/README.enc
#	Driver/baxnet/bin/enc624j6net.device
#	Driver/baxnet/bin/enc624j6net.device_68000
#	Driver/baxnet/source/Makefile.enc
#	Driver/baxnet/source/device.c
#	Driver/baxnet/source/enc624j6net/enc624j6l.asm
#	Driver/baxnet/source/server.c
#	Driver/baxnet/source/version.h
2019-11-19 14:56:37 +01:00
MHeinrichs d125d49fa6 Updated baxnet-driver ansd Z3-Interface 2019-11-15 00:40:34 +01:00
HenrykRichter 718b7fed44 reverted last Z2 firmware VHDL
- useful in Z2 mode until unified firmare is ready
2019-06-06 15:36:49 +02:00
MHeinrichs 906d8a902f Firmware for new version. IDE and CP working 2019-05-26 22:17:28 +02:00
HenrykRichter 5c8a5c12ed updated pinlist for V2 2019-03-20 17:47:16 +01:00
HenrykRichter 87739da8b8 new jed files for V2 board, untested for now 2019-03-20 17:43:32 +01:00
HenrykRichter ec9088d70d V2 changes:
- moved IRQ6 to Pin 135 in pinlist and VHD files
  - added IDE data lines to Z3 vhd
2019-03-19 16:15:22 +01:00
MHeinrichs ecf2d5bc6b Cleaned sensitivity list 2019-03-08 00:04:06 +01:00
MHeinrichs 7936ad431b CP and LAN working! Clockport needed to be stopped if FCS='1' 2019-03-07 23:53:52 +01:00
MHeinrichs 943507175a toggle-edge-detection for fcs 2019-02-28 22:59:03 +01:00
MHeinrichs 95630fdcf7 fully clocked z3-statemachine for lan without reset-hack 2019-02-27 23:06:45 +01:00
MHeinrichs 8230e4fca2 try for CP in Z3 2019-02-26 21:59:05 +01:00
MHeinrichs 6d4a455d68 im3 2019-02-21 23:52:29 +01:00
MHeinrichs 99f78251cd Intermediate2 2019-02-21 23:41:30 +01:00
MHeinrichs b1854c3f8c intermediate 2019-02-21 14:47:36 +01:00
MHeinrichs 18ab58e394 Z3-LAN working and cp working but not together 2019-02-21 14:31:52 +01:00
MHeinrichs b7e4ec2e1d Z3-config-try 2019-02-21 14:02:45 +01:00
MHeinrichs 5fc99a4460 Z2-Firmware with working CP and LAN 2019-02-21 13:53:40 +01:00
MHeinrichs 11c25fe78d CP working in Z3 and driver update
A fix for int6 is needed for the first proto: Connect SJ1 right with INT6-Pad. But CP and lan are not working with AmiTCP
2019-02-20 23:45:57 +01:00
MHeinrichs 94425362cc Update in Firmware (pure Z2-AC but LAN becomes Z3) and new pcb 2019-02-19 23:01:57 +01:00
MHeinrichs e42f097a6c New driver 2019-01-03 00:43:32 +01:00
MHeinrichs eecd6c8918 IDE and CP working in z2-mode 2019-01-03 00:11:33 +01:00
MHeinrichs d11d1c5b27 Start of reintegration IDE/CP AutoConfig works 2019-01-02 22:12:35 +01:00
MHeinrichs ace45ad182 Working! Use "fit.bat 54 35" 2019-01-02 11:11:42 +01:00
MHeinrichs 1ec3fe8e97 before rollback to z2 to find the databus bug 2019-01-02 00:25:30 +01:00
MHeinrichs 01f5ae13ff New compile with 25MHz 2018-12-19 22:28:14 +01:00
MHeinrichs 00f475fed5 No swap of upper/lower word 2018-12-19 19:01:29 +01:00
MHeinrichs d0da391575 Cacheinhibit must be asserted! 2018-12-19 18:49:12 +01:00
MHeinrichs 20aff1a84f Busspeed tweaked: 6-7MB/s Zorro3-Speed 2018-12-18 22:57:37 +01:00
MHeinrichs a28f930027 Set driver init to 25MHz 2018-12-18 22:30:20 +01:00
MHeinrichs 1f390a5b9e Swapping enabled but freeze lock during driver 2018-12-18 12:13:12 +01:00
MHeinrichs 118d024b37 AC working and swapping disabled
use fit.bat 54 35
2018-12-18 11:59:02 +01:00
MHeinrichs 11a6adca8a Byteswap working 2018-12-18 00:00:58 +01:00
MHeinrichs 8cbd5c7cef Datata access works for fixed base address 2018-12-17 23:56:57 +01:00
MHeinrichs deb69da927 sm cleaned up 2018-12-17 23:03:12 +01:00
MHeinrichs 73899442dc z3 ac is working 2018-12-14 01:28:28 +01:00
MHeinrichs eec9e31a7a Auto stash before merge of "master" and "origin/driverupdate" 2018-11-26 20:34:01 +01:00
MHeinrichs 95bc477444 Switched Driver to baxnet-structure 2018-06-09 21:41:07 +02:00
MHeinrichs b714ded89e Working on Rev2 2018-06-09 12:47:10 +02:00
HenrykRichter c8ff432e7a Logic update
- fix LAN port byte swap with byte writes
  - swap UDS/LDS mapping to WRL/WRL
  - duplicate LAN DQ bytes by re-using ClockPort logic
  - issues:
    - DQ logic doesn't fit in one Function Block anymore
    - some optimization/relaxation might be needed
2018-04-30 08:11:45 +02:00
MHeinrichs 16f86601d9 Tweaked the driver a bit 2018-02-09 00:41:02 +01:00
MHeinrichs 0646520752 A12/13 fix Driver improvement git-ignore cleaned 2018-02-03 17:38:48 +01:00