AC very smart&slim but its not working! WHY????
This commit is contained in:
MHeinrichs
@@ -8,18 +8,12 @@
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<msg type="warning" file="Cpld" num="0" delta="new" >Unable to retrieve the path to the iSE Project Repository. Will use the default filename of '<arg fmt="%s" index="1">LAN_IDE_CP.ise</arg>'.
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</msg>
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<msg type="info" file="Cpld" num="0" delta="new" >Inferring BUFG constraint for signal '<arg fmt="%s" index="1">DQ<5></arg>' based upon the LOC constraint '<arg fmt="%s" index="2">P38</arg>'. It is recommended that you declare this BUFG explicitedly in your design. Note that for certain device families the output of a BUFG constraint can not drive a gated clock, and the BUFG constraint will be ignored.
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</msg>
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<msg type="info" file="Cpld" num="0" delta="new" >Inferring BUFG constraint for signal '<arg fmt="%s" index="1">CLK_EXT</arg>' based upon the LOC constraint '<arg fmt="%s" index="2">P30</arg>'. It is recommended that you declare this BUFG explicitedly in your design. Note that for certain device families the output of a BUFG constraint can not drive a gated clock, and the BUFG constraint will be ignored.
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</msg>
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<msg type="warning" file="Cpld" num="936" delta="old" >The output buffer '<arg fmt="%s" index="1">MTACK_OBUF</arg>' is missing an input and will be deleted.
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</msg>
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<msg type="warning" file="Cpld" num="1007" delta="old" >Removing unused input(s) '<arg fmt="%s" index="1">A<15></arg>'. The input(s) are unused after optimization. Please verify functionality via simulation.
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</msg>
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<msg type="warning" file="Cpld" num="1007" delta="old" >Removing unused input(s) '<arg fmt="%s" index="1">CLK_EXT</arg>'. The input(s) are unused after optimization. Please verify functionality via simulation.
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</msg>
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@@ -32,17 +26,11 @@
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<msg type="warning" file="Cpld" num="1007" delta="old" >Removing unused input(s) '<arg fmt="%s" index="1">FCS</arg>'. The input(s) are unused after optimization. Please verify functionality via simulation.
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</msg>
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<msg type="warning" file="Cpld" num="1007" delta="old" >Removing unused input(s) '<arg fmt="%s" index="1">LAN_INT</arg>'. The input(s) are unused after optimization. Please verify functionality via simulation.
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</msg>
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<msg type="warning" file="Cpld" num="1007" delta="old" >Removing unused input(s) '<arg fmt="%s" index="1">MTCR</arg>'. The input(s) are unused after optimization. Please verify functionality via simulation.
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</msg>
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<msg type="warning" file="Cpld" num="1007" delta="old" >Removing unused input(s) '<arg fmt="%s" index="1">Z3</arg>'. The input(s) are unused after optimization. Please verify functionality via simulation.
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</msg>
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<msg type="warning" file="Cpld" num="1239" delta="new" >The global <arg fmt="%s" index="1">clock</arg> designation (BUFG) on signal '<arg fmt="%s" index="2">N47</arg>' is ignored. Most likely the signal is gated and therefore cannot be used as a global control signal.
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</msg>
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</messages>
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@@ -5,8 +5,5 @@
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behavior or data corruption. It is strongly advised that
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users do not edit the contents of this file. -->
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<messages>
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<msg type="warning" file="NgdBuild" num="470" delta="old" ><arg fmt="%s" index="1">bidirect</arg> pad net '<arg fmt="%s" index="2">A<15></arg>' has no legal driver
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</msg>
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</messages>
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@@ -1,15 +0,0 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<!-- IMPORTANT: This is an internal file that has been generated -->
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<!-- by the Xilinx ISE software. Any direct editing or -->
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<!-- changes made to this file may result in unpredictable -->
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<!-- behavior or data corruption. It is strongly advised that -->
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<!-- users do not edit the contents of this file. -->
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<!-- -->
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<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
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<messages>
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<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.vhd" into library work</arg>
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</msg>
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</messages>
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@@ -5,5 +5,143 @@
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behavior or data corruption. It is strongly advised that
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users do not edit the contents of this file. -->
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<messages>
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<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin 'LAN_INT_ENABLE.CLKF' has multiple original clock nets 'C1' 'C3'
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</msg>
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<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin 'AUTO_CONFIG_DONE<1>.CLKF' has multiple original clock nets 'C1' 'C3'
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</msg>
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<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin 'AUTO_CONFIG_DONE<0>.CLKF' has multiple original clock nets 'C1' 'C3'
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</msg>
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<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin 'AUTO_CONFIG_DONE_CYCLE<0>.CLKF' has multiple original clock nets 'C1' 'C3'
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</msg>
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<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin 'AUTO_CONFIG_DONE_CYCLE<1>.CLKF' has multiple original clock nets 'C1' 'C3'
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</msg>
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<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin 'SHUT_UP<0>.CLKF' has multiple original clock nets 'C1' 'C3'
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</msg>
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<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin 'SHUT_UP<1>.CLKF' has multiple original clock nets 'C1' 'C3'
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</msg>
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<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin 'SHUT_UP<2>.CLKF' has multiple original clock nets 'C1' 'C3'
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</msg>
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<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin 'IDE_ENABLE.CLKF' has multiple original clock nets 'C1' 'C3'
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</msg>
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<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin 'CP_BASEADR<0>.CLKF' has multiple original clock nets 'C1' 'C3'
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</msg>
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<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin 'CP_BASEADR<1>.CLKF' has multiple original clock nets 'C1' 'C3'
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</msg>
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<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin 'CP_BASEADR<2>.CLKF' has multiple original clock nets 'C1' 'C3'
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</msg>
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<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin 'CP_BASEADR<3>.CLKF' has multiple original clock nets 'C1' 'C3'
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</msg>
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<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin 'CP_BASEADR<4>.CLKF' has multiple original clock nets 'C1' 'C3'
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</msg>
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<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin 'CP_BASEADR<5>.CLKF' has multiple original clock nets 'C1' 'C3'
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</msg>
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<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin 'CP_BASEADR<6>.CLKF' has multiple original clock nets 'C1' 'C3'
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</msg>
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<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin 'CP_BASEADR<7>.CLKF' has multiple original clock nets 'C1' 'C3'
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</msg>
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<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin 'Dout1<0>.CLKF' has multiple original clock nets 'C1' 'C3'
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</msg>
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<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin 'Dout1<1>.CLKF' has multiple original clock nets 'C1' 'C3'
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</msg>
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<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin 'Dout1<2>.CLKF' has multiple original clock nets 'C1' 'C3'
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</msg>
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<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin 'Dout1<3>.CLKF' has multiple original clock nets 'C1' 'C3'
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</msg>
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<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin 'IDE_BASEADR<0>.CLKF' has multiple original clock nets 'C1' 'C3'
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</msg>
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<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin 'IDE_BASEADR<1>.CLKF' has multiple original clock nets 'C1' 'C3'
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</msg>
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<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin 'IDE_BASEADR<2>.CLKF' has multiple original clock nets 'C1' 'C3'
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</msg>
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<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin 'IDE_BASEADR<3>.CLKF' has multiple original clock nets 'C1' 'C3'
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</msg>
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<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin 'IDE_BASEADR<4>.CLKF' has multiple original clock nets 'C1' 'C3'
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</msg>
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<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin 'IDE_BASEADR<5>.CLKF' has multiple original clock nets 'C1' 'C3'
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</msg>
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<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin 'IDE_BASEADR<6>.CLKF' has multiple original clock nets 'C1' 'C3'
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</msg>
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<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin 'IDE_BASEADR<7>.CLKF' has multiple original clock nets 'C1' 'C3'
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</msg>
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<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin 'LAN_BASEADR<0>.CLKF' has multiple original clock nets 'C1' 'C3'
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</msg>
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<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin 'LAN_BASEADR<1>.CLKF' has multiple original clock nets 'C1' 'C3'
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</msg>
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<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin 'LAN_BASEADR<2>.CLKF' has multiple original clock nets 'C1' 'C3'
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</msg>
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<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin 'LAN_BASEADR<3>.CLKF' has multiple original clock nets 'C1' 'C3'
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</msg>
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<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin 'LAN_BASEADR<4>.CLKF' has multiple original clock nets 'C1' 'C3'
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</msg>
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<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin 'LAN_BASEADR<5>.CLKF' has multiple original clock nets 'C1' 'C3'
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</msg>
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<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin 'LAN_BASEADR<6>.CLKF' has multiple original clock nets 'C1' 'C3'
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</msg>
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<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin 'LAN_BASEADR<7>.CLKF' has multiple original clock nets 'C1' 'C3'
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</msg>
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<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin 'DS_D.CLKF' has multiple original clock nets 'C1' 'C3'
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</msg>
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<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin 'CP_RD_S.CLKF' has multiple original clock nets 'C1' 'C3'
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</msg>
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<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin 'CP_WE_S.CLKF' has multiple original clock nets 'C1' 'C3'
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</msg>
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<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin 'IDE_R_S.CLKF' has multiple original clock nets 'C1' 'C3'
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</msg>
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<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin 'IDE_W_S.CLKF' has multiple original clock nets 'C1' 'C3'
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</msg>
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<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin 'LAN_RD_S.CLKF' has multiple original clock nets 'C1' 'C3'
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</msg>
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<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin 'LAN_WRH_S.CLKF' has multiple original clock nets 'C1' 'C3'
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</msg>
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<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin 'LAN_WRL_S.CLKF' has multiple original clock nets 'C1' 'C3'
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</msg>
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<msg type="warning" file="Cpld" num="0" delta="new" >Possible asynchronous logic: Clock pin 'ROM_OE_S.CLKF' has multiple original clock nets 'C1' 'C3'
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</msg>
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</messages>
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@@ -5,43 +5,38 @@
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behavior or data corruption. It is strongly advised that
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users do not edit the contents of this file. -->
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||||
<messages>
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||||
<msg type="warning" file="Xst" num="647" delta="old" >Input <<arg fmt="%s" index="1">DS0</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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<msg type="warning" file="Xst" num="819" delta="new" >"<arg fmt="%s" index="1">C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.vhd</arg>" line <arg fmt="%d" index="2">131</arg>: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
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<arg fmt="%s" index="3"><AS></arg>
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</msg>
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<msg type="warning" file="Xst" num="647" delta="old" >Input <<arg fmt="%s" index="1">DS1</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">DS0</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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</msg>
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<msg type="warning" file="Xst" num="647" delta="old" >Input <<arg fmt="%s" index="1">FCS</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">DS1</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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</msg>
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<msg type="warning" file="Xst" num="1306" delta="old" >Output <<arg fmt="%s" index="1">MTACK</arg>> is never assigned.
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<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">FCS</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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</msg>
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<msg type="warning" file="Xst" num="647" delta="old" >Input <<arg fmt="%s" index="1">LAN_INT</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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<msg type="warning" file="Xst" num="1306" delta="new" >Output <<arg fmt="%s" index="1">MTACK</arg>> is never assigned.
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</msg>
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<msg type="warning" file="Xst" num="2565" delta="old" >Inout <<arg fmt="%s" index="1">A<15></arg>> is never assigned.
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<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">Z3</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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</msg>
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<msg type="warning" file="Xst" num="647" delta="old" >Input <<arg fmt="%s" index="1">Z3</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">CLK_EXT</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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</msg>
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<msg type="warning" file="Xst" num="647" delta="old" >Input <<arg fmt="%s" index="1">CLK_EXT</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">MTCR</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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</msg>
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<msg type="warning" file="Xst" num="647" delta="old" >Input <<arg fmt="%s" index="1">MTCR</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">LAN_INT_D0</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
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</msg>
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<msg type="warning" file="Xst" num="1780" delta="old" >Signal <<arg fmt="%s" index="1">LAN_INT_ENABLE</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
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<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">DTACK_S</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
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</msg>
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<msg type="warning" file="Xst" num="1780" delta="old" >Signal <<arg fmt="%s" index="1">LAN_INT_D0</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
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</msg>
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<msg type="warning" file="Xst" num="1780" delta="old" >Signal <<arg fmt="%s" index="1">DTACK_S</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
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</msg>
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<msg type="warning" file="Xst" num="1780" delta="old" >Signal <<arg fmt="%s" index="1">AS_D</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
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<msg type="info" file="Xst" num="1767" delta="new" >HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.
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</msg>
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</messages>
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||||
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Reference in New Issue
Block a user