Logic update
- fix LAN port byte swap with byte writes
- swap UDS/LDS mapping to WRL/WRL
- duplicate LAN DQ bytes by re-using ClockPort logic
- issues:
- DQ logic doesn't fit in one Function Block anymore
- some optimization/relaxation might be needed
This commit is contained in:
+1338
-1338
File diff suppressed because it is too large
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@@ -16,6 +16,8 @@
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-- Revision 0.01 - File Created
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-- Revision 0.01 - File Created
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-- Additional Comments:
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-- Additional Comments:
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--
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--
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-- directory cleanup hint:
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-- svn status|grep ^M|sed "s/^M [\t ]*//"|xargs rm
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----------------------------------------------------------------------------------
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----------------------------------------------------------------------------------
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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@@ -92,6 +94,7 @@ architecture Behavioral of LAN_IDE_CP is
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);
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);
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SIGNAL LAN_RST_SM: lan_reset :=nop;
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SIGNAL LAN_RST_SM: lan_reset :=nop;
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SIGNAL lancp: STD_LOGIC; -- LAN or ClockPort
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SIGNAL ide: STD_LOGIC;
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SIGNAL ide: STD_LOGIC;
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SIGNAL autoconfig: STD_LOGIC;
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SIGNAL autoconfig: STD_LOGIC;
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SIGNAL lan_adr: STD_LOGIC;
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SIGNAL lan_adr: STD_LOGIC;
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@@ -200,6 +203,7 @@ begin
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lan_adr <= '0';
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lan_adr <= '0';
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lan_adr_sw <= '0';
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lan_adr_sw <= '0';
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cp <= '0';
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cp <= '0';
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lancp <= '0';
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elsif(falling_edge(AS))then
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elsif(falling_edge(AS))then
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--default values
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--default values
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autoconfig <= '0';
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autoconfig <= '0';
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@@ -207,6 +211,7 @@ begin
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lan_adr <= '0';
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lan_adr <= '0';
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lan_adr_sw <= '0';
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lan_adr_sw <= '0';
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cp <= '0';
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cp <= '0';
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lancp <= '0';
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if(A(23 downto 16) = x"E8" and AUTO_CONFIG_DONE < "11" and CFIN='0')then
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if(A(23 downto 16) = x"E8" and AUTO_CONFIG_DONE < "11" and CFIN='0')then
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autoconfig <= '1';
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autoconfig <= '1';
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elsif(A(23 downto 16) = LAN_BASEADR and SHUT_UP(0)='0' )then
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elsif(A(23 downto 16) = LAN_BASEADR and SHUT_UP(0)='0' )then
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@@ -214,8 +219,10 @@ begin
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lan_adr_sw <= '1';
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lan_adr_sw <= '1';
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end if;
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end if;
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lan_adr <= '1';
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lan_adr <= '1';
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lancp <= '1';
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elsif(A(23 downto 16) = CP_BASEADR and SHUT_UP(1)='0')then
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elsif(A(23 downto 16) = CP_BASEADR and SHUT_UP(1)='0')then
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cp <= '1';
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cp <= '1';
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lancp <= '1';
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elsif(A(23 downto 16) = IDE_BASEADR and SHUT_UP(2)='0')then
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elsif(A(23 downto 16) = IDE_BASEADR and SHUT_UP(2)='0')then
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ide <= '1';
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ide <= '1';
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end if;
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end if;
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@@ -256,8 +263,9 @@ begin
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if(lan_adr='1' and DS='0' and A(15)='0')then
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if(lan_adr='1' and DS='0' and A(15)='0')then
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LAN_RD_S <= RW;
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LAN_RD_S <= RW;
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LAN_WRH_S <= not UDS and not RW;
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-- swapped LDS/UDS here: ENC624 is little endian
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LAN_WRL_S <= not LDS and not RW;
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LAN_WRH_S <= not LDS and not RW;
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LAN_WRL_S <= not UDS and not RW;
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end if;
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end if;
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end if;
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end if;
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end process lan_rw_gen;
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end process lan_rw_gen;
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@@ -442,13 +450,13 @@ begin
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Dout1 & x"FFF" when RW='1' and autoconfig ='1' and AS='0' else
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Dout1 & x"FFF" when RW='1' and autoconfig ='1' and AS='0' else
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(others => 'Z');
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(others => 'Z');
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--defined lancp signal that matches both LAN and CP addresses
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DQ <= LAN_D_CLR when (LAN_RST_SM = wait0 or LAN_RST_SM = clr or LAN_RST_SM = clr_commit) else
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DQ <= LAN_D_CLR when (LAN_RST_SM = wait0 or LAN_RST_SM = clr or LAN_RST_SM = clr_commit) else
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LAN_D_SET when (LAN_RST_SM = wait1 or LAN_RST_SM = set or LAN_RST_SM = set_commit) else
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LAN_D_SET when (LAN_RST_SM = wait1 or LAN_RST_SM = set or LAN_RST_SM = set_commit) else
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D when RW='0' and AS='0' and lan_adr ='1' and lan_adr_sw ='0' else
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D( 7 downto 0) & D( 7 downto 0) when RW='0' and AS='0' and lancp = '1' and LDS='0' and UDS='1' else
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D(15 downto 8) & D(15 downto 8) when RW='0' and AS='0' and lancp = '1' and LDS='1' and UDS='0' else
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D( 7 downto 0) & D(15 downto 8) when RW='0' and AS='0' and lan_adr ='1' and lan_adr_sw ='1' else
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D( 7 downto 0) & D(15 downto 8) when RW='0' and AS='0' and lan_adr ='1' and lan_adr_sw ='1' else
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D when RW='0' and AS='0' and cp = '1' and LDS='0' and UDS='0' else
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D when RW='0' and AS='0' and lancp ='1'
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D( 7 downto 0) & D( 7 downto 0) when RW='0' and AS='0' and cp = '1' and LDS='0' and UDS='1' else
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D(15 downto 8) & D(15 downto 8) when RW='0' and AS='0' and cp = '1' and LDS='1' and UDS='0'
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else (others => 'Z');
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else (others => 'Z');
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IDE_W <= IDE_W_S when AS='0' else '1';
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IDE_W <= IDE_W_S when AS='0' else '1';
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