Update in Firmware (pure Z2-AC but LAN becomes Z3) and new pcb
This commit is contained in:
MHeinrichs
@@ -2,8 +2,9 @@ ENC624J6Net - A SANA-II driver for the Scratze card
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ENC624J6Net Copyright (C) 2018 Henryk Richter <henryk.richter@gmx.net>
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This driver is supposed to support ENC624J600 based ethernet
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on the ZII LAN IDE CP card designed by Matze (a1k.org) and Scrat (a1k.org).
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This driver is supposed to support ENC624J600 based ethernet on the
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ZII LAN IDE CP card designed by Matze (a1k.org), Buggs (a1k.org)
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and Scrat (a1k.org).
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Please see at the end of the file for information about licensing
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conditions.
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@@ -41,7 +42,7 @@ PRIORITY=PRI/K/N,BPS/K/N,MTU/K/N,FULLDUPLEX/S,FLOWCONTROL/S,TIMER/K/N,MULTICAST/
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caution: requires manual configuration of duplex mode
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on the switch, too.
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note: this switch should not be enabled in normal cases.
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The module feeatures autoconfiguration that determines
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The module features autoconfiguration that determines
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speed and duplex automatically.
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PRIORITY - server task priority (default 1)
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@@ -63,6 +64,20 @@ PRIORITY=PRI/K/N,BPS/K/N,MTU/K/N,FULLDUPLEX/S,FLOWCONTROL/S,TIMER/K/N,MULTICAST/
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Changelog:
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----------
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1.99 - fixed soft reset for ZIII firmware
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- re-enabled 32 Bit Buffer copies (unless Miami is active)
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- default server task priority for AmiTCP=6 (otherwise 0)
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- tuned RX/TX balancing to make RoadShow happy
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- added Packet Filter hook processing (needs testing)
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1.98 - improved TX speed
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- precaution: soft-reset cards in detection loop to make
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sure that no bogus settings are left over after reset
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- optional: disable length check in Sana-II Device Query
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1.97 - added New Style Device (NSD) commands
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- implemented SANA-II Device Query Extension
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1.93 - recompiled using SAS/C, now 1kB smaller
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1.91 - first Beta of completely rewritten driver
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@@ -0,0 +1,102 @@
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VWiznet - A SANA-II driver for W5500 10/100 ethernet modules
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Copyright (C) 2018-2019 Henryk Richter <henryk.richter@gmx.net>
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This driver is supposed to support W5500 modules hooked up to the expansion
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port of Vampire 500V2+ cards.
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Installation:
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-------------
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Installation of the driver is straightforward.
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Just copy vwiznet500ex.device from the bin subdirectory to devs:networks
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and enable the interface in your favorite TCP/IP stack as usual. So far,
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successful tests have been done with the free AmiTCP/IP 3.0b2, AmiTCP4.0-4.2,
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Genesis, MiamiDX and RoadShow.
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The minimum system requirement is the Gold 2.10 release of Apollo Core
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for Vampire 500V2+.
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Vampire500 Expansion port Hardware
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-----------------------------------
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Please see http://wiki.apollo-accelerators.com/doku.php/expansionport for
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guidance on pinout of the expansion port.
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The W5500 can be clocked way higher than the ENC28J60 that was used for
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SDNet. As a consequence of clocks beyond 25 MHz, signal integrity is of
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some concern. Therefore it is suggested to connect the module is as close
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as possible to the expansion port and use an Ethernet expansion cable
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in order to reach the edge of the computer case.
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An adapter PCB is in the making. That PCB plugs directly into the Vampire
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expansion port, connects readily available W5500 modules on the other
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side and contains some components to keep signal integrity in a good shape.
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Options
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-------
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Below you find the options accepted by the driver. Please note that no special
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configuration is necessary for normal operation. What you find documented below
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is available for tuning purposes.
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The options template for the config files
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ENVARC:SANA2/vwiznet500ex.config
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is as follows:
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PRIORITY=PRI/K/N,BPS/K/N,MTU/K/N,SPISPEED/K/N,TIMER/K/N,NOINTERRUPT/S
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SPISPEED - SPI clock divider (1-10, default 1), controls maximum
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clock of SPI bus. Actual I/O clock is Core_Clock/(3+SPISPEED).
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PRIORITY - server task priority (default 1)
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BPS - bit per seconds for statistics purposes
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MTU - maximum transmission unit (default 1500)
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NOINTERRUPT - disable hardware interrupt and use polling instead
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(default: interrupt enabled)
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TIMER - when disabling interrupt you also need to specify
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a timer interval in microseconds
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(default: 0, i.e. no timer)
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example1 (useful for DSL via PPPoE,
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higher priority for server task = more speed with AmiTCP
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at the expense of multitasking friendliness):
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echo "MTU=1492 SPISPEED=1 PRIORITY=6" >ENVARC:sana2/vwiznet500ex.config
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Changelog:
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----------
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1.99 - re-enabled 32 Bit Buffer copies (unless Miami is active)
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- default server task priority for AmiTCP=6 (otherwise 0)
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- tuned RX/TX balancing to make RoadShow happy
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- added Packet Filter hook processing (needs testing)
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1.98 - preparations for V2 of the adapter PCB: hardware based reset
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1.97 - added New style device commands
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- implemented SANA-II Device Query Extension
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1.96 - tuned defaults
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1.95 - initial build, aligned with sdnet/v2expeth version
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Copyrights / License:
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---------------------
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Copyright (C) 2018-2019 Henryk Richter <henryk.richter@gmx.net>, all rights reserved.
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Binary file not shown.
Binary file not shown.
@@ -197,17 +197,25 @@ ASM SAVEDS LONG DevOpen( ASMR(a1) struct IOSana2Req *ioreq ASMREG(a1),
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dbm->dbm_CopyFromBuffer = (BMCALL)((void (*)())(GetTagData(S2_CopyFromBuff, 0,
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(struct TagItem *)ioreq->ios2_BufferManagement)));
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/* v1.95: disable CopyToBuffer32 due to problems with MiamiDX */
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dbm->dbm_PacketFilter = (APTR)( GetTagData(S2_PacketFilter,0,
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(struct TagItem *)ioreq->ios2_BufferManagement));
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/* v1.95: disabled CopyToBuffer32 due to problems with MiamiDX */
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/* v1.99: try identifying Miami */
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/* MiamiDX requires byte count to be a multiple of 4 */
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#if 1
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if( FindPort("MIAMI.1") ) /* Miami active ? */
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{
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dbm->dbm_CopyToBuffer32 = (0);
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dbm->dbm_CopyFromBuffer32 = (0);
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#else
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}
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else
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{
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dbm->dbm_CopyToBuffer32 = (BMCALL)((void (*)())(GetTagData(S2_CopyToBuff32, 0,
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(struct TagItem *)ioreq->ios2_BufferManagement)));
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dbm->dbm_CopyFromBuffer32 = (BMCALL)((void (*)())(GetTagData(S2_CopyFromBuff32, 0,
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(struct TagItem *)ioreq->ios2_BufferManagement)));
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#endif
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}
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if( !dbm->dbm_CopyToBuffer32 )
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dbm->dbm_CopyToBuffer32 = dbm->dbm_CopyToBuffer;
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if( !dbm->dbm_CopyFromBuffer32 )
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@@ -255,8 +263,6 @@ ASM SAVEDS LONG DevOpen( ASMR(a1) struct IOSana2Req *ioreq ASMREG(a1),
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}
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ioreq->ios2_Req.io_Message.mn_Node.ln_Type = NT_REPLYMSG;
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D(("DevOpen return code %ld\n",ret));
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return ret;
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}
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@@ -580,8 +586,6 @@ ASM SAVEDS VOID DevBeginIO( ASMR(a1) struct IOSana2Req *ioreq ASMREG(a1),
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{
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struct IOStdReq *stdrq = (struct IOStdReq *)ioreq;
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D(("NSCMD_DEVICEQUERY size %ld\n",(ULONG)stdrq->io_Length));
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if( (!stdrq->io_Data) || (stdrq->io_Length < sizeof( NSDQueryAnswer ) ) )
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{
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ioreq->ios2_Req.io_Error = IOERR_BADLENGTH;
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@@ -592,7 +596,6 @@ ASM SAVEDS VOID DevBeginIO( ASMR(a1) struct IOSana2Req *ioreq ASMREG(a1),
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stdrq->io_Actual = sizeof( NSDQueryAnswer );
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ioreq->ios2_Req.io_Error = 0;
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}
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D(("NSCMD_DEVICEQUERY return %ld\n",(ULONG)ioreq->ios2_Req.io_Error));
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}
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break;
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/* query contents may ask for live data: handle in server.c */
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@@ -749,6 +752,9 @@ static LONG dbStartServer( DEVBASEP, LONG unit )
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sv_tags[i ].ti_Tag = NP_Name;
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sv_tags[i++].ti_Data = (ULONG)db->db_Lib.lib_Node.ln_Name;
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sv_tags[i ].ti_Tag = NP_Priority;
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if( FindPort("AMITCP") ) /* AmiTCP active ? */
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sv_tags[i++].ti_Data = (ULONG)6;
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else
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sv_tags[i++].ti_Data = (ULONG)0;
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sv_tags[i ].ti_Tag = TAG_DONE;
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@@ -131,6 +131,7 @@ struct db_BufferManagement {
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BMCALL dbm_CopyToBuffer32;
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BMCALL dbm_CopyFromBuffer;
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BMCALL dbm_CopyToBuffer;
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APTR dbm_PacketFilter; /* this is actually a Hook */
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ULONG dbm_ID;
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};
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@@ -1,4 +1,3 @@
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;APS00001922000000000000000000000000000000000000000000000000000000000000000000000000
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; ------------------------------------------------------------------------------
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; | Lowlevel Access to memory mapped ENC624J600 in PSP mode |
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; | Henryk Richter <henryk.richter@gmx.net> |
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@@ -25,9 +24,10 @@
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include "enc624j6net/macros.i"
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; enable debugging code block
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DEBUG EQU 1
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DEBUG EQU 0
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;
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ADD_4RX EQU 1 ;add 4 to valid RX size (fake CRC), fixes shapeshifter RAW treatment
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_OPT_LONGRESET EQU 0 ;in testing, don't enable
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;------------- <DANGER! APPLY CHANGES HERE ALSO TO enc624j6l.h !!> ------------
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;
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@@ -365,10 +365,14 @@ _enc624j6l_CheckBoard: ;check whether board is operating correctly
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move.l a0,d0
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beq .err
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move.w #CLOCK_DEF_SET,d0 ;set mask
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SETREG ECON2,a0,d0
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move.w #CLOCK_DEF_CLR,d0 ;clr mask
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CLRREG ECON2,a0,d0
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moveq #60,d0 ;let the board settle in if there was
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bsr _enc624j6l_UMinDelay ;a reset or POR (unlikely)
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; ----------------- quick check for operational mode ------------------
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move.w #$1234,d1
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WRITEREG EUDAST,a0,d1 ;write data
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@@ -377,16 +381,30 @@ _enc624j6l_CheckBoard: ;check whether board is operating correctly
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cmp.w d0,d1 ;do we get the register back ?
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bne.s .err ;no -> complain
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moveq #0,d0 ;magic trick: the board enables Interrupts
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lea $4000(a0),a0
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move.w d0,($4000,a0) ;0=disable interrupt
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lea -$4000(a0),a0
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; ------------------------- reset device ------------------------------
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move #EIR_CRYPTEN|EIR_MODEXIF|EIR_HASHIF|EIR_AESIF|EIR_LINKIF|EIR_PRDYIF|EIR_PKTIF|EIR_DMAIF|EIR_TXIF|EIR_TXABTIF|EIR_RXABTIF|EIR_PCFULIF,d0
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CLRREG EIR,a0,d0
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; ifne _OPT_LONGRESET
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; moveq #ECON2_ETHRST,d0
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; swap d0
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; move.l d0,ECON2-2(a0)
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; else
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moveq #ECON2_ETHRST,d0
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WRITEREG ECON2,a0,d0 ;reset board
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SETREG ECON2,a0,d0 ;reset board, was: WRITEREG
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; endc
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moveq #64-1,d1 ;number of loops to test (max. 7.6 ms)
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.loop:
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moveq #120,d0 ;wait patiently
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bsr _enc624j6l_UMinDelay ;
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READREG ESTAT,a0,d0
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and #(ESTAT_CLKRDY|ESTAT_RSTDONE|ESTAT_PHYRDY),d0
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cmp #(ESTAT_CLKRDY|ESTAT_RSTDONE|ESTAT_PHYRDY),d0
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@@ -400,6 +418,8 @@ _enc624j6l_CheckBoard: ;check whether board is operating correctly
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tst.w d0 ;should have gone to 0 after reset
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bne.s .err ;(see above, we've written $1234)
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ifne 0
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;---------- short RAM check - write phase ----------------------------
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;---------- (device is not receiving after reset) --------------------
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moveq #3,d1
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@@ -425,6 +445,8 @@ _enc624j6l_CheckBoard: ;check whether board is operating correctly
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eor.b #3,d1
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dbf d0,.rdloop
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endc ;ifne 0
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;---------- satisfied, return our sincere happiness -------------------
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moveq #1,d0 ;all fine
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@@ -539,11 +561,11 @@ _enc624j6l_Init:
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moveq #ECON1_RXEN,d0 ;no RX, my dear (yet)
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CLRREG ECON1,a0,d0 ;
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;33.333Mhz clock out frequency (see defines above)
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;25 MHz clock out frequency (see defines in registers.i)
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move.w #CLOCK_DEF_SET,d0 ;set mask
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SETREG ECON2,a0,d0 ;set first, then clear to avoid case of all COCON bits 0
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move.w #CLOCK_DEF_CLR,d0 ;clr mask
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CLRREG ECON2,a0,d0
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move.w #CLOCK_DEF_SET,d0 ;set mask
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SETREG ECON2,a0,d0
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; disable crypto engine and all interrupts
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move #EIR_CRYPTEN|EIR_MODEXIF|EIR_HASHIF|EIR_AESIF|EIR_LINKIF|EIR_PRDYIF|EIR_PKTIF|EIR_DMAIF|EIR_TXIF|EIR_TXABTIF|EIR_RXABTIF|EIR_PCFULIF,d0
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@@ -1230,12 +1252,35 @@ _enc624j6l_RecvFrame: ;
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ifne _OPT_ADR_QUIRK
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eor.w #$6000,d7
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endc
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endc ;_OPT_ADR_QUIRK
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lea (a0,d7.w),a2 ;read pointer
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ifeq _OPT_BUFFER_SWAP
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move.l d0,d2 ;total bytes
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moveq #15,d1 ;
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lsr.w #4,d2 ;total/16
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and.l d0,d1 ;remainder: max 15 bytes
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addq #3,d1 ;remainder, rounded up to +3 bytes
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subq #1,d2 ;dbf
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blt.s .nopt16_read ;less than 16 bytes -> bail out
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bra.s .opt16_read
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.opt16_loop:
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move.l d3,(a1)+
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.opt16_read:
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rept 3
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move.l (a2)+,(a1)+
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endr
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move.l (a2)+,d3
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dbf d2,.opt16_loop
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move.l d3,(a1)+
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.nopt16_read:
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else ;_OPT_BUFFER_SWAP
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moveq #3,d1 ;round bytes up
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add d0,d1 ;byte count + 3
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endc ;_OPT_BUFFER_SWAP
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lsr #2,d1 ;converted to dword count = ceil(bytes/4)
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subq #1,d1 ;longwords - 1
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blt.s .end_read
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.opt_read:
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ifne _OPT_BUFFER_SWAP
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move.l (a2)+,d2 ;get current word
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@@ -1244,11 +1289,12 @@ _enc624j6l_RecvFrame: ;
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rol.w #8,d2 ;swap buffer to Big Endian
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swap D2
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move.l d2,(a1)+
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else
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else ;_OPT_BUFFER_SWAP
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move.l (a2)+,(a1)+
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endc
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endc ;_OPT_BUFFER_SWAP
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dbf d1,.opt_read
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bra.s .end_read
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.nooptrecv:
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endc ;_OPT_RECV
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Binary file not shown.
@@ -86,6 +86,7 @@ ASM SAVEDS LONG hw_Find_Boards( ASMR(a0) DEVBASEP ASMREG(a0) )
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LONG i,ret = 0;
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struct Library *ExpansionBase;
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struct ConfigDev *cfg = (0);
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APTR boardbase;
|
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if( (ExpansionBase = OpenLibrary( (BYTE*)exp_name, 37 )) )
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{
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@@ -97,8 +98,13 @@ ASM SAVEDS LONG hw_Find_Boards( ASMR(a0) DEVBASEP ASMREG(a0) )
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cfg = FindConfigDev( cfg, ENC_MANUFACTURER, ENC_BOARD );
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if( !cfg )
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break;
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db->db_Units[i].duh_BASE = (APTR)cfg->cd_BoardAddr;
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boardbase = (APTR)cfg->cd_BoardAddr;
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db->db_Units[i].duh_BASE = boardbase;
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D(("Board at %lx\n",(ULONG)cfg->cd_BoardAddr ));
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|
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/* bring board to sane state (i.e. perform soft reset) */
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/* if( boardbase < (APTR)0x40000000 ) */ /* debug only */
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enc624j6l_CheckBoard( boardbase );
|
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}
|
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ret = i;
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D(("%ld boards found\n",ret));
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@@ -30,6 +30,11 @@
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static LONG server_queryext( DEVBASEP, ULONG unit, struct IOSana2Req *ioreq );
|
||||
#endif
|
||||
|
||||
/* the XSurf500 network panel currently claims length 0 requests
|
||||
if the line below is not commented out, just check pointer
|
||||
*/
|
||||
#define S2QUERYEXT_NOLENGTHCHECK
|
||||
|
||||
|
||||
/* (avoid external link libraries) this call is not time critical */
|
||||
static void MemSet( void *a, ULONG val, ULONG size )
|
||||
@@ -396,6 +401,8 @@ static LONG server_HandleS2Commands( DEVBASEP )
|
||||
ioreq->ios2_Req.io_Error = S2ERR_NO_ERROR;
|
||||
ioreq->ios2_WireError = S2WERR_GENERIC_ERROR;
|
||||
|
||||
D(("server_HandleS2Commands: CMD %ld",(ULONG)ioreq->ios2_Req.io_Command));
|
||||
|
||||
switch( ioreq->ios2_Req.io_Command)
|
||||
{
|
||||
case S2_ONLINE:
|
||||
@@ -482,9 +489,16 @@ static LONG server_queryext( DEVBASEP, ULONG unit, struct IOSana2Req *ioreq )
|
||||
|
||||
tlist = (struct TagItem*)ioreq->ios2_Data;
|
||||
|
||||
D(("Query for %ld bytes TAGLIST %lx\n",(ULONG)ioreq->ios2_DataLength,(ULONG)tlist ));
|
||||
|
||||
#ifdef S2QUERYEXT_NOLENGTHCHECK
|
||||
if( !tlist )
|
||||
return 0;
|
||||
#else
|
||||
/* 3*4 Bytes needed for one Tag + TAG_DONE */
|
||||
if( (ioreq->ios2_DataLength < 12) || (!tlist) )
|
||||
return 0;
|
||||
#endif
|
||||
|
||||
tval = GetTagData( S2_DevQueryExtVendorName, 0, tlist );
|
||||
if( tval )
|
||||
@@ -494,6 +508,7 @@ static LONG server_queryext( DEVBASEP, ULONG unit, struct IOSana2Req *ioreq )
|
||||
len = min( s2qep->Length, sizeof(server_vendorstring) );
|
||||
CopyMem( (void*)server_vendorstring, s2qep->Data, len );
|
||||
s2qep->Actual = len;
|
||||
D(("Vendorname Query"));
|
||||
}
|
||||
|
||||
tval = GetTagData( S2_DevQueryExtProductName, 0, tlist );
|
||||
@@ -504,6 +519,7 @@ static LONG server_queryext( DEVBASEP, ULONG unit, struct IOSana2Req *ioreq )
|
||||
len = min( s2qep->Length, sizeof(server_productstring) );
|
||||
CopyMem( (void*)server_productstring, s2qep->Data, len );
|
||||
s2qep->Actual = len;
|
||||
D(("Productname Query"));
|
||||
}
|
||||
|
||||
|
||||
@@ -511,6 +527,7 @@ static LONG server_queryext( DEVBASEP, ULONG unit, struct IOSana2Req *ioreq )
|
||||
tval2 = GetTagData( S2_DevQueryExtLinkSpeed, 0, tlist );
|
||||
if( (tval) || (tval2) )
|
||||
{
|
||||
D(("Link Status and/or Speed"));
|
||||
/* ask hardware about link/speed status */
|
||||
len = hw_get_mac_status(db, unit);
|
||||
if( len != HW_MAC_INVALID )
|
||||
@@ -709,6 +726,8 @@ static LONG server_writequeue( DEVBASEP, ULONG unit )
|
||||
/* error handling */
|
||||
server_writeerror( db, unit, ioreq, code );
|
||||
}
|
||||
if( hw_recv_pending(db,unit) )
|
||||
break;
|
||||
}
|
||||
|
||||
ReleaseSemaphore( &db->db_Units[unit].du_Sem );
|
||||
@@ -717,6 +736,9 @@ static LONG server_writequeue( DEVBASEP, ULONG unit )
|
||||
}
|
||||
|
||||
|
||||
typedef ULONG (* ASM PFCALL)( ASMR(a0) struct Hook * ASMREG(a0), ASMR(a2) void * ASMREG(a2), ASMR(a1) ULONG *ASMREG(a1) );
|
||||
#define PFTYPE ULONG (*)( struct Hook *,void *,ULONG * )
|
||||
|
||||
/* note: entering here with locked semaphore */
|
||||
static void server_read_frame( DEVBASEP, ULONG unit, struct IOSana2Req *ioreq, UBYTE *frame, ULONG framesize )
|
||||
{
|
||||
@@ -726,6 +748,8 @@ static void server_read_frame( DEVBASEP, ULONG unit, struct IOSana2Req *ioreq, U
|
||||
COPYMAC( ioreq->ios2_DstAddr, frame ); /* macro in server.h */
|
||||
COPYMAC( ioreq->ios2_SrcAddr, frame+6 );
|
||||
|
||||
dbm = (struct db_BufferManagement *)ioreq->ios2_BufferManagement;
|
||||
|
||||
if( *frame & 1 ) /* just check Ethernet MULTICAST flag */
|
||||
{
|
||||
ULONG mac = *((ULONG*)frame );
|
||||
@@ -751,9 +775,17 @@ static void server_read_frame( DEVBASEP, ULONG unit, struct IOSana2Req *ioreq, U
|
||||
ioreq->ios2_Req.io_Error = 0;
|
||||
ioreq->ios2_WireError = 0;
|
||||
|
||||
dbm = (struct db_BufferManagement *)ioreq->ios2_BufferManagement;
|
||||
D(("ReadFrm IO %lx, DBM %lx frm %lx frmsz %ld\n",(ULONG)ioreq,(ULONG)dbm,(ULONG)frame,framesize));
|
||||
|
||||
if( dbm->dbm_PacketFilter ) /* Filter Packets ? */
|
||||
{
|
||||
struct Hook *hk = (struct Hook *)dbm->dbm_PacketFilter;
|
||||
PFCALL dispatch = (PFCALL)hk->h_Entry;
|
||||
|
||||
if( !dispatch( hk, (void*)ioreq, (ULONG*)frame ) )
|
||||
return;
|
||||
}
|
||||
|
||||
if(!(*dbm->dbm_CopyToBuffer32)(ioreq->ios2_Data, frame, framesize ))
|
||||
{
|
||||
if(!(*dbm->dbm_CopyToBuffer)(ioreq->ios2_Data, frame, framesize ))
|
||||
|
||||
@@ -9,8 +9,8 @@
|
||||
#define _INC_VERSION_H
|
||||
|
||||
#define DEVICEVERSION 1
|
||||
#define DEVICEREVISION 98
|
||||
#define DEVICEREVISION 99
|
||||
#define DEVICEEXTRA Beta
|
||||
#define DEVICEDATE 03.01.2019
|
||||
#define DEVICEDATE 08.01.2019
|
||||
|
||||
#endif
|
||||
|
||||
@@ -67,12 +67,10 @@
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1546470548" xil_pn:in_ck="-2520376148396271922" xil_pn:name="TRANEXT_xstsynthesize_xc9500xl" xil_pn:prop_ck="2647934492491614606" xil_pn:start_ts="1546470526">
|
||||
<transform xil_pn:end_ts="1550612785" xil_pn:in_ck="-2520376148396271922" xil_pn:name="TRANEXT_xstsynthesize_xc9500xl" xil_pn:prop_ck="2647934492491614606" xil_pn:start_ts="1550612764">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="WarningsGenerated"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForInputs"/>
|
||||
<status xil_pn:value="InputChanged"/>
|
||||
<outfile xil_pn:name="LAN_IDE_CP.lso"/>
|
||||
<outfile xil_pn:name="LAN_IDE_CP.ngc"/>
|
||||
<outfile xil_pn:name="LAN_IDE_CP.ngr"/>
|
||||
@@ -90,21 +88,19 @@
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1546470556" xil_pn:in_ck="-8547647177936735053" xil_pn:name="TRAN_ngdbuild" xil_pn:prop_ck="6932115226421322529" xil_pn:start_ts="1546470548">
|
||||
<transform xil_pn:end_ts="1550612793" xil_pn:in_ck="-8547647177936735053" xil_pn:name="TRAN_ngdbuild" xil_pn:prop_ck="6932115226421322529" xil_pn:start_ts="1550612785">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForPredecessor"/>
|
||||
<outfile xil_pn:name="LAN_IDE_CP.bld"/>
|
||||
<outfile xil_pn:name="LAN_IDE_CP.ngd"/>
|
||||
<outfile xil_pn:name="LAN_IDE_CP_ngdbuild.xrpt"/>
|
||||
<outfile xil_pn:name="_ngo"/>
|
||||
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1546470603" xil_pn:in_ck="-2520376148396280667" xil_pn:name="TRANEXT_vm6File_xc9500xl" xil_pn:prop_ck="-1014768965495450326" xil_pn:start_ts="1546470556">
|
||||
<transform xil_pn:end_ts="1550612839" xil_pn:in_ck="-2520376148396280667" xil_pn:name="TRANEXT_vm6File_xc9500xl" xil_pn:prop_ck="-1014768965495450326" xil_pn:start_ts="1550612793">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="WarningsGenerated"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForPredecessor"/>
|
||||
<outfile xil_pn:name="LAN_IDE_CP.gyd"/>
|
||||
<outfile xil_pn:name="LAN_IDE_CP.mfd"/>
|
||||
<outfile xil_pn:name="LAN_IDE_CP.nga"/>
|
||||
@@ -118,25 +114,21 @@
|
||||
<outfile xil_pn:name="LAN_IDE_CP_html"/>
|
||||
<outfile xil_pn:name="LAN_IDE_CP_pad.csv"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1546470606" xil_pn:in_ck="-2520376148396271803" xil_pn:name="TRANEXT_crtProg_xc9500" xil_pn:prop_ck="-6294026017969277533" xil_pn:start_ts="1546470603">
|
||||
<transform xil_pn:end_ts="1550612842" xil_pn:in_ck="-2520376148396271803" xil_pn:name="TRANEXT_crtProg_xc9500" xil_pn:prop_ck="-6294026017969277533" xil_pn:start_ts="1550612839">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForPredecessor"/>
|
||||
<outfile xil_pn:name="LAN_IDE_CP.jed"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1545129218" xil_pn:in_ck="-2520376148396285089" xil_pn:name="TRAN_impactProgrammingTool_CPLD" xil_pn:prop_ck="-3598488201878296819" xil_pn:start_ts="1545129218">
|
||||
<status xil_pn:value="AbortedRun"/>
|
||||
<transform xil_pn:end_ts="1550358728" xil_pn:in_ck="-2520376148396285089" xil_pn:name="TRAN_impactProgrammingTool_CPLD" xil_pn:prop_ck="-3598488201878296819" xil_pn:start_ts="1550358728">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForInputs"/>
|
||||
<status xil_pn:value="OutOfDateForPredecessor"/>
|
||||
<status xil_pn:value="OutOfDateForced"/>
|
||||
<status xil_pn:value="InputChanged"/>
|
||||
</transform>
|
||||
<transform xil_pn:name="TRAN_timRpt">
|
||||
<status xil_pn:value="AbortedRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForInputs"/>
|
||||
<status xil_pn:value="OutOfDateForPredecessor"/>
|
||||
<status xil_pn:value="InputAdded"/>
|
||||
<status xil_pn:value="InputChanged"/>
|
||||
</transform>
|
||||
|
||||
@@ -29,7 +29,7 @@ NGDBUILD Design Results Summary:
|
||||
Number of errors: 0
|
||||
Number of warnings: 0
|
||||
|
||||
Total memory usage is 4418736 kilobytes
|
||||
Total memory usage is 4418696 kilobytes
|
||||
|
||||
Writing NGD file "LAN_IDE_CP.ngd" ...
|
||||
Total REAL time to NGDBUILD completion: 5 sec
|
||||
|
||||
@@ -365,3 +365,168 @@ cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt
|
||||
XSLTProcess LAN_IDE_CP_build.xml
|
||||
tsim -intstyle ise LAN_IDE_CP LAN_IDE_CP.nga
|
||||
hprep6 -s IEEE1149 -n LAN_IDE_CP -i LAN_IDE_CP
|
||||
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
|
||||
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
|
||||
XSLTProcess LAN_IDE_CP_build.xml
|
||||
tsim -intstyle ise LAN_IDE_CP LAN_IDE_CP.nga
|
||||
hprep6 -s IEEE1149 -n LAN_IDE_CP -i LAN_IDE_CP
|
||||
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
|
||||
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
|
||||
XSLTProcess LAN_IDE_CP_build.xml
|
||||
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
|
||||
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
|
||||
XSLTProcess LAN_IDE_CP_build.xml
|
||||
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
|
||||
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
|
||||
XSLTProcess LAN_IDE_CP_build.xml
|
||||
tsim -intstyle ise LAN_IDE_CP LAN_IDE_CP.nga
|
||||
hprep6 -s IEEE1149 -n LAN_IDE_CP -i LAN_IDE_CP
|
||||
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
|
||||
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
|
||||
XSLTProcess LAN_IDE_CP_build.xml
|
||||
tsim -intstyle ise LAN_IDE_CP LAN_IDE_CP.nga
|
||||
hprep6 -s IEEE1149 -n LAN_IDE_CP -i LAN_IDE_CP
|
||||
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
|
||||
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
|
||||
XSLTProcess LAN_IDE_CP_build.xml
|
||||
tsim -intstyle ise LAN_IDE_CP LAN_IDE_CP.nga
|
||||
hprep6 -s IEEE1149 -n LAN_IDE_CP -i LAN_IDE_CP
|
||||
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
|
||||
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
|
||||
XSLTProcess LAN_IDE_CP_build.xml
|
||||
tsim -intstyle ise LAN_IDE_CP LAN_IDE_CP.nga
|
||||
hprep6 -s IEEE1149 -n LAN_IDE_CP -i LAN_IDE_CP
|
||||
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
|
||||
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
|
||||
XSLTProcess LAN_IDE_CP_build.xml
|
||||
tsim -intstyle ise LAN_IDE_CP LAN_IDE_CP.nga
|
||||
hprep6 -s IEEE1149 -n LAN_IDE_CP -i LAN_IDE_CP
|
||||
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
|
||||
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
|
||||
XSLTProcess LAN_IDE_CP_build.xml
|
||||
tsim -intstyle ise LAN_IDE_CP LAN_IDE_CP.nga
|
||||
hprep6 -s IEEE1149 -n LAN_IDE_CP -i LAN_IDE_CP
|
||||
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
|
||||
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
|
||||
XSLTProcess LAN_IDE_CP_build.xml
|
||||
tsim -intstyle ise LAN_IDE_CP LAN_IDE_CP.nga
|
||||
hprep6 -s IEEE1149 -n LAN_IDE_CP -i LAN_IDE_CP
|
||||
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
|
||||
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
|
||||
XSLTProcess LAN_IDE_CP_build.xml
|
||||
tsim -intstyle ise LAN_IDE_CP LAN_IDE_CP.nga
|
||||
hprep6 -s IEEE1149 -n LAN_IDE_CP -i LAN_IDE_CP
|
||||
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
|
||||
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
|
||||
XSLTProcess LAN_IDE_CP_build.xml
|
||||
tsim -intstyle ise LAN_IDE_CP LAN_IDE_CP.nga
|
||||
hprep6 -s IEEE1149 -n LAN_IDE_CP -i LAN_IDE_CP
|
||||
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
|
||||
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
|
||||
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
|
||||
XSLTProcess LAN_IDE_CP_build.xml
|
||||
tsim -intstyle ise LAN_IDE_CP LAN_IDE_CP.nga
|
||||
hprep6 -s IEEE1149 -n LAN_IDE_CP -i LAN_IDE_CP
|
||||
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
|
||||
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
|
||||
XSLTProcess LAN_IDE_CP_build.xml
|
||||
tsim -intstyle ise LAN_IDE_CP LAN_IDE_CP.nga
|
||||
hprep6 -s IEEE1149 -n LAN_IDE_CP -i LAN_IDE_CP
|
||||
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
|
||||
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
|
||||
XSLTProcess LAN_IDE_CP_build.xml
|
||||
tsim -intstyle ise LAN_IDE_CP LAN_IDE_CP.nga
|
||||
hprep6 -s IEEE1149 -n LAN_IDE_CP -i LAN_IDE_CP
|
||||
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
|
||||
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
|
||||
XSLTProcess LAN_IDE_CP_build.xml
|
||||
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
|
||||
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
|
||||
XSLTProcess LAN_IDE_CP_build.xml
|
||||
tsim -intstyle ise LAN_IDE_CP LAN_IDE_CP.nga
|
||||
hprep6 -s IEEE1149 -n LAN_IDE_CP -i LAN_IDE_CP
|
||||
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
|
||||
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
|
||||
XSLTProcess LAN_IDE_CP_build.xml
|
||||
tsim -intstyle ise LAN_IDE_CP LAN_IDE_CP.nga
|
||||
hprep6 -s IEEE1149 -n LAN_IDE_CP -i LAN_IDE_CP
|
||||
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
|
||||
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
|
||||
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
|
||||
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
|
||||
XSLTProcess LAN_IDE_CP_build.xml
|
||||
tsim -intstyle ise LAN_IDE_CP LAN_IDE_CP.nga
|
||||
hprep6 -s IEEE1149 -n LAN_IDE_CP -i LAN_IDE_CP
|
||||
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
|
||||
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
|
||||
XSLTProcess LAN_IDE_CP_build.xml
|
||||
tsim -intstyle ise LAN_IDE_CP LAN_IDE_CP.nga
|
||||
hprep6 -s IEEE1149 -n LAN_IDE_CP -i LAN_IDE_CP
|
||||
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
|
||||
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
|
||||
XSLTProcess LAN_IDE_CP_build.xml
|
||||
tsim -intstyle ise LAN_IDE_CP LAN_IDE_CP.nga
|
||||
hprep6 -s IEEE1149 -n LAN_IDE_CP -i LAN_IDE_CP
|
||||
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
|
||||
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
|
||||
XSLTProcess LAN_IDE_CP_build.xml
|
||||
tsim -intstyle ise LAN_IDE_CP LAN_IDE_CP.nga
|
||||
hprep6 -s IEEE1149 -n LAN_IDE_CP -i LAN_IDE_CP
|
||||
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
|
||||
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
|
||||
XSLTProcess LAN_IDE_CP_build.xml
|
||||
tsim -intstyle ise LAN_IDE_CP LAN_IDE_CP.nga
|
||||
hprep6 -s IEEE1149 -n LAN_IDE_CP -i LAN_IDE_CP
|
||||
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
|
||||
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
|
||||
XSLTProcess LAN_IDE_CP_build.xml
|
||||
tsim -intstyle ise LAN_IDE_CP LAN_IDE_CP.nga
|
||||
hprep6 -s IEEE1149 -n LAN_IDE_CP -i LAN_IDE_CP
|
||||
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
|
||||
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
|
||||
XSLTProcess LAN_IDE_CP_build.xml
|
||||
tsim -intstyle ise LAN_IDE_CP LAN_IDE_CP.nga
|
||||
hprep6 -s IEEE1149 -n LAN_IDE_CP -i LAN_IDE_CP
|
||||
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
|
||||
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
|
||||
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
|
||||
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
|
||||
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
|
||||
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
|
||||
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
|
||||
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
|
||||
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
|
||||
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
|
||||
XSLTProcess LAN_IDE_CP_build.xml
|
||||
tsim -intstyle ise LAN_IDE_CP LAN_IDE_CP.nga
|
||||
hprep6 -s IEEE1149 -n LAN_IDE_CP -i LAN_IDE_CP
|
||||
|
||||
@@ -120,85 +120,85 @@ A<23> S:PIN86
|
||||
;The remaining section of the .gyd file is for documentation purposes only.
|
||||
;It shows where your internal equations were placed in the last successful fit.
|
||||
|
||||
PARTITION FB1_1 DQ_DATA<11> LAN_SM_FSM_FFd2 EXP22_
|
||||
PARTITION FB1_5 D_5_IOBUFE D_4_IOBUFE
|
||||
PARTITION FB1_8 IDE_CS_0_OBUF Z3_A_LOW IDE_CS_1_OBUF LAN_SM_FSM_FFd3
|
||||
IDE_A_0_OBUF$BUF0 DQ_DATA<3> IDE_A_2_OBUF$BUF0 IDE_A_1_OBUF$BUF0
|
||||
DQ_DATA<12> IDE_R_OBUF EXP23_
|
||||
PARTITION FB2_1 LAN_BASEADR<1> A_LAN_4_OBUF A_LAN_7_OBUF LAN_BASEADR<15>
|
||||
A_LAN_6_OBUF ROM_B_0_OBUF$BUF7 LAN_BASEADR<14> ROM_B_0_OBUF$BUF5
|
||||
LAN_BASEADR<13> D_6_IOBUFE LAN_BASEADR<12> D_3_IOBUFE
|
||||
LAN_BASEADR<11> D_7_IOBUFE D_1_IOBUFE LAN_BASEADR<10>
|
||||
D_8_IOBUFE LAN_BASEADR<0>
|
||||
PARTITION FB3_1 $OpTx$INV$215 IDE_W_OBUF EXP24_
|
||||
PARTITION FB3_9 SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF ROM_B_0_OBUF$BUF9/ROM_B_0_OBUF$BUF9_TRST__$INT ROM_B_0_OBUF$BUF8/ROM_B_0_OBUF$BUF8_TRST CP_WE_QUIRK
|
||||
Z3_ADR<9> ROM_B_0_OBUF$BUF8 Z3_ADR<8> Z3_ADR<7>
|
||||
Z3_ADR<6> EXP25_
|
||||
PARTITION FB4_1 D_OUT<7> D_0_IOBUFE D_OUT<3> D_OUT<0>
|
||||
A_LAN_1_OBUF A_LAN_0_OBUF D_OUT<2> A_LAN_3_OBUF
|
||||
D_OUT<6> D_OUT<5> D_OUT<4> A_LAN_2_OBUF
|
||||
D_OUT<1> A_LAN_5_OBUF IDE_BASEADR<3> IDE_BASEADR<2>
|
||||
IDE_BASEADR<1> IDE_BASEADR<0>
|
||||
PARTITION FB5_1 EXP26_ CP_CS_OBUF EXP27_ $OpTx$FX_DC$107
|
||||
ROM_OE_OBUF Z3_ADR<10> AUTOCONFIG_Z2_ACCESS $OpTx$FX_DC$117__$INT
|
||||
D_9_IOBUFE/D_9_IOBUFE_TRST__$INT D_2_IOBUFE EXP28_ D_9_IOBUFE
|
||||
EXP29_ D_10_IOBUFE D_11_IOBUFE EXP30_
|
||||
D_12_IOBUFE ROM_B_0_OBUF$BUF2/ROM_B_0_OBUF$BUF2_TRST
|
||||
PARTITION FB6_1 LAN_A_INIT<3> ROM_B_0_OBUF$BUF6 A_LAN_12_OBUF LAN_IRQ_D0
|
||||
A_LAN_13_OBUF A_LAN_10_OBUF LAN_WR_RST A_LAN_11_OBUF
|
||||
LAN_RST_SM_FSM_FFd3 A_LAN_8_OBUF LAN_RST_SM_FSM_FFd2 LAN_RST_SM_FSM_FFd1
|
||||
LAN_IRQ_OUT A_LAN_9_OBUF LAN_D_INIT<8> LAN_D_INIT<1>
|
||||
LAN_CS_RST LAN_A_INIT<6>
|
||||
PARTITION FB7_1 LAN_SM_RST EXP31_ D_13_IOBUFE AUTO_CONFIG_DONE_CYCLE
|
||||
D_14_IOBUFE EXP32_ SHUT_UP LAN_BASEADR<2>
|
||||
LAN_BASEADR<3> LAN_BASEADR<4> LAN_BASEADR<5> D_15_IOBUFE
|
||||
EXP33_ LAN_BASEADR<6> LAN_BASEADR<7> LAN_INT_ENABLE
|
||||
LAN_BASEADR<8> LAN_BASEADR<9>
|
||||
PARTITION FB8_1 EXP34_ DQ_12_IOBUFE DQ_14_IOBUFE
|
||||
PARTITION FB8_5 LAN_WRH_OBUF
|
||||
PARTITION FB8_8 LAN_CS_OBUF
|
||||
PARTITION FB8_10 LAN_RD_OBUF
|
||||
PARTITION FB8_13 Z3_ADR<13> AUTOCONFIG_Z3_ACCESS AUTO_CONFIG_Z2_DONE<1> AUTO_CONFIG_Z2_DONE<0>
|
||||
EXP35_ IDE_ACCESS
|
||||
PARTITION FB9_1 EXP36_ DQ_SWAP EXP37_ Z3_ADR<12>
|
||||
Z3_ADR<11> ROM_OE_S CONFIG_READY EXP38_
|
||||
LAN_ACCESS EXP39_ Z3_DATA<0> IDE_W_S
|
||||
IDE_R_S Z3_DATA<1> IDE_ENABLE AUTO_CONFIG_DONE
|
||||
Z3_DATA<2> EXP40_
|
||||
PARTITION FB10_1 Z3_ADR<2> DQ_1_IOBUFE DQ_0_IOBUFE IDE_BASEADR<7>
|
||||
DQ_3_IOBUFE DQ_2_IOBUFE IDE_BASEADR<6> DQ_5_IOBUFE
|
||||
IDE_BASEADR<5> DQ_4_IOBUFE DQ_7_IOBUFE DQ_6_IOBUFE
|
||||
IDE_BASEADR<4> DQ_8_IOBUFE CP_BASEADR<6> CP_BASEADR<5>
|
||||
DQ_10_IOBUFE CP_BASEADR<4>
|
||||
PARTITION FB1_2 AUTO_CONFIG_Z2_DONE_CYCLE<2> AUTO_CONFIG_Z2_DONE<2> IDE_BASEADR<7> D_5_IOBUFE
|
||||
D_4_IOBUFE CP_BASEADR<7> IDE_CS_0_OBUF CP_BASEADR<4>
|
||||
IDE_CS_1_OBUF CP_BASEADR<3> IDE_A_0_OBUF$BUF0 CP_BASEADR<2>
|
||||
IDE_A_2_OBUF$BUF0 IDE_A_1_OBUF$BUF0 CP_BASEADR<1> IDE_R_OBUF
|
||||
CP_BASEADR<0>
|
||||
PARTITION FB2_1 D_5_IOBUFE/D_5_IOBUFE_TRST A_LAN_4_OBUF A_LAN_7_OBUF IDE_BASEADR<6>
|
||||
A_LAN_6_OBUF ROM_B_0_OBUF$BUF7 IDE_BASEADR<5> ROM_B_0_OBUF$BUF5
|
||||
IDE_BASEADR<4> D_6_IOBUFE IDE_BASEADR<3> D_3_IOBUFE
|
||||
IDE_BASEADR<2> D_7_IOBUFE D_1_IOBUFE IDE_BASEADR<1>
|
||||
D_8_IOBUFE IDE_BASEADR<0>
|
||||
PARTITION FB3_2 IDE_W_OBUF
|
||||
PARTITION FB3_14 ROM_B_0_OBUF$BUF8 SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF ROM_B_0_OBUF$BUF9/ROM_B_0_OBUF$BUF9_TRST ROM_B_0_OBUF$BUF8/ROM_B_0_OBUF$BUF8_TRST
|
||||
CP_WE_QUIRK
|
||||
PARTITION FB4_1 IDE_ENABLE D_0_IOBUFE Z3_ADR<12> Z3_ADR<11>
|
||||
A_LAN_1_OBUF A_LAN_0_OBUF ROM_OE_S A_LAN_3_OBUF
|
||||
EXP22_ LAN_ACCESS EXP23_ A_LAN_2_OBUF
|
||||
IDE_R_S A_LAN_5_OBUF EXP24_ DQ_SWAP
|
||||
EXP25_ EXP26_
|
||||
PARTITION FB5_1 EXP27_ CP_CS_OBUF EXP28_ EXP29_
|
||||
ROM_OE_OBUF
|
||||
PARTITION FB5_9 LAN_A_INIT<3> D_2_IOBUFE LAN_IRQ_D0 D_9_IOBUFE
|
||||
CONFIG_READY D_10_IOBUFE D_11_IOBUFE LAN_INT_ENABLE
|
||||
D_12_IOBUFE AUTOCONFIG_Z2_ACCESS
|
||||
PARTITION FB6_1 Z3_ADR_1 ROM_B_0_OBUF$BUF6 A_LAN_12_OBUF Z3_ADR_0
|
||||
A_LAN_13_OBUF A_LAN_10_OBUF Z3_ADR<9> A_LAN_11_OBUF
|
||||
Z3_ADR<8> A_LAN_8_OBUF Z3_ADR<7> Z3_ADR<6>
|
||||
Z3_ADR<5> A_LAN_9_OBUF Z3_ADR<4> Z3_ADR<3>
|
||||
LAN_WR_RST LAN_IRQ_OUT
|
||||
PARTITION FB7_1 CP_BASEADR<5> SHUT_UP_Z2<1> D_13_IOBUFE LAN_BASEADR<6>
|
||||
D_14_IOBUFE EXP30_ LAN_BASEADR<5> LAN_BASEADR<2>
|
||||
LAN_BASEADR<14> LAN_BASEADR<13> LAN_BASEADR<11> D_15_IOBUFE
|
||||
LAN_BASEADR<10> EXP31_ EXP32_ LAN_BASEADR<8>
|
||||
LAN_BASEADR<0> CP_BASEADR<6>
|
||||
PARTITION FB8_1 Z3_ADR<2> DQ_12_IOBUFE DQ_14_IOBUFE LAN_BASEADR<12>
|
||||
LAN_WRH_OBUF LAN_BASEADR<15> LAN_BASEADR<1> LAN_CS_OBUF
|
||||
LAN_BASEADR<3> LAN_RD_OBUF LAN_BASEADR<4> LAN_BASEADR<7>
|
||||
LAN_BASEADR<9> Z3_ADR<10> Z3_ADR<13> EXP33_
|
||||
D_Z2_OUT<0> EXP34_
|
||||
PARTITION FB9_1 EXP35_ LAN_WRL_S LAN_WRH_S LAN_SM_RST
|
||||
LAN_SM_FSM_FFd4 LAN_RD_S DQ_12_IOBUFE/DQ_12_IOBUFE_TRST__$INT LAN_READY
|
||||
LAN_SM_FSM_FFd2 Z3_A_LOW Z3_DATA<0> EXP36_
|
||||
LAN_SM_FSM_FFd1 Z3_DATA<1> DQ_DATA<9> EXP37_
|
||||
Z3_DATA<2> DQ_DATA<5>
|
||||
PARTITION FB10_2 DQ_1_IOBUFE DQ_0_IOBUFE
|
||||
PARTITION FB10_5 DQ_3_IOBUFE DQ_2_IOBUFE
|
||||
PARTITION FB10_8 DQ_5_IOBUFE
|
||||
PARTITION FB10_10 DQ_4_IOBUFE DQ_7_IOBUFE DQ_6_IOBUFE
|
||||
PARTITION FB10_14 DQ_8_IOBUFE
|
||||
PARTITION FB10_17 DQ_10_IOBUFE
|
||||
|
||||
PARTITION FB11_1 Z3_DATA<30> Z3_DATA<29> Z3_DATA<3> Z3_DATA<28>
|
||||
Z3_DATA<4> Z3_DATA<27> Z3_DATA<22> Z3_DATA<21>
|
||||
Z3_DATA<20> Z3_DATA<5> Z3_DATA<6> ROM_B_0_OBUF$BUF0
|
||||
Z3_DATA<19> ROM_B_0_OBUF EXP41_ DQ_DATA<8>
|
||||
Z3_DATA<19> ROM_B_0_OBUF EXP38_ DQ_DATA<8>
|
||||
CP_WE_OBUF DQ_DATA<0>
|
||||
PARTITION FB12_1 Z3_ADR_1 ROM_B_0_OBUF$BUF4 D_Z2_OUT<2> EXP42_
|
||||
DQ_15_IOBUFE D_Z2_OUT<3> EXP43_ DQ_13_IOBUFE
|
||||
CP_WE_S DQ_11_IOBUFE Z3_ADR<3> DQ_9_IOBUFE
|
||||
Z3_ADR<4> Z3_ADR<5> EXP44_ D_Z2_OUT<1>
|
||||
EXP45_ Z3_ADR_0
|
||||
PARTITION FB13_1 EXP46_ CP_RD_OBUF Z3_DATA<31> EXP47_
|
||||
LAN_SM_FSM_FFd1 EXP48_ DQ_DATA<6> Z3_DATA<7>
|
||||
Z3_DATA<23> EXP49_ EXP50_ DQ_DATA<5>
|
||||
DQ_DATA<15> LAN_WRL_OBUF DQ_DATA<14> EXP51_
|
||||
EXP52_ DQ_DATA<13>
|
||||
PARTITION FB14_1 CP_BASEADR<3> SHUT_UP_Z2<0> ROM_B_0_OBUF$BUF2 AUTO_CONFIG_Z2_DONE_CYCLE<1>
|
||||
AUTO_CONFIG_Z2_DONE_CYCLE<0> CP_BASEADR<7> EXP53_ CP_BASEADR<2>
|
||||
CP_BASEADR<1> CP_BASEADR<0> CFOUT_OBUF D_Z2_OUT<0>
|
||||
EXP54_ SLAVE_OBUF ROM_B_0_OBUF$BUF1 SHUT_UP_Z2<1>
|
||||
PARTITION FB12_1 LAN_RST_SM_FSM_FFd3 ROM_B_0_OBUF$BUF4 $OpTx$INV$129 EXP39_
|
||||
DQ_15_IOBUFE IDE_W_S LAN_A_INIT<6> DQ_13_IOBUFE
|
||||
LAN_CS_RST DQ_11_IOBUFE LAN_D_INIT<1> DQ_9_IOBUFE
|
||||
LAN_D_INIT<8> LAN_RST_SM_FSM_FFd1 EXP40_ IDE_ACCESS
|
||||
EXP41_ LAN_RST_SM_FSM_FFd2
|
||||
PARTITION FB13_1 EXP42_ CP_RD_OBUF Z3_DATA<31> EXP43_
|
||||
LAN_SM_FSM_FFd3 DQ_DATA<4> EXP44_ Z3_DATA<7>
|
||||
EXP45_ EXP46_ DQ_DATA<3> DQ_DATA<13>
|
||||
EXP47_ LAN_WRL_OBUF Z3_DATA<23> EXP48_
|
||||
DQ_DATA<11> DQ_DATA<12>
|
||||
PARTITION FB14_1 AUTO_CONFIG_Z2_DONE_CYCLE<1> CP_RD_S ROM_B_0_OBUF$BUF2 SHUT_UP_Z2<0>
|
||||
AUTO_CONFIG_Z2_DONE_CYCLE<0> AUTO_CONFIG_Z2_DONE<1> AUTO_CONFIG_Z2_DONE<0> EXP49_
|
||||
EXP50_ D_Z2_OUT<3> CFOUT_OBUF D_Z2_OUT<2>
|
||||
EXP51_ SLAVE_OBUF ROM_B_0_OBUF$BUF1 D_Z2_OUT<1>
|
||||
EXP52_ CP_WE_S
|
||||
PARTITION FB15_1 DQ_DATA<6> DQ_DATA<7> EXP53_ EXP54_
|
||||
EXP55_ EXP56_ DQ_DATA<1> DQ_DATA<14>
|
||||
EXP57_ DQ_DATA<15> EXP58_ ROM_B_0_OBUF$BUF9
|
||||
|
||||
PARTITION FB14_18 EXP55_
|
||||
PARTITION FB15_1 DQ_DATA<1> EXP56_ CP_RD_S LAN_SM_FSM_FFd4
|
||||
DQ_DATA<9> EXP57_ LAN_WRH_S EXP58_
|
||||
EXP59_ DQ_DATA<7> DQ_DATA<4> ROM_B_0_OBUF$BUF9
|
||||
LAN_RD_S Z3_DATA<15> Z3_DATA<14> LAN_READY
|
||||
Z3_DATA<13> LAN_WRL_S
|
||||
PARTITION FB16_1 EXP60_ Z3_DATA<12> Z3_DATA<11>
|
||||
PARTITION FB15_14 Z3_DATA<15> Z3_DATA<14> EXP59_ Z3_DATA<13>
|
||||
EXP60_
|
||||
PARTITION FB16_1 EXP61_ Z3_DATA<12> Z3_DATA<11>
|
||||
PARTITION FB16_5 Z3_DATA<26> Z3_DATA<10> Z3_DATA<25> Z3_DATA<9>
|
||||
Z3_DATA<24> ROM_B_0_OBUF$BUF3 Z3_DATA<8> Z3_DATA<18>
|
||||
Z3_DATA<17> Z3_DATA<16> EXP61_ DQ_DATA<10>
|
||||
DQ_DATA<2> EXP62_
|
||||
Z3_DATA<17> Z3_DATA<16> EXP62_ DQ_DATA<10>
|
||||
DQ_DATA<2> EXP63_
|
||||
|
||||
|
||||
+1456
-1456
File diff suppressed because it is too large
Load Diff
+3090
-3232
File diff suppressed because it is too large
Load Diff
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
@@ -1,7 +1,7 @@
|
||||
Release 8.1i - Fit P.20131013
|
||||
Copyright(c) 1995-2003 Xilinx Inc. All rights reserved
|
||||
|
||||
1- 3-2019 0:09AM
|
||||
2-19-2019 10:47PM
|
||||
|
||||
NOTE: This file is designed to be imported into a spreadsheet program
|
||||
such as Microsoft Excel for viewing, printing and sorting. The pipe '|'
|
||||
|
||||
File diff suppressed because one or more lines are too long
+1633
-1696
File diff suppressed because it is too large
Load Diff
@@ -91,6 +91,7 @@ Analyzing hierarchy for entity <LAN_IDE_CP> in library <work> (architecture <beh
|
||||
* HDL Analysis *
|
||||
=========================================================================
|
||||
Analyzing Entity <LAN_IDE_CP> in library <work> (Architecture <behavioral>).
|
||||
INFO:Xst:2679 - Register <AUTOCONFIG_Z3_ACCESS> in unit <LAN_IDE_CP> has a constant value of 0 during circuit operation. The register is replaced by logic.
|
||||
Entity <LAN_IDE_CP> analyzed. Unit <LAN_IDE_CP> generated.
|
||||
|
||||
|
||||
@@ -111,6 +112,8 @@ Synthesizing Unit <LAN_IDE_CP>.
|
||||
Related source file is "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.vhd".
|
||||
WARNING:Xst:647 - Input <IDE_WAIT> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
WARNING:Xst:647 - Input <MTCR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
WARNING:Xst:646 - Signal <SHUT_UP_Z2<2>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
|
||||
WARNING:Xst:646 - Signal <AUTOCONFIG_Z3_ACCESS> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
|
||||
INFO:Xst:1799 - State start_read_upper is never reached in FSM <LAN_SM>.
|
||||
Found finite state machine <FSM_0> for signal <LAN_SM>.
|
||||
-----------------------------------------------------------------------
|
||||
@@ -140,7 +143,6 @@ INFO:Xst:1799 - State start_read_upper is never reached in FSM <LAN_SM>.
|
||||
| Encoding | compact |
|
||||
| Implementation | automatic |
|
||||
-----------------------------------------------------------------------
|
||||
Found 16x8-bit ROM for signal <D_OUT$mux0004>.
|
||||
Found 16-bit tristate buffer for signal <D>.
|
||||
Found 16-bit tristate buffer for signal <DQ>.
|
||||
Found 1-bit tristate buffer for signal <OWN>.
|
||||
@@ -165,35 +167,31 @@ INFO:Xst:1799 - State start_read_upper is never reached in FSM <LAN_SM>.
|
||||
Found 1-bit tristate buffer for signal <A<10>>.
|
||||
Found 1-bit tristate buffer for signal <A<9>>.
|
||||
Found 1-bit tristate buffer for signal <A<8>>.
|
||||
Found 1-bit xor2 for signal <AMIGA_CLK$xor0000> created at line 181.
|
||||
Found 1-bit register for signal <AUTO_CONFIG_DONE>.
|
||||
Found 1-bit register for signal <AUTO_CONFIG_DONE_CYCLE>.
|
||||
Found 2-bit register for signal <AUTO_CONFIG_Z2_DONE>.
|
||||
Found 2-bit register for signal <AUTO_CONFIG_Z2_DONE_CYCLE>.
|
||||
Found 1-bit xor2 for signal <AMIGA_CLK$xor0000> created at line 177.
|
||||
Found 3-bit register for signal <AUTO_CONFIG_Z2_DONE>.
|
||||
Found 3-bit register for signal <AUTO_CONFIG_Z2_DONE_CYCLE>.
|
||||
Found 1-bit register for signal <AUTOCONFIG_Z2_ACCESS>.
|
||||
Found 1-bit register for signal <AUTOCONFIG_Z3_ACCESS>.
|
||||
Found 1-bit register for signal <CONFIG_READY>.
|
||||
Found 1-bit register for signal <CP_ACCESS>.
|
||||
Found 8-bit comparator equal for signal <CP_ACCESS$cmp_eq0000> created at line 297.
|
||||
Found 8-bit comparator equal for signal <CP_ACCESS$cmp_eq0000> created at line 291.
|
||||
Found 8-bit register for signal <CP_BASEADR>.
|
||||
Found 1-bit register for signal <CP_RD_S>.
|
||||
Found 1-bit register for signal <CP_WE_QUIRK>.
|
||||
Found 1-bit register for signal <CP_WE_S>.
|
||||
Found 8-bit register for signal <D_OUT>.
|
||||
Found 4-bit register for signal <D_Z2_OUT>.
|
||||
Found 4-bit comparator less for signal <DQ$cmp_lt0000> created at line 675.
|
||||
Found 4-bit comparator less for signal <DQ$cmp_lt0000> created at line 636.
|
||||
Found 16-bit register for signal <DQ_DATA>.
|
||||
Found 1-bit register for signal <DQ_SWAP>.
|
||||
Found 2-bit comparator less for signal <DQ_SWAP$cmp_lt0000> created at line 269.
|
||||
Found 2-bit comparator less for signal <DQ_SWAP$cmp_lt0000> created at line 262.
|
||||
Found 1-bit register for signal <IDE_ACCESS>.
|
||||
Found 8-bit comparator equal for signal <IDE_ACCESS$cmp_eq0000> created at line 304.
|
||||
Found 8-bit comparator equal for signal <IDE_ACCESS$cmp_eq0000> created at line 298.
|
||||
Found 8-bit register for signal <IDE_BASEADR>.
|
||||
Found 1-bit register for signal <IDE_ENABLE>.
|
||||
Found 1-bit register for signal <IDE_R_S>.
|
||||
Found 1-bit register for signal <IDE_W_S>.
|
||||
Found 14-bit register for signal <LAN_A_INIT>.
|
||||
Found 1-bit register for signal <LAN_ACCESS>.
|
||||
Found 16-bit comparator equal for signal <LAN_ACCESS$cmp_eq0000> created at line 268.
|
||||
Found 16-bit comparator equal for signal <LAN_ACCESS$cmp_eq0000> created at line 261.
|
||||
Found 16-bit register for signal <LAN_BASEADR>.
|
||||
Found 1-bit register for signal <LAN_CS_RST>.
|
||||
Found 16-bit register for signal <LAN_D_INIT>.
|
||||
@@ -202,21 +200,19 @@ INFO:Xst:1799 - State start_read_upper is never reached in FSM <LAN_SM>.
|
||||
Found 1-bit register for signal <LAN_IRQ_OUT>.
|
||||
Found 1-bit register for signal <LAN_RD_S>.
|
||||
Found 1-bit register for signal <LAN_READY>.
|
||||
Found 2-bit comparator less for signal <LAN_SM$cmp_lt0000> created at line 411.
|
||||
Found 2-bit comparator less for signal <LAN_SM$cmp_lt0000> created at line 405.
|
||||
Found 1-bit register for signal <LAN_SM_RST>.
|
||||
Found 1-bit register for signal <LAN_WR_RST>.
|
||||
Found 1-bit register for signal <LAN_WRH_S>.
|
||||
Found 1-bit register for signal <LAN_WRL_S>.
|
||||
Found 1-bit register for signal <ROM_OE_S>.
|
||||
Found 1-bit register for signal <SHUT_UP>.
|
||||
Found 2-bit register for signal <SHUT_UP_Z2>.
|
||||
Found 2-bit register for signal <SHUT_UP_Z2<1:0>>.
|
||||
Found 1-bit register for signal <Z3_A_LOW>.
|
||||
Found 14-bit register for signal <Z3_ADR>.
|
||||
Found 32-bit register for signal <Z3_DATA>.
|
||||
Summary:
|
||||
inferred 2 Finite State Machine(s).
|
||||
inferred 1 ROM(s).
|
||||
inferred 61 D-type flip-flop(s).
|
||||
inferred 74 D-type flip-flop(s).
|
||||
inferred 6 Comparator(s).
|
||||
inferred 1 Xor(s).
|
||||
inferred 57 Tristate(s).
|
||||
@@ -227,15 +223,13 @@ Unit <LAN_IDE_CP> synthesized.
|
||||
HDL Synthesis Report
|
||||
|
||||
Macro Statistics
|
||||
# ROMs : 1
|
||||
16x8-bit ROM : 1
|
||||
# Registers : 74
|
||||
1-bit register : 64
|
||||
# Registers : 85
|
||||
1-bit register : 77
|
||||
14-bit register : 2
|
||||
16-bit register : 3
|
||||
2-bit register : 1
|
||||
16-bit register : 2
|
||||
3-bit register : 1
|
||||
4-bit register : 1
|
||||
8-bit register : 3
|
||||
8-bit register : 2
|
||||
# Comparators : 6
|
||||
16-bit comparator equal : 1
|
||||
2-bit comparator less : 2
|
||||
@@ -312,10 +306,8 @@ Advanced HDL Synthesis Report
|
||||
|
||||
Macro Statistics
|
||||
# FSMs : 2
|
||||
# ROMs : 1
|
||||
16x8-bit ROM : 1
|
||||
# Registers : 61
|
||||
Flip-Flops : 61
|
||||
# Registers : 74
|
||||
Flip-Flops : 74
|
||||
# Comparators : 3
|
||||
16-bit comparator equal : 1
|
||||
8-bit comparator equal : 2
|
||||
@@ -351,28 +343,22 @@ INFO:Xst:2261 - The FF/Latch <LAN_D_INIT_8> in Unit <LAN_IDE_CP> is equivalent t
|
||||
INFO:Xst:2261 - The FF/Latch <LAN_D_INIT_1> in Unit <LAN_IDE_CP> is equivalent to the following 2 FFs/Latches, which will be removed : <LAN_D_INIT_4> <LAN_D_INIT_9>
|
||||
|
||||
Optimizing unit <LAN_IDE_CP> ...
|
||||
implementation constraint: INIT=s : D_OUT_4
|
||||
implementation constraint: INIT=s : SHUT_UP_Z2_0
|
||||
implementation constraint: INIT=r : AUTO_CONFIG_Z2_DONE_CYCLE_0
|
||||
implementation constraint: INIT=r : AUTO_CONFIG_Z2_DONE_CYCLE_1
|
||||
implementation constraint: INIT=r : AUTO_CONFIG_Z2_DONE_1
|
||||
implementation constraint: INIT=s : SHUT_UP_Z2_1
|
||||
implementation constraint: INIT=s : D_Z2_OUT_3
|
||||
implementation constraint: INIT=s : LAN_A_INIT_3
|
||||
implementation constraint: INIT=s : D_Z2_OUT_2
|
||||
implementation constraint: INIT=s : LAN_A_INIT_6
|
||||
implementation constraint: INIT=s : D_Z2_OUT_1
|
||||
implementation constraint: INIT=s : D_Z2_OUT_0
|
||||
implementation constraint: INIT=s : D_OUT_7
|
||||
implementation constraint: INIT=s : D_OUT_6
|
||||
implementation constraint: INIT=s : D_OUT_5
|
||||
implementation constraint: INIT=s : D_OUT_3
|
||||
implementation constraint: INIT=r : AUTO_CONFIG_Z2_DONE_2
|
||||
implementation constraint: INIT=r : LAN_D_INIT_1
|
||||
implementation constraint: INIT=s : D_OUT_2
|
||||
implementation constraint: INIT=s : D_OUT_1
|
||||
implementation constraint: INIT=s : D_OUT_0
|
||||
implementation constraint: INIT=r : AUTO_CONFIG_Z2_DONE_1
|
||||
implementation constraint: INIT=r : LAN_D_INIT_8
|
||||
implementation constraint: INIT=s : SHUT_UP_Z2_0
|
||||
implementation constraint: INIT=r : AUTO_CONFIG_Z2_DONE_0
|
||||
implementation constraint: INIT=s : SHUT_UP_Z2_1
|
||||
implementation constraint: INIT=r : LAN_D_INIT_8
|
||||
implementation constraint: INIT=r : AUTO_CONFIG_Z2_DONE_CYCLE_2
|
||||
implementation constraint: INIT=r : AUTO_CONFIG_Z2_DONE_CYCLE_1
|
||||
implementation constraint: INIT=r : LAN_RST_SM_FSM_FFd1
|
||||
implementation constraint: INIT=r : LAN_RST_SM_FSM_FFd2
|
||||
implementation constraint: INIT=r : LAN_RST_SM_FSM_FFd3
|
||||
@@ -411,23 +397,24 @@ Design Statistics
|
||||
# IOs : 116
|
||||
|
||||
Cell Usage :
|
||||
# BELS : 1268
|
||||
# AND2 : 378
|
||||
# AND3 : 53
|
||||
# AND4 : 11
|
||||
# AND8 : 6
|
||||
# BELS : 1145
|
||||
# AND2 : 345
|
||||
# AND3 : 41
|
||||
# AND4 : 15
|
||||
# AND5 : 1
|
||||
# AND8 : 4
|
||||
# GND : 1
|
||||
# INV : 468
|
||||
# OR2 : 278
|
||||
# OR3 : 21
|
||||
# OR4 : 1
|
||||
# XOR2 : 51
|
||||
# FlipFlops/Latches : 151
|
||||
# INV : 419
|
||||
# OR2 : 250
|
||||
# OR3 : 17
|
||||
# OR4 : 2
|
||||
# XOR2 : 50
|
||||
# FlipFlops/Latches : 141
|
||||
# FD : 4
|
||||
# FDC : 22
|
||||
# FDC : 21
|
||||
# FDCE : 7
|
||||
# FDP : 49
|
||||
# FDPE : 69
|
||||
# FDP : 41
|
||||
# FDPE : 68
|
||||
# IO Buffers : 114
|
||||
# IBUF : 24
|
||||
# IOBUFE : 48
|
||||
@@ -436,14 +423,14 @@ Cell Usage :
|
||||
=========================================================================
|
||||
|
||||
|
||||
Total REAL time to Xst completion: 19.00 secs
|
||||
Total CPU time to Xst completion: 18.89 secs
|
||||
Total REAL time to Xst completion: 18.00 secs
|
||||
Total CPU time to Xst completion: 18.70 secs
|
||||
|
||||
-->
|
||||
|
||||
Total memory usage is 4534828 kilobytes
|
||||
|
||||
Number of errors : 0 ( 0 filtered)
|
||||
Number of warnings : 46 ( 0 filtered)
|
||||
Number of infos : 10 ( 0 filtered)
|
||||
Number of warnings : 48 ( 0 filtered)
|
||||
Number of infos : 11 ( 0 filtered)
|
||||
|
||||
|
||||
@@ -120,35 +120,8 @@ TS_CLK_EXT:FROM:LAN_SM_FSM_FFd3.Q:TO:Z3_DATA<9>.CE:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd1.Q:TO:Z3_DATA<9>.CE:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd2.Q:TO:Z3_DATA<9>.CE:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd4.Q:TO:Z3_DATA<9>.CE:400
|
||||
TS_CLK_EXT:FROM:AUTO_CONFIG_DONE_CYCLE.Q:TO:AUTO_CONFIG_DONE.D:400
|
||||
TS_CLK_EXT:FROM:AUTO_CONFIG_DONE_CYCLE.Q:TO:AUTO_CONFIG_DONE_CYCLE.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<16>.Q:TO:LAN_BASEADR<0>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<26>.Q:TO:LAN_BASEADR<10>.D:400
|
||||
TS_CLK_EXT:FROM:D_OUT<2>.Q:TO:LAN_BASEADR<10>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<27>.Q:TO:LAN_BASEADR<11>.D:400
|
||||
TS_CLK_EXT:FROM:D_OUT<3>.Q:TO:LAN_BASEADR<11>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<28>.Q:TO:LAN_BASEADR<12>.D:400
|
||||
TS_CLK_EXT:FROM:D_OUT<4>.Q:TO:LAN_BASEADR<12>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<29>.Q:TO:LAN_BASEADR<13>.D:400
|
||||
TS_CLK_EXT:FROM:D_OUT<5>.Q:TO:LAN_BASEADR<13>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<30>.Q:TO:LAN_BASEADR<14>.D:400
|
||||
TS_CLK_EXT:FROM:D_OUT<6>.Q:TO:LAN_BASEADR<14>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<31>.Q:TO:LAN_BASEADR<15>.D:400
|
||||
TS_CLK_EXT:FROM:D_OUT<7>.Q:TO:LAN_BASEADR<15>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<17>.Q:TO:LAN_BASEADR<1>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<18>.Q:TO:LAN_BASEADR<2>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<19>.Q:TO:LAN_BASEADR<3>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<20>.Q:TO:LAN_BASEADR<4>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<21>.Q:TO:LAN_BASEADR<5>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<22>.Q:TO:LAN_BASEADR<6>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<23>.Q:TO:LAN_BASEADR<7>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<24>.Q:TO:LAN_BASEADR<8>.D:400
|
||||
TS_CLK_EXT:FROM:D_OUT<0>.Q:TO:LAN_BASEADR<8>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<25>.Q:TO:LAN_BASEADR<9>.D:400
|
||||
TS_CLK_EXT:FROM:D_OUT<1>.Q:TO:LAN_BASEADR<9>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<15>.Q:TO:LAN_INT_ENABLE.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<31>.Q:TO:LAN_INT_ENABLE.D:400
|
||||
TS_CLK_EXT:FROM:D_OUT<7>.Q:TO:LAN_INT_ENABLE.D:400
|
||||
TS_CLK_EXT:FROM:LAN_INT_ENABLE.Q:TO:LAN_INT_ENABLE.D:400
|
||||
TS_CLK_EXT:FROM:LAN_IRQ_D0.Q:TO:LAN_IRQ_OUT.D:400
|
||||
TS_CLK_EXT:FROM:LAN_IRQ_OUT.Q:TO:LAN_IRQ_OUT.D:400
|
||||
@@ -299,7 +272,6 @@ TS_CLK_EXT:FROM:LAN_SM_FSM_FFd4.Q:TO:DQ_DATA<0>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd3.Q:TO:DQ_DATA<0>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd2.Q:TO:DQ_DATA<0>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<24>.Q:TO:DQ_DATA<0>.D:400
|
||||
TS_CLK_EXT:FROM:D_OUT<0>.Q:TO:DQ_DATA<0>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<16>.Q:TO:DQ_DATA<0>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<0>.Q:TO:DQ_DATA<0>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<8>.Q:TO:DQ_DATA<0>.D:400
|
||||
@@ -311,7 +283,6 @@ TS_CLK_EXT:FROM:LAN_SM_FSM_FFd3.Q:TO:DQ_DATA<10>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd2.Q:TO:DQ_DATA<10>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<18>.Q:TO:DQ_DATA<10>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<26>.Q:TO:DQ_DATA<10>.D:400
|
||||
TS_CLK_EXT:FROM:D_OUT<2>.Q:TO:DQ_DATA<10>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<10>.Q:TO:DQ_DATA<10>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<2>.Q:TO:DQ_DATA<10>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_RST.Q:TO:DQ_DATA<10>.SETF:400
|
||||
@@ -322,7 +293,6 @@ TS_CLK_EXT:FROM:LAN_SM_FSM_FFd3.Q:TO:DQ_DATA<11>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd2.Q:TO:DQ_DATA<11>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<19>.Q:TO:DQ_DATA<11>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<27>.Q:TO:DQ_DATA<11>.D:400
|
||||
TS_CLK_EXT:FROM:D_OUT<3>.Q:TO:DQ_DATA<11>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<11>.Q:TO:DQ_DATA<11>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<3>.Q:TO:DQ_DATA<11>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_RST.Q:TO:DQ_DATA<11>.SETF:400
|
||||
@@ -333,7 +303,6 @@ TS_CLK_EXT:FROM:LAN_SM_FSM_FFd3.Q:TO:DQ_DATA<12>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd2.Q:TO:DQ_DATA<12>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<20>.Q:TO:DQ_DATA<12>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<28>.Q:TO:DQ_DATA<12>.D:400
|
||||
TS_CLK_EXT:FROM:D_OUT<4>.Q:TO:DQ_DATA<12>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<12>.Q:TO:DQ_DATA<12>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<4>.Q:TO:DQ_DATA<12>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_RST.Q:TO:DQ_DATA<12>.SETF:400
|
||||
@@ -344,7 +313,6 @@ TS_CLK_EXT:FROM:LAN_SM_FSM_FFd3.Q:TO:DQ_DATA<13>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd2.Q:TO:DQ_DATA<13>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<21>.Q:TO:DQ_DATA<13>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<29>.Q:TO:DQ_DATA<13>.D:400
|
||||
TS_CLK_EXT:FROM:D_OUT<5>.Q:TO:DQ_DATA<13>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<13>.Q:TO:DQ_DATA<13>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<5>.Q:TO:DQ_DATA<13>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_RST.Q:TO:DQ_DATA<13>.SETF:400
|
||||
@@ -355,7 +323,6 @@ TS_CLK_EXT:FROM:LAN_SM_FSM_FFd3.Q:TO:DQ_DATA<14>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd2.Q:TO:DQ_DATA<14>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<22>.Q:TO:DQ_DATA<14>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<30>.Q:TO:DQ_DATA<14>.D:400
|
||||
TS_CLK_EXT:FROM:D_OUT<6>.Q:TO:DQ_DATA<14>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<14>.Q:TO:DQ_DATA<14>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<6>.Q:TO:DQ_DATA<14>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_RST.Q:TO:DQ_DATA<14>.SETF:400
|
||||
@@ -366,7 +333,6 @@ TS_CLK_EXT:FROM:LAN_SM_FSM_FFd3.Q:TO:DQ_DATA<15>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd2.Q:TO:DQ_DATA<15>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<23>.Q:TO:DQ_DATA<15>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<31>.Q:TO:DQ_DATA<15>.D:400
|
||||
TS_CLK_EXT:FROM:D_OUT<7>.Q:TO:DQ_DATA<15>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<15>.Q:TO:DQ_DATA<15>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<7>.Q:TO:DQ_DATA<15>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_RST.Q:TO:DQ_DATA<15>.SETF:400
|
||||
@@ -376,7 +342,6 @@ TS_CLK_EXT:FROM:LAN_SM_FSM_FFd4.Q:TO:DQ_DATA<1>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd3.Q:TO:DQ_DATA<1>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd2.Q:TO:DQ_DATA<1>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<25>.Q:TO:DQ_DATA<1>.D:400
|
||||
TS_CLK_EXT:FROM:D_OUT<1>.Q:TO:DQ_DATA<1>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<17>.Q:TO:DQ_DATA<1>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<1>.Q:TO:DQ_DATA<1>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<9>.Q:TO:DQ_DATA<1>.D:400
|
||||
@@ -388,7 +353,6 @@ TS_CLK_EXT:FROM:LAN_SM_FSM_FFd3.Q:TO:DQ_DATA<2>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd2.Q:TO:DQ_DATA<2>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<18>.Q:TO:DQ_DATA<2>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<26>.Q:TO:DQ_DATA<2>.D:400
|
||||
TS_CLK_EXT:FROM:D_OUT<2>.Q:TO:DQ_DATA<2>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<10>.Q:TO:DQ_DATA<2>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<2>.Q:TO:DQ_DATA<2>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_RST.Q:TO:DQ_DATA<2>.SETF:400
|
||||
@@ -399,7 +363,6 @@ TS_CLK_EXT:FROM:LAN_SM_FSM_FFd3.Q:TO:DQ_DATA<3>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd2.Q:TO:DQ_DATA<3>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<19>.Q:TO:DQ_DATA<3>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<27>.Q:TO:DQ_DATA<3>.D:400
|
||||
TS_CLK_EXT:FROM:D_OUT<3>.Q:TO:DQ_DATA<3>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<11>.Q:TO:DQ_DATA<3>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<3>.Q:TO:DQ_DATA<3>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_RST.Q:TO:DQ_DATA<3>.SETF:400
|
||||
@@ -410,7 +373,6 @@ TS_CLK_EXT:FROM:LAN_SM_FSM_FFd3.Q:TO:DQ_DATA<4>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd2.Q:TO:DQ_DATA<4>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<20>.Q:TO:DQ_DATA<4>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<28>.Q:TO:DQ_DATA<4>.D:400
|
||||
TS_CLK_EXT:FROM:D_OUT<4>.Q:TO:DQ_DATA<4>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<12>.Q:TO:DQ_DATA<4>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<4>.Q:TO:DQ_DATA<4>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_RST.Q:TO:DQ_DATA<4>.SETF:400
|
||||
@@ -421,7 +383,6 @@ TS_CLK_EXT:FROM:LAN_SM_FSM_FFd3.Q:TO:DQ_DATA<5>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd2.Q:TO:DQ_DATA<5>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<21>.Q:TO:DQ_DATA<5>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<29>.Q:TO:DQ_DATA<5>.D:400
|
||||
TS_CLK_EXT:FROM:D_OUT<5>.Q:TO:DQ_DATA<5>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<13>.Q:TO:DQ_DATA<5>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<5>.Q:TO:DQ_DATA<5>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_RST.Q:TO:DQ_DATA<5>.SETF:400
|
||||
@@ -432,7 +393,6 @@ TS_CLK_EXT:FROM:LAN_SM_FSM_FFd3.Q:TO:DQ_DATA<6>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd2.Q:TO:DQ_DATA<6>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<22>.Q:TO:DQ_DATA<6>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<30>.Q:TO:DQ_DATA<6>.D:400
|
||||
TS_CLK_EXT:FROM:D_OUT<6>.Q:TO:DQ_DATA<6>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<14>.Q:TO:DQ_DATA<6>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<6>.Q:TO:DQ_DATA<6>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_RST.Q:TO:DQ_DATA<6>.SETF:400
|
||||
@@ -443,7 +403,6 @@ TS_CLK_EXT:FROM:LAN_SM_FSM_FFd3.Q:TO:DQ_DATA<7>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd2.Q:TO:DQ_DATA<7>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<23>.Q:TO:DQ_DATA<7>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<31>.Q:TO:DQ_DATA<7>.D:400
|
||||
TS_CLK_EXT:FROM:D_OUT<7>.Q:TO:DQ_DATA<7>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<15>.Q:TO:DQ_DATA<7>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<7>.Q:TO:DQ_DATA<7>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_RST.Q:TO:DQ_DATA<7>.SETF:400
|
||||
@@ -453,7 +412,6 @@ TS_CLK_EXT:FROM:LAN_SM_FSM_FFd4.Q:TO:DQ_DATA<8>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd3.Q:TO:DQ_DATA<8>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd2.Q:TO:DQ_DATA<8>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<24>.Q:TO:DQ_DATA<8>.D:400
|
||||
TS_CLK_EXT:FROM:D_OUT<0>.Q:TO:DQ_DATA<8>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<16>.Q:TO:DQ_DATA<8>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<0>.Q:TO:DQ_DATA<8>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<8>.Q:TO:DQ_DATA<8>.D:400
|
||||
@@ -464,7 +422,6 @@ TS_CLK_EXT:FROM:LAN_SM_FSM_FFd4.Q:TO:DQ_DATA<9>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd3.Q:TO:DQ_DATA<9>.D:400
|
||||
TS_CLK_EXT:FROM:LAN_SM_FSM_FFd2.Q:TO:DQ_DATA<9>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<25>.Q:TO:DQ_DATA<9>.D:400
|
||||
TS_CLK_EXT:FROM:D_OUT<1>.Q:TO:DQ_DATA<9>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<17>.Q:TO:DQ_DATA<9>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<1>.Q:TO:DQ_DATA<9>.D:400
|
||||
TS_CLK_EXT:FROM:Z3_DATA<9>.Q:TO:DQ_DATA<9>.D:400
|
||||
|
||||
@@ -124,14 +124,10 @@ architecture Behavioral of LAN_IDE_CP is
|
||||
signal CP_BASEADR:STD_LOGIC_VECTOR(7 downto 0);
|
||||
signal LAN_ACCESS: STD_LOGIC;
|
||||
signal DQ_SWAP: STD_LOGIC;
|
||||
signal D_OUT:STD_LOGIC_VECTOR(7 downto 0):=x"FF";
|
||||
signal D_Z2_OUT:STD_LOGIC_VECTOR(3 downto 0):=x"F";
|
||||
signal AUTO_CONFIG_DONE:STD_LOGIC;
|
||||
signal AUTO_CONFIG_DONE_CYCLE:STD_LOGIC;
|
||||
signal SHUT_UP:STD_LOGIC;
|
||||
signal AUTO_CONFIG_Z2_DONE:STD_LOGIC_VECTOR(1 downto 0):="00";
|
||||
signal AUTO_CONFIG_Z2_DONE_CYCLE:STD_LOGIC_VECTOR(1 downto 0):="00";
|
||||
signal SHUT_UP_Z2:STD_LOGIC_VECTOR(1 downto 0):="11";
|
||||
signal AUTO_CONFIG_Z2_DONE:STD_LOGIC_VECTOR(2 downto 0):="000";
|
||||
signal AUTO_CONFIG_Z2_DONE_CYCLE:STD_LOGIC_VECTOR(2 downto 0):="000";
|
||||
signal SHUT_UP_Z2:STD_LOGIC_VECTOR(2 downto 0):="111";
|
||||
signal LAN_BASEADR:STD_LOGIC_VECTOR(15 downto 0);
|
||||
signal LAN_INT_ENABLE: std_logic;
|
||||
signal LAN_RD_S: std_logic;
|
||||
@@ -163,8 +159,8 @@ architecture Behavioral of LAN_IDE_CP is
|
||||
signal LAN_D_INIT:STD_LOGIC_VECTOR(15 downto 0) := x"0000";
|
||||
constant LAN_A_CLRREG:STD_LOGIC_VECTOR(13 downto 0) :="11"&x"FF7";
|
||||
constant LAN_A_SETREG:STD_LOGIC_VECTOR(13 downto 0) :="11"&x"FB7";
|
||||
constant LAN_D_SET:STD_LOGIC_VECTOR(15 downto 0) := "0000001000010010"; --25MHz
|
||||
constant LAN_D_CLR:STD_LOGIC_VECTOR(15 downto 0) := "0000110100000000"; --25MHz
|
||||
constant LAN_D_SET:STD_LOGIC_VECTOR(15 downto 0) := "0000001000010010"; --25MHz SET-MASK
|
||||
constant LAN_D_CLR:STD_LOGIC_VECTOR(15 downto 0) := "0000110100000000"; --25MHz CLEAR-MASK
|
||||
|
||||
Function to_std_logic(X: in Boolean) return Std_Logic is
|
||||
variable ret : std_logic;
|
||||
@@ -245,27 +241,24 @@ begin
|
||||
end if;
|
||||
end process clock_init;
|
||||
|
||||
ADDRESS_Z3_DECODE: process(reset,FCS)
|
||||
ADDRESS_Z3_DECODE: process(AS,reset,FCS)
|
||||
begin
|
||||
if(reset ='0')then
|
||||
if(--AS ='0' or
|
||||
reset='0')then
|
||||
AUTOCONFIG_Z3_ACCESS <= '0';
|
||||
LAN_ACCESS <= '0';
|
||||
DQ_SWAP <= '1';
|
||||
Z3_ADR <= (others => '1');
|
||||
|
||||
elsif(falling_edge(FCS))then
|
||||
|
||||
Z3_ADR(15 downto 2) <= A(15 downto 2);-- latch the whole address for the whole cycle
|
||||
|
||||
|
||||
--use D(15 downto 8)& A(23 downto 16) = A(31 downto 16) for quick response
|
||||
--AUTOCONFIG_Z3_ACCESS
|
||||
if(Z3='1' and (D(15 downto 8)& A(23 downto 16)) = x"FF00" and AUTO_CONFIG_DONE = '0' and CFIN='0')then
|
||||
AUTOCONFIG_Z3_ACCESS <= '1';
|
||||
else
|
||||
AUTOCONFIG_Z3_ACCESS <= '0';
|
||||
end if;
|
||||
|
||||
--lan base
|
||||
if(Z3='1' and (D(15 downto 8) & A(23 downto 16)) = LAN_BASEADR and SHUT_UP='0' )then
|
||||
if(Z3='1' and (D(15 downto 8) & A(23 downto 16)) = LAN_BASEADR and SHUT_UP_Z2(0)='0' )then
|
||||
if(A(14 downto 13)<"11")then
|
||||
DQ_SWAP <= '1';
|
||||
else
|
||||
@@ -279,15 +272,16 @@ begin
|
||||
end if;
|
||||
end process ADDRESS_Z3_DECODE;
|
||||
|
||||
ADDRESS_Z2_DECODE: process(reset,AS)
|
||||
ADDRESS_Z2_DECODE: process(FCS,reset,AS)
|
||||
begin
|
||||
if(reset ='0')then
|
||||
if(--FCS ='0' or
|
||||
reset='0')then
|
||||
AUTOCONFIG_Z2_ACCESS <= '0';
|
||||
IDE_ACCESS <= '0';
|
||||
CP_ACCESS <= '0';
|
||||
elsif(falling_edge(AS))then
|
||||
|
||||
if(A(23 downto 16) = x"E8" and AUTO_CONFIG_Z2_DONE /= "11" and CFIN='0')then
|
||||
if(A(23 downto 16) = x"E8" and AUTO_CONFIG_Z2_DONE /= "111" and CFIN='0')then
|
||||
AUTOCONFIG_Z2_ACCESS <= '1';
|
||||
else
|
||||
AUTOCONFIG_Z2_ACCESS <= '0';
|
||||
@@ -500,63 +494,18 @@ begin
|
||||
end if;
|
||||
end process lan_rw_gen;
|
||||
|
||||
|
||||
--AUTOCONFIG_Z3_ACCESS
|
||||
AUTOCONFIG_Z3_ACCESS_proc: process (reset, CLK_EXT)
|
||||
begin
|
||||
if reset = '0' then
|
||||
-- reset active ...
|
||||
AUTO_CONFIG_DONE_CYCLE <='0';
|
||||
D_OUT<=x"FF";
|
||||
SHUT_UP <='1';
|
||||
LAN_BASEADR<=x"FFFF";
|
||||
AUTO_CONFIG_DONE <='0';
|
||||
elsif rising_edge(CLK_EXT) then -- no reset, so wait for rising edge of the clock
|
||||
--default value
|
||||
D_OUT<=x"FF";
|
||||
if(FCS='1')then
|
||||
AUTO_CONFIG_DONE <= AUTO_CONFIG_DONE_CYCLE;
|
||||
elsif(AUTOCONFIG_Z3_ACCESS= '1' and Z3_DS(3)='0' ) then
|
||||
case Z3_ADR(8 downto 2) is
|
||||
when "0000000" => D_OUT <= "10000001" ; --Z3, No mem, no Rom, single, board, 64kb
|
||||
when "1000000" => D_OUT <= "00010001" ; --Z3, No mem, no Rom, single, board, 64kb
|
||||
when "0000001" => D_OUT <= "10000100" ; --ProductID: 7B->10000100
|
||||
when "1000001" => D_OUT <= "01000100" ; --ProductID: 7B->10000100
|
||||
when "0000010" => D_OUT <= "11101101" ; --Flags
|
||||
when "1000010" => D_OUT <= "11011101" ; --Flags
|
||||
when "0000100" => D_OUT <= "11110101" ; --Ventor ID 0/1
|
||||
when "1000100" => D_OUT <= "01010101" ; --Ventor ID 0/1
|
||||
when "0000101" => D_OUT <= "11100011" ; --Ventor ID 2/3 : $0A1C: A1K.org
|
||||
when "1000101" => D_OUT <= "00110011" ; --Ventor ID 2/3 : $0A1C: A1K.org
|
||||
when "0010001" =>
|
||||
if(RW='0')then
|
||||
LAN_BASEADR(15 downto 0) <= Z3_DATA_IN(31 downto 16); --Base address
|
||||
SHUT_UP <='0'; --enable board
|
||||
AUTO_CONFIG_DONE_CYCLE <= '1'; --done here
|
||||
end if;
|
||||
when "0010011" =>
|
||||
if(RW='0')then
|
||||
AUTO_CONFIG_DONE_CYCLE <= '1'; --done here
|
||||
end if;
|
||||
when others =>
|
||||
--nothing
|
||||
end case;
|
||||
end if;
|
||||
end if;
|
||||
end process AUTOCONFIG_Z3_ACCESS_proc; --- that's all
|
||||
|
||||
|
||||
--autoconfig
|
||||
autoconfig_proc: process (reset, AMIGA_CLK)
|
||||
begin
|
||||
if reset = '0' then
|
||||
-- reset active ...
|
||||
AUTO_CONFIG_Z2_DONE_CYCLE <="00";
|
||||
AUTO_CONFIG_Z2_DONE_CYCLE <="000";
|
||||
D_Z2_OUT<="1111";
|
||||
SHUT_UP_Z2 <="11";
|
||||
SHUT_UP_Z2 <="111";
|
||||
IDE_BASEADR<=x"FF";
|
||||
CP_BASEADR<=x"FF";
|
||||
AUTO_CONFIG_Z2_DONE <="00";
|
||||
AUTO_CONFIG_Z2_DONE <="000";
|
||||
LAN_BASEADR<=x"FFFF";
|
||||
elsif falling_edge(AMIGA_CLK) then -- no reset, so wait for rising edge of the clock
|
||||
D_Z2_OUT<="1111";
|
||||
if(AS='1')then
|
||||
@@ -565,38 +514,42 @@ begin
|
||||
case A(6 downto 1) is
|
||||
when "000000" =>
|
||||
if(AUTO_CONFIG_Z2_DONE(0) = '0')then
|
||||
D_Z2_OUT <= "1000" ; --ZII, No-System-Memory, no ROM
|
||||
elsif(AUTO_CONFIG_Z2_DONE(1) = '0')then
|
||||
D_Z2_OUT <= "1100" ; --ZII, No-System-Memory, no ROM
|
||||
else
|
||||
D_Z2_OUT <= "1101" ; --ZII, no System-Memory, (perhaps)ROM
|
||||
end if;
|
||||
when "000001" => D_Z2_OUT <= "0001" ; --one Card, 64KB =001
|
||||
when "000010" =>
|
||||
if(AUTO_CONFIG_Z2_DONE(0) = '0')then
|
||||
if(AUTO_CONFIG_Z2_DONE(0) = '0' or AUTO_CONFIG_Z2_DONE(1) = '0')then
|
||||
D_Z2_OUT <= "1000" ; --ProductID high nibble : 7->1000
|
||||
else
|
||||
D_Z2_OUT <= "1111" ; --ProductID high nibble : 0->1111
|
||||
end if;
|
||||
when "000011" =>
|
||||
if(AUTO_CONFIG_Z2_DONE(0) = '0')then
|
||||
D_Z2_OUT <= "0100" ; --ProductID low nibble: B->0100
|
||||
elsif(AUTO_CONFIG_Z2_DONE(1) = '0')then
|
||||
D_Z2_OUT <= "0011" ; --ProductID low nibble: C->0011
|
||||
else
|
||||
D_Z2_OUT <= "1001" ; --ProductID low nibble: 6->1001
|
||||
end if;
|
||||
when "001000" => D_Z2_OUT <= "1111" ; --Ventor ID 0
|
||||
when "001001" =>
|
||||
if(AUTO_CONFIG_Z2_DONE(0) = '0')then
|
||||
if(AUTO_CONFIG_Z2_DONE(0) = '0' or AUTO_CONFIG_Z2_DONE(1) = '0')then
|
||||
D_Z2_OUT <= "0101" ; --Ventor ID 1
|
||||
else
|
||||
D_Z2_OUT <= "0111" ; --Ventor ID 1
|
||||
end if;
|
||||
when "001010" =>
|
||||
if(AUTO_CONFIG_Z2_DONE(0) = '0')then
|
||||
if(AUTO_CONFIG_Z2_DONE(0) = '0' or AUTO_CONFIG_Z2_DONE(1) = '0')then
|
||||
D_Z2_OUT <= "1110" ; --Ventor ID 2
|
||||
else
|
||||
D_Z2_OUT <= "1101" ; --Ventor ID 2
|
||||
end if;
|
||||
when "001011" =>
|
||||
if(AUTO_CONFIG_Z2_DONE(0) = '0')then
|
||||
if(AUTO_CONFIG_Z2_DONE(0) = '0' or AUTO_CONFIG_Z2_DONE(1) = '0')then
|
||||
D_Z2_OUT <= "0011" ; --Ventor ID 3 : $0A1C: A1K.org
|
||||
else
|
||||
D_Z2_OUT <= "0011" ; --Ventor ID 3 : $082C: BSC
|
||||
@@ -618,19 +571,26 @@ begin
|
||||
else
|
||||
D_Z2_OUT <= "1111" ; --Rom vector low byte low nibble
|
||||
end if;
|
||||
when "100000" => D_Z2_OUT <= "0000" ; --Interrupt config: all zero
|
||||
when "100001" => D_Z2_OUT <= "0000" ; --Interrupt config: all zero
|
||||
when "100010" =>
|
||||
if(RW='0')then
|
||||
if(AUTO_CONFIG_Z2_DONE(1) = '0')then
|
||||
LAN_BASEADR(15 downto 8) <= D(15 downto 8); --Base adress
|
||||
end if;
|
||||
end if;
|
||||
when "100100" =>
|
||||
D_Z2_OUT <= "1111" ;
|
||||
if(RW='0')then
|
||||
if(AUTO_CONFIG_Z2_DONE(0) = '0')then
|
||||
CP_BASEADR(7 downto 0) <= D(15 downto 8); --Base adress
|
||||
LAN_BASEADR(7 downto 0) <= D(15 downto 8); --Base adress
|
||||
SHUT_UP_Z2(0) <='0'; --enable board
|
||||
AUTO_CONFIG_Z2_DONE_CYCLE(0) <= '1'; --done here
|
||||
elsif(AUTO_CONFIG_Z2_DONE(1) = '0')then
|
||||
IDE_BASEADR(7 downto 0) <= D(15 downto 8); --Base adress
|
||||
SHUT_UP_Z2(1) <= '0'; --enable board
|
||||
CP_BASEADR(7 downto 0) <= D(15 downto 8); --Base adress
|
||||
SHUT_UP_Z2(1) <='0'; --enable board
|
||||
AUTO_CONFIG_Z2_DONE_CYCLE(1) <= '1'; --done here
|
||||
elsif(AUTO_CONFIG_Z2_DONE(2) = '0')then
|
||||
IDE_BASEADR(7 downto 0) <= D(15 downto 8); --Base adress
|
||||
SHUT_UP_Z2(2) <= '0'; --enable board
|
||||
AUTO_CONFIG_Z2_DONE_CYCLE(2) <= '1'; --done here
|
||||
end if;
|
||||
end if;
|
||||
when "100110" =>
|
||||
@@ -640,6 +600,8 @@ begin
|
||||
AUTO_CONFIG_Z2_DONE_CYCLE(0) <= '1'; --done here
|
||||
elsif(AUTO_CONFIG_Z2_DONE(1) = '0')then
|
||||
AUTO_CONFIG_Z2_DONE_CYCLE(1) <= '1'; --done here
|
||||
elsif(AUTO_CONFIG_Z2_DONE(2) = '0')then
|
||||
AUTO_CONFIG_Z2_DONE_CYCLE(2) <= '1'; --done here
|
||||
end if;
|
||||
end if;
|
||||
when others => D_Z2_OUT <= "1111" ;
|
||||
@@ -661,12 +623,11 @@ begin
|
||||
Z3_ADR(14 downto 2) & Z3_A_LOW;
|
||||
|
||||
--signal assignment
|
||||
D(15 downto 0) <= Z3_DATA(31 downto 16) when RW='1' and Z3_DS <"1111" and FCS='0' and LAN_ACCESS ='1' else
|
||||
D_OUT & x"FF" when RW='1' and Z3_DS <"1111" and FCS='0' and AUTOCONFIG_Z3_ACCESS ='1' else
|
||||
D(15 downto 0) <= Z3_DATA(31 downto 16) when RW='1' and FCS='0' and LAN_ACCESS ='1' else
|
||||
D_Z2_OUT & x"FFF" when RW='1' and AS='0' and AUTOCONFIG_Z2_ACCESS ='1' else
|
||||
(others => 'Z');
|
||||
|
||||
A(23 downto 8) <= Z3_DATA(15 downto 0) when RW='1' and Z3_DS <"1111" and FCS='0' and LAN_ACCESS ='1' else
|
||||
A(23 downto 8) <= Z3_DATA(15 downto 0) when RW='1' and FCS='0' and LAN_ACCESS ='1' else
|
||||
(others => 'Z');
|
||||
|
||||
A(7 downto 1) <= (others => 'Z');
|
||||
@@ -681,13 +642,13 @@ begin
|
||||
'Z';
|
||||
|
||||
OWN <= 'Z';
|
||||
SLAVE <= '0' when FCS='0' and (AUTOCONFIG_Z3_ACCESS = '1' or LAN_ACCESS = '1') else
|
||||
SLAVE <= '0' when FCS='0' and LAN_ACCESS = '1' else
|
||||
'0' when AS='0' and (AUTOCONFIG_Z2_ACCESS = '1' or IDE_ACCESS = '1' or CP_ACCESS = '1') else '1';
|
||||
CFOUT <= '0' when AUTO_CONFIG_DONE='1' and AUTO_CONFIG_Z2_DONE ="11" else '1';
|
||||
CFOUT <= '0' when AUTO_CONFIG_Z2_DONE ="111" else '1';
|
||||
|
||||
OVR <= '0' when FCS='0' and (AUTOCONFIG_Z3_ACCESS = '1' or LAN_ACCESS = '1') else 'Z'; --is Cache inhibit ob Z3!
|
||||
OVR <= '0' when FCS='0' and LAN_ACCESS = '1' else 'Z'; --is Cache inhibit on Z3!
|
||||
|
||||
DTACK <= '0' when FCS='0' and (LAN_READY = '1' or AUTOCONFIG_Z3_ACCESS ='1' or CONFIG_READY='1') else 'Z';
|
||||
DTACK <= '0' when FCS='0' and (LAN_READY = '1' or CONFIG_READY='1') else 'Z';
|
||||
|
||||
MTACK <= 'Z';
|
||||
|
||||
|
||||
+10983
-11730
File diff suppressed because it is too large
Load Diff
File diff suppressed because one or more lines are too long
@@ -5,7 +5,7 @@
|
||||
The structure and the elements are likely to change over the next few releases.
|
||||
This means code written to parse this file will need to be revisited each subsequent release.-->
|
||||
|
||||
<application stringID="NgdBuild" timeStamp="Thu Jan 03 00:09:14 2019">
|
||||
<application stringID="NgdBuild" timeStamp="Tue Feb 19 22:46:31 2019">
|
||||
<section stringID="User_Env">
|
||||
<table stringID="User_EnvVar">
|
||||
<column stringID="variable"/>
|
||||
@@ -70,36 +70,38 @@
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_INFOS" value="0"/>
|
||||
</section>
|
||||
<section stringID="NGDBUILD_PRE_UNISIM_SUMMARY">
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_AND2" value="378"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_AND3" value="53"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_AND4" value="11"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_AND2" value="345"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_AND3" value="41"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_AND4" value="15"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_AND5" value="1"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_FD" value="4"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_FDC" value="22"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_FDC" value="21"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_FDCE" value="7"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_FDP" value="49"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_FDPE" value="69"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_FDP" value="41"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_FDPE" value="68"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_GND" value="1"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_IBUF" value="24"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="468"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="419"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="33"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_OR2" value="278"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_OR3" value="21"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_OR4" value="1"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_XOR2" value="51"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_OR2" value="250"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_OR3" value="17"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_OR4" value="2"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_XOR2" value="50"/>
|
||||
</section>
|
||||
<section stringID="NGDBUILD_POST_UNISIM_SUMMARY">
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_AND2" value="378"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_AND3" value="53"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_AND4" value="11"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_GND" value="76"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_AND2" value="345"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_AND3" value="41"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_AND4" value="15"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_AND5" value="1"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_GND" value="67"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_IBUF" value="74"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="468"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="419"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="33"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_OR2" value="278"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_OR3" value="21"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_OR4" value="1"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_OR2" value="250"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_OR3" value="17"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_OR4" value="2"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_TS_TIMESPEC" value="1"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_XOR2" value="51"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_XOR2" value="50"/>
|
||||
</section>
|
||||
<section stringID="NGDBUILD_CORE_GENERATION_SUMMARY">
|
||||
<section stringID="NGDBUILD_CORE_INSTANCES"/>
|
||||
|
||||
@@ -1,7 +1,7 @@
|
||||
Release 8.1i - Fit P.20131013
|
||||
Copyright(c) 1995-2003 Xilinx Inc. All rights reserved
|
||||
|
||||
1- 3-2019 0:09AM
|
||||
2-19-2019 10:47PM
|
||||
|
||||
NOTE: This file is designed to be imported into a spreadsheet program
|
||||
such as Microsoft Excel for viewing, printing and sorting. The comma ','
|
||||
|
||||
|
@@ -2,7 +2,7 @@
|
||||
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
|
||||
<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
|
||||
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
|
||||
<TD ALIGN=CENTER COLSPAN='4'><B>LAN_IDE_CP Project Status (01/02/2019 - 00:55:58)</B></TD></TR>
|
||||
<TD ALIGN=CENTER COLSPAN='4'><B>LAN_IDE_CP Project Status (02/19/2019 - 22:47:22)</B></TD></TR>
|
||||
<TR ALIGN=LEFT>
|
||||
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
|
||||
<TD>LAN_IDE.xise</TD>
|
||||
@@ -25,7 +25,7 @@ No Errors</TD>
|
||||
<TR ALIGN=LEFT>
|
||||
<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 14.7</TD>
|
||||
<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
|
||||
<TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE\_xmsgs/*.xmsgs?&DataKey=Warning'>46 Warnings (0 new)</A></TD>
|
||||
<TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE\_xmsgs/*.xmsgs?&DataKey=Warning'>48 Warnings (48 new)</A></TD>
|
||||
</TR>
|
||||
<TR ALIGN=LEFT>
|
||||
<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
|
||||
@@ -65,9 +65,9 @@ System Settings</A>
|
||||
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
|
||||
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
|
||||
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE\LAN_IDE_CP.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Do 3. Jan 00:09:07 2019</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE\_xmsgs/xst.xmsgs?&DataKey=Warning'>46 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE\_xmsgs/xst.xmsgs?&DataKey=Info'>10 Infos (0 new)</A></TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE\LAN_IDE_CP.bld'>Translation Report</A></TD><TD>Current</TD><TD>Do 3. Jan 00:09:14 2019</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE\LAN_IDE_CP.rpt'>CPLD Fitter Report (Text)</A></TD><TD>Current</TD><TD>Do 3. Jan 00:09:53 2019</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE\_xmsgs/cpldfit.xmsgs?&DataKey=Warning'>3 Warnings (1 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE\_xmsgs/cpldfit.xmsgs?&DataKey=Info'>1 Info (1 new)</A></TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE\LAN_IDE_CP.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Di 19. Feb 22:46:23 2019</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE\_xmsgs/xst.xmsgs?&DataKey=Warning'>48 Warnings (48 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE\_xmsgs/xst.xmsgs?&DataKey=Info'>11 Infos (11 new)</A></TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE\LAN_IDE_CP.bld'>Translation Report</A></TD><TD>Current</TD><TD>Di 19. Feb 22:46:32 2019</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE\LAN_IDE_CP.rpt'>CPLD Fitter Report (Text)</A></TD><TD>Current</TD><TD>Di 19. Feb 22:47:09 2019</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE\_xmsgs/cpldfit.xmsgs?&DataKey=Warning'>3 Warnings (1 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE\_xmsgs/cpldfit.xmsgs?&DataKey=Info'>1 Info (1 new)</A></TD></TR>
|
||||
<TR ALIGN=LEFT><TD>Power Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
|
||||
</TABLE>
|
||||
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
|
||||
@@ -77,5 +77,5 @@ System Settings</A>
|
||||
</TABLE>
|
||||
|
||||
|
||||
<br><center><b>Date Generated:</b> 01/03/2019 - 00:29:33</center>
|
||||
<br><center><b>Date Generated:</b> 02/19/2019 - 22:47:22</center>
|
||||
</BODY></HTML>
|
||||
@@ -5,7 +5,7 @@
|
||||
The structure and the elements are likely to change over the next few releases.
|
||||
This means code written to parse this file will need to be revisited each subsequent release.-->
|
||||
|
||||
<application stringID="Xst" timeStamp="Thu Jan 03 00:08:48 2019">
|
||||
<application stringID="Xst" timeStamp="Tue Feb 19 22:46:05 2019">
|
||||
<section stringID="User_Env">
|
||||
<table stringID="User_EnvVar">
|
||||
<column stringID="variable"/>
|
||||
@@ -79,14 +79,13 @@
|
||||
<item DEFAULT="YES" label="-equivalent_register_removal" stringID="XST_EQUIVALENTREGISTERREMOVAL" value="YES"/>
|
||||
</section>
|
||||
<section stringID="XST_HDL_SYNTHESIS_REPORT">
|
||||
<item dataType="int" stringID="XST_ROMS" value="1"></item>
|
||||
<item dataType="int" stringID="XST_REGISTERS" value="74">
|
||||
<item dataType="int" stringID="XST_1BIT_REGISTER" value="64"/>
|
||||
<item dataType="int" stringID="XST_REGISTERS" value="85">
|
||||
<item dataType="int" stringID="XST_1BIT_REGISTER" value="77"/>
|
||||
<item dataType="int" stringID="XST_14BIT_REGISTER" value="2"/>
|
||||
<item dataType="int" stringID="XST_16BIT_REGISTER" value="3"/>
|
||||
<item dataType="int" stringID="XST_2BIT_REGISTER" value="1"/>
|
||||
<item dataType="int" stringID="XST_16BIT_REGISTER" value="2"/>
|
||||
<item dataType="int" stringID="XST_3BIT_REGISTER" value="1"/>
|
||||
<item dataType="int" stringID="XST_4BIT_REGISTER" value="1"/>
|
||||
<item dataType="int" stringID="XST_8BIT_REGISTER" value="3"/>
|
||||
<item dataType="int" stringID="XST_8BIT_REGISTER" value="2"/>
|
||||
</item>
|
||||
<item dataType="int" stringID="XST_COMPARATORS" value="6"></item>
|
||||
<item dataType="int" stringID="XST_TRISTATES" value="27">
|
||||
@@ -98,9 +97,8 @@
|
||||
</section>
|
||||
<section stringID="XST_ADVANCED_HDL_SYNTHESIS_REPORT">
|
||||
<item dataType="int" stringID="XST_FSMS" value="2"/>
|
||||
<item dataType="int" stringID="XST_ROMS" value="1"></item>
|
||||
<item dataType="int" stringID="XST_REGISTERS" value="61">
|
||||
<item dataType="int" stringID="XST_FLIPFLOPS" value="61"/>
|
||||
<item dataType="int" stringID="XST_REGISTERS" value="74">
|
||||
<item dataType="int" stringID="XST_FLIPFLOPS" value="74"/>
|
||||
</item>
|
||||
<item dataType="int" stringID="XST_COMPARATORS" value="3"></item>
|
||||
</section>
|
||||
@@ -121,21 +119,21 @@
|
||||
<item stringID="XST_IOS" value="116"/>
|
||||
</section>
|
||||
<section stringID="XST_CELL_USAGE">
|
||||
<item dataType="int" stringID="XST_BELS" value="1268">
|
||||
<item dataType="int" stringID="XST_AND2" value="378"/>
|
||||
<item dataType="int" stringID="XST_AND3" value="53"/>
|
||||
<item dataType="int" stringID="XST_AND4" value="11"/>
|
||||
<item dataType="int" stringID="XST_BELS" value="1145">
|
||||
<item dataType="int" stringID="XST_AND2" value="345"/>
|
||||
<item dataType="int" stringID="XST_AND3" value="41"/>
|
||||
<item dataType="int" stringID="XST_AND4" value="15"/>
|
||||
<item dataType="int" stringID="XST_GND" value="1"/>
|
||||
<item dataType="int" stringID="XST_INV" value="468"/>
|
||||
<item dataType="int" stringID="XST_OR2" value="278"/>
|
||||
<item dataType="int" stringID="XST_XOR2" value="51"/>
|
||||
<item dataType="int" stringID="XST_INV" value="419"/>
|
||||
<item dataType="int" stringID="XST_OR2" value="250"/>
|
||||
<item dataType="int" stringID="XST_XOR2" value="50"/>
|
||||
</item>
|
||||
<item dataType="int" stringID="XST_FLIPFLOPSLATCHES" value="151">
|
||||
<item dataType="int" stringID="XST_FLIPFLOPSLATCHES" value="141">
|
||||
<item dataType="int" stringID="XST_FD" value="4"/>
|
||||
<item dataType="int" stringID="XST_FDC" value="22"/>
|
||||
<item dataType="int" stringID="XST_FDC" value="21"/>
|
||||
<item dataType="int" stringID="XST_FDCE" value="7"/>
|
||||
<item dataType="int" stringID="XST_FDP" value="49"/>
|
||||
<item dataType="int" stringID="XST_FDPE" value="69"/>
|
||||
<item dataType="int" stringID="XST_FDP" value="41"/>
|
||||
<item dataType="int" stringID="XST_FDPE" value="68"/>
|
||||
</item>
|
||||
<item dataType="int" stringID="XST_IO_BUFFERS" value="114">
|
||||
<item dataType="int" stringID="XST_IBUF" value="24"/>
|
||||
@@ -145,8 +143,8 @@
|
||||
</section>
|
||||
<section stringID="XST_ERRORS_STATISTICS">
|
||||
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_ERRORS" value="0"/>
|
||||
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_WARNINGS" value="46"/>
|
||||
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_INFOS" value="10"/>
|
||||
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_WARNINGS" value="48"/>
|
||||
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_INFOS" value="11"/>
|
||||
</section>
|
||||
</application>
|
||||
|
||||
|
||||
@@ -1,2 +1,2 @@
|
||||
C:\Users\Matze\Amiga\Hardwarehacks\Zorro-LAN-IDE\Logic\LAN_IDE\LAN_IDE_CP.ngc 1546470547
|
||||
C:\Users\Matze\Amiga\Hardwarehacks\Zorro-LAN-IDE\Logic\LAN_IDE\LAN_IDE_CP.ngc 1550612783
|
||||
OK
|
||||
|
||||
@@ -5,172 +5,181 @@
|
||||
behavior or data corruption. It is strongly advised that
|
||||
users do not edit the contents of this file. -->
|
||||
<messages>
|
||||
<msg type="info" file="Xst" num="2561" delta="old" >Always blocking tristate driving signal <<arg fmt="%s" index="1">A</arg>> in unit <<arg fmt="%s" index="2">LAN_IDE_CP</arg>> is removed.
|
||||
<msg type="info" file="Xst" num="2679" delta="new" >Register <<arg fmt="%s" index="1">AUTOCONFIG_Z3_ACCESS</arg>> in unit <<arg fmt="%s" index="2">LAN_IDE_CP</arg>> has a constant value of <arg fmt="%s" index="3">0</arg> during circuit operation. The register is replaced by logic.
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="Xst" num="2561" delta="old" >Always blocking tristate driving signal <<arg fmt="%s" index="1">A</arg>> in unit <<arg fmt="%s" index="2">LAN_IDE_CP</arg>> is removed.
|
||||
<msg type="info" file="Xst" num="2561" delta="new" >Always blocking tristate driving signal <<arg fmt="%s" index="1">A</arg>> in unit <<arg fmt="%s" index="2">LAN_IDE_CP</arg>> is removed.
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="Xst" num="2561" delta="old" >Always blocking tristate driving signal <<arg fmt="%s" index="1">A</arg>> in unit <<arg fmt="%s" index="2">LAN_IDE_CP</arg>> is removed.
|
||||
<msg type="info" file="Xst" num="2561" delta="new" >Always blocking tristate driving signal <<arg fmt="%s" index="1">A</arg>> in unit <<arg fmt="%s" index="2">LAN_IDE_CP</arg>> is removed.
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="Xst" num="2561" delta="old" >Always blocking tristate driving signal <<arg fmt="%s" index="1">A</arg>> in unit <<arg fmt="%s" index="2">LAN_IDE_CP</arg>> is removed.
|
||||
<msg type="info" file="Xst" num="2561" delta="new" >Always blocking tristate driving signal <<arg fmt="%s" index="1">A</arg>> in unit <<arg fmt="%s" index="2">LAN_IDE_CP</arg>> is removed.
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="Xst" num="2561" delta="old" >Always blocking tristate driving signal <<arg fmt="%s" index="1">A</arg>> in unit <<arg fmt="%s" index="2">LAN_IDE_CP</arg>> is removed.
|
||||
<msg type="info" file="Xst" num="2561" delta="new" >Always blocking tristate driving signal <<arg fmt="%s" index="1">A</arg>> in unit <<arg fmt="%s" index="2">LAN_IDE_CP</arg>> is removed.
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="Xst" num="2561" delta="old" >Always blocking tristate driving signal <<arg fmt="%s" index="1">A</arg>> in unit <<arg fmt="%s" index="2">LAN_IDE_CP</arg>> is removed.
|
||||
<msg type="info" file="Xst" num="2561" delta="new" >Always blocking tristate driving signal <<arg fmt="%s" index="1">A</arg>> in unit <<arg fmt="%s" index="2">LAN_IDE_CP</arg>> is removed.
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="Xst" num="2561" delta="old" >Always blocking tristate driving signal <<arg fmt="%s" index="1">A</arg>> in unit <<arg fmt="%s" index="2">LAN_IDE_CP</arg>> is removed.
|
||||
<msg type="info" file="Xst" num="2561" delta="new" >Always blocking tristate driving signal <<arg fmt="%s" index="1">A</arg>> in unit <<arg fmt="%s" index="2">LAN_IDE_CP</arg>> is removed.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="647" delta="old" >Input <<arg fmt="%s" index="1">IDE_WAIT</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
<msg type="info" file="Xst" num="2561" delta="new" >Always blocking tristate driving signal <<arg fmt="%s" index="1">A</arg>> in unit <<arg fmt="%s" index="2">LAN_IDE_CP</arg>> is removed.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="647" delta="old" >Input <<arg fmt="%s" index="1">MTCR</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">IDE_WAIT</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="Xst" num="1799" delta="old" >State <arg fmt="%s" index="1">start_read_upper</arg> is never reached in FSM <<arg fmt="%s" index="2">LAN_SM</arg>>.
|
||||
<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">MTCR</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="1293" delta="old" >FF/Latch <<arg fmt="%s" index="1">0</arg>> has a constant value of <arg fmt="%d" index="2">1</arg> in block <<arg fmt="%s" index="3">13</arg>>. This FF/Latch will be trimmed during the optimization process.
|
||||
<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">SHUT_UP_Z2<2></arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="1293" delta="old" >FF/Latch <<arg fmt="%s" index="1">0</arg>> has a constant value of <arg fmt="%d" index="2">1</arg> in block <<arg fmt="%s" index="3">12</arg>>. This FF/Latch will be trimmed during the optimization process.
|
||||
<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">AUTOCONFIG_Z3_ACCESS</arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="1293" delta="old" >FF/Latch <<arg fmt="%s" index="1">0</arg>> has a constant value of <arg fmt="%d" index="2">1</arg> in block <<arg fmt="%s" index="3">11</arg>>. This FF/Latch will be trimmed during the optimization process.
|
||||
<msg type="info" file="Xst" num="1799" delta="new" >State <arg fmt="%s" index="1">start_read_upper</arg> is never reached in FSM <<arg fmt="%s" index="2">LAN_SM</arg>>.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="1293" delta="old" >FF/Latch <<arg fmt="%s" index="1">0</arg>> has a constant value of <arg fmt="%d" index="2">1</arg> in block <<arg fmt="%s" index="3">10</arg>>. This FF/Latch will be trimmed during the optimization process.
|
||||
<msg type="warning" file="Xst" num="1293" delta="new" >FF/Latch <<arg fmt="%s" index="1">0</arg>> has a constant value of <arg fmt="%d" index="2">1</arg> in block <<arg fmt="%s" index="3">13</arg>>. This FF/Latch will be trimmed during the optimization process.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="1293" delta="old" >FF/Latch <<arg fmt="%s" index="1">0</arg>> has a constant value of <arg fmt="%d" index="2">1</arg> in block <<arg fmt="%s" index="3">9</arg>>. This FF/Latch will be trimmed during the optimization process.
|
||||
<msg type="warning" file="Xst" num="1293" delta="new" >FF/Latch <<arg fmt="%s" index="1">0</arg>> has a constant value of <arg fmt="%d" index="2">1</arg> in block <<arg fmt="%s" index="3">12</arg>>. This FF/Latch will be trimmed during the optimization process.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="1293" delta="old" >FF/Latch <<arg fmt="%s" index="1">0</arg>> has a constant value of <arg fmt="%d" index="2">1</arg> in block <<arg fmt="%s" index="3">8</arg>>. This FF/Latch will be trimmed during the optimization process.
|
||||
<msg type="warning" file="Xst" num="1293" delta="new" >FF/Latch <<arg fmt="%s" index="1">0</arg>> has a constant value of <arg fmt="%d" index="2">1</arg> in block <<arg fmt="%s" index="3">11</arg>>. This FF/Latch will be trimmed during the optimization process.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="1293" delta="old" >FF/Latch <<arg fmt="%s" index="1">0</arg>> has a constant value of <arg fmt="%d" index="2">1</arg> in block <<arg fmt="%s" index="3">7</arg>>. This FF/Latch will be trimmed during the optimization process.
|
||||
<msg type="warning" file="Xst" num="1293" delta="new" >FF/Latch <<arg fmt="%s" index="1">0</arg>> has a constant value of <arg fmt="%d" index="2">1</arg> in block <<arg fmt="%s" index="3">10</arg>>. This FF/Latch will be trimmed during the optimization process.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="1293" delta="old" >FF/Latch <<arg fmt="%s" index="1">0</arg>> has a constant value of <arg fmt="%d" index="2">1</arg> in block <<arg fmt="%s" index="3">5</arg>>. This FF/Latch will be trimmed during the optimization process.
|
||||
<msg type="warning" file="Xst" num="1293" delta="new" >FF/Latch <<arg fmt="%s" index="1">0</arg>> has a constant value of <arg fmt="%d" index="2">1</arg> in block <<arg fmt="%s" index="3">9</arg>>. This FF/Latch will be trimmed during the optimization process.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="1293" delta="old" >FF/Latch <<arg fmt="%s" index="1">0</arg>> has a constant value of <arg fmt="%d" index="2">1</arg> in block <<arg fmt="%s" index="3">4</arg>>. This FF/Latch will be trimmed during the optimization process.
|
||||
<msg type="warning" file="Xst" num="1293" delta="new" >FF/Latch <<arg fmt="%s" index="1">0</arg>> has a constant value of <arg fmt="%d" index="2">1</arg> in block <<arg fmt="%s" index="3">8</arg>>. This FF/Latch will be trimmed during the optimization process.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="1293" delta="old" >FF/Latch <<arg fmt="%s" index="1">0</arg>> has a constant value of <arg fmt="%d" index="2">1</arg> in block <<arg fmt="%s" index="3">2</arg>>. This FF/Latch will be trimmed during the optimization process.
|
||||
<msg type="warning" file="Xst" num="1293" delta="new" >FF/Latch <<arg fmt="%s" index="1">0</arg>> has a constant value of <arg fmt="%d" index="2">1</arg> in block <<arg fmt="%s" index="3">7</arg>>. This FF/Latch will be trimmed during the optimization process.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="1293" delta="old" >FF/Latch <<arg fmt="%s" index="1">0</arg>> has a constant value of <arg fmt="%d" index="2">1</arg> in block <<arg fmt="%s" index="3">1</arg>>. This FF/Latch will be trimmed during the optimization process.
|
||||
<msg type="warning" file="Xst" num="1293" delta="new" >FF/Latch <<arg fmt="%s" index="1">0</arg>> has a constant value of <arg fmt="%d" index="2">1</arg> in block <<arg fmt="%s" index="3">5</arg>>. This FF/Latch will be trimmed during the optimization process.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="1293" delta="old" >FF/Latch <<arg fmt="%s" index="1">0</arg>> has a constant value of <arg fmt="%d" index="2">1</arg> in block <<arg fmt="%s" index="3">0</arg>>. This FF/Latch will be trimmed during the optimization process.
|
||||
<msg type="warning" file="Xst" num="1293" delta="new" >FF/Latch <<arg fmt="%s" index="1">0</arg>> has a constant value of <arg fmt="%d" index="2">1</arg> in block <<arg fmt="%s" index="3">4</arg>>. This FF/Latch will be trimmed during the optimization process.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="1293" delta="old" >FF/Latch <<arg fmt="%s" index="1">0</arg>> has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">15</arg>>. This FF/Latch will be trimmed during the optimization process.
|
||||
<msg type="warning" file="Xst" num="1293" delta="new" >FF/Latch <<arg fmt="%s" index="1">0</arg>> has a constant value of <arg fmt="%d" index="2">1</arg> in block <<arg fmt="%s" index="3">2</arg>>. This FF/Latch will be trimmed during the optimization process.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="1293" delta="old" >FF/Latch <<arg fmt="%s" index="1">0</arg>> has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">14</arg>>. This FF/Latch will be trimmed during the optimization process.
|
||||
<msg type="warning" file="Xst" num="1293" delta="new" >FF/Latch <<arg fmt="%s" index="1">0</arg>> has a constant value of <arg fmt="%d" index="2">1</arg> in block <<arg fmt="%s" index="3">1</arg>>. This FF/Latch will be trimmed during the optimization process.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="1293" delta="old" >FF/Latch <<arg fmt="%s" index="1">0</arg>> has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">13</arg>>. This FF/Latch will be trimmed during the optimization process.
|
||||
<msg type="warning" file="Xst" num="1293" delta="new" >FF/Latch <<arg fmt="%s" index="1">0</arg>> has a constant value of <arg fmt="%d" index="2">1</arg> in block <<arg fmt="%s" index="3">0</arg>>. This FF/Latch will be trimmed during the optimization process.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="1293" delta="old" >FF/Latch <<arg fmt="%s" index="1">0</arg>> has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">12</arg>>. This FF/Latch will be trimmed during the optimization process.
|
||||
<msg type="warning" file="Xst" num="1293" delta="new" >FF/Latch <<arg fmt="%s" index="1">0</arg>> has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">15</arg>>. This FF/Latch will be trimmed during the optimization process.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="1293" delta="old" >FF/Latch <<arg fmt="%s" index="1">0</arg>> has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">7</arg>>. This FF/Latch will be trimmed during the optimization process.
|
||||
<msg type="warning" file="Xst" num="1293" delta="new" >FF/Latch <<arg fmt="%s" index="1">0</arg>> has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">14</arg>>. This FF/Latch will be trimmed during the optimization process.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="1293" delta="old" >FF/Latch <<arg fmt="%s" index="1">0</arg>> has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">6</arg>>. This FF/Latch will be trimmed during the optimization process.
|
||||
<msg type="warning" file="Xst" num="1293" delta="new" >FF/Latch <<arg fmt="%s" index="1">0</arg>> has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">13</arg>>. This FF/Latch will be trimmed during the optimization process.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="1293" delta="old" >FF/Latch <<arg fmt="%s" index="1">0</arg>> has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">5</arg>>. This FF/Latch will be trimmed during the optimization process.
|
||||
<msg type="warning" file="Xst" num="1293" delta="new" >FF/Latch <<arg fmt="%s" index="1">0</arg>> has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">12</arg>>. This FF/Latch will be trimmed during the optimization process.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="1293" delta="old" >FF/Latch <<arg fmt="%s" index="1">0</arg>> has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">3</arg>>. This FF/Latch will be trimmed during the optimization process.
|
||||
<msg type="warning" file="Xst" num="1293" delta="new" >FF/Latch <<arg fmt="%s" index="1">0</arg>> has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">7</arg>>. This FF/Latch will be trimmed during the optimization process.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="1293" delta="old" >FF/Latch <<arg fmt="%s" index="1">0</arg>> has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">2</arg>>. This FF/Latch will be trimmed during the optimization process.
|
||||
<msg type="warning" file="Xst" num="1293" delta="new" >FF/Latch <<arg fmt="%s" index="1">0</arg>> has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">6</arg>>. This FF/Latch will be trimmed during the optimization process.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="1293" delta="old" >FF/Latch <<arg fmt="%s" index="1">0</arg>> has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">0</arg>>. This FF/Latch will be trimmed during the optimization process.
|
||||
<msg type="warning" file="Xst" num="1293" delta="new" >FF/Latch <<arg fmt="%s" index="1">0</arg>> has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">5</arg>>. This FF/Latch will be trimmed during the optimization process.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="1293" delta="old" >FF/Latch <<arg fmt="%s" index="1">LAN_D_INIT_15</arg>> has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">LAN_IDE_CP</arg>>. This FF/Latch will be trimmed during the optimization process.
|
||||
<msg type="warning" file="Xst" num="1293" delta="new" >FF/Latch <<arg fmt="%s" index="1">0</arg>> has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">3</arg>>. This FF/Latch will be trimmed during the optimization process.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="1896" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">LAN_D_INIT_14</arg>> has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">LAN_IDE_CP</arg>>. This FF/Latch will be trimmed during the optimization process.
|
||||
<msg type="warning" file="Xst" num="1293" delta="new" >FF/Latch <<arg fmt="%s" index="1">0</arg>> has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">2</arg>>. This FF/Latch will be trimmed during the optimization process.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="1896" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">LAN_D_INIT_13</arg>> has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">LAN_IDE_CP</arg>>. This FF/Latch will be trimmed during the optimization process.
|
||||
<msg type="warning" file="Xst" num="1293" delta="new" >FF/Latch <<arg fmt="%s" index="1">0</arg>> has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">0</arg>>. This FF/Latch will be trimmed during the optimization process.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="1896" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">LAN_D_INIT_12</arg>> has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">LAN_IDE_CP</arg>>. This FF/Latch will be trimmed during the optimization process.
|
||||
<msg type="warning" file="Xst" num="1293" delta="new" >FF/Latch <<arg fmt="%s" index="1">LAN_D_INIT_15</arg>> has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">LAN_IDE_CP</arg>>. This FF/Latch will be trimmed during the optimization process.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="1896" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">LAN_D_INIT_7</arg>> has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">LAN_IDE_CP</arg>>. This FF/Latch will be trimmed during the optimization process.
|
||||
<msg type="warning" file="Xst" num="1896" delta="new" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">LAN_D_INIT_14</arg>> has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">LAN_IDE_CP</arg>>. This FF/Latch will be trimmed during the optimization process.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="1896" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">LAN_D_INIT_6</arg>> has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">LAN_IDE_CP</arg>>. This FF/Latch will be trimmed during the optimization process.
|
||||
<msg type="warning" file="Xst" num="1896" delta="new" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">LAN_D_INIT_13</arg>> has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">LAN_IDE_CP</arg>>. This FF/Latch will be trimmed during the optimization process.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="1896" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">LAN_D_INIT_5</arg>> has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">LAN_IDE_CP</arg>>. This FF/Latch will be trimmed during the optimization process.
|
||||
<msg type="warning" file="Xst" num="1896" delta="new" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">LAN_D_INIT_12</arg>> has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">LAN_IDE_CP</arg>>. This FF/Latch will be trimmed during the optimization process.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="1896" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">LAN_D_INIT_3</arg>> has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">LAN_IDE_CP</arg>>. This FF/Latch will be trimmed during the optimization process.
|
||||
<msg type="warning" file="Xst" num="1896" delta="new" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">LAN_D_INIT_7</arg>> has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">LAN_IDE_CP</arg>>. This FF/Latch will be trimmed during the optimization process.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="1896" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">LAN_D_INIT_2</arg>> has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">LAN_IDE_CP</arg>>. This FF/Latch will be trimmed during the optimization process.
|
||||
<msg type="warning" file="Xst" num="1896" delta="new" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">LAN_D_INIT_6</arg>> has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">LAN_IDE_CP</arg>>. This FF/Latch will be trimmed during the optimization process.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="1896" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">LAN_D_INIT_0</arg>> has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">LAN_IDE_CP</arg>>. This FF/Latch will be trimmed during the optimization process.
|
||||
<msg type="warning" file="Xst" num="1896" delta="new" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">LAN_D_INIT_5</arg>> has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">LAN_IDE_CP</arg>>. This FF/Latch will be trimmed during the optimization process.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="1896" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">LAN_A_INIT_13</arg>> has a constant value of <arg fmt="%d" index="2">1</arg> in block <<arg fmt="%s" index="3">LAN_IDE_CP</arg>>. This FF/Latch will be trimmed during the optimization process.
|
||||
<msg type="warning" file="Xst" num="1896" delta="new" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">LAN_D_INIT_3</arg>> has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">LAN_IDE_CP</arg>>. This FF/Latch will be trimmed during the optimization process.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="1896" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">LAN_A_INIT_12</arg>> has a constant value of <arg fmt="%d" index="2">1</arg> in block <<arg fmt="%s" index="3">LAN_IDE_CP</arg>>. This FF/Latch will be trimmed during the optimization process.
|
||||
<msg type="warning" file="Xst" num="1896" delta="new" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">LAN_D_INIT_2</arg>> has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">LAN_IDE_CP</arg>>. This FF/Latch will be trimmed during the optimization process.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="1896" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">LAN_A_INIT_11</arg>> has a constant value of <arg fmt="%d" index="2">1</arg> in block <<arg fmt="%s" index="3">LAN_IDE_CP</arg>>. This FF/Latch will be trimmed during the optimization process.
|
||||
<msg type="warning" file="Xst" num="1896" delta="new" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">LAN_D_INIT_0</arg>> has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">LAN_IDE_CP</arg>>. This FF/Latch will be trimmed during the optimization process.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="1896" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">LAN_A_INIT_10</arg>> has a constant value of <arg fmt="%d" index="2">1</arg> in block <<arg fmt="%s" index="3">LAN_IDE_CP</arg>>. This FF/Latch will be trimmed during the optimization process.
|
||||
<msg type="warning" file="Xst" num="1896" delta="new" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">LAN_A_INIT_13</arg>> has a constant value of <arg fmt="%d" index="2">1</arg> in block <<arg fmt="%s" index="3">LAN_IDE_CP</arg>>. This FF/Latch will be trimmed during the optimization process.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="1896" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">LAN_A_INIT_9</arg>> has a constant value of <arg fmt="%d" index="2">1</arg> in block <<arg fmt="%s" index="3">LAN_IDE_CP</arg>>. This FF/Latch will be trimmed during the optimization process.
|
||||
<msg type="warning" file="Xst" num="1896" delta="new" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">LAN_A_INIT_12</arg>> has a constant value of <arg fmt="%d" index="2">1</arg> in block <<arg fmt="%s" index="3">LAN_IDE_CP</arg>>. This FF/Latch will be trimmed during the optimization process.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="1896" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">LAN_A_INIT_8</arg>> has a constant value of <arg fmt="%d" index="2">1</arg> in block <<arg fmt="%s" index="3">LAN_IDE_CP</arg>>. This FF/Latch will be trimmed during the optimization process.
|
||||
<msg type="warning" file="Xst" num="1896" delta="new" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">LAN_A_INIT_11</arg>> has a constant value of <arg fmt="%d" index="2">1</arg> in block <<arg fmt="%s" index="3">LAN_IDE_CP</arg>>. This FF/Latch will be trimmed during the optimization process.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="1896" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">LAN_A_INIT_7</arg>> has a constant value of <arg fmt="%d" index="2">1</arg> in block <<arg fmt="%s" index="3">LAN_IDE_CP</arg>>. This FF/Latch will be trimmed during the optimization process.
|
||||
<msg type="warning" file="Xst" num="1896" delta="new" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">LAN_A_INIT_10</arg>> has a constant value of <arg fmt="%d" index="2">1</arg> in block <<arg fmt="%s" index="3">LAN_IDE_CP</arg>>. This FF/Latch will be trimmed during the optimization process.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="1896" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">LAN_A_INIT_5</arg>> has a constant value of <arg fmt="%d" index="2">1</arg> in block <<arg fmt="%s" index="3">LAN_IDE_CP</arg>>. This FF/Latch will be trimmed during the optimization process.
|
||||
<msg type="warning" file="Xst" num="1896" delta="new" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">LAN_A_INIT_9</arg>> has a constant value of <arg fmt="%d" index="2">1</arg> in block <<arg fmt="%s" index="3">LAN_IDE_CP</arg>>. This FF/Latch will be trimmed during the optimization process.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="1896" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">LAN_A_INIT_4</arg>> has a constant value of <arg fmt="%d" index="2">1</arg> in block <<arg fmt="%s" index="3">LAN_IDE_CP</arg>>. This FF/Latch will be trimmed during the optimization process.
|
||||
<msg type="warning" file="Xst" num="1896" delta="new" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">LAN_A_INIT_8</arg>> has a constant value of <arg fmt="%d" index="2">1</arg> in block <<arg fmt="%s" index="3">LAN_IDE_CP</arg>>. This FF/Latch will be trimmed during the optimization process.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="1896" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">LAN_A_INIT_2</arg>> has a constant value of <arg fmt="%d" index="2">1</arg> in block <<arg fmt="%s" index="3">LAN_IDE_CP</arg>>. This FF/Latch will be trimmed during the optimization process.
|
||||
<msg type="warning" file="Xst" num="1896" delta="new" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">LAN_A_INIT_7</arg>> has a constant value of <arg fmt="%d" index="2">1</arg> in block <<arg fmt="%s" index="3">LAN_IDE_CP</arg>>. This FF/Latch will be trimmed during the optimization process.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="1896" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">LAN_A_INIT_1</arg>> has a constant value of <arg fmt="%d" index="2">1</arg> in block <<arg fmt="%s" index="3">LAN_IDE_CP</arg>>. This FF/Latch will be trimmed during the optimization process.
|
||||
<msg type="warning" file="Xst" num="1896" delta="new" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">LAN_A_INIT_5</arg>> has a constant value of <arg fmt="%d" index="2">1</arg> in block <<arg fmt="%s" index="3">LAN_IDE_CP</arg>>. This FF/Latch will be trimmed during the optimization process.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="1896" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">LAN_A_INIT_0</arg>> has a constant value of <arg fmt="%d" index="2">1</arg> in block <<arg fmt="%s" index="3">LAN_IDE_CP</arg>>. This FF/Latch will be trimmed during the optimization process.
|
||||
<msg type="warning" file="Xst" num="1896" delta="new" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">LAN_A_INIT_4</arg>> has a constant value of <arg fmt="%d" index="2">1</arg> in block <<arg fmt="%s" index="3">LAN_IDE_CP</arg>>. This FF/Latch will be trimmed during the optimization process.
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">LAN_D_INIT_8</arg>> in Unit <<arg fmt="%s" index="2">LAN_IDE_CP</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><LAN_D_INIT_10> <LAN_D_INIT_11> </arg>
|
||||
<msg type="warning" file="Xst" num="1896" delta="new" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">LAN_A_INIT_2</arg>> has a constant value of <arg fmt="%d" index="2">1</arg> in block <<arg fmt="%s" index="3">LAN_IDE_CP</arg>>. This FF/Latch will be trimmed during the optimization process.
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">LAN_D_INIT_1</arg>> in Unit <<arg fmt="%s" index="2">LAN_IDE_CP</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><LAN_D_INIT_4> <LAN_D_INIT_9> </arg>
|
||||
<msg type="warning" file="Xst" num="1896" delta="new" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">LAN_A_INIT_1</arg>> has a constant value of <arg fmt="%d" index="2">1</arg> in block <<arg fmt="%s" index="3">LAN_IDE_CP</arg>>. This FF/Latch will be trimmed during the optimization process.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="1896" delta="new" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">LAN_A_INIT_0</arg>> has a constant value of <arg fmt="%d" index="2">1</arg> in block <<arg fmt="%s" index="3">LAN_IDE_CP</arg>>. This FF/Latch will be trimmed during the optimization process.
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">LAN_D_INIT_8</arg>> in Unit <<arg fmt="%s" index="2">LAN_IDE_CP</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><LAN_D_INIT_10> <LAN_D_INIT_11> </arg>
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">LAN_D_INIT_1</arg>> in Unit <<arg fmt="%s" index="2">LAN_IDE_CP</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><LAN_D_INIT_4> <LAN_D_INIT_9> </arg>
|
||||
</msg>
|
||||
|
||||
</messages>
|
||||
|
||||
@@ -9,13 +9,13 @@
|
||||
<ClosedNodesVersion>2</ClosedNodesVersion>
|
||||
</ClosedNodes>
|
||||
<SelectedItems>
|
||||
<SelectedItem>LAN_IDE_CP - Behavioral (C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.vhd)</SelectedItem>
|
||||
<SelectedItem>pinlist.ucf (C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/pinlist.ucf)</SelectedItem>
|
||||
</SelectedItems>
|
||||
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
|
||||
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
|
||||
<ViewHeaderState orientation="horizontal" >000000ff0000000000000001000000010000000000000000000000000000000002020000000100000001000000640000013c000000020000000000000000000000000200000064ffffffff0000008100000003000000020000013c0000000100000003000000000000000100000003</ViewHeaderState>
|
||||
<UserChangedColumnWidths orientation="horizontal" >true</UserChangedColumnWidths>
|
||||
<CurrentItem>LAN_IDE_CP - Behavioral (C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.vhd)</CurrentItem>
|
||||
<CurrentItem>pinlist.ucf (C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/pinlist.ucf)</CurrentItem>
|
||||
</ItemView>
|
||||
<ItemView engineview="SynthesisOnly" sourcetype="" guiview="Process" >
|
||||
<ClosedNodes>
|
||||
@@ -79,13 +79,13 @@
|
||||
<ClosedNodesVersion>1</ClosedNodesVersion>
|
||||
</ClosedNodes>
|
||||
<SelectedItems>
|
||||
<SelectedItem/>
|
||||
<SelectedItem></SelectedItem>
|
||||
</SelectedItems>
|
||||
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
|
||||
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
|
||||
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000000f8000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f80000000100000000</ViewHeaderState>
|
||||
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
|
||||
<CurrentItem/>
|
||||
<CurrentItem></CurrentItem>
|
||||
</ItemView>
|
||||
<ItemView engineview="BehavioralSim" guiview="Source" compilemode="AutoCompile" >
|
||||
<ClosedNodes>
|
||||
|
||||
@@ -1,7 +1,7 @@
|
||||
<?xml version='1.0' encoding='UTF-8'?>
|
||||
<report-views version="2.0" >
|
||||
<header>
|
||||
<DateModified>2019-01-03T00:29:34</DateModified>
|
||||
<DateModified>2019-02-17T21:10:38</DateModified>
|
||||
<ModuleName>LAN_IDE_CP</ModuleName>
|
||||
<SummaryTimeStamp>2019-01-02T00:55:58</SummaryTimeStamp>
|
||||
<SavedFilePath>C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/iseconfig/LAN_IDE_CP.xreport</SavedFilePath>
|
||||
|
||||
+905
-723
File diff suppressed because it is too large
Load Diff
@@ -3,7 +3,7 @@
|
||||
<!--The data in this file is primarily intended for consumption by Xilinx tools.
|
||||
The structure and the elements are likely to change over the next few releases.
|
||||
This means code written to parse this file will need to be revisited each subsequent release.-->
|
||||
<application name="pn" timeStamp="Thu Jan 03 00:08:47 2019">
|
||||
<application name="pn" timeStamp="Tue Feb 19 22:46:04 2019">
|
||||
<section name="Project Information" visible="false">
|
||||
<property name="ProjectID" value="A2E624B6ED1449CD92F77DE849BF7B51" type="project"/>
|
||||
<property name="ProjectIteration" value="0" type="project"/>
|
||||
|
||||
Binary file not shown.
@@ -0,0 +1,496 @@
|
||||
----------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 22:08:29 12/13/2016
|
||||
-- Design Name:
|
||||
-- Module Name: LAN_IDE_CP - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
-- directory cleanup hint:
|
||||
-- svn status|grep ^M|sed "s/^M [\t ]*//"|xargs rm
|
||||
----------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
--use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if instantiating
|
||||
-- any Xilinx primitives in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity LAN_IDE_CP is
|
||||
Port ( A : inout STD_LOGIC_VECTOR (23 downto 1);
|
||||
D : inout STD_LOGIC_VECTOR (15 downto 0);
|
||||
DQ : inout STD_LOGIC_VECTOR (15 downto 0);
|
||||
A_LAN : out STD_LOGIC_VECTOR (13 downto 0);
|
||||
OWN : out STD_LOGIC;
|
||||
SLAVE : out STD_LOGIC;
|
||||
CFOUT : out STD_LOGIC;
|
||||
CFIN : in STD_LOGIC;
|
||||
C1 : in STD_LOGIC;
|
||||
C3 : in STD_LOGIC;
|
||||
MTCR : in STD_LOGIC;
|
||||
OVR : out STD_LOGIC;
|
||||
BERR : in STD_LOGIC;
|
||||
MTACK : out STD_LOGIC;
|
||||
DS0 : in STD_LOGIC;
|
||||
DTACK : out STD_LOGIC;
|
||||
UDS : in STD_LOGIC;
|
||||
LDS : in STD_LOGIC;
|
||||
AS : in STD_LOGIC;
|
||||
RW : in STD_LOGIC;
|
||||
Z3 : in STD_LOGIC;
|
||||
DS1 : in STD_LOGIC;
|
||||
FCS : in STD_LOGIC;
|
||||
RESET : in STD_LOGIC;
|
||||
INT_OUT : out STD_LOGIC;
|
||||
AUTOBOOT_OFF : in STD_LOGIC;
|
||||
ROM_B : out STD_LOGIC_VECTOR (1 downto 0);
|
||||
ROM_OE : out STD_LOGIC;
|
||||
IDE_WAIT : in STD_LOGIC;
|
||||
CLK_EXT : in STD_LOGIC;
|
||||
IDE_W : out STD_LOGIC;
|
||||
IDE_R : out STD_LOGIC;
|
||||
IDE_A : out STD_LOGIC_VECTOR (2 downto 0);
|
||||
IDE_CS : out STD_LOGIC_VECTOR (1 downto 0);
|
||||
LAN_CFG : out STD_LOGIC_VECTOR (4 downto 1);
|
||||
LAN_RD : out STD_LOGIC;
|
||||
LAN_CS : out STD_LOGIC;
|
||||
LAN_WRH : out STD_LOGIC;
|
||||
LAN_WRL : out STD_LOGIC;
|
||||
LAN_INT : in STD_LOGIC;
|
||||
CP_RD : out STD_LOGIC;
|
||||
CP_WE : out STD_LOGIC;
|
||||
CP_CS : out STD_LOGIC;
|
||||
CP_IRQ : in STD_LOGIC);
|
||||
end LAN_IDE_CP;
|
||||
|
||||
architecture Behavioral of LAN_IDE_CP is
|
||||
|
||||
TYPE lan_reset IS (
|
||||
nop,
|
||||
wait0,
|
||||
clr,
|
||||
clr_commit,
|
||||
wait1,
|
||||
set,
|
||||
set_commit,
|
||||
done
|
||||
);
|
||||
|
||||
SIGNAL LAN_RST_SM: lan_reset :=nop;
|
||||
SIGNAL lancp: STD_LOGIC; -- LAN or ClockPort
|
||||
SIGNAL ide: STD_LOGIC;
|
||||
SIGNAL autoconfig: STD_LOGIC;
|
||||
SIGNAL lan_adr: STD_LOGIC;
|
||||
SIGNAL lan_adr_sw: STD_LOGIC;
|
||||
SIGNAL cp: STD_LOGIC;
|
||||
signal Dout1:STD_LOGIC_VECTOR(3 downto 0);
|
||||
signal AUTO_CONFIG_DONE:STD_LOGIC_VECTOR(1 downto 0);
|
||||
signal AUTO_CONFIG_DONE_CYCLE:STD_LOGIC_VECTOR(1 downto 0);
|
||||
signal SHUT_UP:STD_LOGIC_VECTOR(2 downto 0);
|
||||
signal IDE_BASEADR:STD_LOGIC_VECTOR(7 downto 0);
|
||||
signal LAN_BASEADR:STD_LOGIC_VECTOR(7 downto 0);
|
||||
signal CP_BASEADR:STD_LOGIC_VECTOR(7 downto 0);
|
||||
signal IDE_ENABLE:STD_LOGIC;
|
||||
signal ROM_OE_S:STD_LOGIC;
|
||||
signal IDE_R_S:STD_LOGIC;
|
||||
signal IDE_W_S:STD_LOGIC;
|
||||
signal DTACK_S:STD_LOGIC;
|
||||
signal AMIGA_CLK: std_logic;
|
||||
signal LAN_INT_ENABLE: std_logic;
|
||||
signal DECODE_RESET: std_logic;
|
||||
signal LAN_INT_D0: std_logic;
|
||||
signal DS: std_logic;
|
||||
signal DS_D: std_logic;
|
||||
signal LAN_RD_S: std_logic;
|
||||
signal LAN_WRH_S: std_logic;
|
||||
signal LAN_WRL_S: std_logic;
|
||||
signal LAN_IRQ_D0: std_logic;
|
||||
signal LAN_IRQ_OUT: std_logic;
|
||||
signal CP_RD_S: std_logic;
|
||||
signal CP_WE_S: std_logic;
|
||||
signal CP_WE_QUIRK: std_logic;
|
||||
|
||||
signal LAN_CS_RST: std_logic;
|
||||
signal LAN_WR_RST: std_logic;
|
||||
constant LAN_A_CLRREG:STD_LOGIC_VECTOR(13 downto 0) :="11"&x"FF7";
|
||||
constant LAN_A_SETREG:STD_LOGIC_VECTOR(13 downto 0) :="11"&x"FB7";
|
||||
constant LAN_D_SET:STD_LOGIC_VECTOR(15 downto 0) := "0000000100010000";
|
||||
constant LAN_D_CLR:STD_LOGIC_VECTOR(15 downto 0) := "0000111000000000";
|
||||
|
||||
Function to_std_logic(X: in Boolean) return Std_Logic is
|
||||
variable ret : std_logic;
|
||||
begin
|
||||
if x then ret := '1'; else ret := '0'; end if;
|
||||
return ret;
|
||||
end to_std_logic;
|
||||
|
||||
begin
|
||||
|
||||
AMIGA_CLK <= not (C1 xor C3);
|
||||
DECODE_RESET <= BERR and reset;
|
||||
|
||||
DS <= UDS and LDS;
|
||||
|
||||
clock_init: process(CLK_EXT)
|
||||
begin
|
||||
if(rising_edge(CLK_EXT))then
|
||||
if(reset = '0')then
|
||||
--init the clock!
|
||||
case LAN_RST_SM is
|
||||
when nop=>
|
||||
LAN_CS_RST<='0';
|
||||
LAN_WR_RST<='0';
|
||||
LAN_RST_SM<=wait0;
|
||||
when wait0=>
|
||||
LAN_CS_RST<='1';
|
||||
LAN_WR_RST<='0';
|
||||
LAN_RST_SM<=clr;
|
||||
when clr=>
|
||||
LAN_CS_RST<='1';
|
||||
LAN_WR_RST<='1';
|
||||
LAN_RST_SM<=clr_commit;
|
||||
when clr_commit=>
|
||||
LAN_CS_RST<='1';
|
||||
LAN_WR_RST<='0';
|
||||
LAN_RST_SM<=wait1;
|
||||
when wait1=>
|
||||
LAN_CS_RST<='1';
|
||||
LAN_WR_RST<='0';
|
||||
LAN_RST_SM<=set;
|
||||
when set=>
|
||||
LAN_CS_RST<='1';
|
||||
LAN_WR_RST<='1';
|
||||
LAN_RST_SM<=set_commit;
|
||||
when set_commit=>
|
||||
LAN_CS_RST<='1';
|
||||
LAN_WR_RST<='0';
|
||||
LAN_RST_SM<=done;
|
||||
when done=>
|
||||
LAN_CS_RST<='0';
|
||||
LAN_WR_RST<='0';
|
||||
LAN_RST_SM<=done;
|
||||
end case;
|
||||
else
|
||||
LAN_CS_RST<='0';
|
||||
LAN_WR_RST<='0';
|
||||
LAN_RST_SM<=nop;
|
||||
end if;
|
||||
end if;
|
||||
end process clock_init;
|
||||
|
||||
ADDRESS_DECODE: process(DECODE_RESET,AS)
|
||||
begin
|
||||
if(DECODE_RESET ='0')then
|
||||
autoconfig <= '0';
|
||||
ide <= '0';
|
||||
lan_adr <= '0';
|
||||
lan_adr_sw <= '0';
|
||||
cp <= '0';
|
||||
lancp <= '0';
|
||||
elsif(falling_edge(AS))then
|
||||
--default values
|
||||
autoconfig <= '0';
|
||||
ide <= '0';
|
||||
lan_adr <= '0';
|
||||
lan_adr_sw <= '0';
|
||||
cp <= '0';
|
||||
lancp <= '0';
|
||||
if(A(23 downto 16) = x"E8" and AUTO_CONFIG_DONE < "11" and CFIN='0')then
|
||||
autoconfig <= '1';
|
||||
elsif(A(23 downto 16) = LAN_BASEADR and SHUT_UP(0)='0' )then
|
||||
if(A(14 downto 13)<"11")then
|
||||
lan_adr_sw <= '1';
|
||||
end if;
|
||||
lan_adr <= '1';
|
||||
lancp <= '1';
|
||||
elsif(A(23 downto 16) = CP_BASEADR and SHUT_UP(1)='0')then
|
||||
cp <= '1';
|
||||
lancp <= '1';
|
||||
elsif(A(23 downto 16) = IDE_BASEADR and SHUT_UP(2)='0')then
|
||||
ide <= '1';
|
||||
lancp <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end process ADDRESS_DECODE;
|
||||
|
||||
--LAN interrupt enable
|
||||
lan_int_proc: process (AMIGA_CLK,reset)
|
||||
begin
|
||||
if(reset ='0') then
|
||||
LAN_INT_ENABLE <='0';
|
||||
LAN_IRQ_D0 <='1';
|
||||
LAN_IRQ_OUT <='1';
|
||||
elsif falling_edge(AMIGA_CLK) then
|
||||
LAN_IRQ_D0 <= LAN_INT;
|
||||
if(LAN_INT ='0' and LAN_IRQ_D0 ='1') then
|
||||
LAN_IRQ_OUT <='0';
|
||||
elsif(LAN_INT ='1' or LAN_INT_ENABLE = '0')then
|
||||
LAN_IRQ_OUT <='1';
|
||||
elsif(lan_adr = '1' and DS ='0' and RW='0' and A(15)='1') then
|
||||
LAN_IRQ_OUT <= D(14); --controll lan irq
|
||||
end if;
|
||||
|
||||
if(lan_adr = '1' and DS ='0' and RW='0' and A(15)='1') then --enable if a write to A15 occured
|
||||
LAN_INT_ENABLE <= D(15);
|
||||
end if;
|
||||
end if;
|
||||
end process lan_int_proc;
|
||||
|
||||
--lan signal generation: all Signals are HIGH active!
|
||||
lan_rw_gen: process (AMIGA_CLK)
|
||||
begin
|
||||
if falling_edge(AMIGA_CLK) then
|
||||
--default values
|
||||
LAN_RD_S <= '0';
|
||||
LAN_WRH_S <= '0';
|
||||
LAN_WRL_S <= '0';
|
||||
|
||||
if(lan_adr='1' and DS='0' and A(15)='0')then
|
||||
LAN_RD_S <= RW;
|
||||
-- swapped LDS/UDS here: ENC624 is little endian
|
||||
LAN_WRH_S <= not LDS and not RW;
|
||||
LAN_WRL_S <= not UDS and not RW;
|
||||
end if;
|
||||
end if;
|
||||
end process lan_rw_gen;
|
||||
|
||||
--cp signal generation
|
||||
cp_rw_gen: process (AMIGA_CLK)
|
||||
begin
|
||||
if falling_edge(AMIGA_CLK) then
|
||||
--default values
|
||||
CP_RD_S <= '1';
|
||||
CP_WE_S <= '1';
|
||||
if(cp = '1' and DS='0')then --datastrobe instead of AS!
|
||||
CP_RD_S <= not RW;
|
||||
CP_WE_S <= RW;
|
||||
end if;
|
||||
CP_WE_QUIRK <= CP_WE_S;
|
||||
end if;
|
||||
end process cp_rw_gen;
|
||||
|
||||
--ide signal generation
|
||||
ide_rw_gen: process (reset,AMIGA_CLK)
|
||||
begin
|
||||
if (reset = '0') then
|
||||
IDE_ENABLE <= '1';
|
||||
IDE_R_S <= '1';
|
||||
IDE_W_S <= '1';
|
||||
ROM_OE_S <= '1';
|
||||
elsif falling_edge(AMIGA_CLK) then
|
||||
--default values
|
||||
IDE_R_S <= '1';
|
||||
IDE_W_S <= '1';
|
||||
ROM_OE_S <= '1';
|
||||
if(ide='1' and AS='0')then
|
||||
if(RW='0')then
|
||||
--the write goes to the hdd!
|
||||
IDE_ENABLE <= '0'; -- enable IDE on first read
|
||||
IDE_W_S <= '0';
|
||||
else
|
||||
IDE_R_S <= IDE_ENABLE; --read from IDE instead from ROM
|
||||
ROM_OE_S <= not IDE_ENABLE;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process ide_rw_gen;
|
||||
|
||||
|
||||
--autoconfig
|
||||
autoconfig_proc: process (reset, AMIGA_CLK)
|
||||
begin
|
||||
if reset = '0' then
|
||||
-- reset active ...
|
||||
AUTO_CONFIG_DONE_CYCLE <="00";
|
||||
Dout1<="1111";
|
||||
--Dout2<="1111";
|
||||
SHUT_UP <="111";
|
||||
IDE_BASEADR<=x"FF";
|
||||
LAN_BASEADR<=x"FF";
|
||||
CP_BASEADR<=x"FF";
|
||||
AUTO_CONFIG_DONE <="00";
|
||||
elsif falling_edge(AMIGA_CLK) then -- no reset, so wait for rising edge of the clock
|
||||
DS_D <= DS;
|
||||
if(AS='1')then
|
||||
AUTO_CONFIG_DONE <= AUTO_CONFIG_DONE_CYCLE;
|
||||
elsif(autoconfig= '1' and DS='0') then
|
||||
case A(6 downto 1) is
|
||||
when "000000" =>
|
||||
if(AUTO_CONFIG_DONE < 2)then
|
||||
Dout1 <= "1100" ; --ZII, No-System-Memory, no ROM
|
||||
else
|
||||
Dout1 <= "1101" ; --ZII, no System-Memory, (perhaps)ROM
|
||||
end if;
|
||||
when "000001" => Dout1 <= "0001" ; --one Card, 64KB =001
|
||||
when "000010" =>
|
||||
if(AUTO_CONFIG_DONE < 2)then
|
||||
Dout1 <= "1000" ; --ProductID high nibble : 7->1000
|
||||
else
|
||||
Dout1 <= "1111" ; --ProductID high nibble : 0->1111
|
||||
end if;
|
||||
when "000011" =>
|
||||
if(AUTO_CONFIG_DONE = 0)then
|
||||
Dout1 <= "0100" ; --ProductID low nibble: B->0100
|
||||
elsif(AUTO_CONFIG_DONE = 1)then
|
||||
Dout1 <= "0011" ; --ProductID low nibble: C->0011
|
||||
else
|
||||
Dout1 <= "1001" ; --ProductID low nibble: 6->1001
|
||||
end if;
|
||||
when "001000" => Dout1 <= "1111" ; --Ventor ID 0
|
||||
when "001001" =>
|
||||
if(AUTO_CONFIG_DONE < 2)then
|
||||
Dout1 <= "0101" ; --Ventor ID 1
|
||||
else
|
||||
Dout1 <= "0111" ; --Ventor ID 1
|
||||
end if;
|
||||
when "001010" =>
|
||||
if(AUTO_CONFIG_DONE < 2)then
|
||||
Dout1 <= "1110" ; --Ventor ID 2
|
||||
else
|
||||
Dout1 <= "1101" ; --Ventor ID 2
|
||||
end if;
|
||||
when "001011" =>
|
||||
if(AUTO_CONFIG_DONE < 2)then
|
||||
Dout1 <= "0011" ; --Ventor ID 3 : $0A1C: A1K.org
|
||||
else
|
||||
Dout1 <= "0011" ; --Ventor ID 3 : $082C: BSC
|
||||
end if;
|
||||
when "001100" => Dout1 <= "0100" ; --Serial byte 0 (msb) high nibble
|
||||
when "001101" => Dout1 <= "1110" ; --Serial byte 0 (msb) low nibble
|
||||
when "001110" => Dout1 <= "1001" ; --Serial byte 1 high nibble
|
||||
when "001111" => Dout1 <= "0100" ; --Serial byte 1 low nibble
|
||||
when "010000" => Dout1 <= "1111" ; --Serial byte 2 high nibble
|
||||
when "010001" => Dout1 <= "1111" ; --Serial byte 2 low nibble
|
||||
when "010010" => Dout1 <= "0100" ; --Serial byte 3 (lsb) high nibble
|
||||
when "010011" => Dout1 <= "1010" ; --Serial byte 3 (lsb) low nibble: B16B00B5
|
||||
--when "010100" => Dout1 <= "1111" ; --Rom vector high byte high nibble
|
||||
--when "010101" => Dout1 <= "1111" ; --Rom vector high byte low nibble
|
||||
--when "010110" => Dout1 <= "1111" ; --Rom vector low byte high nibble
|
||||
when "010111" =>
|
||||
if(AUTO_CONFIG_DONE = 2)then
|
||||
Dout1 <= "1110" ; --Rom vector low byte low nibble
|
||||
else
|
||||
Dout1 <= "1111" ; --Rom vector low byte low nibble
|
||||
end if;
|
||||
when "100000" => Dout1 <= "0000" ; --Interrupt config: all zero
|
||||
when "100001" => Dout1 <= "0000" ; --Interrupt config: all zero
|
||||
when "100100" =>
|
||||
Dout1 <= "1111" ;
|
||||
if(RW='0' and DS_D='1')then
|
||||
if(AUTO_CONFIG_DONE = 0)then
|
||||
LAN_BASEADR(7 downto 0) <= D(15 downto 8); --Base adress
|
||||
SHUT_UP(0) <='0'; --enable board
|
||||
AUTO_CONFIG_DONE_CYCLE <= "01"; --done here
|
||||
elsif(AUTO_CONFIG_DONE = 1)then
|
||||
CP_BASEADR(7 downto 0) <= D(15 downto 8); --Base adress
|
||||
SHUT_UP(1) <= '0'; --enable board
|
||||
AUTO_CONFIG_DONE_CYCLE <= '1' & AUTOBOOT_OFF; --done here, if Autoboot = 1 skip ide part!
|
||||
elsif(AUTO_CONFIG_DONE = 2)then
|
||||
IDE_BASEADR(7 downto 0) <= D(15 downto 8); --Base adress
|
||||
SHUT_UP(2) <= '0'; --enable board
|
||||
AUTO_CONFIG_DONE_CYCLE <= "11"; --done here
|
||||
end if;
|
||||
end if;
|
||||
when "100110" =>
|
||||
Dout1 <= "1111" ;
|
||||
if(RW='0' and DS_D='1')then
|
||||
AUTO_CONFIG_DONE_CYCLE <= AUTO_CONFIG_DONE_CYCLE+1; --done here
|
||||
end if;
|
||||
when others => Dout1 <= "1111" ;
|
||||
end case;
|
||||
end if;
|
||||
end if;
|
||||
end process autoconfig_proc; --- that's all
|
||||
|
||||
LAN_CS <= lan_adr when reset='1' else LAN_CS_RST;
|
||||
LAN_WRL <= LAN_WRL_S when AS='0' and reset = '1' else LAN_WR_RST;
|
||||
LAN_WRH <= LAN_WRH_S when AS='0' and reset = '1' else LAN_WR_RST;
|
||||
LAN_RD <= LAN_RD_S when AS='0' and reset = '1' else '0';
|
||||
LAN_CFG <= "0010"; -- "ZZZZ";
|
||||
|
||||
CP_WE <= CP_WE_S when AS='0' and CP_WE_QUIRK ='1' else '1';
|
||||
CP_RD <= CP_RD_S when AS='0' else '1';
|
||||
CP_CS <= not cp;
|
||||
|
||||
--the lanport is shifted by one adress line but I forgot to adopt the clockport address!
|
||||
A_LAN(13 downto 6)<= LAN_A_CLRREG(13 downto 6) when (LAN_RST_SM = wait0 or LAN_RST_SM = clr or LAN_RST_SM = clr_commit) else
|
||||
LAN_A_SETREG(13 downto 6) when (LAN_RST_SM = wait1 or LAN_RST_SM = set or LAN_RST_SM = set_commit) else
|
||||
--(A(14)&A(12)&A(13)&A(11 downto 7)); --swap A12/13 for the enj-Chip
|
||||
A(14 downto 7);
|
||||
A_LAN(5 downto 2) <= LAN_A_CLRREG(5 downto 2) when (LAN_RST_SM = wait0 or LAN_RST_SM = clr or LAN_RST_SM = clr_commit) else
|
||||
LAN_A_SETREG(5 downto 2) when (LAN_RST_SM = wait1 or LAN_RST_SM = set or LAN_RST_SM = set_commit) else
|
||||
A(5 downto 2) when cp='1' else A(6 downto 3); --mux the clock-port adresses!
|
||||
A_LAN(1 downto 0)<= LAN_A_CLRREG(1 downto 0) when (LAN_RST_SM = wait0 or LAN_RST_SM = clr or LAN_RST_SM = clr_commit) else
|
||||
LAN_A_SETREG(1 downto 0) when (LAN_RST_SM = wait1 or LAN_RST_SM = set or LAN_RST_SM = set_commit) else
|
||||
A(2 downto 1);
|
||||
|
||||
|
||||
|
||||
--signal assignment
|
||||
D <= --RAM_D when RW='1' and TRANSFER_IN_PROGRES ='1' else
|
||||
DQ when RW='1' and lan_adr ='1' and lan_adr_sw ='0' and AS='0' else
|
||||
DQ(7 downto 0)&DQ(15 downto 8) when RW='1' and lan_adr ='1' and lan_adr_sw ='1' and AS='0' else
|
||||
DQ(7 downto 0)&DQ(7 downto 0) when RW='1' and cp = '1' and AS='0' else
|
||||
DQ when RW='1' and ide = '1' and AS='0' else
|
||||
Dout1 & x"FFF" when RW='1' and autoconfig ='1' and AS='0' else
|
||||
(others => 'Z');
|
||||
|
||||
--defined lancp signal that matches both LAN and CP addresses (and IDE for Rev2 boards)
|
||||
DQ <= LAN_D_CLR when (LAN_RST_SM = wait0 or LAN_RST_SM = clr or LAN_RST_SM = clr_commit) else
|
||||
LAN_D_SET when (LAN_RST_SM = wait1 or LAN_RST_SM = set or LAN_RST_SM = set_commit) else
|
||||
D( 7 downto 0) & D( 7 downto 0) when RW='0' and AS='0' and lancp = '1' and LDS='0' and UDS='1' else
|
||||
D(15 downto 8) & D(15 downto 8) when RW='0' and AS='0' and lancp = '1' and LDS='1' and UDS='0' else
|
||||
D( 7 downto 0) & D(15 downto 8) when RW='0' and AS='0' and lan_adr ='1' and lan_adr_sw ='1' else
|
||||
D when RW='0' and AS='0' and lancp ='1'
|
||||
else (others => 'Z');
|
||||
|
||||
IDE_W <= IDE_W_S when AS='0' else '1';
|
||||
IDE_R <= IDE_R_S when AS='0' else '1';
|
||||
IDE_CS(0)<= not(A(12));
|
||||
IDE_CS(1)<= not(A(13));
|
||||
IDE_A(2 downto 0) <= A(11 downto 9);
|
||||
ROM_B <= "00";
|
||||
ROM_OE <= ROM_OE_S when AS='0' and AUTOBOOT_OFF = '0' else '1';
|
||||
|
||||
-- INT_OUT <= 'Z';
|
||||
INT_OUT <= '0' when
|
||||
(LAN_IRQ_OUT = '0' and LAN_INT_ENABLE = '1')
|
||||
or CP_IRQ = '0'
|
||||
else 'Z';
|
||||
|
||||
OWN <= 'Z';--'0' when AS='0' and (autoconfig = '1' or ide = '1' or lan_adr = '1' or cp = '1') else 'Z';
|
||||
SLAVE <= '0' when AS='0' and (autoconfig = '1' or ide = '1' or lan_adr = '1' or cp = '1') else '1';
|
||||
CFOUT <= '0' when AUTO_CONFIG_DONE=3 else '1';
|
||||
|
||||
-- OVR <= 'Z';
|
||||
OVR <= '0' when ide='1' and AS='0' else 'Z';
|
||||
|
||||
-- DTACK <= DTACK_S when --TRANSFER_IN_PROGRES ='1' or
|
||||
-- AUTOCONFIG_IN_PROGRES ='1'
|
||||
-- else 'Z';
|
||||
|
||||
DTACK <= '0' when ide='1' and AS='0' and IDE_WAIT='1' else 'Z';
|
||||
-- DTACK <= 'Z';
|
||||
A <= (others => 'Z');
|
||||
MTACK <= 'Z';
|
||||
|
||||
|
||||
end Behavioral;
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,460 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 23:59:54 01/15/2017
|
||||
-- Design Name:
|
||||
-- Module Name: C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP_TB.vhd
|
||||
-- Project Name: LAN_IDE
|
||||
-- Target Device:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-- VHDL Test Bench Created by ISE for module: LAN_IDE_CP
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
-- Notes:
|
||||
-- This testbench has been automatically generated using types std_logic and
|
||||
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
|
||||
-- that these types always be used for the top-level I/O of a design in order
|
||||
-- to guarantee that the testbench will bind correctly to the post-implementation
|
||||
-- simulation model.
|
||||
--------------------------------------------------------------------------------
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
--USE ieee.numeric_std.ALL;
|
||||
|
||||
ENTITY LAN_IDE_CP_TB IS
|
||||
END LAN_IDE_CP_TB;
|
||||
|
||||
ARCHITECTURE behavior OF LAN_IDE_CP_TB IS
|
||||
|
||||
-- Component Declaration for the Unit Under Test (UUT)
|
||||
|
||||
COMPONENT LAN_IDE_CP
|
||||
PORT(
|
||||
A : INOUT std_logic_vector(23 downto 1);
|
||||
D : INOUT std_logic_vector(15 downto 0);
|
||||
DQ : INOUT std_logic_vector(15 downto 0);
|
||||
A_LAN : OUT std_logic_vector(13 downto 0);
|
||||
OWN : OUT std_logic;
|
||||
SLAVE : OUT std_logic;
|
||||
CFOUT : OUT std_logic;
|
||||
CFIN : IN std_logic;
|
||||
C1 : IN std_logic;
|
||||
C3 : IN std_logic;
|
||||
MTCR : IN std_logic;
|
||||
OVR : OUT std_logic;
|
||||
BERR : IN std_logic;
|
||||
MTACK : OUT std_logic;
|
||||
DS0 : IN std_logic;
|
||||
DTACK : OUT std_logic;
|
||||
UDS : IN std_logic;
|
||||
LDS : IN std_logic;
|
||||
AS : IN std_logic;
|
||||
RW : IN std_logic;
|
||||
Z3 : IN std_logic;
|
||||
DS1 : IN std_logic;
|
||||
FCS : IN std_logic;
|
||||
RESET : IN std_logic;
|
||||
INT_OUT : OUT std_logic;
|
||||
AUTOBOOT_OFF : IN std_logic;
|
||||
ROM_B : OUT std_logic_vector(1 downto 0);
|
||||
ROM_OE : OUT std_logic;
|
||||
IDE_WAIT : IN std_logic;
|
||||
CLK_EXT : IN std_logic;
|
||||
IDE_W : OUT std_logic;
|
||||
IDE_R : OUT std_logic;
|
||||
IDE_A : OUT std_logic_vector(2 downto 0);
|
||||
IDE_CS : OUT std_logic_vector(1 downto 0);
|
||||
LAN_CFG : OUT std_logic_vector(4 downto 1);
|
||||
LAN_RD : OUT std_logic;
|
||||
LAN_CS : OUT std_logic;
|
||||
LAN_WRH : OUT std_logic;
|
||||
LAN_WRL : OUT std_logic;
|
||||
LAN_INT : IN std_logic;
|
||||
CP_RD : OUT std_logic;
|
||||
CP_WE : OUT std_logic;
|
||||
CP_CS : OUT std_logic;
|
||||
CP_IRQ : IN std_logic
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
|
||||
--Inputs
|
||||
signal CFIN : std_logic := '0';
|
||||
signal C1 : std_logic := '0';
|
||||
signal C3 : std_logic := '0';
|
||||
signal MTCR : std_logic := '0';
|
||||
signal BERR : std_logic := '0';
|
||||
signal DS0 : std_logic := '0';
|
||||
signal UDS : std_logic := '0';
|
||||
signal LDS : std_logic := '0';
|
||||
signal AS : std_logic := '0';
|
||||
signal RW : std_logic := '0';
|
||||
signal Z3 : std_logic := '0';
|
||||
signal DS1 : std_logic := '0';
|
||||
signal FCS : std_logic := '0';
|
||||
signal RESET : std_logic := '0';
|
||||
signal AUTOBOOT_OFF : std_logic := '0';
|
||||
signal IDE_WAIT : std_logic := '0';
|
||||
signal CLK_EXT : std_logic := '0';
|
||||
signal LAN_INT : std_logic := '0';
|
||||
signal CP_IRQ : std_logic := '0';
|
||||
|
||||
--BiDirs
|
||||
signal A : std_logic_vector(23 downto 1);
|
||||
signal D : std_logic_vector(15 downto 0);
|
||||
signal DQ : std_logic_vector(15 downto 0);
|
||||
|
||||
--Outputs
|
||||
signal A_LAN : std_logic_vector(13 downto 0);
|
||||
signal OWN : std_logic;
|
||||
signal SLAVE : std_logic;
|
||||
signal CFOUT : std_logic;
|
||||
signal OVR : std_logic;
|
||||
signal MTACK : std_logic;
|
||||
signal DTACK : std_logic;
|
||||
signal INT_OUT : std_logic;
|
||||
signal ROM_B : std_logic_vector(1 downto 0);
|
||||
signal ROM_OE : std_logic;
|
||||
signal IDE_W : std_logic;
|
||||
signal IDE_R : std_logic;
|
||||
signal IDE_A : std_logic_vector(2 downto 0);
|
||||
signal IDE_CS : std_logic_vector(1 downto 0);
|
||||
signal LAN_CFG : std_logic_vector(4 downto 1);
|
||||
signal LAN_RD : std_logic;
|
||||
signal LAN_CS : std_logic;
|
||||
signal LAN_WRH : std_logic;
|
||||
signal LAN_WRL : std_logic;
|
||||
signal CP_RD : std_logic;
|
||||
signal CP_WE : std_logic;
|
||||
signal CP_CS : std_logic;
|
||||
|
||||
-- Clock period definitions
|
||||
signal AMIGA_CLK :std_logic;
|
||||
|
||||
constant CLK_EXT_period : time := 40 ns;
|
||||
constant CLK_AMIGA_period : time := 140 ns;
|
||||
|
||||
|
||||
BEGIN
|
||||
|
||||
-- Instantiate the Unit Under Test (UUT)
|
||||
uut: LAN_IDE_CP PORT MAP (
|
||||
A => A,
|
||||
D => D,
|
||||
DQ => DQ,
|
||||
A_LAN => A_LAN,
|
||||
OWN => OWN,
|
||||
SLAVE => SLAVE,
|
||||
CFOUT => CFOUT,
|
||||
CFIN => CFIN,
|
||||
C1 => C1,
|
||||
C3 => C3,
|
||||
MTCR => MTCR,
|
||||
OVR => OVR,
|
||||
BERR => BERR,
|
||||
MTACK => MTACK,
|
||||
DS0 => DS0,
|
||||
DTACK => DTACK,
|
||||
UDS => UDS,
|
||||
LDS => LDS,
|
||||
AS => AS,
|
||||
RW => RW,
|
||||
Z3 => Z3,
|
||||
DS1 => DS1,
|
||||
FCS => FCS,
|
||||
RESET => RESET,
|
||||
INT_OUT => INT_OUT,
|
||||
AUTOBOOT_OFF => AUTOBOOT_OFF,
|
||||
ROM_B => ROM_B,
|
||||
ROM_OE => ROM_OE,
|
||||
IDE_WAIT => IDE_WAIT,
|
||||
CLK_EXT => CLK_EXT,
|
||||
IDE_W => IDE_W,
|
||||
IDE_R => IDE_R,
|
||||
IDE_A => IDE_A,
|
||||
IDE_CS => IDE_CS,
|
||||
LAN_CFG => LAN_CFG,
|
||||
LAN_RD => LAN_RD,
|
||||
LAN_CS => LAN_CS,
|
||||
LAN_WRH => LAN_WRH,
|
||||
LAN_WRL => LAN_WRL,
|
||||
LAN_INT => LAN_INT,
|
||||
CP_RD => CP_RD,
|
||||
CP_WE => CP_WE,
|
||||
CP_CS => CP_CS,
|
||||
CP_IRQ => CP_IRQ
|
||||
);
|
||||
|
||||
AMIGA_CLK <= not (C1 xor C3);
|
||||
|
||||
-- Clock process definitions
|
||||
CLK_EXT_process :process
|
||||
begin
|
||||
CLK_EXT <= '0';
|
||||
wait for CLK_EXT_period/2;
|
||||
CLK_EXT <= '1';
|
||||
wait for CLK_EXT_period/2;
|
||||
end process;
|
||||
|
||||
-- Clock process definitions
|
||||
CLK_13_process :process
|
||||
begin
|
||||
C1 <= '1';
|
||||
C3 <= '0';
|
||||
wait for CLK_AMIGA_period/2;
|
||||
C1 <= '0';
|
||||
C3 <= '0';
|
||||
wait for CLK_AMIGA_period/2;
|
||||
C1 <= '0';
|
||||
C3 <= '1';
|
||||
wait for CLK_AMIGA_period/2;
|
||||
C1 <= '1';
|
||||
C3 <= '1';
|
||||
wait for CLK_AMIGA_period/2;
|
||||
end process;
|
||||
|
||||
|
||||
-- Stimulus process
|
||||
stim_proc: process
|
||||
begin
|
||||
-- hold reset state for 100 ns.
|
||||
RESET <='0';
|
||||
AS <='1';
|
||||
BERR <='1';
|
||||
D <= (others=>'Z');
|
||||
DQ <= (others=>'Z');
|
||||
A <= (others=>'Z');
|
||||
RW <='1';
|
||||
UDS <='1';
|
||||
LDS <='1';
|
||||
CFIN <='0';
|
||||
|
||||
MTCR <='1';
|
||||
DS0 <='1';
|
||||
Z3 <='0';
|
||||
DS1 <='1';
|
||||
FCS <='1';
|
||||
AUTOBOOT_OFF <='1';
|
||||
IDE_WAIT <='1';
|
||||
LAN_INT <='1';
|
||||
CP_IRQ <='1';
|
||||
|
||||
wait for 100 ns;
|
||||
reset <='1';
|
||||
|
||||
wait for CLK_AMIGA_period*10;
|
||||
|
||||
--make a quick autoconfig
|
||||
wait until rising_edge(AMIGA_CLK); --S0
|
||||
RW <='1';
|
||||
wait until falling_edge(AMIGA_CLK); --S1
|
||||
A(23 downto 16) <= x"E8";
|
||||
A(15 downto 8) <= x"00";
|
||||
A(7 downto 1) <= "0100100";
|
||||
wait until rising_edge(AMIGA_CLK); --S2
|
||||
AS<='0';
|
||||
RW<='0';
|
||||
wait until falling_edge(AMIGA_CLK); --S3
|
||||
D <= x"EAEA"; --address config 1
|
||||
wait until rising_edge(AMIGA_CLK); --S4
|
||||
UDS <='0';
|
||||
wait until falling_edge(AMIGA_CLK); --S5
|
||||
wait until rising_edge(AMIGA_CLK); --S6
|
||||
wait until falling_edge(AMIGA_CLK); --S7
|
||||
AS <='1';
|
||||
UDS <='1';
|
||||
LDS <='1';
|
||||
D <= (others=>'Z');
|
||||
|
||||
|
||||
wait until rising_edge(AMIGA_CLK); --S0
|
||||
RW <='1';
|
||||
wait until falling_edge(AMIGA_CLK); --S1
|
||||
A(23 downto 16) <= x"E8";
|
||||
A(15 downto 8) <= x"00";
|
||||
A(7 downto 1) <= "0100100";
|
||||
wait until rising_edge(AMIGA_CLK); --S2
|
||||
AS<='0';
|
||||
RW<='0';
|
||||
wait until falling_edge(AMIGA_CLK); --S3
|
||||
D <= x"EBEB"; --address config 2
|
||||
wait until rising_edge(AMIGA_CLK); --S4
|
||||
UDS <='0';
|
||||
wait until falling_edge(AMIGA_CLK); --S5
|
||||
wait until rising_edge(AMIGA_CLK); --S6
|
||||
wait until falling_edge(AMIGA_CLK); --S7
|
||||
AS <='1';
|
||||
UDS <='1';
|
||||
LDS <='1';
|
||||
D <= (others=>'Z');
|
||||
|
||||
wait until rising_edge(AMIGA_CLK); --S0
|
||||
RW <='1';
|
||||
wait until falling_edge(AMIGA_CLK); --S1
|
||||
A(23 downto 16) <= x"E8";
|
||||
A(15 downto 8) <= x"00";
|
||||
A(7 downto 1) <= "0100100";
|
||||
wait until rising_edge(AMIGA_CLK); --S2
|
||||
AS<='0';
|
||||
RW<='0';
|
||||
wait until falling_edge(AMIGA_CLK); --S3
|
||||
D <= x"ECEC"; --address config 3
|
||||
wait until rising_edge(AMIGA_CLK); --S4
|
||||
UDS <='0';
|
||||
wait until falling_edge(AMIGA_CLK); --S5
|
||||
wait until rising_edge(AMIGA_CLK); --S6
|
||||
wait until falling_edge(AMIGA_CLK); --S7
|
||||
AS <='1';
|
||||
UDS <='1';
|
||||
LDS <='1';
|
||||
D <= (others=>'Z');
|
||||
|
||||
--now do some I/O on LAN
|
||||
wait until rising_edge(AMIGA_CLK); --S0
|
||||
RW <='1';
|
||||
wait until falling_edge(AMIGA_CLK); --S1
|
||||
A(23 downto 16) <= x"EA";
|
||||
A(15 downto 8) <= x"00";
|
||||
A(7 downto 1) <= "0100100";
|
||||
wait until rising_edge(AMIGA_CLK); --S2
|
||||
AS<='0';
|
||||
RW<='0';
|
||||
wait until falling_edge(AMIGA_CLK); --S3
|
||||
D <= x"B00B"; --Testdata
|
||||
wait until rising_edge(AMIGA_CLK); --S4
|
||||
UDS <='0';
|
||||
LDS <='0';
|
||||
wait until falling_edge(AMIGA_CLK); --S5
|
||||
wait until rising_edge(AMIGA_CLK); --S6
|
||||
wait until falling_edge(AMIGA_CLK); --S7
|
||||
AS <='1';
|
||||
UDS <='1';
|
||||
LDS <='1';
|
||||
D <= (others=>'Z');
|
||||
|
||||
wait until rising_edge(AMIGA_CLK); --S0
|
||||
RW <='1';
|
||||
wait until falling_edge(AMIGA_CLK); --S1
|
||||
A(23 downto 16) <= x"EA";
|
||||
A(15 downto 8) <= x"00";
|
||||
A(7 downto 1) <= "0100100";
|
||||
wait until rising_edge(AMIGA_CLK); --S2
|
||||
AS<='0';
|
||||
RW<='1';
|
||||
UDS <='0';
|
||||
LDS <='0';
|
||||
wait until falling_edge(AMIGA_CLK); --S3
|
||||
wait until rising_edge(AMIGA_CLK); --S4
|
||||
wait until falling_edge(AMIGA_CLK); --S5
|
||||
wait until rising_edge(AMIGA_CLK); --S6
|
||||
wait until falling_edge(AMIGA_CLK); --S7
|
||||
AS <='1';
|
||||
UDS <='1';
|
||||
LDS <='1';
|
||||
D <= (others=>'Z');
|
||||
|
||||
--now do some I/O on CS
|
||||
wait until rising_edge(AMIGA_CLK); --S0
|
||||
RW <='1';
|
||||
wait until falling_edge(AMIGA_CLK); --S1
|
||||
A(23 downto 16) <= x"EB";
|
||||
A(15 downto 8) <= x"00";
|
||||
A(7 downto 1) <= "0100100";
|
||||
wait until rising_edge(AMIGA_CLK); --S2
|
||||
AS<='0';
|
||||
RW<='0';
|
||||
wait until falling_edge(AMIGA_CLK); --S3
|
||||
D <= x"B00B"; --Testdata
|
||||
wait until rising_edge(AMIGA_CLK); --S4
|
||||
UDS <='0';
|
||||
LDS <='0';
|
||||
wait until falling_edge(AMIGA_CLK); --S5
|
||||
wait until rising_edge(AMIGA_CLK); --S6
|
||||
wait until falling_edge(AMIGA_CLK); --S7
|
||||
AS <='1';
|
||||
UDS <='1';
|
||||
LDS <='1';
|
||||
D <= (others=>'Z');
|
||||
|
||||
wait until rising_edge(AMIGA_CLK); --S0
|
||||
RW <='1';
|
||||
wait until falling_edge(AMIGA_CLK); --S1
|
||||
A(23 downto 16) <= x"EB";
|
||||
A(15 downto 8) <= x"00";
|
||||
A(7 downto 1) <= "0100100";
|
||||
wait until rising_edge(AMIGA_CLK); --S2
|
||||
AS<='0';
|
||||
RW<='1';
|
||||
UDS <='0';
|
||||
LDS <='0';
|
||||
wait until falling_edge(AMIGA_CLK); --S3
|
||||
wait until rising_edge(AMIGA_CLK); --S4
|
||||
wait until falling_edge(AMIGA_CLK); --S5
|
||||
wait until rising_edge(AMIGA_CLK); --S6
|
||||
wait until falling_edge(AMIGA_CLK); --S7
|
||||
AS <='1';
|
||||
UDS <='1';
|
||||
LDS <='1';
|
||||
D <= (others=>'Z');
|
||||
|
||||
--now do some I/O on IDE
|
||||
wait until rising_edge(AMIGA_CLK); --S0
|
||||
RW <='1';
|
||||
wait until falling_edge(AMIGA_CLK); --S1
|
||||
A(23 downto 16) <= x"EC";
|
||||
A(15 downto 8) <= x"00";
|
||||
A(7 downto 1) <= "0100100";
|
||||
wait until rising_edge(AMIGA_CLK); --S2
|
||||
AS<='0';
|
||||
RW<='0';
|
||||
wait until falling_edge(AMIGA_CLK); --S3
|
||||
D <= x"B00B"; --Testdata
|
||||
wait until rising_edge(AMIGA_CLK); --S4
|
||||
UDS <='0';
|
||||
LDS <='0';
|
||||
wait until falling_edge(AMIGA_CLK); --S5
|
||||
wait until rising_edge(AMIGA_CLK); --S6
|
||||
wait until falling_edge(AMIGA_CLK); --S7
|
||||
AS <='1';
|
||||
UDS <='1';
|
||||
LDS <='1';
|
||||
D <= (others=>'Z');
|
||||
|
||||
wait until rising_edge(AMIGA_CLK); --S0
|
||||
RW <='1';
|
||||
wait until falling_edge(AMIGA_CLK); --S1
|
||||
A(23 downto 16) <= x"EC";
|
||||
A(15 downto 8) <= x"00";
|
||||
A(7 downto 1) <= "0100100";
|
||||
wait until rising_edge(AMIGA_CLK); --S2
|
||||
AS<='0';
|
||||
RW<='1';
|
||||
UDS <='0';
|
||||
LDS <='0';
|
||||
wait until falling_edge(AMIGA_CLK); --S3
|
||||
wait until rising_edge(AMIGA_CLK); --S4
|
||||
wait until falling_edge(AMIGA_CLK); --S5
|
||||
wait until rising_edge(AMIGA_CLK); --S6
|
||||
wait until falling_edge(AMIGA_CLK); --S7
|
||||
AS <='1';
|
||||
UDS <='1';
|
||||
LDS <='1';
|
||||
D <= (others=>'Z');
|
||||
|
||||
wait until rising_edge(AMIGA_CLK);
|
||||
wait until falling_edge(AMIGA_CLK);
|
||||
wait;
|
||||
end process;
|
||||
|
||||
END;
|
||||
@@ -0,0 +1,151 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- For tool use only. Do not edit. -->
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- ProjectNavigator created generated project file. -->
|
||||
|
||||
<!-- For use in tracking generated file and other information -->
|
||||
|
||||
<!-- allowing preservation of process status. -->
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
|
||||
|
||||
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
|
||||
|
||||
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="LAN_IDEz2v2.xise"/>
|
||||
|
||||
<files xmlns="http://www.xilinx.com/XMLSchema">
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="LAN_IDE_CP.bld"/>
|
||||
<file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="LAN_IDE_CP.cmd_log"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_GYD" xil_pn:name="LAN_IDE_CP.gyd"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_JEDEC" xil_pn:name="LAN_IDE_CP.jed"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="LAN_IDE_CP.lso"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MFD" xil_pn:name="LAN_IDE_CP.mfd"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGA" xil_pn:name="LAN_IDE_CP.nga"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="LAN_IDE_CP.ngc"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGD" xil_pn:name="LAN_IDE_CP.ngd"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="LAN_IDE_CP.ngr"/>
|
||||
<file xil_pn:fileType="FILE_PAD_MISC" xil_pn:name="LAN_IDE_CP.pad"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PNX" xil_pn:name="LAN_IDE_CP.pnx"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="LAN_IDE_CP.prj"/>
|
||||
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="LAN_IDE_CP.rpt"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="LAN_IDE_CP.stx"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="LAN_IDE_CP.syr"/>
|
||||
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="LAN_IDE_CP.tspec"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_VM6" xil_pn:name="LAN_IDE_CP.vm6"/>
|
||||
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="LAN_IDE_CP.xml"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="LAN_IDE_CP.xst"/>
|
||||
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="LAN_IDE_CP_build.xml"/>
|
||||
<file xil_pn:fileType="FILE_HTML" xil_pn:name="LAN_IDE_CP_envsettings.html"/>
|
||||
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="LAN_IDE_CP_html"/>
|
||||
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="LAN_IDE_CP_ngdbuild.xrpt"/>
|
||||
<file xil_pn:fileType="FILE_PAD_EXCEL_REPORT" xil_pn:name="LAN_IDE_CP_pad.csv"/>
|
||||
<file xil_pn:fileType="FILE_HTML" xil_pn:name="LAN_IDE_CP_summary.html"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="LAN_IDE_CP_vhdl.prj"/>
|
||||
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="LAN_IDE_CP_xst.xrpt"/>
|
||||
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="_ngo"/>
|
||||
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
|
||||
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/xst.xmsgs"/>
|
||||
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="webtalk_pn.xml"/>
|
||||
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xlnx_auto_0_xdb"/>
|
||||
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xst"/>
|
||||
</files>
|
||||
|
||||
<transforms xmlns="http://www.xilinx.com/XMLSchema">
|
||||
<transform xil_pn:end_ts="1545128934" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1545128934">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1545128934" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="5081391373936803697" xil_pn:start_ts="1545128934">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1545595558" xil_pn:in_ck="-2520376148396271922" xil_pn:name="TRANEXT_xstsynthesize_xc9500xl" xil_pn:prop_ck="1235887333676579674" xil_pn:start_ts="1545595546">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="WarningsGenerated"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForInputs"/>
|
||||
<outfile xil_pn:name="LAN_IDE_CP.lso"/>
|
||||
<outfile xil_pn:name="LAN_IDE_CP.ngc"/>
|
||||
<outfile xil_pn:name="LAN_IDE_CP.ngr"/>
|
||||
<outfile xil_pn:name="LAN_IDE_CP.prj"/>
|
||||
<outfile xil_pn:name="LAN_IDE_CP.stx"/>
|
||||
<outfile xil_pn:name="LAN_IDE_CP.syr"/>
|
||||
<outfile xil_pn:name="LAN_IDE_CP.xst"/>
|
||||
<outfile xil_pn:name="LAN_IDE_CP_vhdl.prj"/>
|
||||
<outfile xil_pn:name="LAN_IDE_CP_xst.xrpt"/>
|
||||
<outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
|
||||
<outfile xil_pn:name="webtalk_pn.xml"/>
|
||||
<outfile xil_pn:name="xst"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1545079613" xil_pn:in_ck="176569500195729039" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-8537920303570934858" xil_pn:start_ts="1545079613">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1545595565" xil_pn:in_ck="-8547647177936735053" xil_pn:name="TRAN_ngdbuild" xil_pn:prop_ck="6932115226421322529" xil_pn:start_ts="1545595558">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="WarningsGenerated"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForInputs"/>
|
||||
<status xil_pn:value="OutOfDateForPredecessor"/>
|
||||
<outfile xil_pn:name="LAN_IDE_CP.bld"/>
|
||||
<outfile xil_pn:name="LAN_IDE_CP.ngd"/>
|
||||
<outfile xil_pn:name="LAN_IDE_CP_ngdbuild.xrpt"/>
|
||||
<outfile xil_pn:name="_ngo"/>
|
||||
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1545595609" xil_pn:in_ck="-2520376148396280667" xil_pn:name="TRANEXT_vm6File_xc9500xl" xil_pn:prop_ck="-1014768965495450326" xil_pn:start_ts="1545595565">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="WarningsGenerated"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForPredecessor"/>
|
||||
<outfile xil_pn:name="LAN_IDE_CP.gyd"/>
|
||||
<outfile xil_pn:name="LAN_IDE_CP.mfd"/>
|
||||
<outfile xil_pn:name="LAN_IDE_CP.nga"/>
|
||||
<outfile xil_pn:name="LAN_IDE_CP.pad"/>
|
||||
<outfile xil_pn:name="LAN_IDE_CP.pnx"/>
|
||||
<outfile xil_pn:name="LAN_IDE_CP.rpt"/>
|
||||
<outfile xil_pn:name="LAN_IDE_CP.tspec"/>
|
||||
<outfile xil_pn:name="LAN_IDE_CP.vm6"/>
|
||||
<outfile xil_pn:name="LAN_IDE_CP.xml"/>
|
||||
<outfile xil_pn:name="LAN_IDE_CP_build.xml"/>
|
||||
<outfile xil_pn:name="LAN_IDE_CP_html"/>
|
||||
<outfile xil_pn:name="LAN_IDE_CP_pad.csv"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1545595612" xil_pn:in_ck="-2520376148396271803" xil_pn:name="TRANEXT_crtProg_xc9500" xil_pn:prop_ck="-6294026017969277533" xil_pn:start_ts="1545595609">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForPredecessor"/>
|
||||
<outfile xil_pn:name="LAN_IDE_CP.jed"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1545129218" xil_pn:in_ck="-2520376148396285089" xil_pn:name="TRAN_impactProgrammingTool_CPLD" xil_pn:prop_ck="-3598488201878296819" xil_pn:start_ts="1545129218">
|
||||
<status xil_pn:value="AbortedRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForInputs"/>
|
||||
<status xil_pn:value="OutOfDateForPredecessor"/>
|
||||
<status xil_pn:value="OutOfDateForced"/>
|
||||
<status xil_pn:value="InputChanged"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1545595676" xil_pn:in_ck="-2520376148396285089" xil_pn:name="TRAN_configureTargetDevice_CPLD" xil_pn:prop_ck="-154879694275837835" xil_pn:start_ts="1545595673">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForPredecessor"/>
|
||||
</transform>
|
||||
<transform xil_pn:name="TRAN_timRpt">
|
||||
<status xil_pn:value="AbortedRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForInputs"/>
|
||||
<status xil_pn:value="OutOfDateForPredecessor"/>
|
||||
<status xil_pn:value="InputAdded"/>
|
||||
<status xil_pn:value="InputChanged"/>
|
||||
</transform>
|
||||
</transforms>
|
||||
|
||||
</generated_project>
|
||||
@@ -0,0 +1,244 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
|
||||
|
||||
<header>
|
||||
<!-- ISE source project file created by Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- This file contains project source information including a list of -->
|
||||
<!-- project source files, project and process properties. This file, -->
|
||||
<!-- along with the project source files, is sufficient to open and -->
|
||||
<!-- implement in ISE Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
|
||||
</header>
|
||||
|
||||
<version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
|
||||
|
||||
<files>
|
||||
<file xil_pn:name="LAN_IDE_CP-Z2v2.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
|
||||
</file>
|
||||
<file xil_pn:name="pinlist.ucf" xil_pn:type="FILE_UCF">
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
||||
</file>
|
||||
<file xil_pn:name="LAN_IDE_CP_TB.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
|
||||
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="74"/>
|
||||
</file>
|
||||
</files>
|
||||
|
||||
<properties>
|
||||
<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Auto Implementation Top" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Autosignature Generation" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bus Delimiter" xil_pn:value="<>" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Clock Enable" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Collapsing Input Limit (2-54)" xil_pn:value="54" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Collapsing Pterm Limit (1-90)" xil_pn:value="25" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile CPLD Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile uni9000 (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Programmable GND Pins on Unused I/O" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Default Powerup Value of Registers" xil_pn:value="Low" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Device" xil_pn:value="xc95288xl" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device Family" xil_pn:value="XC9500XL CPLDs" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-10" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Exhaustive Fit Mode" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Compact" xil_pn:valueState="non-default" xil_pn:x_locked="true"/>
|
||||
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Post-Fit Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="HDL Equations Style" xil_pn:value="Source" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="I/O Pin Termination" xil_pn:value="Keeper" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Implementation Template" xil_pn:value="Optimize Balance" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|LAN_IDE_CP|Behavioral" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top File" xil_pn:value="LAN_IDE_CP-Z2v2.vhd" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/LAN_IDE_CP" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Keep Hierarchy CPLD" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Last Applied Strategy" xil_pn:value="area;C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/area.xds" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Logic Optimization" xil_pn:value="Speed" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Macro Preserve" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Macrocell Power Setting" xil_pn:value="Std" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Max Fanout" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="4" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default" xil_pn:x_locked="true"/>
|
||||
<property xil_pn:name="Other CPLD Fitter Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Fit" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Programming Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Fit" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Timing Report Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output File Name" xil_pn:value="LAN_IDE_CP" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output Slew Rate" xil_pn:value="Fast" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Package" xil_pn:value="TQ144" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="LAN_IDE_CP_map.vhd" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="LAN_IDE_CP_timesim.vhd" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="LAN_IDE_CP_synthesis.vhd" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="LAN_IDE_CP_translate.vhd" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Preserve Unused Inputs" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="LAN_IDE_CP" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default" xil_pn:x_locked="true"/>
|
||||
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Signature /User Code" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Fit" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Speed Grade" xil_pn:value="-10" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Target UCF File Name" xil_pn:value="pinlist.ucf" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Timing Report Format" xil_pn:value="Summary" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Fit" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Fit" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Global Clocks" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Global Output Enables" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Global Set/Reset" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Location Constraints" xil_pn:value="Always" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Multi-level Logic Optimization" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Timing Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/area.xds" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="VCCIO Reference Voltage" xil_pn:value="LVTTL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="WYSIWYG" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="XOR Preserve" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<!-- -->
|
||||
<!-- The following properties are for internal use only. These should not be modified.-->
|
||||
<!-- -->
|
||||
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|LAN_IDE_CP_TB|behavior" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_DesignName" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="xc9500xl" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2018-12-18T11:26:25" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="A2E624B6ED1449CD92F77DE849BF7B51" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
|
||||
</properties>
|
||||
|
||||
<bindings/>
|
||||
|
||||
<libraries/>
|
||||
|
||||
<autoManagedFiles>
|
||||
<!-- The following files are identified by `include statements in verilog -->
|
||||
<!-- source files and are automatically managed by Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- Do not hand-edit this section, as it will be overwritten when the -->
|
||||
<!-- project is analyzed based on files automatically identified as -->
|
||||
<!-- include files. -->
|
||||
</autoManagedFiles>
|
||||
|
||||
</project>
|
||||
@@ -0,0 +1,215 @@
|
||||
<?xml version='1.0' encoding='UTF-8'?>
|
||||
<report-views version="2.0" >
|
||||
<header>
|
||||
<DateModified>2019-02-17T00:06:37</DateModified>
|
||||
<ModuleName>LAN_IDE_CP</ModuleName>
|
||||
<SummaryTimeStamp>Unknown</SummaryTimeStamp>
|
||||
<SavedFilePath>C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE_V2/iseconfig/LAN_IDE_CP.xreport</SavedFilePath>
|
||||
<ImplementationReportsDirectory>C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE_V2\</ImplementationReportsDirectory>
|
||||
<DateInitialized>2019-01-09T22:34:04</DateInitialized>
|
||||
<EnableMessageFiltering>false</EnableMessageFiltering>
|
||||
</header>
|
||||
<body>
|
||||
<viewgroup label="Design Overview" >
|
||||
<view inputState="Unknown" program="implementation" ShowPartitionData="false" type="FPGASummary" file="LAN_IDE_CP_summary.html" label="Summary" >
|
||||
<toc-item title="Design Overview" target="Design Overview" />
|
||||
<toc-item title="Design Utilization Summary" target="Design Utilization Summary" />
|
||||
<toc-item title="Performance Summary" target="Performance Summary" />
|
||||
<toc-item title="Failing Constraints" target="Failing Constraints" />
|
||||
<toc-item title="Detailed Reports" target="Detailed Reports" />
|
||||
</view>
|
||||
<view inputState="Unknown" program="implementation" contextTags="FPGA_ONLY" hidden="true" type="HTML" file="LAN_IDE_CP_envsettings.html" label="System Settings" />
|
||||
<view inputState="Translated" program="map" locator="MAP_IOB_TABLE" contextTags="FPGA_ONLY" hidden="true" type="IOBProperties" file="LAN_IDE_CP_map.xrpt" label="IOB Properties" />
|
||||
<view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Control_Sets" file="LAN_IDE_CP_map.xrpt" label="Control Set Information" />
|
||||
<view inputState="Translated" program="map" locator="MAP_MODULE_HIERARCHY" contextTags="FPGA_ONLY" hidden="true" type="Module_Utilization" file="LAN_IDE_CP_map.xrpt" label="Module Level Utilization" />
|
||||
<view inputState="Mapped" program="par" locator="CONSTRAINT_TABLE" contextTags="FPGA_ONLY" hidden="true" type="ConstraintsData" file="LAN_IDE_CP.ptwx" label="Timing Constraints" translator="ptwxToTableXML.xslt" />
|
||||
<view inputState="Mapped" program="par" locator="PAR_PINOUT_BY_PIN_NUMBER" contextTags="FPGA_ONLY" hidden="true" type="PinoutData" file="LAN_IDE_CP_par.xrpt" label="Pinout Report" />
|
||||
<view inputState="Mapped" program="par" locator="PAR_CLOCK_TABLE" contextTags="FPGA_ONLY" hidden="true" type="ClocksData" file="LAN_IDE_CP_par.xrpt" label="Clock Report" />
|
||||
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY,EDK_OFF" hidden="true" type="Timing_Analyzer" file="LAN_IDE_CP.twx" label="Static Timing" />
|
||||
<view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="false" type="EXTERNAL_HTML" file="LAN_IDE_CP_html/fit/report.htm" label="CPLD Fitter Report" />
|
||||
<view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="false" type="EXTERNAL_HTML" file="LAN_IDE_CP_html/tim/report.htm" label="CPLD Timing Report" />
|
||||
</viewgroup>
|
||||
<viewgroup label="XPS Errors and Warnings" >
|
||||
<view program="platgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/platgen.xmsgs" label="Platgen Messages" />
|
||||
<view program="simgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/simgen.xmsgs" label="Simgen Messages" />
|
||||
<view program="bitinit" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/bitinit.xmsgs" label="BitInit Messages" />
|
||||
</viewgroup>
|
||||
<viewgroup label="XPS Reports" >
|
||||
<view inputState="PreSynthesized" program="platgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="platgen.log" label="Platgen Log File" />
|
||||
<view inputState="PreSynthesized" program="simgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="simgen.log" label="Simgen Log File" />
|
||||
<view inputState="PreSynthesized" program="bitinit" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="bitinit.log" label="BitInit Log File" />
|
||||
<view inputState="PreSynthesized" program="system" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="LAN_IDE_CP.log" label="System Log File" />
|
||||
</viewgroup>
|
||||
<viewgroup label="Errors and Warnings" >
|
||||
<view program="pn" WrapMessages="true" contextTags="EDK_OFF" type="MessageList" hideColumns="Filtered, New" file="_xmsgs/pn_parser.xmsgs" label="Parser Messages" />
|
||||
<view program="xst" WrapMessages="true" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="MessageList" hideColumns="Filtered" file="_xmsgs/xst.xmsgs" label="Synthesis Messages" />
|
||||
<view inputState="Synthesized" program="ngdbuild" WrapMessages="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/ngdbuild.xmsgs" label="Translation Messages" />
|
||||
<view inputState="Translated" program="map" WrapMessages="true" contextTags="FPGA_ONLY" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/map.xmsgs" label="Map Messages" />
|
||||
<view inputState="Mapped" program="par" WrapMessages="true" contextTags="FPGA_ONLY" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/par.xmsgs" label="Place and Route Messages" />
|
||||
<view inputState="Routed" program="trce" WrapMessages="true" contextTags="FPGA_ONLY" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/trce.xmsgs" label="Timing Messages" />
|
||||
<view inputState="Routed" program="xpwr" WrapMessages="true" contextTags="EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/xpwr.xmsgs" label="Power Messages" />
|
||||
<view inputState="Routed" program="bitgen" WrapMessages="true" contextTags="FPGA_ONLY" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/bitgen.xmsgs" label="Bitgen Messages" />
|
||||
<view inputState="Translated" program="cpldfit" WrapMessages="true" contextTags="CPLD_ONLY,EDK_OFF" hidden="false" type="MessageList" hideColumns="Filtered" file="_xmsgs/cpldfit.xmsgs" label="Fitter Messages" />
|
||||
<view inputState="Current" program="implementation" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/map.xmsgs,_xmsgs/par.xmsgs,_xmsgs/trce.xmsgs,_xmsgs/xpwr.xmsgs,_xmsgs/bitgen.xmsgs" contextTags="FPGA_ONLY" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Implementation Messages" />
|
||||
<view inputState="Current" program="fitting" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/cpldfit.xmsgs,_xmsgs/xpwr.xmsgs" contextTags="CPLD_ONLY,EDK_OFF" hidden="false" type="CPLD_MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Implementation Messages (CPLD)" />
|
||||
</viewgroup>
|
||||
<viewgroup label="Detailed Reports" >
|
||||
<view program="xst" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="Report" file="LAN_IDE_CP.syr" label="Synthesis Report" >
|
||||
<toc-item title="Top of Report" target="Copyright " searchDir="Forward" />
|
||||
<toc-item title="Synthesis Options Summary" target=" Synthesis Options Summary " />
|
||||
<toc-item title="HDL Compilation" target=" HDL Compilation " />
|
||||
<toc-item title="Design Hierarchy Analysis" target=" Design Hierarchy Analysis " />
|
||||
<toc-item title="HDL Analysis" target=" HDL Analysis " />
|
||||
<toc-item title="HDL Parsing" target=" HDL Parsing " />
|
||||
<toc-item title="HDL Elaboration" target=" HDL Elaboration " />
|
||||
<toc-item title="HDL Synthesis" target=" HDL Synthesis " />
|
||||
<toc-item title="HDL Synthesis Report" target="HDL Synthesis Report" searchCnt="2" searchDir="Backward" subItemLevel="1" />
|
||||
<toc-item title="Advanced HDL Synthesis" target=" Advanced HDL Synthesis " searchDir="Backward" />
|
||||
<toc-item title="Advanced HDL Synthesis Report" target="Advanced HDL Synthesis Report" subItemLevel="1" />
|
||||
<toc-item title="Low Level Synthesis" target=" Low Level Synthesis " />
|
||||
<toc-item title="Partition Report" target=" Partition Report " />
|
||||
<toc-item title="Final Report" target=" Final Report " />
|
||||
<toc-item title="Design Summary" target=" Design Summary " />
|
||||
<toc-item title="Primitive and Black Box Usage" target="Primitive and Black Box Usage:" subItemLevel="1" />
|
||||
<toc-item title="Device Utilization Summary" target="Device utilization summary:" subItemLevel="1" />
|
||||
<toc-item title="Partition Resource Summary" target="Partition Resource Summary:" subItemLevel="1" />
|
||||
<toc-item title="Timing Report" target="Timing Report" subItemLevel="1" />
|
||||
<toc-item title="Clock Information" target="Clock Information" subItemLevel="2" />
|
||||
<toc-item title="Asynchronous Control Signals Information" target="Asynchronous Control Signals Information" subItemLevel="2" />
|
||||
<toc-item title="Timing Summary" target="Timing Summary" subItemLevel="2" />
|
||||
<toc-item title="Timing Details" target="Timing Details" subItemLevel="2" />
|
||||
<toc-item title="Cross Clock Domains Report" target="Cross Clock Domains Report:" subItemLevel="2" />
|
||||
</view>
|
||||
<view program="synplify" contextTags="SYNPLIFY_ONLY,EDK_OFF" hidden="true" type="Report" file="LAN_IDE_CP.srr" label="Synplify Report" />
|
||||
<view program="precision" contextTags="PRECISION_ONLY,EDK_OFF" hidden="true" type="Report" file="LAN_IDE_CP.prec_log" label="Precision Report" />
|
||||
<view inputState="Synthesized" program="ngdbuild" type="Report" file="LAN_IDE_CP.bld" label="Translation Report" >
|
||||
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
|
||||
<toc-item title="Command Line" target="Command Line:" />
|
||||
<toc-item title="Partition Status" target="Partition Implementation Status" />
|
||||
<toc-item title="Final Summary" target="NGDBUILD Design Results Summary:" />
|
||||
</view>
|
||||
<view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Report" file="LAN_IDE_CP_map.mrp" label="Map Report" >
|
||||
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
|
||||
<toc-item title="Section 1: Errors" target="Section 1 -" searchDir="Backward" />
|
||||
<toc-item title="Section 2: Warnings" target="Section 2 -" searchDir="Backward" />
|
||||
<toc-item title="Section 3: Infos" target="Section 3 -" searchDir="Backward" />
|
||||
<toc-item title="Section 4: Removed Logic Summary" target="Section 4 -" searchDir="Backward" />
|
||||
<toc-item title="Section 5: Removed Logic" target="Section 5 -" searchDir="Backward" />
|
||||
<toc-item title="Section 6: IOB Properties" target="Section 6 -" searchDir="Backward" />
|
||||
<toc-item title="Section 7: RPMs" target="Section 7 -" searchDir="Backward" />
|
||||
<toc-item title="Section 8: Guide Report" target="Section 8 -" searchDir="Backward" />
|
||||
<toc-item title="Section 9: Area Group and Partition Summary" target="Section 9 -" searchDir="Backward" />
|
||||
<toc-item title="Section 10: Timing Report" target="Section 10 -" searchDir="Backward" />
|
||||
<toc-item title="Section 11: Configuration String Details" target="Section 11 -" searchDir="Backward" />
|
||||
<toc-item title="Section 12: Control Set Information" target="Section 12 -" searchDir="Backward" />
|
||||
<toc-item title="Section 13: Utilization by Hierarchy" target="Section 13 -" searchDir="Backward" />
|
||||
</view>
|
||||
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Report" file="LAN_IDE_CP.par" label="Place and Route Report" >
|
||||
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
|
||||
<toc-item title="Device Utilization" target="Device Utilization Summary:" />
|
||||
<toc-item title="Router Information" target="Starting Router" />
|
||||
<toc-item title="Partition Status" target="Partition Implementation Status" />
|
||||
<toc-item title="Clock Report" target="Generating Clock Report" />
|
||||
<toc-item title="Timing Results" target="Timing Score:" />
|
||||
<toc-item title="Final Summary" target="Peak Memory Usage:" />
|
||||
</view>
|
||||
<view inputState="Routed" program="trce" contextTags="FPGA_ONLY" hidden="true" type="Report" file="LAN_IDE_CP.twr" label="Post-PAR Static Timing Report" >
|
||||
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
|
||||
<toc-item title="Timing Report Description" target="Device,package,speed:" />
|
||||
<toc-item title="Informational Messages" target="INFO:" />
|
||||
<toc-item title="Warning Messages" target="WARNING:" />
|
||||
<toc-item title="Timing Constraints" target="Timing constraint:" />
|
||||
<toc-item title="Derived Constraint Report" target="Derived Constraint Report" />
|
||||
<toc-item title="Data Sheet Report" target="Data Sheet report:" />
|
||||
<toc-item title="Timing Summary" target="Timing summary:" />
|
||||
<toc-item title="Trace Settings" target="Trace Settings:" />
|
||||
</view>
|
||||
<view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="false" type="Report" file="LAN_IDE_CP.rpt" label="CPLD Fitter Report (Text)" >
|
||||
<toc-item title="Top of Report" target="cpldfit:" searchDir="Forward" />
|
||||
<toc-item title="Resources Summary" target="** Mapped Resource Summary **" />
|
||||
<toc-item title="Pin Resources" target="** Pin Resources **" />
|
||||
<toc-item title="Global Resources" target="** Global Control Resources **" />
|
||||
</view>
|
||||
<view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="false" type="Report" file="LAN_IDE_CP.tim" label="CPLD Timing Report (Text)" >
|
||||
<toc-item title="Top of Report" target="Performance Summary Report" searchDir="Forward" />
|
||||
<toc-item title="Performance Summary" target="Performance Summary:" />
|
||||
</view>
|
||||
<view inputState="Routed" program="xpwr" contextTags="EDK_OFF" type="Report" file="LAN_IDE_CP.pwr" label="Power Report" >
|
||||
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
|
||||
<toc-item title="Power summary" target="Power summary" />
|
||||
<toc-item title="Thermal summary" target="Thermal summary" />
|
||||
</view>
|
||||
<view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="true" type="Report" file="LAN_IDE_CP.bgn" label="Bitgen Report" >
|
||||
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
|
||||
<toc-item title="Bitgen Options" target="Summary of Bitgen Options:" />
|
||||
<toc-item title="Final Summary" target="DRC detected" />
|
||||
</view>
|
||||
</viewgroup>
|
||||
<viewgroup label="Secondary Reports" >
|
||||
<view inputState="PreSynthesized" program="isim" hidden="if_missing" type="Secondary_Report" file="isim.log" label="ISIM Simulator Log" />
|
||||
<view inputState="Synthesized" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/synthesis/LAN_IDE_CP_synthesis.nlf" label="Post-Synthesis Simulation Model Report" >
|
||||
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
|
||||
</view>
|
||||
<view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/translate/LAN_IDE_CP_translate.nlf" label="Post-Translate Simulation Model Report" >
|
||||
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
|
||||
</view>
|
||||
<view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="LAN_IDE_CP_tran_fecn.nlf" label="Post-Translate Formality Netlist Report" />
|
||||
<view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="LAN_IDE_CP_map.map" label="Map Log File" >
|
||||
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
|
||||
<toc-item title="Design Information" target="Design Information" />
|
||||
<toc-item title="Design Summary" target="Design Summary" />
|
||||
</view>
|
||||
<view inputState="Routed" program="smartxplorer" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="smartxplorer_results/smartxplorer.txt" label="SmartXplorer Report" />
|
||||
<view inputState="Mapped" program="trce" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="LAN_IDE_CP_preroute.twr" label="Post-Map Static Timing Report" >
|
||||
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
|
||||
<toc-item title="Timing Report Description" target="Device,package,speed:" />
|
||||
<toc-item title="Informational Messages" target="INFO:" />
|
||||
<toc-item title="Warning Messages" target="WARNING:" />
|
||||
<toc-item title="Timing Constraints" target="Timing constraint:" />
|
||||
<toc-item title="Derived Constraint Report" target="Derived Constraint Report" />
|
||||
<toc-item title="Data Sheet Report" target="Data Sheet report:" />
|
||||
<toc-item title="Timing Summary" target="Timing summary:" />
|
||||
<toc-item title="Trace Settings" target="Trace Settings:" />
|
||||
</view>
|
||||
<view inputState="Mapped" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/map/LAN_IDE_CP_map.nlf" label="Post-Map Simulation Model Report" />
|
||||
<view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="LAN_IDE_CP_map.psr" label="Physical Synthesis Report" >
|
||||
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
|
||||
</view>
|
||||
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Pad_Report" file="LAN_IDE_CP_pad.txt" label="Pad Report" >
|
||||
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
|
||||
</view>
|
||||
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="LAN_IDE_CP.unroutes" label="Unroutes Report" >
|
||||
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
|
||||
</view>
|
||||
<view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="LAN_IDE_CP_preroute.tsi" label="Post-Map Constraints Interaction Report" >
|
||||
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
|
||||
</view>
|
||||
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="LAN_IDE_CP.grf" label="Guide Results Report" />
|
||||
<view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="LAN_IDE_CP.dly" label="Asynchronous Delay Report" />
|
||||
<view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="LAN_IDE_CP.clk_rgn" label="Clock Region Report" />
|
||||
<view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="LAN_IDE_CP.tsi" label="Post-Place and Route Constraints Interaction Report" >
|
||||
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
|
||||
</view>
|
||||
<view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="LAN_IDE_CP_par_fecn.nlf" label="Post-Place and Route Formality Netlist Report" />
|
||||
<view inputState="Routed" program="netgen" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="netgen/par/LAN_IDE_CP_timesim.nlf" label="Post-Place and Route Simulation Model Report" />
|
||||
<view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="LAN_IDE_CP_sta.nlf" label="Primetime Netlist Report" >
|
||||
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
|
||||
</view>
|
||||
<view inputState="Routed" program="ibiswriter" hidden="if_missing" type="Secondary_Report" file="LAN_IDE_CP.ibs" label="IBIS Model" >
|
||||
<toc-item title="Top of Report" target="IBIS Models for" searchDir="Forward" />
|
||||
<toc-item title="Component" target="Component " />
|
||||
</view>
|
||||
<view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="LAN_IDE_CP.lck" label="Back-annotate Pin Report" >
|
||||
<toc-item title="Top of Report" target="pin2ucf Report File" searchDir="Forward" />
|
||||
<toc-item title="Constraint Conflicts Information" target="Constraint Conflicts Information" />
|
||||
</view>
|
||||
<view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="LAN_IDE_CP.lpc" label="Locked Pin Constraints" >
|
||||
<toc-item title="Top of Report" target="top.lpc" searchDir="Forward" />
|
||||
<toc-item title="Newly Added Constraints" target="The following constraints were newly added" />
|
||||
</view>
|
||||
<view inputState="Translated" program="netgen" contextTags="CPLD_ONLY,EDK_OFF" hidden="false" type="Secondary_Report" file="netgen/fit/LAN_IDE_CP_timesim.nlf" label="Post-Fit Simulation Model Report" />
|
||||
<view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="true" type="HTML" file="usage_statistics_webtalk.html" label="WebTalk Report" />
|
||||
<view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="webtalk.log" label="WebTalk Log File" />
|
||||
</viewgroup>
|
||||
</body>
|
||||
</report-views>
|
||||
@@ -0,0 +1,75 @@
|
||||
<?xml version='1.0' encoding='utf-8'?>
|
||||
<!--This is an ISE project configuration file.-->
|
||||
<!--It holds project specific layout data for the projectmgr plugin.-->
|
||||
<!--Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.-->
|
||||
<Project version="2" owner="projectmgr" name="LAN_IDEz2v2" >
|
||||
<!--This is an ISE project configuration file.-->
|
||||
<ItemView engineview="SynthesisOnly" guiview="Source" compilemode="AutoCompile" >
|
||||
<ClosedNodes>
|
||||
<ClosedNodesVersion>2</ClosedNodesVersion>
|
||||
</ClosedNodes>
|
||||
<SelectedItems>
|
||||
<SelectedItem>pinlist.ucf (C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE_V2/pinlist.ucf)</SelectedItem>
|
||||
</SelectedItems>
|
||||
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
|
||||
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
|
||||
<ViewHeaderState orientation="horizontal" >000000ff0000000000000001000000010000000000000000000000000000000002020000000100000001000000640000015a000000020000000000000000000000000200000064ffffffff0000008100000003000000020000015a0000000100000003000000000000000100000003</ViewHeaderState>
|
||||
<UserChangedColumnWidths orientation="horizontal" >true</UserChangedColumnWidths>
|
||||
<CurrentItem>pinlist.ucf (C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE_V2/pinlist.ucf)</CurrentItem>
|
||||
</ItemView>
|
||||
<ItemView engineview="SynthesisOnly" sourcetype="DESUT_VHDL_ARCHITECTURE" guiview="Process" >
|
||||
<ClosedNodes>
|
||||
<ClosedNodesVersion>1</ClosedNodesVersion>
|
||||
<ClosedNode>Design Utilities</ClosedNode>
|
||||
<ClosedNode>Implement Design</ClosedNode>
|
||||
<ClosedNode>User Constraints</ClosedNode>
|
||||
</ClosedNodes>
|
||||
<SelectedItems>
|
||||
<SelectedItem/>
|
||||
</SelectedItems>
|
||||
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
|
||||
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
|
||||
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000000f8000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f80000000100000000</ViewHeaderState>
|
||||
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
|
||||
<CurrentItem/>
|
||||
</ItemView>
|
||||
<ItemView guiview="File" >
|
||||
<ClosedNodes>
|
||||
<ClosedNodesVersion>1</ClosedNodesVersion>
|
||||
</ClosedNodes>
|
||||
<SelectedItems/>
|
||||
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
|
||||
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
|
||||
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000000000000000100000000000000000000000000000000000003a3000000040101000100000000000000000000000064ffffffff0000008100000000000000040000008b00000001000000000000009d0000000100000000000000660000000100000000000002150000000100000000</ViewHeaderState>
|
||||
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
|
||||
<CurrentItem>LAN_IDE_CP-Z2v2.vhd</CurrentItem>
|
||||
</ItemView>
|
||||
<ItemView guiview="Library" >
|
||||
<ClosedNodes>
|
||||
<ClosedNodesVersion>1</ClosedNodesVersion>
|
||||
<ClosedNode>work</ClosedNode>
|
||||
</ClosedNodes>
|
||||
<SelectedItems/>
|
||||
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
|
||||
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
|
||||
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000000000000010000000000000000000000000000000000000109000000010001000100000000000000000000000064ffffffff000000810000000000000001000001090000000100000000</ViewHeaderState>
|
||||
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
|
||||
<CurrentItem>work</CurrentItem>
|
||||
</ItemView>
|
||||
<SourceProcessView>000000ff00000000000000020000011b0000011b01000000050100000002</SourceProcessView>
|
||||
<CurrentView>Implementation</CurrentView>
|
||||
<ItemView engineview="SynthesisOnly" sourcetype="DESUT_UCF" guiview="Process" >
|
||||
<ClosedNodes>
|
||||
<ClosedNodesVersion>1</ClosedNodesVersion>
|
||||
<ClosedNode>User Constraints</ClosedNode>
|
||||
</ClosedNodes>
|
||||
<SelectedItems>
|
||||
<SelectedItem></SelectedItem>
|
||||
</SelectedItems>
|
||||
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
|
||||
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
|
||||
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000000f8000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f80000000100000000</ViewHeaderState>
|
||||
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
|
||||
<CurrentItem></CurrentItem>
|
||||
</ItemView>
|
||||
</Project>
|
||||
@@ -0,0 +1,123 @@
|
||||
#PACE: Start of Constraints generated by PACE
|
||||
#PACE: Start of PACE I/O Pin Assignments
|
||||
NET "A<10>" LOC = "P59" ;
|
||||
NET "A<11>" LOC = "P60" ;
|
||||
NET "A<12>" LOC = "P61" ;
|
||||
NET "A<13>" LOC = "P64" ;
|
||||
NET "A<14>" LOC = "P66" ;
|
||||
NET "A<15>" LOC = "P74" ;
|
||||
NET "A<16>" LOC = "P97" ;
|
||||
NET "A<17>" LOC = "P95" ;
|
||||
NET "A<18>" LOC = "P94" ;
|
||||
NET "A<19>" LOC = "P92" ;
|
||||
NET "A<1>" LOC = "P57" ;
|
||||
NET "A<20>" LOC = "P91" ;
|
||||
NET "A<21>" LOC = "P88" ;
|
||||
NET "A<22>" LOC = "P87" ;
|
||||
NET "A<23>" LOC = "P86" ;
|
||||
NET "A<2>" LOC = "P54" ;
|
||||
NET "A<3>" LOC = "P52" ;
|
||||
NET "A<4>" LOC = "P50" ;
|
||||
NET "A<5>" LOC = "P49" ;
|
||||
NET "A<6>" LOC = "P51" ;
|
||||
NET "A<7>" LOC = "P53" ;
|
||||
NET "A<8>" LOC = "P56" ;
|
||||
NET "A<9>" LOC = "P58" ;
|
||||
NET "A_LAN<0>" LOC = "P4" ;
|
||||
NET "A_LAN<10>" LOC = "P138" ;
|
||||
NET "A_LAN<11>" LOC = "P139" ;
|
||||
NET "A_LAN<12>" LOC = "P136" ;
|
||||
NET "A_LAN<13>" LOC = "P137" ;
|
||||
NET "A_LAN<1>" LOC = "P3" ;
|
||||
NET "A_LAN<2>" LOC = "P6" ;
|
||||
NET "A_LAN<3>" LOC = "P5" ;
|
||||
NET "A_LAN<4>" LOC = "P9" ;
|
||||
NET "A_LAN<5>" LOC = "P7" ;
|
||||
NET "A_LAN<6>" LOC = "P11" ;
|
||||
NET "A_LAN<7>" LOC = "P10" ;
|
||||
NET "A_LAN<8>" LOC = "P140" ;
|
||||
NET "A_LAN<9>" LOC = "P142" ;
|
||||
NET "AS" LOC = "P80" ;
|
||||
NET "AUTOBOOT_OFF" LOC = "P75" ;
|
||||
NET "BERR" LOC = "P98" ;
|
||||
NET "C1" LOC = "P103" ;
|
||||
NET "C3" LOC = "P102" ;
|
||||
NET "CFIN" LOC = "P104" ;
|
||||
NET "CFOUT" LOC = "P105" ;
|
||||
NET "CLK_EXT" LOC = "P30" ;
|
||||
NET "CP_CS" LOC = "P34" ;
|
||||
NET "CP_IRQ" LOC = "P31" ;
|
||||
NET "CP_RD" LOC = "P71" ;
|
||||
NET "CP_WE" LOC = "P70" ;
|
||||
NET "D<0>" LOC = "P2" ;
|
||||
NET "D<10>" LOC = "P41" ;
|
||||
NET "D<11>" LOC = "P43" ;
|
||||
NET "D<12>" LOC = "P44" ;
|
||||
NET "D<13>" LOC = "P45" ;
|
||||
NET "D<14>" LOC = "P46" ;
|
||||
NET "D<15>" LOC = "P48" ;
|
||||
NET "D<1>" LOC = "P17" ;
|
||||
NET "D<2>" LOC = "P39" ;
|
||||
NET "D<3>" LOC = "P15" ;
|
||||
NET "D<4>" LOC = "P21" ;
|
||||
NET "D<5>" LOC = "P20" ;
|
||||
NET "D<6>" LOC = "P14" ;
|
||||
NET "D<7>" LOC = "P16" ;
|
||||
NET "D<8>" LOC = "P19" ;
|
||||
NET "D<9>" LOC = "P40" ;
|
||||
NET "DQ<0>" LOC = "P118" ;
|
||||
NET "DQ<10>" LOC = "P129" ;
|
||||
NET "DQ<11>" LOC = "P115" ;
|
||||
NET "DQ<12>" LOC = "P130" ;
|
||||
NET "DQ<13>" LOC = "P113" ;
|
||||
NET "DQ<14>" LOC = "P131" ;
|
||||
NET "DQ<15>" LOC = "P112" ;
|
||||
NET "DQ<1>" LOC = "P117" ;
|
||||
NET "DQ<2>" LOC = "P120" ;
|
||||
//NET "DQ<2>" LOC = "P68" ; //fix for broken Xilinx
|
||||
NET "DQ<3>" LOC = "P119" ;
|
||||
NET "DQ<4>" LOC = "P124" ;
|
||||
NET "DQ<5>" LOC = "P121" ;
|
||||
//NET "DQ<5>" LOC = "P38" ;//fix for broken Xilinx
|
||||
NET "DQ<6>" LOC = "P126" ;
|
||||
NET "DQ<7>" LOC = "P125" ;
|
||||
NET "DQ<8>" LOC = "P128" ;
|
||||
NET "DQ<9>" LOC = "P116" ;
|
||||
NET "DS0" LOC = "P93" ;
|
||||
NET "DS1" LOC = "P78" ;
|
||||
NET "DTACK" LOC = "P85" ;
|
||||
NET "FCS" LOC = "P77" ;
|
||||
NET "IDE_A<0>" LOC = "P24" ;
|
||||
NET "IDE_A<1>" LOC = "P26" ;
|
||||
NET "IDE_A<2>" LOC = "P25" ;
|
||||
NET "IDE_CS<0>" LOC = "P22" ;
|
||||
NET "IDE_CS<1>" LOC = "P23" ;
|
||||
NET "IDE_R" LOC = "P27" ;
|
||||
NET "IDE_W" LOC = "P28" ;
|
||||
NET "IDE_WAIT" LOC = "P33" ;
|
||||
NET "INT_OUT" LOC = "P32" ;
|
||||
NET "LAN_CFG<1>" LOC = "P12" ;
|
||||
NET "LAN_CFG<2>" LOC = "P135" ;
|
||||
NET "LAN_CFG<3>" LOC = "P13" ;
|
||||
NET "LAN_CFG<4>" LOC = "P110" ;
|
||||
NET "LAN_CS" LOC = "P133" ;
|
||||
NET "LAN_WRL" LOC = "P76" ;
|
||||
NET "LAN_INT" LOC = "P111" ;
|
||||
NET "LAN_RD" LOC = "P134" ;
|
||||
NET "LAN_WRH" LOC = "P132" ;
|
||||
NET "LDS" LOC = "P82" ;
|
||||
NET "MTACK" LOC = "P96" ;
|
||||
NET "MTCR" LOC = "P101" ;
|
||||
NET "OVR" LOC = "P100" ;
|
||||
NET "OWN" LOC = "P107" ;
|
||||
NET "RESET" LOC = "P143" ;
|
||||
NET "ROM_B<0>" LOC = "P68" ;//comment if fix for broken Xilinx!
|
||||
NET "ROM_B<1>" LOC = "P69" ;
|
||||
NET "ROM_OE" LOC = "P35" ;
|
||||
NET "RW" LOC = "P83" ;
|
||||
NET "SLAVE" LOC = "P106" ;
|
||||
NET "UDS" LOC = "P81" ;
|
||||
NET "Z3" LOC = "P79" ;
|
||||
#Created by Constraints Editor (xc95288xl-tq144-10) - 2017/01/26
|
||||
NET "CLK_EXT" TNM_NET = CLK_EXT;
|
||||
TIMESPEC TS_CLK_EXT = PERIOD "CLK_EXT" 25 MHz HIGH 50%;
|
||||
@@ -1,39 +0,0 @@
|
||||
Stückliste exportiert aus C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/PCB/ZORRO-LAN-IDE-CP-V2E.sch am 06.01.2019 21:21:09
|
||||
|
||||
Qty Value Device Package Parts Description
|
||||
1 4R-NCAY16 CAY16 RN1 Array Chip Resistor
|
||||
6 JP1E JP1 AUTOBOOT_ON, IDE_ACT, IDE_OFF, JP1, LEDA, LEDB JUMPER
|
||||
1 ML10L ML10L SV2 HARTING
|
||||
1 ML14 ML14 SV1 HARTING
|
||||
1 ML40 ML40 IDE HARTING
|
||||
2 SJ SJ SJ1, SJ2 SMD solder JUMPER
|
||||
1 10 R-EU_R0603 R0603 R19 RESISTOR, European symbol
|
||||
12 100n C-EUC0603K C0603K C9, C10, C11, C12, C14, C15, C16, C17, C22, C29, C30, C32 CAPACITOR, European symbol
|
||||
8 100nF C-EUC0805K C0805K C1, C3, C4, C6, C7, C8, C13, C18 CAPACITOR, European symbol
|
||||
2 10n C-EUC0805K C0805K C28, C33 CAPACITOR, European symbol
|
||||
2 10u C-EUC0805K C0805K C2, C23 CAPACITOR, European symbol
|
||||
1 10u C-EUC1206K C1206K C19 CAPACITOR, European symbol
|
||||
2 10u C-EUC1210K C1210K C20, C21 CAPACITOR, European symbol
|
||||
1 12k R-EU_R0603 R0603 R13 RESISTOR, European symbol
|
||||
2 180 R-EU_R0603 R0603 R6, R14 RESISTOR, European symbol
|
||||
2 1K R-EU_R0805 R0805 R10, R11 RESISTOR, European symbol
|
||||
1 25MHz CRYSTALHC18U-V HC18U-V Q1 CRYSTAL
|
||||
1 25MHz CRYSTALHC49UP HC49UP Q2 CRYSTAL
|
||||
2 27p C-EUC0805K C0805K C24, C25 CAPACITOR, European symbol
|
||||
1 3.3k R-EU_R0603 R0603 R12 RESISTOR, European symbol
|
||||
1 330 R-EU_R0603 R0603 R7 RESISTOR, European symbol
|
||||
1 390 R-EU_R0603 R0603 R4 RESISTOR, European symbol
|
||||
6 4.7k R-EU_R0603 R0603 R1, R2, R3, R5, R8, R9 RESISTOR, European symbol
|
||||
1 47u C-EUC1210K C1210K C31 CAPACITOR, European symbol
|
||||
1 47uF C-EUC1206K C1206K C5 CAPACITOR, European symbol
|
||||
4 49.9 R-EU_R0603 R0603 R15, R16, R17, R18 RESISTOR, European symbol
|
||||
1 500mA R-EU_R2512 R2512 F1 RESISTOR, European symbol
|
||||
2 6.8n C-EUC0805K C0805K C26, C27 CAPACITOR, European symbol
|
||||
3 74HCT245PW 74HCT245PW TSSOP20 IC3, IC4, IC5 Octal BUS TRANSCEIVER, 3-state
|
||||
1 A1200-CLOCKPORT A1200-CLOCKPORT CP-2X11-2.00 CN2
|
||||
1 AM29F010S AM29F010S PLCC-SR32 IC8 1-Megabit FLASH MEMORY
|
||||
1 ENC624J600 ENC624J600 SQFP-S-10X10-64 IC1
|
||||
1 LD117ADT33TR LD117ADT33TR DPACK IC7 Low drop fixed and adjustable positive voltage regulators 1 A
|
||||
1 SI-50170 SI-50170 SI-50170 X1 Ethernet Connector MagJack (R)
|
||||
1 XC95288XL-TQ144 XC95288XL-TQ144 TQFP144 IC2
|
||||
1 ZORROII_EDGE_ROUND_CONTACTS ZORROII_EDGE_ROUND_CONTACTS LKONT_50_R CN1
|
||||
@@ -6,7 +6,7 @@
|
||||
<setting alwaysvectorfont="yes"/>
|
||||
<setting verticaltext="up"/>
|
||||
</settings>
|
||||
<grid distance="6.25" unitdist="mil" unit="mil" style="lines" multiple="1" display="yes" altdistance="0.025" altunitdist="inch" altunit="mil"/>
|
||||
<grid distance="0.000123031496" unitdist="mil" unit="mil" style="lines" multiple="1" display="yes" altdistance="0.025" altunitdist="inch" altunit="mil"/>
|
||||
<layers>
|
||||
<layer number="1" name="Top" color="4" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="2" name="Route2-GND" color="1" fill="3" visible="yes" active="yes"/>
|
||||
@@ -4397,12 +4397,7 @@ Sollten andere Lagen belegt und relevant sein, so teilen Sie uns dies bitte expl
|
||||
<wire x1="58.52856875" y1="31.7401875" x2="58.541765625" y2="31.753384375" width="0.254" layer="16"/>
|
||||
<via x="72.30471875" y="31.7644" extent="1-16" drill="0.3000125"/>
|
||||
<via x="87.800146875" y="21.83661875" extent="1-16" drill="0.3000125"/>
|
||||
<wire x1="96.996059375" y1="21.83661875" x2="97.832275" y2="21.000403125" width="0.254" layer="1"/>
|
||||
<wire x1="97.832275" y1="21.000403125" x2="97.832275" y2="10.414446875" width="0.254" layer="1"/>
|
||||
<wire x1="97.832275" y1="10.414446875" x2="96.8822625" y2="9.464434375" width="0.254" layer="1"/>
|
||||
<wire x1="96.8822625" y1="9.464434375" x2="96.8822625" y2="5.0987375" width="0.254" layer="1"/>
|
||||
<wire x1="96.8822625" y1="5.0987375" x2="96.901" y2="5.08" width="0.254" layer="1"/>
|
||||
<wire x1="87.800146875" y1="21.83661875" x2="96.996059375" y2="21.83661875" width="0.254" layer="1"/>
|
||||
<wire x1="58.541765625" y1="31.753384375" x2="72.293703125" y2="31.753384375" width="0.254" layer="1"/>
|
||||
<wire x1="72.293703125" y1="31.753384375" x2="72.30471875" y2="31.7644" width="0.254" layer="1"/>
|
||||
<wire x1="87.805425" y1="21.841896875" x2="87.800146875" y2="21.83661875" width="0.254" layer="16"/>
|
||||
@@ -4433,6 +4428,12 @@ Sollten andere Lagen belegt und relevant sein, so teilen Sie uns dies bitte expl
|
||||
<wire x1="72.30471875" y1="31.7644" x2="73.61385" y2="31.7644" width="0.254" layer="16"/>
|
||||
<wire x1="73.61385" y1="31.7644" x2="77.358875" y2="28.019375" width="0.254" layer="16"/>
|
||||
<wire x1="77.358875" y1="27.94" x2="77.358875" y2="28.019375" width="0.254" layer="16"/>
|
||||
<wire x1="96.8822625" y1="5.0987375" x2="96.8822625" y2="10.10678125" width="0.254" layer="1"/>
|
||||
<wire x1="96.8822625" y1="10.10678125" x2="95.265859375" y2="11.723184375" width="0.254" layer="1"/>
|
||||
<wire x1="95.265859375" y1="11.723184375" x2="95.265859375" y2="18.5014125" width="0.254" layer="1"/>
|
||||
<wire x1="95.265859375" y1="18.5014125" x2="91.9328375" y2="21.834434375" width="0.254" layer="1"/>
|
||||
<wire x1="91.9328375" y1="21.834434375" x2="87.80233125" y2="21.834434375" width="0.254" layer="1"/>
|
||||
<wire x1="87.80233125" y1="21.834434375" x2="87.800146875" y2="21.83661875" width="0.254" layer="1"/>
|
||||
</signal>
|
||||
<signal name="A4">
|
||||
<contactref element="IC8" pad="9"/>
|
||||
@@ -4457,8 +4458,6 @@ Sollten andere Lagen belegt und relevant sein, so teilen Sie uns dies bitte expl
|
||||
<wire x1="68.316034375" y1="33.63890625" x2="68.362846875" y2="33.68571875" width="0.254" layer="1"/>
|
||||
<via x="68.362846875" y="33.68571875" extent="1-16" drill="0.3000125"/>
|
||||
<wire x1="68.362846875" y1="33.68571875" x2="68.362846875" y2="33.71484375" width="0.254" layer="16"/>
|
||||
<wire x1="68.362846875" y1="33.71484375" x2="69.17153125" y2="34.523528125" width="0.254" layer="16"/>
|
||||
<wire x1="69.17153125" y1="34.523528125" x2="94.914915625" y2="34.523528125" width="0.254" layer="16"/>
|
||||
<via x="99.46655" y="20.9096125" extent="1-16" drill="0.3000125"/>
|
||||
<wire x1="99.048815625" y1="5.472184375" x2="99.441" y2="5.08" width="0.254" layer="1"/>
|
||||
<wire x1="99.46655" y1="20.9096125" x2="99.46655" y2="5.88991875" width="0.254" layer="1"/>
|
||||
@@ -4484,9 +4483,16 @@ Sollten andere Lagen belegt und relevant sein, so teilen Sie uns dies bitte expl
|
||||
<wire x1="24.01053125" y1="39.178621875" x2="23.995746875" y2="39.19340625" width="0.254" layer="16"/>
|
||||
<wire x1="23.995746875" y1="39.19340625" x2="23.995746875" y2="41.461384375" width="0.254" layer="16"/>
|
||||
<wire x1="99.46655" y1="20.9096125" x2="98.962034375" y2="20.9096125" width="0.254" layer="16"/>
|
||||
<wire x1="98.962034375" y1="20.9096125" x2="97.137953125" y2="22.73369375" width="0.254" layer="16"/>
|
||||
<wire x1="97.137953125" y1="22.73369375" x2="97.137953125" y2="32.300490625" width="0.254" layer="16"/>
|
||||
<wire x1="97.137953125" y1="32.300490625" x2="94.914915625" y2="34.523528125" width="0.254" layer="16"/>
|
||||
<wire x1="98.962034375" y1="20.9096125" x2="97.13255" y2="22.739096875" width="0.254" layer="16"/>
|
||||
<wire x1="68.362846875" y1="33.71484375" x2="68.687853125" y2="33.71484375" width="0.254" layer="16"/>
|
||||
<wire x1="68.687853125" y1="33.71484375" x2="69.05666875" y2="34.083659375" width="0.254" layer="16"/>
|
||||
<wire x1="69.05666875" y1="34.083659375" x2="69.6893375" y2="34.083659375" width="0.254" layer="16"/>
|
||||
<wire x1="69.6893375" y1="34.083659375" x2="70.263284375" y2="33.5097125" width="0.254" layer="16"/>
|
||||
<wire x1="70.263284375" y1="33.5097125" x2="94.674875" y2="33.5097125" width="0.254" layer="16"/>
|
||||
<wire x1="97.13255" y1="22.739096875" x2="97.13255" y2="22.76660625" width="0.254" layer="16"/>
|
||||
<wire x1="97.13255" y1="22.76660625" x2="97.00011875" y2="22.8990375" width="0.254" layer="16"/>
|
||||
<wire x1="97.00011875" y1="22.8990375" x2="97.00011875" y2="31.18446875" width="0.254" layer="16"/>
|
||||
<wire x1="97.00011875" y1="31.18446875" x2="94.674875" y2="33.5097125" width="0.254" layer="16"/>
|
||||
</signal>
|
||||
<signal name="A5">
|
||||
<contactref element="IC8" pad="8"/>
|
||||
@@ -4566,9 +4572,6 @@ Sollten andere Lagen belegt und relevant sein, so teilen Sie uns dies bitte expl
|
||||
<wire x1="68.753440625" y1="32.6640375" x2="69.40579375" y2="33.316390625" width="0.254" layer="1"/>
|
||||
<via x="69.40579375" y="33.316390625" extent="1-16" drill="0.3000125"/>
|
||||
<wire x1="69.40579375" y1="33.316390625" x2="69.40579375" y2="33.430275" width="0.254" layer="16"/>
|
||||
<wire x1="69.40579375" y1="33.430275" x2="69.9008875" y2="33.92536875" width="0.254" layer="16"/>
|
||||
<wire x1="69.9008875" y1="33.92536875" x2="79.369521875" y2="33.92536875" width="0.254" layer="16"/>
|
||||
<wire x1="79.369521875" y1="33.92536875" x2="79.45308125" y2="34.008928125" width="0.254" layer="16"/>
|
||||
<wire x1="99.439925" y1="19.570971875" x2="99.439925" y2="5.081075" width="0.254" layer="16"/>
|
||||
<wire x1="99.439925" y1="5.081075" x2="99.441" y2="5.08" width="0.254" layer="16"/>
|
||||
<wire x1="33.9691875" y1="35.5460375" x2="33.9691875" y2="35.5331" width="0.254" layer="1"/>
|
||||
@@ -4580,10 +4583,11 @@ Sollten andere Lagen belegt und relevant sein, so teilen Sie uns dies bitte expl
|
||||
<wire x1="29.30534375" y1="34.277465625" x2="24.37821875" y2="34.277465625" width="0.254" layer="1"/>
|
||||
<wire x1="24.37821875" y1="34.277465625" x2="19.80338125" y2="38.852303125" width="0.254" layer="1"/>
|
||||
<wire x1="19.80338125" y1="38.852303125" x2="18.902765625" y2="38.852303125" width="0.254" layer="1"/>
|
||||
<wire x1="79.45308125" y1="34.008928125" x2="94.224425" y2="34.008928125" width="0.254" layer="16"/>
|
||||
<wire x1="94.224425" y1="34.008928125" x2="96.426759375" y2="31.80659375" width="0.254" layer="16"/>
|
||||
<wire x1="96.426759375" y1="31.80659375" x2="96.426759375" y2="22.5841375" width="0.254" layer="16"/>
|
||||
<wire x1="96.426759375" y1="22.5841375" x2="99.439925" y2="19.570971875" width="0.254" layer="16"/>
|
||||
<wire x1="96.426759375" y1="22.5841375" x2="96.426759375" y2="30.890740625" width="0.254" layer="16"/>
|
||||
<wire x1="96.426759375" y1="30.890740625" x2="94.45625" y2="32.86125" width="0.254" layer="16"/>
|
||||
<wire x1="94.45625" y1="32.86125" x2="69.860934375" y2="32.86125" width="0.254" layer="16"/>
|
||||
<wire x1="69.860934375" y1="32.86125" x2="69.40579375" y2="33.316390625" width="0.254" layer="16"/>
|
||||
</signal>
|
||||
<signal name="A7">
|
||||
<contactref element="IC8" pad="6"/>
|
||||
@@ -6329,11 +6333,14 @@ Sollten andere Lagen belegt und relevant sein, so teilen Sie uns dies bitte expl
|
||||
<wire x1="22.60180625" y1="54.736178125" x2="22.62791875" y2="54.710065625" width="0.254" layer="16"/>
|
||||
<wire x1="22.62791875" y1="54.710065625" x2="22.62791875" y2="50.52945" width="0.254" layer="16"/>
|
||||
<wire x1="22.62791875" y1="50.52945" x2="22.60180625" y2="50.5033375" width="0.254" layer="16"/>
|
||||
<wire x1="66.3313875" y1="50.6549125" x2="66.3313875" y2="49.758715625" width="0.254" layer="16"/>
|
||||
<wire x1="66.3313875" y1="49.758715625" x2="66.672640625" y2="49.4174625" width="0.254" layer="16"/>
|
||||
<wire x1="66.672640625" y1="49.4174625" x2="66.672640625" y2="36.457596875" width="0.254" layer="16"/>
|
||||
<wire x1="66.672640625" y1="36.457596875" x2="67.9096875" y2="35.22055" width="0.254" layer="16"/>
|
||||
<wire x1="67.9096875" y1="35.22055" x2="84.193825" y2="35.22055" width="0.254" layer="16"/>
|
||||
<wire x1="66.3313875" y1="50.6549125" x2="66.3313875" y2="49.71861875" width="0.254" layer="16"/>
|
||||
<wire x1="84.193825" y1="35.22055" x2="69.55445" y2="35.22055" width="0.254" layer="16"/>
|
||||
<wire x1="69.55445" y1="35.22055" x2="66.83375" y2="37.94125" width="0.254" layer="16"/>
|
||||
<wire x1="66.3313875" y1="49.71861875" x2="66.67710625" y2="49.3729" width="0.254" layer="16"/>
|
||||
<wire x1="66.67710625" y1="49.3729" x2="66.67710625" y2="48.71655625" width="0.254" layer="16"/>
|
||||
<wire x1="66.67710625" y1="48.71655625" x2="66.842659375" y2="48.551003125" width="0.254" layer="16"/>
|
||||
<wire x1="66.842659375" y1="48.551003125" x2="66.842659375" y2="37.950159375" width="0.254" layer="16"/>
|
||||
<wire x1="66.842659375" y1="37.950159375" x2="66.83375" y2="37.94125" width="0.254" layer="16"/>
|
||||
</signal>
|
||||
<signal name="DQ6">
|
||||
<contactref element="IC2" pad="126"/>
|
||||
@@ -6354,10 +6361,7 @@ Sollten andere Lagen belegt und relevant sein, so teilen Sie uns dies bitte expl
|
||||
<wire x1="82.686971875" y1="38.3906875" x2="68.342653125" y2="38.3906875" width="0.254" layer="16"/>
|
||||
<wire x1="68.342653125" y1="38.3906875" x2="68.310159375" y2="38.42318125" width="0.254" layer="16"/>
|
||||
<via x="68.310159375" y="38.42318125" extent="1-16" drill="0.3000125"/>
|
||||
<wire x1="68.310159375" y1="38.42318125" x2="65.494121875" y2="38.42318125" width="0.254" layer="1"/>
|
||||
<wire x1="65.494121875" y1="38.42318125" x2="65.39643125" y2="38.520871875" width="0.254" layer="1"/>
|
||||
<via x="65.39643125" y="38.520871875" extent="1-16" drill="0.3000125"/>
|
||||
<wire x1="65.39643125" y1="38.520871875" x2="65.39643125" y2="51.505453125" width="0.254" layer="16"/>
|
||||
<via x="66.03143125" y="38.362121875" extent="1-16" drill="0.3000125"/>
|
||||
<wire x1="65.39643125" y1="51.505453125" x2="65.38675" y2="51.515134375" width="0.254" layer="16"/>
|
||||
<wire x1="87.09" y1="77.2" x2="87.09" y2="77.18808125" width="0.254" layer="1"/>
|
||||
<wire x1="87.09" y1="77.18808125" x2="86.147153125" y2="76.245234375" width="0.254" layer="1"/>
|
||||
@@ -6400,6 +6404,12 @@ Sollten andere Lagen belegt und relevant sein, so teilen Sie uns dies bitte expl
|
||||
<wire x1="46.476465625" y1="49.3074125" x2="45.8192125" y2="49.3074125" width="0.254" layer="16"/>
|
||||
<wire x1="45.8192125" y1="49.3074125" x2="45.622784375" y2="49.110984375" width="0.254" layer="16"/>
|
||||
<wire x1="45.622784375" y1="49.110984375" x2="24.45115625" y2="49.110984375" width="0.254" layer="16"/>
|
||||
<wire x1="68.310159375" y1="38.42318125" x2="66.092490625" y2="38.42318125" width="0.254" layer="1"/>
|
||||
<wire x1="66.092490625" y1="38.42318125" x2="66.03143125" y2="38.362121875" width="0.254" layer="1"/>
|
||||
<wire x1="65.39643125" y1="51.505453125" x2="65.39643125" y2="49.85606875" width="0.254" layer="16"/>
|
||||
<wire x1="65.39643125" y1="49.85606875" x2="66.04" y2="49.2125" width="0.254" layer="16"/>
|
||||
<wire x1="66.04" y1="49.2125" x2="66.04" y2="38.370690625" width="0.254" layer="16"/>
|
||||
<wire x1="66.04" y1="38.370690625" x2="66.03143125" y2="38.362121875" width="0.254" layer="16"/>
|
||||
</signal>
|
||||
<signal name="DQ5">
|
||||
<contactref element="IC2" pad="121"/>
|
||||
@@ -6412,9 +6422,9 @@ Sollten andere Lagen belegt und relevant sein, so teilen Sie uns dies bitte expl
|
||||
<wire x1="53.965428125" y1="49.170290625" x2="67.335771875" y2="49.170290625" width="0.254" layer="1"/>
|
||||
<wire x1="67.335771875" y1="49.170290625" x2="67.3587125" y2="49.19323125" width="0.254" layer="1"/>
|
||||
<via x="67.3587125" y="49.19323125" extent="1-16" drill="0.3000125"/>
|
||||
<wire x1="68.1142625" y1="35.798165625" x2="83.111409375" y2="35.798165625" width="0.254" layer="16"/>
|
||||
<wire x1="83.111409375" y1="35.798165625" x2="83.891328125" y2="36.578084375" width="0.254" layer="16"/>
|
||||
<wire x1="83.111409375" y1="35.798165625" x2="83.19074375" y2="35.8775" width="0.254" layer="16"/>
|
||||
<via x="83.891328125" y="36.578084375" extent="1-16" drill="0.3000125"/>
|
||||
<wire x1="83.267246875" y1="35.954003125" x2="83.891328125" y2="36.578084375" width="0.254" layer="16"/>
|
||||
<wire x1="83.891328125" y1="36.578084375" x2="83.891328125" y2="38.27440625" width="0.254" layer="1"/>
|
||||
<wire x1="83.891328125" y1="38.27440625" x2="83.832840625" y2="38.33289375" width="0.254" layer="1"/>
|
||||
<wire x1="83.832840625" y1="38.33289375" x2="83.832840625" y2="38.254903125" width="0.254" layer="1"/>
|
||||
@@ -6427,8 +6437,6 @@ Sollten andere Lagen belegt und relevant sein, so teilen Sie uns dies bitte expl
|
||||
<wire x1="88.18443125" y1="68.662434375" x2="89.087615625" y2="69.56561875" width="0.254" layer="1"/>
|
||||
<wire x1="89.087615625" y1="69.56561875" x2="89.087615625" y2="73.85923125" width="0.254" layer="1"/>
|
||||
<wire x1="89.087615625" y1="73.85923125" x2="89.09" y2="73.861615625" width="0.254" layer="1"/>
|
||||
<wire x1="67.3587125" y1="49.19323125" x2="67.3587125" y2="36.553715625" width="0.254" layer="16"/>
|
||||
<wire x1="67.3587125" y1="36.553715625" x2="68.1142625" y2="35.798165625" width="0.254" layer="16"/>
|
||||
<wire x1="19.995" y1="62.405" x2="19.995" y2="60.79406875" width="0.254" layer="1"/>
|
||||
<wire x1="19.995" y1="60.79406875" x2="19.988509375" y2="60.787578125" width="0.254" layer="1"/>
|
||||
<via x="19.988509375" y="60.787578125" extent="1-16" drill="0.3000125"/>
|
||||
@@ -6470,6 +6478,10 @@ Sollten andere Lagen belegt und relevant sein, so teilen Sie uns dies bitte expl
|
||||
<wire x1="45.3597" y1="48.1796" x2="45.362165625" y2="48.177134375" width="0.254" layer="16"/>
|
||||
<wire x1="83.84" y1="38.85" x2="83.84" y2="38.340053125" width="0.254" layer="1"/>
|
||||
<wire x1="83.84" y1="38.340053125" x2="83.832840625" y2="38.33289375" width="0.254" layer="1"/>
|
||||
<wire x1="67.3587125" y1="49.19323125" x2="67.3587125" y2="38.2100375" width="0.254" layer="16"/>
|
||||
<wire x1="67.3587125" y1="38.2100375" x2="69.69125" y2="35.8775" width="0.254" layer="16"/>
|
||||
<wire x1="69.69125" y1="35.8775" x2="83.19074375" y2="35.8775" width="0.254" layer="16"/>
|
||||
<wire x1="83.19074375" y1="35.8775" x2="83.267246875" y2="35.954003125" width="0.254" layer="16"/>
|
||||
</signal>
|
||||
<signal name="DQ4">
|
||||
<contactref element="IC2" pad="124"/>
|
||||
@@ -6793,12 +6805,6 @@ Sollten andere Lagen belegt und relevant sein, so teilen Sie uns dies bitte expl
|
||||
<wire x1="22.37826875" y1="55.950940625" x2="8.5359375" y2="55.950940625" width="0.254" layer="1"/>
|
||||
<wire x1="8.5359375" y1="55.950940625" x2="7.885" y2="56.601878125" width="0.254" layer="1"/>
|
||||
<wire x1="84.34" y1="50.05" x2="84.34" y2="53.3606125" width="0.254" layer="1"/>
|
||||
<wire x1="84.34" y1="53.3606125" x2="85.5516375" y2="54.57225" width="0.254" layer="1"/>
|
||||
<wire x1="85.5516375" y1="54.57225" x2="85.496071875" y2="54.57225" width="0.254" layer="1"/>
|
||||
<wire x1="85.496071875" y1="54.57225" x2="85.18995625" y2="54.878365625" width="0.254" layer="1"/>
|
||||
<wire x1="85.18995625" y1="54.878365625" x2="84.260059375" y2="54.878365625" width="0.254" layer="1"/>
|
||||
<wire x1="84.260059375" y1="54.878365625" x2="84.1177125" y2="54.73601875" width="0.254" layer="1"/>
|
||||
<wire x1="84.1177125" y1="54.73601875" x2="82.038615625" y2="54.73601875" width="0.254" layer="1"/>
|
||||
<wire x1="82.038615625" y1="54.73601875" x2="81.79713125" y2="54.494534375" width="0.254" layer="1"/>
|
||||
<wire x1="81.79713125" y1="54.494534375" x2="78.215728125" y2="54.494534375" width="0.254" layer="1"/>
|
||||
<wire x1="78.215728125" y1="54.494534375" x2="77.719346875" y2="54.990915625" width="0.254" layer="1"/>
|
||||
@@ -6831,6 +6837,10 @@ Sollten andere Lagen belegt und relevant sein, so teilen Sie uns dies bitte expl
|
||||
<wire x1="55.165678125" y1="52.534759375" x2="54.1810375" y2="53.5194" width="0.254" layer="16"/>
|
||||
<wire x1="54.1810375" y1="53.5194" x2="54.1810375" y2="58.195615625" width="0.254" layer="16"/>
|
||||
<wire x1="54.1810375" y1="58.195615625" x2="54.223696875" y2="58.238275" width="0.254" layer="16"/>
|
||||
<wire x1="82.038615625" y1="54.73601875" x2="83.633621875" y2="54.73601875" width="0.254" layer="1"/>
|
||||
<wire x1="83.633621875" y1="54.73601875" x2="84.33516875" y2="54.034471875" width="0.254" layer="1"/>
|
||||
<wire x1="84.33516875" y1="54.034471875" x2="84.33516875" y2="53.36544375" width="0.254" layer="1"/>
|
||||
<wire x1="84.33516875" y1="53.36544375" x2="84.34" y2="53.3606125" width="0.254" layer="1"/>
|
||||
</signal>
|
||||
<signal name="DQ14">
|
||||
<contactref element="IC2" pad="131"/>
|
||||
@@ -6862,14 +6872,7 @@ Sollten andere Lagen belegt und relevant sein, so teilen Sie uns dies bitte expl
|
||||
<wire x1="44.299215625" y1="50.555346875" x2="26.35709375" y2="50.555346875" width="0.254" layer="16"/>
|
||||
<wire x1="26.35709375" y1="50.555346875" x2="25.88228125" y2="51.030159375" width="0.254" layer="16"/>
|
||||
<wire x1="84.84" y1="50.05" x2="84.84" y2="53.065890625" width="0.254" layer="1"/>
|
||||
<wire x1="84.84" y1="53.065890625" x2="86.3465" y2="54.572390625" width="0.254" layer="1"/>
|
||||
<wire x1="86.3465" y1="54.572390625" x2="86.3465" y2="54.827978125" width="0.254" layer="1"/>
|
||||
<wire x1="86.3465" y1="54.827978125" x2="85.790490625" y2="55.3839875" width="0.254" layer="1"/>
|
||||
<wire x1="85.790490625" y1="55.3839875" x2="84.122484375" y2="55.3839875" width="0.254" layer="1"/>
|
||||
<wire x1="84.122484375" y1="55.3839875" x2="84.017278125" y2="55.27878125" width="0.254" layer="1"/>
|
||||
<wire x1="84.017278125" y1="55.27878125" x2="83.98724375" y2="55.27878125" width="0.254" layer="1"/>
|
||||
<wire x1="83.98724375" y1="55.27878125" x2="83.851978125" y2="55.143515625" width="0.254" layer="1"/>
|
||||
<wire x1="83.851978125" y1="55.143515625" x2="81.79328125" y2="55.143515625" width="0.254" layer="1"/>
|
||||
<wire x1="83.8947875" y1="55.143515625" x2="81.79328125" y2="55.143515625" width="0.254" layer="1"/>
|
||||
<wire x1="81.79328125" y1="55.143515625" x2="81.582865625" y2="54.9331" width="0.254" layer="1"/>
|
||||
<wire x1="81.582865625" y1="54.9331" x2="78.472303125" y2="54.9331" width="0.254" layer="1"/>
|
||||
<wire x1="78.472303125" y1="54.9331" x2="77.99135625" y2="55.414046875" width="0.254" layer="1"/>
|
||||
@@ -6900,6 +6903,9 @@ Sollten andere Lagen belegt und relevant sein, so teilen Sie uns dies bitte expl
|
||||
<wire x1="47.0189375" y1="50.3844375" x2="51.228625" y2="54.594125" width="0.254" layer="16"/>
|
||||
<wire x1="51.228625" y1="54.594125" x2="51.228625" y2="58.115309375" width="0.254" layer="16"/>
|
||||
<wire x1="51.228625" y1="58.115309375" x2="51.2271625" y2="58.116771875" width="0.254" layer="16"/>
|
||||
<wire x1="83.8947875" y1="55.143515625" x2="84.83686875" y2="54.201434375" width="0.254" layer="1"/>
|
||||
<wire x1="84.83686875" y1="54.201434375" x2="84.83686875" y2="53.069021875" width="0.254" layer="1"/>
|
||||
<wire x1="84.83686875" y1="53.069021875" x2="84.84" y2="53.065890625" width="0.254" layer="1"/>
|
||||
</signal>
|
||||
<signal name="DQ13">
|
||||
<contactref element="IC2" pad="113"/>
|
||||
@@ -8564,6 +8570,41 @@ Sollten andere Lagen belegt und relevant sein, so teilen Sie uns dies bitte expl
|
||||
</signal>
|
||||
<signal name="INT6">
|
||||
<contactref element="CN1" pad="22"/>
|
||||
<contactref element="IC2" pad="135"/>
|
||||
<wire x1="47.40421875" y1="52.5166" x2="47.417415625" y2="52.5166" width="0.254" layer="1"/>
|
||||
<wire x1="47.40421875" y1="52.5166" x2="47.4366" y2="52.5166" width="0.254" layer="1"/>
|
||||
<wire x1="56.35625" y1="53.34" x2="63.97625" y2="53.34" width="0.254" layer="1"/>
|
||||
<wire x1="63.97625" y1="53.34" x2="64.4525" y2="53.81625" width="0.254" layer="1"/>
|
||||
<via x="64.4525" y="53.81625" extent="1-16" drill="0.3000125"/>
|
||||
<wire x1="64.4525" y1="53.81625" x2="64.4525" y2="50.00625" width="0.254" layer="16"/>
|
||||
<wire x1="64.4525" y1="50.00625" x2="65.56375" y2="48.895" width="0.254" layer="16"/>
|
||||
<wire x1="65.56375" y1="48.895" x2="65.56375" y2="38.735" width="0.254" layer="16"/>
|
||||
<wire x1="65.56375" y1="38.735" x2="65.24625" y2="38.4175" width="0.254" layer="16"/>
|
||||
<wire x1="65.24625" y1="38.4175" x2="65.24625" y2="38.1" width="0.254" layer="16"/>
|
||||
<wire x1="65.24625" y1="38.1" x2="65.88125" y2="37.465" width="0.254" layer="16"/>
|
||||
<wire x1="47.4366" y1="52.5166" x2="47.4366" y2="52.548803125" width="0.254" layer="1"/>
|
||||
<wire x1="47.4366" y1="52.548803125" x2="50.1929375" y2="55.305140625" width="0.254" layer="1"/>
|
||||
<wire x1="53.8970625" y1="55.3229375" x2="54.76875" y2="54.45125" width="0.254" layer="1"/>
|
||||
<wire x1="50.1929375" y1="55.305140625" x2="50.198840625" y2="55.305140625" width="0.254" layer="1"/>
|
||||
<wire x1="50.198840625" y1="55.305140625" x2="50.2166375" y2="55.3229375" width="0.254" layer="1"/>
|
||||
<wire x1="50.2166375" y1="55.3229375" x2="53.8970625" y2="55.3229375" width="0.254" layer="1"/>
|
||||
<wire x1="54.76875" y1="54.45125" x2="54.783990625" y2="54.45125" width="0.254" layer="1"/>
|
||||
<wire x1="54.783990625" y1="54.45125" x2="54.82038125" y2="54.414859375" width="0.254" layer="1"/>
|
||||
<wire x1="54.82038125" y1="54.414859375" x2="55.281390625" y2="54.414859375" width="0.254" layer="1"/>
|
||||
<wire x1="55.281390625" y1="54.414859375" x2="56.35625" y2="53.34" width="0.254" layer="1"/>
|
||||
<wire x1="65.88125" y1="37.465" x2="66.577209375" y2="37.465" width="0.254" layer="16"/>
|
||||
<wire x1="66.577209375" y1="37.465" x2="69.3647375" y2="34.677471875" width="0.254" layer="16"/>
|
||||
<wire x1="69.3647375" y1="34.677471875" x2="94.331196875" y2="34.677471875" width="0.254" layer="16"/>
|
||||
<wire x1="94.331196875" y1="34.677471875" x2="97.55928125" y2="31.4493875" width="0.254" layer="16"/>
|
||||
<wire x1="97.55928125" y1="31.4493875" x2="97.55928125" y2="23.281484375" width="0.254" layer="16"/>
|
||||
<wire x1="97.55928125" y1="23.281484375" x2="99.089621875" y2="21.75114375" width="0.254" layer="16"/>
|
||||
<wire x1="99.089621875" y1="21.75114375" x2="100.0997" y2="21.75114375" width="0.254" layer="16"/>
|
||||
<wire x1="100.0997" y1="21.75114375" x2="100.833571875" y2="21.017271875" width="0.254" layer="16"/>
|
||||
<via x="100.833571875" y="21.017271875" extent="1-16" drill="0.3000125"/>
|
||||
<wire x1="100.833571875" y1="21.017271875" x2="100.833571875" y2="21.017109375" width="0.254" layer="1"/>
|
||||
<wire x1="100.833571875" y1="21.017109375" x2="101.999071875" y2="19.851609375" width="0.254" layer="1"/>
|
||||
<wire x1="101.999071875" y1="19.851609375" x2="101.999071875" y2="5.098071875" width="0.254" layer="1"/>
|
||||
<wire x1="101.999071875" y1="5.098071875" x2="101.981" y2="5.08" width="0.254" layer="1"/>
|
||||
</signal>
|
||||
<signal name="LAN_A12">
|
||||
<contactref element="IC2" pad="136"/>
|
||||
@@ -8586,20 +8627,21 @@ Sollten andere Lagen belegt und relevant sein, so teilen Sie uns dies bitte expl
|
||||
<wire x1="62.105803125" y1="56.94960625" x2="61.569175" y2="57.486234375" width="0.254" layer="1"/>
|
||||
<wire x1="61.569175" y1="57.486234375" x2="59.624221875" y2="57.486234375" width="0.254" layer="1"/>
|
||||
<wire x1="59.624221875" y1="57.486234375" x2="59.3156625" y2="57.79479375" width="0.254" layer="1"/>
|
||||
<wire x1="47.050665625" y1="52.870153125" x2="47.072325" y2="52.870153125" width="0.254" layer="1"/>
|
||||
<wire x1="47.061053125" y1="52.870153125" x2="47.072325" y2="52.870153125" width="0.254" layer="1"/>
|
||||
<wire x1="47.050665625" y1="52.870153125" x2="47.061053125" y2="52.870153125" width="0.254" layer="1"/>
|
||||
<wire x1="47.061053125" y1="52.870153125" x2="49.956028125" y2="55.765128125" width="0.254" layer="1"/>
|
||||
<wire x1="59.3156625" y1="57.79479375" x2="56.227684375" y2="57.79479375" width="0.254" layer="1"/>
|
||||
<wire x1="56.227684375" y1="57.79479375" x2="56.225309375" y2="57.79241875" width="0.254" layer="1"/>
|
||||
<via x="56.225309375" y="57.79241875" extent="1-16" drill="0.3000125"/>
|
||||
<wire x1="56.27795" y1="57.739778125" x2="56.225309375" y2="57.79241875" width="0.254" layer="16"/>
|
||||
<wire x1="49.956028125" y1="55.765128125" x2="54.14889375" y2="55.765128125" width="0.254" layer="1"/>
|
||||
<wire x1="54.14889375" y1="55.765128125" x2="55.06218125" y2="54.851840625" width="0.254" layer="1"/>
|
||||
<wire x1="55.06218125" y1="54.851840625" x2="55.79531875" y2="54.851840625" width="0.254" layer="1"/>
|
||||
<wire x1="55.79531875" y1="54.851840625" x2="56.233984375" y2="54.413175" width="0.254" layer="1"/>
|
||||
<via x="56.233984375" y="54.413175" extent="1-16" drill="0.3000125"/>
|
||||
<wire x1="56.233984375" y1="54.413175" x2="56.233984375" y2="57.78374375" width="0.254" layer="16"/>
|
||||
<wire x1="56.233984375" y1="57.78374375" x2="56.225309375" y2="57.79241875" width="0.254" layer="16"/>
|
||||
<wire x1="47.061053125" y1="52.870153125" x2="47.061053125" y2="52.884234375" width="0.254" layer="1"/>
|
||||
<wire x1="47.061053125" y1="52.884234375" x2="49.919565625" y2="55.742746875" width="0.254" layer="1"/>
|
||||
<wire x1="49.919565625" y1="55.742746875" x2="54.171275" y2="55.742746875" width="0.254" layer="1"/>
|
||||
<wire x1="54.171275" y1="55.742746875" x2="55.06218125" y2="54.851840625" width="0.254" layer="1"/>
|
||||
</signal>
|
||||
<signal name="LAN_A13">
|
||||
<contactref element="IC2" pad="137"/>
|
||||
@@ -8628,7 +8670,7 @@ Sollten andere Lagen belegt und relevant sein, so teilen Sie uns dies bitte expl
|
||||
<wire x1="46.725190625" y1="53.256178125" x2="49.6377875" y2="56.168775" width="0.254" layer="1"/>
|
||||
<wire x1="58.897615625" y1="57.0301" x2="58.804590625" y2="57.123125" width="0.254" layer="1"/>
|
||||
<via x="58.804590625" y="57.123125" extent="1-16" drill="0.3000125"/>
|
||||
<wire x1="54.400265625" y1="56.173284375" x2="55.247740625" y2="55.325809375" width="0.254" layer="1"/>
|
||||
<wire x1="54.37605" y1="56.1975" x2="55.247740625" y2="55.325809375" width="0.254" layer="1"/>
|
||||
<wire x1="55.247740625" y1="55.325809375" x2="56.300475" y2="55.325809375" width="0.254" layer="1"/>
|
||||
<wire x1="56.300475" y1="55.325809375" x2="56.93216875" y2="54.694115625" width="0.254" layer="1"/>
|
||||
<wire x1="56.93216875" y1="54.694115625" x2="56.93216875" y2="54.15264375" width="0.254" layer="1"/>
|
||||
@@ -8639,17 +8681,15 @@ Sollten andere Lagen belegt und relevant sein, so teilen Sie uns dies bitte expl
|
||||
<wire x1="58.804590625" y1="53.9421" x2="58.804590625" y2="57.123125" width="0.254" layer="16"/>
|
||||
<wire x1="49.6377875" y1="56.168775" x2="49.6411125" y2="56.168775" width="0.254" layer="1"/>
|
||||
<wire x1="49.6411125" y1="56.168775" x2="49.645621875" y2="56.173284375" width="0.254" layer="1"/>
|
||||
<wire x1="49.645621875" y1="56.173284375" x2="54.400265625" y2="56.173284375" width="0.254" layer="1"/>
|
||||
<wire x1="49.645621875" y1="56.173284375" x2="49.664534375" y2="56.173284375" width="0.254" layer="1"/>
|
||||
<wire x1="49.664534375" y1="56.173284375" x2="49.68875" y2="56.1975" width="0.254" layer="1"/>
|
||||
<wire x1="49.68875" y1="56.1975" x2="54.37605" y2="56.1975" width="0.254" layer="1"/>
|
||||
</signal>
|
||||
<signal name="LAN_WRH">
|
||||
<contactref element="IC2" pad="132"/>
|
||||
<contactref element="IC1" pad="48"/>
|
||||
<wire x1="48.464878125" y1="51.455940625" x2="48.50868125" y2="51.455940625" width="0.254" layer="1"/>
|
||||
<wire x1="48.50868125" y1="51.455940625" x2="49.247478125" y2="52.1947375" width="0.254" layer="1"/>
|
||||
<wire x1="49.247478125" y1="52.1947375" x2="49.787659375" y2="52.1947375" width="0.254" layer="1"/>
|
||||
<wire x1="49.787659375" y1="52.1947375" x2="50.868259375" y2="53.2753375" width="0.254" layer="1"/>
|
||||
<wire x1="50.868259375" y1="53.2753375" x2="50.868259375" y2="53.69455625" width="0.254" layer="1"/>
|
||||
<wire x1="50.868259375" y1="53.69455625" x2="51.15701875" y2="53.983315625" width="0.254" layer="1"/>
|
||||
<wire x1="53.213075" y1="54.05255625" x2="54.27944375" y2="52.9861875" width="0.254" layer="1"/>
|
||||
<wire x1="54.27944375" y1="52.9861875" x2="54.589903125" y2="52.9861875" width="0.254" layer="1"/>
|
||||
<wire x1="54.589903125" y1="52.9861875" x2="54.93145" y2="52.644640625" width="0.254" layer="1"/>
|
||||
@@ -8676,6 +8716,10 @@ Sollten andere Lagen belegt und relevant sein, so teilen Sie uns dies bitte expl
|
||||
<wire x1="68.6743875" y1="50.55461875" x2="69.3797125" y2="49.84929375" width="0.254" layer="1"/>
|
||||
<wire x1="69.3797125" y1="49.84929375" x2="81.13929375" y2="49.84929375" width="0.254" layer="1"/>
|
||||
<wire x1="81.13929375" y1="49.84929375" x2="81.34" y2="50.05" width="0.254" layer="1"/>
|
||||
<wire x1="49.247478125" y1="52.1947375" x2="49.247478125" y2="52.202540625" width="0.254" layer="1"/>
|
||||
<wire x1="49.247478125" y1="52.202540625" x2="50.207128125" y2="53.162190625" width="0.254" layer="1"/>
|
||||
<wire x1="50.207128125" y1="53.162190625" x2="50.33589375" y2="53.162190625" width="0.254" layer="1"/>
|
||||
<wire x1="50.33589375" y1="53.162190625" x2="51.15701875" y2="53.983315625" width="0.254" layer="1"/>
|
||||
</signal>
|
||||
<signal name="LAN_INT">
|
||||
<contactref element="IC2" pad="111"/>
|
||||
@@ -8717,15 +8761,8 @@ Sollten andere Lagen belegt und relevant sein, so teilen Sie uns dies bitte expl
|
||||
<contactref element="IC2" pad="133"/>
|
||||
<contactref element="IC1" pad="49"/>
|
||||
<wire x1="48.111325" y1="51.80949375" x2="48.12655" y2="51.80949375" width="0.254" layer="1"/>
|
||||
<wire x1="48.12655" y1="51.80949375" x2="49.054134375" y2="52.737078125" width="0.254" layer="1"/>
|
||||
<wire x1="49.054134375" y1="52.737078125" x2="49.55685625" y2="52.737078125" width="0.254" layer="1"/>
|
||||
<wire x1="49.55685625" y1="52.737078125" x2="50.26279375" y2="53.443015625" width="0.254" layer="1"/>
|
||||
<wire x1="50.26279375" y1="53.443015625" x2="50.26279375" y2="53.983353125" width="0.254" layer="1"/>
|
||||
<wire x1="50.26279375" y1="53.983353125" x2="50.81236875" y2="54.532928125" width="0.254" layer="1"/>
|
||||
<wire x1="79.49" y1="48.2" x2="77.92208125" y2="48.2" width="0.254" layer="1"/>
|
||||
<via x="76.95481875" y="49.1672625" extent="1-16" drill="0.3000125"/>
|
||||
<wire x1="50.81236875" y1="54.532928125" x2="53.451946875" y2="54.532928125" width="0.254" layer="1"/>
|
||||
<wire x1="53.451946875" y1="54.532928125" x2="54.524609375" y2="53.460265625" width="0.254" layer="1"/>
|
||||
<wire x1="54.524609375" y1="53.460265625" x2="54.826234375" y2="53.460265625" width="0.254" layer="1"/>
|
||||
<wire x1="54.826234375" y1="53.460265625" x2="55.865928125" y2="52.420571875" width="0.254" layer="1"/>
|
||||
<wire x1="55.865928125" y1="52.420571875" x2="64.51739375" y2="52.420571875" width="0.254" layer="1"/>
|
||||
@@ -8742,6 +8779,13 @@ Sollten andere Lagen belegt und relevant sein, so teilen Sie uns dies bitte expl
|
||||
<wire x1="77.92208125" y1="48.2" x2="76.95481875" y2="49.1672625" width="0.254" layer="1"/>
|
||||
<wire x1="76.95481875" y1="49.1672625" x2="76.95481875" y2="50.49271875" width="0.254" layer="16"/>
|
||||
<wire x1="76.95481875" y1="50.49271875" x2="76.94125625" y2="50.50628125" width="0.254" layer="16"/>
|
||||
<wire x1="50.26279375" y1="53.75009375" x2="50.97343125" y2="54.46073125" width="0.254" layer="1"/>
|
||||
<wire x1="53.491384375" y1="54.493490625" x2="54.524609375" y2="53.460265625" width="0.254" layer="1"/>
|
||||
<wire x1="50.97343125" y1="54.46073125" x2="50.9757875" y2="54.46073125" width="0.254" layer="1"/>
|
||||
<wire x1="50.9757875" y1="54.46073125" x2="51.008546875" y2="54.493490625" width="0.254" layer="1"/>
|
||||
<wire x1="51.008546875" y1="54.493490625" x2="53.491384375" y2="54.493490625" width="0.254" layer="1"/>
|
||||
<wire x1="50.26279375" y1="53.75009375" x2="50.06715" y2="53.75009375" width="0.254" layer="1"/>
|
||||
<wire x1="50.06715" y1="53.75009375" x2="48.12655" y2="51.80949375" width="0.254" layer="1"/>
|
||||
</signal>
|
||||
<signal name="LAN_CFG4">
|
||||
<contactref element="IC2" pad="110"/>
|
||||
@@ -8825,16 +8869,17 @@ Sollten andere Lagen belegt und relevant sein, so teilen Sie uns dies bitte expl
|
||||
<wire x1="76.2944875" y1="48.08710625" x2="76.443990625" y2="47.937603125" width="0.254" layer="16"/>
|
||||
<wire x1="76.268615625" y1="48.112978125" x2="76.268615625" y2="51.215896875" width="0.254" layer="16"/>
|
||||
<wire x1="76.268615625" y1="51.215896875" x2="76.31065625" y2="51.2579375" width="0.254" layer="16"/>
|
||||
<wire x1="53.65649375" y1="54.94485625" x2="50.53958125" y2="54.94485625" width="0.254" layer="1"/>
|
||||
<wire x1="50.53958125" y1="54.94485625" x2="47.757771875" y2="52.163046875" width="0.254" layer="1"/>
|
||||
<wire x1="54.683690625" y1="53.917659375" x2="53.65649375" y2="54.94485625" width="0.254" layer="1"/>
|
||||
<wire x1="69.19269375" y1="51.408925" x2="69.866828125" y2="50.734790625" width="0.254" layer="1"/>
|
||||
<wire x1="69.866828125" y1="50.734790625" x2="75.787509375" y2="50.734790625" width="0.254" layer="1"/>
|
||||
<wire x1="75.787509375" y1="50.734790625" x2="76.31065625" y2="51.2579375" width="0.254" layer="1"/>
|
||||
</signal>
|
||||
<signal name="LAN_CGF2">
|
||||
<contactref element="IC2" pad="135"/>
|
||||
<wire x1="47.40421875" y1="52.5166" x2="47.417415625" y2="52.5166" width="0.254" layer="1"/>
|
||||
<wire x1="54.683690625" y1="53.917659375" x2="54.683690625" y2="53.94025" width="0.254" layer="1"/>
|
||||
<wire x1="50.47846875" y1="54.88374375" x2="47.757771875" y2="52.163046875" width="0.254" layer="1"/>
|
||||
<wire x1="50.47846875" y1="54.88374375" x2="50.47846875" y2="54.885934375" width="0.254" layer="1"/>
|
||||
<wire x1="50.47846875" y1="54.885934375" x2="50.4907875" y2="54.885934375" width="0.254" layer="1"/>
|
||||
<wire x1="50.4907875" y1="54.885934375" x2="50.5065125" y2="54.901659375" width="0.254" layer="1"/>
|
||||
<wire x1="50.5065125" y1="54.901659375" x2="53.68121875" y2="54.901659375" width="0.254" layer="1"/>
|
||||
<wire x1="54.683690625" y1="53.94025" x2="54.642628125" y2="53.94025" width="0.254" layer="1"/>
|
||||
<wire x1="54.642628125" y1="53.94025" x2="53.68121875" y2="54.901659375" width="0.254" layer="1"/>
|
||||
</signal>
|
||||
<signal name="LAN_CFG1">
|
||||
<contactref element="IC2" pad="12"/>
|
||||
@@ -9268,17 +9313,12 @@ Sollten andere Lagen belegt und relevant sein, so teilen Sie uns dies bitte expl
|
||||
<wire x1="87.84" y1="37.327421875" x2="88.522209375" y2="36.6452125" width="0.254" layer="1"/>
|
||||
<via x="88.522209375" y="36.6452125" extent="1-16" drill="0.3000125"/>
|
||||
<wire x1="88.522209375" y1="36.6452125" x2="88.522209375" y2="36.4957625" width="0.254" layer="16"/>
|
||||
<wire x1="88.522209375" y1="36.4957625" x2="88.7114125" y2="36.306559375" width="0.254" layer="16"/>
|
||||
<wire x1="88.7114125" y1="36.306559375" x2="88.7114125" y2="35.480178125" width="0.254" layer="16"/>
|
||||
<wire x1="88.7114125" y1="35.480178125" x2="89.117984375" y2="35.07360625" width="0.254" layer="16"/>
|
||||
<wire x1="89.117984375" y1="35.07360625" x2="89.695021875" y2="35.07360625" width="0.254" layer="16"/>
|
||||
<wire x1="89.695021875" y1="35.07360625" x2="90.00981875" y2="35.388403125" width="0.254" layer="16"/>
|
||||
<via x="100.599875" y="32.92475" extent="1-16" drill="0.3000125"/>
|
||||
<via x="97.774125" y="32.750125" extent="1-16" drill="0.3000125"/>
|
||||
<contactref element="LEDB" pad="1"/>
|
||||
<wire x1="121.0945" y1="51.927125" x2="120.99925" y2="51.927125" width="0.254" layer="16"/>
|
||||
<contactref element="SV1" pad="13"/>
|
||||
<wire x1="90.00981875" y1="35.388403125" x2="95.135846875" y2="35.388403125" width="0.254" layer="16"/>
|
||||
<wire x1="89.77901875" y1="35.388403125" x2="95.135846875" y2="35.388403125" width="0.254" layer="16"/>
|
||||
<wire x1="95.135846875" y1="35.388403125" x2="97.774125" y2="32.750125" width="0.254" layer="16"/>
|
||||
<wire x1="100.917375" y1="39.798625" x2="100.917375" y2="33.24225" width="0.254" layer="16"/>
|
||||
<wire x1="97.774125" y1="32.750125" x2="100.42525" y2="32.750125" width="0.254" layer="1"/>
|
||||
@@ -9303,6 +9343,7 @@ Sollten andere Lagen belegt und relevant sein, so teilen Sie uns dies bitte expl
|
||||
<wire x1="104.4575" y1="47.450375" x2="103.8225" y2="46.815375" width="0.254" layer="16"/>
|
||||
<wire x1="103.8225" y1="46.815375" x2="103.8225" y2="41.8465" width="0.254" layer="16"/>
|
||||
<wire x1="103.8225" y1="41.8465" x2="101.774625" y2="39.798625" width="0.254" layer="16"/>
|
||||
<wire x1="89.77901875" y1="35.388403125" x2="88.522209375" y2="36.6452125" width="0.254" layer="16"/>
|
||||
</signal>
|
||||
<signal name="N$2">
|
||||
</signal>
|
||||
@@ -16496,7 +16496,7 @@ Low profile connectors, straight<p>
|
||||
<label x="60.96" y="157.48" size="1.27" layer="95" rot="R90"/>
|
||||
</segment>
|
||||
</net>
|
||||
<net name="LAN_CGF2" class="0">
|
||||
<net name="INT6" class="0">
|
||||
<segment>
|
||||
<pinref part="IC2" gate="G$1" pin="P$135-FB6MC02"/>
|
||||
<wire x1="58.42" y1="154.94" x2="58.42" y2="157.48" width="0.1524" layer="91"/>
|
||||
Reference in New Issue
Block a user