Dominick.Vansevenant/Zorro-LAN-IDE
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
Files
94425362cc083230caefe6f526b25db6dbad8460
Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.rpt
T

3221 lines
170 KiB
Plaintext
Raw Blame History

cpldfit: version P.20131013 Xilinx Inc.
Fitter Report
Design Name: LAN_IDE_CP Date: 2-19-2019, 10:47PM
Device Used: XC95288XL-10-TQ144
Fitting Status: Successful
************************* Mapped Resource Summary **************************
Macrocells Product Terms Function Block Registers Pins
Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot
220/288 ( 76%) 1031/1440 ( 72%) 513/864 ( 59%) 141/288 ( 49%) 114/117 ( 97%)
** Function Block Resources **
Function Mcells FB Inps Pterms IO
Block Used/Tot Used/Tot Used/Tot Used/Tot
FB1 17/18 41/54 60/90 8/ 8*
FB2 18/18* 42/54 58/90 10/10*
FB3 6/18 13/54 10/90 4/ 5
FB4 13/18 37/54 67/90 6/ 6*
FB5 12/18 41/54 48/90 7/ 8
FB6 18/18* 23/54 39/90 8/ 8*
FB7 15/18 41/54 85/90 4/ 4*
FB8 16/18 38/54 79/90 5/ 5*
FB9 15/18 32/54 89/90 9/ 9*
FB10 10/18 14/54 24/90 10/10*
FB11 17/18 28/54 79/90 7/ 7*
FB12 15/18 41/54 69/90 6/ 6*
FB13 11/18 37/54 89/90 6/ 6*
FB14 14/18 23/54 79/90 7/ 8
FB15 9/18 35/54 81/90 9/ 9*
FB16 14/18 27/54 75/90 8/ 8*
----- ----- ----- -----
220/288 513/864 1031/1440 114/117
* - Resource is exhausted
** Global Control Resources **
Signal 'CLK_EXT' mapped onto global clock net GCK1.
Global output enable net(s) unused.
Global set/reset net(s) unused.
** Pin Resources **
Signal Type Required Mapped | Pin Type Used Total
------------------------------------|------------------------------------
Input : 23 23 | I/O : 107 109
Output : 42 42 | GCK/IO : 2 3
Bidirectional : 48 48 | GTS/IO : 4 4
GCK : 1 1 | GSR/IO : 1 1
GTS : 0 0 |
GSR : 0 0 |
---- ----
Total 114 114
** Power Data **
There are 220 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
End of Mapped Resource Summary
************************** Errors and Warnings ***************************
WARNING:Cpld - Unable to retrieve the path to the iSE Project Repository. Will
use the default filename of 'LAN_IDE_CP.ise'.
INFO:Cpld - Inferring BUFG constraint for signal 'CLK_EXT' based upon the LOC
constraint 'P30'. It is recommended that you declare this BUFG explicitedly
in your design. Note that for certain device families the output of a BUFG
constraint can not drive a gated clock, and the BUFG constraint will be
ignored.
WARNING:Cpld:1007 - Removing unused input(s) 'IDE_WAIT'. The input(s) are
unused after optimization. Please verify functionality via simulation.
WARNING:Cpld:1007 - Removing unused input(s) 'MTCR'. The input(s) are unused
after optimization. Please verify functionality via simulation.
************************* Summary of Mapped Logic ************************
** 90 Outputs **
Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init
Name Pts Inps No. Type Use Mode Rate State
D<5> 2 5 FB1_5 20 I/O I/O STD FAST
D<4> 2 5 FB1_6 21 I/O I/O STD FAST
IDE_CS<0> 1 1 FB1_8 22 I/O O STD FAST
IDE_CS<1> 1 1 FB1_10 23 I/O O STD FAST
IDE_A<0> 1 1 FB1_12 24 I/O O STD FAST
IDE_A<2> 1 1 FB1_14 25 I/O O STD FAST
IDE_A<1> 1 1 FB1_15 26 I/O O STD FAST
IDE_R 1 2 FB1_17 27 I/O O STD FAST
A_LAN<4> 1 2 FB2_2 9 I/O O STD FAST
A_LAN<7> 1 2 FB2_3 10 I/O O STD FAST
A_LAN<6> 2 3 FB2_5 11 I/O O STD FAST
LAN_CFG<1> 0 0 FB2_6 12 I/O O STD FAST
LAN_CFG<3> 0 0 FB2_8 13 I/O O STD FAST
D<6> 2 5 FB2_10 14 I/O I/O STD FAST
D<3> 2 5 FB2_12 15 I/O I/O STD FAST
D<7> 2 5 FB2_14 16 I/O I/O STD FAST
D<1> 2 5 FB2_15 17 I/O I/O STD FAST
D<8> 2 5 FB2_17 19 I/O I/O STD FAST
IDE_W 1 2 FB3_2 28 I/O O STD FAST
INT_OUT 1 1 FB3_14 32 GCK/I/O O STD FAST
D<0> 2 5 FB4_2 2 GTS/I/O I/O STD FAST
A_LAN<1> 1 2 FB4_5 3 GTS/I/O O STD FAST
A_LAN<0> 1 2 FB4_6 4 I/O O STD FAST
A_LAN<3> 2 3 FB4_8 5 GTS/I/O O STD FAST
A_LAN<2> 1 2 FB4_12 6 GTS/I/O O STD FAST
A_LAN<5> 1 2 FB4_14 7 I/O O STD FAST
CP_CS 19 19 FB5_2 34 I/O O STD FAST SET
ROM_OE 1 3 FB5_5 35 I/O O STD FAST
D<2> 2 5 FB5_10 39 I/O I/O STD FAST
D<9> 2 5 FB5_12 40 I/O I/O STD FAST
D<10> 2 5 FB5_14 41 I/O I/O STD FAST
D<11> 2 5 FB5_15 43 I/O I/O STD FAST
D<12> 5 6 FB5_17 44 I/O I/O STD FAST
LAN_CFG<2> 0 0 FB6_2 135 I/O O STD FAST
A_LAN<12> 1 2 FB6_3 136 I/O O STD FAST
A_LAN<13> 1 2 FB6_5 137 I/O O STD FAST
A_LAN<10> 1 2 FB6_6 138 I/O O STD FAST
A_LAN<11> 1 2 FB6_8 139 I/O O STD FAST
A_LAN<8> 1 2 FB6_10 140 I/O O STD FAST
A_LAN<9> 1 2 FB6_14 142 I/O O STD FAST
Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init
Name Pts Inps No. Type Use Mode Rate State
D<13> 5 6 FB7_3 45 I/O I/O STD FAST
D<14> 5 6 FB7_5 46 I/O I/O STD FAST
D<15> 5 6 FB7_12 48 I/O I/O STD FAST
DQ<12> 2 3 FB8_2 130 I/O I/O STD FAST
DQ<14> 2 3 FB8_3 131 I/O I/O STD FAST
LAN_WRH 3 4 FB8_5 132 I/O O STD FAST
LAN_CS 2 3 FB8_8 133 I/O O STD FAST
LAN_RD 1 3 FB8_10 134 I/O O STD FAST
A<8> 5 11 FB9_11 56 I/O I/O STD FAST RESET
A<9> 5 11 FB9_14 58 I/O I/O STD FAST RESET
A<10> 5 11 FB9_17 59 I/O I/O STD FAST RESET
DQ<1> 3 4 FB10_2 117 I/O I/O STD FAST
DQ<0> 2 3 FB10_3 118 I/O I/O STD FAST
DQ<3> 2 3 FB10_5 119 I/O I/O STD FAST
DQ<2> 2 3 FB10_6 120 I/O I/O STD FAST
DQ<5> 2 3 FB10_8 121 I/O I/O STD FAST
DQ<4> 3 4 FB10_10 124 I/O I/O STD FAST
DQ<7> 2 3 FB10_11 125 I/O I/O STD FAST
DQ<6> 2 3 FB10_12 126 I/O I/O STD FAST
DQ<8> 3 4 FB10_14 128 I/O I/O STD FAST
DQ<10> 3 4 FB10_17 129 I/O I/O STD FAST
A<11> 5 11 FB11_3 60 I/O I/O STD FAST RESET
A<12> 5 11 FB11_5 61 I/O I/O STD FAST RESET
A<13> 5 11 FB11_10 64 I/O I/O STD FAST RESET
A<14> 5 11 FB11_11 66 I/O I/O STD FAST RESET
ROM_B<0> 0 0 FB11_12 68 I/O O STD FAST
ROM_B<1> 0 0 FB11_14 69 I/O O STD FAST
CP_WE 1 3 FB11_17 70 I/O O STD FAST
LAN_CFG<4> 0 0 FB12_2 110 I/O O STD FAST
DQ<15> 2 3 FB12_5 112 I/O I/O STD FAST
DQ<13> 2 3 FB12_8 113 I/O I/O STD FAST
DQ<11> 3 4 FB12_10 115 I/O I/O STD FAST
DQ<9> 3 4 FB12_12 116 I/O I/O STD FAST
CP_RD 1 2 FB13_2 71 I/O O STD FAST
A<15> 5 11 FB13_8 74 I/O I/O STD FAST RESET
LAN_WRL 3 4 FB13_14 76 I/O O STD FAST
OVR 1 2 FB14_3 100 I/O O STD FAST
CFOUT 1 3 FB14_11 105 I/O O STD FAST
SLAVE 4 6 FB14_14 106 I/O O STD FAST
OWN 0 0 FB14_15 107 I/O O STD FAST
Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init
Name Pts Inps No. Type Use Mode Rate State
DTACK 1 1 FB15_12 85 I/O O STD FAST
A<23> 5 11 FB15_14 86 I/O I/O STD FAST RESET
A<22> 5 11 FB15_15 87 I/O I/O STD FAST RESET
A<21> 5 11 FB15_17 88 I/O I/O STD FAST RESET
A<20> 5 11 FB16_2 91 I/O I/O STD FAST RESET
A<19> 5 11 FB16_3 92 I/O I/O STD FAST RESET
A<18> 5 11 FB16_6 94 I/O I/O STD FAST RESET
A<17> 5 11 FB16_8 95 I/O I/O STD FAST RESET
MTACK 0 0 FB16_10 96 I/O O STD FAST
A<16> 5 11 FB16_11 97 I/O I/O STD FAST RESET
** 130 Buried Nodes **
Signal Total Total Loc Pwr Reg Init
Name Pts Inps Mode State
AUTO_CONFIG_Z2_DONE_CYCLE<2> 4 16 FB1_2 STD RESET
AUTO_CONFIG_Z2_DONE<2> 4 5 FB1_3 STD RESET
IDE_BASEADR<7> 6 18 FB1_4 STD RESET
CP_BASEADR<7> 6 17 FB1_7 STD RESET
CP_BASEADR<4> 6 17 FB1_9 STD RESET
CP_BASEADR<3> 6 17 FB1_11 STD RESET
CP_BASEADR<2> 6 17 FB1_13 STD RESET
CP_BASEADR<1> 6 17 FB1_16 STD RESET
CP_BASEADR<0> 6 17 FB1_18 STD RESET
D_5_IOBUFE/D_5_IOBUFE_TRST 2 5 FB2_1 STD
IDE_BASEADR<6> 6 18 FB2_4 STD RESET
IDE_BASEADR<5> 6 18 FB2_7 STD RESET
IDE_BASEADR<4> 6 18 FB2_9 STD RESET
IDE_BASEADR<3> 6 18 FB2_11 STD RESET
IDE_BASEADR<2> 6 18 FB2_13 STD RESET
IDE_BASEADR<1> 6 18 FB2_16 STD RESET
IDE_BASEADR<0> 6 18 FB2_18 STD RESET
SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF 2 2 FB3_15 STD
ROM_B_0_OBUF$BUF9/ROM_B_0_OBUF$BUF9_TRST 2 3 FB3_16 STD
ROM_B_0_OBUF$BUF8/ROM_B_0_OBUF$BUF8_TRST 2 3 FB3_17 STD
CP_WE_QUIRK 2 2 FB3_18 STD RESET
IDE_ENABLE 3 5 FB4_1 STD RESET
Z3_ADR<12> 3 3 FB4_3 STD RESET
Z3_ADR<11> 3 3 FB4_4 STD RESET
ROM_OE_S 3 6 FB4_7 STD RESET
LAN_ACCESS 21 21 FB4_10 STD RESET
IDE_R_S 3 6 FB4_13 STD RESET
DQ_SWAP 23 23 FB4_16 STD RESET
LAN_A_INIT<3> 1 1 FB5_9 STD SET
LAN_IRQ_D0 2 2 FB5_11 STD RESET
CONFIG_READY 2 4 FB5_13 STD RESET
LAN_INT_ENABLE 5 10 FB5_16 STD RESET
AUTOCONFIG_Z2_ACCESS 5 14 FB5_18 STD RESET
Z3_ADR_1 3 3 FB6_1 STD RESET
Z3_ADR_0 3 3 FB6_4 STD RESET
Z3_ADR<9> 3 3 FB6_7 STD RESET
Z3_ADR<8> 3 3 FB6_9 STD RESET
Z3_ADR<7> 3 3 FB6_11 STD RESET
Z3_ADR<6> 3 3 FB6_12 STD RESET
Z3_ADR<5> 3 3 FB6_13 STD RESET
Signal Total Total Loc Pwr Reg Init
Name Pts Inps Mode State
Z3_ADR<4> 3 3 FB6_15 STD RESET
Z3_ADR<3> 3 3 FB6_16 STD RESET
LAN_WR_RST 3 4 FB6_17 STD RESET
LAN_IRQ_OUT 3 4 FB6_18 STD RESET
CP_BASEADR<5> 6 17 FB7_1 STD RESET
SHUT_UP_Z2<1> 4 16 FB7_2 STD SET
LAN_BASEADR<6> 6 16 FB7_4 STD RESET
LAN_BASEADR<5> 6 16 FB7_7 STD RESET
LAN_BASEADR<2> 6 16 FB7_8 STD RESET
LAN_BASEADR<14> 6 16 FB7_9 STD RESET
LAN_BASEADR<13> 6 16 FB7_10 STD RESET
LAN_BASEADR<11> 6 16 FB7_11 STD RESET
LAN_BASEADR<10> 6 16 FB7_13 STD RESET
LAN_BASEADR<8> 6 16 FB7_16 STD RESET
LAN_BASEADR<0> 6 16 FB7_17 STD RESET
CP_BASEADR<6> 6 17 FB7_18 STD RESET
Z3_ADR<2> 3 3 FB8_1 STD RESET
LAN_BASEADR<12> 6 16 FB8_4 STD RESET
LAN_BASEADR<15> 6 16 FB8_6 STD RESET
LAN_BASEADR<1> 6 16 FB8_7 STD RESET
LAN_BASEADR<3> 6 16 FB8_9 STD RESET
LAN_BASEADR<4> 6 16 FB8_11 STD RESET
LAN_BASEADR<7> 6 16 FB8_12 STD RESET
LAN_BASEADR<9> 6 16 FB8_13 STD RESET
Z3_ADR<10> 3 3 FB8_14 STD RESET
Z3_ADR<13> 3 3 FB8_15 STD RESET
D_Z2_OUT<0> 18 15 FB8_17 STD SET
LAN_WRL_S 3 7 FB9_2 STD RESET
LAN_WRH_S 3 7 FB9_3 STD RESET
LAN_SM_RST 4 9 FB9_4 STD RESET
LAN_SM_FSM_FFd4 4 7 FB9_5 STD RESET
LAN_RD_S 4 6 FB9_6 STD RESET
DQ_12_IOBUFE/DQ_12_IOBUFE_TRST__$INT 4 8 FB9_7 STD
LAN_READY 5 7 FB9_8 STD RESET
LAN_SM_FSM_FFd2 6 9 FB9_9 STD RESET
Z3_A_LOW 7 9 FB9_10 STD RESET
LAN_SM_FSM_FFd1 8 8 FB9_13 STD RESET
DQ_DATA<9> 13 13 FB9_15 STD RESET
DQ_DATA<5> 13 13 FB9_18 STD RESET
Z3_DATA<30> 4 7 FB11_1 STD RESET
Signal Total Total Loc Pwr Reg Init
Name Pts Inps Mode State
Z3_DATA<29> 4 7 FB11_2 STD RESET
Z3_DATA<28> 4 7 FB11_4 STD RESET
Z3_DATA<27> 4 7 FB11_6 STD RESET
Z3_DATA<22> 4 7 FB11_7 STD RESET
Z3_DATA<21> 4 7 FB11_8 STD RESET
Z3_DATA<20> 4 7 FB11_9 STD RESET
Z3_DATA<19> 4 7 FB11_13 STD RESET
DQ_DATA<8> 13 13 FB11_16 STD RESET
DQ_DATA<0> 13 13 FB11_18 STD RESET
LAN_RST_SM_FSM_FFd3 3 4 FB12_1 STD RESET
$OpTx$INV$129 16 16 FB12_3 STD
IDE_W_S 3 5 FB12_6 STD RESET
LAN_A_INIT<6> 3 4 FB12_7 STD SET
LAN_CS_RST 3 4 FB12_9 STD RESET
LAN_D_INIT<1> 3 4 FB12_11 STD RESET
LAN_D_INIT<8> 3 4 FB12_13 STD RESET
LAN_RST_SM_FSM_FFd1 3 4 FB12_14 STD RESET
IDE_ACCESS 19 19 FB12_16 STD RESET
LAN_RST_SM_FSM_FFd2 3 4 FB12_18 STD RESET
Z3_DATA<31> 4 7 FB13_3 STD RESET
LAN_SM_FSM_FFd3 7 10 FB13_5 STD RESET
DQ_DATA<4> 13 13 FB13_6 STD RESET
DQ_DATA<3> 13 13 FB13_11 STD RESET
DQ_DATA<13> 13 13 FB13_12 STD RESET
Z3_DATA<23> 4 7 FB13_15 STD RESET
DQ_DATA<11> 13 13 FB13_17 STD RESET
DQ_DATA<12> 13 13 FB13_18 STD RESET
AUTO_CONFIG_Z2_DONE_CYCLE<1> 4 15 FB14_1 STD RESET
CP_RD_S 3 5 FB14_2 STD RESET
SHUT_UP_Z2<0> 4 15 FB14_4 STD SET
AUTO_CONFIG_Z2_DONE_CYCLE<0> 4 14 FB14_5 STD RESET
AUTO_CONFIG_Z2_DONE<1> 4 5 FB14_6 STD RESET
AUTO_CONFIG_Z2_DONE<0> 4 5 FB14_7 STD RESET
D_Z2_OUT<3> 14 14 FB14_10 STD SET
D_Z2_OUT<2> 16 14 FB14_12 STD SET
D_Z2_OUT<1> 17 14 FB14_16 STD SET
CP_WE_S 3 5 FB14_18 STD RESET
DQ_DATA<6> 13 13 FB15_1 STD RESET
DQ_DATA<7> 13 13 FB15_2 STD RESET
DQ_DATA<1> 13 13 FB15_7 STD RESET
Signal Total Total Loc Pwr Reg Init
Name Pts Inps Mode State
DQ_DATA<14> 13 13 FB15_8 STD RESET
DQ_DATA<15> 13 13 FB15_10 STD RESET
Z3_DATA<26> 4 7 FB16_5 STD RESET
Z3_DATA<25> 4 7 FB16_7 STD RESET
Z3_DATA<24> 4 7 FB16_9 STD RESET
Z3_DATA<18> 4 7 FB16_12 STD RESET
Z3_DATA<17> 4 7 FB16_13 STD RESET
Z3_DATA<16> 4 7 FB16_14 STD RESET
DQ_DATA<10> 13 13 FB16_16 STD RESET
DQ_DATA<2> 13 13 FB16_17 STD RESET
** 24 Inputs **
Signal Loc Pin Pin Pin
Name No. Type Use
CLK_EXT FB3_10 30 GCK/I/O GCK
CP_IRQ FB3_12 31 I/O I
RESET FB6_15 143 GSR/I/O I
A<5> FB7_15 49 I/O I
A<4> FB9_2 50 I/O I
A<6> FB9_3 51 I/O I
A<3> FB9_5 52 I/O I
A<7> FB9_6 53 I/O I
A<2> FB9_8 54 I/O I
A<1> FB9_12 57 I/O I
LAN_INT FB12_3 111 I/O I
AUTOBOOT_OFF FB13_11 75 I/O I
FCS FB13_15 77 I/O I
DS1 FB13_17 78 I/O I
C3 FB14_6 102 I/O I
C1 FB14_8 103 I/O I
CFIN FB14_10 104 I/O I
Z3 FB15_2 79 I/O I
AS FB15_3 80 I/O I
UDS FB15_8 81 I/O I
LDS FB15_10 82 I/O I
RW FB15_11 83 I/O I
DS0 FB16_5 93 I/O I
BERR FB16_12 98 I/O I
Legend:
Pin No. - ~ - User Assigned
************************** Function Block Details ************************
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X - Signal used as input to the macrocell logic.
Pin No. - ~ - User Assigned
*********************************** FB1 ***********************************
Number of function block inputs used/remaining: 41/13
Number of signals used by logic mapping into function block: 41
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB1_1 (b)
AUTO_CONFIG_Z2_DONE_CYCLE<2>
4 0 0 1 FB1_2 (b) (b)
AUTO_CONFIG_Z2_DONE<2>
4 0 \/1 0 FB1_3 (b) (b)
IDE_BASEADR<7> 6 1<- 0 0 FB1_4 (b) (b)
D<5> 2 0 0 3 FB1_5 20 I/O I/O
D<4> 2 0 \/1 2 FB1_6 21 I/O I/O
CP_BASEADR<7> 6 1<- 0 0 FB1_7 (b) (b)
IDE_CS<0> 1 0 \/1 3 FB1_8 22 I/O O
CP_BASEADR<4> 6 1<- 0 0 FB1_9 (b) (b)
IDE_CS<1> 1 0 \/1 3 FB1_10 23 I/O O
CP_BASEADR<3> 6 1<- 0 0 FB1_11 (b) (b)
IDE_A<0> 1 0 \/1 3 FB1_12 24 I/O O
CP_BASEADR<2> 6 1<- 0 0 FB1_13 (b) (b)
IDE_A<2> 1 0 0 4 FB1_14 25 I/O O
IDE_A<1> 1 0 \/1 3 FB1_15 26 I/O O
CP_BASEADR<1> 6 1<- 0 0 FB1_16 (b) (b)
IDE_R 1 0 \/1 3 FB1_17 27 I/O O
CP_BASEADR<0> 6 1<- 0 0 FB1_18 (b) (b)
Signals Used by Logic in Function Block
1: AS 15: CP_BASEADR<2> 29: A<13>.PIN
2: AUTOCONFIG_Z2_ACCESS 16: CP_BASEADR<3> 30: D<15>.PIN
3: AUTO_CONFIG_Z2_DONE<0> 17: CP_BASEADR<4> 31: D<12>.PIN
4: AUTO_CONFIG_Z2_DONE<1> 18: CP_BASEADR<7> 32: D<11>.PIN
5: AUTO_CONFIG_Z2_DONE<2> 19: D_5_IOBUFE/D_5_IOBUFE_TRST 33: D<10>.PIN
6: AUTO_CONFIG_Z2_DONE_CYCLE<2> 20: FCS 34: D<9>.PIN
7: A<1> 21: A<9>.PIN 35: D<8>.PIN
8: A<2> 22: A<10>.PIN 36: RESET
9: A<3> 23: A<11>.PIN 37: RW
10: A<4> 24: IDE_BASEADR<7> 38: SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF
11: A<5> 25: IDE_R_S 39: UDS
12: A<6> 26: LAN_ACCESS 40: Z3_DATA<20>
13: CP_BASEADR<0> 27: LDS 41: Z3_DATA<21>
14: CP_BASEADR<1> 28: A<12>.PIN
Signal 1 2 3 4 5 FB
Name 0----+----0----+----0----+----0----+----0----+----0 Inputs
AUTO_CONFIG_Z2_DONE_CYCLE<2>
XXXXXXX.XXXX..............X........XXXX........... 16
AUTO_CONFIG_Z2_DONE<2>
X...XX.............................X.X............ 5
IDE_BASEADR<7> XXXXX.XXXXXX...........X..X..X.....XXXX........... 18
D<5> ..................XX.....X..........X...X......... 5
D<4> ..................XX.....X..........X..X.......... 5
CP_BASEADR<7> XXXX..XXXXXX.....X........X..X.....XXXX........... 17
IDE_CS<0> ...........................X...................... 1
CP_BASEADR<4> XXXX..XXXXXX....X.........X...X....XXXX........... 17
IDE_CS<1> ............................X..................... 1
CP_BASEADR<3> XXXX..XXXXXX...X..........X....X...XXXX........... 17
IDE_A<0> ....................X............................. 1
CP_BASEADR<2> XXXX..XXXXXX..X...........X.....X..XXXX........... 17
IDE_A<2> ......................X........................... 1
IDE_A<1> .....................X............................ 1
CP_BASEADR<1> XXXX..XXXXXX.X............X......X.XXXX........... 17
IDE_R X.......................X......................... 2
CP_BASEADR<0> XXXX..XXXXXXX.............X.......XXXXX........... 17
0----+----1----+----2----+----3----+----4----+----5
0 0 0 0 0
*********************************** FB2 ***********************************
Number of function block inputs used/remaining: 42/12
Number of signals used by logic mapping into function block: 42
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
D_5_IOBUFE/D_5_IOBUFE_TRST
2 0 0 3 FB2_1 (b) (b)
A_LAN<4> 1 0 0 4 FB2_2 9 I/O O
A_LAN<7> 1 0 \/1 3 FB2_3 10 I/O O
IDE_BASEADR<6> 6 1<- 0 0 FB2_4 (b) (b)
A_LAN<6> 2 0 0 3 FB2_5 11 I/O O
LAN_CFG<1> 0 0 \/1 4 FB2_6 12 I/O O
IDE_BASEADR<5> 6 1<- 0 0 FB2_7 (b) (b)
LAN_CFG<3> 0 0 \/1 4 FB2_8 13 I/O O
IDE_BASEADR<4> 6 1<- 0 0 FB2_9 (b) (b)
D<6> 2 0 \/1 2 FB2_10 14 I/O I/O
IDE_BASEADR<3> 6 1<- 0 0 FB2_11 (b) (b)
D<3> 2 0 \/1 2 FB2_12 15 I/O I/O
IDE_BASEADR<2> 6 1<- 0 0 FB2_13 (b) (b)
D<7> 2 0 0 3 FB2_14 16 I/O I/O
D<1> 2 0 \/1 2 FB2_15 17 I/O I/O
IDE_BASEADR<1> 6 1<- 0 0 FB2_16 (b) (b)
D<8> 2 0 \/1 2 FB2_17 19 I/O I/O
IDE_BASEADR<0> 6 1<- 0 0 FB2_18 (b) (b)
Signals Used by Logic in Function Block
1: AS 15: IDE_BASEADR<1> 29: D<9>.PIN
2: AUTOCONFIG_Z2_ACCESS 16: IDE_BASEADR<2> 30: D<8>.PIN
3: AUTO_CONFIG_Z2_DONE<0> 17: IDE_BASEADR<3> 31: RESET
4: AUTO_CONFIG_Z2_DONE<1> 18: IDE_BASEADR<4> 32: RW
5: AUTO_CONFIG_Z2_DONE<2> 19: IDE_BASEADR<5> 33: SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF
6: A<1> 20: IDE_BASEADR<6> 34: UDS
7: A<2> 21: LAN_ACCESS 35: Z3_ADR<3>
8: A<3> 22: LAN_A_INIT<6> 36: Z3_ADR<5>
9: A<4> 23: LDS 37: Z3_ADR<6>
10: A<5> 24: D<14>.PIN 38: Z3_DATA<17>
11: A<6> 25: D<13>.PIN 39: Z3_DATA<19>
12: D_5_IOBUFE/D_5_IOBUFE_TRST 26: D<12>.PIN 40: Z3_DATA<22>
13: FCS 27: D<11>.PIN 41: Z3_DATA<23>
14: IDE_BASEADR<0> 28: D<10>.PIN 42: Z3_DATA<24>
Signal 1 2 3 4 5 FB
Name 0----+----0----+----0----+----0----+----0----+----0 Inputs
D_5_IOBUFE/D_5_IOBUFE_TRST
XX..........X.......X..........X.................. 5
A_LAN<4> ..............................X...X............... 2
A_LAN<7> ..............................X.....X............. 2
IDE_BASEADR<6> XXXXXXXXXXX........X..XX......XXXX................ 18
A_LAN<6> .....................X........X....X.............. 3
LAN_CFG<1> .................................................. 0
IDE_BASEADR<5> XXXXXXXXXXX.......X...X.X.....XXXX................ 18
LAN_CFG<3> .................................................. 0
IDE_BASEADR<4> XXXXXXXXXXX......X....X..X....XXXX................ 18
D<6> ...........XX.......X..........X.......X.......... 5
IDE_BASEADR<3> XXXXXXXXXXX.....X.....X...X...XXXX................ 18
D<3> ...........XX.......X..........X......X........... 5
IDE_BASEADR<2> XXXXXXXXXXX....X......X....X..XXXX................ 18
D<7> ...........XX.......X..........X........X......... 5
D<1> ...........XX.......X..........X.....X............ 5
IDE_BASEADR<1> XXXXXXXXXXX...X.......X.....X.XXXX................ 18
D<8> ...........XX.......X..........X.........X........ 5
IDE_BASEADR<0> XXXXXXXXXXX..X........X......XXXXX................ 18
0----+----1----+----2----+----3----+----4----+----5
0 0 0 0 0
*********************************** FB3 ***********************************
Number of function block inputs used/remaining: 13/41
Number of signals used by logic mapping into function block: 13
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB3_1 (b)
IDE_W 1 0 0 4 FB3_2 28 I/O O
(unused) 0 0 0 5 FB3_3 (b)
(unused) 0 0 0 5 FB3_4 (b)
(unused) 0 0 0 5 FB3_5 (b)
(unused) 0 0 0 5 FB3_6 (b)
(unused) 0 0 0 5 FB3_7 (b)
(unused) 0 0 0 5 FB3_8 (b)
(unused) 0 0 0 5 FB3_9 (b)
(unused) 0 0 0 5 FB3_10 30 GCK/I/O GCK
(unused) 0 0 0 5 FB3_11 (b)
(unused) 0 0 0 5 FB3_12 31 I/O I
(unused) 0 0 0 5 FB3_13 (b)
INT_OUT 1 0 0 4 FB3_14 32 GCK/I/O O
SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF
2 0 0 3 FB3_15 33 I/O (b)
ROM_B_0_OBUF$BUF9/ROM_B_0_OBUF$BUF9_TRST
2 0 0 3 FB3_16 (b) (b)
ROM_B_0_OBUF$BUF8/ROM_B_0_OBUF$BUF8_TRST
2 0 0 3 FB3_17 (b) (b)
CP_WE_QUIRK 2 0 0 3 FB3_18 (b) (b)
Signals Used by Logic in Function Block
1: AS 6: CP_WE_S 10: LAN_IRQ_OUT
2: C1 7: FCS 11: LAN_READY
3: C3 8: IDE_W_S 12: ROM_B_0_OBUF$BUF8/ROM_B_0_OBUF$BUF8_TRST
4: CONFIG_READY 9: LAN_INT_ENABLE 13: SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF
5: CP_IRQ
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
IDE_W X......X................................ 2
INT_OUT ...........X............................ 1
SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF
.XX..................................... 2
ROM_B_0_OBUF$BUF9/ROM_B_0_OBUF$BUF9_TRST
...X..X...X............................. 3
ROM_B_0_OBUF$BUF8/ROM_B_0_OBUF$BUF8_TRST
....X...XX.............................. 3
CP_WE_QUIRK .....X......X........................... 2
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB4 ***********************************
Number of function block inputs used/remaining: 37/17
Number of signals used by logic mapping into function block: 37
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
IDE_ENABLE 3 0 0 2 FB4_1 (b) (b)
D<0> 2 0 0 3 FB4_2 2 GTS/I/O I/O
Z3_ADR<12> 3 0 0 2 FB4_3 (b) (b)
Z3_ADR<11> 3 0 0 2 FB4_4 (b) (b)
A_LAN<1> 1 0 0 4 FB4_5 3 GTS/I/O O
A_LAN<0> 1 0 0 4 FB4_6 4 I/O O
ROM_OE_S 3 0 0 2 FB4_7 (b) (b)
A_LAN<3> 2 0 \/3 0 FB4_8 5 GTS/I/O O
(unused) 0 0 \/5 0 FB4_9 (b) (b)
LAN_ACCESS 21 16<- 0 0 FB4_10 (b) (b)
(unused) 0 0 /\5 0 FB4_11 (b) (b)
A_LAN<2> 1 0 /\3 1 FB4_12 6 GTS/I/O O
IDE_R_S 3 0 0 2 FB4_13 (b) (b)
A_LAN<5> 1 0 \/3 1 FB4_14 7 I/O O
(unused) 0 0 \/5 0 FB4_15 (b) (b)
DQ_SWAP 23 18<- 0 0 FB4_16 (b) (b)
(unused) 0 0 /\5 0 FB4_17 (b) (b)
(unused) 0 0 /\5 0 FB4_18 (b) (b)
Signals Used by Logic in Function Block
1: $OpTx$INV$129 14: LAN_BASEADR<6> 26: A<22>.PIN
2: AS 15: LAN_BASEADR<8> 27: RESET
3: D_5_IOBUFE/D_5_IOBUFE_TRST 16: LAN_BASEADR<9> 28: RW
4: FCS 17: A<13>.PIN 29: SHUT_UP_Z2<0>
5: IDE_ACCESS 18: D<15>.PIN 30: SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF
6: IDE_ENABLE 19: D<13>.PIN 31: Z3_ADR<2>
7: LAN_ACCESS 20: D<12>.PIN 32: Z3_ADR<4>
8: LAN_A_INIT<3> 21: D<11>.PIN 33: Z3_ADR_0
9: LAN_BASEADR<10> 22: D<10>.PIN 34: Z3_ADR_1
10: LAN_BASEADR<11> 23: D<9>.PIN 35: Z3_A_LOW
11: LAN_BASEADR<12> 24: D<8>.PIN 36: Z3_DATA<16>
12: LAN_BASEADR<13> 25: A<14>.PIN 37: Z3
13: LAN_BASEADR<15>
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
IDE_ENABLE .X..X.....................XX.X.......... 5
D<0> ..XX..X....................X.......X.... 5
Z3_ADR<12> ...X....................X.X............. 3
Z3_ADR<11> ...X............X.........X............. 3
A_LAN<1> ..........................X.....X....... 2
A_LAN<0> ..........................X.......X..... 2
ROM_OE_S .X..XX....................XX.X.......... 6
A_LAN<3> .......X..................X...X......... 3
LAN_ACCESS X..X....XXXXXXXX.XXXXXXX.XX.X.......X... 21
A_LAN<2> ..........................X......X...... 2
IDE_R_S .X..XX....................XX.X.......... 6
A_LAN<5> ..........................X....X........ 2
DQ_SWAP X..X....XXXXXXXXXXXXXXXXXXX.X.......X... 23
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB5 ***********************************
Number of function block inputs used/remaining: 41/13
Number of signals used by logic mapping into function block: 41
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 \/5 0 FB5_1 (b) (b)
CP_CS 19 14<- 0 0 FB5_2 34 I/O O
(unused) 0 0 /\5 0 FB5_3 (b) (b)
(unused) 0 0 /\4 1 FB5_4 (b) (b)
ROM_OE 1 0 0 4 FB5_5 35 I/O O
(unused) 0 0 0 5 FB5_6 (b)
(unused) 0 0 0 5 FB5_7 (b)
(unused) 0 0 0 5 FB5_8 38 GCK/I/O
LAN_A_INIT<3> 1 0 0 4 FB5_9 (b) (b)
D<2> 2 0 0 3 FB5_10 39 I/O I/O
LAN_IRQ_D0 2 0 0 3 FB5_11 (b) (b)
D<9> 2 0 0 3 FB5_12 40 I/O I/O
CONFIG_READY 2 0 0 3 FB5_13 (b) (b)
D<10> 2 0 0 3 FB5_14 41 I/O I/O
D<11> 2 0 0 3 FB5_15 43 I/O I/O
LAN_INT_ENABLE 5 0 0 0 FB5_16 (b) (b)
D<12> 5 0 0 0 FB5_17 44 I/O I/O
AUTOCONFIG_Z2_ACCESS
5 0 0 0 FB5_18 (b) (b)
Signals Used by Logic in Function Block
1: AS 15: D_5_IOBUFE/D_5_IOBUFE_TRST 29: A<16>.PIN
2: AUTOBOOT_OFF 16: D_Z2_OUT<0> 30: A<22>.PIN
3: AUTO_CONFIG_Z2_DONE<0> 17: FCS 31: RESET
4: AUTO_CONFIG_Z2_DONE<1> 18: LAN_ACCESS 32: ROM_OE_S
5: AUTO_CONFIG_Z2_DONE<2> 19: LAN_INT_ENABLE 33: RW
6: CFIN 20: LAN_INT 34: SHUT_UP_Z2<0>
7: CP_BASEADR<0> 21: LDS 35: UDS
8: CP_BASEADR<1> 22: A<17>.PIN 36: Z3_ADR<13>
9: CP_BASEADR<2> 23: A<23>.PIN 37: Z3_DATA<18>
10: CP_BASEADR<3> 24: A<18>.PIN 38: Z3_DATA<25>
11: CP_BASEADR<4> 25: A<19>.PIN 39: Z3_DATA<26>
12: CP_BASEADR<5> 26: D<15>.PIN 40: Z3_DATA<27>
13: CP_BASEADR<6> 27: A<20>.PIN 41: Z3_DATA<28>
14: CP_BASEADR<7> 28: A<21>.PIN
Signal 1 2 3 4 5 FB
Name 0----+----0----+----0----+----0----+----0----+----0 Inputs
CP_CS X.....XXXXXXXX.......XXXX.XXXXX..X................ 19
ROM_OE XX.............................X.................. 3
LAN_A_INIT<3> ..............................X................... 1
D<2> ..............X.XX..............X...X............. 5
LAN_IRQ_D0 ...................X..........X................... 2
D<9> ..............X.XX..............X....X............ 5
CONFIG_READY ................XX............X....X.............. 4
D<10> ..............X.XX..............X.....X........... 5
D<11> ..............X.XX..............X......X.......... 5
LAN_INT_ENABLE ................XXX.X.X..X....X.X.XX.............. 10
D<12> ..............XXXX..............X.......X......... 6
AUTOCONFIG_Z2_ACCESS
X.XXXX...............XXXX.XXXXX................... 14
0----+----1----+----2----+----3----+----4----+----5
0 0 0 0 0
*********************************** FB6 ***********************************
Number of function block inputs used/remaining: 23/31
Number of signals used by logic mapping into function block: 23
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
Z3_ADR_1 3 0 0 2 FB6_1 (b) (b)
LAN_CFG<2> 0 0 0 5 FB6_2 135 I/O O
A_LAN<12> 1 0 0 4 FB6_3 136 I/O O
Z3_ADR_0 3 0 0 2 FB6_4 (b) (b)
A_LAN<13> 1 0 0 4 FB6_5 137 I/O O
A_LAN<10> 1 0 0 4 FB6_6 138 I/O O
Z3_ADR<9> 3 0 0 2 FB6_7 (b) (b)
A_LAN<11> 1 0 0 4 FB6_8 139 I/O O
Z3_ADR<8> 3 0 0 2 FB6_9 (b) (b)
A_LAN<8> 1 0 0 4 FB6_10 140 I/O O
Z3_ADR<7> 3 0 0 2 FB6_11 (b) (b)
Z3_ADR<6> 3 0 0 2 FB6_12 (b) (b)
Z3_ADR<5> 3 0 0 2 FB6_13 (b) (b)
A_LAN<9> 1 0 0 4 FB6_14 142 I/O O
Z3_ADR<4> 3 0 0 2 FB6_15 143 GSR/I/O I
Z3_ADR<3> 3 0 0 2 FB6_16 (b) (b)
LAN_WR_RST 3 0 0 2 FB6_17 (b) (b)
LAN_IRQ_OUT 3 0 0 2 FB6_18 (b) (b)
Signals Used by Logic in Function Block
1: A<2> 9: A<11>.PIN 17: RESET
2: A<3> 10: LAN_INT 18: Z3_ADR<10>
3: A<5> 11: LAN_IRQ_D0 19: Z3_ADR<11>
4: A<6> 12: LAN_IRQ_OUT 20: Z3_ADR<12>
5: A<7> 13: LAN_RST_SM_FSM_FFd1 21: Z3_ADR<7>
6: FCS 14: LAN_RST_SM_FSM_FFd2 22: Z3_ADR<8>
7: A<9>.PIN 15: LAN_RST_SM_FSM_FFd3 23: Z3_ADR<9>
8: A<10>.PIN 16: A<8>.PIN
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
Z3_ADR_1 .X...X..........X....................... 3
LAN_CFG<2> ........................................ 0
A_LAN<12> ................X.X..................... 2
Z3_ADR_0 X....X..........X....................... 3
A_LAN<13> ................X..X.................... 2
A_LAN<10> ................X.....X................. 2
Z3_ADR<9> .....X..X.......X....................... 3
A_LAN<11> ................XX...................... 2
Z3_ADR<8> .....X.X........X....................... 3
A_LAN<8> ................X...X................... 2
Z3_ADR<7> .....XX.........X....................... 3
Z3_ADR<6> .....X.........XX....................... 3
Z3_ADR<5> ....XX..........X....................... 3
A_LAN<9> ................X....X.................. 2
Z3_ADR<4> ...X.X..........X....................... 3
Z3_ADR<3> ..X..X..........X....................... 3
LAN_WR_RST ............XXX.X....................... 4
LAN_IRQ_OUT .........XXX....X....................... 4
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB7 ***********************************
Number of function block inputs used/remaining: 41/13
Number of signals used by logic mapping into function block: 41
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
CP_BASEADR<5> 6 1<- 0 0 FB7_1 (b) (b)
SHUT_UP_Z2<1> 4 0 \/1 0 FB7_2 (b) (b)
D<13> 5 1<- \/1 0 FB7_3 45 I/O I/O
LAN_BASEADR<6> 6 1<- 0 0 FB7_4 (b) (b)
D<14> 5 0 0 0 FB7_5 46 I/O I/O
(unused) 0 0 \/3 2 FB7_6 (b) (b)
LAN_BASEADR<5> 6 3<- \/2 0 FB7_7 (b) (b)
LAN_BASEADR<2> 6 2<- \/1 0 FB7_8 (b) (b)
LAN_BASEADR<14> 6 1<- 0 0 FB7_9 (b) (b)
LAN_BASEADR<13> 6 1<- 0 0 FB7_10 (b) (b)
LAN_BASEADR<11> 6 2<- /\1 0 FB7_11 (b) (b)
D<15> 5 2<- /\2 0 FB7_12 48 I/O I/O
LAN_BASEADR<10> 6 3<- /\2 0 FB7_13 (b) (b)
(unused) 0 0 /\3 2 FB7_14 (b) (b)
(unused) 0 0 \/4 1 FB7_15 49 I/O I
LAN_BASEADR<8> 6 4<- \/3 0 FB7_16 (b) (b)
LAN_BASEADR<0> 6 3<- \/2 0 FB7_17 (b) (b)
CP_BASEADR<6> 6 2<- \/1 0 FB7_18 (b) (b)
Signals Used by Logic in Function Block
1: AS 15: D_Z2_OUT<2> 29: D<14>.PIN
2: AUTOCONFIG_Z2_ACCESS 16: D_Z2_OUT<3> 30: D<13>.PIN
3: AUTO_CONFIG_Z2_DONE<0> 17: FCS 31: D<11>.PIN
4: AUTO_CONFIG_Z2_DONE<1> 18: LAN_ACCESS 32: D<10>.PIN
5: A<1> 19: LAN_BASEADR<0> 33: D<8>.PIN
6: A<2> 20: LAN_BASEADR<10> 34: RESET
7: A<3> 21: LAN_BASEADR<11> 35: RW
8: A<4> 22: LAN_BASEADR<13> 36: SHUT_UP_Z2<1>
9: A<5> 23: LAN_BASEADR<14> 37: SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF
10: A<6> 24: LAN_BASEADR<2> 38: UDS
11: CP_BASEADR<5> 25: LAN_BASEADR<5> 39: Z3_DATA<29>
12: CP_BASEADR<6> 26: LAN_BASEADR<6> 40: Z3_DATA<30>
13: D_5_IOBUFE/D_5_IOBUFE_TRST 27: LAN_BASEADR<8> 41: Z3_DATA<31>
14: D_Z2_OUT<1> 28: LDS
Signal 1 2 3 4 5 FB
Name 0----+----0----+----0----+----0----+----0----+----0 Inputs
CP_BASEADR<5> XXXXXXXXXXX................X.X...XX.XX............ 17
SHUT_UP_Z2<1> XXXXXXXXXX.................X.....XXXXX............ 16
D<13> ............XX..XX................X...X........... 6
LAN_BASEADR<6> XXX.XXXXXX...............X.XX....XX.XX............ 16
D<14> ............X.X.XX................X....X.......... 6
LAN_BASEADR<5> XXX.XXXXXX..............X..X.X...XX.XX............ 16
LAN_BASEADR<2> XXX.XXXXXX.............X...X...X.XX.XX............ 16
LAN_BASEADR<14> XX.XXXXXXX............X....XX....XX.XX............ 16
LAN_BASEADR<13> XX.XXXXXXX...........X.....X.X...XX.XX............ 16
LAN_BASEADR<11> XX.XXXXXXX..........X......X..X..XX.XX............ 16
D<15> ............X..XXX................X.....X......... 6
LAN_BASEADR<10> XX.XXXXXXX.........X.......X...X.XX.XX............ 16
LAN_BASEADR<8> XX.XXXXXXX................XX....XXX.XX............ 16
LAN_BASEADR<0> XXX.XXXXXX........X........X....XXX.XX............ 16
CP_BASEADR<6> XXXXXXXXXX.X...............XX....XX.XX............ 17
0----+----1----+----2----+----3----+----4----+----5
0 0 0 0 0
*********************************** FB8 ***********************************
Number of function block inputs used/remaining: 38/16
Number of signals used by logic mapping into function block: 38
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
Z3_ADR<2> 3 0 /\2 0 FB8_1 (b) (b)
DQ<12> 2 0 0 3 FB8_2 130 I/O I/O
DQ<14> 2 0 \/1 2 FB8_3 131 I/O I/O
LAN_BASEADR<12> 6 1<- 0 0 FB8_4 (b) (b)
LAN_WRH 3 0 \/2 0 FB8_5 132 I/O O
LAN_BASEADR<15> 6 2<- \/1 0 FB8_6 (b) (b)
LAN_BASEADR<1> 6 1<- 0 0 FB8_7 (b) (b)
LAN_CS 2 0 \/1 2 FB8_8 133 I/O O
LAN_BASEADR<3> 6 1<- 0 0 FB8_9 (b) (b)
LAN_RD 1 0 \/1 3 FB8_10 134 I/O O
LAN_BASEADR<4> 6 1<- 0 0 FB8_11 (b) (b)
LAN_BASEADR<7> 6 1<- 0 0 FB8_12 (b) (b)
LAN_BASEADR<9> 6 2<- /\1 0 FB8_13 (b) (b)
Z3_ADR<10> 3 0 /\2 0 FB8_14 (b) (b)
Z3_ADR<13> 3 0 \/1 1 FB8_15 (b) (b)
(unused) 0 0 \/5 0 FB8_16 (b) (b)
D_Z2_OUT<0> 18 13<- 0 0 FB8_17 (b) (b)
(unused) 0 0 /\5 0 FB8_18 (b) (b)
Signals Used by Logic in Function Block
1: AS 14: DQ_DATA<14> 27: LAN_WR_RST
2: AUTOCONFIG_Z2_ACCESS 15: FCS 28: LDS
3: AUTO_CONFIG_Z2_DONE<0> 16: LAN_ACCESS 29: A<12>.PIN
4: AUTO_CONFIG_Z2_DONE<1> 17: LAN_BASEADR<12> 30: D<15>.PIN
5: AUTO_CONFIG_Z2_DONE<2> 18: LAN_BASEADR<15> 31: D<12>.PIN
6: A<1> 19: LAN_BASEADR<1> 32: D<11>.PIN
7: A<2> 20: LAN_BASEADR<3> 33: D<9>.PIN
8: A<3> 21: LAN_BASEADR<4> 34: A<15>.PIN
9: A<4> 22: LAN_BASEADR<7> 35: RESET
10: A<5> 23: LAN_BASEADR<9> 36: RW
11: A<6> 24: LAN_CS_RST 37: SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF
12: DQ_12_IOBUFE/DQ_12_IOBUFE_TRST__$INT 25: LAN_RD_S 38: UDS
13: DQ_DATA<12> 26: LAN_WRH_S
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
Z3_ADR<2> ........X.....X...................X..... 3
DQ<12> ...........XX.....................X..... 3
DQ<14> ...........X.X....................X..... 3
LAN_BASEADR<12> XX.X.XXXXXX.....X..........X..X...XXXX.. 16
LAN_WRH ..............X..........XX.......X..... 4
LAN_BASEADR<15> XX.X.XXXXXX......X.........X.X....XXXX.. 16
LAN_BASEADR<1> XXX..XXXXXX.......X........X....X.XXXX.. 16
LAN_CS ...............X.......X..........X..... 3
LAN_BASEADR<3> XXX..XXXXXX........X.......X...X..XXXX.. 16
LAN_RD ..............X.........X.........X..... 3
LAN_BASEADR<4> XXX..XXXXXX.........X......X..X...XXXX.. 16
LAN_BASEADR<7> XXX..XXXXXX..........X.....X.X....XXXX.. 16
LAN_BASEADR<9> XX.X.XXXXXX...........X....X....X.XXXX.. 16
Z3_ADR<10> ..............X.............X.....X..... 3
Z3_ADR<13> ..............X..................XX..... 3
D_Z2_OUT<0> XXXXXXXXXXX................X......X.XX.. 15
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB9 ***********************************
Number of function block inputs used/remaining: 32/22
Number of signals used by logic mapping into function block: 32
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 /\5 0 FB9_1 (b) (b)
LAN_WRL_S 3 2<- /\4 0 FB9_2 50 I/O I
LAN_WRH_S 3 0 /\2 0 FB9_3 51 I/O I
LAN_SM_RST 4 0 0 1 FB9_4 (b) (b)
LAN_SM_FSM_FFd4 4 0 \/1 0 FB9_5 52 I/O I
LAN_RD_S 4 1<- \/2 0 FB9_6 53 I/O I
DQ_12_IOBUFE/DQ_12_IOBUFE_TRST__$INT
4 2<- \/3 0 FB9_7 (b) (b)
LAN_READY 5 3<- \/3 0 FB9_8 54 I/O I
LAN_SM_FSM_FFd2 6 3<- \/2 0 FB9_9 (b) (b)
Z3_A_LOW 7 2<- 0 0 FB9_10 (b) (b)
A<8> 5 0 0 0 FB9_11 56 I/O I/O
(unused) 0 0 \/5 0 FB9_12 57 I/O I
LAN_SM_FSM_FFd1 8 5<- \/2 0 FB9_13 (b) (b)
A<9> 5 2<- \/2 0 FB9_14 58 I/O I/O
DQ_DATA<9> 13 8<- 0 0 FB9_15 (b) (b)
(unused) 0 0 /\5 0 FB9_16 (b) (b)
A<10> 5 1<- /\1 0 FB9_17 59 I/O I/O
DQ_DATA<5> 13 9<- /\1 0 FB9_18 (b) (b)
Signals Used by Logic in Function Block
1: BERR 12: LAN_SM_FSM_FFd3 23: DQ<0>.PIN
2: DQ_DATA<5> 13: LAN_SM_FSM_FFd4 24: D<13>.PIN
3: DQ_DATA<9> 14: LAN_SM_RST 25: D<9>.PIN
4: DQ_SWAP 15: LDS 26: D<5>.PIN
5: DS0 16: A<17>.PIN 27: D<1>.PIN
6: DS1 17: DQ<10>.PIN 28: A<21>.PIN
7: FCS 18: DQ<9>.PIN 29: RESET
8: A<9>.PIN 19: DQ<8>.PIN 30: RW
9: LAN_ACCESS 20: DQ<2>.PIN 31: UDS
10: LAN_SM_FSM_FFd1 21: A<13>.PIN 32: Z3_ADR<13>
11: LAN_SM_FSM_FFd2 22: DQ<1>.PIN
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
LAN_WRL_S .....X...XXXXX................X......... 7
LAN_WRH_S ....X....XXXXXX......................... 7
LAN_SM_RST X...XXX.X.....X.............X.XX........ 9
LAN_SM_FSM_FFd4 ....XX...XXXXX.......................... 7
LAN_RD_S .........XXXXX...............X.......... 6
DQ_12_IOBUFE/DQ_12_IOBUFE_TRST__$INT
....XXX.X.....X.............XXX......... 8
LAN_READY ....XX...XXXXX.......................... 7
LAN_SM_FSM_FFd2 ....XX...XXXXXX...............X......... 9
Z3_A_LOW ....XX...XXXXXX...............X......... 9
A<8> ...X..X.XXXXXX....X...X......X.......... 11
LAN_SM_FSM_FFd1 ....XX...XXXXX...............X.......... 8
A<9> ...X..X.XXXXXX...X...X.......X.......... 11
DQ_DATA<9> ..XX...X.XXXXXXX........X.X...X......... 13
A<10> ...X..X.XXXXXX..X..X.........X.......... 11
DQ_DATA<5> .X.X.....XXXXXX.....X..X.X.X..X......... 13
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB10 ***********************************
Number of function block inputs used/remaining: 14/40
Number of signals used by logic mapping into function block: 14
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB10_1 (b)
DQ<1> 3 0 0 2 FB10_2 117 I/O I/O
DQ<0> 2 0 0 3 FB10_3 118 I/O I/O
(unused) 0 0 0 5 FB10_4 (b)
DQ<3> 2 0 0 3 FB10_5 119 I/O I/O
DQ<2> 2 0 0 3 FB10_6 120 I/O I/O
(unused) 0 0 0 5 FB10_7 (b)
DQ<5> 2 0 0 3 FB10_8 121 I/O I/O
(unused) 0 0 0 5 FB10_9 (b)
DQ<4> 3 0 0 2 FB10_10 124 I/O I/O
DQ<7> 2 0 0 3 FB10_11 125 I/O I/O
DQ<6> 2 0 0 3 FB10_12 126 I/O I/O
(unused) 0 0 0 5 FB10_13 (b)
DQ<8> 3 0 0 2 FB10_14 128 I/O I/O
(unused) 0 0 0 5 FB10_15 (b)
(unused) 0 0 0 5 FB10_16 (b)
DQ<10> 3 0 0 2 FB10_17 129 I/O I/O
(unused) 0 0 0 5 FB10_18 (b)
Signals Used by Logic in Function Block
1: DQ_12_IOBUFE/DQ_12_IOBUFE_TRST__$INT 6: DQ_DATA<3> 11: DQ_DATA<8>
2: DQ_DATA<0> 7: DQ_DATA<4> 12: LAN_D_INIT<1>
3: DQ_DATA<10> 8: DQ_DATA<5> 13: LAN_D_INIT<8>
4: DQ_DATA<1> 9: DQ_DATA<6> 14: RESET
5: DQ_DATA<2> 10: DQ_DATA<7>
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
DQ<1> X..X.......X.X.......................... 4
DQ<0> XX...........X.......................... 3
DQ<3> X....X.......X.......................... 3
DQ<2> X...X........X.......................... 3
DQ<5> X......X.....X.......................... 3
DQ<4> X.....X....X.X.......................... 4
DQ<7> X........X...X.......................... 3
DQ<6> X.......X....X.......................... 3
DQ<8> X.........X.XX.......................... 4
DQ<10> X.X.........XX.......................... 4
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB11 ***********************************
Number of function block inputs used/remaining: 28/26
Number of signals used by logic mapping into function block: 28
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
Z3_DATA<30> 4 2<- /\3 0 FB11_1 (b) (b)
Z3_DATA<29> 4 1<- /\2 0 FB11_2 (b) (b)
A<11> 5 1<- /\1 0 FB11_3 60 I/O I/O
Z3_DATA<28> 4 0 /\1 0 FB11_4 (b) (b)
A<12> 5 0 0 0 FB11_5 61 I/O I/O
Z3_DATA<27> 4 0 0 1 FB11_6 (b) (b)
Z3_DATA<22> 4 0 0 1 FB11_7 (b) (b)
Z3_DATA<21> 4 0 0 1 FB11_8 (b) (b)
Z3_DATA<20> 4 0 0 1 FB11_9 (b) (b)
A<13> 5 0 0 0 FB11_10 64 I/O I/O
A<14> 5 0 0 0 FB11_11 66 I/O I/O
ROM_B<0> 0 0 0 5 FB11_12 68 I/O O
Z3_DATA<19> 4 0 0 1 FB11_13 (b) (b)
ROM_B<1> 0 0 \/4 1 FB11_14 69 I/O O
(unused) 0 0 \/5 0 FB11_15 (b) (b)
DQ_DATA<8> 13 9<- \/1 0 FB11_16 (b) (b)
CP_WE 1 1<- \/5 0 FB11_17 70 I/O O
DQ_DATA<0> 13 8<- 0 0 FB11_18 (b) (b)
Signals Used by Logic in Function Block
1: AS 11: LAN_SM_FSM_FFd3 20: DQ<6>.PIN
2: CP_WE_QUIRK 12: LAN_SM_FSM_FFd4 21: DQ<5>.PIN
3: CP_WE_S 13: LAN_SM_RST 22: DQ<4>.PIN
4: DQ_DATA<0> 14: LDS 23: DQ<3>.PIN
5: DQ_DATA<8> 15: A<8>.PIN 24: D<8>.PIN
6: DQ_SWAP 16: DQ<14>.PIN 25: D<0>.PIN
7: FCS 17: DQ<13>.PIN 26: A<16>.PIN
8: LAN_ACCESS 18: DQ<12>.PIN 27: RW
9: LAN_SM_FSM_FFd1 19: DQ<11>.PIN 28: UDS
10: LAN_SM_FSM_FFd2
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
Z3_DATA<30> .....X..XX.XX..X...X.................... 7
Z3_DATA<29> .....X..XX.XX...X...X................... 7
A<11> .....XXXXXXXX.....X...X...X............. 11
Z3_DATA<28> .....X..XX.XX....X...X.................. 7
A<12> .....XXXXXXXX....X...X....X............. 11
Z3_DATA<27> .....X..XX.XX.....X...X................. 7
Z3_DATA<22> .....X..XX.XX..X...X.................... 7
Z3_DATA<21> .....X..XX.XX...X...X................... 7
Z3_DATA<20> .....X..XX.XX....X...X.................. 7
A<13> .....XXXXXXXX...X...X.....X............. 11
A<14> .....XXXXXXXX..X...X......X............. 11
ROM_B<0> ........................................ 0
Z3_DATA<19> .....X..XX.XX.....X...X................. 7
ROM_B<1> ........................................ 0
DQ_DATA<8> ....XX..XXXXXXX........XXX.X............ 13
CP_WE XXX..................................... 3
DQ_DATA<0> ...X.X..XXXXXXX........XXX.X............ 13
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB12 ***********************************
Number of function block inputs used/remaining: 41/13
Number of signals used by logic mapping into function block: 41
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
LAN_RST_SM_FSM_FFd3 3 0 0 2 FB12_1 (b) (b)
LAN_CFG<4> 0 0 \/4 1 FB12_2 110 I/O O
$OpTx$INV$129 16 11<- 0 0 FB12_3 111 I/O I
(unused) 0 0 /\5 0 FB12_4 (b) (b)
DQ<15> 2 0 /\2 1 FB12_5 112 I/O I/O
IDE_W_S 3 0 0 2 FB12_6 (b) (b)
LAN_A_INIT<6> 3 0 0 2 FB12_7 (b) (b)
DQ<13> 2 0 0 3 FB12_8 113 I/O I/O
LAN_CS_RST 3 0 0 2 FB12_9 (b) (b)
DQ<11> 3 0 0 2 FB12_10 115 I/O I/O
LAN_D_INIT<1> 3 0 0 2 FB12_11 (b) (b)
DQ<9> 3 0 0 2 FB12_12 116 I/O I/O
LAN_D_INIT<8> 3 0 0 2 FB12_13 (b) (b)
LAN_RST_SM_FSM_FFd1 3 0 \/2 0 FB12_14 (b) (b)
(unused) 0 0 \/5 0 FB12_15 (b) (b)
IDE_ACCESS 19 14<- 0 0 FB12_16 (b) (b)
(unused) 0 0 /\5 0 FB12_17 (b) (b)
LAN_RST_SM_FSM_FFd2 3 0 /\2 0 FB12_18 (b) (b)
Signals Used by Logic in Function Block
1: AS 15: IDE_BASEADR<7> 29: A<17>.PIN
2: DQ_12_IOBUFE/DQ_12_IOBUFE_TRST__$INT 16: LAN_BASEADR<0> 30: A<23>.PIN
3: DQ_DATA<11> 17: LAN_BASEADR<14> 31: A<18>.PIN
4: DQ_DATA<13> 18: LAN_BASEADR<1> 32: A<19>.PIN
5: DQ_DATA<15> 19: LAN_BASEADR<2> 33: D<14>.PIN
6: DQ_DATA<9> 20: LAN_BASEADR<3> 34: A<20>.PIN
7: IDE_ACCESS 21: LAN_BASEADR<4> 35: A<21>.PIN
8: IDE_BASEADR<0> 22: LAN_BASEADR<5> 36: A<16>.PIN
9: IDE_BASEADR<1> 23: LAN_BASEADR<7> 37: A<22>.PIN
10: IDE_BASEADR<2> 24: LAN_D_INIT<1> 38: RESET
11: IDE_BASEADR<3> 25: LAN_D_INIT<8> 39: RW
12: IDE_BASEADR<4> 26: LAN_RST_SM_FSM_FFd1 40: SHUT_UP_Z2<1>
13: IDE_BASEADR<5> 27: LAN_RST_SM_FSM_FFd2 41: SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF
14: IDE_BASEADR<6> 28: LAN_RST_SM_FSM_FFd3
Signal 1 2 3 4 5 FB
Name 0----+----0----+----0----+----0----+----0----+----0 Inputs
LAN_RST_SM_FSM_FFd3 .........................XXX.........X............ 4
LAN_CFG<4> .................................................. 0
$OpTx$INV$129 ...............XXXXXXXX.....XXXXXXXX.............. 16
DQ<15> .X..X................................X............ 3
IDE_W_S X.....X..............................XX.X......... 5
LAN_A_INIT<6> .........................XXX.........X............ 4
DQ<13> .X.X.................................X............ 3
LAN_CS_RST .........................XXX.........X............ 4
DQ<11> .XX.....................X............X............ 4
LAN_D_INIT<1> .........................XXX.........X............ 4
DQ<9> .X...X.................X.............X............ 4
LAN_D_INIT<8> .........................XXX.........X............ 4
LAN_RST_SM_FSM_FFd1 .........................XXX.........X............ 4
IDE_ACCESS X......XXXXXXXX.............XXXX.XXXXX.X.......... 19
LAN_RST_SM_FSM_FFd2 .........................XXX.........X............ 4
0----+----1----+----2----+----3----+----4----+----5
0 0 0 0 0
*********************************** FB13 ***********************************
Number of function block inputs used/remaining: 37/17
Number of signals used by logic mapping into function block: 37
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 /\5 0 FB13_1 (b) (b)
CP_RD 1 1<- /\5 0 FB13_2 71 I/O O
Z3_DATA<31> 4 0 /\1 0 FB13_3 (b) (b)
(unused) 0 0 \/5 0 FB13_4 (b) (b)
LAN_SM_FSM_FFd3 7 5<- \/3 0 FB13_5 (b) (b)
DQ_DATA<4> 13 8<- 0 0 FB13_6 (b) (b)
(unused) 0 0 /\5 0 FB13_7 (b) (b)
A<15> 5 0 0 0 FB13_8 74 I/O I/O
(unused) 0 0 \/5 0 FB13_9 (b) (b)
(unused) 0 0 \/5 0 FB13_10 (b) (b)
DQ_DATA<3> 13 10<- \/2 0 FB13_11 75 I/O I
DQ_DATA<13> 13 8<- 0 0 FB13_12 (b) (b)
(unused) 0 0 /\5 0 FB13_13 (b) (b)
LAN_WRL 3 0 /\1 1 FB13_14 76 I/O O
Z3_DATA<23> 4 0 \/1 0 FB13_15 77 I/O I
(unused) 0 0 \/5 0 FB13_16 (b) (b)
DQ_DATA<11> 13 8<- 0 0 FB13_17 78 I/O I
DQ_DATA<12> 13 10<- /\2 0 FB13_18 (b) (b)
Signals Used by Logic in Function Block
1: AS 14: LAN_SM_FSM_FFd1 26: A<13>.PIN
2: CP_RD_S 15: LAN_SM_FSM_FFd2 27: D<13>.PIN
3: DQ_DATA<11> 16: LAN_SM_FSM_FFd3 28: D<12>.PIN
4: DQ_DATA<12> 17: LAN_SM_FSM_FFd4 29: D<11>.PIN
5: DQ_DATA<13> 18: LAN_SM_RST 30: D<5>.PIN
6: DQ_DATA<3> 19: LAN_WRL_S 31: D<4>.PIN
7: DQ_DATA<4> 20: LAN_WR_RST 32: D<3>.PIN
8: DQ_SWAP 21: LDS 33: A<20>.PIN
9: DS0 22: A<19>.PIN 34: A<21>.PIN
10: DS1 23: DQ<15>.PIN 35: RESET
11: FCS 24: A<12>.PIN 36: RW
12: A<11>.PIN 25: DQ<7>.PIN 37: UDS
13: LAN_ACCESS
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
CP_RD XX...................................... 2
Z3_DATA<31> .......X.....XX.XX....X.X............... 7
LAN_SM_FSM_FFd3 ........XX...XXXXX..X..............XX... 10
DQ_DATA<4> ......XX.....XXXXX..X..X...X..X.X...X... 13
A<15> .......X..X.XXXXXX....X.X..........X.... 11
DQ_DATA<3> .....X.X...X.XXXXX..XX......X..X....X... 13
DQ_DATA<13> ....X..X.....XXXXX..X....XX..X...X..X... 13
LAN_WRL ..........X.......XX..............X..... 4
Z3_DATA<23> .......X.....XX.XX....X.X............... 7
DQ_DATA<11> ..X....X...X.XXXXX..XX......X..X....X... 13
DQ_DATA<12> ...X...X.....XXXXX..X..X...X..X.X...X... 13
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB14 ***********************************
Number of function block inputs used/remaining: 23/31
Number of signals used by logic mapping into function block: 23
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
AUTO_CONFIG_Z2_DONE_CYCLE<1>
4 0 /\1 0 FB14_1 (b) (b)
CP_RD_S 3 0 0 2 FB14_2 (b) (b)
OVR 1 0 0 4 FB14_3 100 I/O O
SHUT_UP_Z2<0> 4 0 0 1 FB14_4 (b) (b)
AUTO_CONFIG_Z2_DONE_CYCLE<0>
4 0 0 1 FB14_5 101 I/O (b)
AUTO_CONFIG_Z2_DONE<1>
4 0 0 1 FB14_6 102 I/O I
AUTO_CONFIG_Z2_DONE<0>
4 0 0 1 FB14_7 (b) (b)
(unused) 0 0 \/5 0 FB14_8 103 I/O I
(unused) 0 0 \/5 0 FB14_9 (b) (b)
D_Z2_OUT<3> 14 10<- \/1 0 FB14_10 104 I/O I
CFOUT 1 1<- \/5 0 FB14_11 105 I/O O
D_Z2_OUT<2> 16 11<- 0 0 FB14_12 (b) (b)
(unused) 0 0 /\5 0 FB14_13 (b) (b)
SLAVE 4 0 /\1 0 FB14_14 106 I/O O
OWN 0 0 \/4 1 FB14_15 107 I/O O
D_Z2_OUT<1> 17 12<- 0 0 FB14_16 (b) (b)
(unused) 0 0 /\5 0 FB14_17 (b) (b)
CP_WE_S 3 1<- /\3 0 FB14_18 (b) (b)
Signals Used by Logic in Function Block
1: AS 9: A<2> 17: LAN_ACCESS
2: AUTOCONFIG_Z2_ACCESS 10: A<3> 18: LDS
3: AUTO_CONFIG_Z2_DONE<0> 11: A<4> 19: RESET
4: AUTO_CONFIG_Z2_DONE<1> 12: A<5> 20: RW
5: AUTO_CONFIG_Z2_DONE<2> 13: A<6> 21: SHUT_UP_Z2<0>
6: AUTO_CONFIG_Z2_DONE_CYCLE<0> 14: CP_CS 22: SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF
7: AUTO_CONFIG_Z2_DONE_CYCLE<1> 15: FCS 23: UDS
8: A<1> 16: IDE_ACCESS
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
AUTO_CONFIG_Z2_DONE_CYCLE<1>
XXXX..XX.XXXX....XXX.XX................. 15
CP_RD_S .............X...X.X.XX................. 5
OVR ..............X.X....................... 2
SHUT_UP_Z2<0> XXX....XXXXXX....XXXXXX................. 15
AUTO_CONFIG_Z2_DONE_CYCLE<0>
XXX..X.X.XXXX....XXX.XX................. 14
AUTO_CONFIG_Z2_DONE<1>
X..X..X...........X..X.................. 5
AUTO_CONFIG_Z2_DONE<0>
X.X..X............X..X.................. 5
D_Z2_OUT<3> XXXX...XXXXXX....XX..XX................. 14
CFOUT ..XXX................................... 3
D_Z2_OUT<2> XXXX...XXXXXX....XX..XX................. 14
SLAVE XX...........XXXX....................... 6
OWN ........................................ 0
D_Z2_OUT<1> XXXX...XXXXXX....XX..XX................. 14
CP_WE_S .............X...X.X.XX................. 5
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB15 ***********************************
Number of function block inputs used/remaining: 35/19
Number of signals used by logic mapping into function block: 35
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
DQ_DATA<6> 13 8<- 0 0 FB15_1 (b) (b)
DQ_DATA<7> 13 10<- /\2 0 FB15_2 79 I/O I
(unused) 0 0 /\5 0 FB15_3 80 I/O I
(unused) 0 0 /\5 0 FB15_4 (b) (b)
(unused) 0 0 \/5 0 FB15_5 (b) (b)
(unused) 0 0 \/5 0 FB15_6 (b) (b)
DQ_DATA<1> 13 10<- \/2 0 FB15_7 (b) (b)
DQ_DATA<14> 13 8<- 0 0 FB15_8 81 I/O I
(unused) 0 0 /\5 0 FB15_9 (b) (b)
DQ_DATA<15> 13 9<- /\1 0 FB15_10 82 I/O I
(unused) 0 0 /\5 0 FB15_11 83 I/O I
DTACK 1 0 /\4 0 FB15_12 85 I/O O
(unused) 0 0 0 5 FB15_13 (b)
A<23> 5 0 0 0 FB15_14 86 I/O I/O
A<22> 5 0 0 0 FB15_15 87 I/O I/O
(unused) 0 0 \/1 4 FB15_16 (b) (b)
A<21> 5 1<- \/1 0 FB15_17 88 I/O I/O
(unused) 0 0 \/5 0 FB15_18 (b) (b)
Signals Used by Logic in Function Block
1: DQ_DATA<14> 13: LAN_SM_FSM_FFd4 25: D<14>.PIN
2: DQ_DATA<15> 14: LAN_SM_RST 26: D<9>.PIN
3: DQ_DATA<1> 15: LDS 27: A<14>.PIN
4: DQ_DATA<6> 16: A<17>.PIN 28: D<7>.PIN
5: DQ_DATA<7> 17: A<23>.PIN 29: D<6>.PIN
6: DQ_SWAP 18: DQ<15>.PIN 30: D<1>.PIN
7: FCS 19: DQ<14>.PIN 31: A<15>.PIN
8: A<9>.PIN 20: DQ<13>.PIN 32: A<22>.PIN
9: LAN_ACCESS 21: DQ<7>.PIN 33: ROM_B_0_OBUF$BUF9/ROM_B_0_OBUF$BUF9_TRST
10: LAN_SM_FSM_FFd1 22: DQ<6>.PIN 34: RW
11: LAN_SM_FSM_FFd2 23: DQ<5>.PIN 35: UDS
12: LAN_SM_FSM_FFd3 24: D<15>.PIN
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
DQ_DATA<6> ...X.X...XXXXXX.........X.X.X..X..X..... 13
DQ_DATA<7> ....XX...XXXXXX.X......X...X..X...X..... 13
DQ_DATA<1> ..X..X.X.XXXXXXX.........X...X....X..... 13
DQ_DATA<14> X....X...XXXXXX.........X.X.X..X..X..... 13
DQ_DATA<15> .X...X...XXXXXX.X......X...X..X...X..... 13
DTACK ................................X....... 1
A<23> .....XX.XXXXXX...X..X............X...... 11
A<22> .....XX.XXXXXX....X..X...........X...... 11
A<21> .....XX.XXXXXX.....X..X..........X...... 11
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB16 ***********************************
Number of function block inputs used/remaining: 27/27
Number of signals used by logic mapping into function block: 27
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 /\5 0 FB16_1 (b) (b)
A<20> 5 0 0 0 FB16_2 91 I/O I/O
A<19> 5 0 0 0 FB16_3 92 I/O I/O
(unused) 0 0 0 5 FB16_4 (b)
Z3_DATA<26> 4 0 0 1 FB16_5 93 I/O I
A<18> 5 0 0 0 FB16_6 94 I/O I/O
Z3_DATA<25> 4 0 0 1 FB16_7 (b) (b)
A<17> 5 0 0 0 FB16_8 95 I/O I/O
Z3_DATA<24> 4 0 0 1 FB16_9 (b) (b)
MTACK 0 0 0 5 FB16_10 96 I/O O
A<16> 5 0 0 0 FB16_11 97 I/O I/O
Z3_DATA<18> 4 0 0 1 FB16_12 98 I/O I
Z3_DATA<17> 4 0 0 1 FB16_13 (b) (b)
Z3_DATA<16> 4 0 \/1 0 FB16_14 (b) (b)
(unused) 0 0 \/5 0 FB16_15 (b) (b)
DQ_DATA<10> 13 8<- 0 0 FB16_16 (b) (b)
DQ_DATA<2> 13 10<- /\2 0 FB16_17 (b) (b)
(unused) 0 0 /\5 0 FB16_18 (b) (b)
Signals Used by Logic in Function Block
1: DQ_DATA<10> 10: LAN_SM_FSM_FFd4 19: DQ<4>.PIN
2: DQ_DATA<2> 11: LAN_SM_RST 20: DQ<3>.PIN
3: DQ_SWAP 12: LDS 21: DQ<2>.PIN
4: FCS 13: A<18>.PIN 22: DQ<1>.PIN
5: A<10>.PIN 14: DQ<12>.PIN 23: DQ<0>.PIN
6: LAN_ACCESS 15: DQ<11>.PIN 24: D<10>.PIN
7: LAN_SM_FSM_FFd1 16: DQ<10>.PIN 25: D<2>.PIN
8: LAN_SM_FSM_FFd2 17: DQ<9>.PIN 26: RW
9: LAN_SM_FSM_FFd3 18: DQ<8>.PIN 27: UDS
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
A<20> ..XX.XXXXXX..X....X......X.............. 11
A<19> ..XX.XXXXXX...X....X.....X.............. 11
Z3_DATA<26> ..X...XX.XX....X....X................... 7
A<18> ..XX.XXXXXX....X....X....X.............. 11
Z3_DATA<25> ..X...XX.XX.....X....X.................. 7
A<17> ..XX.XXXXXX.....X....X...X.............. 11
Z3_DATA<24> ..X...XX.XX......X....X................. 7
MTACK ........................................ 0
A<16> ..XX.XXXXXX......X....X..X.............. 11
Z3_DATA<18> ..X...XX.XX....X....X................... 7
Z3_DATA<17> ..X...XX.XX.....X....X.................. 7
Z3_DATA<16> ..X...XX.XX......X....X................. 7
DQ_DATA<10> X.X.X.XXXXXXX..........XX.X............. 13
DQ_DATA<2> .XX.X.XXXXXXX..........XX.X............. 13
0----+----1----+----2----+----3----+----4
0 0 0 0
******************************* Equations ********************************
********** Mapped Logic **********
$OpTx$INV$129 <= ((D(14).PIN AND NOT LAN_BASEADR(14))
OR (LAN_BASEADR(2) AND NOT A(18).PIN)
OR (NOT LAN_BASEADR(2) AND A(18).PIN)
OR (LAN_BASEADR(7) AND NOT A(23).PIN)
OR (DQ_15_IOBUFE.EXP)
OR (NOT D(14).PIN AND LAN_BASEADR(14))
OR (LAN_BASEADR(0) AND NOT A(16).PIN)
OR (NOT LAN_BASEADR(0) AND A(16).PIN)
OR (LAN_BASEADR(4) AND NOT A(20).PIN)
OR (NOT LAN_BASEADR(4) AND A(20).PIN)
OR (LAN_BASEADR(1) AND NOT A(17).PIN)
OR (NOT LAN_BASEADR(1) AND A(17).PIN)
OR (LAN_BASEADR(5) AND NOT A(21).PIN)
OR (NOT LAN_BASEADR(5) AND A(21).PIN)
OR (NOT LAN_BASEADR(7) AND A(23).PIN));
FDCPE_A8: FDCPE port map (A_I(8),A(8),CLK_EXT,'0',LAN_SM_RST,A_CE(8));
A(8) <= ((DQ_SWAP AND DQ(8).PIN)
OR (NOT DQ_SWAP AND DQ(0).PIN));
A_CE(8) <= (LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd4 AND
NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1);
A(8) <= A_I(8) when A_OE(8) = '1' else 'Z';
A_OE(8) <= (RW AND NOT FCS AND LAN_ACCESS);
FDCPE_A9: FDCPE port map (A_I(9),A(9),CLK_EXT,'0',LAN_SM_RST,A_CE(9));
A(9) <= ((DQ_SWAP AND DQ(9).PIN)
OR (NOT DQ_SWAP AND DQ(1).PIN));
A_CE(9) <= (LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd4 AND
NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1);
A(9) <= A_I(9) when A_OE(9) = '1' else 'Z';
A_OE(9) <= (RW AND NOT FCS AND LAN_ACCESS);
FDCPE_A10: FDCPE port map (A_I(10),A(10),CLK_EXT,'0',LAN_SM_RST,A_CE(10));
A(10) <= ((NOT DQ_SWAP AND DQ(2).PIN)
OR (DQ_SWAP AND DQ(10).PIN));
A_CE(10) <= (LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd4 AND
NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1);
A(10) <= A_I(10) when A_OE(10) = '1' else 'Z';
A_OE(10) <= (RW AND NOT FCS AND LAN_ACCESS);
FDCPE_A11: FDCPE port map (A_I(11),A(11),CLK_EXT,'0',LAN_SM_RST,A_CE(11));
A(11) <= ((NOT DQ_SWAP AND DQ(3).PIN)
OR (DQ_SWAP AND DQ(11).PIN));
A_CE(11) <= (LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd4 AND
NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1);
A(11) <= A_I(11) when A_OE(11) = '1' else 'Z';
A_OE(11) <= (RW AND NOT FCS AND LAN_ACCESS);
FDCPE_A12: FDCPE port map (A_I(12),A(12),CLK_EXT,'0',LAN_SM_RST,A_CE(12));
A(12) <= ((DQ_SWAP AND DQ(12).PIN)
OR (NOT DQ_SWAP AND DQ(4).PIN));
A_CE(12) <= (LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd4 AND
NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1);
A(12) <= A_I(12) when A_OE(12) = '1' else 'Z';
A_OE(12) <= (RW AND NOT FCS AND LAN_ACCESS);
FDCPE_A13: FDCPE port map (A_I(13),A(13),CLK_EXT,'0',LAN_SM_RST,A_CE(13));
A(13) <= ((DQ_SWAP AND DQ(13).PIN)
OR (NOT DQ_SWAP AND DQ(5).PIN));
A_CE(13) <= (LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd4 AND
NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1);
A(13) <= A_I(13) when A_OE(13) = '1' else 'Z';
A_OE(13) <= (RW AND NOT FCS AND LAN_ACCESS);
FDCPE_A14: FDCPE port map (A_I(14),A(14),CLK_EXT,'0',LAN_SM_RST,A_CE(14));
A(14) <= ((DQ_SWAP AND DQ(14).PIN)
OR (NOT DQ_SWAP AND DQ(6).PIN));
A_CE(14) <= (LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd4 AND
NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1);
A(14) <= A_I(14) when A_OE(14) = '1' else 'Z';
A_OE(14) <= (RW AND NOT FCS AND LAN_ACCESS);
FDCPE_A15: FDCPE port map (A_I(15),A(15),CLK_EXT,'0',LAN_SM_RST,A_CE(15));
A(15) <= ((DQ_SWAP AND DQ(15).PIN)
OR (NOT DQ_SWAP AND DQ(7).PIN));
A_CE(15) <= (LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd4 AND
NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1);
A(15) <= A_I(15) when A_OE(15) = '1' else 'Z';
A_OE(15) <= (RW AND NOT FCS AND LAN_ACCESS);
FDCPE_A16: FDCPE port map (A_I(16),A(16),CLK_EXT,'0',LAN_SM_RST,A_CE(16));
A(16) <= ((DQ_SWAP AND DQ(0).PIN)
OR (NOT DQ_SWAP AND DQ(8).PIN));
A_CE(16) <= (LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd4 AND
NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1);
A(16) <= A_I(16) when A_OE(16) = '1' else 'Z';
A_OE(16) <= (RW AND NOT FCS AND LAN_ACCESS);
FDCPE_A17: FDCPE port map (A_I(17),A(17),CLK_EXT,'0',LAN_SM_RST,A_CE(17));
A(17) <= ((DQ_SWAP AND DQ(1).PIN)
OR (NOT DQ_SWAP AND DQ(9).PIN));
A_CE(17) <= (LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd4 AND
NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1);
A(17) <= A_I(17) when A_OE(17) = '1' else 'Z';
A_OE(17) <= (RW AND NOT FCS AND LAN_ACCESS);
FDCPE_A18: FDCPE port map (A_I(18),A(18),CLK_EXT,'0',LAN_SM_RST,A_CE(18));
A(18) <= ((DQ_SWAP AND DQ(2).PIN)
OR (NOT DQ_SWAP AND DQ(10).PIN));
A_CE(18) <= (LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd4 AND
NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1);
A(18) <= A_I(18) when A_OE(18) = '1' else 'Z';
A_OE(18) <= (RW AND NOT FCS AND LAN_ACCESS);
FDCPE_A19: FDCPE port map (A_I(19),A(19),CLK_EXT,'0',LAN_SM_RST,A_CE(19));
A(19) <= ((DQ_SWAP AND DQ(3).PIN)
OR (NOT DQ_SWAP AND DQ(11).PIN));
A_CE(19) <= (LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd4 AND
NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1);
A(19) <= A_I(19) when A_OE(19) = '1' else 'Z';
A_OE(19) <= (RW AND NOT FCS AND LAN_ACCESS);
FDCPE_A20: FDCPE port map (A_I(20),A(20),CLK_EXT,'0',LAN_SM_RST,A_CE(20));
A(20) <= ((DQ_SWAP AND DQ(4).PIN)
OR (NOT DQ_SWAP AND DQ(12).PIN));
A_CE(20) <= (LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd4 AND
NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1);
A(20) <= A_I(20) when A_OE(20) = '1' else 'Z';
A_OE(20) <= (RW AND NOT FCS AND LAN_ACCESS);
FDCPE_A21: FDCPE port map (A_I(21),A(21),CLK_EXT,'0',LAN_SM_RST,A_CE(21));
A(21) <= ((DQ_SWAP AND DQ(5).PIN)
OR (NOT DQ_SWAP AND DQ(13).PIN));
A_CE(21) <= (LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd4 AND
NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1);
A(21) <= A_I(21) when A_OE(21) = '1' else 'Z';
A_OE(21) <= (RW AND NOT FCS AND LAN_ACCESS);
FDCPE_A22: FDCPE port map (A_I(22),A(22),CLK_EXT,'0',LAN_SM_RST,A_CE(22));
A(22) <= ((DQ_SWAP AND DQ(6).PIN)
OR (NOT DQ_SWAP AND DQ(14).PIN));
A_CE(22) <= (LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd4 AND
NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1);
A(22) <= A_I(22) when A_OE(22) = '1' else 'Z';
A_OE(22) <= (RW AND NOT FCS AND LAN_ACCESS);
FDCPE_A23: FDCPE port map (A_I(23),A(23),CLK_EXT,'0',LAN_SM_RST,A_CE(23));
A(23) <= ((DQ_SWAP AND DQ(7).PIN)
OR (NOT DQ_SWAP AND DQ(15).PIN));
A_CE(23) <= (LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd4 AND
NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1);
A(23) <= A_I(23) when A_OE(23) = '1' else 'Z';
A_OE(23) <= (RW AND NOT FCS AND LAN_ACCESS);
FDCPE_AUTOCONFIG_Z2_ACCESS: FDCPE port map (AUTOCONFIG_Z2_ACCESS,AUTOCONFIG_Z2_ACCESS_D,NOT AS,NOT RESET,'0');
AUTOCONFIG_Z2_ACCESS_D <= ((NOT AUTO_CONFIG_Z2_DONE(0) AND A(23).PIN AND A(22).PIN AND
A(21).PIN AND A(19).PIN AND NOT CFIN AND NOT A(17).PIN AND NOT A(16).PIN AND
NOT A(20).PIN AND NOT A(18).PIN)
OR (NOT AUTO_CONFIG_Z2_DONE(1) AND A(23).PIN AND A(22).PIN AND
A(21).PIN AND A(19).PIN AND NOT CFIN AND NOT A(17).PIN AND NOT A(16).PIN AND
NOT A(20).PIN AND NOT A(18).PIN)
OR (NOT AUTO_CONFIG_Z2_DONE(2) AND A(23).PIN AND A(22).PIN AND
A(21).PIN AND A(19).PIN AND NOT CFIN AND NOT A(17).PIN AND NOT A(16).PIN AND
NOT A(20).PIN AND NOT A(18).PIN));
FDCPE_AUTO_CONFIG_Z2_DONE0: FDCPE port map (AUTO_CONFIG_Z2_DONE(0),AUTO_CONFIG_Z2_DONE_D(0),SHUT_UP_Z2(1)/SHUT_UP_Z2(1)_CLKF,NOT RESET,'0',AS);
AUTO_CONFIG_Z2_DONE_D(0) <= (NOT AUTO_CONFIG_Z2_DONE(0) AND
NOT AUTO_CONFIG_Z2_DONE_CYCLE(0));
FDCPE_AUTO_CONFIG_Z2_DONE1: FDCPE port map (AUTO_CONFIG_Z2_DONE(1),AUTO_CONFIG_Z2_DONE_D(1),SHUT_UP_Z2(1)/SHUT_UP_Z2(1)_CLKF,NOT RESET,'0',AS);
AUTO_CONFIG_Z2_DONE_D(1) <= (NOT AUTO_CONFIG_Z2_DONE(1) AND
NOT AUTO_CONFIG_Z2_DONE_CYCLE(1));
FDCPE_AUTO_CONFIG_Z2_DONE2: FDCPE port map (AUTO_CONFIG_Z2_DONE(2),AUTO_CONFIG_Z2_DONE_D(2),SHUT_UP_Z2(1)/SHUT_UP_Z2(1)_CLKF,NOT RESET,'0',AS);
AUTO_CONFIG_Z2_DONE_D(2) <= (NOT AUTO_CONFIG_Z2_DONE(2) AND
NOT AUTO_CONFIG_Z2_DONE_CYCLE(2));
FTCPE_AUTO_CONFIG_Z2_DONE_CYCLE0: FTCPE port map (AUTO_CONFIG_Z2_DONE_CYCLE(0),AUTO_CONFIG_Z2_DONE_CYCLE_T(0),SHUT_UP_Z2(1)/SHUT_UP_Z2(1)_CLKF,NOT RESET,'0');
AUTO_CONFIG_Z2_DONE_CYCLE_T(0) <= ((NOT A(5) AND NOT A(4) AND NOT A(1) AND NOT AS AND
NOT AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE_CYCLE(0) AND NOT UDS AND A(6) AND
A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)
OR (NOT A(5) AND NOT A(4) AND NOT A(1) AND NOT AS AND
NOT AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE_CYCLE(0) AND NOT LDS AND A(6) AND
A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS));
FTCPE_AUTO_CONFIG_Z2_DONE_CYCLE1: FTCPE port map (AUTO_CONFIG_Z2_DONE_CYCLE(1),AUTO_CONFIG_Z2_DONE_CYCLE_T(1),SHUT_UP_Z2(1)/SHUT_UP_Z2(1)_CLKF,NOT RESET,'0');
AUTO_CONFIG_Z2_DONE_CYCLE_T(1) <= ((NOT A(5) AND NOT A(4) AND NOT A(1) AND NOT AS AND
AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE(1) AND
NOT AUTO_CONFIG_Z2_DONE_CYCLE(1) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)
OR (NOT A(5) AND NOT A(4) AND NOT A(1) AND NOT AS AND
AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE(1) AND
NOT AUTO_CONFIG_Z2_DONE_CYCLE(1) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS));
FTCPE_AUTO_CONFIG_Z2_DONE_CYCLE2: FTCPE port map (AUTO_CONFIG_Z2_DONE_CYCLE(2),AUTO_CONFIG_Z2_DONE_CYCLE_T(2),SHUT_UP_Z2(1)/SHUT_UP_Z2(1)_CLKF,NOT RESET,'0');
AUTO_CONFIG_Z2_DONE_CYCLE_T(2) <= ((NOT A(5) AND NOT A(4) AND NOT A(1) AND NOT AS AND
AUTO_CONFIG_Z2_DONE(0) AND AUTO_CONFIG_Z2_DONE(1) AND NOT AUTO_CONFIG_Z2_DONE(2) AND
NOT AUTO_CONFIG_Z2_DONE_CYCLE(2) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)
OR (NOT A(5) AND NOT A(4) AND NOT A(1) AND NOT AS AND
AUTO_CONFIG_Z2_DONE(0) AND AUTO_CONFIG_Z2_DONE(1) AND NOT AUTO_CONFIG_Z2_DONE(2) AND
NOT AUTO_CONFIG_Z2_DONE_CYCLE(2) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS));
A_LAN(0) <= NOT ((RESET AND NOT Z3_A_LOW));
A_LAN(1) <= NOT ((RESET AND NOT Z3_ADR_0));
A_LAN(2) <= NOT ((RESET AND NOT Z3_ADR_1));
A_LAN(3) <= ((RESET AND Z3_ADR(2))
OR (NOT RESET AND LAN_A_INIT(3)));
A_LAN(4) <= NOT ((RESET AND NOT Z3_ADR(3)));
A_LAN(5) <= NOT ((RESET AND NOT Z3_ADR(4)));
A_LAN(6) <= ((RESET AND Z3_ADR(5))
OR (NOT RESET AND LAN_A_INIT(6)));
A_LAN(7) <= NOT ((RESET AND NOT Z3_ADR(6)));
A_LAN(8) <= NOT ((RESET AND NOT Z3_ADR(7)));
A_LAN(9) <= NOT ((RESET AND NOT Z3_ADR(8)));
A_LAN(10) <= NOT ((RESET AND NOT Z3_ADR(9)));
A_LAN(11) <= NOT ((RESET AND NOT Z3_ADR(10)));
A_LAN(12) <= NOT ((RESET AND NOT Z3_ADR(11)));
A_LAN(13) <= NOT ((RESET AND NOT Z3_ADR(12)));
CFOUT <= NOT ((AUTO_CONFIG_Z2_DONE(0) AND AUTO_CONFIG_Z2_DONE(1) AND
AUTO_CONFIG_Z2_DONE(2)));
FDCPE_CONFIG_READY: FDCPE port map (CONFIG_READY,CONFIG_READY_D,CLK_EXT,NOT RESET,'0');
CONFIG_READY_D <= (NOT FCS AND LAN_ACCESS AND Z3_ADR(13));
FTCPE_CP_BASEADR0: FTCPE port map (CP_BASEADR(0),CP_BASEADR_T(0),SHUT_UP_Z2(1)/SHUT_UP_Z2(1)_CLKF,'0',NOT RESET);
CP_BASEADR_T(0) <= ((NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE(1) AND D(8).PIN AND
NOT CP_BASEADR(0) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE(1) AND D(8).PIN AND
NOT CP_BASEADR(0) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE(1) AND NOT D(8).PIN AND
CP_BASEADR(0) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE(1) AND NOT D(8).PIN AND
CP_BASEADR(0) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS));
FTCPE_CP_BASEADR1: FTCPE port map (CP_BASEADR(1),CP_BASEADR_T(1),SHUT_UP_Z2(1)/SHUT_UP_Z2(1)_CLKF,'0',NOT RESET);
CP_BASEADR_T(1) <= ((NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE(1) AND D(9).PIN AND
NOT CP_BASEADR(1) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE(1) AND D(9).PIN AND
NOT CP_BASEADR(1) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE(1) AND NOT D(9).PIN AND
CP_BASEADR(1) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE(1) AND NOT D(9).PIN AND
CP_BASEADR(1) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS));
FTCPE_CP_BASEADR2: FTCPE port map (CP_BASEADR(2),CP_BASEADR_T(2),SHUT_UP_Z2(1)/SHUT_UP_Z2(1)_CLKF,'0',NOT RESET);
CP_BASEADR_T(2) <= ((NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE(1) AND D(10).PIN AND
NOT CP_BASEADR(2) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE(1) AND D(10).PIN AND
NOT CP_BASEADR(2) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE(1) AND NOT D(10).PIN AND
CP_BASEADR(2) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE(1) AND NOT D(10).PIN AND
CP_BASEADR(2) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS));
FTCPE_CP_BASEADR3: FTCPE port map (CP_BASEADR(3),CP_BASEADR_T(3),SHUT_UP_Z2(1)/SHUT_UP_Z2(1)_CLKF,'0',NOT RESET);
CP_BASEADR_T(3) <= ((NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE(1) AND D(11).PIN AND
NOT CP_BASEADR(3) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE(1) AND D(11).PIN AND
NOT CP_BASEADR(3) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE(1) AND NOT D(11).PIN AND
CP_BASEADR(3) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE(1) AND NOT D(11).PIN AND
CP_BASEADR(3) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS));
FTCPE_CP_BASEADR4: FTCPE port map (CP_BASEADR(4),CP_BASEADR_T(4),SHUT_UP_Z2(1)/SHUT_UP_Z2(1)_CLKF,'0',NOT RESET);
CP_BASEADR_T(4) <= ((NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE(1) AND D(12).PIN AND
NOT CP_BASEADR(4) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE(1) AND D(12).PIN AND
NOT CP_BASEADR(4) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE(1) AND NOT D(12).PIN AND
CP_BASEADR(4) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE(1) AND NOT D(12).PIN AND
CP_BASEADR(4) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS));
FTCPE_CP_BASEADR5: FTCPE port map (CP_BASEADR(5),CP_BASEADR_T(5),SHUT_UP_Z2(1)/SHUT_UP_Z2(1)_CLKF,'0',NOT RESET);
CP_BASEADR_T(5) <= ((NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE(1) AND D(13).PIN AND
NOT CP_BASEADR(5) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE(1) AND D(13).PIN AND
NOT CP_BASEADR(5) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE(1) AND NOT D(13).PIN AND
CP_BASEADR(5) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE(1) AND NOT D(13).PIN AND
CP_BASEADR(5) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS));
FTCPE_CP_BASEADR6: FTCPE port map (CP_BASEADR(6),CP_BASEADR_T(6),SHUT_UP_Z2(1)/SHUT_UP_Z2(1)_CLKF,'0',NOT RESET);
CP_BASEADR_T(6) <= ((NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE(1) AND D(14).PIN AND
NOT CP_BASEADR(6) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE(1) AND D(14).PIN AND
NOT CP_BASEADR(6) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE(1) AND NOT D(14).PIN AND
CP_BASEADR(6) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE(1) AND NOT D(14).PIN AND
CP_BASEADR(6) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS));
FTCPE_CP_BASEADR7: FTCPE port map (CP_BASEADR(7),CP_BASEADR_T(7),SHUT_UP_Z2(1)/SHUT_UP_Z2(1)_CLKF,'0',NOT RESET);
CP_BASEADR_T(7) <= ((NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE(1) AND D(15).PIN AND
NOT CP_BASEADR(7) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE(1) AND D(15).PIN AND
NOT CP_BASEADR(7) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE(1) AND NOT D(15).PIN AND
CP_BASEADR(7) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE(1) AND NOT D(15).PIN AND
CP_BASEADR(7) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS));
FDCPE_CP_CS: FDCPE port map (CP_CS,CP_CS_D,NOT AS,'0',NOT RESET);
CP_CS_D <= ((SHUT_UP_Z2(0))
OR (CP_BASEADR(1) AND NOT A(17).PIN)
OR (NOT CP_BASEADR(1) AND A(17).PIN)
OR (CP_BASEADR(2) AND NOT A(18).PIN)
OR (NOT CP_BASEADR(2) AND A(18).PIN)
OR (NOT CP_BASEADR(3) AND A(19).PIN)
OR (EXP29_.EXP)
OR (CP_BASEADR(3) AND NOT A(19).PIN)
OR (CP_BASEADR(4) AND NOT A(20).PIN)
OR (NOT CP_BASEADR(4) AND A(20).PIN)
OR (CP_BASEADR(5) AND NOT A(21).PIN)
OR (NOT CP_BASEADR(5) AND A(21).PIN)
OR (CP_BASEADR(0) AND NOT A(16).PIN)
OR (NOT CP_BASEADR(0) AND A(16).PIN));
CP_RD <= NOT ((NOT AS AND NOT CP_RD_S));
FDCPE_CP_RD_S: FDCPE port map (CP_RD_S,CP_RD_S_D,SHUT_UP_Z2(1)/SHUT_UP_Z2(1)_CLKF,'0','0');
CP_RD_S_D <= ((NOT UDS AND RW AND NOT CP_CS)
OR (NOT LDS AND RW AND NOT CP_CS));
CP_WE <= NOT ((NOT AS AND NOT CP_WE_S AND CP_WE_QUIRK));
FDCPE_CP_WE_QUIRK: FDCPE port map (CP_WE_QUIRK,CP_WE_S,SHUT_UP_Z2(1)/SHUT_UP_Z2(1)_CLKF,'0','0');
FDCPE_CP_WE_S: FDCPE port map (CP_WE_S,CP_WE_S_D,SHUT_UP_Z2(1)/SHUT_UP_Z2(1)_CLKF,'0','0');
CP_WE_S_D <= ((NOT LDS AND NOT RW AND NOT CP_CS)
OR (NOT UDS AND NOT RW AND NOT CP_CS));
D_I(0) <= NOT ((NOT Z3_DATA(16) AND RW AND NOT FCS AND LAN_ACCESS));
D(0) <= D_I(0) when D_OE(0) = '1' else 'Z';
D_OE(0) <= D_5_IOBUFE/D_5_IOBUFE_TRST;
D_I(1) <= NOT ((NOT Z3_DATA(17) AND RW AND NOT FCS AND LAN_ACCESS));
D(1) <= D_I(1) when D_OE(1) = '1' else 'Z';
D_OE(1) <= D_5_IOBUFE/D_5_IOBUFE_TRST;
D_I(2) <= NOT ((NOT Z3_DATA(18) AND RW AND NOT FCS AND LAN_ACCESS));
D(2) <= D_I(2) when D_OE(2) = '1' else 'Z';
D_OE(2) <= D_5_IOBUFE/D_5_IOBUFE_TRST;
D_I(3) <= NOT ((NOT Z3_DATA(19) AND RW AND NOT FCS AND LAN_ACCESS));
D(3) <= D_I(3) when D_OE(3) = '1' else 'Z';
D_OE(3) <= D_5_IOBUFE/D_5_IOBUFE_TRST;
D_I(4) <= NOT ((NOT Z3_DATA(20) AND RW AND NOT FCS AND LAN_ACCESS));
D(4) <= D_I(4) when D_OE(4) = '1' else 'Z';
D_OE(4) <= D_5_IOBUFE/D_5_IOBUFE_TRST;
D_I(5) <= NOT ((NOT Z3_DATA(21) AND RW AND NOT FCS AND LAN_ACCESS));
D(5) <= D_I(5) when D_OE(5) = '1' else 'Z';
D_OE(5) <= D_5_IOBUFE/D_5_IOBUFE_TRST;
D_I(6) <= NOT ((NOT Z3_DATA(22) AND RW AND NOT FCS AND LAN_ACCESS));
D(6) <= D_I(6) when D_OE(6) = '1' else 'Z';
D_OE(6) <= D_5_IOBUFE/D_5_IOBUFE_TRST;
D_I(7) <= NOT ((NOT Z3_DATA(23) AND RW AND NOT FCS AND LAN_ACCESS));
D(7) <= D_I(7) when D_OE(7) = '1' else 'Z';
D_OE(7) <= D_5_IOBUFE/D_5_IOBUFE_TRST;
D_I(8) <= NOT ((NOT Z3_DATA(24) AND RW AND NOT FCS AND LAN_ACCESS));
D(8) <= D_I(8) when D_OE(8) = '1' else 'Z';
D_OE(8) <= D_5_IOBUFE/D_5_IOBUFE_TRST;
D_I(9) <= NOT ((NOT Z3_DATA(25) AND RW AND NOT FCS AND LAN_ACCESS));
D(9) <= D_I(9) when D_OE(9) = '1' else 'Z';
D_OE(9) <= D_5_IOBUFE/D_5_IOBUFE_TRST;
D_I(10) <= NOT ((NOT Z3_DATA(26) AND RW AND NOT FCS AND LAN_ACCESS));
D(10) <= D_I(10) when D_OE(10) = '1' else 'Z';
D_OE(10) <= D_5_IOBUFE/D_5_IOBUFE_TRST;
D_I(11) <= NOT ((NOT Z3_DATA(27) AND RW AND NOT FCS AND LAN_ACCESS));
D(11) <= D_I(11) when D_OE(11) = '1' else 'Z';
D_OE(11) <= D_5_IOBUFE/D_5_IOBUFE_TRST;
D_I(12) <= ((NOT RW AND D_Z2_OUT(0))
OR (FCS AND D_Z2_OUT(0))
OR (NOT LAN_ACCESS AND D_Z2_OUT(0))
OR (Z3_DATA(28) AND RW AND NOT FCS AND LAN_ACCESS));
D(12) <= D_I(12) when D_OE(12) = '1' else 'Z';
D_OE(12) <= D_5_IOBUFE/D_5_IOBUFE_TRST;
D_I(13) <= ((Z3_DATA(29) AND RW AND NOT FCS AND LAN_ACCESS)
OR (NOT RW AND D_Z2_OUT(1))
OR (FCS AND D_Z2_OUT(1))
OR (NOT LAN_ACCESS AND D_Z2_OUT(1)));
D(13) <= D_I(13) when D_OE(13) = '1' else 'Z';
D_OE(13) <= D_5_IOBUFE/D_5_IOBUFE_TRST;
D_I(14) <= ((NOT RW AND D_Z2_OUT(2))
OR (FCS AND D_Z2_OUT(2))
OR (NOT LAN_ACCESS AND D_Z2_OUT(2))
OR (Z3_DATA(30) AND RW AND NOT FCS AND LAN_ACCESS));
D(14) <= D_I(14) when D_OE(14) = '1' else 'Z';
D_OE(14) <= D_5_IOBUFE/D_5_IOBUFE_TRST;
D_I(15) <= ((FCS AND D_Z2_OUT(3))
OR (Z3_DATA(31) AND RW AND NOT FCS AND LAN_ACCESS)
OR (NOT RW AND D_Z2_OUT(3))
OR (NOT LAN_ACCESS AND D_Z2_OUT(3)));
D(15) <= D_I(15) when D_OE(15) = '1' else 'Z';
D_OE(15) <= D_5_IOBUFE/D_5_IOBUFE_TRST;
DQ_I(0) <= (RESET AND DQ_DATA(0));
DQ(0) <= DQ_I(0) when DQ_OE(0) = '1' else 'Z';
DQ_OE(0) <= NOT DQ_12_IOBUFE/DQ_12_IOBUFE_TRST__$INT;
DQ_I(1) <= ((RESET AND DQ_DATA(1))
OR (NOT RESET AND LAN_D_INIT(1)));
DQ(1) <= DQ_I(1) when DQ_OE(1) = '1' else 'Z';
DQ_OE(1) <= NOT DQ_12_IOBUFE/DQ_12_IOBUFE_TRST__$INT;
DQ_I(2) <= (RESET AND DQ_DATA(2));
DQ(2) <= DQ_I(2) when DQ_OE(2) = '1' else 'Z';
DQ_OE(2) <= NOT DQ_12_IOBUFE/DQ_12_IOBUFE_TRST__$INT;
DQ_I(3) <= (RESET AND DQ_DATA(3));
DQ(3) <= DQ_I(3) when DQ_OE(3) = '1' else 'Z';
DQ_OE(3) <= NOT DQ_12_IOBUFE/DQ_12_IOBUFE_TRST__$INT;
DQ_I(4) <= ((RESET AND DQ_DATA(4))
OR (NOT RESET AND LAN_D_INIT(1)));
DQ(4) <= DQ_I(4) when DQ_OE(4) = '1' else 'Z';
DQ_OE(4) <= NOT DQ_12_IOBUFE/DQ_12_IOBUFE_TRST__$INT;
DQ_I(5) <= (RESET AND DQ_DATA(5));
DQ(5) <= DQ_I(5) when DQ_OE(5) = '1' else 'Z';
DQ_OE(5) <= NOT DQ_12_IOBUFE/DQ_12_IOBUFE_TRST__$INT;
DQ_I(6) <= (RESET AND DQ_DATA(6));
DQ(6) <= DQ_I(6) when DQ_OE(6) = '1' else 'Z';
DQ_OE(6) <= NOT DQ_12_IOBUFE/DQ_12_IOBUFE_TRST__$INT;
DQ_I(7) <= (RESET AND DQ_DATA(7));
DQ(7) <= DQ_I(7) when DQ_OE(7) = '1' else 'Z';
DQ_OE(7) <= NOT DQ_12_IOBUFE/DQ_12_IOBUFE_TRST__$INT;
DQ_I(8) <= ((RESET AND DQ_DATA(8))
OR (NOT RESET AND LAN_D_INIT(8)));
DQ(8) <= DQ_I(8) when DQ_OE(8) = '1' else 'Z';
DQ_OE(8) <= NOT DQ_12_IOBUFE/DQ_12_IOBUFE_TRST__$INT;
DQ_I(9) <= ((RESET AND DQ_DATA(9))
OR (NOT RESET AND LAN_D_INIT(1)));
DQ(9) <= DQ_I(9) when DQ_OE(9) = '1' else 'Z';
DQ_OE(9) <= NOT DQ_12_IOBUFE/DQ_12_IOBUFE_TRST__$INT;
DQ_I(10) <= ((RESET AND DQ_DATA(10))
OR (NOT RESET AND LAN_D_INIT(8)));
DQ(10) <= DQ_I(10) when DQ_OE(10) = '1' else 'Z';
DQ_OE(10) <= NOT DQ_12_IOBUFE/DQ_12_IOBUFE_TRST__$INT;
DQ_I(11) <= ((RESET AND DQ_DATA(11))
OR (NOT RESET AND LAN_D_INIT(8)));
DQ(11) <= DQ_I(11) when DQ_OE(11) = '1' else 'Z';
DQ_OE(11) <= NOT DQ_12_IOBUFE/DQ_12_IOBUFE_TRST__$INT;
DQ_I(12) <= (RESET AND DQ_DATA(12));
DQ(12) <= DQ_I(12) when DQ_OE(12) = '1' else 'Z';
DQ_OE(12) <= NOT DQ_12_IOBUFE/DQ_12_IOBUFE_TRST__$INT;
DQ_I(13) <= (RESET AND DQ_DATA(13));
DQ(13) <= DQ_I(13) when DQ_OE(13) = '1' else 'Z';
DQ_OE(13) <= NOT DQ_12_IOBUFE/DQ_12_IOBUFE_TRST__$INT;
DQ_I(14) <= (RESET AND DQ_DATA(14));
DQ(14) <= DQ_I(14) when DQ_OE(14) = '1' else 'Z';
DQ_OE(14) <= NOT DQ_12_IOBUFE/DQ_12_IOBUFE_TRST__$INT;
DQ_I(15) <= (RESET AND DQ_DATA(15));
DQ(15) <= DQ_I(15) when DQ_OE(15) = '1' else 'Z';
DQ_OE(15) <= NOT DQ_12_IOBUFE/DQ_12_IOBUFE_TRST__$INT;
DQ_12_IOBUFE/DQ_12_IOBUFE_TRST__$INT <= ((RESET AND FCS)
OR (RESET AND UDS AND LDS AND DS1 AND DS0)
OR (RESET AND RW)
OR (RESET AND NOT LAN_ACCESS));
FDCPE_DQ_DATA0: FDCPE port map (DQ_DATA(0),DQ_DATA_D(0),CLK_EXT,'0',LAN_SM_RST);
DQ_DATA_D(0) <= ((D(8).PIN AND NOT LDS AND DQ_SWAP AND NOT LAN_SM_FSM_FFd3 AND
NOT LAN_SM_FSM_FFd4)
OR (UDS AND LDS AND A(16).PIN AND DQ_SWAP AND
NOT LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd4)
OR (UDS AND LDS AND NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd3 AND
NOT LAN_SM_FSM_FFd4 AND A(8).PIN)
OR (D(8).PIN AND NOT UDS AND DQ_SWAP AND NOT LAN_SM_FSM_FFd3 AND
NOT LAN_SM_FSM_FFd4)
OR (NOT UDS AND NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd3 AND
NOT LAN_SM_FSM_FFd4 AND D(0).PIN)
OR (NOT LDS AND NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd3 AND
NOT LAN_SM_FSM_FFd4 AND D(0).PIN)
OR (A(16).PIN AND DQ_SWAP AND NOT LAN_SM_FSM_FFd4 AND
LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1)
OR (NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
NOT LAN_SM_FSM_FFd1 AND A(8).PIN)
OR (LAN_SM_FSM_FFd4 AND DQ_DATA(0))
OR (LAN_SM_FSM_FFd1 AND DQ_DATA(0))
OR (LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd2 AND DQ_DATA(0))
OR (NOT LAN_SM_FSM_FFd3 AND LAN_SM_FSM_FFd2 AND DQ_DATA(0)));
FDCPE_DQ_DATA1: FDCPE port map (DQ_DATA(1),DQ_DATA_D(1),CLK_EXT,'0',LAN_SM_RST);
DQ_DATA_D(1) <= ((EXP55_.EXP)
OR (LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd2 AND DQ_DATA(1))
OR (NOT LAN_SM_FSM_FFd3 AND LAN_SM_FSM_FFd2 AND DQ_DATA(1))
OR (NOT UDS AND NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd3 AND
NOT LAN_SM_FSM_FFd4 AND D(1).PIN)
OR (A(17).PIN AND DQ_SWAP AND NOT LAN_SM_FSM_FFd4 AND
LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1)
OR (NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
NOT LAN_SM_FSM_FFd1 AND A(9).PIN)
OR (LAN_SM_FSM_FFd4 AND DQ_DATA(1))
OR (LAN_SM_FSM_FFd1 AND DQ_DATA(1)));
FDCPE_DQ_DATA2: FDCPE port map (DQ_DATA(2),DQ_DATA_D(2),CLK_EXT,'0',LAN_SM_RST);
DQ_DATA_D(2) <= ((EXP61_.EXP)
OR (LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd2 AND DQ_DATA(2))
OR (NOT LAN_SM_FSM_FFd3 AND LAN_SM_FSM_FFd2 AND DQ_DATA(2))
OR (D(10).PIN AND NOT UDS AND DQ_SWAP AND NOT LAN_SM_FSM_FFd3 AND
NOT LAN_SM_FSM_FFd4)
OR (DQ_SWAP AND NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
NOT LAN_SM_FSM_FFd1 AND A(18).PIN)
OR (NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
NOT LAN_SM_FSM_FFd1 AND A(10).PIN)
OR (LAN_SM_FSM_FFd4 AND DQ_DATA(2))
OR (LAN_SM_FSM_FFd1 AND DQ_DATA(2)));
FDCPE_DQ_DATA3: FDCPE port map (DQ_DATA(3),DQ_DATA_D(3),CLK_EXT,'0',LAN_SM_RST);
DQ_DATA_D(3) <= ((EXP45_.EXP)
OR (LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd2 AND DQ_DATA(3))
OR (NOT LAN_SM_FSM_FFd3 AND LAN_SM_FSM_FFd2 AND DQ_DATA(3))
OR (D(11).PIN AND NOT UDS AND DQ_SWAP AND NOT LAN_SM_FSM_FFd3 AND
NOT LAN_SM_FSM_FFd4)
OR (A(19).PIN AND DQ_SWAP AND NOT LAN_SM_FSM_FFd4 AND
LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1)
OR (NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
NOT LAN_SM_FSM_FFd1 AND A(11).PIN)
OR (LAN_SM_FSM_FFd4 AND DQ_DATA(3))
OR (LAN_SM_FSM_FFd1 AND DQ_DATA(3)));
FDCPE_DQ_DATA4: FDCPE port map (DQ_DATA(4),DQ_DATA_D(4),CLK_EXT,'0',LAN_SM_RST);
DQ_DATA_D(4) <= ((D(12).PIN AND NOT UDS AND DQ_SWAP AND NOT LAN_SM_FSM_FFd3 AND
NOT LAN_SM_FSM_FFd4)
OR (DQ_SWAP AND NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
NOT LAN_SM_FSM_FFd1 AND A(20).PIN)
OR (NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
NOT LAN_SM_FSM_FFd1 AND A(12).PIN)
OR (D(12).PIN AND NOT LDS AND DQ_SWAP AND NOT LAN_SM_FSM_FFd3 AND
NOT LAN_SM_FSM_FFd4)
OR (NOT UDS AND NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd3 AND
NOT LAN_SM_FSM_FFd4 AND D(4).PIN)
OR (NOT LDS AND NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd3 AND
NOT LAN_SM_FSM_FFd4 AND D(4).PIN)
OR (UDS AND LDS AND DQ_SWAP AND NOT LAN_SM_FSM_FFd3 AND
NOT LAN_SM_FSM_FFd4 AND A(20).PIN)
OR (UDS AND LDS AND NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd3 AND
NOT LAN_SM_FSM_FFd4 AND A(12).PIN)
OR (LAN_SM_FSM_FFd4 AND DQ_DATA(4))
OR (LAN_SM_FSM_FFd1 AND DQ_DATA(4))
OR (LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd2 AND DQ_DATA(4))
OR (NOT LAN_SM_FSM_FFd3 AND LAN_SM_FSM_FFd2 AND DQ_DATA(4)));
FDCPE_DQ_DATA5: FDCPE port map (DQ_DATA(5),DQ_DATA_D(5),CLK_EXT,'0',LAN_SM_RST);
DQ_DATA_D(5) <= ((LAN_WRL_S.EXP)
OR (LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd2 AND DQ_DATA(5))
OR (D(13).PIN AND NOT UDS AND DQ_SWAP AND NOT LAN_SM_FSM_FFd3 AND
NOT LAN_SM_FSM_FFd4)
OR (D(13).PIN AND NOT LDS AND DQ_SWAP AND NOT LAN_SM_FSM_FFd3 AND
NOT LAN_SM_FSM_FFd4)
OR (A(21).PIN AND DQ_SWAP AND NOT LAN_SM_FSM_FFd4 AND
LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1)
OR (NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
NOT LAN_SM_FSM_FFd1 AND A(13).PIN)
OR (LAN_SM_FSM_FFd4 AND DQ_DATA(5))
OR (LAN_SM_FSM_FFd1 AND DQ_DATA(5))
OR (NOT LAN_SM_FSM_FFd3 AND LAN_SM_FSM_FFd2 AND DQ_DATA(5)));
FDCPE_DQ_DATA6: FDCPE port map (DQ_DATA(6),DQ_DATA_D(6),CLK_EXT,'0',LAN_SM_RST);
DQ_DATA_D(6) <= ((NOT LDS AND NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd3 AND
NOT LAN_SM_FSM_FFd4 AND D(6).PIN)
OR (UDS AND LDS AND NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd3 AND
NOT LAN_SM_FSM_FFd4 AND A(14).PIN)
OR (Z3_DATA(13).EXP)
OR (D(14).PIN AND NOT UDS AND DQ_SWAP AND NOT LAN_SM_FSM_FFd3 AND
NOT LAN_SM_FSM_FFd4)
OR (D(14).PIN AND NOT LDS AND DQ_SWAP AND NOT LAN_SM_FSM_FFd3 AND
NOT LAN_SM_FSM_FFd4)
OR (NOT UDS AND NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd3 AND
NOT LAN_SM_FSM_FFd4 AND D(6).PIN)
OR (A(22).PIN AND DQ_SWAP AND NOT LAN_SM_FSM_FFd4 AND
LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1)
OR (NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
NOT LAN_SM_FSM_FFd1 AND A(14).PIN)
OR (LAN_SM_FSM_FFd4 AND DQ_DATA(6))
OR (LAN_SM_FSM_FFd1 AND DQ_DATA(6))
OR (LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd2 AND DQ_DATA(6))
OR (NOT LAN_SM_FSM_FFd3 AND LAN_SM_FSM_FFd2 AND DQ_DATA(6)));
FDCPE_DQ_DATA7: FDCPE port map (DQ_DATA(7),DQ_DATA_D(7),CLK_EXT,'0',LAN_SM_RST);
DQ_DATA_D(7) <= ((EXP54_.EXP)
OR (LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd2 AND DQ_DATA(7))
OR (NOT LAN_SM_FSM_FFd3 AND LAN_SM_FSM_FFd2 AND DQ_DATA(7))
OR (D(15).PIN AND NOT UDS AND DQ_SWAP AND NOT LAN_SM_FSM_FFd3 AND
NOT LAN_SM_FSM_FFd4)
OR (A(23).PIN AND DQ_SWAP AND NOT LAN_SM_FSM_FFd4 AND
LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1)
OR (NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
NOT LAN_SM_FSM_FFd1 AND A(15).PIN)
OR (LAN_SM_FSM_FFd4 AND DQ_DATA(7))
OR (LAN_SM_FSM_FFd1 AND DQ_DATA(7)));
FDCPE_DQ_DATA8: FDCPE port map (DQ_DATA(8),DQ_DATA_D(8),CLK_EXT,'0',LAN_SM_RST);
DQ_DATA_D(8) <= ((ROM_B_0_OBUF.EXP)
OR (LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd2 AND DQ_DATA(8))
OR (NOT UDS AND DQ_SWAP AND NOT LAN_SM_FSM_FFd3 AND
NOT LAN_SM_FSM_FFd4 AND D(0).PIN)
OR (NOT LDS AND DQ_SWAP AND NOT LAN_SM_FSM_FFd3 AND
NOT LAN_SM_FSM_FFd4 AND D(0).PIN)
OR (A(16).PIN AND NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd4 AND
LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1)
OR (DQ_SWAP AND NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
NOT LAN_SM_FSM_FFd1 AND A(8).PIN)
OR (LAN_SM_FSM_FFd4 AND DQ_DATA(8))
OR (LAN_SM_FSM_FFd1 AND DQ_DATA(8))
OR (NOT LAN_SM_FSM_FFd3 AND LAN_SM_FSM_FFd2 AND DQ_DATA(8)));
FDCPE_DQ_DATA9: FDCPE port map (DQ_DATA(9),DQ_DATA_D(9),CLK_EXT,'0',LAN_SM_RST);
DQ_DATA_D(9) <= ((A(17).PIN AND NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd4 AND
LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1)
OR (DQ_SWAP AND NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
NOT LAN_SM_FSM_FFd1 AND A(9).PIN)
OR (Z3_DATA(2).EXP)
OR (D(9).PIN AND NOT UDS AND NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd3 AND
NOT LAN_SM_FSM_FFd4)
OR (D(9).PIN AND NOT LDS AND NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd3 AND
NOT LAN_SM_FSM_FFd4)
OR (NOT UDS AND DQ_SWAP AND NOT LAN_SM_FSM_FFd3 AND
NOT LAN_SM_FSM_FFd4 AND D(1).PIN)
OR (NOT LDS AND DQ_SWAP AND NOT LAN_SM_FSM_FFd3 AND
NOT LAN_SM_FSM_FFd4 AND D(1).PIN)
OR (UDS AND LDS AND A(17).PIN AND NOT DQ_SWAP AND
NOT LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd4)
OR (LAN_SM_FSM_FFd4 AND DQ_DATA(9))
OR (LAN_SM_FSM_FFd1 AND DQ_DATA(9))
OR (LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd2 AND DQ_DATA(9))
OR (NOT LAN_SM_FSM_FFd3 AND LAN_SM_FSM_FFd2 AND DQ_DATA(9)));
FDCPE_DQ_DATA10: FDCPE port map (DQ_DATA(10),DQ_DATA_D(10),CLK_EXT,'0',LAN_SM_RST);
DQ_DATA_D(10) <= ((Z3_DATA(16).EXP)
OR (D(10).PIN AND NOT UDS AND NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd3 AND
NOT LAN_SM_FSM_FFd4)
OR (D(10).PIN AND NOT LDS AND NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd3 AND
NOT LAN_SM_FSM_FFd4)
OR (NOT UDS AND DQ_SWAP AND NOT LAN_SM_FSM_FFd3 AND
NOT LAN_SM_FSM_FFd4 AND D(2).PIN)
OR (DQ_SWAP AND NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
NOT LAN_SM_FSM_FFd1 AND A(10).PIN)
OR (NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
NOT LAN_SM_FSM_FFd1 AND A(18).PIN)
OR (NOT LDS AND DQ_SWAP AND NOT LAN_SM_FSM_FFd3 AND
NOT LAN_SM_FSM_FFd4 AND D(2).PIN)
OR (UDS AND LDS AND DQ_SWAP AND NOT LAN_SM_FSM_FFd3 AND
NOT LAN_SM_FSM_FFd4 AND A(10).PIN)
OR (LAN_SM_FSM_FFd4 AND DQ_DATA(10))
OR (LAN_SM_FSM_FFd1 AND DQ_DATA(10))
OR (LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd2 AND DQ_DATA(10))
OR (NOT LAN_SM_FSM_FFd3 AND LAN_SM_FSM_FFd2 AND DQ_DATA(10)));
FDCPE_DQ_DATA11: FDCPE port map (DQ_DATA(11),DQ_DATA_D(11),CLK_EXT,'0',LAN_SM_RST);
DQ_DATA_D(11) <= ((Z3_DATA(23).EXP)
OR (D(11).PIN AND NOT UDS AND NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd3 AND
NOT LAN_SM_FSM_FFd4)
OR (D(11).PIN AND NOT LDS AND NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd3 AND
NOT LAN_SM_FSM_FFd4)
OR (NOT UDS AND DQ_SWAP AND NOT LAN_SM_FSM_FFd3 AND
NOT LAN_SM_FSM_FFd4 AND D(3).PIN)
OR (A(19).PIN AND NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd4 AND
LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1)
OR (DQ_SWAP AND NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
NOT LAN_SM_FSM_FFd1 AND A(11).PIN)
OR (NOT LDS AND DQ_SWAP AND NOT LAN_SM_FSM_FFd3 AND
NOT LAN_SM_FSM_FFd4 AND D(3).PIN)
OR (UDS AND LDS AND DQ_SWAP AND NOT LAN_SM_FSM_FFd3 AND
NOT LAN_SM_FSM_FFd4 AND A(11).PIN)
OR (LAN_SM_FSM_FFd4 AND DQ_DATA(11))
OR (LAN_SM_FSM_FFd1 AND DQ_DATA(11))
OR (LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd2 AND DQ_DATA(11))
OR (NOT LAN_SM_FSM_FFd3 AND LAN_SM_FSM_FFd2 AND DQ_DATA(11)));
FDCPE_DQ_DATA12: FDCPE port map (DQ_DATA(12),DQ_DATA_D(12),CLK_EXT,'0',LAN_SM_RST);
DQ_DATA_D(12) <= ((CP_RD_OBUF.EXP)
OR (LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd2 AND DQ_DATA(12))
OR (NOT LAN_SM_FSM_FFd3 AND LAN_SM_FSM_FFd2 AND DQ_DATA(12))
OR (D(12).PIN AND NOT UDS AND NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd3 AND
NOT LAN_SM_FSM_FFd4)
OR (DQ_SWAP AND NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
NOT LAN_SM_FSM_FFd1 AND A(12).PIN)
OR (NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
NOT LAN_SM_FSM_FFd1 AND A(20).PIN)
OR (LAN_SM_FSM_FFd4 AND DQ_DATA(12))
OR (LAN_SM_FSM_FFd1 AND DQ_DATA(12)));
FDCPE_DQ_DATA13: FDCPE port map (DQ_DATA(13),DQ_DATA_D(13),CLK_EXT,'0',LAN_SM_RST);
DQ_DATA_D(13) <= ((A(21).PIN AND NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd4 AND
LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1)
OR (DQ_SWAP AND NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
NOT LAN_SM_FSM_FFd1 AND A(13).PIN)
OR (LAN_WRL_OBUF.EXP)
OR (D(13).PIN AND NOT UDS AND NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd3 AND
NOT LAN_SM_FSM_FFd4)
OR (D(13).PIN AND NOT LDS AND NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd3 AND
NOT LAN_SM_FSM_FFd4)
OR (NOT UDS AND DQ_SWAP AND NOT LAN_SM_FSM_FFd3 AND
NOT LAN_SM_FSM_FFd4 AND D(5).PIN)
OR (NOT LDS AND DQ_SWAP AND NOT LAN_SM_FSM_FFd3 AND
NOT LAN_SM_FSM_FFd4 AND D(5).PIN)
OR (UDS AND LDS AND DQ_SWAP AND NOT LAN_SM_FSM_FFd3 AND
NOT LAN_SM_FSM_FFd4 AND A(13).PIN)
OR (LAN_SM_FSM_FFd4 AND DQ_DATA(13))
OR (LAN_SM_FSM_FFd1 AND DQ_DATA(13))
OR (LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd2 AND DQ_DATA(13))
OR (NOT LAN_SM_FSM_FFd3 AND LAN_SM_FSM_FFd2 AND DQ_DATA(13)));
FDCPE_DQ_DATA14: FDCPE port map (DQ_DATA(14),DQ_DATA_D(14),CLK_EXT,'0',LAN_SM_RST);
DQ_DATA_D(14) <= ((A(22).PIN AND NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd4 AND
LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1)
OR (DQ_SWAP AND NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
NOT LAN_SM_FSM_FFd1 AND A(14).PIN)
OR (DQ_DATA(15).EXP)
OR (D(14).PIN AND NOT UDS AND NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd3 AND
NOT LAN_SM_FSM_FFd4)
OR (D(14).PIN AND NOT LDS AND NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd3 AND
NOT LAN_SM_FSM_FFd4)
OR (NOT UDS AND DQ_SWAP AND NOT LAN_SM_FSM_FFd3 AND
NOT LAN_SM_FSM_FFd4 AND D(6).PIN)
OR (NOT LDS AND DQ_SWAP AND NOT LAN_SM_FSM_FFd3 AND
NOT LAN_SM_FSM_FFd4 AND D(6).PIN)
OR (UDS AND LDS AND DQ_SWAP AND NOT LAN_SM_FSM_FFd3 AND
NOT LAN_SM_FSM_FFd4 AND A(14).PIN)
OR (LAN_SM_FSM_FFd4 AND DQ_DATA(14))
OR (LAN_SM_FSM_FFd1 AND DQ_DATA(14))
OR (LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd2 AND DQ_DATA(14))
OR (NOT LAN_SM_FSM_FFd3 AND LAN_SM_FSM_FFd2 AND DQ_DATA(14)));
FDCPE_DQ_DATA15: FDCPE port map (DQ_DATA(15),DQ_DATA_D(15),CLK_EXT,'0',LAN_SM_RST);
DQ_DATA_D(15) <= ((ROM_B_0_OBUF$BUF9.EXP)
OR (LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd2 AND DQ_DATA(15))
OR (D(15).PIN AND NOT UDS AND NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd3 AND
NOT LAN_SM_FSM_FFd4)
OR (D(15).PIN AND NOT LDS AND NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd3 AND
NOT LAN_SM_FSM_FFd4)
OR (A(23).PIN AND NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd4 AND
LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1)
OR (DQ_SWAP AND NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
NOT LAN_SM_FSM_FFd1 AND A(15).PIN)
OR (LAN_SM_FSM_FFd4 AND DQ_DATA(15))
OR (LAN_SM_FSM_FFd1 AND DQ_DATA(15))
OR (NOT LAN_SM_FSM_FFd3 AND LAN_SM_FSM_FFd2 AND DQ_DATA(15)));
FDCPE_DQ_SWAP: FDCPE port map (DQ_SWAP,DQ_SWAP_D,NOT FCS,'0',NOT RESET);
DQ_SWAP_D <= ((NOT Z3)
OR (SHUT_UP_Z2(0))
OR ($OpTx$INV$129)
OR (NOT A(13).PIN)
OR (NOT A(14).PIN)
OR (A_LAN_5_OBUF.EXP)
OR (D(9).PIN AND NOT LAN_BASEADR(9))
OR (NOT D(9).PIN AND LAN_BASEADR(9))
OR (D(11).PIN AND NOT LAN_BASEADR(11))
OR (EXP26_.EXP)
OR (D(10).PIN AND NOT LAN_BASEADR(10))
OR (NOT D(10).PIN AND LAN_BASEADR(10))
OR (NOT D(11).PIN AND LAN_BASEADR(11))
OR (D(15).PIN AND NOT LAN_BASEADR(15))
OR (NOT D(15).PIN AND LAN_BASEADR(15)));
DTACK_I <= '0';
DTACK <= DTACK_I when DTACK_OE = '1' else 'Z';
DTACK_OE <= ROM_B_0_OBUF$BUF9/ROM_B_0_OBUF$BUF9_TRST;
D_5_IOBUFE/D_5_IOBUFE_TRST <= ((NOT AS AND RW AND AUTOCONFIG_Z2_ACCESS)
OR (RW AND NOT FCS AND LAN_ACCESS));
FDCPE_D_Z2_OUT0: FDCPE port map (D_Z2_OUT(0),D_Z2_OUT_D(0),SHUT_UP_Z2(1)/SHUT_UP_Z2(1)_CLKF,'0',NOT RESET);
D_Z2_OUT_D(0) <= ((AS)
OR (A(6))
OR (NOT AUTOCONFIG_Z2_ACCESS)
OR (Z3_ADR(13).EXP)
OR (A(5) AND A(4))
OR (A(5) AND NOT A(2))
OR (UDS AND LDS)
OR (NOT A(5) AND NOT A(4) AND A(3))
OR (A(4) AND A(1) AND NOT A(3))
OR (Z3_ADR(2).EXP)
OR (A(4) AND NOT A(2) AND NOT A(3))
OR (NOT A(4) AND NOT A(2) AND A(1))
OR (NOT A(4) AND NOT AUTO_CONFIG_Z2_DONE(0) AND A(3))
OR (NOT A(4) AND AUTO_CONFIG_Z2_DONE(1) AND A(3))
OR (A(2) AND NOT A(1) AND A(3)));
FDCPE_D_Z2_OUT1: FDCPE port map (D_Z2_OUT(1),D_Z2_OUT_D(1),SHUT_UP_Z2(1)/SHUT_UP_Z2(1)_CLKF,'0',NOT RESET);
D_Z2_OUT_D(1) <= ((A(6))
OR (NOT AUTOCONFIG_Z2_ACCESS)
OR (A(4) AND A(2) AND NOT AUTO_CONFIG_Z2_DONE(1) AND NOT A(3))
OR (A(4) AND NOT A(2) AND NOT A(1) AND NOT A(3))
OR (AS)
OR (CP_WE_S.EXP)
OR (A(5) AND A(4))
OR (A(5) AND NOT A(2))
OR (A(5) AND A(1))
OR (NOT A(4) AND A(3))
OR (A(4) AND A(2) AND NOT AUTO_CONFIG_Z2_DONE(0) AND NOT A(3))
OR (A(4) AND A(1) AND AUTO_CONFIG_Z2_DONE(0) AND
AUTO_CONFIG_Z2_DONE(1) AND NOT A(3))
OR (A(2) AND A(1) AND AUTO_CONFIG_Z2_DONE(0) AND
NOT AUTO_CONFIG_Z2_DONE(1) AND NOT A(3)));
FDCPE_D_Z2_OUT2: FDCPE port map (D_Z2_OUT(2),D_Z2_OUT_D(2),SHUT_UP_Z2(1)/SHUT_UP_Z2(1)_CLKF,'0',NOT RESET);
D_Z2_OUT_D(2) <= ((AS)
OR (A(6))
OR (NOT AUTOCONFIG_Z2_ACCESS)
OR (A(5) AND A(4))
OR (A(5) AND NOT A(2))
OR (A(4) AND NOT A(2))
OR (NOT A(4) AND A(3))
OR (A(1) AND A(3))
OR (SLAVE_OBUF.EXP)
OR (A(5) AND NOT A(1))
OR (UDS AND LDS)
OR (A(4) AND NOT A(1) AND NOT A(3))
OR (NOT A(2) AND NOT A(1) AND AUTO_CONFIG_Z2_DONE(0))
OR (NOT A(4) AND NOT A(1) AND AUTO_CONFIG_Z2_DONE(0) AND
AUTO_CONFIG_Z2_DONE(1)));
FDCPE_D_Z2_OUT3: FDCPE port map (D_Z2_OUT(3),D_Z2_OUT_D(3),SHUT_UP_Z2(1)/SHUT_UP_Z2(1)_CLKF,'0',NOT RESET);
D_Z2_OUT_D(3) <= ((EXP49_.EXP)
OR (NOT A(5) AND NOT A(2) AND A(1) AND NOT AS AND NOT UDS AND NOT A(6) AND NOT A(3) AND
AUTOCONFIG_Z2_ACCESS)
OR (NOT A(5) AND NOT A(2) AND A(1) AND NOT AS AND NOT LDS AND NOT A(6) AND NOT A(3) AND
AUTOCONFIG_Z2_ACCESS)
OR (NOT A(5) AND A(1) AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(0) AND
NOT UDS AND NOT A(6) AND NOT A(3) AND AUTOCONFIG_Z2_ACCESS)
OR (NOT A(5) AND A(1) AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(1) AND
NOT UDS AND NOT A(6) AND NOT A(3) AND AUTOCONFIG_Z2_ACCESS)
OR (NOT A(5) AND A(1) AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(1) AND
NOT LDS AND NOT A(6) AND NOT A(3) AND AUTOCONFIG_Z2_ACCESS)
OR (NOT A(5) AND A(4) AND A(2) AND A(1) AND NOT AS AND NOT UDS AND NOT A(6) AND
AUTOCONFIG_Z2_ACCESS)
OR (NOT A(5) AND A(4) AND A(2) AND A(1) AND NOT AS AND NOT LDS AND NOT A(6) AND
AUTOCONFIG_Z2_ACCESS));
IDE_A(0) <= A(9).PIN;
IDE_A(1) <= A(10).PIN;
IDE_A(2) <= A(11).PIN;
FDCPE_IDE_ACCESS: FDCPE port map (IDE_ACCESS,IDE_ACCESS_D,NOT AS,NOT RESET,'0');
IDE_ACCESS_D <= ((SHUT_UP_Z2(1))
OR (LAN_RST_SM_FSM_FFd1.EXP)
OR (IDE_BASEADR(1) AND NOT A(17).PIN)
OR (NOT IDE_BASEADR(1) AND A(17).PIN)
OR (IDE_BASEADR(2) AND NOT A(18).PIN)
OR (NOT IDE_BASEADR(2) AND A(18).PIN)
OR (NOT IDE_BASEADR(7) AND A(23).PIN)
OR (LAN_RST_SM_FSM_FFd2.EXP)
OR (IDE_BASEADR(4) AND NOT A(20).PIN)
OR (NOT IDE_BASEADR(4) AND A(20).PIN)
OR (IDE_BASEADR(5) AND NOT A(21).PIN)
OR (NOT IDE_BASEADR(5) AND A(21).PIN)
OR (IDE_BASEADR(7) AND NOT A(23).PIN)
OR (IDE_BASEADR(0) AND NOT A(16).PIN)
OR (NOT IDE_BASEADR(0) AND A(16).PIN));
FTCPE_IDE_BASEADR0: FTCPE port map (IDE_BASEADR(0),IDE_BASEADR_T(0),SHUT_UP_Z2(1)/SHUT_UP_Z2(1)_CLKF,'0',NOT RESET);
IDE_BASEADR_T(0) <= ((NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
AUTO_CONFIG_Z2_DONE(0) AND AUTO_CONFIG_Z2_DONE(1) AND NOT AUTO_CONFIG_Z2_DONE(2) AND
D(8).PIN AND NOT IDE_BASEADR(0) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND
AUTOCONFIG_Z2_ACCESS)
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
AUTO_CONFIG_Z2_DONE(0) AND AUTO_CONFIG_Z2_DONE(1) AND NOT AUTO_CONFIG_Z2_DONE(2) AND
D(8).PIN AND NOT IDE_BASEADR(0) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND
AUTOCONFIG_Z2_ACCESS)
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
AUTO_CONFIG_Z2_DONE(0) AND AUTO_CONFIG_Z2_DONE(1) AND NOT AUTO_CONFIG_Z2_DONE(2) AND
NOT D(8).PIN AND IDE_BASEADR(0) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND
AUTOCONFIG_Z2_ACCESS)
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
AUTO_CONFIG_Z2_DONE(0) AND AUTO_CONFIG_Z2_DONE(1) AND NOT AUTO_CONFIG_Z2_DONE(2) AND
NOT D(8).PIN AND IDE_BASEADR(0) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND
AUTOCONFIG_Z2_ACCESS));
FTCPE_IDE_BASEADR1: FTCPE port map (IDE_BASEADR(1),IDE_BASEADR_T(1),SHUT_UP_Z2(1)/SHUT_UP_Z2(1)_CLKF,'0',NOT RESET);
IDE_BASEADR_T(1) <= ((NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
AUTO_CONFIG_Z2_DONE(0) AND AUTO_CONFIG_Z2_DONE(1) AND NOT AUTO_CONFIG_Z2_DONE(2) AND
D(9).PIN AND NOT IDE_BASEADR(1) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND
AUTOCONFIG_Z2_ACCESS)
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
AUTO_CONFIG_Z2_DONE(0) AND AUTO_CONFIG_Z2_DONE(1) AND NOT AUTO_CONFIG_Z2_DONE(2) AND
D(9).PIN AND NOT IDE_BASEADR(1) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND
AUTOCONFIG_Z2_ACCESS)
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
AUTO_CONFIG_Z2_DONE(0) AND AUTO_CONFIG_Z2_DONE(1) AND NOT AUTO_CONFIG_Z2_DONE(2) AND
NOT D(9).PIN AND IDE_BASEADR(1) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND
AUTOCONFIG_Z2_ACCESS)
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
AUTO_CONFIG_Z2_DONE(0) AND AUTO_CONFIG_Z2_DONE(1) AND NOT AUTO_CONFIG_Z2_DONE(2) AND
NOT D(9).PIN AND IDE_BASEADR(1) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND
AUTOCONFIG_Z2_ACCESS));
FTCPE_IDE_BASEADR2: FTCPE port map (IDE_BASEADR(2),IDE_BASEADR_T(2),SHUT_UP_Z2(1)/SHUT_UP_Z2(1)_CLKF,'0',NOT RESET);
IDE_BASEADR_T(2) <= ((NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
AUTO_CONFIG_Z2_DONE(0) AND AUTO_CONFIG_Z2_DONE(1) AND NOT AUTO_CONFIG_Z2_DONE(2) AND
D(10).PIN AND NOT IDE_BASEADR(2) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND
AUTOCONFIG_Z2_ACCESS)
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
AUTO_CONFIG_Z2_DONE(0) AND AUTO_CONFIG_Z2_DONE(1) AND NOT AUTO_CONFIG_Z2_DONE(2) AND
D(10).PIN AND NOT IDE_BASEADR(2) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND
AUTOCONFIG_Z2_ACCESS)
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
AUTO_CONFIG_Z2_DONE(0) AND AUTO_CONFIG_Z2_DONE(1) AND NOT AUTO_CONFIG_Z2_DONE(2) AND
NOT D(10).PIN AND IDE_BASEADR(2) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND
AUTOCONFIG_Z2_ACCESS)
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
AUTO_CONFIG_Z2_DONE(0) AND AUTO_CONFIG_Z2_DONE(1) AND NOT AUTO_CONFIG_Z2_DONE(2) AND
NOT D(10).PIN AND IDE_BASEADR(2) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND
AUTOCONFIG_Z2_ACCESS));
FTCPE_IDE_BASEADR3: FTCPE port map (IDE_BASEADR(3),IDE_BASEADR_T(3),SHUT_UP_Z2(1)/SHUT_UP_Z2(1)_CLKF,'0',NOT RESET);
IDE_BASEADR_T(3) <= ((NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
AUTO_CONFIG_Z2_DONE(0) AND AUTO_CONFIG_Z2_DONE(1) AND NOT AUTO_CONFIG_Z2_DONE(2) AND
D(11).PIN AND NOT IDE_BASEADR(3) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND
AUTOCONFIG_Z2_ACCESS)
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
AUTO_CONFIG_Z2_DONE(0) AND AUTO_CONFIG_Z2_DONE(1) AND NOT AUTO_CONFIG_Z2_DONE(2) AND
D(11).PIN AND NOT IDE_BASEADR(3) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND
AUTOCONFIG_Z2_ACCESS)
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
AUTO_CONFIG_Z2_DONE(0) AND AUTO_CONFIG_Z2_DONE(1) AND NOT AUTO_CONFIG_Z2_DONE(2) AND
NOT D(11).PIN AND IDE_BASEADR(3) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND
AUTOCONFIG_Z2_ACCESS)
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
AUTO_CONFIG_Z2_DONE(0) AND AUTO_CONFIG_Z2_DONE(1) AND NOT AUTO_CONFIG_Z2_DONE(2) AND
NOT D(11).PIN AND IDE_BASEADR(3) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND
AUTOCONFIG_Z2_ACCESS));
FTCPE_IDE_BASEADR4: FTCPE port map (IDE_BASEADR(4),IDE_BASEADR_T(4),SHUT_UP_Z2(1)/SHUT_UP_Z2(1)_CLKF,'0',NOT RESET);
IDE_BASEADR_T(4) <= ((NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
AUTO_CONFIG_Z2_DONE(0) AND AUTO_CONFIG_Z2_DONE(1) AND NOT AUTO_CONFIG_Z2_DONE(2) AND
D(12).PIN AND NOT IDE_BASEADR(4) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND
AUTOCONFIG_Z2_ACCESS)
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
AUTO_CONFIG_Z2_DONE(0) AND AUTO_CONFIG_Z2_DONE(1) AND NOT AUTO_CONFIG_Z2_DONE(2) AND
D(12).PIN AND NOT IDE_BASEADR(4) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND
AUTOCONFIG_Z2_ACCESS)
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
AUTO_CONFIG_Z2_DONE(0) AND AUTO_CONFIG_Z2_DONE(1) AND NOT AUTO_CONFIG_Z2_DONE(2) AND
NOT D(12).PIN AND IDE_BASEADR(4) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND
AUTOCONFIG_Z2_ACCESS)
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
AUTO_CONFIG_Z2_DONE(0) AND AUTO_CONFIG_Z2_DONE(1) AND NOT AUTO_CONFIG_Z2_DONE(2) AND
NOT D(12).PIN AND IDE_BASEADR(4) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND
AUTOCONFIG_Z2_ACCESS));
FTCPE_IDE_BASEADR5: FTCPE port map (IDE_BASEADR(5),IDE_BASEADR_T(5),SHUT_UP_Z2(1)/SHUT_UP_Z2(1)_CLKF,'0',NOT RESET);
IDE_BASEADR_T(5) <= ((NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
AUTO_CONFIG_Z2_DONE(0) AND AUTO_CONFIG_Z2_DONE(1) AND NOT AUTO_CONFIG_Z2_DONE(2) AND
D(13).PIN AND NOT IDE_BASEADR(5) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND
AUTOCONFIG_Z2_ACCESS)
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
AUTO_CONFIG_Z2_DONE(0) AND AUTO_CONFIG_Z2_DONE(1) AND NOT AUTO_CONFIG_Z2_DONE(2) AND
D(13).PIN AND NOT IDE_BASEADR(5) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND
AUTOCONFIG_Z2_ACCESS)
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
AUTO_CONFIG_Z2_DONE(0) AND AUTO_CONFIG_Z2_DONE(1) AND NOT AUTO_CONFIG_Z2_DONE(2) AND
NOT D(13).PIN AND IDE_BASEADR(5) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND
AUTOCONFIG_Z2_ACCESS)
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
AUTO_CONFIG_Z2_DONE(0) AND AUTO_CONFIG_Z2_DONE(1) AND NOT AUTO_CONFIG_Z2_DONE(2) AND
NOT D(13).PIN AND IDE_BASEADR(5) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND
AUTOCONFIG_Z2_ACCESS));
FTCPE_IDE_BASEADR6: FTCPE port map (IDE_BASEADR(6),IDE_BASEADR_T(6),SHUT_UP_Z2(1)/SHUT_UP_Z2(1)_CLKF,'0',NOT RESET);
IDE_BASEADR_T(6) <= ((NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
AUTO_CONFIG_Z2_DONE(0) AND AUTO_CONFIG_Z2_DONE(1) AND NOT AUTO_CONFIG_Z2_DONE(2) AND
D(14).PIN AND NOT IDE_BASEADR(6) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND
AUTOCONFIG_Z2_ACCESS)
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
AUTO_CONFIG_Z2_DONE(0) AND AUTO_CONFIG_Z2_DONE(1) AND NOT AUTO_CONFIG_Z2_DONE(2) AND
D(14).PIN AND NOT IDE_BASEADR(6) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND
AUTOCONFIG_Z2_ACCESS)
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
AUTO_CONFIG_Z2_DONE(0) AND AUTO_CONFIG_Z2_DONE(1) AND NOT AUTO_CONFIG_Z2_DONE(2) AND
NOT D(14).PIN AND IDE_BASEADR(6) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND
AUTOCONFIG_Z2_ACCESS)
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
AUTO_CONFIG_Z2_DONE(0) AND AUTO_CONFIG_Z2_DONE(1) AND NOT AUTO_CONFIG_Z2_DONE(2) AND
NOT D(14).PIN AND IDE_BASEADR(6) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND
AUTOCONFIG_Z2_ACCESS));
FTCPE_IDE_BASEADR7: FTCPE port map (IDE_BASEADR(7),IDE_BASEADR_T(7),SHUT_UP_Z2(1)/SHUT_UP_Z2(1)_CLKF,'0',NOT RESET);
IDE_BASEADR_T(7) <= ((NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
AUTO_CONFIG_Z2_DONE(0) AND AUTO_CONFIG_Z2_DONE(1) AND NOT AUTO_CONFIG_Z2_DONE(2) AND
D(15).PIN AND NOT IDE_BASEADR(7) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND
AUTOCONFIG_Z2_ACCESS)
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
AUTO_CONFIG_Z2_DONE(0) AND AUTO_CONFIG_Z2_DONE(1) AND NOT AUTO_CONFIG_Z2_DONE(2) AND
D(15).PIN AND NOT IDE_BASEADR(7) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND
AUTOCONFIG_Z2_ACCESS)
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
AUTO_CONFIG_Z2_DONE(0) AND AUTO_CONFIG_Z2_DONE(1) AND NOT AUTO_CONFIG_Z2_DONE(2) AND
NOT D(15).PIN AND IDE_BASEADR(7) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND
AUTOCONFIG_Z2_ACCESS)
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
AUTO_CONFIG_Z2_DONE(0) AND AUTO_CONFIG_Z2_DONE(1) AND NOT AUTO_CONFIG_Z2_DONE(2) AND
NOT D(15).PIN AND IDE_BASEADR(7) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND
AUTOCONFIG_Z2_ACCESS));
IDE_CS(0) <= NOT A(12).PIN;
IDE_CS(1) <= NOT A(13).PIN;
FDCPE_IDE_ENABLE: FDCPE port map (IDE_ENABLE,'0',SHUT_UP_Z2(1)/SHUT_UP_Z2(1)_CLKF,'0',NOT RESET,IDE_ENABLE_CE);
IDE_ENABLE_CE <= (NOT AS AND NOT RW AND IDE_ACCESS);
IDE_R <= NOT ((NOT AS AND NOT IDE_R_S));
FDCPE_IDE_R_S: FDCPE port map (IDE_R_S,IDE_R_S_D,SHUT_UP_Z2(1)/SHUT_UP_Z2(1)_CLKF,'0',NOT RESET);
IDE_R_S_D <= (NOT AS AND RW AND IDE_ACCESS AND NOT IDE_ENABLE);
IDE_W <= NOT ((NOT AS AND NOT IDE_W_S));
FDCPE_IDE_W_S: FDCPE port map (IDE_W_S,IDE_W_S_D,SHUT_UP_Z2(1)/SHUT_UP_Z2(1)_CLKF,'0',NOT RESET);
IDE_W_S_D <= (NOT AS AND NOT RW AND IDE_ACCESS);
INT_OUT_I <= '0';
INT_OUT <= INT_OUT_I when INT_OUT_OE = '1' else 'Z';
INT_OUT_OE <= ROM_B_0_OBUF$BUF8/ROM_B_0_OBUF$BUF8_TRST;
FDCPE_LAN_ACCESS: FDCPE port map (LAN_ACCESS,LAN_ACCESS_D,NOT FCS,NOT RESET,'0');
LAN_ACCESS_D <= ((NOT Z3)
OR (SHUT_UP_Z2(0))
OR ($OpTx$INV$129)
OR (A_LAN_3_OBUF.EXP)
OR (D(9).PIN AND NOT LAN_BASEADR(9))
OR (NOT D(9).PIN AND LAN_BASEADR(9))
OR (D(11).PIN AND NOT LAN_BASEADR(11))
OR (NOT D(11).PIN AND LAN_BASEADR(11))
OR (D(15).PIN AND NOT LAN_BASEADR(15))
OR (A_LAN_2_OBUF.EXP)
OR (D(10).PIN AND NOT LAN_BASEADR(10))
OR (NOT D(10).PIN AND LAN_BASEADR(10))
OR (D(12).PIN AND NOT LAN_BASEADR(12))
OR (NOT D(12).PIN AND LAN_BASEADR(12))
OR (NOT D(15).PIN AND LAN_BASEADR(15)));
FDCPE_LAN_A_INIT3: FDCPE port map (LAN_A_INIT(3),'0',CLK_EXT,'0',RESET);
FDCPE_LAN_A_INIT6: FDCPE port map (LAN_A_INIT(6),LAN_A_INIT_D(6),CLK_EXT,'0',RESET);
LAN_A_INIT_D(6) <= ((LAN_RST_SM_FSM_FFd3 AND LAN_RST_SM_FSM_FFd1)
OR (NOT LAN_RST_SM_FSM_FFd3 AND NOT LAN_RST_SM_FSM_FFd2));
FTCPE_LAN_BASEADR0: FTCPE port map (LAN_BASEADR(0),LAN_BASEADR_T(0),SHUT_UP_Z2(1)/SHUT_UP_Z2(1)_CLKF,'0',NOT RESET);
LAN_BASEADR_T(0) <= ((NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
NOT AUTO_CONFIG_Z2_DONE(0) AND D(8).PIN AND NOT LAN_BASEADR(0) AND NOT UDS AND A(6) AND A(3) AND
NOT RW AND AUTOCONFIG_Z2_ACCESS)
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
NOT AUTO_CONFIG_Z2_DONE(0) AND D(8).PIN AND NOT LAN_BASEADR(0) AND NOT LDS AND A(6) AND A(3) AND
NOT RW AND AUTOCONFIG_Z2_ACCESS)
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
NOT AUTO_CONFIG_Z2_DONE(0) AND NOT D(8).PIN AND LAN_BASEADR(0) AND NOT LDS AND A(6) AND A(3) AND
NOT RW AND AUTOCONFIG_Z2_ACCESS)
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
NOT AUTO_CONFIG_Z2_DONE(0) AND NOT D(8).PIN AND LAN_BASEADR(0) AND NOT UDS AND A(6) AND A(3) AND
NOT RW AND AUTOCONFIG_Z2_ACCESS));
FTCPE_LAN_BASEADR1: FTCPE port map (LAN_BASEADR(1),LAN_BASEADR_T(1),SHUT_UP_Z2(1)/SHUT_UP_Z2(1)_CLKF,'0',NOT RESET);
LAN_BASEADR_T(1) <= ((NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
NOT AUTO_CONFIG_Z2_DONE(0) AND D(9).PIN AND NOT LAN_BASEADR(1) AND NOT LDS AND A(6) AND A(3) AND
NOT RW AND AUTOCONFIG_Z2_ACCESS)
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
NOT AUTO_CONFIG_Z2_DONE(0) AND D(9).PIN AND NOT LAN_BASEADR(1) AND NOT UDS AND A(6) AND A(3) AND
NOT RW AND AUTOCONFIG_Z2_ACCESS)
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
NOT AUTO_CONFIG_Z2_DONE(0) AND NOT D(9).PIN AND LAN_BASEADR(1) AND NOT UDS AND A(6) AND A(3) AND
NOT RW AND AUTOCONFIG_Z2_ACCESS)
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
NOT AUTO_CONFIG_Z2_DONE(0) AND NOT D(9).PIN AND LAN_BASEADR(1) AND NOT LDS AND A(6) AND A(3) AND
NOT RW AND AUTOCONFIG_Z2_ACCESS));
FTCPE_LAN_BASEADR2: FTCPE port map (LAN_BASEADR(2),LAN_BASEADR_T(2),SHUT_UP_Z2(1)/SHUT_UP_Z2(1)_CLKF,'0',NOT RESET);
LAN_BASEADR_T(2) <= ((NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
NOT AUTO_CONFIG_Z2_DONE(0) AND D(10).PIN AND NOT LAN_BASEADR(2) AND NOT UDS AND A(6) AND A(3) AND
NOT RW AND AUTOCONFIG_Z2_ACCESS)
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
NOT AUTO_CONFIG_Z2_DONE(0) AND D(10).PIN AND NOT LAN_BASEADR(2) AND NOT LDS AND A(6) AND A(3) AND
NOT RW AND AUTOCONFIG_Z2_ACCESS)
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
NOT AUTO_CONFIG_Z2_DONE(0) AND NOT D(10).PIN AND LAN_BASEADR(2) AND NOT UDS AND A(6) AND A(3) AND
NOT RW AND AUTOCONFIG_Z2_ACCESS)
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
NOT AUTO_CONFIG_Z2_DONE(0) AND NOT D(10).PIN AND LAN_BASEADR(2) AND NOT LDS AND A(6) AND A(3) AND
NOT RW AND AUTOCONFIG_Z2_ACCESS));
FTCPE_LAN_BASEADR3: FTCPE port map (LAN_BASEADR(3),LAN_BASEADR_T(3),SHUT_UP_Z2(1)/SHUT_UP_Z2(1)_CLKF,'0',NOT RESET);
LAN_BASEADR_T(3) <= ((NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
NOT AUTO_CONFIG_Z2_DONE(0) AND D(11).PIN AND NOT LAN_BASEADR(3) AND NOT LDS AND A(6) AND A(3) AND
NOT RW AND AUTOCONFIG_Z2_ACCESS)
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
NOT AUTO_CONFIG_Z2_DONE(0) AND D(11).PIN AND NOT LAN_BASEADR(3) AND NOT UDS AND A(6) AND A(3) AND
NOT RW AND AUTOCONFIG_Z2_ACCESS)
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
NOT AUTO_CONFIG_Z2_DONE(0) AND NOT D(11).PIN AND LAN_BASEADR(3) AND NOT UDS AND A(6) AND A(3) AND
NOT RW AND AUTOCONFIG_Z2_ACCESS)
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
NOT AUTO_CONFIG_Z2_DONE(0) AND NOT D(11).PIN AND LAN_BASEADR(3) AND NOT LDS AND A(6) AND A(3) AND
NOT RW AND AUTOCONFIG_Z2_ACCESS));
FTCPE_LAN_BASEADR4: FTCPE port map (LAN_BASEADR(4),LAN_BASEADR_T(4),SHUT_UP_Z2(1)/SHUT_UP_Z2(1)_CLKF,'0',NOT RESET);
LAN_BASEADR_T(4) <= ((NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
NOT AUTO_CONFIG_Z2_DONE(0) AND D(12).PIN AND NOT LAN_BASEADR(4) AND NOT LDS AND A(6) AND A(3) AND
NOT RW AND AUTOCONFIG_Z2_ACCESS)
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
NOT AUTO_CONFIG_Z2_DONE(0) AND D(12).PIN AND NOT LAN_BASEADR(4) AND NOT UDS AND A(6) AND A(3) AND
NOT RW AND AUTOCONFIG_Z2_ACCESS)
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
NOT AUTO_CONFIG_Z2_DONE(0) AND NOT D(12).PIN AND LAN_BASEADR(4) AND NOT UDS AND A(6) AND A(3) AND
NOT RW AND AUTOCONFIG_Z2_ACCESS)
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
NOT AUTO_CONFIG_Z2_DONE(0) AND NOT D(12).PIN AND LAN_BASEADR(4) AND NOT LDS AND A(6) AND A(3) AND
NOT RW AND AUTOCONFIG_Z2_ACCESS));
FTCPE_LAN_BASEADR5: FTCPE port map (LAN_BASEADR(5),LAN_BASEADR_T(5),SHUT_UP_Z2(1)/SHUT_UP_Z2(1)_CLKF,'0',NOT RESET);
LAN_BASEADR_T(5) <= ((NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
NOT AUTO_CONFIG_Z2_DONE(0) AND D(13).PIN AND NOT LAN_BASEADR(5) AND NOT UDS AND A(6) AND A(3) AND
NOT RW AND AUTOCONFIG_Z2_ACCESS)
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
NOT AUTO_CONFIG_Z2_DONE(0) AND D(13).PIN AND NOT LAN_BASEADR(5) AND NOT LDS AND A(6) AND A(3) AND
NOT RW AND AUTOCONFIG_Z2_ACCESS)
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
NOT AUTO_CONFIG_Z2_DONE(0) AND NOT D(13).PIN AND LAN_BASEADR(5) AND NOT LDS AND A(6) AND A(3) AND
NOT RW AND AUTOCONFIG_Z2_ACCESS)
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
NOT AUTO_CONFIG_Z2_DONE(0) AND NOT D(13).PIN AND LAN_BASEADR(5) AND NOT UDS AND A(6) AND A(3) AND
NOT RW AND AUTOCONFIG_Z2_ACCESS));
FTCPE_LAN_BASEADR6: FTCPE port map (LAN_BASEADR(6),LAN_BASEADR_T(6),SHUT_UP_Z2(1)/SHUT_UP_Z2(1)_CLKF,'0',NOT RESET);
LAN_BASEADR_T(6) <= ((NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
NOT AUTO_CONFIG_Z2_DONE(0) AND D(14).PIN AND NOT LAN_BASEADR(6) AND NOT LDS AND A(6) AND A(3) AND
NOT RW AND AUTOCONFIG_Z2_ACCESS)
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
NOT AUTO_CONFIG_Z2_DONE(0) AND D(14).PIN AND NOT LAN_BASEADR(6) AND NOT UDS AND A(6) AND A(3) AND
NOT RW AND AUTOCONFIG_Z2_ACCESS)
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
NOT AUTO_CONFIG_Z2_DONE(0) AND NOT D(14).PIN AND LAN_BASEADR(6) AND NOT UDS AND A(6) AND A(3) AND
NOT RW AND AUTOCONFIG_Z2_ACCESS)
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
NOT AUTO_CONFIG_Z2_DONE(0) AND NOT D(14).PIN AND LAN_BASEADR(6) AND NOT LDS AND A(6) AND A(3) AND
NOT RW AND AUTOCONFIG_Z2_ACCESS));
FTCPE_LAN_BASEADR7: FTCPE port map (LAN_BASEADR(7),LAN_BASEADR_T(7),SHUT_UP_Z2(1)/SHUT_UP_Z2(1)_CLKF,'0',NOT RESET);
LAN_BASEADR_T(7) <= ((NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
NOT AUTO_CONFIG_Z2_DONE(0) AND D(15).PIN AND NOT LAN_BASEADR(7) AND NOT LDS AND A(6) AND A(3) AND
NOT RW AND AUTOCONFIG_Z2_ACCESS)
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
NOT AUTO_CONFIG_Z2_DONE(0) AND D(15).PIN AND NOT LAN_BASEADR(7) AND NOT UDS AND A(6) AND A(3) AND
NOT RW AND AUTOCONFIG_Z2_ACCESS)
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
NOT AUTO_CONFIG_Z2_DONE(0) AND NOT D(15).PIN AND LAN_BASEADR(7) AND NOT UDS AND A(6) AND A(3) AND
NOT RW AND AUTOCONFIG_Z2_ACCESS)
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
NOT AUTO_CONFIG_Z2_DONE(0) AND NOT D(15).PIN AND LAN_BASEADR(7) AND NOT LDS AND A(6) AND A(3) AND
NOT RW AND AUTOCONFIG_Z2_ACCESS));
FTCPE_LAN_BASEADR8: FTCPE port map (LAN_BASEADR(8),LAN_BASEADR_T(8),SHUT_UP_Z2(1)/SHUT_UP_Z2(1)_CLKF,'0',NOT RESET);
LAN_BASEADR_T(8) <= ((NOT A(5) AND NOT A(4) AND A(2) AND NOT A(1) AND NOT AS AND
NOT AUTO_CONFIG_Z2_DONE(1) AND D(8).PIN AND NOT LAN_BASEADR(8) AND NOT UDS AND A(6) AND NOT A(3) AND
NOT RW AND AUTOCONFIG_Z2_ACCESS)
OR (NOT A(5) AND NOT A(4) AND A(2) AND NOT A(1) AND NOT AS AND
NOT AUTO_CONFIG_Z2_DONE(1) AND D(8).PIN AND NOT LAN_BASEADR(8) AND NOT LDS AND A(6) AND NOT A(3) AND
NOT RW AND AUTOCONFIG_Z2_ACCESS)
OR (NOT A(5) AND NOT A(4) AND A(2) AND NOT A(1) AND NOT AS AND
NOT AUTO_CONFIG_Z2_DONE(1) AND NOT D(8).PIN AND LAN_BASEADR(8) AND NOT UDS AND A(6) AND NOT A(3) AND
NOT RW AND AUTOCONFIG_Z2_ACCESS)
OR (NOT A(5) AND NOT A(4) AND A(2) AND NOT A(1) AND NOT AS AND
NOT AUTO_CONFIG_Z2_DONE(1) AND NOT D(8).PIN AND LAN_BASEADR(8) AND NOT LDS AND A(6) AND NOT A(3) AND
NOT RW AND AUTOCONFIG_Z2_ACCESS));
FTCPE_LAN_BASEADR9: FTCPE port map (LAN_BASEADR(9),LAN_BASEADR_T(9),SHUT_UP_Z2(1)/SHUT_UP_Z2(1)_CLKF,'0',NOT RESET);
LAN_BASEADR_T(9) <= ((NOT A(5) AND NOT A(4) AND A(2) AND NOT A(1) AND NOT AS AND
NOT AUTO_CONFIG_Z2_DONE(1) AND D(9).PIN AND NOT LAN_BASEADR(9) AND NOT UDS AND A(6) AND NOT A(3) AND
NOT RW AND AUTOCONFIG_Z2_ACCESS)
OR (NOT A(5) AND NOT A(4) AND A(2) AND NOT A(1) AND NOT AS AND
NOT AUTO_CONFIG_Z2_DONE(1) AND D(9).PIN AND NOT LAN_BASEADR(9) AND NOT LDS AND A(6) AND NOT A(3) AND
NOT RW AND AUTOCONFIG_Z2_ACCESS)
OR (NOT A(5) AND NOT A(4) AND A(2) AND NOT A(1) AND NOT AS AND
NOT AUTO_CONFIG_Z2_DONE(1) AND NOT D(9).PIN AND LAN_BASEADR(9) AND NOT UDS AND A(6) AND NOT A(3) AND
NOT RW AND AUTOCONFIG_Z2_ACCESS)
OR (NOT A(5) AND NOT A(4) AND A(2) AND NOT A(1) AND NOT AS AND
NOT AUTO_CONFIG_Z2_DONE(1) AND NOT D(9).PIN AND LAN_BASEADR(9) AND NOT LDS AND A(6) AND NOT A(3) AND
NOT RW AND AUTOCONFIG_Z2_ACCESS));
FTCPE_LAN_BASEADR10: FTCPE port map (LAN_BASEADR(10),LAN_BASEADR_T(10),SHUT_UP_Z2(1)/SHUT_UP_Z2(1)_CLKF,'0',NOT RESET);
LAN_BASEADR_T(10) <= ((NOT A(5) AND NOT A(4) AND A(2) AND NOT A(1) AND NOT AS AND
NOT AUTO_CONFIG_Z2_DONE(1) AND D(10).PIN AND NOT LAN_BASEADR(10) AND NOT UDS AND A(6) AND
NOT A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)
OR (NOT A(5) AND NOT A(4) AND A(2) AND NOT A(1) AND NOT AS AND
NOT AUTO_CONFIG_Z2_DONE(1) AND D(10).PIN AND NOT LAN_BASEADR(10) AND NOT LDS AND A(6) AND
NOT A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)
OR (NOT A(5) AND NOT A(4) AND A(2) AND NOT A(1) AND NOT AS AND
NOT AUTO_CONFIG_Z2_DONE(1) AND NOT D(10).PIN AND LAN_BASEADR(10) AND NOT LDS AND A(6) AND
NOT A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)
OR (NOT A(5) AND NOT A(4) AND A(2) AND NOT A(1) AND NOT AS AND
NOT AUTO_CONFIG_Z2_DONE(1) AND NOT D(10).PIN AND LAN_BASEADR(10) AND NOT UDS AND A(6) AND
NOT A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS));
FTCPE_LAN_BASEADR11: FTCPE port map (LAN_BASEADR(11),LAN_BASEADR_T(11),SHUT_UP_Z2(1)/SHUT_UP_Z2(1)_CLKF,'0',NOT RESET);
LAN_BASEADR_T(11) <= ((NOT A(5) AND NOT A(4) AND A(2) AND NOT A(1) AND NOT AS AND
NOT AUTO_CONFIG_Z2_DONE(1) AND D(11).PIN AND NOT LAN_BASEADR(11) AND NOT UDS AND A(6) AND
NOT A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)
OR (NOT A(5) AND NOT A(4) AND A(2) AND NOT A(1) AND NOT AS AND
NOT AUTO_CONFIG_Z2_DONE(1) AND D(11).PIN AND NOT LAN_BASEADR(11) AND NOT LDS AND A(6) AND
NOT A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)
OR (NOT A(5) AND NOT A(4) AND A(2) AND NOT A(1) AND NOT AS AND
NOT AUTO_CONFIG_Z2_DONE(1) AND NOT D(11).PIN AND LAN_BASEADR(11) AND NOT UDS AND A(6) AND
NOT A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)
OR (NOT A(5) AND NOT A(4) AND A(2) AND NOT A(1) AND NOT AS AND
NOT AUTO_CONFIG_Z2_DONE(1) AND NOT D(11).PIN AND LAN_BASEADR(11) AND NOT LDS AND A(6) AND
NOT A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS));
FTCPE_LAN_BASEADR12: FTCPE port map (LAN_BASEADR(12),LAN_BASEADR_T(12),SHUT_UP_Z2(1)/SHUT_UP_Z2(1)_CLKF,'0',NOT RESET);
LAN_BASEADR_T(12) <= ((NOT A(5) AND NOT A(4) AND A(2) AND NOT A(1) AND NOT AS AND
NOT AUTO_CONFIG_Z2_DONE(1) AND D(12).PIN AND NOT LAN_BASEADR(12) AND NOT LDS AND A(6) AND
NOT A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)
OR (NOT A(5) AND NOT A(4) AND A(2) AND NOT A(1) AND NOT AS AND
NOT AUTO_CONFIG_Z2_DONE(1) AND D(12).PIN AND NOT LAN_BASEADR(12) AND NOT UDS AND A(6) AND
NOT A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)
OR (NOT A(5) AND NOT A(4) AND A(2) AND NOT A(1) AND NOT AS AND
NOT AUTO_CONFIG_Z2_DONE(1) AND NOT D(12).PIN AND LAN_BASEADR(12) AND NOT UDS AND A(6) AND
NOT A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)
OR (NOT A(5) AND NOT A(4) AND A(2) AND NOT A(1) AND NOT AS AND
NOT AUTO_CONFIG_Z2_DONE(1) AND NOT D(12).PIN AND LAN_BASEADR(12) AND NOT LDS AND A(6) AND
NOT A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS));
FTCPE_LAN_BASEADR13: FTCPE port map (LAN_BASEADR(13),LAN_BASEADR_T(13),SHUT_UP_Z2(1)/SHUT_UP_Z2(1)_CLKF,'0',NOT RESET);
LAN_BASEADR_T(13) <= ((NOT A(5) AND NOT A(4) AND A(2) AND NOT A(1) AND NOT AS AND
NOT AUTO_CONFIG_Z2_DONE(1) AND D(13).PIN AND NOT LAN_BASEADR(13) AND NOT LDS AND A(6) AND
NOT A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)
OR (NOT A(5) AND NOT A(4) AND A(2) AND NOT A(1) AND NOT AS AND
NOT AUTO_CONFIG_Z2_DONE(1) AND D(13).PIN AND NOT LAN_BASEADR(13) AND NOT UDS AND A(6) AND
NOT A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)
OR (NOT A(5) AND NOT A(4) AND A(2) AND NOT A(1) AND NOT AS AND
NOT AUTO_CONFIG_Z2_DONE(1) AND NOT D(13).PIN AND LAN_BASEADR(13) AND NOT UDS AND A(6) AND
NOT A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)
OR (NOT A(5) AND NOT A(4) AND A(2) AND NOT A(1) AND NOT AS AND
NOT AUTO_CONFIG_Z2_DONE(1) AND NOT D(13).PIN AND LAN_BASEADR(13) AND NOT LDS AND A(6) AND
NOT A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS));
FTCPE_LAN_BASEADR14: FTCPE port map (LAN_BASEADR(14),LAN_BASEADR_T(14),SHUT_UP_Z2(1)/SHUT_UP_Z2(1)_CLKF,'0',NOT RESET);
LAN_BASEADR_T(14) <= ((NOT A(5) AND NOT A(4) AND A(2) AND NOT A(1) AND NOT AS AND
NOT AUTO_CONFIG_Z2_DONE(1) AND D(14).PIN AND NOT LAN_BASEADR(14) AND NOT LDS AND A(6) AND
NOT A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)
OR (NOT A(5) AND NOT A(4) AND A(2) AND NOT A(1) AND NOT AS AND
NOT AUTO_CONFIG_Z2_DONE(1) AND D(14).PIN AND NOT LAN_BASEADR(14) AND NOT UDS AND A(6) AND
NOT A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)
OR (NOT A(5) AND NOT A(4) AND A(2) AND NOT A(1) AND NOT AS AND
NOT AUTO_CONFIG_Z2_DONE(1) AND NOT D(14).PIN AND LAN_BASEADR(14) AND NOT UDS AND A(6) AND
NOT A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)
OR (NOT A(5) AND NOT A(4) AND A(2) AND NOT A(1) AND NOT AS AND
NOT AUTO_CONFIG_Z2_DONE(1) AND NOT D(14).PIN AND LAN_BASEADR(14) AND NOT LDS AND A(6) AND
NOT A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS));
FTCPE_LAN_BASEADR15: FTCPE port map (LAN_BASEADR(15),LAN_BASEADR_T(15),SHUT_UP_Z2(1)/SHUT_UP_Z2(1)_CLKF,'0',NOT RESET);
LAN_BASEADR_T(15) <= ((NOT A(5) AND NOT A(4) AND A(2) AND NOT A(1) AND NOT AS AND
NOT AUTO_CONFIG_Z2_DONE(1) AND D(15).PIN AND NOT LAN_BASEADR(15) AND NOT UDS AND A(6) AND
NOT A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)
OR (NOT A(5) AND NOT A(4) AND A(2) AND NOT A(1) AND NOT AS AND
NOT AUTO_CONFIG_Z2_DONE(1) AND D(15).PIN AND NOT LAN_BASEADR(15) AND NOT LDS AND A(6) AND
NOT A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)
OR (NOT A(5) AND NOT A(4) AND A(2) AND NOT A(1) AND NOT AS AND
NOT AUTO_CONFIG_Z2_DONE(1) AND NOT D(15).PIN AND LAN_BASEADR(15) AND NOT UDS AND A(6) AND
NOT A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)
OR (NOT A(5) AND NOT A(4) AND A(2) AND NOT A(1) AND NOT AS AND
NOT AUTO_CONFIG_Z2_DONE(1) AND NOT D(15).PIN AND LAN_BASEADR(15) AND NOT LDS AND A(6) AND
NOT A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS));
LAN_CFG_I(1) <= '0';
LAN_CFG(1) <= LAN_CFG_I(1) when LAN_CFG_OE(1) = '1' else 'Z';
LAN_CFG_OE(1) <= '0';
LAN_CFG_I(2) <= '0';
LAN_CFG(2) <= LAN_CFG_I(2) when LAN_CFG_OE(2) = '1' else 'Z';
LAN_CFG_OE(2) <= '0';
LAN_CFG_I(3) <= '0';
LAN_CFG(3) <= LAN_CFG_I(3) when LAN_CFG_OE(3) = '1' else 'Z';
LAN_CFG_OE(3) <= '0';
LAN_CFG_I(4) <= '0';
LAN_CFG(4) <= LAN_CFG_I(4) when LAN_CFG_OE(4) = '1' else 'Z';
LAN_CFG_OE(4) <= '0';
LAN_CS <= ((RESET AND LAN_ACCESS)
OR (NOT RESET AND LAN_CS_RST));
FDCPE_LAN_CS_RST: FDCPE port map (LAN_CS_RST,LAN_CS_RST_D,CLK_EXT,RESET,'0');
LAN_CS_RST_D <= ((NOT LAN_RST_SM_FSM_FFd3 AND LAN_RST_SM_FSM_FFd2 AND
LAN_RST_SM_FSM_FFd1)
OR (NOT LAN_RST_SM_FSM_FFd3 AND NOT LAN_RST_SM_FSM_FFd2 AND
NOT LAN_RST_SM_FSM_FFd1));
FDCPE_LAN_D_INIT1: FDCPE port map (LAN_D_INIT(1),LAN_D_INIT_D(1),CLK_EXT,RESET,'0');
LAN_D_INIT_D(1) <= ((LAN_RST_SM_FSM_FFd3 AND NOT LAN_RST_SM_FSM_FFd1)
OR (NOT LAN_RST_SM_FSM_FFd3 AND LAN_RST_SM_FSM_FFd2));
FDCPE_LAN_D_INIT8: FDCPE port map (LAN_D_INIT(8),LAN_D_INIT_D(8),CLK_EXT,RESET,'0');
LAN_D_INIT_D(8) <= ((LAN_RST_SM_FSM_FFd3 AND LAN_RST_SM_FSM_FFd1)
OR (NOT LAN_RST_SM_FSM_FFd3 AND NOT LAN_RST_SM_FSM_FFd2));
FTCPE_LAN_INT_ENABLE: FTCPE port map (LAN_INT_ENABLE,LAN_INT_ENABLE_T,CLK_EXT,NOT RESET,'0');
LAN_INT_ENABLE_T <= ((D(15).PIN AND NOT LAN_INT_ENABLE AND NOT UDS AND NOT RW AND NOT FCS AND
LAN_ACCESS AND Z3_ADR(13))
OR (NOT D(15).PIN AND LAN_INT_ENABLE AND NOT UDS AND NOT RW AND NOT FCS AND
LAN_ACCESS AND Z3_ADR(13))
OR (LAN_INT_ENABLE AND UDS AND NOT LDS AND NOT A(23).PIN AND NOT RW AND
NOT FCS AND LAN_ACCESS AND Z3_ADR(13))
OR (NOT LAN_INT_ENABLE AND UDS AND NOT LDS AND A(23).PIN AND NOT RW AND
NOT FCS AND LAN_ACCESS AND Z3_ADR(13)));
FDCPE_LAN_IRQ_D0: FDCPE port map (LAN_IRQ_D0,LAN_INT,CLK_EXT,'0',NOT RESET);
FDCPE_LAN_IRQ_OUT: FDCPE port map (LAN_IRQ_OUT,LAN_IRQ_OUT_D,CLK_EXT,'0',NOT RESET);
LAN_IRQ_OUT_D <= ((LAN_INT)
OR (LAN_IRQ_OUT AND NOT LAN_IRQ_D0));
LAN_RD <= (RESET AND NOT FCS AND LAN_RD_S);
FDCPE_LAN_RD_S: FDCPE port map (LAN_RD_S,LAN_RD_S_D,CLK_EXT,LAN_SM_RST,'0');
LAN_RD_S_D <= ((RW AND NOT LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd4)
OR (NOT LAN_SM_FSM_FFd3 AND LAN_SM_FSM_FFd2 AND
NOT LAN_SM_FSM_FFd1)
OR (LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND
NOT LAN_SM_FSM_FFd1));
FDCPE_LAN_READY: FDCPE port map (LAN_READY,LAN_READY_D,CLK_EXT,LAN_SM_RST,'0');
LAN_READY_D <= ((LAN_SM_FSM_FFd3 AND LAN_SM_FSM_FFd4 AND
LAN_SM_FSM_FFd1)
OR (NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND
LAN_SM_FSM_FFd1)
OR (DS1 AND DS0 AND NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2)
OR (LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd2));
FDCPE_LAN_RST_SM_FSM_FFd1: FDCPE port map (LAN_RST_SM_FSM_FFd1,LAN_RST_SM_FSM_FFd1_D,CLK_EXT,RESET,'0');
LAN_RST_SM_FSM_FFd1_D <= ((NOT LAN_RST_SM_FSM_FFd3)
OR (NOT LAN_RST_SM_FSM_FFd2 AND LAN_RST_SM_FSM_FFd1));
FDCPE_LAN_RST_SM_FSM_FFd2: FDCPE port map (LAN_RST_SM_FSM_FFd2,LAN_RST_SM_FSM_FFd2_D,CLK_EXT,RESET,'0');
LAN_RST_SM_FSM_FFd2_D <= ((NOT LAN_RST_SM_FSM_FFd3 AND NOT LAN_RST_SM_FSM_FFd2)
OR (LAN_RST_SM_FSM_FFd3 AND LAN_RST_SM_FSM_FFd2 AND
LAN_RST_SM_FSM_FFd1));
FTCPE_LAN_RST_SM_FSM_FFd3: FTCPE port map (LAN_RST_SM_FSM_FFd3,LAN_RST_SM_FSM_FFd3_T,CLK_EXT,RESET,'0');
LAN_RST_SM_FSM_FFd3_T <= ((LAN_RST_SM_FSM_FFd3 AND LAN_RST_SM_FSM_FFd2 AND
NOT LAN_RST_SM_FSM_FFd1)
OR (NOT LAN_RST_SM_FSM_FFd3 AND NOT LAN_RST_SM_FSM_FFd2 AND
LAN_RST_SM_FSM_FFd1));
FDCPE_LAN_SM_FSM_FFd1: FDCPE port map (LAN_SM_FSM_FFd1,LAN_SM_FSM_FFd1_D,CLK_EXT,LAN_SM_RST,'0');
LAN_SM_FSM_FFd1_D <= ((NOT RW AND NOT LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd4)
OR (NOT LAN_SM_FSM_FFd3 AND LAN_SM_FSM_FFd2 AND
NOT LAN_SM_FSM_FFd1)
OR (DS1 AND DS0 AND NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd1)
OR (NOT DS1 AND NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
NOT LAN_SM_FSM_FFd1)
OR (NOT DS0 AND NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
NOT LAN_SM_FSM_FFd1)
OR (NOT LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd1)
OR (LAN_SM_FSM_FFd3 AND LAN_SM_FSM_FFd4 AND
LAN_SM_FSM_FFd1));
FDCPE_LAN_SM_FSM_FFd2: FDCPE port map (LAN_SM_FSM_FFd2,LAN_SM_FSM_FFd2_D,CLK_EXT,LAN_SM_RST,'0');
LAN_SM_FSM_FFd2_D <= ((NOT UDS AND NOT LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd4)
OR (NOT LDS AND NOT LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd4)
OR (NOT LAN_SM_FSM_FFd3 AND LAN_SM_FSM_FFd2 AND
NOT LAN_SM_FSM_FFd1)
OR (LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2)
OR (DS1 AND DS0 AND LAN_SM_FSM_FFd2));
FDCPE_LAN_SM_FSM_FFd3: FDCPE port map (LAN_SM_FSM_FFd3,LAN_SM_FSM_FFd3_D,CLK_EXT,LAN_SM_RST,'0');
LAN_SM_FSM_FFd3_D <= ((LAN_SM_FSM_FFd4)
OR (LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd2)
OR (NOT LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd1)
OR (DS1 AND DS0 AND LAN_SM_FSM_FFd2)
OR (NOT LAN_SM_FSM_FFd3 AND LAN_SM_FSM_FFd2 AND
NOT LAN_SM_FSM_FFd1)
OR (UDS AND LDS AND RW AND NOT LAN_SM_FSM_FFd3));
FDCPE_LAN_SM_FSM_FFd4: FDCPE port map (LAN_SM_FSM_FFd4,LAN_SM_FSM_FFd4_D,CLK_EXT,LAN_SM_RST,'0');
LAN_SM_FSM_FFd4_D <= ((LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd2)
OR (LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
NOT LAN_SM_FSM_FFd1)
OR (DS1 AND DS0 AND LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd4));
FDCPE_LAN_SM_RST: FDCPE port map (LAN_SM_RST,LAN_SM_RST_D,NOT CLK_EXT,'0','0');
LAN_SM_RST_D <= ((RESET AND NOT UDS AND NOT FCS AND LAN_ACCESS AND NOT Z3_ADR(13) AND
BERR)
OR (RESET AND NOT LDS AND NOT FCS AND LAN_ACCESS AND NOT Z3_ADR(13) AND
BERR)
OR (RESET AND NOT DS1 AND NOT FCS AND LAN_ACCESS AND NOT Z3_ADR(13) AND
BERR)
OR (RESET AND NOT DS0 AND NOT FCS AND LAN_ACCESS AND NOT Z3_ADR(13) AND
BERR));
LAN_WRH <= ((NOT RESET AND LAN_WR_RST)
OR (FCS AND LAN_WR_RST)
OR (RESET AND NOT FCS AND LAN_WRH_S));
FDCPE_LAN_WRH_S: FDCPE port map (LAN_WRH_S,LAN_WRH_S_D,CLK_EXT,LAN_SM_RST,'0');
LAN_WRH_S_D <= ((NOT LDS AND LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
LAN_SM_FSM_FFd1)
OR (NOT DS0 AND NOT LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd2 AND
LAN_SM_FSM_FFd1));
LAN_WRL <= ((NOT RESET AND LAN_WR_RST)
OR (FCS AND LAN_WR_RST)
OR (RESET AND NOT FCS AND LAN_WRL_S));
FDCPE_LAN_WRL_S: FDCPE port map (LAN_WRL_S,LAN_WRL_S_D,CLK_EXT,LAN_SM_RST,'0');
LAN_WRL_S_D <= ((NOT UDS AND LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
LAN_SM_FSM_FFd1)
OR (NOT DS1 AND NOT LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd2 AND
LAN_SM_FSM_FFd1));
FDCPE_LAN_WR_RST: FDCPE port map (LAN_WR_RST,LAN_WR_RST_D,CLK_EXT,RESET,'0');
LAN_WR_RST_D <= ((LAN_RST_SM_FSM_FFd3 AND LAN_RST_SM_FSM_FFd2 AND
NOT LAN_RST_SM_FSM_FFd1)
OR (LAN_RST_SM_FSM_FFd3 AND NOT LAN_RST_SM_FSM_FFd2 AND
LAN_RST_SM_FSM_FFd1));
MTACK_I <= '0';
MTACK <= MTACK_I when MTACK_OE = '1' else 'Z';
MTACK_OE <= '0';
OVR_I <= '0';
OVR <= OVR_I when OVR_OE = '1' else 'Z';
OVR_OE <= (NOT FCS AND LAN_ACCESS);
OWN_I <= '0';
OWN <= OWN_I when OWN_OE = '1' else 'Z';
OWN_OE <= '0';
ROM_B(0) <= '0';
ROM_B(1) <= '0';
ROM_B_0_OBUF$BUF8/ROM_B_0_OBUF$BUF8_TRST <= ((NOT CP_IRQ)
OR (LAN_INT_ENABLE AND NOT LAN_IRQ_OUT));
ROM_B_0_OBUF$BUF9/ROM_B_0_OBUF$BUF9_TRST <= ((NOT FCS AND CONFIG_READY)
OR (NOT FCS AND LAN_READY));
ROM_OE <= NOT ((NOT AS AND NOT ROM_OE_S AND NOT AUTOBOOT_OFF));
FDCPE_ROM_OE_S: FDCPE port map (ROM_OE_S,ROM_OE_S_D,SHUT_UP_Z2(1)/SHUT_UP_Z2(1)_CLKF,'0',NOT RESET);
ROM_OE_S_D <= (NOT AS AND RW AND IDE_ACCESS AND IDE_ENABLE);
FTCPE_SHUT_UP_Z20: FTCPE port map (SHUT_UP_Z2(0),SHUT_UP_Z2_T(0),SHUT_UP_Z2(1)/SHUT_UP_Z2(1)_CLKF,'0',NOT RESET);
SHUT_UP_Z2_T(0) <= ((NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
NOT AUTO_CONFIG_Z2_DONE(0) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS AND
SHUT_UP_Z2(0))
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
NOT AUTO_CONFIG_Z2_DONE(0) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS AND
SHUT_UP_Z2(0)));
FTCPE_SHUT_UP_Z21: FTCPE port map (SHUT_UP_Z2(1),SHUT_UP_Z2_T(1),SHUT_UP_Z2(1)/SHUT_UP_Z2(1)_CLKF,'0',NOT RESET);
SHUT_UP_Z2_T(1) <= ((NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE(1) AND NOT UDS AND A(6) AND A(3) AND
NOT RW AND AUTOCONFIG_Z2_ACCESS AND SHUT_UP_Z2(1))
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE(1) AND NOT LDS AND A(6) AND A(3) AND
NOT RW AND AUTOCONFIG_Z2_ACCESS AND SHUT_UP_Z2(1)));
SHUT_UP_Z2(1)/SHUT_UP_Z2(1)_CLKF <= C1
XOR
SHUT_UP_Z2(1)/SHUT_UP_Z2(1)_CLKF <= C3;
SLAVE <= ((AS AND FCS)
OR (AS AND NOT LAN_ACCESS)
OR (FCS AND NOT AUTOCONFIG_Z2_ACCESS AND NOT IDE_ACCESS AND CP_CS)
OR (NOT AUTOCONFIG_Z2_ACCESS AND NOT LAN_ACCESS AND NOT IDE_ACCESS AND
CP_CS));
FDCPE_Z3_ADR2: FDCPE port map (Z3_ADR(2),A(4),NOT FCS,'0',NOT RESET);
FDCPE_Z3_ADR3: FDCPE port map (Z3_ADR(3),A(5),NOT FCS,'0',NOT RESET);
FDCPE_Z3_ADR4: FDCPE port map (Z3_ADR(4),A(6),NOT FCS,'0',NOT RESET);
FDCPE_Z3_ADR5: FDCPE port map (Z3_ADR(5),A(7),NOT FCS,'0',NOT RESET);
FDCPE_Z3_ADR6: FDCPE port map (Z3_ADR(6),A(8).PIN,NOT FCS,'0',NOT RESET);
FDCPE_Z3_ADR7: FDCPE port map (Z3_ADR(7),A(9).PIN,NOT FCS,'0',NOT RESET);
FDCPE_Z3_ADR8: FDCPE port map (Z3_ADR(8),A(10).PIN,NOT FCS,'0',NOT RESET);
FDCPE_Z3_ADR9: FDCPE port map (Z3_ADR(9),A(11).PIN,NOT FCS,'0',NOT RESET);
FDCPE_Z3_ADR10: FDCPE port map (Z3_ADR(10),A(12).PIN,NOT FCS,'0',NOT RESET);
FDCPE_Z3_ADR11: FDCPE port map (Z3_ADR(11),A(13).PIN,NOT FCS,'0',NOT RESET);
FDCPE_Z3_ADR12: FDCPE port map (Z3_ADR(12),A(14).PIN,NOT FCS,'0',NOT RESET);
FDCPE_Z3_ADR13: FDCPE port map (Z3_ADR(13),A(15).PIN,NOT FCS,'0',NOT RESET);
FDCPE_Z3_ADR_0: FDCPE port map (Z3_ADR_0,A(2),NOT FCS,'0',NOT RESET);
FDCPE_Z3_ADR_1: FDCPE port map (Z3_ADR_1,A(3),NOT FCS,'0',NOT RESET);
FDCPE_Z3_A_LOW: FDCPE port map (Z3_A_LOW,Z3_A_LOW_D,CLK_EXT,LAN_SM_RST,'0');
Z3_A_LOW_D <= ((LAN_SM_FSM_FFd3 AND LAN_SM_FSM_FFd4 AND
LAN_SM_FSM_FFd1)
OR (UDS AND LDS AND NOT LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd4)
OR (LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2)
OR (NOT DS1 AND NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2)
OR (NOT DS0 AND NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2)
OR (NOT LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd2 AND
LAN_SM_FSM_FFd1));
FDCPE_Z3_DATA16: FDCPE port map (Z3_DATA(16),Z3_DATA_D(16),CLK_EXT,'0',LAN_SM_RST,Z3_DATA_CE(16));
Z3_DATA_D(16) <= ((DQ_SWAP AND DQ(8).PIN)
OR (NOT DQ_SWAP AND DQ(0).PIN));
Z3_DATA_CE(16) <= (NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
LAN_SM_FSM_FFd1);
FDCPE_Z3_DATA17: FDCPE port map (Z3_DATA(17),Z3_DATA_D(17),CLK_EXT,'0',LAN_SM_RST,Z3_DATA_CE(17));
Z3_DATA_D(17) <= ((DQ_SWAP AND DQ(9).PIN)
OR (NOT DQ_SWAP AND DQ(1).PIN));
Z3_DATA_CE(17) <= (NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
LAN_SM_FSM_FFd1);
FDCPE_Z3_DATA18: FDCPE port map (Z3_DATA(18),Z3_DATA_D(18),CLK_EXT,'0',LAN_SM_RST,Z3_DATA_CE(18));
Z3_DATA_D(18) <= ((DQ_SWAP AND DQ(10).PIN)
OR (NOT DQ_SWAP AND DQ(2).PIN));
Z3_DATA_CE(18) <= (NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
LAN_SM_FSM_FFd1);
FDCPE_Z3_DATA19: FDCPE port map (Z3_DATA(19),Z3_DATA_D(19),CLK_EXT,'0',LAN_SM_RST,Z3_DATA_CE(19));
Z3_DATA_D(19) <= ((DQ_SWAP AND DQ(11).PIN)
OR (NOT DQ_SWAP AND DQ(3).PIN));
Z3_DATA_CE(19) <= (NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
LAN_SM_FSM_FFd1);
FDCPE_Z3_DATA20: FDCPE port map (Z3_DATA(20),Z3_DATA_D(20),CLK_EXT,'0',LAN_SM_RST,Z3_DATA_CE(20));
Z3_DATA_D(20) <= ((DQ_SWAP AND DQ(12).PIN)
OR (NOT DQ_SWAP AND DQ(4).PIN));
Z3_DATA_CE(20) <= (NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
LAN_SM_FSM_FFd1);
FDCPE_Z3_DATA21: FDCPE port map (Z3_DATA(21),Z3_DATA_D(21),CLK_EXT,'0',LAN_SM_RST,Z3_DATA_CE(21));
Z3_DATA_D(21) <= ((DQ_SWAP AND DQ(13).PIN)
OR (NOT DQ_SWAP AND DQ(5).PIN));
Z3_DATA_CE(21) <= (NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
LAN_SM_FSM_FFd1);
FDCPE_Z3_DATA22: FDCPE port map (Z3_DATA(22),Z3_DATA_D(22),CLK_EXT,'0',LAN_SM_RST,Z3_DATA_CE(22));
Z3_DATA_D(22) <= ((DQ_SWAP AND DQ(14).PIN)
OR (NOT DQ_SWAP AND DQ(6).PIN));
Z3_DATA_CE(22) <= (NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
LAN_SM_FSM_FFd1);
FDCPE_Z3_DATA23: FDCPE port map (Z3_DATA(23),Z3_DATA_D(23),CLK_EXT,'0',LAN_SM_RST,Z3_DATA_CE(23));
Z3_DATA_D(23) <= ((DQ_SWAP AND DQ(15).PIN)
OR (NOT DQ_SWAP AND DQ(7).PIN));
Z3_DATA_CE(23) <= (NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
LAN_SM_FSM_FFd1);
FDCPE_Z3_DATA24: FDCPE port map (Z3_DATA(24),Z3_DATA_D(24),CLK_EXT,'0',LAN_SM_RST,Z3_DATA_CE(24));
Z3_DATA_D(24) <= ((DQ_SWAP AND DQ(0).PIN)
OR (NOT DQ_SWAP AND DQ(8).PIN));
Z3_DATA_CE(24) <= (NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
LAN_SM_FSM_FFd1);
FDCPE_Z3_DATA25: FDCPE port map (Z3_DATA(25),Z3_DATA_D(25),CLK_EXT,'0',LAN_SM_RST,Z3_DATA_CE(25));
Z3_DATA_D(25) <= ((DQ_SWAP AND DQ(1).PIN)
OR (NOT DQ_SWAP AND DQ(9).PIN));
Z3_DATA_CE(25) <= (NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
LAN_SM_FSM_FFd1);
FDCPE_Z3_DATA26: FDCPE port map (Z3_DATA(26),Z3_DATA_D(26),CLK_EXT,'0',LAN_SM_RST,Z3_DATA_CE(26));
Z3_DATA_D(26) <= ((DQ_SWAP AND DQ(2).PIN)
OR (NOT DQ_SWAP AND DQ(10).PIN));
Z3_DATA_CE(26) <= (NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
LAN_SM_FSM_FFd1);
FDCPE_Z3_DATA27: FDCPE port map (Z3_DATA(27),Z3_DATA_D(27),CLK_EXT,'0',LAN_SM_RST,Z3_DATA_CE(27));
Z3_DATA_D(27) <= ((DQ_SWAP AND DQ(3).PIN)
OR (NOT DQ_SWAP AND DQ(11).PIN));
Z3_DATA_CE(27) <= (NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
LAN_SM_FSM_FFd1);
FDCPE_Z3_DATA28: FDCPE port map (Z3_DATA(28),Z3_DATA_D(28),CLK_EXT,'0',LAN_SM_RST,Z3_DATA_CE(28));
Z3_DATA_D(28) <= ((DQ_SWAP AND DQ(4).PIN)
OR (NOT DQ_SWAP AND DQ(12).PIN));
Z3_DATA_CE(28) <= (NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
LAN_SM_FSM_FFd1);
FDCPE_Z3_DATA29: FDCPE port map (Z3_DATA(29),Z3_DATA_D(29),CLK_EXT,'0',LAN_SM_RST,Z3_DATA_CE(29));
Z3_DATA_D(29) <= ((DQ_SWAP AND DQ(5).PIN)
OR (NOT DQ_SWAP AND DQ(13).PIN));
Z3_DATA_CE(29) <= (NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
LAN_SM_FSM_FFd1);
FDCPE_Z3_DATA30: FDCPE port map (Z3_DATA(30),Z3_DATA_D(30),CLK_EXT,'0',LAN_SM_RST,Z3_DATA_CE(30));
Z3_DATA_D(30) <= ((DQ_SWAP AND DQ(6).PIN)
OR (NOT DQ_SWAP AND DQ(14).PIN));
Z3_DATA_CE(30) <= (NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
LAN_SM_FSM_FFd1);
FDCPE_Z3_DATA31: FDCPE port map (Z3_DATA(31),Z3_DATA_D(31),CLK_EXT,'0',LAN_SM_RST,Z3_DATA_CE(31));
Z3_DATA_D(31) <= ((DQ_SWAP AND DQ(7).PIN)
OR (NOT DQ_SWAP AND DQ(15).PIN));
Z3_DATA_CE(31) <= (NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
LAN_SM_FSM_FFd1);
Register Legend:
FDCPE (Q,D,C,CLR,PRE,CE);
FTCPE (Q,D,C,CLR,PRE,CE);
LDCP (Q,D,G,CLR,PRE);
****************************** Device Pin Out *****************************
Device : XC95288XL-10-TQ144
Pin Signal Pin Signal
No. Name No. Name
1 VCC 73 VCC
2 D<0> 74 A<15>
3 A_LAN<1> 75 AUTOBOOT_OFF
4 A_LAN<0> 76 LAN_WRL
5 A_LAN<3> 77 FCS
6 A_LAN<2> 78 DS1
7 A_LAN<5> 79 Z3
8 VCC 80 AS
9 A_LAN<4> 81 UDS
10 A_LAN<7> 82 LDS
11 A_LAN<6> 83 RW
12 LAN_CFG<1> 84 VCC
13 LAN_CFG<3> 85 DTACK
14 D<6> 86 A<23>
15 D<3> 87 A<22>
16 D<7> 88 A<21>
17 D<1> 89 GND
18 GND 90 GND
19 D<8> 91 A<20>
20 D<5> 92 A<19>
21 D<4> 93 DS0
22 IDE_CS<0> 94 A<18>
23 IDE_CS<1> 95 A<17>
24 IDE_A<0> 96 MTACK
25 IDE_A<2> 97 A<16>
26 IDE_A<1> 98 BERR
27 IDE_R 99 GND
28 IDE_W 100 OVR
29 GND 101 KPR
30 CLK_EXT 102 C3
31 CP_IRQ 103 C1
32 INT_OUT 104 CFIN
33 KPR 105 CFOUT
34 CP_CS 106 SLAVE
35 ROM_OE 107 OWN
36 GND 108 GND
37 VCC 109 VCC
38 KPR 110 LAN_CFG<4>
39 D<2> 111 LAN_INT
40 D<9> 112 DQ<15>
41 D<10> 113 DQ<13>
42 VCC 114 GND
43 D<11> 115 DQ<11>
44 D<12> 116 DQ<9>
45 D<13> 117 DQ<1>
46 D<14> 118 DQ<0>
47 GND 119 DQ<3>
48 D<15> 120 DQ<2>
49 A<5> 121 DQ<5>
50 A<4> 122 TDO
51 A<6> 123 GND
52 A<3> 124 DQ<4>
53 A<7> 125 DQ<7>
54 A<2> 126 DQ<6>
55 VCC 127 VCC
56 A<8> 128 DQ<8>
57 A<1> 129 DQ<10>
58 A<9> 130 DQ<12>
59 A<10> 131 DQ<14>
60 A<11> 132 LAN_WRH
61 A<12> 133 LAN_CS
62 GND 134 LAN_RD
63 TDI 135 LAN_CFG<2>
64 A<13> 136 A_LAN<12>
65 TMS 137 A_LAN<13>
66 A<14> 138 A_LAN<10>
67 TCK 139 A_LAN<11>
68 ROM_B<0> 140 A_LAN<8>
69 ROM_B<1> 141 VCC
70 CP_WE 142 A_LAN<9>
71 CP_RD 143 RESET
72 GND 144 GND
Legend : NC = Not Connected, unbonded pin
PGND = Unused I/O configured as additional Ground pin
TIE = Unused I/O floating -- must tie to VCC, GND or other signal
KPR = Unused I/O with weak keeper (leave unconnected)
VCC = Dedicated Power Pin
GND = Dedicated Ground Pin
TDI = Test Data In, JTAG pin
TDO = Test Data Out, JTAG pin
TCK = Test Clock, JTAG pin
TMS = Test Mode Select, JTAG pin
PROHIBITED = User reserved pin
**************************** Compiler Options ****************************
Following is a list of all global compiler options used by the fitter run.
Device(s) Specified : xc95288xl-10-TQ144
Optimization Method : SPEED
Multi-Level Logic Optimization : ON
Ignore Timing Specifications : OFF
Default Register Power Up Value : LOW
Keep User Location Constraints : ON
What-You-See-Is-What-You-Get : OFF
Exhaustive Fitting : OFF
Keep Unused Inputs : OFF
Slew Rate : FAST
Power Mode : STD
Ground on Unused IOs : OFF
Set I/O Pin Termination : KEEPER
Global Clock Optimization : ON
Global Set/Reset Optimization : ON
Global Ouput Enable Optimization : ON
Input Limit : 54
Pterm Limit : 25
Reference in New Issue View Git Blame Copy Permalink