Dominick.Vansevenant/Zorro-LAN-IDE
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Fixed reset issue: The initialisation loop must be performed exactly once!

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buffered address
This commit is contained in:
MHeinrichs
2022-03-08 12:25:56 +01:00
parent dc65757a8a
commit 88cdb9fb52
14 changed files with 17896 additions and 16293 deletions
Download Patch File Download Diff File Expand all files Collapse all files
Logic/LAN_IDE_V2/LAN_IDE_CP-Z2v2.vhd
+62 -43
View File
@@ -94,7 +94,6 @@ architecture Behavioral of LAN_IDE_CP is
); );
SIGNAL LAN_RST_SM: lan_reset :=nop; SIGNAL LAN_RST_SM: lan_reset :=nop;
SIGNAL lancp: STD_LOGIC; -- LAN or ClockPort
SIGNAL ide: STD_LOGIC; SIGNAL ide: STD_LOGIC;
SIGNAL autoconfig: STD_LOGIC; SIGNAL autoconfig: STD_LOGIC;
SIGNAL lan_adr: STD_LOGIC; SIGNAL lan_adr: STD_LOGIC;
@@ -105,6 +104,7 @@ architecture Behavioral of LAN_IDE_CP is
signal AUTO_CONFIG_DONE_CYCLE:STD_LOGIC_VECTOR(1 downto 0); signal AUTO_CONFIG_DONE_CYCLE:STD_LOGIC_VECTOR(1 downto 0);
signal D_IN:STD_LOGIC_VECTOR(15 downto 0); signal D_IN:STD_LOGIC_VECTOR(15 downto 0);
signal D_OUT:STD_LOGIC_VECTOR(15 downto 0); signal D_OUT:STD_LOGIC_VECTOR(15 downto 0);
signal A_LAN_OUT:STD_LOGIC_VECTOR(13 downto 0);
signal SHUT_UP:STD_LOGIC_VECTOR(2 downto 0); signal SHUT_UP:STD_LOGIC_VECTOR(2 downto 0);
signal IDE_BASEADR:STD_LOGIC_VECTOR(7 downto 0); signal IDE_BASEADR:STD_LOGIC_VECTOR(7 downto 0);
signal LAN_BASEADR:STD_LOGIC_VECTOR(7 downto 0); signal LAN_BASEADR:STD_LOGIC_VECTOR(7 downto 0);
@@ -131,6 +131,7 @@ architecture Behavioral of LAN_IDE_CP is
signal CP_RD_S: std_logic; signal CP_RD_S: std_logic;
signal CP_WE_S: std_logic; signal CP_WE_S: std_logic;
signal CP_WE_QUIRK: std_logic; signal CP_WE_QUIRK: std_logic;
signal SET_FREQUENCY: std_logic :='1';
signal LAN_CS_RST: std_logic; signal LAN_CS_RST: std_logic;
signal LAN_WR_RST: std_logic; signal LAN_WR_RST: std_logic;
@@ -153,17 +154,22 @@ begin
DS <= UDS and LDS; DS <= UDS and LDS;
AS_DELAY: process(CLK_EXT) AS_DELAY: process(CLK_EXT,reset)
begin begin
if(rising_edge(AMIGA_CLK))then if(rising_edge(AMIGA_CLK))then
AS_D <= AS; if(reset = '0' )then
AS_D <= '1';
else
AS_D <= AS;
end if;
end if; end if;
end process; end process;
clock_init: process(CLK_EXT) clock_init: process(CLK_EXT)
begin begin
if(rising_edge(CLK_EXT))then if(rising_edge(CLK_EXT))then
if(reset = '0' )then if(reset = '0' and SET_FREQUENCY ='1')then
LAN_RST_SM <= nop; LAN_RST_SM <= nop;
LAN_CS_RST<='0'; LAN_CS_RST<='0';
LAN_WR_RST<='0'; LAN_WR_RST<='0';
@@ -199,6 +205,7 @@ begin
LAN_WR_RST<='0'; LAN_WR_RST<='0';
LAN_RST_SM<=done; LAN_RST_SM<=done;
when done=> --stay here when done=> --stay here
SET_FREQUENCY <='0';
LAN_CS_RST<='0'; LAN_CS_RST<='0';
LAN_WR_RST<='0'; LAN_WR_RST<='0';
LAN_RST_SM<=done; LAN_RST_SM<=done;
@@ -215,7 +222,6 @@ begin
lan_adr <= '0'; lan_adr <= '0';
lan_adr_sw <= '0'; lan_adr_sw <= '0';
cp <= '0'; cp <= '0';
lancp <= '0';
elsif(rising_edge(AMIGA_CLK))then elsif(rising_edge(AMIGA_CLK))then
--default values --default values
autoconfig <= '0'; autoconfig <= '0';
@@ -223,7 +229,6 @@ begin
lan_adr <= '0'; lan_adr <= '0';
lan_adr_sw <= '0'; lan_adr_sw <= '0';
cp <= '0'; cp <= '0';
lancp <= '0';
if(A(23 downto 16) = x"E8" and AUTO_CONFIG_DONE > "00" and CFIN='0')then if(A(23 downto 16) = x"E8" and AUTO_CONFIG_DONE > "00" and CFIN='0')then
autoconfig <= '1'; autoconfig <= '1';
end if; end if;
@@ -232,15 +237,12 @@ begin
lan_adr_sw <= '1'; lan_adr_sw <= '1';
end if; end if;
lan_adr <= '1'; lan_adr <= '1';
lancp <= '1';
end if; end if;
if(A(23 downto 16) = CP_BASEADR and SHUT_UP(1)='0')then if(A(23 downto 16) = CP_BASEADR and SHUT_UP(1)='0')then
cp <= '1'; cp <= '1';
lancp <= '1';
end if; end if;
if(A(23 downto 16) = IDE_BASEADR and SHUT_UP(2)='0')then if(A(23 downto 16) = IDE_BASEADR and SHUT_UP(2)='0')then
ide <= '1'; ide <= '1';
lancp <= '1';
end if; end if;
end if; end if;
end process ADDRESS_DECODE; end process ADDRESS_DECODE;
@@ -249,21 +251,21 @@ begin
lan_int_proc: process (AMIGA_CLK,reset) lan_int_proc: process (AMIGA_CLK,reset)
begin begin
if(reset ='0') then if(reset ='0') then
LAN_INT_ENABLE <='0'; LAN_INT_ENABLE <='1';
LAN_IRQ_D0 <='1'; LAN_IRQ_D0 <='1';
LAN_IRQ_OUT <='1'; LAN_IRQ_OUT <='1';
elsif falling_edge(AMIGA_CLK) then elsif falling_edge(AMIGA_CLK) then
LAN_IRQ_D0 <= LAN_INT; LAN_IRQ_D0 <= LAN_INT;
if(LAN_INT ='0' and LAN_IRQ_D0 ='1') then if(LAN_INT ='0' and LAN_IRQ_D0 ='1') then
LAN_IRQ_OUT <='0'; LAN_IRQ_OUT <='0';
elsif(LAN_INT ='1' or LAN_INT_ENABLE = '0')then elsif(LAN_INT ='1' or LAN_INT_ENABLE = '1')then
LAN_IRQ_OUT <='1'; LAN_IRQ_OUT <='1';
elsif(lan_adr = '1' and DS ='0' and RW='0' and A(15)='1') then elsif(lan_adr = '1' and DS ='0' and RW='0' and A(15)='1') then
LAN_IRQ_OUT <= D(14); --controll lan irq LAN_IRQ_OUT <= D(14); --controll lan irq
end if; end if;
if(lan_adr = '1' and DS ='0' and RW='0' and A(15)='1') then --enable if a write to A15 occured if(lan_adr = '1' and DS ='0' and RW='0' and A(15)='1') then --enable if a write to A15 occured
LAN_INT_ENABLE <= D(15); LAN_INT_ENABLE <= not(D(15));
end if; end if;
end if; end if;
end process lan_int_proc; end process lan_int_proc;
@@ -272,20 +274,20 @@ begin
lan_rw_gen: process (AMIGA_CLK,reset) lan_rw_gen: process (AMIGA_CLK,reset)
begin begin
if(reset ='0') then if(reset ='0') then
LAN_RD_S <= '0'; LAN_RD_S <= '1';
LAN_WRH_S <= '0'; LAN_WRH_S <= '1';
LAN_WRL_S <= '0'; LAN_WRL_S <= '1';
elsif falling_edge(AMIGA_CLK) then elsif falling_edge(AMIGA_CLK) then
--default values --default values
LAN_RD_S <= '0'; LAN_RD_S <= '1';
LAN_WRH_S <= '0'; LAN_WRH_S <= '1';
LAN_WRL_S <= '0'; LAN_WRL_S <= '1';
if(lan_adr='1' and DS='0' and A(15)='0')then if(lan_adr='1' and DS='0' and A(15)='0')then
LAN_RD_S <= RW; LAN_RD_S <= not(RW);
-- swapped LDS/UDS here: ENC624 is little endian -- swapped LDS/UDS here: ENC624 is little endian
LAN_WRH_S <= not LDS and not RW; LAN_WRH_S <= not(not LDS and not RW);
LAN_WRL_S <= not UDS and not RW; LAN_WRL_S <= not(not UDS and not RW);
end if; end if;
end if; end if;
end process lan_rw_gen; end process lan_rw_gen;
@@ -469,11 +471,41 @@ begin
end if; end if;
end process autoconfig_proc; --- that's all end process autoconfig_proc; --- that's all
ADDRESS_SAMPLE: process(CLK_EXT)
begin
if(rising_edge(CLK_EXT))then
--clear and set-register adresses during initialization phase
if(LAN_RST_SM = wait0 or LAN_RST_SM = clr or LAN_RST_SM = clr_commit)then
A_LAN_OUT <= LAN_A_CLRREG(13 downto 0);
end if;
if(LAN_RST_SM = wait1 or LAN_RST_SM = set or LAN_RST_SM = set_commit)then
A_LAN_OUT <= LAN_A_SETREG(13 downto 0);
end if;
if(lan_adr ='1')then --the lanport is shifted by one adress line but I forgot to adopt the clockport address!
A_LAN_OUT <= A(14 downto 1);
end if;
if(cp = '1')then
A_LAN_OUT <= A(12 downto 1) &"00";
end if;
end if;
end process;
DATA_SAMPLE: process(CLK_EXT) DATA_SAMPLE: process(CLK_EXT)
begin begin
if(rising_edge(CLK_EXT))then if(rising_edge(CLK_EXT))then
if(DS='0')then if(DS='0')then
if(LAN_RST_SM = wait0 or LAN_RST_SM = clr or LAN_RST_SM = clr_commit) then
D_IN <= LAN_D_CLR;
end if;
if(LAN_RST_SM = wait1 or LAN_RST_SM = set or LAN_RST_SM = set_commit) then
D_IN <= LAN_D_SET;
end if;
if(lan_adr ='1' and lan_adr_sw ='1') then if(lan_adr ='1' and lan_adr_sw ='1') then
D_IN <= D( 7 downto 0) & D(15 downto 8); D_IN <= D( 7 downto 0) & D(15 downto 8);
end if; end if;
@@ -503,32 +535,22 @@ begin
LAN_CS <= lan_adr when LAN_RST_SM =done else LAN_CS_RST; LAN_CS <= lan_adr when LAN_RST_SM =done else LAN_CS_RST;
LAN_WRL <= LAN_WRL_S when AS ='0' and LAN_RST_SM =done else LAN_WR_RST; LAN_WRL <= not(LAN_WRL_S) when AS ='0' and LAN_RST_SM =done else LAN_WR_RST;
LAN_WRH <= LAN_WRH_S when AS ='0' and LAN_RST_SM =done else LAN_WR_RST; LAN_WRH <= not(LAN_WRH_S) when AS ='0' and LAN_RST_SM =done else LAN_WR_RST;
LAN_RD <= LAN_RD_S when (AS_D ='0' or AS ='0') and LAN_RST_SM =done else '0'; LAN_RD <= not(LAN_RD_S ) when (AS_D ='0' or AS ='0') and LAN_RST_SM =done else '0';
CP_WE <= CP_WE_S when AS ='0' and CP_WE_QUIRK ='1' else '1'; CP_WE <= CP_WE_S when AS ='0' and CP_WE_QUIRK ='1' else '1';
CP_RD <= CP_RD_S when (AS_D ='0' or AS ='0') else '1'; CP_RD <= CP_RD_S when (AS_D ='0' or AS ='0') else '1';
CP_CS <= not cp; CP_CS <= not cp;
--the lanport is shifted by one adress line but I forgot to adopt the clockport address! A_LAN(13 downto 0)<= A_LAN_OUT;
A_LAN(13 downto 0)<= LAN_A_CLRREG(13 downto 0) when (LAN_RST_SM = wait0 or LAN_RST_SM = clr or LAN_RST_SM = clr_commit) else
LAN_A_SETREG(13 downto 0) when (LAN_RST_SM = wait1 or LAN_RST_SM = set or LAN_RST_SM = set_commit) else
A(14 downto 1) when lan_adr ='1' else
A(12 downto 1) &"00";
--signal assignment --signal assignment
D <= --RAM_D when RW='1' and TRANSFER_IN_PROGRES ='1' else D <= D_OUT when RW='1' and (AS_D ='0' or AS ='0') and (lan_adr ='1' or ide = '1' or cp = '1' or autoconfig ='1') else
D_OUT when RW='1' and (AS_D ='0' or AS ='0') and (lan_adr ='1' or ide = '1' or cp = '1' or autoconfig ='1') else
(others => 'Z'); (others => 'Z');
--defined lancp signal that matches both LAN and CP addresses (and IDE for Rev2 boards)
DQ <= DQ <= D_IN when (RW='0' and AS='0' and (lan_adr ='1' or cp ='1' or ide ='1')) or SET_FREQUENCY ='1'
LAN_D_CLR WHEN (LAN_RST_SM = wait0 or LAN_RST_SM = clr or LAN_RST_SM = clr_commit) else
LAN_D_SET WHEN (LAN_RST_SM = wait1 or LAN_RST_SM = set or LAN_RST_SM = set_commit) else
D_IN when (RW='0' and AS='0' and (lan_adr ='1' or cp ='1' or ide ='1'))
else (others => 'Z'); else (others => 'Z');
IDE_W <= IDE_W_S when AS = '0' else '1'; IDE_W <= IDE_W_S when AS = '0' else '1';
@@ -539,13 +561,10 @@ begin
ROM_B <= "00"; ROM_B <= "00";
ROM_OE <= ROM_OE_S when (AS_D ='0' or AS ='0') else '1'; ROM_OE <= ROM_OE_S when (AS_D ='0' or AS ='0') else '1';
-- INT_OUT <= 'Z'; INT2_OUT <= '0' when (LAN_IRQ_OUT = '0' and LAN_INT_ENABLE = '0')
INT2_OUT <= '0' when
(LAN_IRQ_OUT = '0' and LAN_INT_ENABLE = '1')
else 'Z'; else 'Z';
INT6_OUT <= '0' when INT6_OUT <= '0' when CP_IRQ = '0'
CP_IRQ = '0'
else 'Z'; else 'Z';
Logic/LAN_IDE_V2/LAN_IDE_CP-z2v2.jed
+1465 -1465
View File
File diff suppressed because it is too large Load Diff
Logic/LAN_IDE_V2/LAN_IDE_CP.cmd_log
+49
View File
@@ -793,3 +793,52 @@ cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt
XSLTProcess LAN_IDE_CP_build.xml XSLTProcess LAN_IDE_CP_build.xml
tsim -intstyle ise LAN_IDE_CP LAN_IDE_CP.nga tsim -intstyle ise LAN_IDE_CP LAN_IDE_CP.nga
hprep6 -s IEEE1149 -n LAN_IDE_CP -i LAN_IDE_CP hprep6 -s IEEE1149 -n LAN_IDE_CP -i LAN_IDE_CP
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE_V2/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE_V2/LAN_IDE_CP.syr"
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -exhaust -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
XSLTProcess LAN_IDE_CP_build.xml
tsim -intstyle ise LAN_IDE_CP LAN_IDE_CP.nga
hprep6 -s IEEE1149 -n LAN_IDE_CP -i LAN_IDE_CP
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE_V2/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE_V2/LAN_IDE_CP.syr"
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -exhaust -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE_V2/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE_V2/LAN_IDE_CP.syr"
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -exhaust -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE_V2/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE_V2/LAN_IDE_CP.syr"
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -exhaust -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE_V2/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE_V2/LAN_IDE_CP.syr"
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -exhaust -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE_V2/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE_V2/LAN_IDE_CP.syr"
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -exhaust -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
XSLTProcess LAN_IDE_CP_build.xml
tsim -intstyle ise LAN_IDE_CP LAN_IDE_CP.nga
hprep6 -s IEEE1149 -n LAN_IDE_CP -i LAN_IDE_CP
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init high -exhaust -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
XSLTProcess LAN_IDE_CP_build.xml
tsim -intstyle ise LAN_IDE_CP LAN_IDE_CP.nga
hprep6 -s IEEE1149 -n LAN_IDE_CP -i LAN_IDE_CP
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE_V2/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE_V2/LAN_IDE_CP.syr"
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init high -exhaust -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
XSLTProcess LAN_IDE_CP_build.xml
tsim -intstyle ise LAN_IDE_CP LAN_IDE_CP.nga
hprep6 -s IEEE1149 -n LAN_IDE_CP -i LAN_IDE_CP
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE_V2/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE_V2/LAN_IDE_CP.syr"
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init high -exhaust -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
XSLTProcess LAN_IDE_CP_build.xml
tsim -intstyle ise LAN_IDE_CP LAN_IDE_CP.nga
hprep6 -s IEEE1149 -n LAN_IDE_CP -i LAN_IDE_CP
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE_V2/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE_V2/LAN_IDE_CP.syr"
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init high -exhaust -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE_V2/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE_V2/LAN_IDE_CP.syr"
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95288xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95288xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init high -exhaust -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
XSLTProcess LAN_IDE_CP_build.xml
tsim -intstyle ise LAN_IDE_CP LAN_IDE_CP.nga
hprep6 -s IEEE1149 -n LAN_IDE_CP -i LAN_IDE_CP
Logic/LAN_IDE_V2/LAN_IDE_CP.gyd
+86 -88
View File
@@ -37,10 +37,6 @@ RESET S:PIN143
RW S:PIN83 RW S:PIN83
UDS S:PIN81 UDS S:PIN81
A_LAN<0> S:PIN4 A_LAN<0> S:PIN4
A_LAN<10> S:PIN138
A_LAN<11> S:PIN139
A_LAN<12> S:PIN136
A_LAN<13> S:PIN137
A_LAN<1> S:PIN3 A_LAN<1> S:PIN3
A_LAN<2> S:PIN6 A_LAN<2> S:PIN6
A_LAN<3> S:PIN5 A_LAN<3> S:PIN5
@@ -50,26 +46,22 @@ A_LAN<6> S:PIN11
A_LAN<7> S:PIN10 A_LAN<7> S:PIN10
A_LAN<8> S:PIN140 A_LAN<8> S:PIN140
A_LAN<9> S:PIN142 A_LAN<9> S:PIN142
A_LAN<10> S:PIN138
A_LAN<11> S:PIN139
A_LAN<12> S:PIN136
A_LAN<13> S:PIN137
CFOUT S:PIN105 CFOUT S:PIN105
CP_CS S:PIN34 CP_CS S:PIN34
CP_RD S:PIN71 CP_RD S:PIN71
CP_WE S:PIN70 CP_WE S:PIN70
DQ<0> S:PIN118 DQ<0> S:PIN118
DQ<10> S:PIN129 DQ<1> S:PIN117
DQ<2> S:PIN120
DQ<11> S:PIN115 DQ<11> S:PIN115
DQ<12> S:PIN130 DQ<12> S:PIN130
DQ<13> S:PIN113 DQ<13> S:PIN113
DQ<14> S:PIN131 DQ<14> S:PIN131
DQ<15> S:PIN112 DQ<15> S:PIN112
DQ<1> S:PIN117
DQ<2> S:PIN120
DQ<3> S:PIN119
DQ<4> S:PIN124
DQ<5> S:PIN121
DQ<6> S:PIN126
DQ<7> S:PIN125
DQ<8> S:PIN128
DQ<9> S:PIN116
D<0> S:PIN2 D<0> S:PIN2
D<1> S:PIN17 D<1> S:PIN17
D<2> S:PIN39 D<2> S:PIN39
@@ -107,89 +99,95 @@ INT2_OUT S:PIN32
DTACK S:PIN85 DTACK S:PIN85
ROM_OE S:PIN35 ROM_OE S:PIN35
SLAVE S:PIN106 SLAVE S:PIN106
DQ<8> S:PIN128
DQ<4> S:PIN124
DQ<10> S:PIN129
DQ<7> S:PIN125
DQ<6> S:PIN126
DQ<5> S:PIN121
DQ<3> S:PIN119
DQ<9> S:PIN116
;The remaining section of the .gyd file is for documentation purposes only. ;The remaining section of the .gyd file is for documentation purposes only.
;It shows where your internal equations were placed in the last successful fit. ;It shows where your internal equations were placed in the last successful fit.
PARTITION FB1_1 EXP22_ EXP23_ PARTITION FB1_4 EXP30_ D_OUT<5> D_OUT<4> EXP31_
PARTITION FB1_4 EXP24_ D_OUT<5> D_OUT<4> EXP25_ IDE_CS_0_OBUF LAN_BASEADR<0> IDE_CS_1_OBUF IDE_BASEADR<0>
IDE_CS_0_OBUF IDE_A_0_OBUF$BUF0 CP_BASEADR<1> IDE_A_2_OBUF$BUF0 IDE_A_1_OBUF$BUF0
PARTITION FB1_10 IDE_CS_1_OBUF D_IN<3> IDE_A_0_OBUF$BUF0 D_IN<2> CP_BASEADR<0> IDE_R_OBUF AUTO_CONFIG_DONE_CYCLE<0>
IDE_A_2_OBUF$BUF0 IDE_A_1_OBUF$BUF0 D_IN<11> IDE_R_OBUF PARTITION FB2_1 D_OUT<13>/D_OUT<13>_TRST__$INT A_LAN_OUT<4> A_LAN_OUT<7> DQ<10>_BUFR.MC
D_IN<10> A_LAN_OUT<6> EXP32_ EXP33_ EXP34_
PARTITION FB2_1 EXP26_ A_LAN_4_OBUF A_LAN_7_OBUF D_IN<0> EXP35_ D_OUT<6> EXP36_ D_OUT<3>
A_LAN_6_OBUF DQ_9_IOBUFE/DQ_9_IOBUFE_TRST__$INT EXP27_ D_IN<8> EXP37_ D_OUT<7> D_OUT<1> EXP38_
EXP28_ D_OUT<6> EXP29_ D_OUT<3> D_OUT<8> EXP39_
EXP30_ D_OUT<7> D_OUT<1> EXP31_ PARTITION FB3_1 EXP40_ IDE_W_OBUF EXP41_ Dout1<3>
D_OUT<8> EXP32_ EXP42_ LAN_IRQ_D0 CP_WE_QUIRK
PARTITION FB3_1 EXP33_ IDE_W_OBUF SHUT_UP<0> AUTO_CONFIG_DONE<0> PARTITION FB3_11 EXP43_ EXP44_ ide ROM_B_0_OBUF$BUF5
SHUT_UP<1> EXP34_ Dout1<2> EXP35_ autoconfig AUTO_CONFIG_DONE<1> EXP45_ Dout1<0>
AUTO_CONFIG_DONE<1> EXP36_ EXP37_ Dout1<0>
EXP38_ ROM_B_0_OBUF$BUF5 AUTO_CONFIG_DONE_CYCLE<1> SHUT_UP<2> PARTITION FB4_1 EXP46_ D_OUT<0> DQ<8>_BUFR.MC EXP47_
EXP39_ Dout1<1> A_LAN_OUT<1> A_LAN_OUT<0> CP_WE_S A_LAN_OUT<3>
PARTITION FB4_1 AUTO_CONFIG_DONE_CYCLE<0> D_OUT<0> EXP40_ DQ<3>_BUFR.MC DQ<5>_BUFR.MC EXP48_ A_LAN_OUT<2>
PARTITION FB4_5 A_LAN_1_OBUF A_LAN_0_OBUF D_IN<10>/D_IN<10>_TRST__$INT A_LAN_OUT<5> LAN_WR_RST LAN_RST_SM_FSM_FFd8
PARTITION FB4_8 A_LAN_3_OBUF DQ<4>_BUFR.MC EXP49_
PARTITION FB4_10 LAN_WR_RST LAN_CS_RST A_LAN_2_OBUF LAN_BASEADR<0> PARTITION FB5_1 AS_D CP_CS_OBUF EXP50_ EXP51_
A_LAN_5_OBUF IDE_BASEADR<0> CP_BASEADR<1> CP_BASEADR<0>
EXP41_
PARTITION FB5_1 EXP42_ CP_CS_OBUF EXP43_ EXP44_
ROM_OE_OBUF ROM_OE_OBUF
PARTITION FB5_8 EXP45_ EXP46_ D_OUT<2> EXP47_ PARTITION FB5_8 EXP52_ EXP53_ D_OUT<2> EXP54_
D_OUT<9> EXP48_ D_OUT<10> D_OUT<11> D_OUT<9> EXP55_ D_OUT<10> D_OUT<11>
EXP49_ D_OUT<12> EXP50_ EXP56_ D_OUT<12> EXP57_
PARTITION FB6_1 EXP51_ ROM_B_0_OBUF$BUF4 A_LAN_12_OBUF PARTITION FB6_1 EXP58_ ROM_B_0_OBUF$BUF4 A_LAN_OUT<12> SET_FREQUENCY
PARTITION FB6_5 A_LAN_13_OBUF A_LAN_10_OBUF A_LAN_OUT<13> A_LAN_OUT<10> LAN_RST_SM_FSM_FFd6 A_LAN_OUT<11>
PARTITION FB6_8 A_LAN_11_OBUF LAN_RST_SM_FSM_FFd5 A_LAN_OUT<8> LAN_RST_SM_FSM_FFd4 EXP59_
PARTITION FB6_10 A_LAN_8_OBUF EXP52_ EXP53_ lan_adr lan_adr A_LAN_OUT<9> LAN_RST_SM_FSM_FFd3 LAN_RST_SM_FSM_FFd1
A_LAN_9_OBUF LAN_WRH_S autoconfig EXP54_ LAN_RST_SM_FSM_FFd2 lan_adr_sw
lan_adr_sw PARTITION FB7_1 Dout1<2> EXP60_ D_OUT<13> EXP61_
PARTITION FB7_1 EXP55_ D_IN<13> D_OUT<13> EXP56_ D_OUT<14> EXP62_ EXP63_ AUTO_CONFIG_DONE<0>
D_OUT<14> EXP57_ EXP58_ EXP59_ CP_BASEADR<2> EXP64_ EXP65_ D_OUT<15>
D_IN<4> EXP60_ D_IN<5> D_OUT<15> EXP66_ Dout1<1> EXP67_ EXP68_
EXP61_ $OpTx$INV$125__$INT LAN_RD_S EXP62_ EXP69_ EXP70_
D_IN<12> EXP63_ PARTITION FB8_1 DQ<6>_BUFR.MC D_IN<12> D_IN<14> EXP71_
PARTITION FB8_2 DQ_12_IOBUFE DQ_14_IOBUFE LAN_WRH_OBUF EXP72_
PARTITION FB8_5 LAN_WRH_OBUF
PARTITION FB8_8 LAN_CS_OBUF PARTITION FB8_8 LAN_CS_OBUF
PARTITION FB8_10 LAN_RD_OBUF PARTITION FB8_10 LAN_RD_OBUF
PARTITION FB8_14 LAN_BASEADR<2> IDE_BASEADR<3> IDE_BASEADR<2> CP_BASEADR<3> PARTITION FB8_14 IDE_ENABLE CP_BASEADR<4> EXP73_ DQ<7>_BUFR.MC
CP_BASEADR<2> EXP74_
PARTITION FB9_1 IDE_BASEADR<7>/IDE_BASEADR<7>_CLKF IDE_BASEADR<6>/IDE_BASEADR<6>_CLKF IDE_BASEADR<5>/IDE_BASEADR<5>_CLKF IDE_BASEADR<4>/IDE_BASEADR<4>_CLKF PARTITION FB9_1 LAN_BASEADR<2>/LAN_BASEADR<2>_CLKF LAN_BASEADR<1>/LAN_BASEADR<1>_CLKF LAN_BASEADR<0>/LAN_BASEADR<0>_CLKF IDE_W_S/IDE_W_S_CLKF
IDE_BASEADR<3>/IDE_BASEADR<3>_CLKF IDE_BASEADR<2>/IDE_BASEADR<2>_CLKF IDE_BASEADR<1>/IDE_BASEADR<1>_CLKF IDE_BASEADR<0>/IDE_BASEADR<0>_CLKF IDE_R_S/IDE_R_S_CLKF IDE_ENABLE/IDE_ENABLE_CLKF IDE_BASEADR<7>/IDE_BASEADR<7>_CLKF IDE_BASEADR<6>/IDE_BASEADR<6>_CLKF
Dout1<3>/Dout1<3>_CLKF Dout1<2>/Dout1<2>_CLKF Dout1<1>/Dout1<1>_CLKF Dout1<0>/Dout1<0>_CLKF IDE_BASEADR<5>/IDE_BASEADR<5>_CLKF IDE_BASEADR<4>/IDE_BASEADR<4>_CLKF IDE_BASEADR<3>/IDE_BASEADR<3>_CLKF IDE_BASEADR<2>/IDE_BASEADR<2>_CLKF
CP_WE_S/CP_WE_S_CLKF CP_WE_QUIRK/CP_WE_QUIRK_CLKF CP_RD_S/CP_RD_S_CLKF CP_BASEADR<7>/CP_BASEADR<7>_CLKF IDE_BASEADR<1>/IDE_BASEADR<1>_CLKF IDE_BASEADR<0>/IDE_BASEADR<0>_CLKF Dout1<3>/Dout1<3>_CLKF Dout1<2>/Dout1<2>_CLKF
CP_BASEADR<6>/CP_BASEADR<6>_CLKF CP_BASEADR<5>/CP_BASEADR<5>_CLKF Dout1<1>/Dout1<1>_CLKF Dout1<0>/Dout1<0>_CLKF
PARTITION FB10_1 D_IN<1> DQ_1_IOBUFE DQ_0_IOBUFE D_IN<14> PARTITION FB10_1 EXP75_ D_IN<1> D_IN<0> EXP76_
DQ_3_IOBUFE DQ_2_IOBUFE _24_ D_IN<2> EXP77_ _23_
PARTITION FB10_8 DQ_5_IOBUFE D_IN<6> DQ_4_IOBUFE DQ_7_IOBUFE
DQ_6_IOBUFE D_IN<9> DQ_8_IOBUFE LAN_RST_SM_FSM_FFd1 PARTITION FB10_10 _19_ _21_ _22_
LAN_RST_SM_FSM_FFd2 DQ_10_IOBUFE LAN_RST_SM_FSM_FFd3 PARTITION FB10_14 _18_ DQ<9>_BUFR.MC EXP78_ _20_
PARTITION FB11_1 CP_WE_QUIRK EXP64_ ide CP_BASEADR<3>/CP_BASEADR<3>_CLKF LAN_RD_S
CP_BASEADR<2>/CP_BASEADR<2>_CLKF CP_BASEADR<1>/CP_BASEADR<1>_CLKF CP_BASEADR<0>/CP_BASEADR<0>_CLKF AUTO_CONFIG_DONE_CYCLE<1>/AUTO_CONFIG_DONE_CYCLE<1>_CLKF PARTITION FB11_1 CP_WE_S/CP_WE_S_CLKF CP_WE_QUIRK/CP_WE_QUIRK_CLKF CP_RD_S/CP_RD_S_CLKF CP_BASEADR<7>/CP_BASEADR<7>_CLKF
AUTO_CONFIG_DONE_CYCLE<0>/AUTO_CONFIG_DONE_CYCLE<0>_CLKF AUTO_CONFIG_DONE<1>/AUTO_CONFIG_DONE<1>_CLKF AUTO_CONFIG_DONE<0>/AUTO_CONFIG_DONE<0>_CLKF ROM_B_0_OBUF$BUF0 CP_BASEADR<6>/CP_BASEADR<6>_CLKF CP_BASEADR<5>/CP_BASEADR<5>_CLKF CP_BASEADR<4>/CP_BASEADR<4>_CLKF CP_BASEADR<3>/CP_BASEADR<3>_CLKF
AS_D ROM_B_0_OBUF Dout1<3> EXP65_ CP_BASEADR<2>/CP_BASEADR<2>_CLKF CP_BASEADR<1>/CP_BASEADR<1>_CLKF CP_BASEADR<0>/CP_BASEADR<0>_CLKF ROM_B_0_OBUF$BUF0
CP_WE_OBUF CP_BASEADR<4>/CP_BASEADR<4>_CLKF AUTO_CONFIG_DONE_CYCLE<1>/AUTO_CONFIG_DONE_CYCLE<1>_CLKF ROM_B_0_OBUF AUTO_CONFIG_DONE_CYCLE<0>/AUTO_CONFIG_DONE_CYCLE<0>_CLKF AUTO_CONFIG_DONE<1>/AUTO_CONFIG_DONE<1>_CLKF
PARTITION FB12_1 EXP66_ D_IN<15> ROM_OE_S LAN_WRL_S CP_WE_OBUF AUTO_CONFIG_DONE<0>/AUTO_CONFIG_DONE<0>_CLKF
DQ_15_IOBUFE LAN_IRQ_D0 IDE_W_S DQ_13_IOBUFE PARTITION FB12_2 ROM_OE_S LAN_WRL_S EXP79_ D_IN<15>
IDE_R_S DQ_11_IOBUFE IDE_ENABLE DQ_9_IOBUFE LAN_WRH_S EXP80_ D_IN<13> EXP81_
CP_RD_S CP_WE_S LAN_INT_ENABLE LAN_IRQ_OUT D_IN<11> LAN_RST_SM_FSM_FFd7 _25_ LAN_CS_RST
EXP67_ D_IN<7> IDE_R_S CP_RD_S LAN_INT_ENABLE LAN_IRQ_OUT
PARTITION FB13_2 CP_RD_OBUF IDE_W_S
PARTITION FB13_11 LAN_BASEADR<5> LAN_BASEADR<4> IDE_BASEADR<5> LAN_WRL_OBUF PARTITION FB13_1 EXP82_ CP_RD_OBUF
IDE_BASEADR<4> CP_BASEADR<6> CP_BASEADR<5> CP_BASEADR<4> PARTITION FB13_7 SHUT_UP<2> SHUT_UP<1> SHUT_UP<0> LAN_BASEADR<7>
LAN_BASEADR<4> LAN_BASEADR<2> LAN_BASEADR<1> LAN_WRL_OBUF
IDE_BASEADR<4> IDE_BASEADR<2> IDE_BASEADR<1> AUTO_CONFIG_DONE_CYCLE<1>
PARTITION FB14_3 ROM_B_0_OBUF$BUF2 PARTITION FB14_3 ROM_B_0_OBUF$BUF2
PARTITION FB14_8 LAN_BASEADR<7> LAN_BASEADR<6> LAN_BASEADR<3> CFOUT_OBUF PARTITION FB14_5 LAN_BASEADR<6> LAN_BASEADR<5> LAN_BASEADR<3> IDE_BASEADR<7>
LAN_BASEADR<1> IDE_BASEADR<7> SLAVE_OBUF ROM_B_0_OBUF$BUF1 IDE_BASEADR<6> IDE_BASEADR<5> CFOUT_OBUF IDE_BASEADR<3>
IDE_BASEADR<6> IDE_BASEADR<1> CP_BASEADR<7> CP_BASEADR<7> SLAVE_OBUF ROM_B_0_OBUF$BUF1 CP_BASEADR<6>
PARTITION FB15_1 LAN_WRL_S/LAN_WRL_S_CLKF LAN_WRH_S/LAN_WRH_S_CLKF LAN_RD_S/LAN_RD_S_CLKF LAN_IRQ_OUT/LAN_IRQ_OUT_CLKF CP_BASEADR<5> CP_BASEADR<3>
LAN_IRQ_D0/LAN_IRQ_D0_CLKF LAN_INT_ENABLE/LAN_INT_ENABLE_CLKF LAN_BASEADR<7>/LAN_BASEADR<7>_CLKF LAN_BASEADR<6>/LAN_BASEADR<6>_CLKF PARTITION FB15_2 lan_adr_sw/lan_adr_sw_CLKF SHUT_UP<2>/SHUT_UP<2>_CLKF SHUT_UP<1>/SHUT_UP<1>_CLKF SHUT_UP<0>/SHUT_UP<0>_CLKF
LAN_BASEADR<5>/LAN_BASEADR<5>_CLKF LAN_BASEADR<4>/LAN_BASEADR<4>_CLKF LAN_BASEADR<3>/LAN_BASEADR<3>_CLKF ROM_B_0_OBUF$BUF6 ROM_OE_S/ROM_OE_S_CLKF LAN_WRL_S/LAN_WRL_S_CLKF LAN_WRH_S/LAN_WRH_S_CLKF LAN_RD_S/LAN_RD_S_CLKF
LAN_BASEADR<2>/LAN_BASEADR<2>_CLKF LAN_BASEADR<1>/LAN_BASEADR<1>_CLKF LAN_BASEADR<0>/LAN_BASEADR<0>_CLKF IDE_W_S/IDE_W_S_CLKF LAN_IRQ_OUT/LAN_IRQ_OUT_CLKF LAN_IRQ_D0/LAN_IRQ_D0_CLKF ROM_B_0_OBUF$BUF6 LAN_INT_ENABLE/LAN_INT_ENABLE_CLKF
IDE_R_S/IDE_R_S_CLKF IDE_ENABLE/IDE_ENABLE_CLKF LAN_BASEADR<7>/LAN_BASEADR<7>_CLKF LAN_BASEADR<6>/LAN_BASEADR<6>_CLKF LAN_BASEADR<5>/LAN_BASEADR<5>_CLKF LAN_BASEADR<4>/LAN_BASEADR<4>_CLKF
LAN_BASEADR<3>/LAN_BASEADR<3>_CLKF
PARTITION FB16_10 ROM_B_0_OBUF$BUF3 PARTITION FB16_10 ROM_B_0_OBUF$BUF3
PARTITION FB16_14 lan_adr_sw/lan_adr_sw_CLKF SHUT_UP<2>/SHUT_UP<2>_CLKF SHUT_UP<1>/SHUT_UP<1>_CLKF SHUT_UP<0>/SHUT_UP<0>_CLKF
ROM_OE_S/ROM_OE_S_CLKF
Logic/LAN_IDE_V2/LAN_IDE_CP.mfd
+3161 -2840
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File diff suppressed because it is too large Load Diff
Logic/LAN_IDE_V2/LAN_IDE_CP.nga
+1 -1
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File diff suppressed because one or more lines are too long
Logic/LAN_IDE_V2/LAN_IDE_CP.ngd
+1 -1
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File diff suppressed because one or more lines are too long
Logic/LAN_IDE_V2/LAN_IDE_CP.pad
+1 -1
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@@ -1,7 +1,7 @@
Release 8.1i - Fit P.20131013 Release 8.1i - Fit P.20131013
Copyright(c) 1995-2003 Xilinx Inc. All rights reserved Copyright(c) 1995-2003 Xilinx Inc. All rights reserved
3- 6-2022 0:08AM 3- 8-2022 12:14PM
NOTE: This file is designed to be imported into a spreadsheet program NOTE: This file is designed to be imported into a spreadsheet program
such as Microsoft Excel for viewing, printing and sorting. The pipe '|' such as Microsoft Excel for viewing, printing and sorting. The pipe '|'
Logic/LAN_IDE_V2/LAN_IDE_CP.rpt
+1856 -1799
View File
File diff suppressed because it is too large Load Diff
Logic/LAN_IDE_V2/LAN_IDE_CP.syr
+57 -46
View File
@@ -4,13 +4,13 @@ Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Total REAL time to Xst completion: 0.00 secs Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.09 secs Total CPU time to Xst completion: 0.08 secs
--> Parameter xsthdpdir set to xst --> Parameter xsthdpdir set to xst
Total REAL time to Xst completion: 0.00 secs Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.09 secs Total CPU time to Xst completion: 0.08 secs
--> Reading design: LAN_IDE_CP.prj --> Reading design: LAN_IDE_CP.prj
@@ -43,7 +43,7 @@ Target Device : XC9500XL CPLDs
---- Source Options ---- Source Options
Top Module Name : LAN_IDE_CP Top Module Name : LAN_IDE_CP
Automatic FSM Extraction : YES Automatic FSM Extraction : YES
FSM Encoding Algorithm : Gray FSM Encoding Algorithm : Auto
Safe Implementation : No Safe Implementation : No
Mux Extraction : Yes Mux Extraction : Yes
Resource Sharing : YES Resource Sharing : YES
@@ -71,15 +71,12 @@ wysiwyg : NO
========================================================================= =========================================================================
Setting FSM Encoding Algorithm to : Gray
========================================================================= =========================================================================
* HDL Compilation * * HDL Compilation *
========================================================================= =========================================================================
Compiling vhdl file "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE_V2/LAN_IDE_CP-Z2v2.vhd" in Library work. Compiling vhdl file "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE_V2/LAN_IDE_CP-Z2v2.vhd" in Library work.
Entity <lan_ide_cp> compiled. Architecture behavioral of Entity lan_ide_cp is up to date.
Entity <lan_ide_cp> (Architecture <behavioral>) compiled.
========================================================================= =========================================================================
* Design Hierarchy Analysis * * Design Hierarchy Analysis *
@@ -91,7 +88,7 @@ Analyzing hierarchy for entity <LAN_IDE_CP> in library <work> (architecture <beh
* HDL Analysis * * HDL Analysis *
========================================================================= =========================================================================
Analyzing Entity <LAN_IDE_CP> in library <work> (Architecture <behavioral>). Analyzing Entity <LAN_IDE_CP> in library <work> (Architecture <behavioral>).
WARNING:Xst:819 - "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE_V2/LAN_IDE_CP-Z2v2.vhd" line 158: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are: WARNING:Xst:819 - "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE_V2/LAN_IDE_CP-Z2v2.vhd" line 161: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<AMIGA_CLK> <AMIGA_CLK>
Entity <LAN_IDE_CP> analyzed. Unit <LAN_IDE_CP> generated. Entity <LAN_IDE_CP> analyzed. Unit <LAN_IDE_CP> generated.
@@ -122,13 +119,13 @@ WARNING:Xst:646 - Signal <DECODE_RESET> is assigned but never used. This unconne
| States | 8 | | States | 8 |
| Transitions | 8 | | Transitions | 8 |
| Inputs | 0 | | Inputs | 0 |
| Outputs | 9 | | Outputs | 10 |
| Clock | CLK_EXT (rising_edge) | | Clock | CLK_EXT (rising_edge) |
| Reset | RESET (negative) | | Reset | LAN_RST_SM$and0000 (positive) |
| Reset type | synchronous | | Reset type | synchronous |
| Reset State | nop | | Reset State | nop |
| Power Up State | nop | | Power Up State | nop |
| Encoding | gray | | Encoding | automatic |
| Implementation | automatic | | Implementation | automatic |
----------------------------------------------------------------------- -----------------------------------------------------------------------
Found 16-bit tristate buffer for signal <D>. Found 16-bit tristate buffer for signal <D>.
@@ -139,15 +136,16 @@ WARNING:Xst:646 - Signal <DECODE_RESET> is assigned but never used. This unconne
Found 1-bit tristate buffer for signal <DTACK>. Found 1-bit tristate buffer for signal <DTACK>.
Found 1-bit tristate buffer for signal <INT2_OUT>. Found 1-bit tristate buffer for signal <INT2_OUT>.
Found 1-bit tristate buffer for signal <INT6_OUT>. Found 1-bit tristate buffer for signal <INT6_OUT>.
Found 1-bit xor2 for signal <AMIGA_CLK$xor0000> created at line 151. Found 14-bit register for signal <A_LAN_OUT>.
Found 1-bit xor2 for signal <AMIGA_CLK$xor0000> created at line 153.
Found 1-bit register for signal <AS_D>. Found 1-bit register for signal <AS_D>.
Found 2-bit register for signal <AUTO_CONFIG_DONE>. Found 2-bit register for signal <AUTO_CONFIG_DONE>.
Found 2-bit register for signal <AUTO_CONFIG_DONE_CYCLE>. Found 2-bit register for signal <AUTO_CONFIG_DONE_CYCLE>.
Found 2-bit subtractor for signal <AUTO_CONFIG_DONE_CYCLE$addsub0000> created at line 464. Found 2-bit subtractor for signal <AUTO_CONFIG_DONE_CYCLE$addsub0000> created at line 472.
Found 1-bit register for signal <autoconfig>. Found 1-bit register for signal <autoconfig>.
Found 2-bit comparator greater for signal <autoconfig$cmp_gt0000> created at line 227. Found 2-bit comparator greater for signal <autoconfig$cmp_gt0000> created at line 235.
Found 1-bit register for signal <cp>. Found 1-bit register for signal <cp>.
Found 8-bit comparator equal for signal <cp$cmp_eq0000> created at line 237. Found 8-bit comparator equal for signal <cp$cmp_eq0000> created at line 245.
Found 8-bit register for signal <CP_BASEADR>. Found 8-bit register for signal <CP_BASEADR>.
Found 1-bit register for signal <CP_RD_S>. Found 1-bit register for signal <CP_RD_S>.
Found 1-bit register for signal <CP_WE_QUIRK>. Found 1-bit register for signal <CP_WE_QUIRK>.
@@ -155,17 +153,17 @@ WARNING:Xst:646 - Signal <DECODE_RESET> is assigned but never used. This unconne
Found 16-bit register for signal <D_IN>. Found 16-bit register for signal <D_IN>.
Found 16-bit register for signal <D_OUT>. Found 16-bit register for signal <D_OUT>.
Found 4-bit register for signal <Dout1>. Found 4-bit register for signal <Dout1>.
Found 3-bit comparator greater for signal <Dout1$cmp_gt0000> created at line 391. Found 3-bit comparator greater for signal <Dout1$cmp_gt0000> created at line 399.
Found 1-bit register for signal <ide>. Found 1-bit register for signal <ide>.
Found 8-bit comparator equal for signal <ide$cmp_eq0000> created at line 241. Found 8-bit comparator equal for signal <ide$cmp_eq0000> created at line 249.
Found 8-bit register for signal <IDE_BASEADR>. Found 8-bit register for signal <IDE_BASEADR>.
Found 1-bit register for signal <IDE_ENABLE>. Found 1-bit register for signal <IDE_ENABLE>.
Found 1-bit register for signal <IDE_R_S>. Found 1-bit register for signal <IDE_R_S>.
Found 1-bit register for signal <IDE_W_S>. Found 1-bit register for signal <IDE_W_S>.
Found 1-bit register for signal <lan_adr>. Found 1-bit register for signal <lan_adr>.
Found 1-bit register for signal <lan_adr_sw>. Found 1-bit register for signal <lan_adr_sw>.
Found 8-bit comparator equal for signal <lan_adr_sw$cmp_eq0000> created at line 230. Found 8-bit comparator equal for signal <lan_adr_sw$cmp_eq0000> created at line 238.
Found 2-bit comparator less for signal <lan_adr_sw$cmp_lt0000> created at line 231. Found 2-bit comparator less for signal <lan_adr_sw$cmp_lt0000> created at line 239.
Found 8-bit register for signal <LAN_BASEADR>. Found 8-bit register for signal <LAN_BASEADR>.
Found 1-bit register for signal <LAN_CS_RST>. Found 1-bit register for signal <LAN_CS_RST>.
Found 1-bit register for signal <LAN_INT_ENABLE>. Found 1-bit register for signal <LAN_INT_ENABLE>.
@@ -176,6 +174,7 @@ WARNING:Xst:646 - Signal <DECODE_RESET> is assigned but never used. This unconne
Found 1-bit register for signal <LAN_WRH_S>. Found 1-bit register for signal <LAN_WRH_S>.
Found 1-bit register for signal <LAN_WRL_S>. Found 1-bit register for signal <LAN_WRL_S>.
Found 1-bit register for signal <ROM_OE_S>. Found 1-bit register for signal <ROM_OE_S>.
Found 1-bit register for signal <SET_FREQUENCY>.
Found 3-bit register for signal <SHUT_UP>. Found 3-bit register for signal <SHUT_UP>.
Summary: Summary:
inferred 1 Finite State Machine(s). inferred 1 Finite State Machine(s).
@@ -193,8 +192,9 @@ HDL Synthesis Report
Macro Statistics Macro Statistics
# Adders/Subtractors : 1 # Adders/Subtractors : 1
2-bit subtractor : 1 2-bit subtractor : 1
# Registers : 32 # Registers : 34
1-bit register : 24 1-bit register : 25
14-bit register : 1
16-bit register : 2 16-bit register : 2
2-bit register : 2 2-bit register : 2
4-bit register : 1 4-bit register : 1
@@ -216,19 +216,22 @@ Macro Statistics
* Advanced HDL Synthesis * * Advanced HDL Synthesis *
========================================================================= =========================================================================
Optimizing FSM <LAN_RST_SM/FSM> on signal <LAN_RST_SM[1:3]> with gray encoding. Analyzing FSM <FSM_0> for best encoding.
Optimizing FSM <LAN_RST_SM/FSM> on signal <LAN_RST_SM[1:8]> with one-hot encoding.
------------------------ ------------------------
State | Encoding State | Encoding
------------------------ ------------------------
nop | 000 nop | 00000001
wait0 | 001 wait0 | 00000010
clr | 011 clr | 00000100
clr_commit | 010 clr_commit | 00001000
wait1 | 110 wait1 | 00010000
set | 111 set | 00100000
set_commit | 101 set_commit | 01000000
done | 100 done | 10000000
------------------------ ------------------------
WARNING:Xst:1426 - The value init of the FF/Latch 0 hinder the constant cleaning in the block SET_FREQUENCY.
You should achieve better results by setting this init to 0.
========================================================================= =========================================================================
Advanced HDL Synthesis Report Advanced HDL Synthesis Report
@@ -247,8 +250,16 @@ Macro Statistics
========================================================================= =========================================================================
* Low Level Synthesis * * Low Level Synthesis *
========================================================================= =========================================================================
WARNING:Xst:1426 - The value init of the FF/Latch SET_FREQUENCY hinder the constant cleaning in the block LAN_IDE_CP.
You should achieve better results by setting this init to 0.
Optimizing unit <LAN_IDE_CP> ... Optimizing unit <LAN_IDE_CP> ...
implementation constraint: INIT=s : SET_FREQUENCY
implementation constraint: INIT=s : LAN_RST_SM_FSM_FFd8
implementation constraint: INIT=r : LAN_RST_SM_FSM_FFd7
implementation constraint: INIT=r : LAN_RST_SM_FSM_FFd6
implementation constraint: INIT=r : LAN_RST_SM_FSM_FFd5
implementation constraint: INIT=r : LAN_RST_SM_FSM_FFd4
implementation constraint: INIT=r : LAN_RST_SM_FSM_FFd3 implementation constraint: INIT=r : LAN_RST_SM_FSM_FFd3
implementation constraint: INIT=r : LAN_RST_SM_FSM_FFd2 implementation constraint: INIT=r : LAN_RST_SM_FSM_FFd2
implementation constraint: INIT=r : LAN_RST_SM_FSM_FFd1 implementation constraint: INIT=r : LAN_RST_SM_FSM_FFd1
@@ -283,23 +294,23 @@ Design Statistics
# IOs : 113 # IOs : 113
Cell Usage : Cell Usage :
# BELS : 745 # BELS : 879
# AND2 : 193 # AND2 : 267
# AND3 : 54 # AND3 : 41
# AND4 : 7 # AND4 : 7
# AND8 : 3 # AND8 : 3
# GND : 1 # GND : 1
# INV : 284 # INV : 333
# OR2 : 155 # OR2 : 166
# OR3 : 20 # OR3 : 32
# OR4 : 2 # OR4 : 3
# XOR2 : 26 # XOR2 : 26
# FlipFlops/Latches : 91 # FlipFlops/Latches : 111
# FD : 6 # FD : 25
# FDC : 8 # FDC : 5
# FDCE : 33 # FDCE : 33
# FDP : 7 # FDP : 10
# FDPE : 37 # FDPE : 38
# IO Buffers : 106 # IO Buffers : 106
# IBUF : 35 # IBUF : 35
# IOBUFE : 32 # IOBUFE : 32
@@ -308,14 +319,14 @@ Cell Usage :
========================================================================= =========================================================================
Total REAL time to Xst completion: 2.00 secs Total REAL time to Xst completion: 3.00 secs
Total CPU time to Xst completion: 2.72 secs Total CPU time to Xst completion: 2.77 secs
--> -->
Total memory usage is 4514348 kilobytes Total memory usage is 4514408 kilobytes
Number of errors : 0 ( 0 filtered) Number of errors : 0 ( 0 filtered)
Number of warnings : 13 ( 0 filtered) Number of warnings : 15 ( 0 filtered)
Number of infos : 1 ( 0 filtered) Number of infos : 1 ( 0 filtered)
Logic/LAN_IDE_V2/LAN_IDE_CP.tspec
+279 -99
View File
@@ -1,150 +1,330 @@
TS_CLK_EXT:FROM:D_IN<0>.Q:TO:D_OUT<0>.D:400 TS_CLK_EXT:FROM:D_IN<0>.Q:TO:D_OUT<0>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd3.Q:TO:D_OUT<0>.D:400 TS_CLK_EXT:FROM:SET_FREQUENCY.Q:TO:D_OUT<0>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd2.Q:TO:D_OUT<0>.D:400
TS_CLK_EXT:FROM:D_OUT<0>.Q:TO:D_OUT<0>.D:400 TS_CLK_EXT:FROM:D_OUT<0>.Q:TO:D_OUT<0>.D:400
TS_CLK_EXT:FROM:D_IN<8>.Q:TO:D_OUT<0>.D:400 TS_CLK_EXT:FROM:D_IN<8>.Q:TO:D_OUT<0>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd1.Q:TO:D_OUT<0>.D:400
TS_CLK_EXT:FROM:D_IN<2>.Q:TO:D_OUT<10>.D:400 TS_CLK_EXT:FROM:D_IN<2>.Q:TO:D_OUT<10>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd3.Q:TO:D_OUT<10>.D:400 TS_CLK_EXT:FROM:SET_FREQUENCY.Q:TO:D_OUT<10>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd2.Q:TO:D_OUT<10>.D:400
TS_CLK_EXT:FROM:D_OUT<10>.Q:TO:D_OUT<10>.D:400 TS_CLK_EXT:FROM:D_OUT<10>.Q:TO:D_OUT<10>.D:400
TS_CLK_EXT:FROM:D_IN<10>.Q:TO:D_OUT<10>.D:400 TS_CLK_EXT:FROM:D_IN<10>.Q:TO:D_OUT<10>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd1.Q:TO:D_OUT<10>.D:400
TS_CLK_EXT:FROM:D_IN<3>.Q:TO:D_OUT<11>.D:400 TS_CLK_EXT:FROM:D_IN<3>.Q:TO:D_OUT<11>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd3.Q:TO:D_OUT<11>.D:400 TS_CLK_EXT:FROM:SET_FREQUENCY.Q:TO:D_OUT<11>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd2.Q:TO:D_OUT<11>.D:400
TS_CLK_EXT:FROM:D_OUT<11>.Q:TO:D_OUT<11>.D:400 TS_CLK_EXT:FROM:D_OUT<11>.Q:TO:D_OUT<11>.D:400
TS_CLK_EXT:FROM:D_IN<11>.Q:TO:D_OUT<11>.D:400 TS_CLK_EXT:FROM:D_IN<11>.Q:TO:D_OUT<11>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd1.Q:TO:D_OUT<11>.D:400
TS_CLK_EXT:FROM:D_IN<1>.Q:TO:D_OUT<1>.D:400 TS_CLK_EXT:FROM:D_IN<1>.Q:TO:D_OUT<1>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd3.Q:TO:D_OUT<1>.D:400 TS_CLK_EXT:FROM:SET_FREQUENCY.Q:TO:D_OUT<1>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd2.Q:TO:D_OUT<1>.D:400
TS_CLK_EXT:FROM:D_OUT<1>.Q:TO:D_OUT<1>.D:400 TS_CLK_EXT:FROM:D_OUT<1>.Q:TO:D_OUT<1>.D:400
TS_CLK_EXT:FROM:D_IN<9>.Q:TO:D_OUT<1>.D:400 TS_CLK_EXT:FROM:D_IN<9>.Q:TO:D_OUT<1>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd1.Q:TO:D_OUT<1>.D:400
TS_CLK_EXT:FROM:D_IN<2>.Q:TO:D_OUT<2>.D:400 TS_CLK_EXT:FROM:D_IN<2>.Q:TO:D_OUT<2>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd3.Q:TO:D_OUT<2>.D:400 TS_CLK_EXT:FROM:SET_FREQUENCY.Q:TO:D_OUT<2>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd2.Q:TO:D_OUT<2>.D:400
TS_CLK_EXT:FROM:D_OUT<2>.Q:TO:D_OUT<2>.D:400 TS_CLK_EXT:FROM:D_OUT<2>.Q:TO:D_OUT<2>.D:400
TS_CLK_EXT:FROM:D_IN<10>.Q:TO:D_OUT<2>.D:400 TS_CLK_EXT:FROM:D_IN<10>.Q:TO:D_OUT<2>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd1.Q:TO:D_OUT<2>.D:400
TS_CLK_EXT:FROM:D_IN<3>.Q:TO:D_OUT<3>.D:400 TS_CLK_EXT:FROM:D_IN<3>.Q:TO:D_OUT<3>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd3.Q:TO:D_OUT<3>.D:400 TS_CLK_EXT:FROM:SET_FREQUENCY.Q:TO:D_OUT<3>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd2.Q:TO:D_OUT<3>.D:400
TS_CLK_EXT:FROM:D_OUT<3>.Q:TO:D_OUT<3>.D:400 TS_CLK_EXT:FROM:D_OUT<3>.Q:TO:D_OUT<3>.D:400
TS_CLK_EXT:FROM:D_IN<11>.Q:TO:D_OUT<3>.D:400 TS_CLK_EXT:FROM:D_IN<11>.Q:TO:D_OUT<3>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd1.Q:TO:D_OUT<3>.D:400
TS_CLK_EXT:FROM:D_IN<4>.Q:TO:D_OUT<4>.D:400 TS_CLK_EXT:FROM:D_IN<4>.Q:TO:D_OUT<4>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd1.Q:TO:D_OUT<4>.D:400 TS_CLK_EXT:FROM:SET_FREQUENCY.Q:TO:D_OUT<4>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd3.Q:TO:D_OUT<4>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd2.Q:TO:D_OUT<4>.D:400
TS_CLK_EXT:FROM:D_OUT<4>.Q:TO:D_OUT<4>.D:400 TS_CLK_EXT:FROM:D_OUT<4>.Q:TO:D_OUT<4>.D:400
TS_CLK_EXT:FROM:D_IN<12>.Q:TO:D_OUT<4>.D:400 TS_CLK_EXT:FROM:D_IN<12>.Q:TO:D_OUT<4>.D:400
TS_CLK_EXT:FROM:D_IN<5>.Q:TO:D_OUT<5>.D:400 TS_CLK_EXT:FROM:D_IN<5>.Q:TO:D_OUT<5>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd3.Q:TO:D_OUT<5>.D:400 TS_CLK_EXT:FROM:SET_FREQUENCY.Q:TO:D_OUT<5>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd2.Q:TO:D_OUT<5>.D:400
TS_CLK_EXT:FROM:D_OUT<5>.Q:TO:D_OUT<5>.D:400 TS_CLK_EXT:FROM:D_OUT<5>.Q:TO:D_OUT<5>.D:400
TS_CLK_EXT:FROM:D_IN<13>.Q:TO:D_OUT<5>.D:400 TS_CLK_EXT:FROM:D_IN<13>.Q:TO:D_OUT<5>.D:400
TS_CLK_EXT:FROM:D_IN<6>.Q:TO:D_OUT<6>.D:400 TS_CLK_EXT:FROM:D_IN<6>.Q:TO:D_OUT<6>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd3.Q:TO:D_OUT<6>.D:400 TS_CLK_EXT:FROM:SET_FREQUENCY.Q:TO:D_OUT<6>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd2.Q:TO:D_OUT<6>.D:400
TS_CLK_EXT:FROM:D_OUT<6>.Q:TO:D_OUT<6>.D:400 TS_CLK_EXT:FROM:D_OUT<6>.Q:TO:D_OUT<6>.D:400
TS_CLK_EXT:FROM:D_IN<14>.Q:TO:D_OUT<6>.D:400 TS_CLK_EXT:FROM:D_IN<14>.Q:TO:D_OUT<6>.D:400
TS_CLK_EXT:FROM:D_IN<7>.Q:TO:D_OUT<7>.D:400 TS_CLK_EXT:FROM:D_IN<7>.Q:TO:D_OUT<7>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd3.Q:TO:D_OUT<7>.D:400 TS_CLK_EXT:FROM:SET_FREQUENCY.Q:TO:D_OUT<7>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd2.Q:TO:D_OUT<7>.D:400
TS_CLK_EXT:FROM:D_OUT<7>.Q:TO:D_OUT<7>.D:400 TS_CLK_EXT:FROM:D_OUT<7>.Q:TO:D_OUT<7>.D:400
TS_CLK_EXT:FROM:D_IN<15>.Q:TO:D_OUT<7>.D:400 TS_CLK_EXT:FROM:D_IN<15>.Q:TO:D_OUT<7>.D:400
TS_CLK_EXT:FROM:D_IN<8>.Q:TO:D_OUT<8>.D:400 TS_CLK_EXT:FROM:D_IN<8>.Q:TO:D_OUT<8>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd1.Q:TO:D_OUT<8>.D:400 TS_CLK_EXT:FROM:SET_FREQUENCY.Q:TO:D_OUT<8>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd3.Q:TO:D_OUT<8>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd2.Q:TO:D_OUT<8>.D:400
TS_CLK_EXT:FROM:D_OUT<8>.Q:TO:D_OUT<8>.D:400 TS_CLK_EXT:FROM:D_OUT<8>.Q:TO:D_OUT<8>.D:400
TS_CLK_EXT:FROM:D_IN<0>.Q:TO:D_OUT<8>.D:400 TS_CLK_EXT:FROM:D_IN<0>.Q:TO:D_OUT<8>.D:400
TS_CLK_EXT:FROM:D_IN<9>.Q:TO:D_OUT<9>.D:400 TS_CLK_EXT:FROM:D_IN<9>.Q:TO:D_OUT<9>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd1.Q:TO:D_OUT<9>.D:400 TS_CLK_EXT:FROM:SET_FREQUENCY.Q:TO:D_OUT<9>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd3.Q:TO:D_OUT<9>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd2.Q:TO:D_OUT<9>.D:400
TS_CLK_EXT:FROM:D_OUT<9>.Q:TO:D_OUT<9>.D:400 TS_CLK_EXT:FROM:D_OUT<9>.Q:TO:D_OUT<9>.D:400
TS_CLK_EXT:FROM:D_IN<1>.Q:TO:D_OUT<9>.D:400 TS_CLK_EXT:FROM:D_IN<1>.Q:TO:D_OUT<9>.D:400
TS_CLK_EXT:FROM:D_OUT<0>.Q:TO:D_IN<0>.D:400
TS_CLK_EXT:FROM:D_IN<0>.Q:TO:D_IN<0>.D:400
TS_CLK_EXT:FROM:D_OUT<8>.Q:TO:D_IN<0>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd2.Q:TO:D_IN<0>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd3.Q:TO:D_IN<0>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd4.Q:TO:D_IN<0>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd5.Q:TO:D_IN<0>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd6.Q:TO:D_IN<0>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd7.Q:TO:D_IN<0>.D:400
TS_CLK_EXT:FROM:D_OUT<10>.Q:TO:D_IN<10>.D:400
TS_CLK_EXT:FROM:D_IN<10>.Q:TO:D_IN<10>.D:400
TS_CLK_EXT:FROM:D_OUT<2>.Q:TO:D_IN<10>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd2.Q:TO:D_IN<10>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd3.Q:TO:D_IN<10>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd4.Q:TO:D_IN<10>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd5.Q:TO:D_IN<10>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd6.Q:TO:D_IN<10>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd7.Q:TO:D_IN<10>.D:400
TS_CLK_EXT:FROM:D_OUT<11>.Q:TO:D_IN<11>.D:400
TS_CLK_EXT:FROM:D_IN<11>.Q:TO:D_IN<11>.D:400
TS_CLK_EXT:FROM:D_OUT<3>.Q:TO:D_IN<11>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd2.Q:TO:D_IN<11>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd3.Q:TO:D_IN<11>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd4.Q:TO:D_IN<11>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd5.Q:TO:D_IN<11>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd6.Q:TO:D_IN<11>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd7.Q:TO:D_IN<11>.D:400
TS_CLK_EXT:FROM:D_OUT<12>.Q:TO:D_IN<12>.D:400
TS_CLK_EXT:FROM:D_IN<12>.Q:TO:D_IN<12>.D:400
TS_CLK_EXT:FROM:D_OUT<4>.Q:TO:D_IN<12>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd2.Q:TO:D_IN<12>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd3.Q:TO:D_IN<12>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd4.Q:TO:D_IN<12>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd5.Q:TO:D_IN<12>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd6.Q:TO:D_IN<12>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd7.Q:TO:D_IN<12>.D:400
TS_CLK_EXT:FROM:D_OUT<13>.Q:TO:D_IN<13>.D:400
TS_CLK_EXT:FROM:D_IN<13>.Q:TO:D_IN<13>.D:400
TS_CLK_EXT:FROM:D_OUT<5>.Q:TO:D_IN<13>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd2.Q:TO:D_IN<13>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd3.Q:TO:D_IN<13>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd4.Q:TO:D_IN<13>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd5.Q:TO:D_IN<13>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd6.Q:TO:D_IN<13>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd7.Q:TO:D_IN<13>.D:400
TS_CLK_EXT:FROM:D_OUT<14>.Q:TO:D_IN<14>.D:400
TS_CLK_EXT:FROM:D_IN<14>.Q:TO:D_IN<14>.D:400
TS_CLK_EXT:FROM:D_OUT<6>.Q:TO:D_IN<14>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd2.Q:TO:D_IN<14>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd3.Q:TO:D_IN<14>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd4.Q:TO:D_IN<14>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd5.Q:TO:D_IN<14>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd6.Q:TO:D_IN<14>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd7.Q:TO:D_IN<14>.D:400
TS_CLK_EXT:FROM:D_OUT<15>.Q:TO:D_IN<15>.D:400
TS_CLK_EXT:FROM:D_IN<15>.Q:TO:D_IN<15>.D:400
TS_CLK_EXT:FROM:D_OUT<7>.Q:TO:D_IN<15>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd2.Q:TO:D_IN<15>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd3.Q:TO:D_IN<15>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd4.Q:TO:D_IN<15>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd5.Q:TO:D_IN<15>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd6.Q:TO:D_IN<15>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd7.Q:TO:D_IN<15>.D:400
TS_CLK_EXT:FROM:D_OUT<1>.Q:TO:D_IN<1>.D:400
TS_CLK_EXT:FROM:D_IN<1>.Q:TO:D_IN<1>.D:400
TS_CLK_EXT:FROM:D_OUT<9>.Q:TO:D_IN<1>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd2.Q:TO:D_IN<1>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd3.Q:TO:D_IN<1>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd4.Q:TO:D_IN<1>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd5.Q:TO:D_IN<1>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd6.Q:TO:D_IN<1>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd7.Q:TO:D_IN<1>.D:400
TS_CLK_EXT:FROM:D_OUT<2>.Q:TO:D_IN<2>.D:400
TS_CLK_EXT:FROM:D_IN<2>.Q:TO:D_IN<2>.D:400
TS_CLK_EXT:FROM:D_OUT<10>.Q:TO:D_IN<2>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd2.Q:TO:D_IN<2>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd3.Q:TO:D_IN<2>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd4.Q:TO:D_IN<2>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd5.Q:TO:D_IN<2>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd6.Q:TO:D_IN<2>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd7.Q:TO:D_IN<2>.D:400
TS_CLK_EXT:FROM:D_OUT<3>.Q:TO:D_IN<3>.D:400
TS_CLK_EXT:FROM:D_IN<3>.Q:TO:D_IN<3>.D:400
TS_CLK_EXT:FROM:D_OUT<11>.Q:TO:D_IN<3>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd2.Q:TO:D_IN<3>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd3.Q:TO:D_IN<3>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd4.Q:TO:D_IN<3>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd5.Q:TO:D_IN<3>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd6.Q:TO:D_IN<3>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd7.Q:TO:D_IN<3>.D:400
TS_CLK_EXT:FROM:D_OUT<4>.Q:TO:D_IN<4>.D:400
TS_CLK_EXT:FROM:D_IN<4>.Q:TO:D_IN<4>.D:400
TS_CLK_EXT:FROM:D_OUT<12>.Q:TO:D_IN<4>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd5.Q:TO:D_IN<4>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd6.Q:TO:D_IN<4>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd7.Q:TO:D_IN<4>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd2.Q:TO:D_IN<4>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd3.Q:TO:D_IN<4>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd4.Q:TO:D_IN<4>.D:400
TS_CLK_EXT:FROM:D_OUT<5>.Q:TO:D_IN<5>.D:400
TS_CLK_EXT:FROM:D_IN<5>.Q:TO:D_IN<5>.D:400
TS_CLK_EXT:FROM:D_OUT<13>.Q:TO:D_IN<5>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd2.Q:TO:D_IN<5>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd3.Q:TO:D_IN<5>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd4.Q:TO:D_IN<5>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd5.Q:TO:D_IN<5>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd6.Q:TO:D_IN<5>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd7.Q:TO:D_IN<5>.D:400
TS_CLK_EXT:FROM:D_OUT<6>.Q:TO:D_IN<6>.D:400
TS_CLK_EXT:FROM:D_IN<6>.Q:TO:D_IN<6>.D:400
TS_CLK_EXT:FROM:D_OUT<14>.Q:TO:D_IN<6>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd2.Q:TO:D_IN<6>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd3.Q:TO:D_IN<6>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd4.Q:TO:D_IN<6>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd5.Q:TO:D_IN<6>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd6.Q:TO:D_IN<6>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd7.Q:TO:D_IN<6>.D:400
TS_CLK_EXT:FROM:D_OUT<7>.Q:TO:D_IN<7>.D:400
TS_CLK_EXT:FROM:D_IN<7>.Q:TO:D_IN<7>.D:400
TS_CLK_EXT:FROM:D_OUT<15>.Q:TO:D_IN<7>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd2.Q:TO:D_IN<7>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd3.Q:TO:D_IN<7>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd4.Q:TO:D_IN<7>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd5.Q:TO:D_IN<7>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd6.Q:TO:D_IN<7>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd7.Q:TO:D_IN<7>.D:400
TS_CLK_EXT:FROM:D_OUT<8>.Q:TO:D_IN<8>.D:400
TS_CLK_EXT:FROM:D_IN<8>.Q:TO:D_IN<8>.D:400
TS_CLK_EXT:FROM:D_OUT<0>.Q:TO:D_IN<8>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd5.Q:TO:D_IN<8>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd6.Q:TO:D_IN<8>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd7.Q:TO:D_IN<8>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd2.Q:TO:D_IN<8>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd3.Q:TO:D_IN<8>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd4.Q:TO:D_IN<8>.D:400
TS_CLK_EXT:FROM:D_OUT<9>.Q:TO:D_IN<9>.D:400
TS_CLK_EXT:FROM:D_IN<9>.Q:TO:D_IN<9>.D:400
TS_CLK_EXT:FROM:D_OUT<1>.Q:TO:D_IN<9>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd2.Q:TO:D_IN<9>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd3.Q:TO:D_IN<9>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd4.Q:TO:D_IN<9>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd5.Q:TO:D_IN<9>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd6.Q:TO:D_IN<9>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd7.Q:TO:D_IN<9>.D:400
TS_CLK_EXT:FROM:D_OUT<12>.Q:TO:D_OUT<12>.D:400 TS_CLK_EXT:FROM:D_OUT<12>.Q:TO:D_OUT<12>.D:400
TS_CLK_EXT:FROM:D_IN<4>.Q:TO:D_OUT<12>.D:400 TS_CLK_EXT:FROM:D_IN<4>.Q:TO:D_OUT<12>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd1.Q:TO:D_OUT<12>.D:400 TS_CLK_EXT:FROM:SET_FREQUENCY.Q:TO:D_OUT<12>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd3.Q:TO:D_OUT<12>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd2.Q:TO:D_OUT<12>.D:400
TS_CLK_EXT:FROM:D_IN<12>.Q:TO:D_OUT<12>.D:400 TS_CLK_EXT:FROM:D_IN<12>.Q:TO:D_OUT<12>.D:400
TS_CLK_EXT:FROM:D_OUT<13>.Q:TO:D_OUT<13>.D:400 TS_CLK_EXT:FROM:D_OUT<13>.Q:TO:D_OUT<13>.D:400
TS_CLK_EXT:FROM:D_IN<5>.Q:TO:D_OUT<13>.D:400 TS_CLK_EXT:FROM:D_IN<5>.Q:TO:D_OUT<13>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd3.Q:TO:D_OUT<13>.D:400 TS_CLK_EXT:FROM:SET_FREQUENCY.Q:TO:D_OUT<13>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd2.Q:TO:D_OUT<13>.D:400
TS_CLK_EXT:FROM:D_IN<13>.Q:TO:D_OUT<13>.D:400 TS_CLK_EXT:FROM:D_IN<13>.Q:TO:D_OUT<13>.D:400
TS_CLK_EXT:FROM:D_OUT<14>.Q:TO:D_OUT<14>.D:400 TS_CLK_EXT:FROM:D_OUT<14>.Q:TO:D_OUT<14>.D:400
TS_CLK_EXT:FROM:D_IN<6>.Q:TO:D_OUT<14>.D:400 TS_CLK_EXT:FROM:D_IN<6>.Q:TO:D_OUT<14>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd3.Q:TO:D_OUT<14>.D:400 TS_CLK_EXT:FROM:SET_FREQUENCY.Q:TO:D_OUT<14>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd2.Q:TO:D_OUT<14>.D:400
TS_CLK_EXT:FROM:D_IN<14>.Q:TO:D_OUT<14>.D:400 TS_CLK_EXT:FROM:D_IN<14>.Q:TO:D_OUT<14>.D:400
TS_CLK_EXT:FROM:D_OUT<15>.Q:TO:D_OUT<15>.D:400 TS_CLK_EXT:FROM:D_OUT<15>.Q:TO:D_OUT<15>.D:400
TS_CLK_EXT:FROM:D_IN<7>.Q:TO:D_OUT<15>.D:400 TS_CLK_EXT:FROM:D_IN<7>.Q:TO:D_OUT<15>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd3.Q:TO:D_OUT<15>.D:400 TS_CLK_EXT:FROM:SET_FREQUENCY.Q:TO:D_OUT<15>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd2.Q:TO:D_OUT<15>.D:400
TS_CLK_EXT:FROM:D_IN<15>.Q:TO:D_OUT<15>.D:400 TS_CLK_EXT:FROM:D_IN<15>.Q:TO:D_OUT<15>.D:400
TS_CLK_EXT:FROM:D_OUT<8>.Q:TO:D_IN<0>.D:400 TS_CLK_EXT:FROM:A_LAN_OUT<0>.Q:TO:A_LAN_OUT<0>.D:400
TS_CLK_EXT:FROM:D_OUT<0>.Q:TO:D_IN<0>.D:400 TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd2.Q:TO:A_LAN_OUT<0>.D:400
TS_CLK_EXT:FROM:D_IN<0>.Q:TO:D_IN<0>.D:400 TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd3.Q:TO:A_LAN_OUT<0>.D:400
TS_CLK_EXT:FROM:D_OUT<2>.Q:TO:D_IN<10>.D:400 TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd4.Q:TO:A_LAN_OUT<0>.D:400
TS_CLK_EXT:FROM:D_OUT<10>.Q:TO:D_IN<10>.D:400 TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd5.Q:TO:A_LAN_OUT<0>.D:400
TS_CLK_EXT:FROM:D_IN<10>.Q:TO:D_IN<10>.D:400 TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd6.Q:TO:A_LAN_OUT<0>.D:400
TS_CLK_EXT:FROM:D_OUT<3>.Q:TO:D_IN<11>.D:400 TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd7.Q:TO:A_LAN_OUT<0>.D:400
TS_CLK_EXT:FROM:D_OUT<11>.Q:TO:D_IN<11>.D:400 TS_CLK_EXT:FROM:A_LAN_OUT<10>.Q:TO:A_LAN_OUT<10>.D:400
TS_CLK_EXT:FROM:D_IN<11>.Q:TO:D_IN<11>.D:400 TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd2.Q:TO:A_LAN_OUT<10>.D:400
TS_CLK_EXT:FROM:D_OUT<4>.Q:TO:D_IN<12>.D:400 TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd3.Q:TO:A_LAN_OUT<10>.D:400
TS_CLK_EXT:FROM:D_OUT<12>.Q:TO:D_IN<12>.D:400 TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd4.Q:TO:A_LAN_OUT<10>.D:400
TS_CLK_EXT:FROM:D_IN<12>.Q:TO:D_IN<12>.D:400 TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd5.Q:TO:A_LAN_OUT<10>.D:400
TS_CLK_EXT:FROM:D_OUT<5>.Q:TO:D_IN<13>.D:400 TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd6.Q:TO:A_LAN_OUT<10>.D:400
TS_CLK_EXT:FROM:D_OUT<13>.Q:TO:D_IN<13>.D:400 TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd7.Q:TO:A_LAN_OUT<10>.D:400
TS_CLK_EXT:FROM:D_IN<13>.Q:TO:D_IN<13>.D:400 TS_CLK_EXT:FROM:A_LAN_OUT<11>.Q:TO:A_LAN_OUT<11>.D:400
TS_CLK_EXT:FROM:D_OUT<6>.Q:TO:D_IN<14>.D:400 TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd2.Q:TO:A_LAN_OUT<11>.D:400
TS_CLK_EXT:FROM:D_OUT<14>.Q:TO:D_IN<14>.D:400 TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd3.Q:TO:A_LAN_OUT<11>.D:400
TS_CLK_EXT:FROM:D_IN<14>.Q:TO:D_IN<14>.D:400 TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd4.Q:TO:A_LAN_OUT<11>.D:400
TS_CLK_EXT:FROM:D_OUT<7>.Q:TO:D_IN<15>.D:400 TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd5.Q:TO:A_LAN_OUT<11>.D:400
TS_CLK_EXT:FROM:D_OUT<15>.Q:TO:D_IN<15>.D:400 TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd6.Q:TO:A_LAN_OUT<11>.D:400
TS_CLK_EXT:FROM:D_IN<15>.Q:TO:D_IN<15>.D:400 TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd7.Q:TO:A_LAN_OUT<11>.D:400
TS_CLK_EXT:FROM:D_OUT<9>.Q:TO:D_IN<1>.D:400 TS_CLK_EXT:FROM:A_LAN_OUT<12>.Q:TO:A_LAN_OUT<12>.D:400
TS_CLK_EXT:FROM:D_OUT<1>.Q:TO:D_IN<1>.D:400 TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd2.Q:TO:A_LAN_OUT<12>.D:400
TS_CLK_EXT:FROM:D_IN<1>.Q:TO:D_IN<1>.D:400 TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd3.Q:TO:A_LAN_OUT<12>.D:400
TS_CLK_EXT:FROM:D_OUT<2>.Q:TO:D_IN<2>.D:400 TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd4.Q:TO:A_LAN_OUT<12>.D:400
TS_CLK_EXT:FROM:D_OUT<10>.Q:TO:D_IN<2>.D:400 TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd5.Q:TO:A_LAN_OUT<12>.D:400
TS_CLK_EXT:FROM:D_IN<2>.Q:TO:D_IN<2>.D:400 TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd6.Q:TO:A_LAN_OUT<12>.D:400
TS_CLK_EXT:FROM:D_OUT<3>.Q:TO:D_IN<3>.D:400 TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd7.Q:TO:A_LAN_OUT<12>.D:400
TS_CLK_EXT:FROM:D_OUT<11>.Q:TO:D_IN<3>.D:400 TS_CLK_EXT:FROM:A_LAN_OUT<13>.Q:TO:A_LAN_OUT<13>.D:400
TS_CLK_EXT:FROM:D_IN<3>.Q:TO:D_IN<3>.D:400 TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd2.Q:TO:A_LAN_OUT<13>.D:400
TS_CLK_EXT:FROM:D_OUT<4>.Q:TO:D_IN<4>.D:400 TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd3.Q:TO:A_LAN_OUT<13>.D:400
TS_CLK_EXT:FROM:D_OUT<12>.Q:TO:D_IN<4>.D:400 TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd4.Q:TO:A_LAN_OUT<13>.D:400
TS_CLK_EXT:FROM:D_IN<4>.Q:TO:D_IN<4>.D:400 TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd5.Q:TO:A_LAN_OUT<13>.D:400
TS_CLK_EXT:FROM:D_OUT<5>.Q:TO:D_IN<5>.D:400 TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd6.Q:TO:A_LAN_OUT<13>.D:400
TS_CLK_EXT:FROM:D_OUT<13>.Q:TO:D_IN<5>.D:400 TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd7.Q:TO:A_LAN_OUT<13>.D:400
TS_CLK_EXT:FROM:D_IN<5>.Q:TO:D_IN<5>.D:400 TS_CLK_EXT:FROM:A_LAN_OUT<1>.Q:TO:A_LAN_OUT<1>.D:400
TS_CLK_EXT:FROM:D_OUT<6>.Q:TO:D_IN<6>.D:400 TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd2.Q:TO:A_LAN_OUT<1>.D:400
TS_CLK_EXT:FROM:D_OUT<14>.Q:TO:D_IN<6>.D:400 TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd3.Q:TO:A_LAN_OUT<1>.D:400
TS_CLK_EXT:FROM:D_IN<6>.Q:TO:D_IN<6>.D:400 TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd4.Q:TO:A_LAN_OUT<1>.D:400
TS_CLK_EXT:FROM:D_OUT<7>.Q:TO:D_IN<7>.D:400 TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd5.Q:TO:A_LAN_OUT<1>.D:400
TS_CLK_EXT:FROM:D_OUT<15>.Q:TO:D_IN<7>.D:400 TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd6.Q:TO:A_LAN_OUT<1>.D:400
TS_CLK_EXT:FROM:D_IN<7>.Q:TO:D_IN<7>.D:400 TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd7.Q:TO:A_LAN_OUT<1>.D:400
TS_CLK_EXT:FROM:D_OUT<8>.Q:TO:D_IN<8>.D:400 TS_CLK_EXT:FROM:A_LAN_OUT<2>.Q:TO:A_LAN_OUT<2>.D:400
TS_CLK_EXT:FROM:D_OUT<0>.Q:TO:D_IN<8>.D:400 TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd2.Q:TO:A_LAN_OUT<2>.D:400
TS_CLK_EXT:FROM:D_IN<8>.Q:TO:D_IN<8>.D:400 TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd3.Q:TO:A_LAN_OUT<2>.D:400
TS_CLK_EXT:FROM:D_OUT<9>.Q:TO:D_IN<9>.D:400 TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd4.Q:TO:A_LAN_OUT<2>.D:400
TS_CLK_EXT:FROM:D_OUT<1>.Q:TO:D_IN<9>.D:400 TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd5.Q:TO:A_LAN_OUT<2>.D:400
TS_CLK_EXT:FROM:D_IN<9>.Q:TO:D_IN<9>.D:400 TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd6.Q:TO:A_LAN_OUT<2>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd2.Q:TO:LAN_RST_SM_FSM_FFd2.D:400 TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd7.Q:TO:A_LAN_OUT<2>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd3.Q:TO:LAN_RST_SM_FSM_FFd2.D:400 TS_CLK_EXT:FROM:A_LAN_OUT<3>.Q:TO:A_LAN_OUT<3>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd1.Q:TO:LAN_RST_SM_FSM_FFd2.D:400 TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd2.Q:TO:A_LAN_OUT<3>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd2.Q:TO:LAN_RST_SM_FSM_FFd3.D:400 TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd3.Q:TO:A_LAN_OUT<3>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd1.Q:TO:LAN_RST_SM_FSM_FFd3.D:400 TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd4.Q:TO:A_LAN_OUT<3>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd5.Q:TO:A_LAN_OUT<3>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd6.Q:TO:A_LAN_OUT<3>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd7.Q:TO:A_LAN_OUT<3>.D:400
TS_CLK_EXT:FROM:A_LAN_OUT<4>.Q:TO:A_LAN_OUT<4>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd2.Q:TO:A_LAN_OUT<4>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd3.Q:TO:A_LAN_OUT<4>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd4.Q:TO:A_LAN_OUT<4>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd5.Q:TO:A_LAN_OUT<4>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd6.Q:TO:A_LAN_OUT<4>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd7.Q:TO:A_LAN_OUT<4>.D:400
TS_CLK_EXT:FROM:A_LAN_OUT<5>.Q:TO:A_LAN_OUT<5>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd2.Q:TO:A_LAN_OUT<5>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd3.Q:TO:A_LAN_OUT<5>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd4.Q:TO:A_LAN_OUT<5>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd5.Q:TO:A_LAN_OUT<5>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd6.Q:TO:A_LAN_OUT<5>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd7.Q:TO:A_LAN_OUT<5>.D:400
TS_CLK_EXT:FROM:A_LAN_OUT<6>.Q:TO:A_LAN_OUT<6>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd2.Q:TO:A_LAN_OUT<6>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd3.Q:TO:A_LAN_OUT<6>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd4.Q:TO:A_LAN_OUT<6>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd5.Q:TO:A_LAN_OUT<6>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd6.Q:TO:A_LAN_OUT<6>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd7.Q:TO:A_LAN_OUT<6>.D:400
TS_CLK_EXT:FROM:A_LAN_OUT<7>.Q:TO:A_LAN_OUT<7>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd2.Q:TO:A_LAN_OUT<7>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd3.Q:TO:A_LAN_OUT<7>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd4.Q:TO:A_LAN_OUT<7>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd5.Q:TO:A_LAN_OUT<7>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd6.Q:TO:A_LAN_OUT<7>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd7.Q:TO:A_LAN_OUT<7>.D:400
TS_CLK_EXT:FROM:A_LAN_OUT<8>.Q:TO:A_LAN_OUT<8>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd2.Q:TO:A_LAN_OUT<8>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd3.Q:TO:A_LAN_OUT<8>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd4.Q:TO:A_LAN_OUT<8>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd5.Q:TO:A_LAN_OUT<8>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd6.Q:TO:A_LAN_OUT<8>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd7.Q:TO:A_LAN_OUT<8>.D:400
TS_CLK_EXT:FROM:A_LAN_OUT<9>.Q:TO:A_LAN_OUT<9>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd2.Q:TO:A_LAN_OUT<9>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd3.Q:TO:A_LAN_OUT<9>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd4.Q:TO:A_LAN_OUT<9>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd5.Q:TO:A_LAN_OUT<9>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd6.Q:TO:A_LAN_OUT<9>.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd7.Q:TO:A_LAN_OUT<9>.D:400
TS_CLK_EXT:FROM:SET_FREQUENCY.Q:TO:LAN_RST_SM_FSM_FFd1.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd1.Q:TO:LAN_RST_SM_FSM_FFd1.D:400 TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd1.Q:TO:LAN_RST_SM_FSM_FFd1.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd2.Q:TO:LAN_RST_SM_FSM_FFd1.D:400 TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd2.Q:TO:LAN_RST_SM_FSM_FFd1.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd3.Q:TO:LAN_RST_SM_FSM_FFd1.D:400 TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd4.Q:TO:LAN_RST_SM_FSM_FFd3.D:400
TS_CLK_EXT:FROM:SET_FREQUENCY.Q:TO:LAN_RST_SM_FSM_FFd3.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd7.Q:TO:LAN_RST_SM_FSM_FFd6.D:400
TS_CLK_EXT:FROM:SET_FREQUENCY.Q:TO:LAN_RST_SM_FSM_FFd6.D:400
TS_CLK_EXT:FROM:SET_FREQUENCY.Q:TO:SET_FREQUENCY.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd1.Q:TO:SET_FREQUENCY.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd3.Q:TO:LAN_RST_SM_FSM_FFd2.D:400
TS_CLK_EXT:FROM:SET_FREQUENCY.Q:TO:LAN_RST_SM_FSM_FFd2.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd5.Q:TO:LAN_RST_SM_FSM_FFd4.D:400
TS_CLK_EXT:FROM:SET_FREQUENCY.Q:TO:LAN_RST_SM_FSM_FFd4.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd6.Q:TO:LAN_RST_SM_FSM_FFd5.D:400
TS_CLK_EXT:FROM:SET_FREQUENCY.Q:TO:LAN_RST_SM_FSM_FFd5.D:400
TS_CLK_EXT:FROM:SET_FREQUENCY.Q:TO:LAN_RST_SM_FSM_FFd7.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd8.Q:TO:LAN_RST_SM_FSM_FFd7.D:400
TS_CLK_EXT:FROM:SET_FREQUENCY.Q:TO:LAN_RST_SM_FSM_FFd8.D:400
TS_CLK_EXT:FROM:SET_FREQUENCY.Q:TO:LAN_WR_RST.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd3.Q:TO:LAN_WR_RST.D:400 TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd3.Q:TO:LAN_WR_RST.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd2.Q:TO:LAN_WR_RST.D:400 TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd6.Q:TO:LAN_WR_RST.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd3.Q:TO:LAN_CS_RST.D:400 TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd1.Q:TO:LAN_CS_RST.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd2.Q:TO:LAN_CS_RST.D:400 TS_CLK_EXT:FROM:SET_FREQUENCY.Q:TO:LAN_CS_RST.D:400
TS_CLK_EXT:FROM:LAN_RST_SM_FSM_FFd8.Q:TO:LAN_CS_RST.D:400
Logic/LAN_IDE_V2/LAN_IDE_CP.vm6
+10873 -9905
View File
File diff suppressed because it is too large Load Diff
Logic/LAN_IDE_V2/LAN_IDEz2v2.gise
+4 -4
View File
@@ -68,7 +68,7 @@
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1646521688" xil_pn:in_ck="-8368315473908605201" xil_pn:name="TRANEXT_xstsynthesize_xc9500xl" xil_pn:prop_ck="-5742752562858310575" xil_pn:start_ts="1646521683"> <transform xil_pn:end_ts="1646738026" xil_pn:in_ck="-8368315473908605201" xil_pn:name="TRANEXT_xstsynthesize_xc9500xl" xil_pn:prop_ck="3376396177162561847" xil_pn:start_ts="1646738022">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/> <status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
@@ -89,7 +89,7 @@
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1646521691" xil_pn:in_ck="-8547647177936735053" xil_pn:name="TRAN_ngdbuild" xil_pn:prop_ck="6932115226421322529" xil_pn:start_ts="1646521688"> <transform xil_pn:end_ts="1646738029" xil_pn:in_ck="-8547647177936735053" xil_pn:name="TRAN_ngdbuild" xil_pn:prop_ck="6932115226421322529" xil_pn:start_ts="1646738026">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="LAN_IDE_CP.bld"/> <outfile xil_pn:name="LAN_IDE_CP.bld"/>
@@ -98,7 +98,7 @@
<outfile xil_pn:name="_ngo"/> <outfile xil_pn:name="_ngo"/>
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/> <outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
</transform> </transform>
<transform xil_pn:end_ts="1646521717" xil_pn:in_ck="-2520376148396280667" xil_pn:name="TRANEXT_vm6File_xc9500xl" xil_pn:prop_ck="5255378627744949663" xil_pn:start_ts="1646521691"> <transform xil_pn:end_ts="1646738059" xil_pn:in_ck="-2520376148396280667" xil_pn:name="TRANEXT_vm6File_xc9500xl" xil_pn:prop_ck="-35312228449237523" xil_pn:start_ts="1646738029">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/> <status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
@@ -116,7 +116,7 @@
<outfile xil_pn:name="LAN_IDE_CP_html"/> <outfile xil_pn:name="LAN_IDE_CP_html"/>
<outfile xil_pn:name="LAN_IDE_CP_pad.csv"/> <outfile xil_pn:name="LAN_IDE_CP_pad.csv"/>
</transform> </transform>
<transform xil_pn:end_ts="1646521719" xil_pn:in_ck="-2520376148396271803" xil_pn:name="TRANEXT_crtProg_xc9500" xil_pn:prop_ck="-6294026017969277533" xil_pn:start_ts="1646521717"> <transform xil_pn:end_ts="1646738061" xil_pn:in_ck="-2520376148396271803" xil_pn:name="TRANEXT_crtProg_xc9500" xil_pn:prop_ck="-6294026017969277533" xil_pn:start_ts="1646738059">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="LAN_IDE_CP.jed"/> <outfile xil_pn:name="LAN_IDE_CP.jed"/>
Logic/LAN_IDE_V2/LAN_IDEz2v2.xise
+2 -2
View File
@@ -52,7 +52,7 @@
<property xil_pn:name="Compile uni9000 (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Compile uni9000 (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Programmable GND Pins on Unused I/O" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Create Programmable GND Pins on Unused I/O" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Default Powerup Value of Registers" xil_pn:value="Low" xil_pn:valueState="default"/> <property xil_pn:name="Default Powerup Value of Registers" xil_pn:value="High" xil_pn:valueState="non-default"/>
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/> <property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
<property xil_pn:name="Device" xil_pn:value="xc95288xl" xil_pn:valueState="non-default"/> <property xil_pn:name="Device" xil_pn:value="xc95288xl" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Family" xil_pn:value="XC9500XL CPLDs" xil_pn:valueState="non-default"/> <property xil_pn:name="Device Family" xil_pn:value="XC9500XL CPLDs" xil_pn:valueState="non-default"/>
@@ -63,7 +63,7 @@
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/> <property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
<property xil_pn:name="Exhaustive Fit Mode" xil_pn:value="true" xil_pn:valueState="non-default"/> <property xil_pn:name="Exhaustive Fit Mode" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Gray" xil_pn:valueState="non-default"/> <property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="VHDL" xil_pn:valueState="default"/> <property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="VHDL" xil_pn:valueState="default"/> <property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="VHDL" xil_pn:valueState="default"/>