Dominick.Vansevenant/Zorro-LAN-IDE
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changed write-data preparation for lan

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This commit is contained in:
MHeinrichs
2022-03-14 00:10:05 +01:00
parent 066344f4bf
commit 7444299170
2 changed files with 1320 additions and 1298 deletions
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Logic/LAN_IDE_V2/LAN_IDE_CP-z3v2.jed
+1273 -1273
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File diff suppressed because it is too large Load Diff
Logic/LAN_IDE_V2/LAN_IDE_CP.vhd
+46 -24
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@@ -132,7 +132,7 @@ architecture Behavioral of LAN_IDE_CP is
signal AUTO_CONFIG_Z2_DONE:STD_LOGIC_VECTOR(2 downto 0):="000"; signal AUTO_CONFIG_Z2_DONE:STD_LOGIC_VECTOR(2 downto 0):="000";
signal AUTO_CONFIG_Z2_DONE_CYCLE:STD_LOGIC_VECTOR(2 downto 0):="000"; signal AUTO_CONFIG_Z2_DONE_CYCLE:STD_LOGIC_VECTOR(2 downto 0):="000";
signal SHUT_UP_Z2:STD_LOGIC_VECTOR(2 downto 0):="111"; signal SHUT_UP_Z2:STD_LOGIC_VECTOR(2 downto 0):="111";
signal LAN_BASEADR:STD_LOGIC_VECTOR(15 downto 0); signal LAN_BASEADR:STD_LOGIC_VECTOR(7 downto 0);
signal LAN_INT_ENABLE: std_logic :='0'; signal LAN_INT_ENABLE: std_logic :='0';
signal LAN_RD_S: std_logic; signal LAN_RD_S: std_logic;
signal LAN_WRH_S: std_logic; signal LAN_WRH_S: std_logic;
@@ -273,7 +273,7 @@ begin
--lan base --lan base
--if(Z3='1' and (D(15 downto 8) & A(23 downto 16)) = LAN_BASEADR and SHUT_UP_Z2(0)='0' )then --if(Z3='1' and (D(15 downto 8) & A(23 downto 16)) = LAN_BASEADR and SHUT_UP_Z2(0)='0' )then
if((D(15 downto 8) ) = LAN_BASEADR(15 downto 8) and SHUT_UP_Z2(0)='0' )then --only the upper 8 bits matter!!! if((D(15 downto 8) ) = LAN_BASEADR and SHUT_UP_Z2(0)='0' )then --only the upper 8 bits matter!!!
if(A(14 downto 13)<"11")then if(A(14 downto 13)<"11")then
DQ_SWAP <= '1'; DQ_SWAP <= '1';
else else
@@ -358,6 +358,45 @@ begin
end if; end if;
end process lan_rst_gen; end process lan_rst_gen;
--lan signal generation: all Signals are HIGH active!
lan_data_multiplex: process (CLK_EXT,reset)
begin
if(reset ='0' ) then
DQ_DATA(15 downto 0) <= x"FFFF";
elsif rising_edge(CLK_EXT) then
-- this is a quite complex thing for a cpld
-- so I have to move this out of the cycle start condition and prepare it for every loop
if(LAN_SM = nop) then
-- prepare the data for write
if(Z3_DS(3 downto 2) < "11")then
if(DQ_SWAP='0') then
DQ_DATA(15 downto 0) <= Z3_DATA_IN(31 downto 16);
else
DQ_DATA(15 downto 0) <= Z3_DATA_IN(23 downto 16) & Z3_DATA_IN(31 downto 24);
end if;
else -- lower word!
if(DQ_SWAP='0') then
DQ_DATA(15 downto 0) <= Z3_DATA_IN(15 downto 0);
else
DQ_DATA(15 downto 0) <= Z3_DATA_IN( 7 downto 0) & Z3_DATA_IN(15 downto 8);
end if;
end if;
elsif(LAN_SM = end_write_upper)then
-- prepare the data for lower write
if(DQ_SWAP='0') then
DQ_DATA(15 downto 0) <= Z3_DATA_IN(15 downto 0);
else
DQ_DATA(15 downto 0) <= Z3_DATA_IN( 7 downto 0) & Z3_DATA_IN(15 downto 8);
end if;
end if;
end if;
end process lan_data_multiplex;
--lan signal generation: all Signals are HIGH active! --lan signal generation: all Signals are HIGH active!
lan_rw_gen: process (CLK_EXT,LAN_SM_RST) lan_rw_gen: process (CLK_EXT,LAN_SM_RST)
begin begin
@@ -369,7 +408,6 @@ begin
Z3_A_LOW <= '0'; Z3_A_LOW <= '0';
LAN_READY <= '0'; LAN_READY <= '0';
Z3_DATA(31 downto 0) <= x"FFFFFFFF"; Z3_DATA(31 downto 0) <= x"FFFFFFFF";
DQ_DATA(15 downto 0) <= x"FFFF";
elsif rising_edge(CLK_EXT) then elsif rising_edge(CLK_EXT) then
--default values --default values
LAN_RD_S <= '0'; LAN_RD_S <= '0';
@@ -384,21 +422,12 @@ begin
-- prepare the data for write -- prepare the data for write
-- this is a quite complex thing for a cpld -- this is a quite complex thing for a cpld
-- so I have to move this out of the cycle start condition and prepare it for every loop -- so I have to move this out of the cycle start condition and prepare it for every loop
if(Z3_DS(3 downto 2) < "11")then if(Z3_DS(3 downto 2) = "11")then
if(DQ_SWAP='0') then -- lower word!
DQ_DATA(15 downto 0) <= Z3_DATA_IN(31 downto 16);
else
DQ_DATA(15 downto 0) <= Z3_DATA_IN(23 downto 16) & Z3_DATA_IN(31 downto 24);
end if;
else -- lower word!
Z3_A_LOW <= '1'; Z3_A_LOW <= '1';
if(DQ_SWAP='0') then
DQ_DATA(15 downto 0) <= Z3_DATA_IN(15 downto 0);
else
DQ_DATA(15 downto 0) <= Z3_DATA_IN( 7 downto 0) & Z3_DATA_IN(15 downto 8);
end if;
end if; end if;
if(Z3_ADR(15)='1')then if(Z3_ADR(15)='1')then
LAN_SM <= config_rw; LAN_SM <= config_rw;
elsif(RW='1')then --read from MSB elsif(RW='1')then --read from MSB
@@ -463,13 +492,6 @@ begin
when wait_write_upper=> when wait_write_upper=>
LAN_SM<=end_write_upper; LAN_SM<=end_write_upper;
when end_write_upper=> when end_write_upper=>
-- prepare the data for write
if(DQ_SWAP='0') then
DQ_DATA(15 downto 0) <= Z3_DATA_IN(15 downto 0);
else
DQ_DATA(15 downto 0) <= Z3_DATA_IN( 7 downto 0) & Z3_DATA_IN(15 downto 8);
end if;
if(Z3_DS(1 downto 0) = "11")then -- no lower half if(Z3_DS(1 downto 0) = "11")then -- no lower half
LAN_READY <='1'; LAN_READY <='1';
LAN_SM <= end_write_upper; -- stay here until cylce end LAN_SM <= end_write_upper; -- stay here until cylce end
@@ -513,7 +535,7 @@ begin
IDE_BASEADR<=x"FF"; IDE_BASEADR<=x"FF";
CP_BASEADR<=x"FF"; CP_BASEADR<=x"FF";
AUTO_CONFIG_Z2_DONE <="000"; AUTO_CONFIG_Z2_DONE <="000";
LAN_BASEADR<=x"FFFF"; LAN_BASEADR<=x"FF";
elsif rising_edge(CLK_EXT) then -- no reset, so wait for rising edge of the clock elsif rising_edge(CLK_EXT) then -- no reset, so wait for rising edge of the clock
D_Z2_OUT<="1111"; D_Z2_OUT<="1111";
if(AS='1')then if(AS='1')then
@@ -584,7 +606,7 @@ begin
D_Z2_OUT <= "1111" ; D_Z2_OUT <= "1111" ;
if(RW='0')then if(RW='0')then
if(AUTO_CONFIG_Z2_DONE(0) = '0')then if(AUTO_CONFIG_Z2_DONE(0) = '0')then
LAN_BASEADR(15 downto 0) <= D(15 downto 0); --Base adress LAN_BASEADR(7 downto 0) <= D(15 downto 8); --Base adress
SHUT_UP_Z2(0) <='0'; --enable board SHUT_UP_Z2(0) <='0'; --enable board
AUTO_CONFIG_Z2_DONE_CYCLE(0) <= '1'; --done here AUTO_CONFIG_Z2_DONE_CYCLE(0) <= '1'; --done here
end if; end if;