Dominick.Vansevenant/Zorro-LAN-IDE
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Adopted the fixes for no IDE-ROM and no IDE-Drive from Z2-Firmware

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This commit is contained in:
MHeinrichs
2022-03-13 20:37:49 +01:00
parent e2a09186e2
commit 066344f4bf
4 changed files with 1327 additions and 1319 deletions
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Logic/LAN_IDE_V2/LAN_IDE_CP-z3v2.jed
+1305 -1305
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Logic/LAN_IDE_V2/LAN_IDE_CP.vhd
+18 -10
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@@ -155,6 +155,7 @@ architecture Behavioral of LAN_IDE_CP is
signal AMIGA_CLK:STD_LOGIC;
signal DS:STD_LOGIC;
signal AS_D:STD_LOGIC;
signal LAN_CS_RST: std_logic;
signal LAN_WR_RST: std_logic;
@@ -181,7 +182,16 @@ begin
Z3_DS <= UDS & LDS & DS1 & DS0;
AMIGA_CLK <= not (C1 xor C3);
DS <= UDS and LDS;
AS_DELAY: process(CLK_EXT,reset)
begin
if(reset = '0' )then
AS_D <= '1';
elsif(rising_edge(AMIGA_CLK))then
AS_D <= AS;
end if;
end process;
clock_init: process(reset,CLK_EXT)
begin
if(reset='0')then
@@ -624,9 +634,9 @@ begin
--signal assignment
D(15 downto 0) <= Z3_DATA(31 downto 16) when RW='1' and FCS='0' and LAN_ACCESS ='1' else
D_Z2_OUT & x"FFF" when RW='1' and AS='0' and AUTOCONFIG_Z2_ACCESS ='1' else
DQ(7 downto 0)&DQ(7 downto 0) when RW='1' and CP_ACCESS = '1' and AS='0' else
DQ(15 downto 0) when RW='1' and IDE_ACCESS = '1' and AS='0' else
D_Z2_OUT & x"FFF" when RW='1' and AS_D='0' and AUTOCONFIG_Z2_ACCESS ='1' else
DQ(7 downto 0)&DQ(7 downto 0) when RW='1' and CP_ACCESS = '1' and AS_D='0' else
DQ(15 downto 0) when RW='1' and IDE_ACCESS = '1' and AS_D='0' else
(others => 'Z');
A(23 downto 8) <= Z3_DATA(15 downto 0) when RW='1' and FCS='0' and LAN_ACCESS ='1' else
@@ -639,12 +649,10 @@ begin
DQ_DATA(15 downto 0) when RW='0' and FCS='0' and Z3_DS <"1111" and LAN_ACCESS ='1' else
D(15 downto 8 ) & D(15 downto 8) when RW='0' and AS='0' and CP_ACCESS ='1' else
D when RW='0' and AS='0' and IDE_ACCESS ='1' else
x"0000" when RW = '1' and AS= '0' and IDE_ACCESS ='1' and ROM_OE_S ='1' and IDE_R_S = '1' else --clear the bus just before an IDE-Read!
(others => 'Z');
INT2_OUT <= '0' when LAN_IRQ_OUT = '0' and LAN_INT_ENABLE = '1' else
--'0' when CP_IRQ = '0' else
'Z';
@@ -688,9 +696,9 @@ begin
end if;
end if;
end process ide_rw_gen;
IDE_W <= IDE_W_S when AS='0' else '1';
IDE_R <= IDE_R_S when AS='0' else '1';
ROM_OE<= ROM_OE_S when AS='0' else '1';
IDE_W <= IDE_W_S when AS ='0' else '1';
IDE_R <= IDE_R_S when AS ='0' else '1';
ROM_OE<= ROM_OE_S when AS ='0' else '1';
IDE_CS(0)<= not(A(12));
IDE_CS(1)<= not(A(13));
IDE_A(2 downto 0) <= A(11 downto 9);
Logic/LAN_IDE_V2/LAN_IDEz3v2.xise
+4 -4
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@@ -62,8 +62,8 @@
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
<property xil_pn:name="Exhaustive Fit Mode" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Sequential" xil_pn:valueState="non-default"/>
<property xil_pn:name="Exhaustive Fit Mode" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Gray" xil_pn:valueState="non-default"/>
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="VHDL" xil_pn:valueState="default"/>
@@ -111,8 +111,8 @@
<property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="4" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Effort" xil_pn:value="High" xil_pn:valueState="non-default"/>
<property xil_pn:name="Optimization Goal" xil_pn:value="Area" xil_pn:valueState="non-default"/>
<property xil_pn:name="Other CPLD Fitter Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Fit" xil_pn:value="" xil_pn:valueState="default"/>
Logic/LAN_IDE_V2/ZORO_LAN_IDE_Z3.ipf
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