Dominick.Vansevenant/Zorro-LAN-IDE
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Converted logic to all registers high during power up AND reset!

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This commit is contained in:
MHeinrichs
2022-03-08 12:39:34 +01:00
parent 88cdb9fb52
commit 65af379ced
13 changed files with 19433 additions and 17623 deletions
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Logic/LAN_IDE_V2/LAN_IDE_CP.syr
+35 -35
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@@ -10,7 +10,7 @@ Total CPU time to Xst completion: 0.08 secs
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.08 secs
Total CPU time to Xst completion: 0.09 secs
--> Reading design: LAN_IDE_CP.prj
@@ -76,7 +76,8 @@ wysiwyg : NO
* HDL Compilation *
=========================================================================
Compiling vhdl file "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE_V2/LAN_IDE_CP-Z2v2.vhd" in Library work.
Architecture behavioral of Entity lan_ide_cp is up to date.
Entity <lan_ide_cp> compiled.
Entity <lan_ide_cp> (Architecture <behavioral>) compiled.
=========================================================================
* Design Hierarchy Analysis *
@@ -88,7 +89,7 @@ Analyzing hierarchy for entity <LAN_IDE_CP> in library <work> (architecture <beh
* HDL Analysis *
=========================================================================
Analyzing Entity <LAN_IDE_CP> in library <work> (Architecture <behavioral>).
WARNING:Xst:819 - "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE_V2/LAN_IDE_CP-Z2v2.vhd" line 161: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
WARNING:Xst:819 - "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE_V2/LAN_IDE_CP-Z2v2.vhd" line 160: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<AMIGA_CLK>
Entity <LAN_IDE_CP> analyzed. Unit <LAN_IDE_CP> generated.
@@ -107,7 +108,6 @@ WARNING:Xst:647 - Input <DS1> is never used. This port will be preserved and lef
WARNING:Xst:647 - Input <FCS> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Z3> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <MTCR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:646 - Signal <lancp> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ROM_OE_D0> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <LAN_INT_D0> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <IDE_TERM> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
@@ -119,10 +119,10 @@ WARNING:Xst:646 - Signal <DECODE_RESET> is assigned but never used. This unconne
| States | 8 |
| Transitions | 8 |
| Inputs | 0 |
| Outputs | 10 |
| Outputs | 9 |
| Clock | CLK_EXT (rising_edge) |
| Reset | LAN_RST_SM$and0000 (positive) |
| Reset type | synchronous |
| Reset type | asynchronous |
| Reset State | nop |
| Power Up State | nop |
| Encoding | automatic |
@@ -137,15 +137,15 @@ WARNING:Xst:646 - Signal <DECODE_RESET> is assigned but never used. This unconne
Found 1-bit tristate buffer for signal <INT2_OUT>.
Found 1-bit tristate buffer for signal <INT6_OUT>.
Found 14-bit register for signal <A_LAN_OUT>.
Found 1-bit xor2 for signal <AMIGA_CLK$xor0000> created at line 153.
Found 1-bit xor2 for signal <AMIGA_CLK$xor0000> created at line 152.
Found 1-bit register for signal <AS_D>.
Found 2-bit register for signal <AUTO_CONFIG_DONE>.
Found 2-bit register for signal <AUTO_CONFIG_DONE_CYCLE>.
Found 2-bit subtractor for signal <AUTO_CONFIG_DONE_CYCLE$addsub0000> created at line 472.
Found 2-bit subtractor for signal <AUTO_CONFIG_DONE_CYCLE$addsub0000> created at line 466.
Found 1-bit register for signal <autoconfig>.
Found 2-bit comparator greater for signal <autoconfig$cmp_gt0000> created at line 235.
Found 2-bit comparator greater for signal <autoconfig$cmp_gt0000> created at line 232.
Found 1-bit register for signal <cp>.
Found 8-bit comparator equal for signal <cp$cmp_eq0000> created at line 245.
Found 8-bit comparator equal for signal <cp$cmp_eq0000> created at line 241.
Found 8-bit register for signal <CP_BASEADR>.
Found 1-bit register for signal <CP_RD_S>.
Found 1-bit register for signal <CP_WE_QUIRK>.
@@ -153,17 +153,17 @@ WARNING:Xst:646 - Signal <DECODE_RESET> is assigned but never used. This unconne
Found 16-bit register for signal <D_IN>.
Found 16-bit register for signal <D_OUT>.
Found 4-bit register for signal <Dout1>.
Found 3-bit comparator greater for signal <Dout1$cmp_gt0000> created at line 399.
Found 3-bit comparator greater for signal <Dout1$cmp_gt0000> created at line 393.
Found 1-bit register for signal <ide>.
Found 8-bit comparator equal for signal <ide$cmp_eq0000> created at line 249.
Found 8-bit comparator equal for signal <ide$cmp_eq0000> created at line 244.
Found 8-bit register for signal <IDE_BASEADR>.
Found 1-bit register for signal <IDE_ENABLE>.
Found 1-bit register for signal <IDE_R_S>.
Found 1-bit register for signal <IDE_W_S>.
Found 1-bit register for signal <lan_adr>.
Found 1-bit register for signal <lan_adr_sw>.
Found 8-bit comparator equal for signal <lan_adr_sw$cmp_eq0000> created at line 238.
Found 2-bit comparator less for signal <lan_adr_sw$cmp_lt0000> created at line 239.
Found 8-bit comparator equal for signal <lan_adr_sw$cmp_eq0000> created at line 235.
Found 2-bit comparator less for signal <lan_adr_sw$cmp_lt0000> created at line 236.
Found 8-bit register for signal <LAN_BASEADR>.
Found 1-bit register for signal <LAN_CS_RST>.
Found 1-bit register for signal <LAN_INT_ENABLE>.
@@ -178,7 +178,7 @@ WARNING:Xst:646 - Signal <DECODE_RESET> is assigned but never used. This unconne
Found 3-bit register for signal <SHUT_UP>.
Summary:
inferred 1 Finite State Machine(s).
inferred 22 D-type flip-flop(s).
inferred 24 D-type flip-flop(s).
inferred 1 Adder/Subtractor(s).
inferred 6 Comparator(s).
inferred 1 Xor(s).
@@ -240,8 +240,8 @@ Macro Statistics
# FSMs : 1
# Adders/Subtractors : 1
2-bit subtractor : 1
# Registers : 22
Flip-Flops : 22
# Registers : 24
Flip-Flops : 24
# Comparators : 3
8-bit comparator equal : 3
@@ -255,14 +255,14 @@ WARNING:Xst:1426 - The value init of the FF/Latch SET_FREQUENCY hinder the const
Optimizing unit <LAN_IDE_CP> ...
implementation constraint: INIT=s : SET_FREQUENCY
implementation constraint: INIT=s : LAN_RST_SM_FSM_FFd8
implementation constraint: INIT=r : LAN_RST_SM_FSM_FFd7
implementation constraint: INIT=r : LAN_RST_SM_FSM_FFd6
implementation constraint: INIT=r : LAN_RST_SM_FSM_FFd5
implementation constraint: INIT=r : LAN_RST_SM_FSM_FFd4
implementation constraint: INIT=r : LAN_RST_SM_FSM_FFd3
implementation constraint: INIT=r : LAN_RST_SM_FSM_FFd2
implementation constraint: INIT=r : LAN_RST_SM_FSM_FFd1
implementation constraint: INIT=r : LAN_RST_SM_FSM_FFd2
implementation constraint: INIT=r : LAN_RST_SM_FSM_FFd3
implementation constraint: INIT=r : LAN_RST_SM_FSM_FFd4
implementation constraint: INIT=r : LAN_RST_SM_FSM_FFd5
implementation constraint: INIT=r : LAN_RST_SM_FSM_FFd6
implementation constraint: INIT=r : LAN_RST_SM_FSM_FFd7
implementation constraint: INIT=s : LAN_RST_SM_FSM_FFd8
=========================================================================
* Partition Report *
@@ -294,22 +294,22 @@ Design Statistics
# IOs : 113
Cell Usage :
# BELS : 879
# AND2 : 267
# AND3 : 41
# AND4 : 7
# BELS : 884
# AND2 : 255
# AND3 : 44
# AND4 : 6
# AND8 : 3
# GND : 1
# INV : 333
# INV : 348
# OR2 : 166
# OR3 : 32
# OR4 : 3
# XOR2 : 26
# FlipFlops/Latches : 111
# FD : 25
# FDC : 5
# FD : 15
# FDC : 7
# FDCE : 33
# FDP : 10
# FDP : 18
# FDPE : 38
# IO Buffers : 106
# IBUF : 35
@@ -320,13 +320,13 @@ Cell Usage :
Total REAL time to Xst completion: 3.00 secs
Total CPU time to Xst completion: 2.77 secs
Total CPU time to Xst completion: 2.76 secs
-->
Total memory usage is 4514408 kilobytes
Total memory usage is 4514448 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 15 ( 0 filtered)
Number of warnings : 14 ( 0 filtered)
Number of infos : 1 ( 0 filtered)