333 lines
16 KiB
Plaintext
333 lines
16 KiB
Plaintext
Release 14.7 - xst P.20131013 (nt64)
|
|
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
|
|
--> Parameter TMPDIR set to xst/projnav.tmp
|
|
|
|
|
|
Total REAL time to Xst completion: 0.00 secs
|
|
Total CPU time to Xst completion: 0.08 secs
|
|
|
|
--> Parameter xsthdpdir set to xst
|
|
|
|
|
|
Total REAL time to Xst completion: 0.00 secs
|
|
Total CPU time to Xst completion: 0.09 secs
|
|
|
|
--> Reading design: LAN_IDE_CP.prj
|
|
|
|
TABLE OF CONTENTS
|
|
1) Synthesis Options Summary
|
|
2) HDL Compilation
|
|
3) Design Hierarchy Analysis
|
|
4) HDL Analysis
|
|
5) HDL Synthesis
|
|
5.1) HDL Synthesis Report
|
|
6) Advanced HDL Synthesis
|
|
6.1) Advanced HDL Synthesis Report
|
|
7) Low Level Synthesis
|
|
8) Partition Report
|
|
9) Final Report
|
|
|
|
=========================================================================
|
|
* Synthesis Options Summary *
|
|
=========================================================================
|
|
---- Source Parameters
|
|
Input File Name : "LAN_IDE_CP.prj"
|
|
Input Format : mixed
|
|
Ignore Synthesis Constraint File : NO
|
|
|
|
---- Target Parameters
|
|
Output File Name : "LAN_IDE_CP"
|
|
Output Format : NGC
|
|
Target Device : XC9500XL CPLDs
|
|
|
|
---- Source Options
|
|
Top Module Name : LAN_IDE_CP
|
|
Automatic FSM Extraction : YES
|
|
FSM Encoding Algorithm : Auto
|
|
Safe Implementation : No
|
|
Mux Extraction : Yes
|
|
Resource Sharing : YES
|
|
|
|
---- Target Options
|
|
Add IO Buffers : YES
|
|
MACRO Preserve : YES
|
|
XOR Preserve : YES
|
|
Equivalent register Removal : YES
|
|
|
|
---- General Options
|
|
Optimization Goal : Speed
|
|
Optimization Effort : 2
|
|
Keep Hierarchy : Yes
|
|
Netlist Hierarchy : As_Optimized
|
|
RTL Output : Yes
|
|
Hierarchy Separator : /
|
|
Bus Delimiter : <>
|
|
Case Specifier : Maintain
|
|
Verilog 2001 : YES
|
|
|
|
---- Other Options
|
|
Clock Enable : YES
|
|
wysiwyg : NO
|
|
|
|
=========================================================================
|
|
|
|
|
|
=========================================================================
|
|
* HDL Compilation *
|
|
=========================================================================
|
|
Compiling vhdl file "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE_V2/LAN_IDE_CP-Z2v2.vhd" in Library work.
|
|
Entity <lan_ide_cp> compiled.
|
|
Entity <lan_ide_cp> (Architecture <behavioral>) compiled.
|
|
|
|
=========================================================================
|
|
* Design Hierarchy Analysis *
|
|
=========================================================================
|
|
Analyzing hierarchy for entity <LAN_IDE_CP> in library <work> (architecture <behavioral>).
|
|
|
|
|
|
=========================================================================
|
|
* HDL Analysis *
|
|
=========================================================================
|
|
Analyzing Entity <LAN_IDE_CP> in library <work> (Architecture <behavioral>).
|
|
WARNING:Xst:819 - "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE_V2/LAN_IDE_CP-Z2v2.vhd" line 160: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
|
|
<AMIGA_CLK>
|
|
Entity <LAN_IDE_CP> analyzed. Unit <LAN_IDE_CP> generated.
|
|
|
|
|
|
=========================================================================
|
|
* HDL Synthesis *
|
|
=========================================================================
|
|
|
|
Performing bidirectional port resolution...
|
|
INFO:Xst:2561 - Always blocking tristate driving signal <A> in unit <LAN_IDE_CP> is removed.
|
|
|
|
Synthesizing Unit <LAN_IDE_CP>.
|
|
Related source file is "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE_V2/LAN_IDE_CP-Z2v2.vhd".
|
|
WARNING:Xst:647 - Input <DS0> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <DS1> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <FCS> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <Z3> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <MTCR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:646 - Signal <ROM_OE_D0> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
|
|
WARNING:Xst:1780 - Signal <LAN_INT_D0> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
|
|
WARNING:Xst:646 - Signal <IDE_TERM> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
|
|
WARNING:Xst:1780 - Signal <DTACK_S> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
|
|
WARNING:Xst:646 - Signal <DS_D> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
|
|
WARNING:Xst:646 - Signal <DECODE_RESET> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
|
|
Found finite state machine <FSM_0> for signal <LAN_RST_SM>.
|
|
-----------------------------------------------------------------------
|
|
| States | 8 |
|
|
| Transitions | 8 |
|
|
| Inputs | 0 |
|
|
| Outputs | 9 |
|
|
| Clock | CLK_EXT (rising_edge) |
|
|
| Reset | LAN_RST_SM$and0000 (positive) |
|
|
| Reset type | asynchronous |
|
|
| Reset State | nop |
|
|
| Power Up State | nop |
|
|
| Encoding | automatic |
|
|
| Implementation | automatic |
|
|
-----------------------------------------------------------------------
|
|
Found 16-bit tristate buffer for signal <D>.
|
|
Found 16-bit tristate buffer for signal <DQ>.
|
|
Found 1-bit tristate buffer for signal <OWN>.
|
|
Found 1-bit tristate buffer for signal <OVR>.
|
|
Found 1-bit tristate buffer for signal <MTACK>.
|
|
Found 1-bit tristate buffer for signal <DTACK>.
|
|
Found 1-bit tristate buffer for signal <INT2_OUT>.
|
|
Found 1-bit tristate buffer for signal <INT6_OUT>.
|
|
Found 14-bit register for signal <A_LAN_OUT>.
|
|
Found 1-bit xor2 for signal <AMIGA_CLK$xor0000> created at line 152.
|
|
Found 1-bit register for signal <AS_D>.
|
|
Found 2-bit register for signal <AUTO_CONFIG_DONE>.
|
|
Found 2-bit register for signal <AUTO_CONFIG_DONE_CYCLE>.
|
|
Found 2-bit subtractor for signal <AUTO_CONFIG_DONE_CYCLE$addsub0000> created at line 466.
|
|
Found 1-bit register for signal <autoconfig>.
|
|
Found 2-bit comparator greater for signal <autoconfig$cmp_gt0000> created at line 232.
|
|
Found 1-bit register for signal <cp>.
|
|
Found 8-bit comparator equal for signal <cp$cmp_eq0000> created at line 241.
|
|
Found 8-bit register for signal <CP_BASEADR>.
|
|
Found 1-bit register for signal <CP_RD_S>.
|
|
Found 1-bit register for signal <CP_WE_QUIRK>.
|
|
Found 1-bit register for signal <CP_WE_S>.
|
|
Found 16-bit register for signal <D_IN>.
|
|
Found 16-bit register for signal <D_OUT>.
|
|
Found 4-bit register for signal <Dout1>.
|
|
Found 3-bit comparator greater for signal <Dout1$cmp_gt0000> created at line 393.
|
|
Found 1-bit register for signal <ide>.
|
|
Found 8-bit comparator equal for signal <ide$cmp_eq0000> created at line 244.
|
|
Found 8-bit register for signal <IDE_BASEADR>.
|
|
Found 1-bit register for signal <IDE_ENABLE>.
|
|
Found 1-bit register for signal <IDE_R_S>.
|
|
Found 1-bit register for signal <IDE_W_S>.
|
|
Found 1-bit register for signal <lan_adr>.
|
|
Found 1-bit register for signal <lan_adr_sw>.
|
|
Found 8-bit comparator equal for signal <lan_adr_sw$cmp_eq0000> created at line 235.
|
|
Found 2-bit comparator less for signal <lan_adr_sw$cmp_lt0000> created at line 236.
|
|
Found 8-bit register for signal <LAN_BASEADR>.
|
|
Found 1-bit register for signal <LAN_CS_RST>.
|
|
Found 1-bit register for signal <LAN_INT_ENABLE>.
|
|
Found 1-bit register for signal <LAN_IRQ_D0>.
|
|
Found 1-bit register for signal <LAN_IRQ_OUT>.
|
|
Found 1-bit register for signal <LAN_RD_S>.
|
|
Found 1-bit register for signal <LAN_WR_RST>.
|
|
Found 1-bit register for signal <LAN_WRH_S>.
|
|
Found 1-bit register for signal <LAN_WRL_S>.
|
|
Found 1-bit register for signal <ROM_OE_S>.
|
|
Found 1-bit register for signal <SET_FREQUENCY>.
|
|
Found 3-bit register for signal <SHUT_UP>.
|
|
Summary:
|
|
inferred 1 Finite State Machine(s).
|
|
inferred 24 D-type flip-flop(s).
|
|
inferred 1 Adder/Subtractor(s).
|
|
inferred 6 Comparator(s).
|
|
inferred 1 Xor(s).
|
|
inferred 38 Tristate(s).
|
|
Unit <LAN_IDE_CP> synthesized.
|
|
|
|
|
|
=========================================================================
|
|
HDL Synthesis Report
|
|
|
|
Macro Statistics
|
|
# Adders/Subtractors : 1
|
|
2-bit subtractor : 1
|
|
# Registers : 34
|
|
1-bit register : 25
|
|
14-bit register : 1
|
|
16-bit register : 2
|
|
2-bit register : 2
|
|
4-bit register : 1
|
|
8-bit register : 3
|
|
# Comparators : 6
|
|
2-bit comparator greater : 1
|
|
2-bit comparator less : 1
|
|
3-bit comparator greater : 1
|
|
8-bit comparator equal : 3
|
|
# Tristates : 8
|
|
1-bit tristate buffer : 6
|
|
16-bit tristate buffer : 2
|
|
# Xors : 1
|
|
1-bit xor2 : 1
|
|
|
|
=========================================================================
|
|
|
|
=========================================================================
|
|
* Advanced HDL Synthesis *
|
|
=========================================================================
|
|
|
|
Analyzing FSM <FSM_0> for best encoding.
|
|
Optimizing FSM <LAN_RST_SM/FSM> on signal <LAN_RST_SM[1:8]> with one-hot encoding.
|
|
------------------------
|
|
State | Encoding
|
|
------------------------
|
|
nop | 00000001
|
|
wait0 | 00000010
|
|
clr | 00000100
|
|
clr_commit | 00001000
|
|
wait1 | 00010000
|
|
set | 00100000
|
|
set_commit | 01000000
|
|
done | 10000000
|
|
------------------------
|
|
WARNING:Xst:1426 - The value init of the FF/Latch 0 hinder the constant cleaning in the block SET_FREQUENCY.
|
|
You should achieve better results by setting this init to 0.
|
|
|
|
=========================================================================
|
|
Advanced HDL Synthesis Report
|
|
|
|
Macro Statistics
|
|
# FSMs : 1
|
|
# Adders/Subtractors : 1
|
|
2-bit subtractor : 1
|
|
# Registers : 24
|
|
Flip-Flops : 24
|
|
# Comparators : 3
|
|
8-bit comparator equal : 3
|
|
|
|
=========================================================================
|
|
|
|
=========================================================================
|
|
* Low Level Synthesis *
|
|
=========================================================================
|
|
WARNING:Xst:1426 - The value init of the FF/Latch SET_FREQUENCY hinder the constant cleaning in the block LAN_IDE_CP.
|
|
You should achieve better results by setting this init to 0.
|
|
|
|
Optimizing unit <LAN_IDE_CP> ...
|
|
implementation constraint: INIT=s : SET_FREQUENCY
|
|
implementation constraint: INIT=r : LAN_RST_SM_FSM_FFd1
|
|
implementation constraint: INIT=r : LAN_RST_SM_FSM_FFd2
|
|
implementation constraint: INIT=r : LAN_RST_SM_FSM_FFd3
|
|
implementation constraint: INIT=r : LAN_RST_SM_FSM_FFd4
|
|
implementation constraint: INIT=r : LAN_RST_SM_FSM_FFd5
|
|
implementation constraint: INIT=r : LAN_RST_SM_FSM_FFd6
|
|
implementation constraint: INIT=r : LAN_RST_SM_FSM_FFd7
|
|
implementation constraint: INIT=s : LAN_RST_SM_FSM_FFd8
|
|
|
|
=========================================================================
|
|
* Partition Report *
|
|
=========================================================================
|
|
|
|
Partition Implementation Status
|
|
-------------------------------
|
|
|
|
No Partitions were found in this design.
|
|
|
|
-------------------------------
|
|
|
|
=========================================================================
|
|
* Final Report *
|
|
=========================================================================
|
|
Final Results
|
|
RTL Top Level Output File Name : LAN_IDE_CP.ngr
|
|
Top Level Output File Name : LAN_IDE_CP
|
|
Output Format : NGC
|
|
Optimization Goal : Speed
|
|
Keep Hierarchy : Yes
|
|
Target Technology : XC9500XL CPLDs
|
|
Macro Preserve : YES
|
|
XOR Preserve : YES
|
|
Clock Enable : YES
|
|
wysiwyg : NO
|
|
|
|
Design Statistics
|
|
# IOs : 113
|
|
|
|
Cell Usage :
|
|
# BELS : 884
|
|
# AND2 : 255
|
|
# AND3 : 44
|
|
# AND4 : 6
|
|
# AND8 : 3
|
|
# GND : 1
|
|
# INV : 348
|
|
# OR2 : 166
|
|
# OR3 : 32
|
|
# OR4 : 3
|
|
# XOR2 : 26
|
|
# FlipFlops/Latches : 111
|
|
# FD : 15
|
|
# FDC : 7
|
|
# FDCE : 33
|
|
# FDP : 18
|
|
# FDPE : 38
|
|
# IO Buffers : 106
|
|
# IBUF : 35
|
|
# IOBUFE : 32
|
|
# OBUF : 33
|
|
# OBUFE : 6
|
|
=========================================================================
|
|
|
|
|
|
Total REAL time to Xst completion: 3.00 secs
|
|
Total CPU time to Xst completion: 2.76 secs
|
|
|
|
-->
|
|
|
|
Total memory usage is 4514448 kilobytes
|
|
|
|
Number of errors : 0 ( 0 filtered)
|
|
Number of warnings : 14 ( 0 filtered)
|
|
Number of infos : 1 ( 0 filtered)
|
|
|