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to much logic!

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This commit is contained in:
MHeinrichs
2016-12-28 20:57:10 +01:00
parent 9e20fea5db
commit 53aacaf617
106 changed files with 13289 additions and 16053 deletions
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Logic/LAN_IDE/LAN_IDE.gise
+110 -2
View File
@@ -21,8 +21,116 @@
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="LAN_IDE.xise"/>
<files xmlns="http://www.xilinx.com/XMLSchema"/>
<files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="LAN_IDE_CP.bld"/>
<file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="LAN_IDE_CP.cmd_log"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_GYD" xil_pn:name="LAN_IDE_CP.gyd"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_JEDEC" xil_pn:name="LAN_IDE_CP.jed"/>
<file xil_pn:fileType="FILE_LFP" xil_pn:name="LAN_IDE_CP.lfp"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="LAN_IDE_CP.lso"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MFD" xil_pn:name="LAN_IDE_CP.mfd"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGA" xil_pn:name="LAN_IDE_CP.nga"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="LAN_IDE_CP.ngc"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGD" xil_pn:name="LAN_IDE_CP.ngd"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="LAN_IDE_CP.ngr"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PNX" xil_pn:name="LAN_IDE_CP.pnx"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="LAN_IDE_CP.prj"/>
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="LAN_IDE_CP.rpt"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="LAN_IDE_CP.stx"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="LAN_IDE_CP.syr"/>
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="LAN_IDE_CP.tim"/>
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="LAN_IDE_CP.tspec"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_VM6" xil_pn:name="LAN_IDE_CP.vm6"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="LAN_IDE_CP.xst"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="LAN_IDE_CP_envsettings.html"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="LAN_IDE_CP_html"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="LAN_IDE_CP_ngdbuild.xrpt"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="LAN_IDE_CP_summary.html"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="LAN_IDE_CP_vhdl.prj"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="LAN_IDE_CP_xst.xrpt"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="_ngo"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/xst.xmsgs"/>
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="webtalk_pn.xml"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xlnx_auto_0_xdb"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xst"/>
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema"/>
<transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1481823627" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1481823627">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1481823627" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="5081391373936803697" xil_pn:start_ts="1481823627">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1482093889" xil_pn:in_ck="-2520376148396271922" xil_pn:name="TRANEXT_xstsynthesize_xc9500xl" xil_pn:prop_ck="-3821115760053952169" xil_pn:start_ts="1482093879">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="LAN_IDE_CP.lso"/>
<outfile xil_pn:name="LAN_IDE_CP.ngc"/>
<outfile xil_pn:name="LAN_IDE_CP.ngr"/>
<outfile xil_pn:name="LAN_IDE_CP.prj"/>
<outfile xil_pn:name="LAN_IDE_CP.stx"/>
<outfile xil_pn:name="LAN_IDE_CP.syr"/>
<outfile xil_pn:name="LAN_IDE_CP.xst"/>
<outfile xil_pn:name="LAN_IDE_CP_vhdl.prj"/>
<outfile xil_pn:name="LAN_IDE_CP_xst.xrpt"/>
<outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/>
</transform>
<transform xil_pn:end_ts="1481833317" xil_pn:in_ck="176569500195729039" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-8537920303570934858" xil_pn:start_ts="1481833317">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1482093897" xil_pn:in_ck="-8547647177936735053" xil_pn:name="TRAN_ngdbuild" xil_pn:prop_ck="-1996509353111835880" xil_pn:start_ts="1482093889">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="LAN_IDE_CP.bld"/>
<outfile xil_pn:name="LAN_IDE_CP.ngd"/>
<outfile xil_pn:name="LAN_IDE_CP_ngdbuild.xrpt"/>
<outfile xil_pn:name="_ngo"/>
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
</transform>
<transform xil_pn:end_ts="1482093915" xil_pn:in_ck="-2520376148396280667" xil_pn:name="TRANEXT_vm6File_xc9500xl" xil_pn:prop_ck="-2093792004516735551" xil_pn:start_ts="1482093897">
<status xil_pn:value="FailedRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="LAN_IDE_CP.rpt"/>
<outfile xil_pn:name="LAN_IDE_CP.tim"/>
<outfile xil_pn:name="LAN_IDE_CP.tspec"/>
<outfile xil_pn:name="LAN_IDE_CP_html"/>
</transform>
<transform xil_pn:end_ts="1482076402" xil_pn:in_ck="-2520376148396271803" xil_pn:name="TRANEXT_crtProg_xc9500" xil_pn:prop_ck="-6294026017969277533" xil_pn:start_ts="1482076400">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="LAN_IDE_CP.jed"/>
</transform>
<transform xil_pn:end_ts="1481825870" xil_pn:in_ck="-2520376148396271803" xil_pn:name="TRAN_timRpt" xil_pn:prop_ck="111903974446" xil_pn:start_ts="1481825868">
<status xil_pn:value="AbortedRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="InputChanged"/>
</transform>
<transform xil_pn:end_ts="1481823675" xil_pn:in_ck="-8497105071423008236" xil_pn:name="TRAN_createTimingConstraints" xil_pn:start_ts="1481823675">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="InputChanged"/>
</transform>
</transforms>
</generated_project>
Logic/LAN_IDE/LAN_IDE.xise
+5 -5
View File
@@ -91,7 +91,7 @@
<property xil_pn:name="Keep Hierarchy CPLD" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Strategy" xil_pn:value="area;C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/area.xds" xil_pn:valueState="non-default"/>
<property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
@@ -106,8 +106,8 @@
<property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="4" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Effort" xil_pn:value="High" xil_pn:valueState="non-default" xil_pn:x_locked="true"/>
<property xil_pn:name="Optimization Goal" xil_pn:value="Area" xil_pn:valueState="non-default" xil_pn:x_locked="true"/>
<property xil_pn:name="Other CPLD Fitter Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Fit" xil_pn:value="" xil_pn:valueState="default"/>
@@ -150,7 +150,7 @@
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="Yes" xil_pn:valueState="non-default" xil_pn:x_locked="true"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
@@ -194,7 +194,7 @@
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Timing Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="C:/Xilinx/14.6/ISE_DS/ISE/data/default.xds" xil_pn:valueState="non-default"/>
<property xil_pn:name="VCCIO Reference Voltage" xil_pn:value="LVTTL" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
Logic/LAN_IDE/LAN_IDE_CP.bld
+1 -1
View File
@@ -30,7 +30,7 @@ NGDBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 1
Total memory usage is 190196 kilobytes
Total memory usage is 190216 kilobytes
Writing NGD file "LAN_IDE_CP.ngd" ...
Total REAL time to NGDBUILD completion: 5 sec
Logic/LAN_IDE/LAN_IDE_CP.cmd_log
+40
View File
@@ -1,3 +1,43 @@
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95144xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95144xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
XSLTProcess LAN_IDE_CP_build.xml
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95144xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95144xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
XSLTProcess LAN_IDE_CP_build.xml
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95144xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95144xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95144xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95144xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95144xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95144xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95144xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95144xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95144xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95144xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95144xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95144xl-10-TQ144 -ofmt vhdl -optimize speed -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95144xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95144xl-10-TQ144 -ofmt vhdl -optimize speed -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95144xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95144xl-10-TQ144 -ofmt vhdl -optimize speed -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
tsim -intstyle ise LAN_IDE_CP LAN_IDE_CP.nga
hprep6 -s IEEE1149 -n LAN_IDE_CP -i LAN_IDE_CP
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95144xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95144xl-10-TQ144 -ofmt vhdl -optimize speed -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
xst -intstyle ise -ifn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.xst" -ofn "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.syr"
ngdbuild -intstyle ise -dd _ngo -uc pinlist.ucf -p xc95144xl-TQ144-10 LAN_IDE_CP.ngc LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95144xl-10-TQ144 -ofmt vhdl -optimize speed -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95144xl-10-TQ144 -ofmt vhdl -optimize speed -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
cpldfit -intstyle ise -p xc95144xl-10-TQ144 -ofmt vhdl -optimize speed -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper LAN_IDE_CP.ngd
Logic/LAN_IDE/LAN_IDE_CP.gyd
+47 -47
View File
@@ -3,18 +3,19 @@ Pin Freeze File: version P.68d
95144XL144TQ XC95144XL-10-TQ144
AS S:PIN80
AUTOBOOT_OFF S:PIN75
A<12> S:PIN61
A<13> S:PIN64
A<14> S:PIN66
A<16> S:PIN97
A<17> S:PIN95
A<18> S:PIN94
A<19> S:PIN92
A<1> S:PIN57
A<20> S:PIN91
A<21> S:PIN88
A<22> S:PIN87
A<23> S:PIN86
A<1> S:PIN57
A<11> S:PIN60
A<12> S:PIN61
A<13> S:PIN64
A<14> S:PIN66
A<2> S:PIN54
A<3> S:PIN52
A<4> S:PIN50
@@ -22,20 +23,20 @@ A<5> S:PIN49
A<6> S:PIN51
A<7> S:PIN53
A<8> S:PIN56
A<9> S:PIN58
A<10> S:PIN59
BERR S:PIN98
C1 S:PIN103
C3 S:PIN102
CFIN S:PIN104
CP_IRQ S:PIN31
A<9> S:PIN58
A<10> S:PIN59
A<11> S:PIN60
LAN_INT S:PIN111
LDS S:PIN82
RESET S:PIN143
RW S:PIN83
UDS S:PIN81
A_LAN<0> S:PIN4
IDE_A<2> S:PIN25
A_LAN<10> S:PIN138
A_LAN<11> S:PIN139
A_LAN<12> S:PIN137
@@ -47,10 +48,11 @@ A_LAN<4> S:PIN9
A_LAN<5> S:PIN7
A_LAN<6> S:PIN11
A_LAN<7> S:PIN10
IDE_A<0> S:PIN24
A_LAN<8> S:PIN140
IDE_A<1> S:PIN26
A_LAN<9> S:PIN142
CFOUT S:PIN105
CP_CS S:PIN34
CP_RD S:PIN71
CP_WE S:PIN70
DQ<0> S:PIN118
@@ -85,9 +87,6 @@ D<6> S:PIN14
D<7> S:PIN16
D<8> S:PIN19
D<9> S:PIN40
IDE_A<0> S:PIN24
IDE_A<1> S:PIN26
IDE_A<2> S:PIN25
IDE_CS<0> S:PIN22
IDE_CS<1> S:PIN23
IDE_R S:PIN27
@@ -107,49 +106,50 @@ INT_OUT S:PIN32
DTACK S:PIN85
ROM_OE S:PIN35
SLAVE S:PIN106
CP_CS S:PIN34
;The remaining section of the .gyd file is for documentation purposes only.
;It shows where your internal equations were placed in the last successful fit.
PARTITION FB1_1 IDE_CS_1_OBUF D_7_IOBUFE D_1_IOBUFE IDE_A_2_OBUF$BUF0
D_8_IOBUFE D_5_IOBUFE IDE_BASEADR<4> D_4_IOBUFE
IDE_CS_0_OBUF CP_BASEADR<7> IDE_A_0_OBUF$BUF0 IDE_A_1_OBUF$BUF0
CP_BASEADR<6> IDE_R_S IDE_W_S ROM_OE_S
CP_BASEADR<5> CP_BASEADR<4>
PARTITION FB2_1 A_LAN_9_OBUF CP_BASEADR<3> CP_BASEADR<2> A_LAN_0_OBUF
D_0_IOBUFE A_LAN_1_OBUF CP_BASEADR<1> A_LAN_3_OBUF
A_LAN_2_OBUF A_LAN_5_OBUF A_LAN_4_OBUF A_LAN_7_OBUF
ROM_B_0_OBUF$BUF4 A_LAN_6_OBUF ROM_B_0_OBUF$BUF3 D_6_IOBUFE
D_3_IOBUFE CP_BASEADR<0>
PARTITION FB1_1 IDE_CS_1_OBUF D_7_IOBUFE D_1_IOBUFE A_LAN_10_OBUF$BUF0
D_8_IOBUFE D_5_IOBUFE IDE_ENABLE D_4_IOBUFE
IDE_CS_0_OBUF Dout1<0> A_LAN_8_OBUF$BUF0 A_LAN_9_OBUF$BUF0
PARTITION FB1_14 IDE_R_S IDE_W_S ROM_OE_S EXP11_
Dout1<1>
PARTITION FB2_1 A_LAN_9_OBUF$BUF1 CP_BASEADR<5> CP_BASEADR<4> A_LAN_0_OBUF$BUF0
D_0_IOBUFE A_LAN_1_OBUF$BUF0 CP_BASEADR<3> A_LAN_3_OBUF$BUF0
A_LAN_2_OBUF$BUF0 A_LAN_5_OBUF$BUF0 A_LAN_4_OBUF$BUF0 A_LAN_7_OBUF$BUF0
ROM_B_0_OBUF$BUF4 A_LAN_6_OBUF$BUF0 ROM_B_0_OBUF$BUF3 D_6_IOBUFE
D_3_IOBUFE CP_BASEADR<2>
PARTITION FB3_1 D_2_IOBUFE ROM_B_0_OBUF$BUF5 D_10_IOBUFE D_12_IOBUFE
SLAVE_OBUF__$INT CP_CS_OBUF D_14_IOBUFE $OpTx$INV$99__$INT
AUTO_CONFIG_DONE<0> _10_ D_14_IOBUFE LAN_BASEADR<0>
D_9_IOBUFE D_15_IOBUFE D_11_IOBUFE D_13_IOBUFE
IDE_BASEADR<6> IDE_BASEADR<5> IDE_BASEADR<3> IDE_BASEADR<2>
IDE_BASEADR<1> IDE_BASEADR<0>
PARTITION FB4_1 DQ_0_IOBUFE$BUF0 DQ_6_IOBUFE$BUF0 LAN_CFG_2_OBUF SHUT_UP<2>
DQ_8_IOBUFE$BUF0 DQ_10_IOBUFE$BUF0 LAN_BASEADR<6> DQ_12_IOBUFE$BUF0
CP_BASEADR<1> CP_BASEADR<0> Dout1<3> SLAVE_OBUF__$INT
EXP12_ Dout1<2>
PARTITION FB4_1 DQ_0_IOBUFE$BUF0 DQ_6_IOBUFE$BUF0 LAN_CFG_2_OBUF LAN_BASEADR<2>
DQ_8_IOBUFE$BUF0 DQ_10_IOBUFE$BUF0 CP_BASEADR<7> DQ_12_IOBUFE$BUF0
DQ_14_IOBUFE$BUF0 LAN_CFG_2_OBUF$BUF0 LAN_WRH_OBUF LAN_RD_OBUF
A_LAN_12_OBUF A_LAN_13_OBUF A_LAN_10_OBUF A_LAN_11_OBUF
A_LAN_8_OBUF IDE_BASEADR<7>
PARTITION FB5_1 SHUT_UP<1> SHUT_UP<0> AUTO_CONFIG_DONE_CYCLE<2> AUTO_CONFIG_DONE_CYCLE<1>
AUTO_CONFIG_DONE_CYCLE<0> $OpTx$FX_DC$122 $OpTx$FX_DC$118 $OpTx$$OpTx$FX_DC$121_INV$1021
$OpTx$$OpTx$FX_DC$115_INV$1019 ROM_B_0_OBUF$BUF0 LAN_BASEADR<4> $OpTx$INV$98
CP_WE_OBUF $OpTx$FX_DC$123 Dout1<2> Dout1<1>
ROM_B_0_OBUF Dout1<0>
PARTITION FB6_1 LAN_BASEADR<7> SLAVE_OBUF LAN_BASEADR<5> LAN_BASEADR<3>
ROM_B_0_OBUF$BUF2 DQ_15_IOBUFE$BUF0 LAN_BASEADR<2> DQ_13_IOBUFE$BUF0
A_LAN_12_OBUF$BUF0 A_LAN_13_OBUF$BUF0 A_LAN_10_OBUF$BUF1 A_LAN_11_OBUF$BUF0
A_LAN_8_OBUF$BUF1 CP_BASEADR<6>
PARTITION FB5_1 lan/lan_RSTF__$INT LAN_INT_ENABLE ROM_B_0_OBUF$BUF5/ROM_B_0_OBUF$BUF5_TRST CP_BASEADR<3>/CP_BASEADR<3>_CLKF
CP_BASEADR<2>/CP_BASEADR<2>_CLKF CP_BASEADR<1>/CP_BASEADR<1>_CLKF CP_BASEADR<0>/CP_BASEADR<0>_CLKF AUTO_CONFIG_DONE_CYCLE<1>/AUTO_CONFIG_DONE_CYCLE<1>_CLKF
AUTO_CONFIG_DONE_CYCLE<0>/AUTO_CONFIG_DONE_CYCLE<0>_CLKF ROM_B_0_OBUF$BUF0 AUTO_CONFIG_DONE<2> SHUT_UP<1>
CP_WE_OBUF SHUT_UP<0> AUTO_CONFIG_DONE_CYCLE<1> AUTO_CONFIG_DONE_CYCLE<0>
ROM_B_0_OBUF autoconfig
PARTITION FB6_1 LAN_BASEADR<7> SLAVE_OBUF LAN_BASEADR<6> LAN_BASEADR<5>
ROM_B_0_OBUF$BUF2 DQ_15_IOBUFE$BUF0 LAN_BASEADR<4> DQ_13_IOBUFE$BUF0
DQ_9_IOBUFE$BUF0 DQ_11_IOBUFE$BUF0 DQ_3_IOBUFE$BUF0 DQ_2_IOBUFE$BUF0
LAN_BASEADR<1> DQ_5_IOBUFE$BUF0 DQ_4_IOBUFE$BUF0 DQ_1_IOBUFE$BUF0
DQ_7_IOBUFE$BUF0 LAN_BASEADR<0>
PARTITION FB7_1 EXP10_ CP_RD_OBUF EXP11_ ide
EXP12_ LAN_WRL_OBUF IDE_ENABLE AUTO_CONFIG_DONE<0>
AUTO_CONFIG_DONE<1> AUTO_CONFIG_DONE<2> LAN_INT_ENABLE ROM_B_0_OBUF$BUF6
$OpTx$$OpTx$FX_DC$100_INV$1016
PARTITION FB7_16 autoconfig EXP13_ cp
PARTITION FB8_1 lan EXP14_ $OpTx$$OpTx$FX_DC$117_INV$1020 $OpTx$$OpTx$FX_DC$108_INV$1018
$OpTx$$OpTx$FX_DC$106_INV$1017 SHUT_UP<2>/SHUT_UP<2>_CLKF ROM_B_0_OBUF$BUF5/ROM_B_0_OBUF$BUF5_TRST $OpTx$FX_DC$120
$OpTx$FX_DC$119 $OpTx$FX_DC$112 $OpTx$FX_DC$111 $OpTx$FX_DC$110
$OpTx$FX_DC$109 $OpTx$FX_DC$103 Dout1<3> ROM_B_0_OBUF$BUF1
CFOUT_OBUF EXP15_
LAN_BASEADR<3> DQ_5_IOBUFE$BUF0 DQ_4_IOBUFE$BUF0 DQ_1_IOBUFE$BUF0
DQ_7_IOBUFE$BUF0 LAN_BASEADR<1>
PARTITION FB7_1 CP_CS_BUFR.MC CP_RD_OBUF IDE_ENABLE/IDE_ENABLE_CLKF Dout1<3>/Dout1<3>_CLKF
Dout1<2>/Dout1<2>_CLKF LAN_WRL_OBUF Dout1<1>/Dout1<1>_CLKF Dout1<0>/Dout1<0>_CLKF
CP_BASEADR<7>/CP_BASEADR<7>_CLKF CP_BASEADR<6>/CP_BASEADR<6>_CLKF CP_BASEADR<5>/CP_BASEADR<5>_CLKF ROM_B_0_OBUF$BUF6
EXP13_ lan EXP14_ CP_BASEADR<4>/CP_BASEADR<4>_CLKF
IDE_R_S/IDE_R_S_CLKF EXP15_
PARTITION FB8_4 lan/lan_CLKF SHUT_UP<1>/SHUT_UP<1>_CLKF SHUT_UP<0>/SHUT_UP<0>_CLKF ROM_OE_S/ROM_OE_S_CLKF
LAN_BASEADR<7>/LAN_BASEADR<7>_CLKF LAN_BASEADR<6>/LAN_BASEADR<6>_CLKF LAN_BASEADR<5>/LAN_BASEADR<5>_CLKF LAN_BASEADR<4>/LAN_BASEADR<4>_CLKF
LAN_BASEADR<3>/LAN_BASEADR<3>_CLKF LAN_BASEADR<2>/LAN_BASEADR<2>_CLKF LAN_BASEADR<1>/LAN_BASEADR<1>_CLKF LAN_BASEADR<0>/LAN_BASEADR<0>_CLKF
ROM_B_0_OBUF$BUF1 CFOUT_OBUF IDE_W_S/IDE_W_S_CLKF
Logic/LAN_IDE/LAN_IDE_CP.jed
+1038 -1038
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File diff suppressed because it is too large Load Diff
Logic/LAN_IDE/LAN_IDE_CP.mfd
+1385 -1410
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File diff suppressed because it is too large Load Diff
Logic/LAN_IDE/LAN_IDE_CP.nga
+1 -1
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Logic/LAN_IDE/LAN_IDE_CP.ngc
+1 -1
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Logic/LAN_IDE/LAN_IDE_CP.ngd
+1 -1
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Logic/LAN_IDE/LAN_IDE_CP.ngr
+1 -1
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File diff suppressed because one or more lines are too long
Logic/LAN_IDE/LAN_IDE_CP.pad
+1 -1
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@@ -1,7 +1,7 @@
Release 8.1i - Fit P.68d
Copyright(c) 1995-2003 Xilinx Inc. All rights reserved
12-28-2016 0:50AM
12-28-2016 8:53PM
NOTE: This file is designed to be imported into a spreadsheet program
such as Microsoft Excel for viewing, printing and sorting. The pipe '|'
Logic/LAN_IDE/LAN_IDE_CP.pnx
+1 -1
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File diff suppressed because one or more lines are too long
Logic/LAN_IDE/LAN_IDE_CP.rpt
+1029 -1424
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File diff suppressed because it is too large Load Diff
Logic/LAN_IDE/LAN_IDE_CP.syr
+33 -50
View File
@@ -4,13 +4,13 @@ Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.12 secs
Total CPU time to Xst completion: 0.11 secs
--> Parameter xsthdpdir set to xst
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.12 secs
Total CPU time to Xst completion: 0.11 secs
--> Reading design: LAN_IDE_CP.prj
@@ -44,7 +44,7 @@ Target Device : XC9500XL CPLDs
Top Module Name : LAN_IDE_CP
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
Safe Implementation : No
Safe Implementation : Yes
Mux Extraction : Yes
Resource Sharing : YES
@@ -55,8 +55,8 @@ XOR Preserve : YES
Equivalent register Removal : YES
---- General Options
Optimization Goal : Speed
Optimization Effort : 1
Optimization Goal : Area
Optimization Effort : 2
Keep Hierarchy : Yes
Netlist Hierarchy : As_Optimized
RTL Output : Yes
@@ -76,22 +76,19 @@ wysiwyg : NO
* HDL Compilation *
=========================================================================
Compiling vhdl file "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.vhd" in Library work.
Entity <LAN_IDE_CP> compiled.
Entity <LAN_IDE_CP> (Architecture <Behavioral>) compiled.
Entity <lan_ide_cp> compiled.
Entity <lan_ide_cp> (Architecture <behavioral>) compiled.
=========================================================================
* Design Hierarchy Analysis *
=========================================================================
Analyzing hierarchy for entity <LAN_IDE_CP> in library <work> (architecture <Behavioral>).
Analyzing hierarchy for entity <LAN_IDE_CP> in library <work> (architecture <behavioral>).
=========================================================================
* HDL Analysis *
=========================================================================
Analyzing Entity <LAN_IDE_CP> in library <work> (Architecture <Behavioral>).
WARNING:Xst:819 - "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.vhd" line 114: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<AS>
WARNING:Xst:795 - "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.vhd" line 156: Size of operands are different : result is <false>.
Analyzing Entity <LAN_IDE_CP> in library <work> (Architecture <behavioral>).
Entity <LAN_IDE_CP> analyzed. Unit <LAN_IDE_CP> generated.
@@ -120,28 +117,28 @@ WARNING:Xst:1780 - Signal <AS_D> is never used or assigned. This unconnected sig
Found 1-bit tristate buffer for signal <OWN>.
Found 1-bit tristate buffer for signal <DTACK>.
Found 1-bit tristate buffer for signal <INT_OUT>.
Found 1-bit xor2 for signal <AMIGA_CLK$xor0000> created at line 110.
Found 1-bit xor2 for signal <AMIGA_CLK$xor0000> created at line 111.
Found 3-bit register for signal <AUTO_CONFIG_DONE>.
Found 3-bit register for signal <AUTO_CONFIG_DONE_CYCLE>.
Found 1-bit register for signal <autoconfig>.
Found 1-bit register for signal <cp>.
Found 8-bit comparator not equal for signal <cp$cmp_ne0000> created at line 135.
Found 8-bit comparator equal for signal <cp$cmp_eq0000> created at line 141.
Found 8-bit register for signal <CP_BASEADR>.
Found 4-bit register for signal <Dout1>.
Found 1-bit register for signal <ide>.
Found 8-bit comparator not equal for signal <ide$cmp_ne0000> created at line 129.
Found 8-bit comparator equal for signal <ide$cmp_eq0000> created at line 135.
Found 8-bit register for signal <IDE_BASEADR>.
Found 1-bit register for signal <IDE_ENABLE>.
Found 1-bit register for signal <IDE_R_S>.
Found 1-bit register for signal <IDE_W_S>.
Found 1-bit register for signal <lan>.
Found 8-bit comparator not equal for signal <lan$cmp_ne0000> created at line 123.
Found 8-bit comparator equal for signal <lan$cmp_eq0000> created at line 129.
Found 8-bit register for signal <LAN_BASEADR>.
Found 1-bit register for signal <LAN_INT_ENABLE>.
Found 1-bit register for signal <ROM_OE_S>.
Found 3-bit register for signal <SHUT_UP>.
Summary:
inferred 1 D-type flip-flop(s).
inferred 5 D-type flip-flop(s).
inferred 3 Comparator(s).
inferred 1 Xor(s).
inferred 35 Tristate(s).
@@ -158,7 +155,7 @@ Macro Statistics
4-bit register : 1
8-bit register : 3
# Comparators : 3
8-bit comparator not equal : 3
8-bit comparator equal : 3
# Tristates : 5
1-bit tristate buffer : 3
16-bit tristate buffer : 2
@@ -171,34 +168,23 @@ Macro Statistics
* Advanced HDL Synthesis *
=========================================================================
WARNING:Xst:1426 - The value init of the FF/Latch 0 hinder the constant cleaning in the block LAN_INT_ENABLE.
You should achieve better results by setting this init to 0.
=========================================================================
Advanced HDL Synthesis Report
Macro Statistics
# Registers : 1
Flip-Flops : 1
# Registers : 5
Flip-Flops : 5
# Comparators : 3
8-bit comparator equal : 3
=========================================================================
=========================================================================
* Low Level Synthesis *
=========================================================================
WARNING:Xst:1426 - The value init of the FF/Latch LAN_INT_ENABLE hinder the constant cleaning in the block LAN_IDE_CP.
You should achieve better results by setting this init to 0.
Optimizing unit <LAN_IDE_CP> ...
implementation constraint: INIT=r : IDE_ENABLE
implementation constraint: INIT=r : ide
implementation constraint: INIT=r : autoconfig
implementation constraint: INIT=s : IDE_R_S
implementation constraint: INIT=s : IDE_W_S
implementation constraint: INIT=r : cp
implementation constraint: INIT=s : ROM_OE_S
implementation constraint: INIT=r : lan
implementation constraint: INIT=s : LAN_INT_ENABLE
=========================================================================
* Partition Report *
@@ -218,7 +204,7 @@ Final Results
RTL Top Level Output File Name : LAN_IDE_CP.ngr
Top Level Output File Name : LAN_IDE_CP
Output Format : NGC
Optimization Goal : Speed
Optimization Goal : Area
Keep Hierarchy : Yes
Target Technology : XC9500XL CPLDs
Macro Preserve : YES
@@ -230,23 +216,20 @@ Design Statistics
# IOs : 116
Cell Usage :
# BELS : 537
# AND2 : 132
# AND3 : 22
# AND4 : 11
# AND5 : 2
# BELS : 373
# AND2 : 83
# AND3 : 23
# GND : 1
# INV : 225
# OR2 : 106
# OR3 : 15
# INV : 148
# OR2 : 87
# OR3 : 2
# OR4 : 3
# OR5 : 3
# VCC : 1
# XOR2 : 16
# XOR2 : 25
# FlipFlops/Latches : 46
# FD : 7
# FDC : 3
# FDCE : 36
# FD : 3
# FDC : 8
# FDCE : 35
# IO Buffers : 106
# IBUF : 34
# IOBUFE : 32
@@ -256,13 +239,13 @@ Cell Usage :
Total REAL time to Xst completion: 8.00 secs
Total CPU time to Xst completion: 8.15 secs
Total CPU time to Xst completion: 8.07 secs
-->
Total memory usage is 290008 kilobytes
Total memory usage is 290060 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 16 ( 0 filtered)
Number of warnings : 12 ( 0 filtered)
Number of infos : 0 ( 0 filtered)
Logic/LAN_IDE/LAN_IDE_CP.vhd
+54 -57
View File
@@ -78,10 +78,10 @@ end LAN_IDE_CP;
architecture Behavioral of LAN_IDE_CP is
SIGNAL ide: STD_LOGIC:= '0';
SIGNAL autoconfig: STD_LOGIC:= '0';
SIGNAL lan: STD_LOGIC:= '0';
SIGNAL cp: STD_LOGIC:= '0';
SIGNAL ide: STD_LOGIC;
SIGNAL autoconfig: STD_LOGIC;
SIGNAL lan: STD_LOGIC;
SIGNAL cp: STD_LOGIC;
signal Dout1:STD_LOGIC_VECTOR(3 downto 0);
signal AUTO_CONFIG_DONE:STD_LOGIC_VECTOR(2 downto 0);
signal AUTO_CONFIG_DONE_CYCLE:STD_LOGIC_VECTOR(2 downto 0);
@@ -89,14 +89,15 @@ architecture Behavioral of LAN_IDE_CP is
signal IDE_BASEADR:STD_LOGIC_VECTOR(7 downto 0);
signal LAN_BASEADR:STD_LOGIC_VECTOR(7 downto 0);
signal CP_BASEADR:STD_LOGIC_VECTOR(7 downto 0);
signal IDE_ENABLE:STD_LOGIC:= '0';
signal ROM_OE_S:STD_LOGIC:= '1';
signal IDE_R_S:STD_LOGIC:= '1';
signal IDE_W_S:STD_LOGIC:= '1';
signal DTACK_S:STD_LOGIC:= '1';
signal AS_D: std_logic:= '1';
signal AMIGA_CLK: std_logic:= '1';
signal LAN_INT_ENABLE: std_logic:= '1';
signal IDE_ENABLE:STD_LOGIC;
signal ROM_OE_S:STD_LOGIC;
signal IDE_R_S:STD_LOGIC;
signal IDE_W_S:STD_LOGIC;
signal DTACK_S:STD_LOGIC;
signal AS_D: std_logic;
signal AMIGA_CLK: std_logic;
signal LAN_INT_ENABLE: std_logic;
signal DECODE_RESET: std_logic;
Function to_std_logic(X: in Boolean) return Std_Logic is
variable ret : std_logic;
@@ -108,56 +109,50 @@ architecture Behavioral of LAN_IDE_CP is
begin
AMIGA_CLK <= not (C1 xor C3);
DECODE_RESET <= BERR and reset;
ADDRESS_DECODE: process(AMIGA_CLK)
ADDRESS_DECODE: process(DECODE_RESET,AMIGA_CLK)
begin
if(falling_edge(AS))then
if(BERR='1') then
if(A(23 downto 16) = x"E8" and not(AUTO_CONFIG_DONE ="111") and CFIN='0')then
autoconfig <='1';
else
autoconfig <='0';
end if;
if(A(23 downto 16) = LAN_BASEADR and SHUT_UP(0) = '0')then
lan <='1';
else
lan <='0';
end if;
if(A(23 downto 16) = IDE_BASEADR and SHUT_UP(1) = '0')then
ide <='1';
else
ide <='0';
end if;
if(A(23 downto 16) = CP_BASEADR and SHUT_UP(2) = '0')then
cp <='1';
else
cp <='0';
end if;
if(DECODE_RESET ='0')then
autoconfig <='0';
ide <='0';
lan <='0';
cp <='0';
elsif(falling_edge(AMIGA_CLK))then
if(A(23 downto 16) = x"E8" and not(AUTO_CONFIG_DONE ="111") and CFIN='0')then
autoconfig <='1';
else
autoconfig <='0';
ide <='0';
end if;
if(A(23 downto 16) = LAN_BASEADR and SHUT_UP(0) = '0')then
lan <='1';
else
lan <='0';
cp <='0';
end if;
if(A(23 downto 16) = IDE_BASEADR and SHUT_UP(1) = '0')then
ide <='1';
else
ide <='0';
end if;
if(A(23 downto 16) = CP_BASEADR and SHUT_UP(2) = '0')then
cp <='1';
else
cp <='0';
end if;
end if;
end process ADDRESS_DECODE;
--LAN interrupt enable
lan_int_proc: process (AMIGA_CLK)
lan_int_proc: process (LAN_INT,reset)
begin
if rising_edge(AMIGA_CLK) then
if(reset ='0') then
if(reset ='0') then
LAN_INT_ENABLE <='0';
elsif(lan='1' and AS='0' and RW='0')then
if(A(15 downto 8) = x"8")then
LAN_INT_ENABLE <=D(15);
end if;
end if;
elsif rising_edge(LAN_INT) then
LAN_INT_ENABLE <='1';
end if;
end process lan_int_proc;
@@ -317,8 +312,9 @@ begin
elsif(A (6 downto 1)="100110")then
AUTO_CONFIG_DONE_CYCLE(0) <='1'; --done here
end if;
elsif(AUTO_CONFIG_DONE(1)='0')then
-- if(AUTO_CONFIG_DONE(1)='0')then
end if;
-- elsif(AUTO_CONFIG_DONE(1)='0')then
if(AUTO_CONFIG_DONE(0)='1')then
if(A (6 downto 1)="100100")then
IDE_BASEADR(7 downto 0) <= D(15 downto 8); --Base adress
SHUT_UP(1) <= '0'; --enable board
@@ -326,8 +322,9 @@ begin
elsif(A (6 downto 1)="100110")then
AUTO_CONFIG_DONE_CYCLE(1) <='1'; --done here
end if;
elsif(AUTO_CONFIG_DONE(2)='0')then
-- if(AUTO_CONFIG_DONE(1)='0')then
end if;
-- elsif(AUTO_CONFIG_DONE(2)='0')then
if(AUTO_CONFIG_DONE(1)='1')then
if(A (6 downto 1)="100100")then
CP_BASEADR(7 downto 0) <= D(15 downto 8); --Base adress
SHUT_UP(2) <= '0'; --enable board
@@ -344,15 +341,15 @@ begin
LAN_WRL <= '1' when AS='0' and RW='0' and lan='1' and LDS = '0' else '0';
LAN_WRH <= '1' when AS='0' and RW='0' and lan='1' and UDS = '0' else '0';
LAN_CS <= '1';-- when AS='0' and lan='1' else '0';
LAN_CS <= '1';
LAN_RD <= '1' when AS='0' and RW='1' and lan='1' else '0';
LAN_CFG <= "0010";
CP_WE <= '0' when AS='0' and RW='0' and cp='1' and (UDS='0' or LDS='0') else '1';
CP_RD <= '0' when AS='0' and RW='1' and cp='1' else '1';
CP_CS <= '0' when AS='0' and cp='1' else '1';
CP_CS <= cp;
A_LAN <= A(14 downto 1) when lan='1' else A(13 downto 1) &'0';
A_LAN <= A(14 downto 1);-- when lan='1' else A(13 downto 1) &'0';
--signal assignment
D <= --RAM_D when RW='1' and TRANSFER_IN_PROGRES ='1' else
DQ when RW='1' and (lan ='1' or cp = '1') and AS='0' else
Logic/LAN_IDE/LAN_IDE_CP.vm6
+6199 -6916
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Logic/LAN_IDE/LAN_IDE_CP.xml
+2 -2
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Logic/LAN_IDE/LAN_IDE_CP.xst
+3 -3
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@@ -7,8 +7,8 @@ run
-ofmt NGC
-p xc9500xl
-top LAN_IDE_CP
-opt_mode Speed
-opt_level 1
-opt_mode Area
-opt_level 2
-iuc NO
-keep_hierarchy Yes
-netlist_hierarchy As_Optimized
@@ -18,7 +18,7 @@ run
-case Maintain
-verilog2001 YES
-fsm_extract YES -fsm_encoding Auto
-safe_implementation No
-safe_implementation Yes
-mux_extract Yes
-resource_sharing YES
-iobuf YES
Logic/LAN_IDE/LAN_IDE_CP_build.xml
+5 -114
View File
@@ -1,10 +1,10 @@
<?xml version='1.0' encoding='utf-8' ?>
<!DOCTYPE document SYSTEM 'file:///c:/Xilinx/14.6/ISE_DS/ISE/chipviewer/data/xsl/buildXML.dtd'>
<!DOCTYPE document SYSTEM 'file:///C:/Xilinx/14.6/ISE_DS/ISE/chipviewer/data/xsl/buildXML.dtd'>
<document>
<design name='LAN_IDE_CP'/>
<rptdir name='LAN_IDE_CP'/>
<xilinx path='c:/Xilinx/14.6/ISE_DS/ISE;'/>
<xilinx path='C:/Xilinx/14.6/ISE_DS/ISE;'/>
<projDir path='C:\Users\Matze\Amiga\Hardwarehacks\Zorro-LAN-IDE\Logic\LAN_IDE'/>
<xslDir path='chipviewer/data/xsl'/>
<fileDir path='/chipviewer/data/html'/>
@@ -13,9 +13,6 @@
<dataFile file='genmsg.htm'/>
<dataFile file='eqns.js'/>
<dataFile file='maplogic.js'/>
<dataFile file='fbs.js'/>
<dataFile file='pins.js'/>
<dataFile file='tooltips.js'/>
<dataFile file='errors.js'/>
<dataFile file='leftnav.js'/>
<dataFile file='paths.js'/>
@@ -69,7 +66,7 @@
<output file='topnav.htm'/>
</xslFile>
<xslFile file='leftnav.xsl'>
<param name='result' value='1'/>
<param name='result' value='10'/>
<output file='leftnav.htm'/>
</xslFile>
<xslFile file='print.xsl'>
@@ -106,120 +103,14 @@
<xslFile file='inputleft.xsl'>
<output file='inputleft.htm'/>
</xslFile>
<xslFile file='printPins.xsl'>
<param name='appletOn' value='0'/>
<output file='pins.htm'/>
</xslFile>
<xslFile file='wait.xsl'>
<output file='wait.htm'/>
</xslFile>
<xslDebug file='printErrors.xsl'>
<output file='errors.htm'/>
</xslDebug>
<xslDebug file='printPins.xsl'>
<output file='pinout.htm'/>
</xslDebug>
<xslDebug file='printEqns.xsl'>
<output file='eqnout.htm'/>
</xslDebug>
<xslFile file='maplogic.xsl'>
<param name='sortType' value='0'/>
<param name='mapLog' value='1'/>
<param name='mapIn' value='0'/>
<param name='unmapLog' value='0'/>
<param name='unmapIn' value='0'/>
<param name='legendOn' value='1'/>
<param name='appletOn' value='0'/>
<output file='maplogic_00.htm'/>
<param name='sortType' value='1'/>
<param name='mapLog' value='1'/>
<param name='mapIn' value='0'/>
<param name='unmapLog' value='0'/>
<param name='unmapIn' value='0'/>
<param name='legendOn' value='1'/>
<param name='appletOn' value='0'/>
<output file='maplogic_01.htm'/>
<param name='sortType' value='2'/>
<param name='mapLog' value='1'/>
<param name='mapIn' value='0'/>
<param name='unmapLog' value='0'/>
<param name='unmapIn' value='0'/>
<param name='legendOn' value='1'/>
<param name='appletOn' value='0'/>
<output file='maplogic_02.htm'/>
<param name='sortType' value='0'/>
<param name='mapLog' value='0'/>
<param name='mapIn' value='1'/>
<param name='unmapLog' value='0'/>
<param name='unmapIn' value='0'/>
<param name='legendOn' value='1'/>
<param name='appletOn' value='0'/>
<output file='mapinput_00.htm'/>
<param name='sortType' value='1'/>
<param name='mapLog' value='0'/>
<param name='mapIn' value='1'/>
<param name='unmapLog' value='0'/>
<param name='unmapIn' value='0'/>
<param name='legendOn' value='1'/>
<param name='appletOn' value='0'/>
<output file='mapinput_01.htm'/>
<param name='sortType' value='2'/>
<param name='mapLog' value='0'/>
<param name='mapIn' value='1'/>
<param name='unmapLog' value='0'/>
<param name='unmapIn' value='0'/>
<param name='legendOn' value='1'/>
<param name='appletOn' value='0'/>
<output file='mapinput_02.htm'/>
</xslFile>
<xslFile file='fbsum.xsl'>
<param name='legendOn' value='0'/>
<output file='fbs.htm'/>
</xslFile>
<xslFile file='fbs.xsl'>
<param name='fb' value='FB1'/>
<param name='type' value='1'/>
<param name='legendOn' value='1'/>
<param name='appletOn' value='0'/>
<output file='fbs_FB1.htm'/>
<param name='fb' value='FB2'/>
<param name='type' value='3'/>
<param name='legendOn' value='1'/>
<param name='appletOn' value='0'/>
<output file='fbs_FB2.htm'/>
<param name='fb' value='FB3'/>
<param name='type' value='3'/>
<param name='legendOn' value='1'/>
<param name='appletOn' value='0'/>
<output file='fbs_FB3.htm'/>
<param name='fb' value='FB4'/>
<param name='type' value='3'/>
<param name='legendOn' value='1'/>
<param name='appletOn' value='0'/>
<output file='fbs_FB4.htm'/>
<param name='fb' value='FB5'/>
<param name='type' value='3'/>
<param name='legendOn' value='1'/>
<param name='appletOn' value='0'/>
<output file='fbs_FB5.htm'/>
<param name='fb' value='FB6'/>
<param name='type' value='3'/>
<param name='legendOn' value='1'/>
<param name='appletOn' value='0'/>
<output file='fbs_FB6.htm'/>
<param name='fb' value='FB7'/>
<param name='type' value='3'/>
<param name='legendOn' value='1'/>
<param name='appletOn' value='0'/>
<output file='fbs_FB7.htm'/>
<param name='fb' value='FB8'/>
<param name='type' value='2'/>
<param name='legendOn' value='1'/>
<param name='appletOn' value='0'/>
<output file='fbs_FB8.htm'/>
</xslFile>
</xmlFile>
<xmlFile file='c:/Xilinx/14.6/ISE_DS/ISE/chipviewer/data/xsl/pinlegend.xml'>
<xmlFile file='C:/Xilinx/14.6/ISE_DS/ISE/chipviewer/data/xsl/pinlegend.xml'>
<xslFile file='legend.xsl'>
<param name='device' value='XC95144XL-10-TQ144'/>
<param name='verOn' value='0'/>
@@ -231,7 +122,7 @@
<output file='pinlegendV.htm'/>
</xslFile>
</xmlFile>
<xmlFile file='c:/Xilinx/14.6/ISE_DS/ISE/chipviewer/data/xsl/logiclegend.xml'>
<xmlFile file='C:/Xilinx/14.6/ISE_DS/ISE/chipviewer/data/xsl/logiclegend.xml'>
<xslFile file='legend.xsl'>
<param name='device' value='XC95144XL-10-TQ144'/>
<param name='verOn' value='0'/>
Logic/LAN_IDE/LAN_IDE_CP_envsettings.html
+3 -3
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@@ -92,13 +92,13 @@
<tr>
<td>-opt_mode</td>
<td>Optimization Goal</td>
<td>Speed</td>
<td>Area</td>
<td>SPEED</td>
</tr>
<tr>
<td>-opt_level</td>
<td>Optimization Effort</td>
<td>1</td>
<td>2</td>
<td>1</td>
</tr>
<tr>
@@ -152,7 +152,7 @@
<tr>
<td>-safe_implementation</td>
<td>&nbsp;</td>
<td>No</td>
<td>Yes</td>
<td>NO</td>
</tr>
<tr>
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<html></html>
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+518 -1140
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+1
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function showFailTable() { parent.leftnav.showFailTable(); }
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@@ -0,0 +1 @@
function showInputLeft() { parent.leftnav.showInputLeft(); }
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Logic/LAN_IDE/LAN_IDE_CP_html/fit/logic_legXC95.htm
+2
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@@ -0,0 +1,2 @@
<html><body><pre>
</pre></body></html>
Logic/LAN_IDE/LAN_IDE_CP_html/fit/logic_legXbr.htm
+16
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@@ -0,0 +1,16 @@
<html><body><pre>
I/O Style - OD - OpenDrain
- PU - Pullup
- PN - Pulldown
- KPR - Keeper
- S - SchmittTrigger
- DG - DataGate
Reg Use - LATCH - Transparent latch
- DFF - D-flip-flop
- DEFF - D-flip-flop with clock enable
- TFF - T-flip-flop
- TDFF - Dual-edge-triggered T-flip-flop
- DDFF - Dual-edge-triggered flip-flop
- DDEFF - Dual-edge-triggered flip-flop with clock enable
/S (after any above flop/latch type) indicates initial state is Set
</pre></body></html>
Logic/LAN_IDE/LAN_IDE_CP_html/fit/logic_legXpla3.htm
+3
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@@ -0,0 +1,3 @@
<html><body><pre>
Legend: PU - Pull Up
</pre></body></html>
Logic/LAN_IDE/LAN_IDE_CP_html/fit/logicleft.js
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@@ -0,0 +1 @@
function showLogicLeft() { parent.leftnav.showLogicLeft(); }
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Logic/LAN_IDE/LAN_IDE_CP_html/fit/pin_legXC95.htm
+13
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@@ -0,0 +1,13 @@
<html><body><pre>
Legend : NC = Not Connected, unbonded pin
PGND = Unused I/O configured as additional Ground pin
TIE = Unused I/O floating -- must tie to VCC, GND or other signal
VCC = Dedicated Power Pin
GND = Dedicated Ground Pin
TDI = Test Data In, JTAG pin
TDO = Test Data Out, JTAG pin
TCK = Test Clock, JTAG pin
TMS = Test Mode Select, JTAG pin
PE = Port Enable pin
PROHIBITED = User reserved pin
</pre></body></html>
Logic/LAN_IDE/LAN_IDE_CP_html/fit/pin_legXbr.htm
+21
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@@ -0,0 +1,21 @@
<html><body><pre>
Legend : NC = Not Connected, unbonded pin
PGND = Unused I/O configured as additional Ground pin
KPR = Unused I/O with weak keeper (leave unconnected)
WPU = Unused I/O with weak pull up (leave unconnected)
WPD = Unused I/O with weak pull down (leave unconnected)
TIE = Unused I/O floating -- must tie to VCC, GND or other signal
VCC = Dedicated Power Pin
VCCAUX = Power supply for JTAG pins
VCCIO-3.3 = I/O supply voltage for LVTTL, LVCMOS33, SSTL3_I
VCCIO-2.5 = I/O supply voltage for LVCMOS25, SSTL2_I
VCCIO-1.8 = I/O supply voltage for LVCMOS18
VCCIO-1.5 = I/O supply voltage for LVCMOS15, HSTL_I
VREF = Reference voltage for indicated input standard
GND = Dedicated Ground Pin
TDI = Test Data In, JTAG pin
TDO = Test Data Out, JTAG pin
TCK = Test Clock, JTAG pin
TMS = Test Mode Select, JTAG pin
PROHIBITED = User reserved pin
</pre></body></html>
Logic/LAN_IDE/LAN_IDE_CP_html/fit/pin_legXpla3.htm
+13
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@@ -0,0 +1,13 @@
<html><body><pre>
Legend : NC = Not Connected, unbonded pin
PE = Port Enable pin
WPU = Unused with Internal Weak Pull Up
TIE = Unused I/O floating -- must tie to VCC, GND or other signal
VCC = Dedicated Power Pin
GND = Dedicated Ground Pin
TDI = Test Data In, JTAG pin
TDO = Test Data Out, JTAG pin
TCK = Test Clock, JTAG pin
TMS = Test Mode Select, JTAG pin
PROHIBITED = User reserved pin
</pre></body></html>
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Logic/LAN_IDE/LAN_IDE_CP_html/fit/summary.htm
+11 -11
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@@ -30,7 +30,7 @@
<tr>
<td width="40%"> <b>Date</b>
</td>
<td width="60%"> 12-28-2016, 0:50AM</td>
<td width="60%"> 12-28-2016, 2:13AM</td>
</tr>
</table></span><br><span id="sumres" class="pgRef"><h5 align="center">RESOURCES SUMMARY</h5>
<table align="center" width="90%" border="1" cellspacing="0" cellpadding="0">
@@ -42,11 +42,11 @@
<th width="20%">Function Block Inputs Used</th>
</tr>
<tr>
<td width="20%" align="center">136/144  (95%)</td>
<td width="20%" align="center">406/720  (57%)</td>
<td width="20%" align="center">46/144  (32%)</td>
<td width="20%" align="center">106/117  (91%)</td>
<td width="20%" align="center">309/432  (72%)</td>
<td width="20%" align="center">107/144  (75%)</td>
<td width="20%" align="center">228/720  (32%)</td>
<td width="20%" align="center">22/144  (16%)</td>
<td width="20%" align="center">107/117  (92%)</td>
<td width="20%" align="center">193/432  (45%)</td>
</tr>
</table></span><br><span id="pinres" class="pgRef"><h5 align="center">PIN RESOURCES</h5>
<table align="center" width="90%" border="0" cellspacing="0" cellpadding="0"><tr>
@@ -58,8 +58,8 @@
</tr>
<tr>
<td width="33%"> Input</td>
<td width="33%" align="center"> 33</td>
<td width="33%" align="center"> 33</td>
<td width="33%" align="center"> 34</td>
<td width="33%" align="center"> 34</td>
</tr>
<tr>
<td width="33%"> Output</td>
@@ -96,7 +96,7 @@
<tr>
<td width="33%"> I/O</td>
<td width="33%" align="center"> 
100</td>
101</td>
<td width="33%" align="center"> 110</td>
</tr>
<tr>
@@ -123,7 +123,7 @@
<table align="center" width="90%" border="1" cellspacing="0" cellpadding="0">
<tr>
<td width="50%"> Macrocells in high performance mode (MCHP)</td>
<td width="50%"> 136</td>
<td width="50%"> 107</td>
</tr>
<tr>
<td width="50%"> Macrocells in low power mode (MCLP)</td>
@@ -131,7 +131,7 @@
</tr>
<tr>
<td width="50%"> Total macrocells used (MC)</td>
<td width="50%"> 136</td>
<td width="50%"> 107</td>
</tr>
</table></span><form><span class="pgRef"><table width="90%" align="center"><tr>
<td align="left"><input type="button" onclick="javascript:parent.leftnav.showTop()" onmouseover="window.status='goto top of page'; return true;" onmouseout="window.status=''" value="back to top"></td>
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@@ -0,0 +1,65 @@
<!doctype HTML public "-//W3C//DTD HTML 4.0 Frameset//EN">
<html>
<!--(==============================================================)-->
<!--(Document created with RoboEditor. )============================-->
<!--(==============================================================)-->
<head>
<title>unmapinputdoc</title>
<!--(Meta)==========================================================-->
<meta name=generator content="RoboHELP by eHelp Corporation - www.ehelp.com">
<meta name=generator-major-version content=0.1>
<meta name=generator-minor-version content=1>
<meta name=filetype content=kadov>
<meta name=filetype-version content=1>
<meta name=page-count content=1>
<meta name=layout-height content=353>
<meta name=layout-width content=615>
<meta name=date content="11 26, 2002 2:10:18 PM">
<style>
<!--
p.whs1 {font-family: arial, sans-serif; font-size: 10pt;}
--></style><script language="javascript" title="WebHelpInlineScript">
<!--
function reDo() {
if (innerWidth != origWidth || innerHeight != origHeight)
location.reload();
}
if ((parseInt(navigator.appVersion) == 4) && (navigator.appName == "Netscape")) {
origWidth = innerWidth;
origHeight = innerHeight;
onresize = reDo;
}
//-->
</script><style>
<!--
div.WebHelpPopupMenu {position:absolute; left:0px; top:0px; z-index:4; visibility:hidden;}
p.WebHelpNavBar {text-align:right;}
-->
</style>
</head>
<!--(Body)==========================================================-->
<body>
<h1>Unmapped Inputs</h1>
<p class="whs1">This page shows
input signals which were either not mapped or <span style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">not
routed.</FONT></span></p>
</body>
</html>
Logic/LAN_IDE/LAN_IDE_CP_html/fit/unmaplogicdoc.htm
+68
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@@ -0,0 +1,68 @@
<!doctype HTML public "-//W3C//DTD HTML 4.0 Frameset//EN">
<html>
<!--(==============================================================)-->
<!--(Document created with RoboEditor. )============================-->
<!--(==============================================================)-->
<head>
<title>unmaplogicdoc</title>
<!--(Meta)==========================================================-->
<meta name=generator content="RoboHELP by eHelp Corporation - www.ehelp.com">
<meta name=generator-major-version content=0.1>
<meta name=generator-minor-version content=1>
<meta name=filetype content=kadov>
<meta name=filetype-version content=1>
<meta name=page-count content=1>
<meta name=layout-height content=353>
<meta name=layout-width content=615>
<meta name=date content="11 26, 2002 2:04:45 PM">
<style>
<!--
p.whs1 {font-size: 22pt; font-weight: bold;}
p.whs2 {font-family: arial, sans-serif; font-size: 10pt; font-weight: normal;}
--></style><script language="javascript" title="WebHelpInlineScript">
<!--
function reDo() {
if (innerWidth != origWidth || innerHeight != origHeight)
location.reload();
}
if ((parseInt(navigator.appVersion) == 4) && (navigator.appName == "Netscape")) {
origWidth = innerWidth;
origHeight = innerHeight;
onresize = reDo;
}
//-->
</script><style>
<!--
div.WebHelpPopupMenu {position:absolute; left:0px; top:0px; z-index:4; visibility:hidden;}
p.WebHelpNavBar {text-align:right;}
-->
</style>
</head>
<!--(Body)==========================================================-->
<body>
<p class="whs1">Unmapped Logic</p>
<p class="whs2">This page shows those equations whose
logic was either not placed or not <span style="font-family: arial, sans-serif;
font-size: 10pt;
font-weight: normal;"><FONT SIZE=2 style="font-size:10pt;">completely
placed in the specified device.</FONT></span></p>
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<!doctype HTML public "-//W3C//DTD HTML 4.0 Frameset//EN">
<html>
<!--(==============================================================)-->
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<head>
<title>CPLD Timing Analysis Glossary</title>
<!--(Meta)==========================================================-->
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<meta name=date content="04 8, 2003 10:49:54 AM">
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<!--(Body)==========================================================-->
<body>
<h1>Introduction</h1>
<p>This report is the result of a static timing analysis of your design
after it has been fit in the device that you selected. The timing values
given represent the worst-case values over the recommended operating conditions
for the part. </p>
<h1>Overview</h1>
<p>The timing report consists of a series of sections: </p>
<h2>Summary</h2>
<p>This table summarizes the external timing parameters for your device,
including <a href="#tPD"><!--kadov_tag{{<ignored>}}-->tPD<!--kadov_tag{{</ignored>}}--></a>,
<a href="#tCO"><!--kadov_tag{{<ignored>}}-->tCO<!--kadov_tag{{</ignored>}}--></a>,
<a href="#tSU"><!--kadov_tag{{<ignored>}}-->tSU<!--kadov_tag{{</ignored>}}--></a>,
<a href="#tCYC"><!--kadov_tag{{<ignored>}}-->tCYC<!--kadov_tag{{</ignored>}}--></a>,
and <a href="#fSYSTEM"><!--kadov_tag{{<ignored>}}-->fSYSTEM<!--kadov_tag{{</ignored>}}--></a>.
<!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->For a more
detailed description of the timing model for your device, please refer
to the application notes linked below.</p>
<h2>Timing Constraints</h2>
<p>This section reports on any timing constraints that you created for
your design. Timing constraints can be entered using the Constraints Editor
tool, or by editing an Implementation Constraints File directly. For more
information on creating timing constraints, see the Constraints Guide.
</p>
<p class=Note><span style="font-weight: bold;">Note</span> that if you
did not define any constraints for your design, then the timing analysis
software will automatically create a default set of constraints for you.
These include pad-to-pad, register-to-register, pad-to-register, and period
constraints. A constraint value of 0 <!--kadov_tag{{<ignored>}}-->ns<!--kadov_tag{{</ignored>}}-->
will be used for all of these automatically generated constraints. As
a result, all paths listed under each constraint will violate the constraint,
and will have a negative value for slack.</p>
<p class=Note><span style="font-weight: bold;">Note</span> also that to
limit the size of the report, each path endpoint involved in a timing
path will only be listed once, under a single constraint. <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}--></p>
<p>For each timing path listed under a constraint, there is a hyperlink
that can be used to open a window listing the individual internal delay
elements traversed in the path. To understand these delay elements, consult
the <a href="#Definitions">Definitions</a> section below, or the following
application notes and white papers: </p>
<p><a href="http://www.xilinx.com/apps/epld.htm#CoolRunner2">XAPP375: Understanding
the <!--kadov_tag{{<ignored>}}-->CoolRunner-II<!--kadov_tag{{</ignored>}}-->
Timing Model</a> </p>
<p><a href="http://www.xilinx.com/publications/whitepapers/index.htm">WP122:
Using the <!--kadov_tag{{<ignored>}}-->CoolRunner<!--kadov_tag{{</ignored>}}-->
XPLA3 Timing Model</a> </p>
<p><a href="http://www.xilinx.com/apps/epld.htm#CoolRunner2">XAPP071: Using
the XC9500 Timing Model</a> </p>
<p><a href="http://www.xilinx.com/apps/epld.htm#CoolRunner2">XAPP111: Using
the XC9500XL Timing Model</a></p>
<p><a href="http://www.xilinx.com/apps/epld.htm#CoolRunner2"><!--kadov_tag{{<ignored>}}-->XAPP<!--kadov_tag{{</ignored>}}-->
362: Using the XC9500XV Timing Model</a></p>
<p>available in the literature section of <a href="http://www.xilinx.com"><!--kadov_tag{{<ignored>}}-->www.xilinx.com</a>.<!--kadov_tag{{</ignored>}}-->
</p>
<h2>Data Sheet Report</h2>
<p>This section of the report lists the external timing parameters for
your design. This includes; maximum external clock speed for each clock,
setup and hold times for each registered input, clock-to-output pad timing
for each registered output, clock to setup time for each register-to-register
timing path, and pad-to-pad time for each combinatorial path through your
design. </p>
<h2>Going Further</h2>
<p>To do more advanced timing analysis of your design, select the process
<span style="font-weight: bold;">Analyze Post-Fit Static Timing</span>
in <!--kadov_tag{{<ignored>}}-->iSE<!--kadov_tag{{</ignored>}}-->. This
will run <!--kadov_tag{{<ignored>}}-->Xilinx's<!--kadov_tag{{</ignored>}}-->
Timing Analyzer tool interactively. <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->The
Timing Analyzer provides a powerful, flexible, and easy way to perform
static timing analysis on <!--kadov_tag{{<ignored>}}-->FPGA<!--kadov_tag{{</ignored>}}-->
and <!--kadov_tag{{<ignored>}}-->CPLD<!--kadov_tag{{</ignored>}}--> designs.
With Timing Analyzer, analysis can be performed immediately after mapping,
placing or routing an <!--kadov_tag{{<ignored>}}-->FPGA<!--kadov_tag{{</ignored>}}-->
design, and after fitting and routing a <!--kadov_tag{{<ignored>}}-->CPLD<!--kadov_tag{{</ignored>}}-->
design. </p>
<p>Timing Analyzer verifies that the delay along a given path or paths
meets specified timing requirements. It organizes and displays data that
allows you to analyze critical paths in a circuit, the cycle time of the
circuit, the delay along any specified <!--kadov_tag{{<ignored>}}-->path(s<!--kadov_tag{{</ignored>}}-->),
and the path with the greatest delay. It also provides a quick analysis
of the effect different speed grades have on the same design. <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}--></p>
<p>Timing Analyzer performs setup and hold checks (skew analysis). It works
with synchronous systems composed of synchronous elements and combinatorial
logic. In synchronous design, Timing Analyzer takes into account all path
delays, including clock-to-out and setup requirements, while calculating
the worst-case timing of the design. </p>
<p>Timing Analyzer creates timing analysis reports based on existing timing
constraints or user specified paths within the program. Timing reports
have a hierarchical browser to quickly jump to different sections of the
reports. Timing paths in reports can be cross probed to synthesis tools
(Exemplar and <!--kadov_tag{{<ignored>}}-->Synplicity<!--kadov_tag{{</ignored>}}-->)
and <!--kadov_tag{{<ignored>}}-->Floorplanner<!--kadov_tag{{</ignored>}}-->.
</p>
<p>There are several ways to issue commands in Timing Analyzer. Timing
Analyzer can be controlled through <!--kadov_tag{{<ignored>}}-->GUI<!--kadov_tag{{</ignored>}}-->
features (menu commands) or its comprehensive macro command language facility.
You can select from menus, click toolbar buttons, type keyboard commands
in the console window, and run macros. </p>
<h1><a name=Definitions></a>Definitions</h1>
<h2><a name=tPD></a>Pad to Pad (<!--kadov_tag{{<ignored>}}-->tPD<!--kadov_tag{{</ignored>}}-->)
</h2>
<p>Reports pad to pad paths that start at input pads and end at output
pads. The maximum external pad to pad delay. <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->Combinatorial
pad-to-pad paths begin at input pads, propagate through one or more levels
of combinatorial logic and end at output pads. Combinatorial paths also
trace through the enable inputs of 3-state controlled pads. Combinatorial
paths are not traced through clock, and asynchronous set and reset inputs
of registers. These paths are also broken at bidirectional pins</p>
<h2><a name=tCO></a>Clock Pad to Output Pad (<!--kadov_tag{{<ignored>}}-->tCO<!--kadov_tag{{</ignored>}}-->)
</h2>
<p>The maximum external clock pad to output pad delay. <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->Reports
paths that start at input <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->pads
trace through clock inputs of <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->registers
and end at output pads. Paths are not traced through PRE/<!--kadov_tag{{<ignored>}}-->CLR<!--kadov_tag{{</ignored>}}-->
<!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->inputs
of registers. <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->You
can directly specify <!--kadov_tag{{<ignored>}}-->tCO<!--kadov_tag{{</ignored>}}-->
for all registered output paths in your design using the Pad-to-Pad <!--kadov_tag{{<ignored>}}-->timespec<!--kadov_tag{{</ignored>}}-->.
Clock-Pad-to-Pad paths for global clocks begin at global clock pads, propagate
through global clock buffers, and propagate through the flip-flop <!--kadov_tag{{<ignored>}}-->Q<!--kadov_tag{{</ignored>}}-->
output and any number of levels of combinatorial logic and end at the
output pad. Clock-Pad-to-Pad paths for product term clock paths begin
at input pads, propagate through any number of logic levels feeding into
a clock product term, propagate through the flip-flop <!--kadov_tag{{<ignored>}}-->Q<!--kadov_tag{{</ignored>}}-->
output and any number of levels of combinatorial logic and end at the
output pad. Clock-Pad-to-Pad paths also trace through the enable inputs
of 3-state controlled pads.</p>
<h2><a name=tSU></a>Setup to Clock at Pad (<!--kadov_tag{{<ignored>}}-->tSU<!--kadov_tag{{</ignored>}}-->
or <!--kadov_tag{{<ignored>}}-->tSUF<!--kadov_tag{{</ignored>}}-->) </h2>
<p>Reports external setup time of data <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->to
clock at pad. Data path starts at an input pad and ends at register <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->(Fast
Input Register for <!--kadov_tag{{<ignored>}}-->tSUF<!--kadov_tag{{</ignored>}}-->)
D/<!--kadov_tag{{<ignored>}}-->T<!--kadov_tag{{</ignored>}}--> <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->input.
Clock path starts at input pad and ends at the register clock input. <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->Paths
are not traced through registers. Pin-to-pin setup requirement is not
reported or guaranteed for product-term clocks derived from <!--kadov_tag{{<ignored>}}-->macrocell<!--kadov_tag{{</ignored>}}-->
feedback signals. </p>
<p>The minimum required setup time for flip-flops. <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->You
can specify the <!--kadov_tag{{<ignored>}}-->tSU<!--kadov_tag{{</ignored>}}-->
(setup-to-clock) for all inputs in your design relative to a global clock
or product term clock. Each <!--kadov_tag{{<ignored>}}-->tSU<!--kadov_tag{{</ignored>}}-->
OFFSET timespec involves an input path and a clock path. Input paths start
at input pads, propagate through input buffers and any number of combinatorial
logic levels before ending at a flip-flop D/T input, including the receiving
flip-flop's tSU. <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->Input
paths are not traced through flip-flop clock pins, asynchronous set/reset
inputs or bidirectional I/O pins. Global clock paths start at global clock
pads, propagate through global clock buffers and end at the flip-flop
clock pin. Product term clock paths start at input pads, propagate through
a single level of logic implemented in a clock product term and end at
the flip-flop clock pin.</p>
<h2><a name=tCYC></a>Clock to Setup (tCYC) </h2>
<p>Register to register cycle time. Includes source register tCO and destination
register tSU. </p>
<p class=Note><span style="font-weight: bold;">Note</span> that when the
computed Maximum Clock Speed is limited by tCYC, it is computed assuming
that all registers are rising-edge sensitive. </p>
<h2><a name=fSYSTEM></a>fSYSTEM </h2>
<p>Maximum clock operating frequency. <!--kadov_tag{{<spaces>}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->You
can specify the fSYSTEM (clock frequency or period) for all registered
paths in your design using a Register-to-Register timespec. Register-to-Register
paths begin at flip-flop clock inputs, propagate through the flip-flop
Q output and any number of levels of combinatorial logic and end at the
receiving flip-flop D/T input, including the receiving flip-flop's tSU.
When these flip-flops are clocked by the same clock, the delay on this
path is equivalent to the cycle time of the clock. Registered paths do
not propagate through clock, and asynchronous set and reset inputs of
registers as shown below. These paths are also broken at bidirectional
pins.</p>
<p>&nbsp;</p>
</body>
</html>
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<!-- $Id: cpldta_style.css,v 1.2 2003/03/20 05:15:52 soeren Exp $ -->
<!-- Stylesheet for the CPLD HTML Timing Report -->
<!-- style for H1 elements -->
.cpldta_text_report_header {
font-style: normal;
font-weight: bold;
font-size: 25pt;
font-family: Arial, Helvetica, sans-serif;
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.cpldta_text_section_header {
font-style: normal;
font-weight: bold;
font-size: 15pt;
font-family: Arial, Helvetica, sans-serif;
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font-style: normal;
font-weight: bold;
font-size: 10pt;
font-family: Arial, Helvetica, sans-serif;
text-align: left;}
<!-- Following used for the header of the notes and warnings table -->
.cpldta_warnings_header {
font-style: normal;
font-weight: normal;
font-size: 10pt;
font-family: Arial, Helvetica, sans-serif;
text-align: center;
background-color: #FFFFCC; }
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.cpldta_text_normal {
font-style: normal;
font-weight: normal;
font-size: 10pt;
font-family: Arial, Helvetica, sans-serif;
text-align: left;}
<!-- style for general text label fields -->
.cpldta_text_normal_bold {
font-style: normal;
font-weight: bold;
font-size: 10pt;
font-family: Arial, Helvetica, sans-serif;
text-align: left;}
<!-- Following two styles are used for constraint descriptions -->
.cpldta_constraint_description_normal {
font-style: normal;
font-weight: normal;
font-size: 10pt;
font-family: Arial, Helvetica, sans-serif;
text-align: left;}
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font-style: normal;
font-weight: bold;
font-size: 10pt;
font-family: Arial, Helvetica, sans-serif;
text-align: left;}
<!-- Style for the name of a constraint that is met -->
.cpldta_constraint_name {
font-style: normal;
font-weight: normal;
font-size: 10pt;
font-family: Arial, Helvetica, sans-serif;
text-align: left;}
<!-- Style for the name of a constraint that is not met -->
.cpldta_constraint_name_error {
font-style: normal;
font-weight: normal;
font-size: 10pt;
font-family: Arial, Helvetica, sans-serif;
text-align: left;
background-color: #FFCCCC; }
<!-- Style for the delay of a constraint that is met -->
.cpldta_time_value {
font-style: normal;
font-weight: normal;
font-size: 10pt;
font-family: Arial, Helvetica, sans-serif;
text-align: center;}
<!-- Style for the delay of a constraint that is not met -->
.cpldta_time_value_error {
font-style: normal;
font-weight: normal;
font-size: 10pt;
font-family: Arial, Helvetica, sans-serif;
text-align: center;
background-color: #FFCCCC; }
<!-- Styles for the header of the delay table for a constraint -->
.cpldta_delaytable_header {
font-style: normal;
font-weight: bold;
font-size: 12pt;
font-family: Arial, Helvetica, sans-serif;
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font-style: normal;
font-weight: Bold;
font-size: 10pt;
font-family: Arial, Helvetica, sans-serif;
text-align: center;}
<!-- Following styles used for the datasheet section of the report -->
.cpldta_datasheet_pathname {
font-style: normal;
font-weight: normal;
font-size: 10pt;
font-family: Arial, Helvetica, sans-serif;
text-align: left;}
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font-size: 10pt;
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text-align: center;}
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<html>
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<title>Reports</title>
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<head>
<title>Timing Navigation</title>
<meta http-equiv="Content-Type" content="text/html; charset=iso-8859-1">
<link rel="stylesheet" type="text/css" href="../tim/toc.css">
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<body bgcolor="#CCCCCC" text="#000000" onLoad="parent.frames.mainFrame.location='timing_report.htm'">
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<div align="left"><SPAN class="HEADING">Timing Report</span></div>
</td>
</tr>
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<td width="7">&nbsp;</td>
<td colspan="2"><a href="timing_report.htm#TimingReport" target="mainFrame" class="SECONDARY-NAV">Description</a></td>
</tr>
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<td colspan="2"><a href="cpldta_glossary.htm" target="mainFrame" class="SECONDARY-NAV">Definitions</a></td>
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</tr>
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@@ -0,0 +1,14 @@
<html>
<head>
<title>Reports</title>
<meta http-equiv="Content-Type" content="text/html; charset=iso-8859-1">
</head>
<frameset rows="94,*" cols="*" frameborder="NO" border="0" framespacing="0">;
<frame name="topFrame" scrolling="NO" noresize src="topnav.htm" marginwidth="0" marginheight="0">
<frame name="mainFrame" src="timing_report.htm" marginwidth="0" marginheight="0">
</frameset>
<noframes>
<body bgcolor="#FFFFFF" text="#000000">
</body>
</noframes>
</html>
Logic/LAN_IDE/LAN_IDE_CP_html/tim/timing_report.htm
+10
View File
@@ -0,0 +1,10 @@
<html><head>
<title>Timing report</title><meta http-equiv="Content-Type" content="text/html; charset=iso-8859-1"></head>
<body bgcolor="#ffffff" text="#000000">
<p><font face="Arial, Helvetica, sans-serif" size="2">No timing data is available
for your design. </font></p>
<p><font face="Arial, Helvetica, sans-serif" size="2">Please double click on the
<b>Generate Timing</b> process in the "Process for Current Sources"
window.</font></p>
</body></html>
Logic/LAN_IDE/LAN_IDE_CP_html/tim/toc.css
+36
View File
@@ -0,0 +1,36 @@
.HEADING {
font-size: 15px;
font-family: Arial, Geneva, Verdana, Helvetica;
font-weight: bold; color: #000000;
text-align: normal;
margin-left: 0px; }
.Fitting {
font-size: 11px;
font-family: Arial, Geneva, Verdana, Helvetica;
font-weight: bold; color: #000000;
text-align: normal;
margin-left: 0px; }
.SECONDARY-NAV {
font-size: 11px;
font-family: Arial, Geneva, Verdana, Helvetica;
font-weight: bold; color: #FFFFFF;
margin-left: 0px;
text-decoration: none; ;
list-style-type: disc ;
list-style-position: inside }
.Timing {
font-size: 11px;
font-family: Arial, Geneva, Verdana, Helvetica;
font-weight: bold; color: #333333;
margin-left: 0px;
text-decoration: none; ;
list-style-type: disc ;
list-style-position: inside }
.Timing-Error {
font-size: 11px;
font-family: Arial, Geneva, Verdana, Helvetica;
font-weight: bold; color: #990000;
margin-left: 0px;
text-decoration: none; ;
list-style-type: disc ;
list-style-position: inside }
Logic/LAN_IDE/LAN_IDE_CP_html/tim/topnav.htm
+31
View File
@@ -0,0 +1,31 @@
<html>
<head>
<title>CPLD Reports Banner</title>
<meta http-equiv="Content-Type" content="text/html; charset=iso-8859-1">
</head>
<body bgcolor="#FFFFFF" text="#000000">
<table width="100%" border="0" cellspacing="0" cellpadding="0">
<tr>
<td width="607" height="69"><img src="../images/cpldBanner.jpg" width="486" height="69"></td>
<td width="251"><img src="../images/logo.jpg"></td>
<td bgcolor="#FFFFFF">&nbsp;</td>
</tr>
<tr>
<td bgcolor="#000000" height="24">
<img src="../images/blackBar.jpg" width="125" height="24">
<img src="../images/fitterRpt.jpg" width="88" height="24" usemap="#fitReport" border="0">
<img src="../images/spacer.jpg" width="32" height="24">
<img src="../images/timingRpt.jpg" width="100" height="24" usemap="#timReport" border="0">
<td bgcolor="#000000" height="24">&nbsp;</td>
<td bgcolor="#000000">&nbsp;</td>
</tr>
</table>
<map name="fitReport">
<area shape="rect" coords="1,1,86,22" href="../fit/report.htm" target="_top">
</map>
<map name="timReport">
<area shape="rect" coords="1,1,101,24" href="../tim/report.htm" target="_top">
</map>
</body>
</html>
Logic/LAN_IDE/LAN_IDE_CP_ngdbuild.xrpt
+17 -23
View File
@@ -5,7 +5,7 @@
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="NgdBuild" timeStamp="Wed Dec 28 00:50:15 2016">
<application stringID="NgdBuild" timeStamp="Wed Dec 28 20:28:43 2016">
<section stringID="User_Env">
<table stringID="User_EnvVar">
<column stringID="variable"/>
@@ -70,39 +70,33 @@
<item dataType="int" stringID="NGDBUILD_NUM_INFOS" value="0"/>
</section>
<section stringID="NGDBUILD_PRE_UNISIM_SUMMARY">
<item dataType="int" stringID="NGDBUILD_NUM_AND2" value="132"/>
<item dataType="int" stringID="NGDBUILD_NUM_AND3" value="22"/>
<item dataType="int" stringID="NGDBUILD_NUM_AND4" value="11"/>
<item dataType="int" stringID="NGDBUILD_NUM_AND5" value="2"/>
<item dataType="int" stringID="NGDBUILD_NUM_FD" value="7"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDC" value="3"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDCE" value="36"/>
<item dataType="int" stringID="NGDBUILD_NUM_AND2" value="83"/>
<item dataType="int" stringID="NGDBUILD_NUM_AND3" value="23"/>
<item dataType="int" stringID="NGDBUILD_NUM_FD" value="3"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDC" value="8"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDCE" value="35"/>
<item dataType="int" stringID="NGDBUILD_NUM_GND" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_IBUF" value="34"/>
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="225"/>
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="148"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="37"/>
<item dataType="int" stringID="NGDBUILD_NUM_OR2" value="106"/>
<item dataType="int" stringID="NGDBUILD_NUM_OR3" value="15"/>
<item dataType="int" stringID="NGDBUILD_NUM_OR2" value="87"/>
<item dataType="int" stringID="NGDBUILD_NUM_OR3" value="2"/>
<item dataType="int" stringID="NGDBUILD_NUM_OR4" value="3"/>
<item dataType="int" stringID="NGDBUILD_NUM_OR5" value="3"/>
<item dataType="int" stringID="NGDBUILD_NUM_VCC" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_XOR2" value="16"/>
<item dataType="int" stringID="NGDBUILD_NUM_XOR2" value="25"/>
</section>
<section stringID="NGDBUILD_POST_UNISIM_SUMMARY">
<item dataType="int" stringID="NGDBUILD_NUM_AND2" value="132"/>
<item dataType="int" stringID="NGDBUILD_NUM_AND3" value="22"/>
<item dataType="int" stringID="NGDBUILD_NUM_AND4" value="11"/>
<item dataType="int" stringID="NGDBUILD_NUM_AND5" value="2"/>
<item dataType="int" stringID="NGDBUILD_NUM_GND" value="11"/>
<item dataType="int" stringID="NGDBUILD_NUM_AND2" value="83"/>
<item dataType="int" stringID="NGDBUILD_NUM_AND3" value="23"/>
<item dataType="int" stringID="NGDBUILD_NUM_GND" value="12"/>
<item dataType="int" stringID="NGDBUILD_NUM_IBUF" value="74"/>
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="225"/>
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="148"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="39"/>
<item dataType="int" stringID="NGDBUILD_NUM_OR2" value="106"/>
<item dataType="int" stringID="NGDBUILD_NUM_OR3" value="15"/>
<item dataType="int" stringID="NGDBUILD_NUM_OR2" value="87"/>
<item dataType="int" stringID="NGDBUILD_NUM_OR3" value="2"/>
<item dataType="int" stringID="NGDBUILD_NUM_OR4" value="3"/>
<item dataType="int" stringID="NGDBUILD_NUM_OR5" value="3"/>
<item dataType="int" stringID="NGDBUILD_NUM_VCC" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_XOR2" value="16"/>
<item dataType="int" stringID="NGDBUILD_NUM_XOR2" value="25"/>
</section>
<section stringID="NGDBUILD_CORE_GENERATION_SUMMARY">
<section stringID="NGDBUILD_CORE_INSTANCES"/>
Logic/LAN_IDE/LAN_IDE_CP_pad.csv
+1 -1
View File
@@ -1,7 +1,7 @@
Release 8.1i - Fit P.68d
Copyright(c) 1995-2003 Xilinx Inc. All rights reserved
12-28-2016 0:50AM
12-28-2016 8:53PM
NOTE: This file is designed to be imported into a spreadsheet program
such as Microsoft Excel for viewing, printing and sorting. The comma ','
1 Release 8.1i - Fit P.68d
2 Copyright(c) 1995-2003 Xilinx Inc. All rights reserved
3 12-28-2016 0:50AM 12-28-2016 8:53PM
4 NOTE: This file is designed to be imported into a spreadsheet program
5 such as Microsoft Excel for viewing, printing and sorting. The comma ','
6 character is used as the data field separator.
7 This file is also designed to support parsing.
Logic/LAN_IDE/LAN_IDE_CP_summary.html
+8 -7
View File
@@ -2,11 +2,12 @@
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='4'><B>LAN_IDE_CP Project Status (12/28/2016 - 00:50:17)</B></TD></TR>
<TD ALIGN=CENTER COLSPAN='4'><B>LAN_IDE_CP Project Status (12/28/2016 - 02:12:48)</B></TD></TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
<TD>LAN_IDE.xise</TD>
<TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD>
<TD> No Errors </TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>
@@ -24,7 +25,7 @@ No Errors</TD>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 14.6</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
<TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE\_xmsgs/*.xmsgs?&DataKey=Warning'>17 Warnings (17 new)</A></TD>
<TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE\_xmsgs/*.xmsgs?&DataKey=Warning'>13 Warnings (2 new)</A></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
@@ -35,7 +36,7 @@ No Errors</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD>
<TD><A HREF_DISABLED='Xilinx Default (unlocked)?&DataKey=Strategy'>Xilinx Default (unlocked)</A></TD>
<TD><A HREF_DISABLED='area?&DataKey=Strategy'>area</A></TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD>
<TD>&nbsp;</TD>
</TR>
@@ -64,9 +65,9 @@ System Settings</A>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE\LAN_IDE_CP.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Mi 28. Dez 00:50:08 2016</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE\_xmsgs/xst.xmsgs?&DataKey=Warning'>16 Warnings (16 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE\LAN_IDE_CP.bld'>Translation Report</A></TD><TD>Current</TD><TD>Mi 28. Dez 00:50:16 2016</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE\_xmsgs/ngdbuild.xmsgs?&DataKey=Warning'>1 Warning (1 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD>CPLD Fitter Report (Text)</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE\LAN_IDE_CP.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Mi 28. Dez 20:17:00 2016</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE\_xmsgs/xst.xmsgs?&DataKey=Warning'>12 Warnings (1 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE\LAN_IDE_CP.bld'>Translation Report</A></TD><TD>Current</TD><TD>Mi 28. Dez 20:17:08 2016</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE\_xmsgs/ngdbuild.xmsgs?&DataKey=Warning'>1 Warning (1 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE\LAN_IDE_CP.rpt'>CPLD Fitter Report (Text)</A></TD><TD>Current</TD><TD>Mi 28. Dez 20:17:21 2016</TD><TD ALIGN=LEFT><font color="red"; face="Arial"><b>X </b></font><A HREF_DISABLED='C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE\_xmsgs/cpldfit.xmsgs?&DataKey=Error'>2 Errors (2 new)</A></TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE\_xmsgs/cpldfit.xmsgs?&DataKey=Warning'>11 Warnings (2 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE\_xmsgs/cpldfit.xmsgs?&DataKey=Info'>1 Info (1 new)</A></TD></TR>
<TR ALIGN=LEFT><TD>Power Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
@@ -76,5 +77,5 @@ System Settings</A>
</TABLE>
<br><center><b>Date Generated:</b> 12/28/2016 - 00:50:17</center>
<br><center><b>Date Generated:</b> 12/28/2016 - 20:17:54</center>
</BODY></HTML>
Logic/LAN_IDE/LAN_IDE_CP_xst.xrpt
+18 -18
View File
@@ -5,7 +5,7 @@
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="Xst" timeStamp="Wed Dec 28 00:50:00 2016">
<application stringID="Xst" timeStamp="Wed Dec 28 20:28:28 2016">
<section stringID="User_Env">
<table stringID="User_EnvVar">
<column stringID="variable"/>
@@ -60,8 +60,8 @@
<item DEFAULT="NGC" label="-ofmt" stringID="XST_OFMT" value="NGC"/>
<item DEFAULT="" label="-p" stringID="XST_P" value="xc9500xl"/>
<item DEFAULT="" label="-top" stringID="XST_TOP" value="LAN_IDE_CP"/>
<item DEFAULT="SPEED" label="-opt_mode" stringID="XST_OPTMODE" value="Speed"/>
<item DEFAULT="1" label="-opt_level" stringID="XST_OPTLEVEL" value="1"/>
<item DEFAULT="SPEED" label="-opt_mode" stringID="XST_OPTMODE" value="Area"/>
<item DEFAULT="1" label="-opt_level" stringID="XST_OPTLEVEL" value="2"/>
<item DEFAULT="NO" label="-iuc" stringID="XST_IUC" value="NO"/>
<item DEFAULT="YES" label="-keep_hierarchy" stringID="XST_KEEPHIERARCHY" value="Yes"/>
<item DEFAULT="as_optimized" label="-netlist_hierarchy" stringID="XST_NETLISTHIERARCHY" value="As_Optimized"/>
@@ -72,7 +72,7 @@
<item DEFAULT="YES" label="-verilog2001" stringID="XST_VERILOG2001" value="YES"/>
<item DEFAULT="YES" label="-fsm_extract" stringID="XST_FSMEXTRACT" value="YES"/>
<item DEFAULT="AUTO" label="-fsm_encoding" stringID="XST_FSMENCODING" value="Auto"/>
<item DEFAULT="NO" label="-safe_implementation" stringID="XST_SAFEIMPLEMENTATION" value="No"/>
<item DEFAULT="NO" label="-safe_implementation" stringID="XST_SAFEIMPLEMENTATION" value="Yes"/>
<item DEFAULT="YES" stringID="XST_MUXEXTRACT" value="Yes"/>
<item DEFAULT="YES" label="-resource_sharing" stringID="XST_RESOURCESHARING" value="YES"/>
<item DEFAULT="YES" label="-iobuf" stringID="XST_IOBUF" value="YES"/>
@@ -94,9 +94,10 @@
</item>
</section>
<section stringID="XST_ADVANCED_HDL_SYNTHESIS_REPORT">
<item dataType="int" stringID="XST_REGISTERS" value="1">
<item dataType="int" stringID="XST_FLIPFLOPS" value="1"/>
<item dataType="int" stringID="XST_REGISTERS" value="5">
<item dataType="int" stringID="XST_FLIPFLOPS" value="5"/>
</item>
<item dataType="int" stringID="XST_COMPARATORS" value="3"></item>
</section>
<section stringID="XST_PARTITION_REPORT">
<section stringID="XST_PARTITION_IMPLEMENTATION_STATUS">
@@ -108,27 +109,26 @@
<item stringID="XST_RTL_TOP_LEVEL_OUTPUT_FILE_NAME" value="LAN_IDE_CP.ngr"/>
<item stringID="XST_TOP_LEVEL_OUTPUT_FILE_NAME" value="LAN_IDE_CP"/>
<item stringID="XST_OUTPUT_FORMAT" value="NGC"/>
<item stringID="XST_OPTIMIZATION_GOAL" value="Speed"/>
<item stringID="XST_OPTIMIZATION_GOAL" value="Area"/>
<item stringID="XST_KEEP_HIERARCHY" value="Yes"/>
</section>
<section stringID="XST_DESIGN_STATISTICS">
<item stringID="XST_IOS" value="116"/>
</section>
<section stringID="XST_CELL_USAGE">
<item dataType="int" stringID="XST_BELS" value="537">
<item dataType="int" stringID="XST_AND2" value="132"/>
<item dataType="int" stringID="XST_AND3" value="22"/>
<item dataType="int" stringID="XST_AND4" value="11"/>
<item dataType="int" stringID="XST_BELS" value="373">
<item dataType="int" stringID="XST_AND2" value="83"/>
<item dataType="int" stringID="XST_AND3" value="23"/>
<item dataType="int" stringID="XST_GND" value="1"/>
<item dataType="int" stringID="XST_INV" value="225"/>
<item dataType="int" stringID="XST_OR2" value="106"/>
<item dataType="int" stringID="XST_INV" value="148"/>
<item dataType="int" stringID="XST_OR2" value="87"/>
<item dataType="int" stringID="XST_VCC" value="1"/>
<item dataType="int" stringID="XST_XOR2" value="16"/>
<item dataType="int" stringID="XST_XOR2" value="25"/>
</item>
<item dataType="int" stringID="XST_FLIPFLOPSLATCHES" value="46">
<item dataType="int" stringID="XST_FD" value="7"/>
<item dataType="int" stringID="XST_FDC" value="3"/>
<item dataType="int" stringID="XST_FDCE" value="36"/>
<item dataType="int" stringID="XST_FD" value="3"/>
<item dataType="int" stringID="XST_FDC" value="8"/>
<item dataType="int" stringID="XST_FDCE" value="35"/>
</item>
<item dataType="int" stringID="XST_IO_BUFFERS" value="106">
<item dataType="int" stringID="XST_IBUF" value="34"/>
@@ -138,7 +138,7 @@
</section>
<section stringID="XST_ERRORS_STATISTICS">
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_ERRORS" value="0"/>
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_WARNINGS" value="16"/>
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_WARNINGS" value="12"/>
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_INFOS" value="0"/>
</section>
</application>
Logic/LAN_IDE/_ngo/netlist.lst
+1 -1
View File
@@ -1,2 +1,2 @@
C:\Users\Matze\Amiga\Hardwarehacks\Zorro-LAN-IDE\Logic\LAN_IDE\LAN_IDE_CP.ngc 1482882608
C:\Users\Matze\Amiga\Hardwarehacks\Zorro-LAN-IDE\Logic\LAN_IDE\LAN_IDE_CP.ngc 1482953316
OK
Logic/LAN_IDE/_xmsgs/cpldfit.xmsgs
+6
View File
@@ -41,5 +41,11 @@
<msg type="warning" file="Cpld" num="1007" delta="old" >Removing unused input(s) &apos;<arg fmt="%s" index="1">Z3</arg>&apos;. The input(s) are unused after optimization. Please verify functionality via simulation.
</msg>
<msg type="error" file="Cpld" num="837" delta="old" >Insufficient number of macrocells. The design needs at least <arg fmt="%d" index="1">157</arg> but only <arg fmt="%d" index="2">144</arg> left after allocating other resources.
</msg>
<msg type="error" file="Cpld" num="868" delta="old" >Cannot fit the design into any of the specified devices with the selected implementation options.
</msg>
</messages>
Logic/LAN_IDE/_xmsgs/ngdbuild.xmsgs
+1 -1
View File
@@ -5,7 +5,7 @@
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="warning" file="NgdBuild" num="470" delta="new" ><arg fmt="%s" index="1">bidirect</arg> pad net &apos;<arg fmt="%s" index="2">A&lt;15&gt;</arg>&apos; has no legal driver
<msg type="warning" file="NgdBuild" num="470" delta="old" ><arg fmt="%s" index="1">bidirect</arg> pad net &apos;<arg fmt="%s" index="2">A&lt;15&gt;</arg>&apos; has no legal driver
</msg>
</messages>
Logic/LAN_IDE/_xmsgs/pn_parser.xmsgs
+15
View File
@@ -0,0 +1,15 @@
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated -->
<!-- by the Xilinx ISE software. Any direct editing or -->
<!-- changes made to this file may result in unpredictable -->
<!-- behavior or data corruption. It is strongly advised that -->
<!-- users do not edit the contents of this file. -->
<!-- -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
<messages>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.vhd&quot; into library work</arg>
</msg>
</messages>
Logic/LAN_IDE/_xmsgs/xst.xmsgs
+12 -27
View File
@@ -5,55 +5,40 @@
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="warning" file="Xst" num="819" delta="new" >&quot;<arg fmt="%s" index="1">C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.vhd</arg>&quot; line <arg fmt="%d" index="2">114</arg>: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<arg fmt="%s" index="3">&lt;AS&gt;</arg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">IDE_WAIT</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="795" delta="new" >&quot;<arg fmt="%s" index="1">C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.vhd</arg>&quot; line <arg fmt="%d" index="2">156</arg>: Size of operands are different : result is &lt;false&gt;.
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">DS0</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">IDE_WAIT</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">DS1</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">DS0</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">FCS</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">DS1</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
<msg type="warning" file="Xst" num="1306" delta="old" >Output &lt;<arg fmt="%s" index="1">MTACK</arg>&gt; is never assigned.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">FCS</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
<msg type="warning" file="Xst" num="2565" delta="old" >Inout &lt;<arg fmt="%s" index="1">A&lt;15&gt;</arg>&gt; is never assigned.
</msg>
<msg type="warning" file="Xst" num="1306" delta="new" >Output &lt;<arg fmt="%s" index="1">MTACK</arg>&gt; is never assigned.
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">Z3</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="2565" delta="new" >Inout &lt;<arg fmt="%s" index="1">A&lt;15&gt;</arg>&gt; is never assigned.
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">CLK_EXT</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">Z3</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
<msg type="warning" file="Xst" num="1306" delta="old" >Output &lt;<arg fmt="%s" index="1">OVR</arg>&gt; is never assigned.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">CLK_EXT</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">MTCR</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="1306" delta="new" >Output &lt;<arg fmt="%s" index="1">OVR</arg>&gt; is never assigned.
<msg type="warning" file="Xst" num="1780" delta="old" >Signal &lt;<arg fmt="%s" index="1">DTACK_S</arg>&gt; is never used or assigned. This unconnected signal will be trimmed during the optimization process.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">MTCR</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="1780" delta="new" >Signal &lt;<arg fmt="%s" index="1">DTACK_S</arg>&gt; is never used or assigned. This unconnected signal will be trimmed during the optimization process.
</msg>
<msg type="warning" file="Xst" num="1780" delta="new" >Signal &lt;<arg fmt="%s" index="1">AS_D</arg>&gt; is never used or assigned. This unconnected signal will be trimmed during the optimization process.
</msg>
<msg type="warning" file="Xst" num="1426" delta="new" >The value init of the FF/Latch <arg fmt="%s" index="1">0</arg> hinder the constant cleaning in the block <arg fmt="%s" index="2">LAN_INT_ENABLE</arg>.
You should achieve better results by setting this init to <arg fmt="%i" index="3">0</arg>.
</msg>
<msg type="warning" file="Xst" num="1426" delta="new" >The value init of the FF/Latch <arg fmt="%s" index="1">LAN_INT_ENABLE</arg> hinder the constant cleaning in the block <arg fmt="%s" index="2">LAN_IDE_CP</arg>.
You should achieve better results by setting this init to <arg fmt="%i" index="3">0</arg>.
<msg type="warning" file="Xst" num="1780" delta="old" >Signal &lt;<arg fmt="%s" index="1">AS_D</arg>&gt; is never used or assigned. This unconnected signal will be trimmed during the optimization process.
</msg>
</messages>
Logic/LAN_IDE/area.xds
+14
View File
@@ -0,0 +1,14 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<DesignStrategy goal="Balanced" strategy="area" version="12.1">
<Description>The Default strategy provides a balanced optimization of performance results vs. runtime. The default property values correspond to the default values of each of the underlying implementation tools. This strategy keeps all properties in an unlocked state so that you can modify the values as you wish.</Description>
<DeviceList devices="xc9500xl"/>
<Properties>
<property name="Synthesize - XST:Optimization Goal" value="Area"/>
<property name="Synthesize - XST:Optimization Effort" value="High"/>
<property name="Synthesize - XST:Safe Implementation" value="Yes"/>
</Properties>
</DesignStrategy>
Logic/LAN_IDE/fit.bat
+1 -1
View File
@@ -1,6 +1,6 @@
@SET PATH=c:\Xilinx\14.6\ISE_DS\ISE\bin\nt64;C:\Xilinx\14.6\ISE_DS\ISE\lib\nt64
@SET XILINX=c:\Xilinx\14.6\ISE_DS\ISE
cpldfit -intstyle ise -p xc95144xl-10-TQ144 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs %1 -pterms %2 -unused float -power std -terminate float LAN_IDE_CP.ngd >log.txt
cpldfit -intstyle ise -p xc95144xl-10-TQ144 -ofmt vhdl -optimize density -htmlrpt -loc on -slew fast -init low -inputs %1 -pterms %2 -unused float -power std -terminate float LAN_IDE_CP.ngd >log.txt
@IF %ERRORLEVEL% NEQ 0 GOTO NO_SUCCESS
tsim -intstyle ise LAN_IDE_CP LAN_IDE_CP.nga >>log.txt
hprep6 -s IEEE1149 -n LAN_IDE_CP -i LAN_IDE_CP
Logic/LAN_IDE/iseconfig/LAN_IDE.projectmgr
+4 -4
View File
@@ -23,13 +23,13 @@
<ClosedNode>Design Utilities</ClosedNode>
</ClosedNodes>
<SelectedItems>
<SelectedItem></SelectedItem>
<SelectedItem/>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000000ef000000010000000100000000000000000000000064ffffffff000000810000000000000001000000ef0000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem></CurrentItem>
<CurrentItem/>
</ItemView>
<ItemView guiview="File" >
<ClosedNodes>
@@ -40,7 +40,7 @@
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000000000000010000000000000000000000000000000000000130000000040101000100000000000000000000000064ffffffff000000810000000000000004000000420000000100000000000000240000000100000000000000660000000100000000000000640000000100000000</ViewHeaderState>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000000000000000100000000000000000000000000000000000003a3000000040101000100000000000000000000000064ffffffff000000810000000000000004000000420000000100000000000000240000000100000000000000660000000100000000000002d70000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem>LAN_IDE_CP.vhd</CurrentItem>
</ItemView>
@@ -52,7 +52,7 @@
<SelectedItems/>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000000000000000100000000000000000000000000000000000000ef000000010001000100000000000000000000000064ffffffff000000810000000000000001000000ef0000000100000000</ViewHeaderState>
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000000000000010000000000000000000000000000000000000109000000010001000100000000000000000000000064ffffffff000000810000000000000001000001090000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem>work</CurrentItem>
</ItemView>
Logic/LAN_IDE/iseconfig/LAN_IDE_CP.xreport
+2 -2
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@@ -1,9 +1,9 @@
<?xml version='1.0' encoding='UTF-8'?>
<report-views version="2.0" >
<header>
<DateModified>2016-12-28T00:49:57</DateModified>
<DateModified>2016-12-28T20:17:23</DateModified>
<ModuleName>LAN_IDE_CP</ModuleName>
<SummaryTimeStamp>2016-12-28T00:48:21</SummaryTimeStamp>
<SummaryTimeStamp>2016-12-28T02:12:48</SummaryTimeStamp>
<SavedFilePath>C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/iseconfig/LAN_IDE_CP.xreport</SavedFilePath>
<ImplementationReportsDirectory>C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE\</ImplementationReportsDirectory>
<DateInitialized>2016-12-13T22:08:29</DateInitialized>
Logic/LAN_IDE/log.txt
+895 -2041
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File diff suppressed because it is too large Load Diff
Logic/LAN_IDE/tmperr.err
+31
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@@ -0,0 +1,31 @@
WARNING:Cpld - Unable to retrieve the path to the iSE Project Repository. Will
use the default filename of 'LAN_IDE_CP.ise'.
INFO:Cpld - Inferring BUFG constraint for signal 'CLK_EXT' based upon the LOC
constraint 'P30'. It is recommended that you declare this BUFG explicitedly
in your design. Note that for certain device families the output of a BUFG
constraint can not drive a gated clock, and the BUFG constraint will be
ignored.
WARNING:Cpld:936 - The output buffer 'OVR_OBUF' is missing an input and will be
deleted.
WARNING:Cpld:936 - The output buffer 'MTACK_OBUF' is missing an input and will
be deleted.
WARNING:Cpld:1007 - Removing unused input(s) 'A<15>'. The input(s) are unused
after optimization. Please verify functionality via simulation.
WARNING:Cpld:1007 - Removing unused input(s) 'CLK_EXT'. The input(s) are unused
after optimization. Please verify functionality via simulation.
WARNING:Cpld:1007 - Removing unused input(s) 'DS0'. The input(s) are unused
after optimization. Please verify functionality via simulation.
WARNING:Cpld:1007 - Removing unused input(s) 'DS1'. The input(s) are unused
after optimization. Please verify functionality via simulation.
WARNING:Cpld:1007 - Removing unused input(s) 'FCS'. The input(s) are unused
after optimization. Please verify functionality via simulation.
WARNING:Cpld:1007 - Removing unused input(s) 'IDE_WAIT'. The input(s) are
unused after optimization. Please verify functionality via simulation.
WARNING:Cpld:1007 - Removing unused input(s) 'MTCR'. The input(s) are unused
after optimization. Please verify functionality via simulation.
WARNING:Cpld:1007 - Removing unused input(s) 'Z3'. The input(s) are unused
after optimization. Please verify functionality via simulation.
ERROR:Cpld:837 - Insufficient number of macrocells. The design needs at least
157 but only 144 left after allocating other resources.
ERROR:Cpld:868 - Cannot fit the design into any of the specified devices with
the selected implementation options.

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