3535 lines
137 KiB
Plaintext
3535 lines
137 KiB
Plaintext
MDF Database: version 1.0
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MDF_INFO | LAN_IDE_CP | XC95288XL-10-TQ144
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MACROCELL | 8 | 10 | Z3_DATA<0>
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ATTRIBUTES | 8685506 | 0
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INPUTS | 11 | DQ_SWAP | DQ<8>.PIN | DQ<0>.PIN | LAN_SM_RST | RW | FCS | $OpTx$FX_DC$50 | LAN_SM_FSM_FFd3 | LAN_SM_FSM_FFd4 | LAN_SM_FSM_FFd2 | LAN_SM_FSM_FFd1
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INPUTMC | 7 | 0 | 15 | 11 | 0 | 13 | 6 | 15 | 16 | 10 | 6 | 10 | 7 | 10 | 12
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INPUTP | 4 | 231 | 217 | 158 | 147
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EQ | 7 |
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A<8>.D = DQ_SWAP & DQ<8>.PIN
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# !DQ_SWAP & DQ<0>.PIN;
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A<8>.CLK = CLK_EXT; // GCK
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A<8>.AP = LAN_SM_RST;
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A<8>.OE = RW & !FCS & !$OpTx$FX_DC$50;
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A<8>.CE = LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 &
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!LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1;
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GLOBALS | 1 | 2 | CLK_EXT
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MACROCELL | 15 | 5 | Z3_DATA<10>
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ATTRIBUTES | 8685506 | 0
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INPUTS | 11 | DQ_SWAP | DQ<2>.PIN | DQ<10>.PIN | LAN_SM_RST | RW | FCS | $OpTx$FX_DC$50 | LAN_SM_FSM_FFd3 | LAN_SM_FSM_FFd4 | LAN_SM_FSM_FFd2 | LAN_SM_FSM_FFd1
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INPUTMC | 7 | 0 | 15 | 11 | 0 | 13 | 6 | 15 | 16 | 10 | 6 | 10 | 7 | 10 | 12
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INPUTP | 4 | 220 | 234 | 158 | 147
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EQ | 7 |
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A<18>.D = DQ_SWAP & DQ<2>.PIN
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# !DQ_SWAP & DQ<10>.PIN;
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A<18>.CLK = CLK_EXT; // GCK
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A<18>.AP = LAN_SM_RST;
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A<18>.OE = RW & !FCS & !$OpTx$FX_DC$50;
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A<18>.CE = LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 &
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!LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1;
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GLOBALS | 1 | 2 | CLK_EXT
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MACROCELL | 15 | 2 | Z3_DATA<11>
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ATTRIBUTES | 8685506 | 0
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INPUTS | 11 | DQ_SWAP | DQ<3>.PIN | DQ<11>.PIN | LAN_SM_RST | RW | FCS | $OpTx$FX_DC$50 | LAN_SM_FSM_FFd3 | LAN_SM_FSM_FFd4 | LAN_SM_FSM_FFd2 | LAN_SM_FSM_FFd1
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INPUTMC | 7 | 0 | 15 | 11 | 0 | 13 | 6 | 15 | 16 | 10 | 6 | 10 | 7 | 10 | 12
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INPUTP | 4 | 219 | 207 | 158 | 147
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EQ | 7 |
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A<19>.D = DQ_SWAP & DQ<3>.PIN
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# !DQ_SWAP & DQ<11>.PIN;
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A<19>.CLK = CLK_EXT; // GCK
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A<19>.AP = LAN_SM_RST;
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A<19>.OE = RW & !FCS & !$OpTx$FX_DC$50;
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A<19>.CE = LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 &
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!LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1;
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GLOBALS | 1 | 2 | CLK_EXT
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MACROCELL | 15 | 1 | Z3_DATA<12>
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ATTRIBUTES | 8685506 | 0
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INPUTS | 11 | DQ_SWAP | DQ<4>.PIN | DQ<12>.PIN | LAN_SM_RST | RW | FCS | $OpTx$FX_DC$50 | LAN_SM_FSM_FFd3 | LAN_SM_FSM_FFd4 | LAN_SM_FSM_FFd2 | LAN_SM_FSM_FFd1
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INPUTMC | 7 | 0 | 15 | 11 | 0 | 13 | 6 | 15 | 16 | 10 | 6 | 10 | 7 | 10 | 12
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INPUTP | 4 | 225 | 235 | 158 | 147
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EQ | 7 |
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A<20>.D = DQ_SWAP & DQ<4>.PIN
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# !DQ_SWAP & DQ<12>.PIN;
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A<20>.CLK = CLK_EXT; // GCK
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A<20>.AP = LAN_SM_RST;
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A<20>.OE = RW & !FCS & !$OpTx$FX_DC$50;
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A<20>.CE = LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 &
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!LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1;
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GLOBALS | 1 | 2 | CLK_EXT
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MACROCELL | 14 | 16 | Z3_DATA<13>
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ATTRIBUTES | 8685506 | 0
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INPUTS | 11 | DQ_SWAP | DQ<5>.PIN | DQ<13>.PIN | LAN_SM_RST | RW | FCS | $OpTx$FX_DC$50 | LAN_SM_FSM_FFd3 | LAN_SM_FSM_FFd4 | LAN_SM_FSM_FFd2 | LAN_SM_FSM_FFd1
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INPUTMC | 7 | 0 | 15 | 11 | 0 | 13 | 6 | 15 | 16 | 10 | 6 | 10 | 7 | 10 | 12
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INPUTP | 4 | 221 | 204 | 158 | 147
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EQ | 7 |
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A<21>.D = DQ_SWAP & DQ<5>.PIN
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# !DQ_SWAP & DQ<13>.PIN;
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A<21>.CLK = CLK_EXT; // GCK
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A<21>.AP = LAN_SM_RST;
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A<21>.OE = RW & !FCS & !$OpTx$FX_DC$50;
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A<21>.CE = LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 &
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!LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1;
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GLOBALS | 1 | 2 | CLK_EXT
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MACROCELL | 14 | 14 | Z3_DATA<14>
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ATTRIBUTES | 8685506 | 0
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INPUTS | 11 | DQ_SWAP | DQ<6>.PIN | DQ<14>.PIN | LAN_SM_RST | RW | FCS | $OpTx$FX_DC$50 | LAN_SM_FSM_FFd3 | LAN_SM_FSM_FFd4 | LAN_SM_FSM_FFd2 | LAN_SM_FSM_FFd1
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INPUTMC | 7 | 0 | 15 | 11 | 0 | 13 | 6 | 15 | 16 | 10 | 6 | 10 | 7 | 10 | 12
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INPUTP | 4 | 227 | 236 | 158 | 147
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EQ | 7 |
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A<22>.D = DQ_SWAP & DQ<6>.PIN
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# !DQ_SWAP & DQ<14>.PIN;
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A<22>.CLK = CLK_EXT; // GCK
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A<22>.AP = LAN_SM_RST;
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A<22>.OE = RW & !FCS & !$OpTx$FX_DC$50;
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A<22>.CE = LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 &
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!LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1;
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GLOBALS | 1 | 2 | CLK_EXT
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MACROCELL | 14 | 13 | Z3_DATA<15>
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ATTRIBUTES | 8685506 | 0
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INPUTS | 11 | DQ_SWAP | DQ<7>.PIN | DQ<15>.PIN | LAN_SM_RST | RW | FCS | $OpTx$FX_DC$50 | LAN_SM_FSM_FFd3 | LAN_SM_FSM_FFd4 | LAN_SM_FSM_FFd2 | LAN_SM_FSM_FFd1
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INPUTMC | 7 | 0 | 15 | 11 | 0 | 13 | 6 | 15 | 16 | 10 | 6 | 10 | 7 | 10 | 12
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INPUTP | 4 | 226 | 202 | 158 | 147
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EQ | 7 |
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A<23>.D = DQ_SWAP & DQ<7>.PIN
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# !DQ_SWAP & DQ<15>.PIN;
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A<23>.CLK = CLK_EXT; // GCK
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A<23>.AP = LAN_SM_RST;
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A<23>.OE = RW & !FCS & !$OpTx$FX_DC$50;
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A<23>.CE = LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 &
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!LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1;
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GLOBALS | 1 | 2 | CLK_EXT
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MACROCELL | 8 | 13 | Z3_DATA<1>
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ATTRIBUTES | 8685506 | 0
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INPUTS | 11 | DQ_SWAP | DQ<9>.PIN | DQ<1>.PIN | LAN_SM_RST | RW | FCS | $OpTx$FX_DC$50 | LAN_SM_FSM_FFd3 | LAN_SM_FSM_FFd4 | LAN_SM_FSM_FFd2 | LAN_SM_FSM_FFd1
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INPUTMC | 7 | 0 | 15 | 11 | 0 | 13 | 6 | 15 | 16 | 10 | 6 | 10 | 7 | 10 | 12
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INPUTP | 4 | 209 | 216 | 158 | 147
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EQ | 7 |
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A<9>.D = DQ_SWAP & DQ<9>.PIN
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# !DQ_SWAP & DQ<1>.PIN;
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A<9>.CLK = CLK_EXT; // GCK
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A<9>.AP = LAN_SM_RST;
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A<9>.OE = RW & !FCS & !$OpTx$FX_DC$50;
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A<9>.CE = LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 &
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!LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1;
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GLOBALS | 1 | 2 | CLK_EXT
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MACROCELL | 8 | 16 | Z3_DATA<2>
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ATTRIBUTES | 8685506 | 0
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INPUTS | 11 | DQ_SWAP | DQ<2>.PIN | DQ<10>.PIN | LAN_SM_RST | RW | FCS | $OpTx$FX_DC$50 | LAN_SM_FSM_FFd3 | LAN_SM_FSM_FFd4 | LAN_SM_FSM_FFd2 | LAN_SM_FSM_FFd1
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INPUTMC | 7 | 0 | 15 | 11 | 0 | 13 | 6 | 15 | 16 | 10 | 6 | 10 | 7 | 10 | 12
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INPUTP | 4 | 220 | 234 | 158 | 147
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EQ | 7 |
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A<10>.D = DQ_SWAP & DQ<10>.PIN
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# !DQ_SWAP & DQ<2>.PIN;
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A<10>.CLK = CLK_EXT; // GCK
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A<10>.AP = LAN_SM_RST;
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A<10>.OE = RW & !FCS & !$OpTx$FX_DC$50;
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A<10>.CE = LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 &
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!LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1;
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GLOBALS | 1 | 2 | CLK_EXT
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MACROCELL | 10 | 2 | Z3_DATA<3>
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ATTRIBUTES | 8685506 | 0
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INPUTS | 11 | DQ_SWAP | DQ<3>.PIN | DQ<11>.PIN | LAN_SM_RST | RW | FCS | $OpTx$FX_DC$50 | LAN_SM_FSM_FFd3 | LAN_SM_FSM_FFd4 | LAN_SM_FSM_FFd2 | LAN_SM_FSM_FFd1
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INPUTMC | 7 | 0 | 15 | 11 | 0 | 13 | 6 | 15 | 16 | 10 | 6 | 10 | 7 | 10 | 12
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INPUTP | 4 | 219 | 207 | 158 | 147
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EQ | 7 |
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A<11>.D = DQ_SWAP & DQ<11>.PIN
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# !DQ_SWAP & DQ<3>.PIN;
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A<11>.CLK = CLK_EXT; // GCK
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A<11>.AP = LAN_SM_RST;
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A<11>.OE = RW & !FCS & !$OpTx$FX_DC$50;
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A<11>.CE = LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 &
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!LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1;
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GLOBALS | 1 | 2 | CLK_EXT
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MACROCELL | 10 | 4 | Z3_DATA<4>
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ATTRIBUTES | 8685506 | 0
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INPUTS | 11 | DQ_SWAP | DQ<4>.PIN | DQ<12>.PIN | LAN_SM_RST | RW | FCS | $OpTx$FX_DC$50 | LAN_SM_FSM_FFd3 | LAN_SM_FSM_FFd4 | LAN_SM_FSM_FFd2 | LAN_SM_FSM_FFd1
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INPUTMC | 7 | 0 | 15 | 11 | 0 | 13 | 6 | 15 | 16 | 10 | 6 | 10 | 7 | 10 | 12
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INPUTP | 4 | 225 | 235 | 158 | 147
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EQ | 7 |
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A<12>.D = DQ_SWAP & DQ<12>.PIN
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# !DQ_SWAP & DQ<4>.PIN;
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A<12>.CLK = CLK_EXT; // GCK
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A<12>.AP = LAN_SM_RST;
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A<12>.OE = RW & !FCS & !$OpTx$FX_DC$50;
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A<12>.CE = LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 &
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!LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1;
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GLOBALS | 1 | 2 | CLK_EXT
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MACROCELL | 10 | 9 | Z3_DATA<5>
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ATTRIBUTES | 8685506 | 0
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INPUTS | 11 | DQ_SWAP | DQ<5>.PIN | DQ<13>.PIN | LAN_SM_RST | RW | FCS | $OpTx$FX_DC$50 | LAN_SM_FSM_FFd3 | LAN_SM_FSM_FFd4 | LAN_SM_FSM_FFd2 | LAN_SM_FSM_FFd1
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INPUTMC | 7 | 0 | 15 | 11 | 0 | 13 | 6 | 15 | 16 | 10 | 6 | 10 | 7 | 10 | 12
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INPUTP | 4 | 221 | 204 | 158 | 147
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EQ | 7 |
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A<13>.D = DQ_SWAP & DQ<13>.PIN
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# !DQ_SWAP & DQ<5>.PIN;
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A<13>.CLK = CLK_EXT; // GCK
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A<13>.AP = LAN_SM_RST;
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A<13>.OE = RW & !FCS & !$OpTx$FX_DC$50;
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A<13>.CE = LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 &
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!LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1;
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GLOBALS | 1 | 2 | CLK_EXT
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MACROCELL | 10 | 10 | Z3_DATA<6>
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ATTRIBUTES | 8685506 | 0
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INPUTS | 11 | DQ_SWAP | DQ<6>.PIN | DQ<14>.PIN | LAN_SM_RST | RW | FCS | $OpTx$FX_DC$50 | LAN_SM_FSM_FFd3 | LAN_SM_FSM_FFd4 | LAN_SM_FSM_FFd2 | LAN_SM_FSM_FFd1
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INPUTMC | 7 | 0 | 15 | 11 | 0 | 13 | 6 | 15 | 16 | 10 | 6 | 10 | 7 | 10 | 12
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INPUTP | 4 | 227 | 236 | 158 | 147
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EQ | 7 |
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A<14>.D = DQ_SWAP & DQ<14>.PIN
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# !DQ_SWAP & DQ<6>.PIN;
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A<14>.CLK = CLK_EXT; // GCK
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A<14>.AP = LAN_SM_RST;
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A<14>.OE = RW & !FCS & !$OpTx$FX_DC$50;
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A<14>.CE = LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 &
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!LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1;
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GLOBALS | 1 | 2 | CLK_EXT
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MACROCELL | 12 | 7 | Z3_DATA<7>
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ATTRIBUTES | 8685506 | 0
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INPUTS | 11 | DQ_SWAP | DQ<7>.PIN | DQ<15>.PIN | LAN_SM_RST | RW | FCS | $OpTx$FX_DC$50 | LAN_SM_FSM_FFd3 | LAN_SM_FSM_FFd4 | LAN_SM_FSM_FFd2 | LAN_SM_FSM_FFd1
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INPUTMC | 7 | 0 | 15 | 11 | 0 | 13 | 6 | 15 | 16 | 10 | 6 | 10 | 7 | 10 | 12
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INPUTP | 4 | 226 | 202 | 158 | 147
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EQ | 7 |
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A<15>.D = DQ_SWAP & DQ<15>.PIN
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# !DQ_SWAP & DQ<7>.PIN;
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A<15>.CLK = CLK_EXT; // GCK
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A<15>.AP = LAN_SM_RST;
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A<15>.OE = RW & !FCS & !$OpTx$FX_DC$50;
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A<15>.CE = LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 &
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!LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1;
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GLOBALS | 1 | 2 | CLK_EXT
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MACROCELL | 15 | 10 | Z3_DATA<8>
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ATTRIBUTES | 8685506 | 0
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INPUTS | 11 | DQ_SWAP | DQ<8>.PIN | DQ<0>.PIN | LAN_SM_RST | RW | FCS | $OpTx$FX_DC$50 | LAN_SM_FSM_FFd3 | LAN_SM_FSM_FFd4 | LAN_SM_FSM_FFd2 | LAN_SM_FSM_FFd1
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INPUTMC | 7 | 0 | 15 | 11 | 0 | 13 | 6 | 15 | 16 | 10 | 6 | 10 | 7 | 10 | 12
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INPUTP | 4 | 231 | 217 | 158 | 147
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EQ | 7 |
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A<16>.D = DQ_SWAP & DQ<0>.PIN
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# !DQ_SWAP & DQ<8>.PIN;
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A<16>.CLK = CLK_EXT; // GCK
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A<16>.AP = LAN_SM_RST;
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A<16>.OE = RW & !FCS & !$OpTx$FX_DC$50;
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A<16>.CE = LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 &
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!LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1;
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GLOBALS | 1 | 2 | CLK_EXT
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MACROCELL | 15 | 7 | Z3_DATA<9>
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ATTRIBUTES | 8685506 | 0
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INPUTS | 11 | DQ_SWAP | DQ<9>.PIN | DQ<1>.PIN | LAN_SM_RST | RW | FCS | $OpTx$FX_DC$50 | LAN_SM_FSM_FFd3 | LAN_SM_FSM_FFd4 | LAN_SM_FSM_FFd2 | LAN_SM_FSM_FFd1
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INPUTMC | 7 | 0 | 15 | 11 | 0 | 13 | 6 | 15 | 16 | 10 | 6 | 10 | 7 | 10 | 12
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INPUTP | 4 | 209 | 216 | 158 | 147
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EQ | 7 |
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A<17>.D = DQ_SWAP & DQ<1>.PIN
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# !DQ_SWAP & DQ<9>.PIN;
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A<17>.CLK = CLK_EXT; // GCK
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A<17>.AP = LAN_SM_RST;
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A<17>.OE = RW & !FCS & !$OpTx$FX_DC$50;
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A<17>.CE = LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 &
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!LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1;
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GLOBALS | 1 | 2 | CLK_EXT
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MACROCELL | 9 | 15 | AUTO_CONFIG_Z2_DONE<0>
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ATTRIBUTES | 8520560 | 0
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OUTPUTMC | 11 | 9 | 15 | 3 | 8 | 3 | 10 | 9 | 17 | 3 | 13 | 3 | 1 | 13 | 10 | 3 | 2 | 3 | 12 | 3 | 17 | 3 | 16
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INPUTS | 5 | AUTO_CONFIG_Z2_DONE<0> | AUTO_CONFIG_Z2_DONE_CYCLE<0> | SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF | RESET | AS
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INPUTMC | 3 | 9 | 15 | 3 | 8 | 5 | 11
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INPUTP | 2 | 263 | 152
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EQ | 5 |
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!AUTO_CONFIG_Z2_DONE<0>.D = !AUTO_CONFIG_Z2_DONE<0> &
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!AUTO_CONFIG_Z2_DONE_CYCLE<0>;
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AUTO_CONFIG_Z2_DONE<0>.CLK = SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF;
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AUTO_CONFIG_Z2_DONE<0>.AR = !RESET;
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AUTO_CONFIG_Z2_DONE<0>.CE = AS;
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MACROCELL | 9 | 14 | AUTO_CONFIG_Z2_DONE<1>
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ATTRIBUTES | 8520560 | 0
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OUTPUTMC | 6 | 9 | 14 | 3 | 10 | 9 | 17 | 3 | 17 | 13 | 10 | 3 | 1
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INPUTS | 5 | AUTO_CONFIG_Z2_DONE<1> | AUTO_CONFIG_Z2_DONE_CYCLE<1> | SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF | RESET | AS
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INPUTMC | 3 | 9 | 14 | 3 | 10 | 5 | 11
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INPUTP | 2 | 263 | 152
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EQ | 5 |
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!AUTO_CONFIG_Z2_DONE<1>.D = !AUTO_CONFIG_Z2_DONE<1> &
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!AUTO_CONFIG_Z2_DONE_CYCLE<1>;
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AUTO_CONFIG_Z2_DONE<1>.CLK = SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF;
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AUTO_CONFIG_Z2_DONE<1>.AR = !RESET;
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AUTO_CONFIG_Z2_DONE<1>.CE = AS;
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MACROCELL | 3 | 8 | AUTO_CONFIG_Z2_DONE_CYCLE<0>
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ATTRIBUTES | 4326192 | 0
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OUTPUTMC | 2 | 9 | 15 | 3 | 8
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INPUTS | 11 | AUTO_CONFIG_Z2_DONE<0> | AUTO_CONFIG_Z2_DONE_CYCLE<0> | RW | A<5> | A<4> | A<1> | A<6> | A<3> | $OpTx$FX_DC$16 | SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF | RESET
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INPUTMC | 4 | 9 | 15 | 3 | 8 | 0 | 0 | 5 | 11
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INPUTP | 7 | 158 | 91 | 97 | 107 | 98 | 99 | 263
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EQ | 5 |
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AUTO_CONFIG_Z2_DONE_CYCLE<0>.T = !AUTO_CONFIG_Z2_DONE<0> &
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!AUTO_CONFIG_Z2_DONE_CYCLE<0> & !RW & !A<5> & !A<4> & !A<1> & A<6> & A<3> &
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$OpTx$FX_DC$16;
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AUTO_CONFIG_Z2_DONE_CYCLE<0>.CLK = SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF;
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AUTO_CONFIG_Z2_DONE_CYCLE<0>.AR = !RESET;
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MACROCELL | 3 | 10 | AUTO_CONFIG_Z2_DONE_CYCLE<1>
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ATTRIBUTES | 4326192 | 0
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OUTPUTMC | 2 | 9 | 14 | 3 | 10
|
|
INPUTS | 13 | AUTO_CONFIG_Z2_DONE<0> | AUTO_CONFIG_Z2_DONE_CYCLE<1> | RW | A<5> | A<4> | A<1> | A<2> | A<6> | A<3> | $OpTx$FX_DC$16 | AUTO_CONFIG_Z2_DONE<1> | SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF | RESET
|
|
INPUTMC | 5 | 9 | 15 | 3 | 10 | 0 | 0 | 9 | 14 | 5 | 11
|
|
INPUTP | 8 | 158 | 91 | 97 | 107 | 101 | 98 | 99 | 263
|
|
EQ | 8 |
|
|
AUTO_CONFIG_Z2_DONE_CYCLE<1>.T = AUTO_CONFIG_Z2_DONE<0> & !AUTO_CONFIG_Z2_DONE<1> &
|
|
!AUTO_CONFIG_Z2_DONE_CYCLE<1> & !RW & !A<5> & !A<4> & !A<1> & A<6> & A<3> &
|
|
$OpTx$FX_DC$16
|
|
# AUTO_CONFIG_Z2_DONE<0> &
|
|
!AUTO_CONFIG_Z2_DONE_CYCLE<1> & !RW & !A<5> & !A<4> & !A<1> & A<2> & A<6> & A<3> &
|
|
$OpTx$FX_DC$16;
|
|
AUTO_CONFIG_Z2_DONE_CYCLE<1>.CLK = SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF;
|
|
AUTO_CONFIG_Z2_DONE_CYCLE<1>.AR = !RESET;
|
|
|
|
MACROCELL | 0 | 10 | IDE_ENABLE
|
|
ATTRIBUTES | 8520496 | 0
|
|
OUTPUTMC | 3 | 0 | 10 | 0 | 16 | 4 | 4
|
|
INPUTS | 5 | RW | BUF_IDE_ACCESS | IDE_ENABLE | AS | RESET
|
|
INPUTMC | 2 | 7 | 17 | 0 | 10
|
|
INPUTP | 3 | 158 | 152 | 263
|
|
EQ | 4 |
|
|
IDE_ENABLE.D = !RW & !BUF_IDE_ACCESS
|
|
# IDE_ENABLE & BUF_IDE_ACCESS;
|
|
IDE_ENABLE.CLK = !AS;
|
|
IDE_ENABLE.AR = !RESET;
|
|
|
|
MACROCELL | 12 | 11 | AUTO_CONFIG_DONE
|
|
ATTRIBUTES | 8553296 | 0
|
|
OUTPUTMC | 2 | 9 | 12 | 13 | 10
|
|
INPUTS | 3 | AUTO_CONFIG_DONE_CYCLE | RESET | FCS
|
|
INPUTMC | 1 | 12 | 10
|
|
INPUTP | 2 | 263 | 147
|
|
EQ | 4 |
|
|
AUTO_CONFIG_DONE.D = AUTO_CONFIG_DONE_CYCLE;
|
|
AUTO_CONFIG_DONE.CLK = CLK_EXT; // GCK
|
|
AUTO_CONFIG_DONE.AR = !RESET;
|
|
AUTO_CONFIG_DONE.CE = FCS;
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 12 | 10 | AUTO_CONFIG_DONE_CYCLE
|
|
ATTRIBUTES | 4358992 | 0
|
|
OUTPUTMC | 2 | 12 | 11 | 12 | 10
|
|
INPUTS | 12 | RW | AUTO_CONFIG_DONE_CYCLE | Z3_ADR<2> | Z3_ADR_0 | Z3_ADR<6> | Z3_ADR<3> | Z3_ADR<4> | Z3_ADR<5> | RESET | UDS | FCS | AUTOCONFIG_Z3_ACCESS
|
|
INPUTMC | 8 | 12 | 10 | 13 | 16 | 13 | 8 | 13 | 9 | 13 | 15 | 13 | 12 | 13 | 11 | 9 | 12
|
|
INPUTP | 4 | 158 | 263 | 155 | 147
|
|
EQ | 5 |
|
|
AUTO_CONFIG_DONE_CYCLE.T = !RW & !AUTO_CONFIG_DONE_CYCLE & !Z3_ADR<2> &
|
|
Z3_ADR_0 & !Z3_ADR<6> & !Z3_ADR<3> & Z3_ADR<4> & !Z3_ADR<5>;
|
|
AUTO_CONFIG_DONE_CYCLE.CLK = CLK_EXT; // GCK
|
|
AUTO_CONFIG_DONE_CYCLE.AR = !RESET;
|
|
AUTO_CONFIG_DONE_CYCLE.CE = !UDS & !FCS & AUTOCONFIG_Z3_ACCESS;
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 6 | 16 | CP_BASEADR<0>
|
|
ATTRIBUTES | 8520608 | 0
|
|
OUTPUTMC | 3 | 6 | 16 | 6 | 0 | 6 | 17
|
|
INPUTS | 7 | D<8>.PIN | $OpTx$FX_DC$34 | CP_BASEADR<0> | SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF | RESET | CP_BASEADR<7> | A<23>.PIN
|
|
INPUTMC | 4 | 3 | 2 | 6 | 16 | 5 | 11 | 7 | 15
|
|
INPUTP | 3 | 32 | 263 | 161
|
|
EXPORTS | 1 | 6 | 17
|
|
EQ | 5 |
|
|
CP_BASEADR<0>.D = D<8>.PIN & $OpTx$FX_DC$34
|
|
# CP_BASEADR<0> & !$OpTx$FX_DC$34;
|
|
CP_BASEADR<0>.CLK = SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF;
|
|
CP_BASEADR<0>.AP = !RESET;
|
|
CP_BASEADR<0>.EXP = !CP_BASEADR<7> & A<23>.PIN
|
|
|
|
MACROCELL | 6 | 15 | CP_BASEADR<1>
|
|
ATTRIBUTES | 8520608 | 0
|
|
OUTPUTMC | 2 | 6 | 15 | 6 | 17
|
|
INPUTS | 5 | D<9>.PIN | $OpTx$FX_DC$34 | CP_BASEADR<1> | SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF | RESET
|
|
INPUTMC | 3 | 3 | 2 | 6 | 15 | 5 | 11
|
|
INPUTP | 2 | 73 | 263
|
|
EQ | 4 |
|
|
CP_BASEADR<1>.D = D<9>.PIN & $OpTx$FX_DC$34
|
|
# CP_BASEADR<1> & !$OpTx$FX_DC$34;
|
|
CP_BASEADR<1>.CLK = SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF;
|
|
CP_BASEADR<1>.AP = !RESET;
|
|
|
|
MACROCELL | 6 | 14 | CP_BASEADR<2>
|
|
ATTRIBUTES | 8520608 | 0
|
|
OUTPUTMC | 2 | 6 | 14 | 6 | 17
|
|
INPUTS | 5 | D<10>.PIN | $OpTx$FX_DC$34 | CP_BASEADR<2> | SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF | RESET
|
|
INPUTMC | 3 | 3 | 2 | 6 | 14 | 5 | 11
|
|
INPUTP | 2 | 74 | 263
|
|
EQ | 4 |
|
|
CP_BASEADR<2>.D = D<10>.PIN & $OpTx$FX_DC$34
|
|
# CP_BASEADR<2> & !$OpTx$FX_DC$34;
|
|
CP_BASEADR<2>.CLK = SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF;
|
|
CP_BASEADR<2>.AP = !RESET;
|
|
|
|
MACROCELL | 6 | 13 | CP_BASEADR<3>
|
|
ATTRIBUTES | 8520608 | 0
|
|
OUTPUTMC | 3 | 6 | 13 | 6 | 1 | 6 | 17
|
|
INPUTS | 5 | D<11>.PIN | $OpTx$FX_DC$34 | CP_BASEADR<3> | SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF | RESET
|
|
INPUTMC | 3 | 3 | 2 | 6 | 13 | 5 | 11
|
|
INPUTP | 2 | 77 | 263
|
|
EQ | 4 |
|
|
CP_BASEADR<3>.D = D<11>.PIN & $OpTx$FX_DC$34
|
|
# CP_BASEADR<3> & !$OpTx$FX_DC$34;
|
|
CP_BASEADR<3>.CLK = SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF;
|
|
CP_BASEADR<3>.AP = !RESET;
|
|
|
|
MACROCELL | 6 | 12 | CP_BASEADR<4>
|
|
ATTRIBUTES | 8520608 | 0
|
|
OUTPUTMC | 2 | 6 | 12 | 6 | 1
|
|
INPUTS | 5 | D<12>.PIN | $OpTx$FX_DC$34 | CP_BASEADR<4> | SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF | RESET
|
|
INPUTMC | 3 | 3 | 2 | 6 | 12 | 5 | 11
|
|
INPUTP | 2 | 78 | 263
|
|
EQ | 4 |
|
|
CP_BASEADR<4>.D = D<12>.PIN & $OpTx$FX_DC$34
|
|
# CP_BASEADR<4> & !$OpTx$FX_DC$34;
|
|
CP_BASEADR<4>.CLK = SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF;
|
|
CP_BASEADR<4>.AP = !RESET;
|
|
|
|
MACROCELL | 6 | 10 | CP_BASEADR<5>
|
|
ATTRIBUTES | 8520608 | 0
|
|
OUTPUTMC | 2 | 6 | 10 | 6 | 1
|
|
INPUTS | 5 | D<13>.PIN | $OpTx$FX_DC$34 | CP_BASEADR<5> | SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF | RESET
|
|
INPUTMC | 3 | 3 | 2 | 6 | 10 | 5 | 11
|
|
INPUTP | 2 | 80 | 263
|
|
EQ | 4 |
|
|
CP_BASEADR<5>.D = D<13>.PIN & $OpTx$FX_DC$34
|
|
# CP_BASEADR<5> & !$OpTx$FX_DC$34;
|
|
CP_BASEADR<5>.CLK = SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF;
|
|
CP_BASEADR<5>.AP = !RESET;
|
|
|
|
MACROCELL | 3 | 9 | CP_BASEADR<6>
|
|
ATTRIBUTES | 8520608 | 0
|
|
OUTPUTMC | 2 | 3 | 9 | 6 | 2
|
|
INPUTS | 5 | D<14>.PIN | $OpTx$FX_DC$34 | CP_BASEADR<6> | SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF | RESET
|
|
INPUTMC | 3 | 3 | 2 | 3 | 9 | 5 | 11
|
|
INPUTP | 2 | 81 | 263
|
|
EQ | 4 |
|
|
CP_BASEADR<6>.D = D<14>.PIN & $OpTx$FX_DC$34
|
|
# CP_BASEADR<6> & !$OpTx$FX_DC$34;
|
|
CP_BASEADR<6>.CLK = SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF;
|
|
CP_BASEADR<6>.AP = !RESET;
|
|
|
|
MACROCELL | 7 | 15 | CP_BASEADR<7>
|
|
ATTRIBUTES | 8520608 | 0
|
|
OUTPUTMC | 4 | 7 | 14 | 6 | 2 | 6 | 16 | 7 | 16
|
|
INPUTS | 7 | IDE_BASEADR<6> | A<22>.PIN | IDE_BASEADR<7> | SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF | RESET | A<23>.PIN | IDE_BASEADR<0>.EXP
|
|
INPUTMC | 4 | 7 | 6 | 7 | 5 | 5 | 11 | 7 | 14
|
|
INPUTP | 3 | 162 | 263 | 161
|
|
EXPORTS | 1 | 7 | 16
|
|
IMPORTS | 1 | 7 | 14
|
|
EQ | 8 |
|
|
CP_BASEADR<7>.D = ;Imported pterms FB8_15
|
|
D<15>.PIN & $OpTx$FX_DC$34
|
|
# CP_BASEADR<7> & !$OpTx$FX_DC$34;
|
|
CP_BASEADR<7>.CLK = SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF;
|
|
CP_BASEADR<7>.AP = !RESET;
|
|
CP_BASEADR<7>.EXP = IDE_BASEADR<6> & !A<22>.PIN
|
|
# !IDE_BASEADR<6> & A<22>.PIN
|
|
# IDE_BASEADR<7> & !A<23>.PIN
|
|
|
|
MACROCELL | 7 | 14 | IDE_BASEADR<0>
|
|
ATTRIBUTES | 8520608 | 0
|
|
OUTPUTMC | 3 | 7 | 13 | 7 | 17 | 7 | 15
|
|
INPUTS | 8 | D<8>.PIN | $OpTx$FX_DC$35 | D<15>.PIN | SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF | RESET | $OpTx$FX_DC$34 | CP_BASEADR<7> | IDE_BASEADR<1>.EXP
|
|
INPUTMC | 5 | 3 | 17 | 5 | 11 | 3 | 2 | 7 | 15 | 7 | 13
|
|
INPUTP | 3 | 32 | 89 | 263
|
|
EXPORTS | 1 | 7 | 15
|
|
IMPORTS | 1 | 7 | 13
|
|
EQ | 7 |
|
|
IDE_BASEADR<0>.D = D<8>.PIN & $OpTx$FX_DC$35
|
|
;Imported pterms FB8_14
|
|
# IDE_BASEADR<0> & !$OpTx$FX_DC$35;
|
|
IDE_BASEADR<0>.CLK = SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF;
|
|
IDE_BASEADR<0>.AP = !RESET;
|
|
IDE_BASEADR<0>.EXP = D<15>.PIN & $OpTx$FX_DC$34
|
|
# CP_BASEADR<7> & !$OpTx$FX_DC$34
|
|
|
|
MACROCELL | 7 | 13 | IDE_BASEADR<1>
|
|
ATTRIBUTES | 8520608 | 0
|
|
OUTPUTMC | 3 | 7 | 13 | 7 | 17 | 7 | 14
|
|
INPUTS | 6 | D<9>.PIN | $OpTx$FX_DC$35 | IDE_BASEADR<1> | SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF | RESET | IDE_BASEADR<0>
|
|
INPUTMC | 4 | 3 | 17 | 7 | 13 | 5 | 11 | 7 | 14
|
|
INPUTP | 2 | 73 | 263
|
|
EXPORTS | 1 | 7 | 14
|
|
EQ | 5 |
|
|
IDE_BASEADR<1>.D = D<9>.PIN & $OpTx$FX_DC$35
|
|
# IDE_BASEADR<1> & !$OpTx$FX_DC$35;
|
|
IDE_BASEADR<1>.CLK = SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF;
|
|
IDE_BASEADR<1>.AP = !RESET;
|
|
IDE_BASEADR<1>.EXP = IDE_BASEADR<0> & !$OpTx$FX_DC$35
|
|
|
|
MACROCELL | 7 | 12 | IDE_BASEADR<2>
|
|
ATTRIBUTES | 8520608 | 0
|
|
OUTPUTMC | 2 | 7 | 12 | 7 | 16
|
|
INPUTS | 5 | D<10>.PIN | $OpTx$FX_DC$35 | IDE_BASEADR<2> | SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF | RESET
|
|
INPUTMC | 3 | 3 | 17 | 7 | 12 | 5 | 11
|
|
INPUTP | 2 | 74 | 263
|
|
EQ | 4 |
|
|
IDE_BASEADR<2>.D = D<10>.PIN & $OpTx$FX_DC$35
|
|
# IDE_BASEADR<2> & !$OpTx$FX_DC$35;
|
|
IDE_BASEADR<2>.CLK = SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF;
|
|
IDE_BASEADR<2>.AP = !RESET;
|
|
|
|
MACROCELL | 7 | 11 | IDE_BASEADR<3>
|
|
ATTRIBUTES | 8520608 | 0
|
|
OUTPUTMC | 2 | 7 | 11 | 7 | 16
|
|
INPUTS | 5 | D<11>.PIN | $OpTx$FX_DC$35 | IDE_BASEADR<3> | SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF | RESET
|
|
INPUTMC | 3 | 3 | 17 | 7 | 11 | 5 | 11
|
|
INPUTP | 2 | 77 | 263
|
|
EQ | 4 |
|
|
IDE_BASEADR<3>.D = D<11>.PIN & $OpTx$FX_DC$35
|
|
# IDE_BASEADR<3> & !$OpTx$FX_DC$35;
|
|
IDE_BASEADR<3>.CLK = SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF;
|
|
IDE_BASEADR<3>.AP = !RESET;
|
|
|
|
MACROCELL | 7 | 10 | IDE_BASEADR<4>
|
|
ATTRIBUTES | 8520608 | 0
|
|
OUTPUTMC | 3 | 7 | 10 | 7 | 16 | 7 | 0
|
|
INPUTS | 5 | D<12>.PIN | $OpTx$FX_DC$35 | IDE_BASEADR<4> | SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF | RESET
|
|
INPUTMC | 3 | 3 | 17 | 7 | 10 | 5 | 11
|
|
INPUTP | 2 | 78 | 263
|
|
EQ | 4 |
|
|
IDE_BASEADR<4>.D = D<12>.PIN & $OpTx$FX_DC$35
|
|
# IDE_BASEADR<4> & !$OpTx$FX_DC$35;
|
|
IDE_BASEADR<4>.CLK = SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF;
|
|
IDE_BASEADR<4>.AP = !RESET;
|
|
|
|
MACROCELL | 7 | 8 | IDE_BASEADR<5>
|
|
ATTRIBUTES | 8520608 | 0
|
|
OUTPUTMC | 2 | 7 | 8 | 7 | 0
|
|
INPUTS | 5 | D<13>.PIN | $OpTx$FX_DC$35 | IDE_BASEADR<5> | SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF | RESET
|
|
INPUTMC | 3 | 3 | 17 | 7 | 8 | 5 | 11
|
|
INPUTP | 2 | 80 | 263
|
|
EQ | 4 |
|
|
IDE_BASEADR<5>.D = D<13>.PIN & $OpTx$FX_DC$35
|
|
# IDE_BASEADR<5> & !$OpTx$FX_DC$35;
|
|
IDE_BASEADR<5>.CLK = SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF;
|
|
IDE_BASEADR<5>.AP = !RESET;
|
|
|
|
MACROCELL | 7 | 6 | IDE_BASEADR<6>
|
|
ATTRIBUTES | 8520608 | 0
|
|
OUTPUTMC | 2 | 7 | 6 | 7 | 15
|
|
INPUTS | 5 | D<14>.PIN | $OpTx$FX_DC$35 | IDE_BASEADR<6> | SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF | RESET
|
|
INPUTMC | 3 | 3 | 17 | 7 | 6 | 5 | 11
|
|
INPUTP | 2 | 81 | 263
|
|
EQ | 4 |
|
|
IDE_BASEADR<6>.D = D<14>.PIN & $OpTx$FX_DC$35
|
|
# IDE_BASEADR<6> & !$OpTx$FX_DC$35;
|
|
IDE_BASEADR<6>.CLK = SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF;
|
|
IDE_BASEADR<6>.AP = !RESET;
|
|
|
|
MACROCELL | 7 | 5 | IDE_BASEADR<7>
|
|
ATTRIBUTES | 8520608 | 0
|
|
OUTPUTMC | 3 | 7 | 5 | 7 | 15 | 7 | 0
|
|
INPUTS | 5 | D<15>.PIN | $OpTx$FX_DC$35 | IDE_BASEADR<7> | SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF | RESET
|
|
INPUTMC | 3 | 3 | 17 | 7 | 5 | 5 | 11
|
|
INPUTP | 2 | 89 | 263
|
|
EQ | 4 |
|
|
IDE_BASEADR<7>.D = D<15>.PIN & $OpTx$FX_DC$35
|
|
# IDE_BASEADR<7> & !$OpTx$FX_DC$35;
|
|
IDE_BASEADR<7>.CLK = SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF;
|
|
IDE_BASEADR<7>.AP = !RESET;
|
|
|
|
MACROCELL | 1 | 17 | LAN_BASEADR<0>
|
|
ATTRIBUTES | 8553408 | 0
|
|
OUTPUTMC | 1 | 13 | 0
|
|
INPUTS | 13 | D<0>.PIN | RESET | UDS | RW | FCS | Z3_ADR<2> | Z3_ADR_1 | Z3_ADR_0 | Z3_ADR<6> | AUTOCONFIG_Z3_ACCESS | Z3_ADR<3> | Z3_ADR<4> | Z3_ADR<5>
|
|
INPUTMC | 8 | 13 | 16 | 13 | 7 | 13 | 8 | 13 | 9 | 9 | 12 | 13 | 15 | 13 | 12 | 13 | 11
|
|
INPUTP | 5 | 4 | 263 | 155 | 158 | 147
|
|
EQ | 6 |
|
|
LAN_BASEADR<0>.D = D<0>.PIN;
|
|
LAN_BASEADR<0>.CLK = CLK_EXT; // GCK
|
|
LAN_BASEADR<0>.AP = !RESET;
|
|
LAN_BASEADR<0>.CE = !UDS & !RW & !FCS & !Z3_ADR<2> & !Z3_ADR_1 &
|
|
Z3_ADR_0 & !Z3_ADR<6> & AUTOCONFIG_Z3_ACCESS & !Z3_ADR<3> &
|
|
Z3_ADR<4> & !Z3_ADR<5>;
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 1 | 15 | LAN_BASEADR<10>
|
|
ATTRIBUTES | 8553408 | 0
|
|
OUTPUTMC | 1 | 5 | 17
|
|
INPUTS | 13 | D<10>.PIN | RESET | UDS | RW | FCS | Z3_ADR<2> | Z3_ADR_1 | Z3_ADR_0 | Z3_ADR<6> | AUTOCONFIG_Z3_ACCESS | Z3_ADR<3> | Z3_ADR<4> | Z3_ADR<5>
|
|
INPUTMC | 8 | 13 | 16 | 13 | 7 | 13 | 8 | 13 | 9 | 9 | 12 | 13 | 15 | 13 | 12 | 13 | 11
|
|
INPUTP | 5 | 74 | 263 | 155 | 158 | 147
|
|
EQ | 6 |
|
|
LAN_BASEADR<10>.D = D<10>.PIN;
|
|
LAN_BASEADR<10>.CLK = CLK_EXT; // GCK
|
|
LAN_BASEADR<10>.AP = !RESET;
|
|
LAN_BASEADR<10>.CE = !UDS & !RW & !FCS & !Z3_ADR<2> & !Z3_ADR_1 &
|
|
Z3_ADR_0 & !Z3_ADR<6> & AUTOCONFIG_Z3_ACCESS & !Z3_ADR<3> &
|
|
Z3_ADR<4> & !Z3_ADR<5>;
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 1 | 12 | LAN_BASEADR<11>
|
|
ATTRIBUTES | 8553408 | 0
|
|
OUTPUTMC | 1 | 7 | 1
|
|
INPUTS | 13 | D<11>.PIN | RESET | UDS | RW | FCS | Z3_ADR<2> | Z3_ADR_1 | Z3_ADR_0 | Z3_ADR<6> | AUTOCONFIG_Z3_ACCESS | Z3_ADR<3> | Z3_ADR<4> | Z3_ADR<5>
|
|
INPUTMC | 8 | 13 | 16 | 13 | 7 | 13 | 8 | 13 | 9 | 9 | 12 | 13 | 15 | 13 | 12 | 13 | 11
|
|
INPUTP | 5 | 77 | 263 | 155 | 158 | 147
|
|
EQ | 6 |
|
|
LAN_BASEADR<11>.D = D<11>.PIN;
|
|
LAN_BASEADR<11>.CLK = CLK_EXT; // GCK
|
|
LAN_BASEADR<11>.AP = !RESET;
|
|
LAN_BASEADR<11>.CE = !UDS & !RW & !FCS & !Z3_ADR<2> & !Z3_ADR_1 &
|
|
Z3_ADR_0 & !Z3_ADR<6> & AUTOCONFIG_Z3_ACCESS & !Z3_ADR<3> &
|
|
Z3_ADR<4> & !Z3_ADR<5>;
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 1 | 10 | LAN_BASEADR<12>
|
|
ATTRIBUTES | 8553408 | 0
|
|
OUTPUTMC | 2 | 0 | 15 | 0 | 8
|
|
INPUTS | 13 | D<12>.PIN | RESET | UDS | RW | FCS | Z3_ADR<2> | Z3_ADR_1 | Z3_ADR_0 | Z3_ADR<6> | AUTOCONFIG_Z3_ACCESS | Z3_ADR<3> | Z3_ADR<4> | Z3_ADR<5>
|
|
INPUTMC | 8 | 13 | 16 | 13 | 7 | 13 | 8 | 13 | 9 | 9 | 12 | 13 | 15 | 13 | 12 | 13 | 11
|
|
INPUTP | 5 | 78 | 263 | 155 | 158 | 147
|
|
EQ | 6 |
|
|
LAN_BASEADR<12>.D = D<12>.PIN;
|
|
LAN_BASEADR<12>.CLK = CLK_EXT; // GCK
|
|
LAN_BASEADR<12>.AP = !RESET;
|
|
LAN_BASEADR<12>.CE = !UDS & !RW & !FCS & !Z3_ADR<2> & !Z3_ADR_1 &
|
|
Z3_ADR_0 & !Z3_ADR<6> & AUTOCONFIG_Z3_ACCESS & !Z3_ADR<3> &
|
|
Z3_ADR<4> & !Z3_ADR<5>;
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 1 | 8 | LAN_BASEADR<13>
|
|
ATTRIBUTES | 8553408 | 0
|
|
OUTPUTMC | 1 | 8 | 7
|
|
INPUTS | 13 | D<13>.PIN | RESET | UDS | RW | FCS | Z3_ADR<2> | Z3_ADR_1 | Z3_ADR_0 | Z3_ADR<6> | AUTOCONFIG_Z3_ACCESS | Z3_ADR<3> | Z3_ADR<4> | Z3_ADR<5>
|
|
INPUTMC | 8 | 13 | 16 | 13 | 7 | 13 | 8 | 13 | 9 | 9 | 12 | 13 | 15 | 13 | 12 | 13 | 11
|
|
INPUTP | 5 | 80 | 263 | 155 | 158 | 147
|
|
EQ | 6 |
|
|
LAN_BASEADR<13>.D = D<13>.PIN;
|
|
LAN_BASEADR<13>.CLK = CLK_EXT; // GCK
|
|
LAN_BASEADR<13>.AP = !RESET;
|
|
LAN_BASEADR<13>.CE = !UDS & !RW & !FCS & !Z3_ADR<2> & !Z3_ADR_1 &
|
|
Z3_ADR_0 & !Z3_ADR<6> & AUTOCONFIG_Z3_ACCESS & !Z3_ADR<3> &
|
|
Z3_ADR<4> & !Z3_ADR<5>;
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 1 | 6 | LAN_BASEADR<14>
|
|
ATTRIBUTES | 8553408 | 0
|
|
OUTPUTMC | 1 | 13 | 16
|
|
INPUTS | 13 | D<14>.PIN | RESET | UDS | RW | FCS | Z3_ADR<2> | Z3_ADR_1 | Z3_ADR_0 | Z3_ADR<6> | AUTOCONFIG_Z3_ACCESS | Z3_ADR<3> | Z3_ADR<4> | Z3_ADR<5>
|
|
INPUTMC | 8 | 13 | 16 | 13 | 7 | 13 | 8 | 13 | 9 | 9 | 12 | 13 | 15 | 13 | 12 | 13 | 11
|
|
INPUTP | 5 | 81 | 263 | 155 | 158 | 147
|
|
EQ | 6 |
|
|
LAN_BASEADR<14>.D = D<14>.PIN;
|
|
LAN_BASEADR<14>.CLK = CLK_EXT; // GCK
|
|
LAN_BASEADR<14>.AP = !RESET;
|
|
LAN_BASEADR<14>.CE = !UDS & !RW & !FCS & !Z3_ADR<2> & !Z3_ADR_1 &
|
|
Z3_ADR_0 & !Z3_ADR<6> & AUTOCONFIG_Z3_ACCESS & !Z3_ADR<3> &
|
|
Z3_ADR<4> & !Z3_ADR<5>;
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 4 | 12 | LAN_BASEADR<15>
|
|
ATTRIBUTES | 8553408 | 0
|
|
OUTPUTMC | 1 | 5 | 14
|
|
INPUTS | 13 | D<15>.PIN | RESET | UDS | RW | FCS | Z3_ADR<2> | Z3_ADR_1 | Z3_ADR_0 | Z3_ADR<6> | AUTOCONFIG_Z3_ACCESS | Z3_ADR<3> | Z3_ADR<4> | Z3_ADR<5>
|
|
INPUTMC | 8 | 13 | 16 | 13 | 7 | 13 | 8 | 13 | 9 | 9 | 12 | 13 | 15 | 13 | 12 | 13 | 11
|
|
INPUTP | 5 | 89 | 263 | 155 | 158 | 147
|
|
EQ | 6 |
|
|
LAN_BASEADR<15>.D = D<15>.PIN;
|
|
LAN_BASEADR<15>.CLK = CLK_EXT; // GCK
|
|
LAN_BASEADR<15>.AP = !RESET;
|
|
LAN_BASEADR<15>.CE = !UDS & !RW & !FCS & !Z3_ADR<2> & !Z3_ADR_1 &
|
|
Z3_ADR_0 & !Z3_ADR<6> & AUTOCONFIG_Z3_ACCESS & !Z3_ADR<3> &
|
|
Z3_ADR<4> & !Z3_ADR<5>;
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 4 | 10 | LAN_BASEADR<1>
|
|
ATTRIBUTES | 8553408 | 0
|
|
OUTPUTMC | 1 | 13 | 0
|
|
INPUTS | 13 | D<1>.PIN | RESET | UDS | RW | FCS | Z3_ADR<2> | Z3_ADR_1 | Z3_ADR_0 | Z3_ADR<6> | AUTOCONFIG_Z3_ACCESS | Z3_ADR<3> | Z3_ADR<4> | Z3_ADR<5>
|
|
INPUTMC | 8 | 13 | 16 | 13 | 7 | 13 | 8 | 13 | 9 | 9 | 12 | 13 | 15 | 13 | 12 | 13 | 11
|
|
INPUTP | 5 | 30 | 263 | 155 | 158 | 147
|
|
EQ | 6 |
|
|
LAN_BASEADR<1>.D = D<1>.PIN;
|
|
LAN_BASEADR<1>.CLK = CLK_EXT; // GCK
|
|
LAN_BASEADR<1>.AP = !RESET;
|
|
LAN_BASEADR<1>.CE = !UDS & !RW & !FCS & !Z3_ADR<2> & !Z3_ADR_1 &
|
|
Z3_ADR_0 & !Z3_ADR<6> & AUTOCONFIG_Z3_ACCESS & !Z3_ADR<3> &
|
|
Z3_ADR<4> & !Z3_ADR<5>;
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 4 | 8 | LAN_BASEADR<2>
|
|
ATTRIBUTES | 8553408 | 0
|
|
OUTPUTMC | 2 | 13 | 0 | 13 | 17
|
|
INPUTS | 13 | D<2>.PIN | RESET | UDS | RW | FCS | Z3_ADR<2> | Z3_ADR_1 | Z3_ADR_0 | Z3_ADR<6> | AUTOCONFIG_Z3_ACCESS | Z3_ADR<3> | Z3_ADR<4> | Z3_ADR<5>
|
|
INPUTMC | 8 | 13 | 16 | 13 | 7 | 13 | 8 | 13 | 9 | 9 | 12 | 13 | 15 | 13 | 12 | 13 | 11
|
|
INPUTP | 5 | 71 | 263 | 155 | 158 | 147
|
|
EQ | 6 |
|
|
LAN_BASEADR<2>.D = D<2>.PIN;
|
|
LAN_BASEADR<2>.CLK = CLK_EXT; // GCK
|
|
LAN_BASEADR<2>.AP = !RESET;
|
|
LAN_BASEADR<2>.CE = !UDS & !RW & !FCS & !Z3_ADR<2> & !Z3_ADR_1 &
|
|
Z3_ADR_0 & !Z3_ADR<6> & AUTOCONFIG_Z3_ACCESS & !Z3_ADR<3> &
|
|
Z3_ADR<4> & !Z3_ADR<5>;
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 4 | 7 | LAN_BASEADR<3>
|
|
ATTRIBUTES | 8553408 | 0
|
|
OUTPUTMC | 1 | 13 | 17
|
|
INPUTS | 13 | D<3>.PIN | RESET | UDS | RW | FCS | Z3_ADR<2> | Z3_ADR_1 | Z3_ADR_0 | Z3_ADR<6> | AUTOCONFIG_Z3_ACCESS | Z3_ADR<3> | Z3_ADR<4> | Z3_ADR<5>
|
|
INPUTMC | 8 | 13 | 16 | 13 | 7 | 13 | 8 | 13 | 9 | 9 | 12 | 13 | 15 | 13 | 12 | 13 | 11
|
|
INPUTP | 5 | 28 | 263 | 155 | 158 | 147
|
|
EQ | 6 |
|
|
LAN_BASEADR<3>.D = D<3>.PIN;
|
|
LAN_BASEADR<3>.CLK = CLK_EXT; // GCK
|
|
LAN_BASEADR<3>.AP = !RESET;
|
|
LAN_BASEADR<3>.CE = !UDS & !RW & !FCS & !Z3_ADR<2> & !Z3_ADR_1 &
|
|
Z3_ADR_0 & !Z3_ADR<6> & AUTOCONFIG_Z3_ACCESS & !Z3_ADR<3> &
|
|
Z3_ADR<4> & !Z3_ADR<5>;
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 4 | 6 | LAN_BASEADR<4>
|
|
ATTRIBUTES | 8553408 | 0
|
|
OUTPUTMC | 1 | 13 | 17
|
|
INPUTS | 13 | D<4>.PIN | RESET | UDS | RW | FCS | Z3_ADR<2> | Z3_ADR_1 | Z3_ADR_0 | Z3_ADR<6> | AUTOCONFIG_Z3_ACCESS | Z3_ADR<3> | Z3_ADR<4> | Z3_ADR<5>
|
|
INPUTMC | 8 | 13 | 16 | 13 | 7 | 13 | 8 | 13 | 9 | 9 | 12 | 13 | 15 | 13 | 12 | 13 | 11
|
|
INPUTP | 5 | 38 | 263 | 155 | 158 | 147
|
|
EQ | 6 |
|
|
LAN_BASEADR<4>.D = D<4>.PIN;
|
|
LAN_BASEADR<4>.CLK = CLK_EXT; // GCK
|
|
LAN_BASEADR<4>.AP = !RESET;
|
|
LAN_BASEADR<4>.CE = !UDS & !RW & !FCS & !Z3_ADR<2> & !Z3_ADR_1 &
|
|
Z3_ADR_0 & !Z3_ADR<6> & AUTOCONFIG_Z3_ACCESS & !Z3_ADR<3> &
|
|
Z3_ADR<4> & !Z3_ADR<5>;
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 4 | 5 | LAN_BASEADR<5>
|
|
ATTRIBUTES | 8553408 | 0
|
|
OUTPUTMC | 1 | 13 | 1
|
|
INPUTS | 13 | D<5>.PIN | RESET | UDS | RW | FCS | Z3_ADR<2> | Z3_ADR_1 | Z3_ADR_0 | Z3_ADR<6> | AUTOCONFIG_Z3_ACCESS | Z3_ADR<3> | Z3_ADR<4> | Z3_ADR<5>
|
|
INPUTMC | 8 | 13 | 16 | 13 | 7 | 13 | 8 | 13 | 9 | 9 | 12 | 13 | 15 | 13 | 12 | 13 | 11
|
|
INPUTP | 5 | 37 | 263 | 155 | 158 | 147
|
|
EQ | 6 |
|
|
LAN_BASEADR<5>.D = D<5>.PIN;
|
|
LAN_BASEADR<5>.CLK = CLK_EXT; // GCK
|
|
LAN_BASEADR<5>.AP = !RESET;
|
|
LAN_BASEADR<5>.CE = !UDS & !RW & !FCS & !Z3_ADR<2> & !Z3_ADR_1 &
|
|
Z3_ADR_0 & !Z3_ADR<6> & AUTOCONFIG_Z3_ACCESS & !Z3_ADR<3> &
|
|
Z3_ADR<4> & !Z3_ADR<5>;
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 4 | 3 | LAN_BASEADR<6>
|
|
ATTRIBUTES | 8553408 | 0
|
|
OUTPUTMC | 1 | 8 | 6
|
|
INPUTS | 13 | D<6>.PIN | RESET | UDS | RW | FCS | Z3_ADR<2> | Z3_ADR_1 | Z3_ADR_0 | Z3_ADR<6> | AUTOCONFIG_Z3_ACCESS | Z3_ADR<3> | Z3_ADR<4> | Z3_ADR<5>
|
|
INPUTMC | 8 | 13 | 16 | 13 | 7 | 13 | 8 | 13 | 9 | 9 | 12 | 13 | 15 | 13 | 12 | 13 | 11
|
|
INPUTP | 5 | 26 | 263 | 155 | 158 | 147
|
|
EQ | 6 |
|
|
LAN_BASEADR<6>.D = D<6>.PIN;
|
|
LAN_BASEADR<6>.CLK = CLK_EXT; // GCK
|
|
LAN_BASEADR<6>.AP = !RESET;
|
|
LAN_BASEADR<6>.CE = !UDS & !RW & !FCS & !Z3_ADR<2> & !Z3_ADR_1 &
|
|
Z3_ADR_0 & !Z3_ADR<6> & AUTOCONFIG_Z3_ACCESS & !Z3_ADR<3> &
|
|
Z3_ADR<4> & !Z3_ADR<5>;
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 4 | 2 | LAN_BASEADR<7>
|
|
ATTRIBUTES | 8553408 | 0
|
|
OUTPUTMC | 1 | 13 | 1
|
|
INPUTS | 13 | D<7>.PIN | RESET | UDS | RW | FCS | Z3_ADR<2> | Z3_ADR_1 | Z3_ADR_0 | Z3_ADR<6> | AUTOCONFIG_Z3_ACCESS | Z3_ADR<3> | Z3_ADR<4> | Z3_ADR<5>
|
|
INPUTMC | 8 | 13 | 16 | 13 | 7 | 13 | 8 | 13 | 9 | 9 | 12 | 13 | 15 | 13 | 12 | 13 | 11
|
|
INPUTP | 5 | 29 | 263 | 155 | 158 | 147
|
|
EQ | 6 |
|
|
LAN_BASEADR<7>.D = D<7>.PIN;
|
|
LAN_BASEADR<7>.CLK = CLK_EXT; // GCK
|
|
LAN_BASEADR<7>.AP = !RESET;
|
|
LAN_BASEADR<7>.CE = !UDS & !RW & !FCS & !Z3_ADR<2> & !Z3_ADR_1 &
|
|
Z3_ADR_0 & !Z3_ADR<6> & AUTOCONFIG_Z3_ACCESS & !Z3_ADR<3> &
|
|
Z3_ADR<4> & !Z3_ADR<5>;
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 4 | 0 | LAN_BASEADR<8>
|
|
ATTRIBUTES | 8553408 | 0
|
|
OUTPUTMC | 1 | 5 | 15
|
|
INPUTS | 13 | D<8>.PIN | RESET | UDS | RW | FCS | Z3_ADR<2> | Z3_ADR_1 | Z3_ADR_0 | Z3_ADR<6> | AUTOCONFIG_Z3_ACCESS | Z3_ADR<3> | Z3_ADR<4> | Z3_ADR<5>
|
|
INPUTMC | 8 | 13 | 16 | 13 | 7 | 13 | 8 | 13 | 9 | 9 | 12 | 13 | 15 | 13 | 12 | 13 | 11
|
|
INPUTP | 5 | 32 | 263 | 155 | 158 | 147
|
|
EQ | 6 |
|
|
LAN_BASEADR<8>.D = D<8>.PIN;
|
|
LAN_BASEADR<8>.CLK = CLK_EXT; // GCK
|
|
LAN_BASEADR<8>.AP = !RESET;
|
|
LAN_BASEADR<8>.CE = !UDS & !RW & !FCS & !Z3_ADR<2> & !Z3_ADR_1 &
|
|
Z3_ADR_0 & !Z3_ADR<6> & AUTOCONFIG_Z3_ACCESS & !Z3_ADR<3> &
|
|
Z3_ADR<4> & !Z3_ADR<5>;
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 1 | 3 | LAN_BASEADR<9>
|
|
ATTRIBUTES | 8553408 | 0
|
|
OUTPUTMC | 1 | 5 | 16
|
|
INPUTS | 13 | D<9>.PIN | RESET | UDS | RW | FCS | Z3_ADR<2> | Z3_ADR_1 | Z3_ADR_0 | Z3_ADR<6> | AUTOCONFIG_Z3_ACCESS | Z3_ADR<3> | Z3_ADR<4> | Z3_ADR<5>
|
|
INPUTMC | 8 | 13 | 16 | 13 | 7 | 13 | 8 | 13 | 9 | 9 | 12 | 13 | 15 | 13 | 12 | 13 | 11
|
|
INPUTP | 5 | 73 | 263 | 155 | 158 | 147
|
|
EQ | 6 |
|
|
LAN_BASEADR<9>.D = D<9>.PIN;
|
|
LAN_BASEADR<9>.CLK = CLK_EXT; // GCK
|
|
LAN_BASEADR<9>.AP = !RESET;
|
|
LAN_BASEADR<9>.CE = !UDS & !RW & !FCS & !Z3_ADR<2> & !Z3_ADR_1 &
|
|
Z3_ADR_0 & !Z3_ADR<6> & AUTOCONFIG_Z3_ACCESS & !Z3_ADR<3> &
|
|
Z3_ADR<4> & !Z3_ADR<5>;
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 0 | 17 | LAN_INT_ENABLE
|
|
ATTRIBUTES | 4358928 | 0
|
|
OUTPUTMC | 2 | 0 | 17 | 2 | 13
|
|
INPUTS | 8 | D<15>.PIN | UDS | RW | LAN_INT_ENABLE | BUF_CONFIG_READY | LDS | A<23>.PIN | RESET
|
|
INPUTMC | 2 | 0 | 17 | 13 | 1
|
|
INPUTP | 6 | 89 | 155 | 158 | 157 | 161 | 263
|
|
EQ | 10 |
|
|
LAN_INT_ENABLE.T = D<15>.PIN & !UDS & !RW & !LAN_INT_ENABLE &
|
|
BUF_CONFIG_READY
|
|
# !D<15>.PIN & !UDS & !RW & LAN_INT_ENABLE &
|
|
BUF_CONFIG_READY
|
|
# UDS & !LDS & !RW & LAN_INT_ENABLE & !A<23>.PIN &
|
|
BUF_CONFIG_READY
|
|
# UDS & !LDS & !RW & !LAN_INT_ENABLE & A<23>.PIN &
|
|
BUF_CONFIG_READY;
|
|
LAN_INT_ENABLE.CLK = CLK_EXT; // GCK
|
|
LAN_INT_ENABLE.AR = !RESET;
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 11 | 16 | LAN_IRQ_OUT
|
|
ATTRIBUTES | 8553344 | 0
|
|
OUTPUTMC | 2 | 11 | 16 | 2 | 13
|
|
INPUTS | 4 | LAN_IRQ_OUT | LAN_IRQ_D0 | LAN_INT | RESET
|
|
INPUTMC | 2 | 11 | 16 | 11 | 2
|
|
INPUTP | 2 | 201 | 263
|
|
EQ | 4 |
|
|
LAN_IRQ_OUT.D = LAN_INT
|
|
# LAN_IRQ_OUT & !LAN_IRQ_D0;
|
|
LAN_IRQ_OUT.CLK = CLK_EXT; // GCK
|
|
LAN_IRQ_OUT.AP = !RESET;
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 15 | 14 | Z3_DATA<16>
|
|
ATTRIBUTES | 8553408 | 0
|
|
OUTPUTMC | 2 | 3 | 1 | 15 | 15
|
|
INPUTS | 8 | DQ_SWAP | DQ<8>.PIN | DQ<0>.PIN | LAN_SM_RST | LAN_SM_FSM_FFd4 | LAN_SM_FSM_FFd2 | LAN_SM_FSM_FFd1 | $OpTx$FX_DC$12
|
|
INPUTMC | 6 | 0 | 15 | 11 | 0 | 10 | 6 | 10 | 7 | 10 | 12 | 5 | 8
|
|
INPUTP | 2 | 231 | 217
|
|
EXPORTS | 1 | 15 | 15
|
|
EQ | 8 |
|
|
Z3_DATA<16>.D = DQ_SWAP & DQ<8>.PIN
|
|
# !DQ_SWAP & DQ<0>.PIN;
|
|
Z3_DATA<16>.CLK = CLK_EXT; // GCK
|
|
Z3_DATA<16>.AP = LAN_SM_RST;
|
|
Z3_DATA<16>.CE = !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 &
|
|
LAN_SM_FSM_FFd1;
|
|
Z3_DATA<16>.EXP = !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 &
|
|
!$OpTx$FX_DC$12
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 15 | 13 | Z3_DATA<17>
|
|
ATTRIBUTES | 8553408 | 0
|
|
OUTPUTMC | 1 | 1 | 14
|
|
INPUTS | 7 | DQ_SWAP | DQ<9>.PIN | DQ<1>.PIN | LAN_SM_RST | LAN_SM_FSM_FFd4 | LAN_SM_FSM_FFd2 | LAN_SM_FSM_FFd1
|
|
INPUTMC | 5 | 0 | 15 | 11 | 0 | 10 | 6 | 10 | 7 | 10 | 12
|
|
INPUTP | 2 | 209 | 216
|
|
EQ | 6 |
|
|
Z3_DATA<17>.D = DQ_SWAP & DQ<9>.PIN
|
|
# !DQ_SWAP & DQ<1>.PIN;
|
|
Z3_DATA<17>.CLK = CLK_EXT; // GCK
|
|
Z3_DATA<17>.AP = LAN_SM_RST;
|
|
Z3_DATA<17>.CE = !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 &
|
|
LAN_SM_FSM_FFd1;
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 15 | 17 | Z3_DATA<18>
|
|
ATTRIBUTES | 8553408 | 0
|
|
OUTPUTMC | 2 | 4 | 9 | 15 | 16
|
|
INPUTS | 9 | DQ_SWAP | DQ<2>.PIN | DQ<10>.PIN | LAN_SM_RST | LAN_SM_FSM_FFd4 | LAN_SM_FSM_FFd2 | LAN_SM_FSM_FFd1 | LAN_SM_FSM_FFd3 | $OpTx$FX_DC$10
|
|
INPUTMC | 7 | 0 | 15 | 11 | 0 | 10 | 6 | 10 | 7 | 10 | 12 | 15 | 16 | 5 | 10
|
|
INPUTP | 2 | 220 | 234
|
|
EXPORTS | 1 | 15 | 16
|
|
EQ | 8 |
|
|
Z3_DATA<18>.D = DQ_SWAP & DQ<10>.PIN
|
|
# !DQ_SWAP & DQ<2>.PIN;
|
|
Z3_DATA<18>.CLK = CLK_EXT; // GCK
|
|
Z3_DATA<18>.AP = LAN_SM_RST;
|
|
Z3_DATA<18>.CE = !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 &
|
|
LAN_SM_FSM_FFd1;
|
|
Z3_DATA<18>.EXP = !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 &
|
|
!LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1 & !$OpTx$FX_DC$10
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 15 | 12 | Z3_DATA<19>
|
|
ATTRIBUTES | 8553408 | 0
|
|
OUTPUTMC | 1 | 1 | 11
|
|
INPUTS | 7 | DQ_SWAP | DQ<3>.PIN | DQ<11>.PIN | LAN_SM_RST | LAN_SM_FSM_FFd4 | LAN_SM_FSM_FFd2 | LAN_SM_FSM_FFd1
|
|
INPUTMC | 5 | 0 | 15 | 11 | 0 | 10 | 6 | 10 | 7 | 10 | 12
|
|
INPUTP | 2 | 219 | 207
|
|
EQ | 6 |
|
|
Z3_DATA<19>.D = DQ_SWAP & DQ<11>.PIN
|
|
# !DQ_SWAP & DQ<3>.PIN;
|
|
Z3_DATA<19>.CLK = CLK_EXT; // GCK
|
|
Z3_DATA<19>.AP = LAN_SM_RST;
|
|
Z3_DATA<19>.CE = !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 &
|
|
LAN_SM_FSM_FFd1;
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 15 | 11 | Z3_DATA<20>
|
|
ATTRIBUTES | 8553408 | 0
|
|
OUTPUTMC | 1 | 0 | 5
|
|
INPUTS | 7 | DQ_SWAP | DQ<4>.PIN | DQ<12>.PIN | LAN_SM_RST | LAN_SM_FSM_FFd4 | LAN_SM_FSM_FFd2 | LAN_SM_FSM_FFd1
|
|
INPUTMC | 5 | 0 | 15 | 11 | 0 | 10 | 6 | 10 | 7 | 10 | 12
|
|
INPUTP | 2 | 225 | 235
|
|
EQ | 6 |
|
|
Z3_DATA<20>.D = DQ_SWAP & DQ<12>.PIN
|
|
# !DQ_SWAP & DQ<4>.PIN;
|
|
Z3_DATA<20>.CLK = CLK_EXT; // GCK
|
|
Z3_DATA<20>.AP = LAN_SM_RST;
|
|
Z3_DATA<20>.CE = !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 &
|
|
LAN_SM_FSM_FFd1;
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 10 | 5 | Z3_DATA<21>
|
|
ATTRIBUTES | 8553408 | 0
|
|
OUTPUTMC | 1 | 0 | 4
|
|
INPUTS | 7 | DQ_SWAP | DQ<5>.PIN | DQ<13>.PIN | LAN_SM_RST | LAN_SM_FSM_FFd4 | LAN_SM_FSM_FFd2 | LAN_SM_FSM_FFd1
|
|
INPUTMC | 5 | 0 | 15 | 11 | 0 | 10 | 6 | 10 | 7 | 10 | 12
|
|
INPUTP | 2 | 221 | 204
|
|
EQ | 6 |
|
|
Z3_DATA<21>.D = DQ_SWAP & DQ<13>.PIN
|
|
# !DQ_SWAP & DQ<5>.PIN;
|
|
Z3_DATA<21>.CLK = CLK_EXT; // GCK
|
|
Z3_DATA<21>.AP = LAN_SM_RST;
|
|
Z3_DATA<21>.CE = !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 &
|
|
LAN_SM_FSM_FFd1;
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 10 | 3 | Z3_DATA<22>
|
|
ATTRIBUTES | 8553408 | 0
|
|
OUTPUTMC | 1 | 1 | 9
|
|
INPUTS | 7 | DQ_SWAP | DQ<6>.PIN | DQ<14>.PIN | LAN_SM_RST | LAN_SM_FSM_FFd4 | LAN_SM_FSM_FFd2 | LAN_SM_FSM_FFd1
|
|
INPUTMC | 5 | 0 | 15 | 11 | 0 | 10 | 6 | 10 | 7 | 10 | 12
|
|
INPUTP | 2 | 227 | 236
|
|
EQ | 6 |
|
|
Z3_DATA<22>.D = DQ_SWAP & DQ<14>.PIN
|
|
# !DQ_SWAP & DQ<6>.PIN;
|
|
Z3_DATA<22>.CLK = CLK_EXT; // GCK
|
|
Z3_DATA<22>.AP = LAN_SM_RST;
|
|
Z3_DATA<22>.CE = !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 &
|
|
LAN_SM_FSM_FFd1;
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 14 | 5 | Z3_DATA<23>
|
|
ATTRIBUTES | 8553408 | 0
|
|
OUTPUTMC | 2 | 1 | 13 | 14 | 4
|
|
INPUTS | 7 | DQ_SWAP | DQ<7>.PIN | DQ<15>.PIN | LAN_SM_RST | LAN_SM_FSM_FFd4 | LAN_SM_FSM_FFd2 | LAN_SM_FSM_FFd1
|
|
INPUTMC | 5 | 0 | 15 | 11 | 0 | 10 | 6 | 10 | 7 | 10 | 12
|
|
INPUTP | 2 | 226 | 202
|
|
EXPORTS | 1 | 14 | 4
|
|
EQ | 8 |
|
|
Z3_DATA<23>.D = DQ_SWAP & DQ<15>.PIN
|
|
# !DQ_SWAP & DQ<7>.PIN;
|
|
Z3_DATA<23>.CLK = CLK_EXT; // GCK
|
|
Z3_DATA<23>.AP = LAN_SM_RST;
|
|
Z3_DATA<23>.CE = !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 &
|
|
LAN_SM_FSM_FFd1;
|
|
Z3_DATA<23>.EXP = !LAN_SM_FSM_FFd4 & !LAN_SM_FSM_FFd2 &
|
|
LAN_SM_FSM_FFd1
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 15 | 8 | Z3_DATA<24>
|
|
ATTRIBUTES | 8553408 | 0
|
|
OUTPUTMC | 1 | 1 | 16
|
|
INPUTS | 7 | DQ_SWAP | DQ<8>.PIN | DQ<0>.PIN | LAN_SM_RST | LAN_SM_FSM_FFd4 | LAN_SM_FSM_FFd2 | LAN_SM_FSM_FFd1
|
|
INPUTMC | 5 | 0 | 15 | 11 | 0 | 10 | 6 | 10 | 7 | 10 | 12
|
|
INPUTP | 2 | 231 | 217
|
|
EQ | 6 |
|
|
Z3_DATA<24>.D = DQ_SWAP & DQ<0>.PIN
|
|
# !DQ_SWAP & DQ<8>.PIN;
|
|
Z3_DATA<24>.CLK = CLK_EXT; // GCK
|
|
Z3_DATA<24>.AP = LAN_SM_RST;
|
|
Z3_DATA<24>.CE = !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 &
|
|
LAN_SM_FSM_FFd1;
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 15 | 6 | Z3_DATA<25>
|
|
ATTRIBUTES | 8553408 | 0
|
|
OUTPUTMC | 1 | 4 | 11
|
|
INPUTS | 7 | DQ_SWAP | DQ<9>.PIN | DQ<1>.PIN | LAN_SM_RST | LAN_SM_FSM_FFd4 | LAN_SM_FSM_FFd2 | LAN_SM_FSM_FFd1
|
|
INPUTMC | 5 | 0 | 15 | 11 | 0 | 10 | 6 | 10 | 7 | 10 | 12
|
|
INPUTP | 2 | 209 | 216
|
|
EQ | 6 |
|
|
Z3_DATA<25>.D = DQ_SWAP & DQ<1>.PIN
|
|
# !DQ_SWAP & DQ<9>.PIN;
|
|
Z3_DATA<25>.CLK = CLK_EXT; // GCK
|
|
Z3_DATA<25>.AP = LAN_SM_RST;
|
|
Z3_DATA<25>.CE = !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 &
|
|
LAN_SM_FSM_FFd1;
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 15 | 4 | Z3_DATA<26>
|
|
ATTRIBUTES | 8553408 | 0
|
|
OUTPUTMC | 1 | 4 | 13
|
|
INPUTS | 7 | DQ_SWAP | DQ<2>.PIN | DQ<10>.PIN | LAN_SM_RST | LAN_SM_FSM_FFd4 | LAN_SM_FSM_FFd2 | LAN_SM_FSM_FFd1
|
|
INPUTMC | 5 | 0 | 15 | 11 | 0 | 10 | 6 | 10 | 7 | 10 | 12
|
|
INPUTP | 2 | 220 | 234
|
|
EQ | 6 |
|
|
Z3_DATA<26>.D = DQ_SWAP & DQ<2>.PIN
|
|
# !DQ_SWAP & DQ<10>.PIN;
|
|
Z3_DATA<26>.CLK = CLK_EXT; // GCK
|
|
Z3_DATA<26>.AP = LAN_SM_RST;
|
|
Z3_DATA<26>.CE = !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 &
|
|
LAN_SM_FSM_FFd1;
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 15 | 3 | Z3_DATA<27>
|
|
ATTRIBUTES | 8553408 | 0
|
|
OUTPUTMC | 1 | 4 | 14
|
|
INPUTS | 7 | DQ_SWAP | DQ<3>.PIN | DQ<11>.PIN | LAN_SM_RST | LAN_SM_FSM_FFd4 | LAN_SM_FSM_FFd2 | LAN_SM_FSM_FFd1
|
|
INPUTMC | 5 | 0 | 15 | 11 | 0 | 10 | 6 | 10 | 7 | 10 | 12
|
|
INPUTP | 2 | 219 | 207
|
|
EQ | 6 |
|
|
Z3_DATA<27>.D = DQ_SWAP & DQ<3>.PIN
|
|
# !DQ_SWAP & DQ<11>.PIN;
|
|
Z3_DATA<27>.CLK = CLK_EXT; // GCK
|
|
Z3_DATA<27>.AP = LAN_SM_RST;
|
|
Z3_DATA<27>.CE = !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 &
|
|
LAN_SM_FSM_FFd1;
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 15 | 0 | Z3_DATA<28>
|
|
ATTRIBUTES | 8553408 | 0
|
|
OUTPUTMC | 1 | 4 | 16
|
|
INPUTS | 7 | DQ_SWAP | DQ<4>.PIN | DQ<12>.PIN | LAN_SM_RST | LAN_SM_FSM_FFd4 | LAN_SM_FSM_FFd2 | LAN_SM_FSM_FFd1
|
|
INPUTMC | 5 | 0 | 15 | 11 | 0 | 10 | 6 | 10 | 7 | 10 | 12
|
|
INPUTP | 2 | 225 | 235
|
|
EQ | 6 |
|
|
Z3_DATA<28>.D = DQ_SWAP & DQ<4>.PIN
|
|
# !DQ_SWAP & DQ<12>.PIN;
|
|
Z3_DATA<28>.CLK = CLK_EXT; // GCK
|
|
Z3_DATA<28>.AP = LAN_SM_RST;
|
|
Z3_DATA<28>.CE = !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 &
|
|
LAN_SM_FSM_FFd1;
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 10 | 1 | Z3_DATA<29>
|
|
ATTRIBUTES | 8553408 | 0
|
|
OUTPUTMC | 1 | 6 | 3
|
|
INPUTS | 7 | DQ_SWAP | DQ<5>.PIN | DQ<13>.PIN | LAN_SM_RST | LAN_SM_FSM_FFd4 | LAN_SM_FSM_FFd2 | LAN_SM_FSM_FFd1
|
|
INPUTMC | 5 | 0 | 15 | 11 | 0 | 10 | 6 | 10 | 7 | 10 | 12
|
|
INPUTP | 2 | 221 | 204
|
|
EQ | 6 |
|
|
Z3_DATA<29>.D = DQ_SWAP & DQ<5>.PIN
|
|
# !DQ_SWAP & DQ<13>.PIN;
|
|
Z3_DATA<29>.CLK = CLK_EXT; // GCK
|
|
Z3_DATA<29>.AP = LAN_SM_RST;
|
|
Z3_DATA<29>.CE = !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 &
|
|
LAN_SM_FSM_FFd1;
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 10 | 0 | Z3_DATA<30>
|
|
ATTRIBUTES | 8553408 | 0
|
|
OUTPUTMC | 2 | 6 | 4 | 10 | 17
|
|
INPUTS | 10 | DQ_SWAP | DQ<6>.PIN | DQ<14>.PIN | LAN_SM_RST | LAN_SM_FSM_FFd4 | LAN_SM_FSM_FFd2 | LAN_SM_FSM_FFd1 | D<8>.PIN | LAN_SM_FSM_FFd3 | $OpTx$FX_DC$10
|
|
INPUTMC | 7 | 0 | 15 | 11 | 0 | 10 | 6 | 10 | 7 | 10 | 12 | 15 | 16 | 5 | 10
|
|
INPUTP | 3 | 227 | 236 | 32
|
|
EXPORTS | 1 | 10 | 17
|
|
EQ | 8 |
|
|
Z3_DATA<30>.D = DQ_SWAP & DQ<6>.PIN
|
|
# !DQ_SWAP & DQ<14>.PIN;
|
|
Z3_DATA<30>.CLK = CLK_EXT; // GCK
|
|
Z3_DATA<30>.AP = LAN_SM_RST;
|
|
Z3_DATA<30>.CE = !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 &
|
|
LAN_SM_FSM_FFd1;
|
|
Z3_DATA<30>.EXP = D<8>.PIN & DQ_SWAP & !LAN_SM_FSM_FFd3 &
|
|
!LAN_SM_FSM_FFd4 & !$OpTx$FX_DC$10
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 14 | 6 | Z3_DATA<31>
|
|
ATTRIBUTES | 8553408 | 0
|
|
OUTPUTMC | 1 | 6 | 11
|
|
INPUTS | 7 | DQ_SWAP | DQ<7>.PIN | DQ<15>.PIN | LAN_SM_RST | LAN_SM_FSM_FFd4 | LAN_SM_FSM_FFd2 | LAN_SM_FSM_FFd1
|
|
INPUTMC | 5 | 0 | 15 | 11 | 0 | 10 | 6 | 10 | 7 | 10 | 12
|
|
INPUTP | 2 | 226 | 202
|
|
EQ | 6 |
|
|
Z3_DATA<31>.D = DQ_SWAP & DQ<7>.PIN
|
|
# !DQ_SWAP & DQ<15>.PIN;
|
|
Z3_DATA<31>.CLK = CLK_EXT; // GCK
|
|
Z3_DATA<31>.AP = LAN_SM_RST;
|
|
Z3_DATA<31>.CE = !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 &
|
|
LAN_SM_FSM_FFd1;
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 9 | 16 | DQ_10_IOBUFE
|
|
ATTRIBUTES | 265986 | 0
|
|
INPUTS | 4 | RESET | LAN_D_INIT<8> | DQ_DATA<10> | DQ_5_IOBUFE/DQ_5_IOBUFE_TRST
|
|
INPUTMC | 3 | 11 | 3 | 10 | 15 | 0 | 1
|
|
INPUTP | 1 | 263
|
|
EQ | 3 |
|
|
DQ<10> = RESET & DQ_DATA<10>
|
|
# !RESET & LAN_D_INIT<8>;
|
|
DQ<10>.OE = DQ_5_IOBUFE/DQ_5_IOBUFE_TRST;
|
|
|
|
MACROCELL | 11 | 9 | DQ_11_IOBUFE
|
|
ATTRIBUTES | 265986 | 0
|
|
INPUTS | 4 | RESET | LAN_D_INIT<8> | DQ_DATA<11> | DQ_5_IOBUFE/DQ_5_IOBUFE_TRST
|
|
INPUTMC | 3 | 11 | 3 | 14 | 0 | 0 | 1
|
|
INPUTP | 1 | 263
|
|
EQ | 3 |
|
|
DQ<11> = RESET & DQ_DATA<11>
|
|
# !RESET & LAN_D_INIT<8>;
|
|
DQ<11>.OE = DQ_5_IOBUFE/DQ_5_IOBUFE_TRST;
|
|
|
|
MACROCELL | 9 | 1 | DQ_1_IOBUFE
|
|
ATTRIBUTES | 265986 | 0
|
|
INPUTS | 4 | RESET | LAN_D_INIT<1> | DQ_DATA<1> | DQ_5_IOBUFE/DQ_5_IOBUFE_TRST
|
|
INPUTMC | 3 | 11 | 5 | 12 | 17 | 0 | 1
|
|
INPUTP | 1 | 263
|
|
EQ | 3 |
|
|
DQ<1> = RESET & DQ_DATA<1>
|
|
# !RESET & LAN_D_INIT<1>;
|
|
DQ<1>.OE = DQ_5_IOBUFE/DQ_5_IOBUFE_TRST;
|
|
|
|
MACROCELL | 9 | 9 | DQ_4_IOBUFE
|
|
ATTRIBUTES | 265986 | 0
|
|
INPUTS | 4 | RESET | LAN_D_INIT<1> | DQ_DATA<4> | DQ_5_IOBUFE/DQ_5_IOBUFE_TRST
|
|
INPUTMC | 3 | 11 | 5 | 14 | 3 | 0 | 1
|
|
INPUTP | 1 | 263
|
|
EQ | 3 |
|
|
DQ<4> = RESET & DQ_DATA<4>
|
|
# !RESET & LAN_D_INIT<1>;
|
|
DQ<4>.OE = DQ_5_IOBUFE/DQ_5_IOBUFE_TRST;
|
|
|
|
MACROCELL | 9 | 13 | DQ_8_IOBUFE
|
|
ATTRIBUTES | 265986 | 0
|
|
INPUTS | 4 | RESET | LAN_D_INIT<8> | DQ_DATA<8> | DQ_5_IOBUFE/DQ_5_IOBUFE_TRST
|
|
INPUTMC | 3 | 11 | 3 | 10 | 14 | 0 | 1
|
|
INPUTP | 1 | 263
|
|
EQ | 3 |
|
|
DQ<8> = RESET & DQ_DATA<8>
|
|
# !RESET & LAN_D_INIT<8>;
|
|
DQ<8>.OE = DQ_5_IOBUFE/DQ_5_IOBUFE_TRST;
|
|
|
|
MACROCELL | 11 | 11 | DQ_9_IOBUFE
|
|
ATTRIBUTES | 265986 | 0
|
|
INPUTS | 4 | RESET | LAN_D_INIT<1> | DQ_DATA<9> | DQ_5_IOBUFE/DQ_5_IOBUFE_TRST
|
|
INPUTMC | 3 | 11 | 5 | 12 | 15 | 0 | 1
|
|
INPUTP | 1 | 263
|
|
EQ | 3 |
|
|
DQ<9> = RESET & DQ_DATA<9>
|
|
# !RESET & LAN_D_INIT<1>;
|
|
DQ<9>.OE = DQ_5_IOBUFE/DQ_5_IOBUFE_TRST;
|
|
|
|
MACROCELL | 3 | 1 | D_0_IOBUFE
|
|
ATTRIBUTES | 265986 | 0
|
|
OUTPUTMC | 1 | 3 | 0
|
|
INPUTS | 11 | Z3_DATA<16> | Z3_DATA<9>/Z3_DATA<9>_TRST | D_9_IOBUFE/D_9_IOBUFE_TRST | AUTO_CONFIG_Z2_DONE<1> | A<5> | A<3> | AUTO_CONFIG_Z2_DONE<0> | BUF_D_Z2_OUT<3> | A<1> | A<6> | BUF_D_Z2_OUT<2>
|
|
INPUTMC | 7 | 15 | 14 | 14 | 17 | 0 | 12 | 9 | 14 | 9 | 15 | 3 | 14 | 3 | 12
|
|
INPUTP | 4 | 91 | 99 | 107 | 98
|
|
EXPORTS | 1 | 3 | 0
|
|
EQ | 6 |
|
|
!D<0> = !Z3_DATA<16> & Z3_DATA<9>/Z3_DATA<9>_TRST;
|
|
D<0>.OE = D_9_IOBUFE/D_9_IOBUFE_TRST;
|
|
D_0_IOBUFE.EXP = AUTO_CONFIG_Z2_DONE<1> & A<5> & A<3>
|
|
# AUTO_CONFIG_Z2_DONE<0> & !A<5> & !A<3> &
|
|
BUF_D_Z2_OUT<3>
|
|
# A<1> & !A<6> & BUF_D_Z2_OUT<2> & !BUF_D_Z2_OUT<3>
|
|
|
|
MACROCELL | 4 | 13 | D_10_IOBUFE
|
|
ATTRIBUTES | 265986 | 0
|
|
INPUTS | 5 | Z3_DATA<26> | Z3_DATA<9>/Z3_DATA<9>_TRST | D_OUT<2> | $OpTx$FX_DC$36 | D_9_IOBUFE/D_9_IOBUFE_TRST
|
|
INPUTMC | 5 | 15 | 4 | 14 | 17 | 12 | 9 | 14 | 10 | 0 | 12
|
|
EQ | 4 |
|
|
!D<10> = !Z3_DATA<26> & Z3_DATA<9>/Z3_DATA<9>_TRST
|
|
# !D_OUT<2> & !Z3_DATA<9>/Z3_DATA<9>_TRST &
|
|
$OpTx$FX_DC$36;
|
|
D<10>.OE = D_9_IOBUFE/D_9_IOBUFE_TRST;
|
|
|
|
MACROCELL | 4 | 14 | D_11_IOBUFE
|
|
ATTRIBUTES | 265986 | 0
|
|
INPUTS | 5 | Z3_DATA<27> | Z3_DATA<9>/Z3_DATA<9>_TRST | D_OUT<3> | $OpTx$FX_DC$36 | D_9_IOBUFE/D_9_IOBUFE_TRST
|
|
INPUTMC | 5 | 15 | 3 | 14 | 17 | 12 | 4 | 14 | 10 | 0 | 12
|
|
EQ | 4 |
|
|
!D<11> = !Z3_DATA<27> & Z3_DATA<9>/Z3_DATA<9>_TRST
|
|
# !D_OUT<3> & !Z3_DATA<9>/Z3_DATA<9>_TRST &
|
|
$OpTx$FX_DC$36;
|
|
D<11>.OE = D_9_IOBUFE/D_9_IOBUFE_TRST;
|
|
|
|
MACROCELL | 4 | 16 | D_12_IOBUFE
|
|
ATTRIBUTES | 265986 | 0
|
|
INPUTS | 7 | D_OUT<4> | $OpTx$FX_SC$66 | Z3_DATA<28> | Z3_DATA<9>/Z3_DATA<9>_TRST | D_Z2_OUT<0> | $OpTx$FX_DC$36 | D_9_IOBUFE/D_9_IOBUFE_TRST
|
|
INPUTMC | 7 | 12 | 12 | 14 | 15 | 15 | 0 | 14 | 17 | 3 | 0 | 14 | 10 | 0 | 12
|
|
EQ | 5 |
|
|
D<12> = Z3_DATA<28> & Z3_DATA<9>/Z3_DATA<9>_TRST
|
|
# D_OUT<4> & $OpTx$FX_SC$66
|
|
# D_Z2_OUT<0> & !Z3_DATA<9>/Z3_DATA<9>_TRST &
|
|
!$OpTx$FX_DC$36;
|
|
D<12>.OE = D_9_IOBUFE/D_9_IOBUFE_TRST;
|
|
|
|
MACROCELL | 6 | 2 | D_13_IOBUFE
|
|
ATTRIBUTES | 265986 | 0
|
|
OUTPUTMC | 1 | 6 | 1
|
|
INPUTS | 8 | D_OUT<5> | $OpTx$FX_SC$66 | CP_BASEADR<6> | A<22>.PIN | CP_BASEADR<7> | A<23>.PIN | D_9_IOBUFE/D_9_IOBUFE_TRST | EXP24_.EXP
|
|
INPUTMC | 6 | 4 | 17 | 14 | 15 | 3 | 9 | 7 | 15 | 0 | 12 | 6 | 3
|
|
INPUTP | 2 | 162 | 161
|
|
EXPORTS | 1 | 6 | 1
|
|
IMPORTS | 1 | 6 | 3
|
|
EQ | 9 |
|
|
D<13> = D_OUT<5> & $OpTx$FX_SC$66
|
|
;Imported pterms FB7_4
|
|
# Z3_DATA<29> & Z3_DATA<9>/Z3_DATA<9>_TRST
|
|
# D_Z2_OUT<1> & !Z3_DATA<9>/Z3_DATA<9>_TRST &
|
|
!$OpTx$FX_DC$36;
|
|
D<13>.OE = D_9_IOBUFE/D_9_IOBUFE_TRST;
|
|
D_13_IOBUFE.EXP = CP_BASEADR<6> & !A<22>.PIN
|
|
# !CP_BASEADR<6> & A<22>.PIN
|
|
# CP_BASEADR<7> & !A<23>.PIN
|
|
|
|
MACROCELL | 6 | 4 | D_14_IOBUFE
|
|
ATTRIBUTES | 265986 | 0
|
|
INPUTS | 7 | D_OUT<6> | $OpTx$FX_SC$66 | Z3_DATA<30> | Z3_DATA<9>/Z3_DATA<9>_TRST | D_Z2_OUT<2> | $OpTx$FX_DC$36 | D_9_IOBUFE/D_9_IOBUFE_TRST
|
|
INPUTMC | 7 | 4 | 15 | 14 | 15 | 10 | 0 | 14 | 17 | 3 | 6 | 14 | 10 | 0 | 12
|
|
EQ | 5 |
|
|
D<14> = Z3_DATA<30> & Z3_DATA<9>/Z3_DATA<9>_TRST
|
|
# D_OUT<6> & $OpTx$FX_SC$66
|
|
# D_Z2_OUT<2> & !Z3_DATA<9>/Z3_DATA<9>_TRST &
|
|
!$OpTx$FX_DC$36;
|
|
D<14>.OE = D_9_IOBUFE/D_9_IOBUFE_TRST;
|
|
|
|
MACROCELL | 6 | 11 | D_15_IOBUFE
|
|
ATTRIBUTES | 265986 | 0
|
|
INPUTS | 7 | D_OUT<7> | $OpTx$FX_SC$66 | Z3_DATA<31> | Z3_DATA<9>/Z3_DATA<9>_TRST | D_Z2_OUT<3> | $OpTx$FX_DC$36 | D_9_IOBUFE/D_9_IOBUFE_TRST
|
|
INPUTMC | 7 | 12 | 3 | 14 | 15 | 14 | 6 | 14 | 17 | 3 | 3 | 14 | 10 | 0 | 12
|
|
EQ | 5 |
|
|
D<15> = Z3_DATA<31> & Z3_DATA<9>/Z3_DATA<9>_TRST
|
|
# D_OUT<7> & $OpTx$FX_SC$66
|
|
# D_Z2_OUT<3> & !Z3_DATA<9>/Z3_DATA<9>_TRST &
|
|
!$OpTx$FX_DC$36;
|
|
D<15>.OE = D_9_IOBUFE/D_9_IOBUFE_TRST;
|
|
|
|
MACROCELL | 1 | 14 | D_1_IOBUFE
|
|
ATTRIBUTES | 265986 | 0
|
|
INPUTS | 3 | Z3_DATA<17> | Z3_DATA<9>/Z3_DATA<9>_TRST | D_9_IOBUFE/D_9_IOBUFE_TRST
|
|
INPUTMC | 3 | 15 | 13 | 14 | 17 | 0 | 12
|
|
EQ | 2 |
|
|
!D<1> = !Z3_DATA<17> & Z3_DATA<9>/Z3_DATA<9>_TRST;
|
|
D<1>.OE = D_9_IOBUFE/D_9_IOBUFE_TRST;
|
|
|
|
MACROCELL | 4 | 9 | D_2_IOBUFE
|
|
ATTRIBUTES | 265986 | 0
|
|
INPUTS | 3 | Z3_DATA<18> | Z3_DATA<9>/Z3_DATA<9>_TRST | D_9_IOBUFE/D_9_IOBUFE_TRST
|
|
INPUTMC | 3 | 15 | 17 | 14 | 17 | 0 | 12
|
|
EQ | 2 |
|
|
!D<2> = !Z3_DATA<18> & Z3_DATA<9>/Z3_DATA<9>_TRST;
|
|
D<2>.OE = D_9_IOBUFE/D_9_IOBUFE_TRST;
|
|
|
|
MACROCELL | 1 | 11 | D_3_IOBUFE
|
|
ATTRIBUTES | 265986 | 0
|
|
INPUTS | 3 | Z3_DATA<19> | Z3_DATA<9>/Z3_DATA<9>_TRST | D_9_IOBUFE/D_9_IOBUFE_TRST
|
|
INPUTMC | 3 | 15 | 12 | 14 | 17 | 0 | 12
|
|
EQ | 2 |
|
|
!D<3> = !Z3_DATA<19> & Z3_DATA<9>/Z3_DATA<9>_TRST;
|
|
D<3>.OE = D_9_IOBUFE/D_9_IOBUFE_TRST;
|
|
|
|
MACROCELL | 0 | 5 | D_4_IOBUFE
|
|
ATTRIBUTES | 265986 | 0
|
|
INPUTS | 3 | Z3_DATA<20> | Z3_DATA<9>/Z3_DATA<9>_TRST | D_9_IOBUFE/D_9_IOBUFE_TRST
|
|
INPUTMC | 3 | 15 | 11 | 14 | 17 | 0 | 12
|
|
EQ | 2 |
|
|
!D<4> = !Z3_DATA<20> & Z3_DATA<9>/Z3_DATA<9>_TRST;
|
|
D<4>.OE = D_9_IOBUFE/D_9_IOBUFE_TRST;
|
|
|
|
MACROCELL | 0 | 4 | D_5_IOBUFE
|
|
ATTRIBUTES | 265986 | 0
|
|
INPUTS | 3 | Z3_DATA<21> | Z3_DATA<9>/Z3_DATA<9>_TRST | D_9_IOBUFE/D_9_IOBUFE_TRST
|
|
INPUTMC | 3 | 10 | 5 | 14 | 17 | 0 | 12
|
|
EQ | 2 |
|
|
!D<5> = !Z3_DATA<21> & Z3_DATA<9>/Z3_DATA<9>_TRST;
|
|
D<5>.OE = D_9_IOBUFE/D_9_IOBUFE_TRST;
|
|
|
|
MACROCELL | 1 | 9 | D_6_IOBUFE
|
|
ATTRIBUTES | 265986 | 0
|
|
INPUTS | 3 | Z3_DATA<22> | Z3_DATA<9>/Z3_DATA<9>_TRST | D_9_IOBUFE/D_9_IOBUFE_TRST
|
|
INPUTMC | 3 | 10 | 3 | 14 | 17 | 0 | 12
|
|
EQ | 2 |
|
|
!D<6> = !Z3_DATA<22> & Z3_DATA<9>/Z3_DATA<9>_TRST;
|
|
D<6>.OE = D_9_IOBUFE/D_9_IOBUFE_TRST;
|
|
|
|
MACROCELL | 1 | 13 | D_7_IOBUFE
|
|
ATTRIBUTES | 265986 | 0
|
|
INPUTS | 3 | Z3_DATA<23> | Z3_DATA<9>/Z3_DATA<9>_TRST | D_9_IOBUFE/D_9_IOBUFE_TRST
|
|
INPUTMC | 3 | 14 | 5 | 14 | 17 | 0 | 12
|
|
EQ | 2 |
|
|
!D<7> = !Z3_DATA<23> & Z3_DATA<9>/Z3_DATA<9>_TRST;
|
|
D<7>.OE = D_9_IOBUFE/D_9_IOBUFE_TRST;
|
|
|
|
MACROCELL | 1 | 16 | D_8_IOBUFE
|
|
ATTRIBUTES | 265986 | 0
|
|
INPUTS | 5 | Z3_DATA<24> | Z3_DATA<9>/Z3_DATA<9>_TRST | D_OUT<0> | $OpTx$FX_DC$36 | D_9_IOBUFE/D_9_IOBUFE_TRST
|
|
INPUTMC | 5 | 15 | 8 | 14 | 17 | 12 | 5 | 14 | 10 | 0 | 12
|
|
EQ | 4 |
|
|
!D<8> = !Z3_DATA<24> & Z3_DATA<9>/Z3_DATA<9>_TRST
|
|
# !D_OUT<0> & !Z3_DATA<9>/Z3_DATA<9>_TRST &
|
|
$OpTx$FX_DC$36;
|
|
D<8>.OE = D_9_IOBUFE/D_9_IOBUFE_TRST;
|
|
|
|
MACROCELL | 4 | 11 | D_9_IOBUFE
|
|
ATTRIBUTES | 265986 | 0
|
|
INPUTS | 5 | Z3_DATA<25> | Z3_DATA<9>/Z3_DATA<9>_TRST | D_OUT<1> | $OpTx$FX_DC$36 | D_9_IOBUFE/D_9_IOBUFE_TRST
|
|
INPUTMC | 5 | 15 | 6 | 14 | 17 | 12 | 14 | 14 | 10 | 0 | 12
|
|
EQ | 4 |
|
|
!D<9> = !Z3_DATA<25> & Z3_DATA<9>/Z3_DATA<9>_TRST
|
|
# !D_OUT<1> & !Z3_DATA<9>/Z3_DATA<9>_TRST &
|
|
$OpTx$FX_DC$36;
|
|
D<9>.OE = D_9_IOBUFE/D_9_IOBUFE_TRST;
|
|
|
|
MACROCELL | 9 | 2 | DQ_0_IOBUFE
|
|
ATTRIBUTES | 265986 | 0
|
|
INPUTS | 3 | RESET | DQ_DATA<0> | DQ_5_IOBUFE/DQ_5_IOBUFE_TRST
|
|
INPUTMC | 2 | 10 | 17 | 0 | 1
|
|
INPUTP | 1 | 263
|
|
EQ | 2 |
|
|
DQ<0> = RESET & DQ_DATA<0>;
|
|
DQ<0>.OE = DQ_5_IOBUFE/DQ_5_IOBUFE_TRST;
|
|
|
|
MACROCELL | 7 | 1 | DQ_12_IOBUFE
|
|
ATTRIBUTES | 265986 | 0
|
|
OUTPUTMC | 1 | 7 | 0
|
|
INPUTS | 4 | RESET | DQ_DATA<12> | DQ_5_IOBUFE/DQ_5_IOBUFE_TRST | LAN_BASEADR<11>
|
|
INPUTMC | 3 | 14 | 1 | 0 | 1 | 1 | 12
|
|
INPUTP | 1 | 263
|
|
EXPORTS | 1 | 7 | 0
|
|
EQ | 3 |
|
|
DQ<12> = RESET & DQ_DATA<12>;
|
|
DQ<12>.OE = DQ_5_IOBUFE/DQ_5_IOBUFE_TRST;
|
|
DQ_12_IOBUFE.EXP = LAN_BASEADR<11>
|
|
|
|
MACROCELL | 11 | 7 | DQ_13_IOBUFE
|
|
ATTRIBUTES | 265986 | 0
|
|
INPUTS | 3 | RESET | DQ_DATA<13> | DQ_5_IOBUFE/DQ_5_IOBUFE_TRST
|
|
INPUTMC | 2 | 8 | 0 | 0 | 1
|
|
INPUTP | 1 | 263
|
|
EQ | 2 |
|
|
DQ<13> = RESET & DQ_DATA<13>;
|
|
DQ<13>.OE = DQ_5_IOBUFE/DQ_5_IOBUFE_TRST;
|
|
|
|
MACROCELL | 7 | 2 | DQ_14_IOBUFE
|
|
ATTRIBUTES | 265986 | 0
|
|
INPUTS | 3 | RESET | DQ_DATA<14> | DQ_5_IOBUFE/DQ_5_IOBUFE_TRST
|
|
INPUTMC | 2 | 8 | 1 | 0 | 1
|
|
INPUTP | 1 | 263
|
|
EQ | 2 |
|
|
DQ<14> = RESET & DQ_DATA<14>;
|
|
DQ<14>.OE = DQ_5_IOBUFE/DQ_5_IOBUFE_TRST;
|
|
|
|
MACROCELL | 11 | 4 | DQ_15_IOBUFE
|
|
ATTRIBUTES | 265986 | 0
|
|
INPUTS | 3 | RESET | DQ_DATA<15> | DQ_5_IOBUFE/DQ_5_IOBUFE_TRST
|
|
INPUTMC | 2 | 8 | 2 | 0 | 1
|
|
INPUTP | 1 | 263
|
|
EQ | 2 |
|
|
DQ<15> = RESET & DQ_DATA<15>;
|
|
DQ<15>.OE = DQ_5_IOBUFE/DQ_5_IOBUFE_TRST;
|
|
|
|
MACROCELL | 9 | 5 | DQ_2_IOBUFE
|
|
ATTRIBUTES | 265986 | 0
|
|
INPUTS | 3 | RESET | DQ_DATA<2> | DQ_5_IOBUFE/DQ_5_IOBUFE_TRST
|
|
INPUTMC | 2 | 12 | 16 | 0 | 1
|
|
INPUTP | 1 | 263
|
|
EQ | 2 |
|
|
DQ<2> = RESET & DQ_DATA<2>;
|
|
DQ<2>.OE = DQ_5_IOBUFE/DQ_5_IOBUFE_TRST;
|
|
|
|
MACROCELL | 9 | 4 | DQ_3_IOBUFE
|
|
ATTRIBUTES | 265986 | 0
|
|
INPUTS | 3 | RESET | DQ_DATA<3> | DQ_5_IOBUFE/DQ_5_IOBUFE_TRST
|
|
INPUTMC | 2 | 14 | 2 | 0 | 1
|
|
INPUTP | 1 | 263
|
|
EQ | 2 |
|
|
DQ<3> = RESET & DQ_DATA<3>;
|
|
DQ<3>.OE = DQ_5_IOBUFE/DQ_5_IOBUFE_TRST;
|
|
|
|
MACROCELL | 9 | 7 | DQ_5_IOBUFE
|
|
ATTRIBUTES | 265986 | 0
|
|
INPUTS | 3 | RESET | DQ_DATA<5> | DQ_5_IOBUFE/DQ_5_IOBUFE_TRST
|
|
INPUTMC | 2 | 8 | 3 | 0 | 1
|
|
INPUTP | 1 | 263
|
|
EQ | 2 |
|
|
DQ<5> = RESET & DQ_DATA<5>;
|
|
DQ<5>.OE = DQ_5_IOBUFE/DQ_5_IOBUFE_TRST;
|
|
|
|
MACROCELL | 9 | 11 | DQ_6_IOBUFE
|
|
ATTRIBUTES | 265986 | 0
|
|
INPUTS | 3 | RESET | DQ_DATA<6> | DQ_5_IOBUFE/DQ_5_IOBUFE_TRST
|
|
INPUTMC | 2 | 8 | 4 | 0 | 1
|
|
INPUTP | 1 | 263
|
|
EQ | 2 |
|
|
DQ<6> = RESET & DQ_DATA<6>;
|
|
DQ<6>.OE = DQ_5_IOBUFE/DQ_5_IOBUFE_TRST;
|
|
|
|
MACROCELL | 9 | 10 | DQ_7_IOBUFE
|
|
ATTRIBUTES | 265986 | 0
|
|
INPUTS | 3 | RESET | DQ_DATA<7> | DQ_5_IOBUFE/DQ_5_IOBUFE_TRST
|
|
INPUTMC | 2 | 8 | 5 | 0 | 1
|
|
INPUTP | 1 | 263
|
|
EQ | 2 |
|
|
DQ<7> = RESET & DQ_DATA<7>;
|
|
DQ<7>.OE = DQ_5_IOBUFE/DQ_5_IOBUFE_TRST;
|
|
|
|
MACROCELL | 0 | 15 | DQ_SWAP
|
|
ATTRIBUTES | 8520608 | 0
|
|
OUTPUTMC | 56 | 8 | 10 | 15 | 5 | 15 | 2 | 15 | 1 | 14 | 16 | 14 | 14 | 14 | 13 | 8 | 13 | 8 | 16 | 10 | 2 | 10 | 4 | 10 | 9 | 10 | 10 | 12 | 7 | 15 | 10 | 15 | 7 | 15 | 14 | 15 | 13 | 15 | 17 | 15 | 12 | 15 | 11 | 10 | 5 | 10 | 3 | 14 | 5 | 15 | 8 | 15 | 6 | 15 | 4 | 15 | 3 | 15 | 0 | 10 | 1 | 10 | 0 | 14 | 6 | 10 | 17 | 10 | 15 | 14 | 0 | 14 | 1 | 8 | 0 | 8 | 1 | 8 | 2 | 12 | 17 | 12 | 16 | 14 | 2 | 14 | 3 | 8 | 3 | 8 | 4 | 8 | 5 | 10 | 14 | 12 | 15 | 8 | 6 | 8 | 17 | 10 | 13 | 10 | 16 | 12 | 0 | 12 | 14 | 14 | 4 | 14 | 17
|
|
INPUTS | 15 | Z3 | D<12>.PIN | LAN_BASEADR<12> | SHUT_UP | A<13>.PIN | A<14>.PIN | $OpTx$FX_DC$62 | $OpTx$FX_DC$61 | $OpTx$FX_DC$60 | $OpTx$FX_DC$59 | $OpTx$FX_DC$63 | $OpTx$INV$5 | $OpTx$INV$4 | FCS | RESET
|
|
INPUTMC | 9 | 1 | 10 | 1 | 0 | 5 | 15 | 5 | 16 | 5 | 17 | 7 | 0 | 5 | 14 | 8 | 6 | 13 | 0
|
|
INPUTP | 6 | 151 | 78 | 123 | 125 | 147 | 263
|
|
EQ | 10 |
|
|
!DQ_SWAP.D = Z3 & D<12>.PIN & LAN_BASEADR<12> & !SHUT_UP &
|
|
A<13>.PIN & A<14>.PIN & !$OpTx$FX_DC$62 & !$OpTx$FX_DC$61 &
|
|
!$OpTx$FX_DC$60 & !$OpTx$FX_DC$59 & !$OpTx$FX_DC$63 & !$OpTx$INV$5 &
|
|
!$OpTx$INV$4
|
|
# Z3 & !D<12>.PIN & !LAN_BASEADR<12> & !SHUT_UP &
|
|
A<13>.PIN & A<14>.PIN & !$OpTx$FX_DC$62 & !$OpTx$FX_DC$61 &
|
|
!$OpTx$FX_DC$60 & !$OpTx$FX_DC$59 & !$OpTx$FX_DC$63 & !$OpTx$INV$5 &
|
|
!$OpTx$INV$4;
|
|
DQ_SWAP.CLK = !FCS;
|
|
DQ_SWAP.AP = !RESET;
|
|
|
|
MACROCELL | 15 | 16 | LAN_SM_FSM_FFd3
|
|
ATTRIBUTES | 8553232 | 0
|
|
OUTPUTMC | 52 | 8 | 10 | 15 | 5 | 15 | 2 | 15 | 1 | 14 | 16 | 14 | 14 | 14 | 13 | 8 | 13 | 8 | 16 | 10 | 2 | 10 | 4 | 10 | 9 | 10 | 10 | 12 | 7 | 15 | 10 | 15 | 7 | 15 | 16 | 10 | 6 | 10 | 7 | 10 | 12 | 10 | 17 | 10 | 15 | 12 | 17 | 14 | 1 | 14 | 12 | 8 | 0 | 8 | 2 | 12 | 14 | 12 | 16 | 14 | 2 | 14 | 0 | 8 | 3 | 8 | 1 | 8 | 4 | 10 | 14 | 12 | 15 | 10 | 8 | 14 | 7 | 14 | 8 | 15 | 15 | 14 | 4 | 14 | 9 | 8 | 5 | 8 | 6 | 8 | 17 | 10 | 0 | 10 | 13 | 10 | 16 | 12 | 0 | 14 | 3 | 14 | 17 | 15 | 17
|
|
INPUTS | 9 | LAN_SM_FSM_FFd3 | LAN_SM_FSM_FFd4 | LAN_SM_FSM_FFd2 | $OpTx$FX_DC$12 | RW | LAN_SM_FSM_FFd1 | $OpTx$FX_DC$10 | LAN_SM_RST | Z3_DATA<18>.EXP
|
|
INPUTMC | 8 | 15 | 16 | 10 | 6 | 10 | 7 | 5 | 8 | 10 | 12 | 5 | 10 | 11 | 0 | 15 | 17
|
|
INPUTP | 1 | 158
|
|
IMPORTS | 1 | 15 | 17
|
|
EQ | 13 |
|
|
!LAN_SM_FSM_FFd3.D = LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 &
|
|
LAN_SM_FSM_FFd2 & !$OpTx$FX_DC$12
|
|
# !RW & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 &
|
|
!LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1
|
|
# !RW & !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 &
|
|
LAN_SM_FSM_FFd1 & !$OpTx$FX_DC$12
|
|
# !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 &
|
|
LAN_SM_FSM_FFd1 & !$OpTx$FX_DC$10 & !$OpTx$FX_DC$12
|
|
;Imported pterms FB16_18
|
|
# !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 &
|
|
!LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1 & !$OpTx$FX_DC$10;
|
|
LAN_SM_FSM_FFd3.CLK = CLK_EXT; // GCK
|
|
LAN_SM_FSM_FFd3.AR = LAN_SM_RST;
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 10 | 6 | LAN_SM_FSM_FFd4
|
|
ATTRIBUTES | 8553232 | 0
|
|
OUTPUTMC | 66 | 8 | 10 | 15 | 5 | 15 | 2 | 15 | 1 | 14 | 16 | 14 | 14 | 14 | 13 | 8 | 13 | 8 | 16 | 10 | 2 | 10 | 4 | 10 | 9 | 10 | 10 | 12 | 7 | 15 | 10 | 15 | 7 | 15 | 14 | 15 | 13 | 15 | 17 | 15 | 12 | 15 | 11 | 10 | 5 | 10 | 3 | 14 | 5 | 15 | 8 | 15 | 6 | 15 | 4 | 15 | 3 | 15 | 0 | 10 | 1 | 10 | 0 | 14 | 6 | 15 | 16 | 10 | 6 | 10 | 7 | 10 | 12 | 10 | 17 | 10 | 15 | 12 | 17 | 14 | 1 | 14 | 12 | 8 | 0 | 8 | 2 | 12 | 14 | 12 | 16 | 14 | 2 | 14 | 0 | 8 | 3 | 8 | 1 | 8 | 4 | 10 | 14 | 12 | 15 | 10 | 8 | 14 | 7 | 14 | 8 | 15 | 15 | 14 | 4 | 14 | 9 | 8 | 5 | 8 | 6 | 8 | 17 | 10 | 13 | 10 | 16 | 12 | 0 | 14 | 3 | 14 | 17
|
|
INPUTS | 7 | LAN_SM_FSM_FFd3 | $OpTx$FX_DC$57 | LAN_SM_FSM_FFd4 | BUF_LAN_READY | LAN_SM_FSM_FFd2 | LAN_SM_FSM_FFd1 | LAN_SM_RST
|
|
INPUTMC | 7 | 15 | 16 | 5 | 3 | 10 | 6 | 14 | 4 | 10 | 7 | 10 | 12 | 11 | 0
|
|
EQ | 6 |
|
|
LAN_SM_FSM_FFd4.D = !LAN_SM_FSM_FFd3 & !$OpTx$FX_DC$57
|
|
# !LAN_SM_FSM_FFd4 & !BUF_LAN_READY
|
|
# LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 &
|
|
LAN_SM_FSM_FFd1;
|
|
LAN_SM_FSM_FFd4.CLK = CLK_EXT; // GCK
|
|
LAN_SM_FSM_FFd4.AR = LAN_SM_RST;
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 10 | 7 | LAN_SM_FSM_FFd2
|
|
ATTRIBUTES | 4358928 | 0
|
|
OUTPUTMC | 44 | 8 | 10 | 15 | 5 | 15 | 2 | 15 | 1 | 14 | 16 | 14 | 14 | 14 | 13 | 8 | 13 | 8 | 16 | 10 | 2 | 10 | 4 | 10 | 9 | 10 | 10 | 12 | 7 | 15 | 10 | 15 | 7 | 15 | 14 | 15 | 13 | 15 | 17 | 15 | 12 | 15 | 11 | 10 | 5 | 10 | 3 | 14 | 5 | 15 | 8 | 15 | 6 | 15 | 4 | 15 | 3 | 15 | 0 | 10 | 1 | 10 | 0 | 14 | 6 | 15 | 16 | 10 | 6 | 10 | 7 | 10 | 12 | 10 | 8 | 14 | 7 | 14 | 8 | 15 | 15 | 5 | 3 | 14 | 4 | 14 | 9 | 14 | 12
|
|
INPUTS | 7 | LAN_SM_FSM_FFd3 | LAN_SM_FSM_FFd4 | LAN_SM_FSM_FFd2 | $OpTx$FX_DC$10 | $OpTx$FX_DC$12 | LAN_SM_FSM_FFd1 | LAN_SM_RST
|
|
INPUTMC | 7 | 15 | 16 | 10 | 6 | 10 | 7 | 5 | 10 | 5 | 8 | 10 | 12 | 11 | 0
|
|
EQ | 8 |
|
|
LAN_SM_FSM_FFd2.T = LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 &
|
|
LAN_SM_FSM_FFd2 & !$OpTx$FX_DC$12
|
|
# !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 &
|
|
!LAN_SM_FSM_FFd2 & !$OpTx$FX_DC$10
|
|
# !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 &
|
|
LAN_SM_FSM_FFd1 & $OpTx$FX_DC$10 & !$OpTx$FX_DC$12;
|
|
LAN_SM_FSM_FFd2.CLK = CLK_EXT; // GCK
|
|
LAN_SM_FSM_FFd2.AR = LAN_SM_RST;
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 10 | 12 | LAN_SM_FSM_FFd1
|
|
ATTRIBUTES | 8553232 | 0
|
|
OUTPUTMC | 43 | 8 | 10 | 15 | 5 | 15 | 2 | 15 | 1 | 14 | 16 | 14 | 14 | 14 | 13 | 8 | 13 | 8 | 16 | 10 | 2 | 10 | 4 | 10 | 9 | 10 | 10 | 12 | 7 | 15 | 10 | 15 | 7 | 15 | 14 | 15 | 13 | 15 | 17 | 15 | 12 | 15 | 11 | 10 | 5 | 10 | 3 | 14 | 5 | 15 | 8 | 15 | 6 | 15 | 4 | 15 | 3 | 15 | 0 | 10 | 1 | 10 | 0 | 14 | 6 | 15 | 16 | 10 | 6 | 10 | 7 | 10 | 12 | 10 | 8 | 14 | 7 | 14 | 8 | 15 | 15 | 14 | 4 | 14 | 9 | 14 | 12
|
|
INPUTS | 8 | LAN_SM_FSM_FFd3 | LAN_SM_FSM_FFd2 | LAN_SM_FSM_FFd1 | RW | LAN_SM_FSM_FFd4 | BUF_LAN_READY | $OpTx$FX_DC$57 | LAN_SM_RST
|
|
INPUTMC | 7 | 15 | 16 | 10 | 7 | 10 | 12 | 10 | 6 | 14 | 4 | 5 | 3 | 11 | 0
|
|
INPUTP | 1 | 158
|
|
EQ | 8 |
|
|
LAN_SM_FSM_FFd1.D = LAN_SM_FSM_FFd1 & !$OpTx$FX_DC$57
|
|
# !RW & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4
|
|
# !LAN_SM_FSM_FFd3 & LAN_SM_FSM_FFd2 &
|
|
!LAN_SM_FSM_FFd1
|
|
# LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 &
|
|
!LAN_SM_FSM_FFd1 & !BUF_LAN_READY;
|
|
LAN_SM_FSM_FFd1.CLK = CLK_EXT; // GCK
|
|
LAN_SM_FSM_FFd1.AR = LAN_SM_RST;
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 13 | 16 | Z3_ADR<2>
|
|
ATTRIBUTES | 8520608 | 0
|
|
OUTPUTMC | 26 | 12 | 10 | 1 | 17 | 1 | 15 | 1 | 12 | 1 | 10 | 1 | 8 | 1 | 6 | 4 | 12 | 4 | 10 | 4 | 8 | 4 | 7 | 4 | 6 | 4 | 5 | 4 | 3 | 4 | 2 | 4 | 0 | 1 | 3 | 1 | 0 | 12 | 5 | 12 | 14 | 12 | 9 | 12 | 12 | 4 | 17 | 4 | 15 | 3 | 7 | 13 | 17
|
|
INPUTS | 5 | A<4> | FCS | RESET | D<14>.PIN | LAN_BASEADR<14>
|
|
INPUTMC | 1 | 1 | 6
|
|
INPUTP | 4 | 97 | 147 | 263 | 81
|
|
EXPORTS | 1 | 13 | 17
|
|
EQ | 5 |
|
|
Z3_ADR<2>.D = A<4>;
|
|
Z3_ADR<2>.CLK = !FCS;
|
|
Z3_ADR<2>.AP = !RESET;
|
|
Z3_ADR<2>.EXP = D<14>.PIN & !LAN_BASEADR<14>
|
|
# !D<14>.PIN & LAN_BASEADR<14>
|
|
|
|
MACROCELL | 13 | 7 | Z3_ADR_1
|
|
ATTRIBUTES | 8520608 | 0
|
|
OUTPUTMC | 26 | 1 | 17 | 1 | 15 | 1 | 12 | 1 | 10 | 1 | 8 | 1 | 6 | 4 | 12 | 4 | 10 | 4 | 8 | 4 | 7 | 4 | 6 | 4 | 5 | 4 | 3 | 4 | 2 | 4 | 0 | 1 | 3 | 1 | 0 | 12 | 5 | 12 | 14 | 12 | 9 | 12 | 4 | 12 | 12 | 4 | 17 | 4 | 15 | 12 | 3 | 3 | 11
|
|
INPUTS | 3 | A<3> | FCS | RESET
|
|
INPUTP | 3 | 99 | 147 | 263
|
|
EQ | 3 |
|
|
Z3_ADR_1.D = A<3>;
|
|
Z3_ADR_1.CLK = !FCS;
|
|
Z3_ADR_1.AP = !RESET;
|
|
|
|
MACROCELL | 13 | 8 | Z3_ADR_0
|
|
ATTRIBUTES | 8520608 | 0
|
|
OUTPUTMC | 25 | 12 | 10 | 1 | 17 | 1 | 15 | 1 | 12 | 1 | 10 | 1 | 8 | 1 | 6 | 4 | 12 | 4 | 10 | 4 | 8 | 4 | 7 | 4 | 6 | 4 | 5 | 4 | 3 | 4 | 2 | 4 | 0 | 1 | 3 | 1 | 0 | 12 | 5 | 12 | 14 | 12 | 9 | 12 | 12 | 4 | 17 | 4 | 15 | 3 | 4
|
|
INPUTS | 3 | A<2> | FCS | RESET
|
|
INPUTP | 3 | 101 | 147 | 263
|
|
EQ | 3 |
|
|
Z3_ADR_0.D = A<2>;
|
|
Z3_ADR_0.CLK = !FCS;
|
|
Z3_ADR_0.AP = !RESET;
|
|
|
|
MACROCELL | 11 | 13 | LAN_RST_SM_FSM_FFd3
|
|
ATTRIBUTES | 4358928 | 0
|
|
OUTPUTMC | 6 | 11 | 13 | 11 | 14 | 11 | 15 | 11 | 12 | 11 | 17 | 11 | 10
|
|
INPUTS | 4 | LAN_RST_SM_FSM_FFd3 | LAN_RST_SM_FSM_FFd2 | LAN_RST_SM_FSM_FFd1 | RESET
|
|
INPUTMC | 3 | 11 | 13 | 11 | 14 | 11 | 15
|
|
INPUTP | 1 | 263
|
|
EQ | 6 |
|
|
LAN_RST_SM_FSM_FFd3.T = LAN_RST_SM_FSM_FFd3 & LAN_RST_SM_FSM_FFd2 &
|
|
!LAN_RST_SM_FSM_FFd1
|
|
# !LAN_RST_SM_FSM_FFd3 & !LAN_RST_SM_FSM_FFd2 &
|
|
LAN_RST_SM_FSM_FFd1;
|
|
LAN_RST_SM_FSM_FFd3.CLK = CLK_EXT; // GCK
|
|
LAN_RST_SM_FSM_FFd3.AR = RESET;
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 11 | 14 | LAN_RST_SM_FSM_FFd2
|
|
ATTRIBUTES | 8553232 | 0
|
|
OUTPUTMC | 6 | 11 | 13 | 11 | 14 | 11 | 15 | 11 | 12 | 11 | 17 | 11 | 10
|
|
INPUTS | 4 | LAN_RST_SM_FSM_FFd3 | LAN_RST_SM_FSM_FFd2 | LAN_RST_SM_FSM_FFd1 | RESET
|
|
INPUTMC | 3 | 11 | 13 | 11 | 14 | 11 | 15
|
|
INPUTP | 1 | 263
|
|
EQ | 5 |
|
|
!LAN_RST_SM_FSM_FFd2.D = !LAN_RST_SM_FSM_FFd3 & !LAN_RST_SM_FSM_FFd2
|
|
# LAN_RST_SM_FSM_FFd3 & LAN_RST_SM_FSM_FFd2 &
|
|
LAN_RST_SM_FSM_FFd1;
|
|
LAN_RST_SM_FSM_FFd2.CLK = CLK_EXT; // GCK
|
|
LAN_RST_SM_FSM_FFd2.AR = RESET;
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 13 | 9 | Z3_ADR<6>
|
|
ATTRIBUTES | 8520608 | 0
|
|
OUTPUTMC | 23 | 12 | 10 | 1 | 17 | 1 | 15 | 1 | 12 | 1 | 10 | 1 | 8 | 1 | 6 | 4 | 12 | 4 | 10 | 4 | 8 | 4 | 7 | 4 | 6 | 4 | 5 | 4 | 3 | 4 | 2 | 4 | 0 | 1 | 3 | 1 | 0 | 12 | 12 | 4 | 17 | 4 | 15 | 12 | 3 | 1 | 2
|
|
INPUTS | 3 | A<8>.PIN | FCS | RESET
|
|
INPUTP | 3 | 106 | 147 | 263
|
|
EQ | 3 |
|
|
Z3_ADR<6>.D = A<8>.PIN;
|
|
Z3_ADR<6>.CLK = !FCS;
|
|
Z3_ADR<6>.AP = !RESET;
|
|
|
|
MACROCELL | 11 | 15 | LAN_RST_SM_FSM_FFd1
|
|
ATTRIBUTES | 8553232 | 0
|
|
OUTPUTMC | 6 | 11 | 13 | 11 | 14 | 11 | 15 | 11 | 12 | 11 | 17 | 11 | 10
|
|
INPUTS | 4 | LAN_RST_SM_FSM_FFd3 | LAN_RST_SM_FSM_FFd2 | LAN_RST_SM_FSM_FFd1 | RESET
|
|
INPUTMC | 3 | 11 | 13 | 11 | 14 | 11 | 15
|
|
INPUTP | 1 | 263
|
|
EQ | 4 |
|
|
LAN_RST_SM_FSM_FFd1.D = !LAN_RST_SM_FSM_FFd3
|
|
# !LAN_RST_SM_FSM_FFd2 & LAN_RST_SM_FSM_FFd1;
|
|
LAN_RST_SM_FSM_FFd1.CLK = CLK_EXT; // GCK
|
|
LAN_RST_SM_FSM_FFd1.AR = RESET;
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 0 | 8 | LAN_ACCESS
|
|
ATTRIBUTES | 8520496 | 0
|
|
OUTPUTMC | 4 | 7 | 7 | 13 | 6 | 13 | 1 | 13 | 5
|
|
INPUTS | 13 | Z3 | D<12>.PIN | LAN_BASEADR<12> | SHUT_UP | $OpTx$FX_DC$62 | $OpTx$FX_DC$61 | $OpTx$FX_DC$60 | $OpTx$FX_DC$59 | $OpTx$FX_DC$63 | $OpTx$INV$5 | $OpTx$INV$4 | FCS | RESET
|
|
INPUTMC | 9 | 1 | 10 | 1 | 0 | 5 | 15 | 5 | 16 | 5 | 17 | 7 | 0 | 5 | 14 | 8 | 6 | 13 | 0
|
|
INPUTP | 4 | 151 | 78 | 147 | 263
|
|
EQ | 8 |
|
|
LAN_ACCESS.D = Z3 & D<12>.PIN & LAN_BASEADR<12> & !SHUT_UP &
|
|
!$OpTx$FX_DC$62 & !$OpTx$FX_DC$61 & !$OpTx$FX_DC$60 & !$OpTx$FX_DC$59 &
|
|
!$OpTx$FX_DC$63 & !$OpTx$INV$5 & !$OpTx$INV$4
|
|
# Z3 & !D<12>.PIN & !LAN_BASEADR<12> & !SHUT_UP &
|
|
!$OpTx$FX_DC$62 & !$OpTx$FX_DC$61 & !$OpTx$FX_DC$60 & !$OpTx$FX_DC$59 &
|
|
!$OpTx$FX_DC$63 & !$OpTx$INV$5 & !$OpTx$INV$4;
|
|
LAN_ACCESS.CLK = !FCS;
|
|
LAN_ACCESS.AR = !RESET;
|
|
|
|
MACROCELL | 9 | 17 | AUTOCONFIG_Z2_ACCESS
|
|
ATTRIBUTES | 8520496 | 0
|
|
OUTPUTMC | 3 | 13 | 13 | 0 | 0 | 0 | 12
|
|
INPUTS | 13 | CFIN | A<20>.PIN | A<19>.PIN | A<18>.PIN | A<17>.PIN | A<16>.PIN | AUTO_CONFIG_Z2_DONE<0> | A<23>.PIN | A<22>.PIN | A<21>.PIN | AUTO_CONFIG_Z2_DONE<1> | AS | RESET
|
|
INPUTMC | 2 | 9 | 15 | 9 | 14
|
|
INPUTP | 11 | 190 | 167 | 169 | 171 | 172 | 175 | 161 | 162 | 163 | 152 | 263
|
|
EQ | 8 |
|
|
AUTOCONFIG_Z2_ACCESS.D = !CFIN & !A<20>.PIN & A<19>.PIN & !A<18>.PIN &
|
|
!A<17>.PIN & !A<16>.PIN & !AUTO_CONFIG_Z2_DONE<0> & A<23>.PIN &
|
|
A<22>.PIN & A<21>.PIN
|
|
# !CFIN & !A<20>.PIN & A<19>.PIN & !A<18>.PIN &
|
|
!A<17>.PIN & !A<16>.PIN & !AUTO_CONFIG_Z2_DONE<1> & A<23>.PIN &
|
|
A<22>.PIN & A<21>.PIN;
|
|
AUTOCONFIG_Z2_ACCESS.CLK = !AS;
|
|
AUTOCONFIG_Z2_ACCESS.AR = !RESET;
|
|
|
|
MACROCELL | 9 | 12 | AUTOCONFIG_Z3_ACCESS
|
|
ATTRIBUTES | 8520496 | 0
|
|
OUTPUTMC | 31 | 12 | 10 | 1 | 17 | 1 | 15 | 1 | 12 | 1 | 10 | 1 | 8 | 1 | 6 | 4 | 12 | 4 | 10 | 4 | 8 | 4 | 7 | 4 | 6 | 4 | 5 | 4 | 3 | 4 | 2 | 4 | 0 | 1 | 3 | 1 | 0 | 12 | 5 | 12 | 14 | 12 | 9 | 12 | 4 | 12 | 12 | 4 | 17 | 4 | 15 | 12 | 3 | 0 | 12 | 14 | 10 | 14 | 15 | 13 | 5 | 13 | 4
|
|
INPUTS | 21 | Z3 | D<9>.PIN | D<8>.PIN | D<14>.PIN | D<13>.PIN | D<12>.PIN | D<11>.PIN | D<10>.PIN | D<15>.PIN | CFIN | A<20>.PIN | A<19>.PIN | A<18>.PIN | A<17>.PIN | A<16>.PIN | AUTO_CONFIG_DONE | A<23>.PIN | A<22>.PIN | A<21>.PIN | FCS | RESET
|
|
INPUTMC | 1 | 12 | 11
|
|
INPUTP | 20 | 151 | 73 | 32 | 81 | 80 | 78 | 77 | 74 | 89 | 190 | 167 | 169 | 171 | 172 | 175 | 161 | 162 | 163 | 147 | 263
|
|
EQ | 7 |
|
|
AUTOCONFIG_Z3_ACCESS.D = Z3 & D<9>.PIN & D<8>.PIN & D<14>.PIN &
|
|
D<13>.PIN & D<12>.PIN & D<11>.PIN & D<10>.PIN & D<15>.PIN &
|
|
!CFIN & !A<20>.PIN & !A<19>.PIN & !A<18>.PIN & !A<17>.PIN &
|
|
!A<16>.PIN & !AUTO_CONFIG_DONE & !A<23>.PIN & !A<22>.PIN &
|
|
!A<21>.PIN;
|
|
AUTOCONFIG_Z3_ACCESS.CLK = !FCS;
|
|
AUTOCONFIG_Z3_ACCESS.AR = !RESET;
|
|
|
|
MACROCELL | 13 | 15 | Z3_ADR<3>
|
|
ATTRIBUTES | 8520608 | 0
|
|
OUTPUTMC | 27 | 12 | 10 | 1 | 17 | 1 | 15 | 1 | 12 | 1 | 10 | 1 | 8 | 1 | 6 | 4 | 12 | 4 | 10 | 4 | 8 | 4 | 7 | 4 | 6 | 4 | 5 | 4 | 3 | 4 | 2 | 4 | 0 | 1 | 3 | 1 | 0 | 12 | 5 | 12 | 14 | 12 | 9 | 12 | 4 | 12 | 12 | 4 | 17 | 4 | 15 | 12 | 3 | 1 | 1
|
|
INPUTS | 3 | A<5> | FCS | RESET
|
|
INPUTP | 3 | 91 | 147 | 263
|
|
EQ | 3 |
|
|
Z3_ADR<3>.D = A<5>;
|
|
Z3_ADR<3>.CLK = !FCS;
|
|
Z3_ADR<3>.AP = !RESET;
|
|
|
|
MACROCELL | 13 | 12 | Z3_ADR<4>
|
|
ATTRIBUTES | 8520608 | 0
|
|
OUTPUTMC | 27 | 12 | 10 | 1 | 17 | 1 | 15 | 1 | 12 | 1 | 10 | 1 | 8 | 1 | 6 | 4 | 12 | 4 | 10 | 4 | 8 | 4 | 7 | 4 | 6 | 4 | 5 | 4 | 3 | 4 | 2 | 4 | 0 | 1 | 3 | 1 | 0 | 12 | 5 | 12 | 14 | 12 | 9 | 12 | 4 | 12 | 12 | 4 | 17 | 4 | 15 | 12 | 3 | 3 | 12
|
|
INPUTS | 3 | A<6> | FCS | RESET
|
|
INPUTP | 3 | 98 | 147 | 263
|
|
EQ | 3 |
|
|
Z3_ADR<4>.D = A<6>;
|
|
Z3_ADR<4>.CLK = !FCS;
|
|
Z3_ADR<4>.AP = !RESET;
|
|
|
|
MACROCELL | 13 | 11 | Z3_ADR<5>
|
|
ATTRIBUTES | 8520608 | 0
|
|
OUTPUTMC | 27 | 12 | 10 | 1 | 17 | 1 | 15 | 1 | 12 | 1 | 10 | 1 | 8 | 1 | 6 | 4 | 12 | 4 | 10 | 4 | 8 | 4 | 7 | 4 | 6 | 4 | 5 | 4 | 3 | 4 | 2 | 4 | 0 | 1 | 3 | 1 | 0 | 12 | 5 | 12 | 14 | 12 | 9 | 12 | 4 | 12 | 12 | 4 | 17 | 4 | 15 | 12 | 3 | 1 | 4
|
|
INPUTS | 3 | A<7> | FCS | RESET
|
|
INPUTP | 3 | 100 | 147 | 263
|
|
EQ | 3 |
|
|
Z3_ADR<5>.D = A<7>;
|
|
Z3_ADR<5>.CLK = !FCS;
|
|
Z3_ADR<5>.AP = !RESET;
|
|
|
|
MACROCELL | 0 | 6 | IDE_ACCESS
|
|
ATTRIBUTES | 8520496 | 0
|
|
OUTPUTMC | 4 | 0 | 16 | 4 | 4 | 13 | 13 | 2 | 1
|
|
INPUTS | 3 | BUF_IDE_ACCESS | AS | RESET
|
|
INPUTMC | 1 | 7 | 17
|
|
INPUTP | 2 | 152 | 263
|
|
EQ | 3 |
|
|
!IDE_ACCESS.D = BUF_IDE_ACCESS;
|
|
IDE_ACCESS.CLK = !AS;
|
|
IDE_ACCESS.AR = !RESET;
|
|
|
|
MACROCELL | 8 | 9 | Z3_ADR<13>
|
|
ATTRIBUTES | 8520608 | 0
|
|
OUTPUTMC | 1 | 13 | 1
|
|
INPUTS | 3 | A<15>.PIN | FCS | RESET
|
|
INPUTP | 3 | 139 | 147 | 263
|
|
EQ | 3 |
|
|
Z3_ADR<13>.D = A<15>.PIN;
|
|
Z3_ADR<13>.CLK = !FCS;
|
|
Z3_ADR<13>.AP = !RESET;
|
|
|
|
MACROCELL | 11 | 5 | LAN_D_INIT<1>
|
|
ATTRIBUTES | 8553232 | 0
|
|
OUTPUTMC | 3 | 9 | 1 | 9 | 9 | 11 | 11
|
|
INPUTS | 2 | BUF_LAN_D_INIT<1> | RESET
|
|
INPUTMC | 1 | 11 | 10
|
|
INPUTP | 1 | 263
|
|
EQ | 3 |
|
|
LAN_D_INIT<1>.D = BUF_LAN_D_INIT<1>;
|
|
LAN_D_INIT<1>.CLK = CLK_EXT; // GCK
|
|
LAN_D_INIT<1>.AR = RESET;
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 11 | 3 | LAN_D_INIT<8>
|
|
ATTRIBUTES | 8553232 | 0
|
|
OUTPUTMC | 3 | 9 | 16 | 11 | 9 | 9 | 13
|
|
INPUTS | 2 | BUF_LAN_D_INIT<1> | RESET
|
|
INPUTMC | 1 | 11 | 10
|
|
INPUTP | 1 | 263
|
|
EQ | 3 |
|
|
!LAN_D_INIT<8>.D = BUF_LAN_D_INIT<1>;
|
|
LAN_D_INIT<8>.CLK = CLK_EXT; // GCK
|
|
LAN_D_INIT<8>.AR = RESET;
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 10 | 17 | DQ_DATA<0>
|
|
ATTRIBUTES | 8553344 | 0
|
|
OUTPUTMC | 2 | 9 | 2 | 10 | 17
|
|
INPUTS | 12 | DQ_DATA<0> | $OpTx$FX_DC$30 | A<16>.PIN | DQ_SWAP | $OpTx$FX_SC$31 | A<8>.PIN | D<0>.PIN | LAN_SM_FSM_FFd3 | LAN_SM_FSM_FFd4 | $OpTx$FX_DC$10 | Z3_DATA<30>.EXP | LAN_SM_RST
|
|
INPUTMC | 9 | 10 | 17 | 14 | 9 | 0 | 15 | 14 | 12 | 15 | 16 | 10 | 6 | 5 | 10 | 10 | 0 | 11 | 0
|
|
INPUTP | 3 | 175 | 106 | 4
|
|
IMPORTS | 1 | 10 | 0
|
|
EQ | 10 |
|
|
DQ_DATA<0>.D = DQ_DATA<0> & !$OpTx$FX_DC$30
|
|
# A<16>.PIN & DQ_SWAP & $OpTx$FX_SC$31
|
|
# !DQ_SWAP & A<8>.PIN & $OpTx$FX_SC$31
|
|
# D<0>.PIN & !DQ_SWAP & !LAN_SM_FSM_FFd3 &
|
|
!LAN_SM_FSM_FFd4 & !$OpTx$FX_DC$10
|
|
;Imported pterms FB11_1
|
|
# D<8>.PIN & DQ_SWAP & !LAN_SM_FSM_FFd3 &
|
|
!LAN_SM_FSM_FFd4 & !$OpTx$FX_DC$10;
|
|
DQ_DATA<0>.CLK = CLK_EXT; // GCK
|
|
DQ_DATA<0>.AP = LAN_SM_RST;
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 10 | 15 | DQ_DATA<10>
|
|
ATTRIBUTES | 8553344 | 0
|
|
OUTPUTMC | 2 | 9 | 16 | 10 | 15
|
|
INPUTS | 12 | DQ_DATA<10> | $OpTx$FX_DC$30 | DQ_SWAP | A<10>.PIN | $OpTx$FX_SC$31 | A<18>.PIN | D<10>.PIN | LAN_SM_FSM_FFd3 | LAN_SM_FSM_FFd4 | $OpTx$FX_DC$10 | CP_WE_OBUF.EXP | LAN_SM_RST
|
|
INPUTMC | 9 | 10 | 15 | 14 | 9 | 0 | 15 | 14 | 12 | 15 | 16 | 10 | 6 | 5 | 10 | 10 | 16 | 11 | 0
|
|
INPUTP | 3 | 112 | 171 | 74
|
|
IMPORTS | 1 | 10 | 16
|
|
EQ | 10 |
|
|
DQ_DATA<10>.D = DQ_DATA<10> & !$OpTx$FX_DC$30
|
|
# A<18>.PIN & !DQ_SWAP & $OpTx$FX_SC$31
|
|
# DQ_SWAP & A<10>.PIN & $OpTx$FX_SC$31
|
|
# D<10>.PIN & !DQ_SWAP & !LAN_SM_FSM_FFd3 &
|
|
!LAN_SM_FSM_FFd4 & !$OpTx$FX_DC$10
|
|
;Imported pterms FB11_17
|
|
# D<2>.PIN & DQ_SWAP & !LAN_SM_FSM_FFd3 &
|
|
!LAN_SM_FSM_FFd4 & !$OpTx$FX_DC$10;
|
|
DQ_DATA<10>.CLK = CLK_EXT; // GCK
|
|
DQ_DATA<10>.AP = LAN_SM_RST;
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 14 | 0 | DQ_DATA<11>
|
|
ATTRIBUTES | 8553344 | 0
|
|
OUTPUTMC | 3 | 11 | 9 | 14 | 0 | 14 | 1
|
|
INPUTS | 12 | DQ_DATA<11> | $OpTx$FX_DC$30 | DQ_SWAP | A<11>.PIN | $OpTx$FX_SC$31 | A<19>.PIN | D<4>.PIN | LAN_SM_FSM_FFd3 | LAN_SM_FSM_FFd4 | $OpTx$FX_DC$10 | Z3_DATA<9>/Z3_DATA<9>_TRST.EXP | LAN_SM_RST
|
|
INPUTMC | 9 | 14 | 0 | 14 | 9 | 0 | 15 | 14 | 12 | 15 | 16 | 10 | 6 | 5 | 10 | 14 | 17 | 11 | 0
|
|
INPUTP | 3 | 114 | 169 | 38
|
|
EXPORTS | 1 | 14 | 1
|
|
IMPORTS | 1 | 14 | 17
|
|
EQ | 12 |
|
|
DQ_DATA<11>.D = DQ_DATA<11> & !$OpTx$FX_DC$30
|
|
# A<19>.PIN & !DQ_SWAP & $OpTx$FX_SC$31
|
|
# DQ_SWAP & A<11>.PIN & $OpTx$FX_SC$31
|
|
;Imported pterms FB15_18
|
|
# D<11>.PIN & !DQ_SWAP & !LAN_SM_FSM_FFd3 &
|
|
!LAN_SM_FSM_FFd4 & !$OpTx$FX_DC$10
|
|
# D<3>.PIN & DQ_SWAP & !LAN_SM_FSM_FFd3 &
|
|
!LAN_SM_FSM_FFd4 & !$OpTx$FX_DC$10;
|
|
DQ_DATA<11>.CLK = CLK_EXT; // GCK
|
|
DQ_DATA<11>.AP = LAN_SM_RST;
|
|
DQ_DATA<11>.EXP = D<4>.PIN & DQ_SWAP & !LAN_SM_FSM_FFd3 &
|
|
!LAN_SM_FSM_FFd4 & !$OpTx$FX_DC$10
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 14 | 1 | DQ_DATA<12>
|
|
ATTRIBUTES | 8553344 | 0
|
|
OUTPUTMC | 2 | 7 | 1 | 14 | 1
|
|
INPUTS | 12 | DQ_DATA<12> | $OpTx$FX_DC$30 | DQ_SWAP | A<12>.PIN | $OpTx$FX_SC$31 | A<20>.PIN | D<12>.PIN | LAN_SM_FSM_FFd3 | LAN_SM_FSM_FFd4 | $OpTx$FX_DC$10 | DQ_DATA<11>.EXP | LAN_SM_RST
|
|
INPUTMC | 9 | 14 | 1 | 14 | 9 | 0 | 15 | 14 | 12 | 15 | 16 | 10 | 6 | 5 | 10 | 14 | 0 | 11 | 0
|
|
INPUTP | 3 | 115 | 167 | 78
|
|
IMPORTS | 1 | 14 | 0
|
|
EQ | 10 |
|
|
DQ_DATA<12>.D = DQ_DATA<12> & !$OpTx$FX_DC$30
|
|
# A<20>.PIN & !DQ_SWAP & $OpTx$FX_SC$31
|
|
# DQ_SWAP & A<12>.PIN & $OpTx$FX_SC$31
|
|
# D<12>.PIN & !DQ_SWAP & !LAN_SM_FSM_FFd3 &
|
|
!LAN_SM_FSM_FFd4 & !$OpTx$FX_DC$10
|
|
;Imported pterms FB15_1
|
|
# D<4>.PIN & DQ_SWAP & !LAN_SM_FSM_FFd3 &
|
|
!LAN_SM_FSM_FFd4 & !$OpTx$FX_DC$10;
|
|
DQ_DATA<12>.CLK = CLK_EXT; // GCK
|
|
DQ_DATA<12>.AP = LAN_SM_RST;
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 8 | 0 | DQ_DATA<13>
|
|
ATTRIBUTES | 8553344 | 0
|
|
OUTPUTMC | 3 | 11 | 7 | 8 | 0 | 8 | 1
|
|
INPUTS | 12 | DQ_DATA<13> | $OpTx$FX_DC$30 | DQ_SWAP | A<13>.PIN | $OpTx$FX_SC$31 | D<14>.PIN | LAN_SM_FSM_FFd3 | LAN_SM_FSM_FFd4 | $OpTx$FX_DC$10 | D<6>.PIN | EXP27_.EXP | LAN_SM_RST
|
|
INPUTMC | 9 | 8 | 0 | 14 | 9 | 0 | 15 | 14 | 12 | 15 | 16 | 10 | 6 | 5 | 10 | 8 | 17 | 11 | 0
|
|
INPUTP | 3 | 123 | 81 | 26
|
|
EXPORTS | 1 | 8 | 1
|
|
IMPORTS | 1 | 8 | 17
|
|
EQ | 14 |
|
|
DQ_DATA<13>.D = DQ_DATA<13> & !$OpTx$FX_DC$30
|
|
# DQ_SWAP & A<13>.PIN & $OpTx$FX_SC$31
|
|
;Imported pterms FB9_18
|
|
# A<21>.PIN & !DQ_SWAP & $OpTx$FX_SC$31
|
|
# D<13>.PIN & !DQ_SWAP & !LAN_SM_FSM_FFd3 &
|
|
!LAN_SM_FSM_FFd4 & !$OpTx$FX_DC$10
|
|
# D<5>.PIN & DQ_SWAP & !LAN_SM_FSM_FFd3 &
|
|
!LAN_SM_FSM_FFd4 & !$OpTx$FX_DC$10;
|
|
DQ_DATA<13>.CLK = CLK_EXT; // GCK
|
|
DQ_DATA<13>.AP = LAN_SM_RST;
|
|
DQ_DATA<13>.EXP = D<14>.PIN & !DQ_SWAP & !LAN_SM_FSM_FFd3 &
|
|
!LAN_SM_FSM_FFd4 & !$OpTx$FX_DC$10
|
|
# D<6>.PIN & DQ_SWAP & !LAN_SM_FSM_FFd3 &
|
|
!LAN_SM_FSM_FFd4 & !$OpTx$FX_DC$10
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 8 | 1 | DQ_DATA<14>
|
|
ATTRIBUTES | 8553344 | 0
|
|
OUTPUTMC | 3 | 7 | 2 | 8 | 1 | 8 | 2
|
|
INPUTS | 12 | DQ_DATA<14> | $OpTx$FX_DC$30 | DQ_SWAP | A<14>.PIN | $OpTx$FX_SC$31 | A<22>.PIN | D<7>.PIN | LAN_SM_FSM_FFd3 | LAN_SM_FSM_FFd4 | $OpTx$FX_DC$10 | DQ_DATA<13>.EXP | LAN_SM_RST
|
|
INPUTMC | 9 | 8 | 1 | 14 | 9 | 0 | 15 | 14 | 12 | 15 | 16 | 10 | 6 | 5 | 10 | 8 | 0 | 11 | 0
|
|
INPUTP | 3 | 125 | 162 | 29
|
|
EXPORTS | 1 | 8 | 2
|
|
IMPORTS | 1 | 8 | 0
|
|
EQ | 12 |
|
|
DQ_DATA<14>.D = DQ_DATA<14> & !$OpTx$FX_DC$30
|
|
# A<22>.PIN & !DQ_SWAP & $OpTx$FX_SC$31
|
|
# DQ_SWAP & A<14>.PIN & $OpTx$FX_SC$31
|
|
;Imported pterms FB9_1
|
|
# D<14>.PIN & !DQ_SWAP & !LAN_SM_FSM_FFd3 &
|
|
!LAN_SM_FSM_FFd4 & !$OpTx$FX_DC$10
|
|
# D<6>.PIN & DQ_SWAP & !LAN_SM_FSM_FFd3 &
|
|
!LAN_SM_FSM_FFd4 & !$OpTx$FX_DC$10;
|
|
DQ_DATA<14>.CLK = CLK_EXT; // GCK
|
|
DQ_DATA<14>.AP = LAN_SM_RST;
|
|
DQ_DATA<14>.EXP = D<7>.PIN & DQ_SWAP & !LAN_SM_FSM_FFd3 &
|
|
!LAN_SM_FSM_FFd4 & !$OpTx$FX_DC$10
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 8 | 2 | DQ_DATA<15>
|
|
ATTRIBUTES | 8553344 | 0
|
|
OUTPUTMC | 2 | 11 | 4 | 8 | 2
|
|
INPUTS | 12 | DQ_DATA<15> | $OpTx$FX_DC$30 | DQ_SWAP | A<15>.PIN | $OpTx$FX_SC$31 | A<23>.PIN | D<15>.PIN | LAN_SM_FSM_FFd3 | LAN_SM_FSM_FFd4 | $OpTx$FX_DC$10 | DQ_DATA<14>.EXP | LAN_SM_RST
|
|
INPUTMC | 9 | 8 | 2 | 14 | 9 | 0 | 15 | 14 | 12 | 15 | 16 | 10 | 6 | 5 | 10 | 8 | 1 | 11 | 0
|
|
INPUTP | 3 | 139 | 161 | 89
|
|
IMPORTS | 1 | 8 | 1
|
|
EQ | 10 |
|
|
DQ_DATA<15>.D = DQ_DATA<15> & !$OpTx$FX_DC$30
|
|
# A<23>.PIN & !DQ_SWAP & $OpTx$FX_SC$31
|
|
# DQ_SWAP & A<15>.PIN & $OpTx$FX_SC$31
|
|
# D<15>.PIN & !DQ_SWAP & !LAN_SM_FSM_FFd3 &
|
|
!LAN_SM_FSM_FFd4 & !$OpTx$FX_DC$10
|
|
;Imported pterms FB9_2
|
|
# D<7>.PIN & DQ_SWAP & !LAN_SM_FSM_FFd3 &
|
|
!LAN_SM_FSM_FFd4 & !$OpTx$FX_DC$10;
|
|
DQ_DATA<15>.CLK = CLK_EXT; // GCK
|
|
DQ_DATA<15>.AP = LAN_SM_RST;
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 12 | 17 | DQ_DATA<1>
|
|
ATTRIBUTES | 8553344 | 0
|
|
OUTPUTMC | 3 | 9 | 1 | 12 | 17 | 12 | 16
|
|
INPUTS | 12 | DQ_DATA<1> | $OpTx$FX_DC$30 | A<17>.PIN | DQ_SWAP | $OpTx$FX_SC$31 | A<9>.PIN | D<10>.PIN | LAN_SM_FSM_FFd3 | LAN_SM_FSM_FFd4 | $OpTx$FX_DC$10 | EXP28_.EXP | LAN_SM_RST
|
|
INPUTMC | 9 | 12 | 17 | 14 | 9 | 0 | 15 | 14 | 12 | 15 | 16 | 10 | 6 | 5 | 10 | 12 | 0 | 11 | 0
|
|
INPUTP | 3 | 172 | 108 | 74
|
|
EXPORTS | 1 | 12 | 16
|
|
IMPORTS | 1 | 12 | 0
|
|
EQ | 12 |
|
|
DQ_DATA<1>.D = DQ_DATA<1> & !$OpTx$FX_DC$30
|
|
# A<17>.PIN & DQ_SWAP & $OpTx$FX_SC$31
|
|
# !DQ_SWAP & A<9>.PIN & $OpTx$FX_SC$31
|
|
;Imported pterms FB13_1
|
|
# D<9>.PIN & DQ_SWAP & !LAN_SM_FSM_FFd3 &
|
|
!LAN_SM_FSM_FFd4 & !$OpTx$FX_DC$10
|
|
# D<1>.PIN & !DQ_SWAP & !LAN_SM_FSM_FFd3 &
|
|
!LAN_SM_FSM_FFd4 & !$OpTx$FX_DC$10;
|
|
DQ_DATA<1>.CLK = CLK_EXT; // GCK
|
|
DQ_DATA<1>.AP = LAN_SM_RST;
|
|
DQ_DATA<1>.EXP = D<10>.PIN & DQ_SWAP & !LAN_SM_FSM_FFd3 &
|
|
!LAN_SM_FSM_FFd4 & !$OpTx$FX_DC$10
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 12 | 16 | DQ_DATA<2>
|
|
ATTRIBUTES | 8553344 | 0
|
|
OUTPUTMC | 2 | 9 | 5 | 12 | 16
|
|
INPUTS | 12 | DQ_DATA<2> | $OpTx$FX_DC$30 | A<18>.PIN | DQ_SWAP | $OpTx$FX_SC$31 | A<10>.PIN | D<2>.PIN | LAN_SM_FSM_FFd3 | LAN_SM_FSM_FFd4 | $OpTx$FX_DC$10 | DQ_DATA<1>.EXP | LAN_SM_RST
|
|
INPUTMC | 9 | 12 | 16 | 14 | 9 | 0 | 15 | 14 | 12 | 15 | 16 | 10 | 6 | 5 | 10 | 12 | 17 | 11 | 0
|
|
INPUTP | 3 | 171 | 112 | 71
|
|
IMPORTS | 1 | 12 | 17
|
|
EQ | 10 |
|
|
DQ_DATA<2>.D = DQ_DATA<2> & !$OpTx$FX_DC$30
|
|
# A<18>.PIN & DQ_SWAP & $OpTx$FX_SC$31
|
|
# !DQ_SWAP & A<10>.PIN & $OpTx$FX_SC$31
|
|
# D<2>.PIN & !DQ_SWAP & !LAN_SM_FSM_FFd3 &
|
|
!LAN_SM_FSM_FFd4 & !$OpTx$FX_DC$10
|
|
;Imported pterms FB13_18
|
|
# D<10>.PIN & DQ_SWAP & !LAN_SM_FSM_FFd3 &
|
|
!LAN_SM_FSM_FFd4 & !$OpTx$FX_DC$10;
|
|
DQ_DATA<2>.CLK = CLK_EXT; // GCK
|
|
DQ_DATA<2>.AP = LAN_SM_RST;
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 14 | 2 | DQ_DATA<3>
|
|
ATTRIBUTES | 8553344 | 0
|
|
OUTPUTMC | 2 | 9 | 4 | 14 | 2
|
|
INPUTS | 12 | DQ_DATA<3> | $OpTx$FX_DC$30 | A<19>.PIN | DQ_SWAP | $OpTx$FX_SC$31 | A<11>.PIN | D<3>.PIN | LAN_SM_FSM_FFd3 | LAN_SM_FSM_FFd4 | $OpTx$FX_DC$10 | DQ_DATA<4>.EXP | LAN_SM_RST
|
|
INPUTMC | 9 | 14 | 2 | 14 | 9 | 0 | 15 | 14 | 12 | 15 | 16 | 10 | 6 | 5 | 10 | 14 | 3 | 11 | 0
|
|
INPUTP | 3 | 169 | 114 | 28
|
|
IMPORTS | 1 | 14 | 3
|
|
EQ | 10 |
|
|
DQ_DATA<3>.D = DQ_DATA<3> & !$OpTx$FX_DC$30
|
|
# A<19>.PIN & DQ_SWAP & $OpTx$FX_SC$31
|
|
# !DQ_SWAP & A<11>.PIN & $OpTx$FX_SC$31
|
|
# D<3>.PIN & !DQ_SWAP & !LAN_SM_FSM_FFd3 &
|
|
!LAN_SM_FSM_FFd4 & !$OpTx$FX_DC$10
|
|
;Imported pterms FB15_4
|
|
# D<11>.PIN & DQ_SWAP & !LAN_SM_FSM_FFd3 &
|
|
!LAN_SM_FSM_FFd4 & !$OpTx$FX_DC$10;
|
|
DQ_DATA<3>.CLK = CLK_EXT; // GCK
|
|
DQ_DATA<3>.AP = LAN_SM_RST;
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 14 | 3 | DQ_DATA<4>
|
|
ATTRIBUTES | 8553344 | 0
|
|
OUTPUTMC | 3 | 9 | 9 | 14 | 3 | 14 | 2
|
|
INPUTS | 12 | DQ_DATA<4> | $OpTx$FX_DC$30 | A<20>.PIN | DQ_SWAP | $OpTx$FX_SC$31 | A<12>.PIN | D<11>.PIN | LAN_SM_FSM_FFd3 | LAN_SM_FSM_FFd4 | $OpTx$FX_DC$10 | BUF_LAN_READY.EXP | LAN_SM_RST
|
|
INPUTMC | 9 | 14 | 3 | 14 | 9 | 0 | 15 | 14 | 12 | 15 | 16 | 10 | 6 | 5 | 10 | 14 | 4 | 11 | 0
|
|
INPUTP | 3 | 167 | 115 | 77
|
|
EXPORTS | 1 | 14 | 2
|
|
IMPORTS | 1 | 14 | 4
|
|
EQ | 12 |
|
|
DQ_DATA<4>.D = DQ_DATA<4> & !$OpTx$FX_DC$30
|
|
# A<20>.PIN & DQ_SWAP & $OpTx$FX_SC$31
|
|
# !DQ_SWAP & A<12>.PIN & $OpTx$FX_SC$31
|
|
;Imported pterms FB15_5
|
|
# D<12>.PIN & DQ_SWAP & !LAN_SM_FSM_FFd3 &
|
|
!LAN_SM_FSM_FFd4 & !$OpTx$FX_DC$10
|
|
# D<4>.PIN & !DQ_SWAP & !LAN_SM_FSM_FFd3 &
|
|
!LAN_SM_FSM_FFd4 & !$OpTx$FX_DC$10;
|
|
DQ_DATA<4>.CLK = CLK_EXT; // GCK
|
|
DQ_DATA<4>.AP = LAN_SM_RST;
|
|
DQ_DATA<4>.EXP = D<11>.PIN & DQ_SWAP & !LAN_SM_FSM_FFd3 &
|
|
!LAN_SM_FSM_FFd4 & !$OpTx$FX_DC$10
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 8 | 3 | DQ_DATA<5>
|
|
ATTRIBUTES | 8553344 | 0
|
|
OUTPUTMC | 2 | 9 | 7 | 8 | 3
|
|
INPUTS | 12 | DQ_DATA<5> | $OpTx$FX_DC$30 | A<21>.PIN | DQ_SWAP | $OpTx$FX_SC$31 | A<13>.PIN | D<5>.PIN | LAN_SM_FSM_FFd3 | LAN_SM_FSM_FFd4 | $OpTx$FX_DC$10 | DQ_DATA<6>.EXP | LAN_SM_RST
|
|
INPUTMC | 9 | 8 | 3 | 14 | 9 | 0 | 15 | 14 | 12 | 15 | 16 | 10 | 6 | 5 | 10 | 8 | 4 | 11 | 0
|
|
INPUTP | 3 | 163 | 123 | 37
|
|
IMPORTS | 1 | 8 | 4
|
|
EQ | 10 |
|
|
DQ_DATA<5>.D = DQ_DATA<5> & !$OpTx$FX_DC$30
|
|
# A<21>.PIN & DQ_SWAP & $OpTx$FX_SC$31
|
|
# !DQ_SWAP & A<13>.PIN & $OpTx$FX_SC$31
|
|
# D<5>.PIN & !DQ_SWAP & !LAN_SM_FSM_FFd3 &
|
|
!LAN_SM_FSM_FFd4 & !$OpTx$FX_DC$10
|
|
;Imported pterms FB9_5
|
|
# D<13>.PIN & DQ_SWAP & !LAN_SM_FSM_FFd3 &
|
|
!LAN_SM_FSM_FFd4 & !$OpTx$FX_DC$10;
|
|
DQ_DATA<5>.CLK = CLK_EXT; // GCK
|
|
DQ_DATA<5>.AP = LAN_SM_RST;
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 8 | 4 | DQ_DATA<6>
|
|
ATTRIBUTES | 8553344 | 0
|
|
OUTPUTMC | 3 | 9 | 11 | 8 | 4 | 8 | 3
|
|
INPUTS | 12 | DQ_DATA<6> | $OpTx$FX_DC$30 | A<22>.PIN | DQ_SWAP | $OpTx$FX_SC$31 | A<14>.PIN | D<13>.PIN | LAN_SM_FSM_FFd3 | LAN_SM_FSM_FFd4 | $OpTx$FX_DC$10 | DQ_DATA<7>.EXP | LAN_SM_RST
|
|
INPUTMC | 9 | 8 | 4 | 14 | 9 | 0 | 15 | 14 | 12 | 15 | 16 | 10 | 6 | 5 | 10 | 8 | 5 | 11 | 0
|
|
INPUTP | 3 | 162 | 125 | 80
|
|
EXPORTS | 1 | 8 | 3
|
|
IMPORTS | 1 | 8 | 5
|
|
EQ | 12 |
|
|
DQ_DATA<6>.D = DQ_DATA<6> & !$OpTx$FX_DC$30
|
|
# A<22>.PIN & DQ_SWAP & $OpTx$FX_SC$31
|
|
# !DQ_SWAP & A<14>.PIN & $OpTx$FX_SC$31
|
|
;Imported pterms FB9_6
|
|
# D<14>.PIN & DQ_SWAP & !LAN_SM_FSM_FFd3 &
|
|
!LAN_SM_FSM_FFd4 & !$OpTx$FX_DC$10
|
|
# D<6>.PIN & !DQ_SWAP & !LAN_SM_FSM_FFd3 &
|
|
!LAN_SM_FSM_FFd4 & !$OpTx$FX_DC$10;
|
|
DQ_DATA<6>.CLK = CLK_EXT; // GCK
|
|
DQ_DATA<6>.AP = LAN_SM_RST;
|
|
DQ_DATA<6>.EXP = D<13>.PIN & DQ_SWAP & !LAN_SM_FSM_FFd3 &
|
|
!LAN_SM_FSM_FFd4 & !$OpTx$FX_DC$10
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 8 | 5 | DQ_DATA<7>
|
|
ATTRIBUTES | 8553344 | 0
|
|
OUTPUTMC | 3 | 9 | 10 | 8 | 5 | 8 | 4
|
|
INPUTS | 12 | DQ_DATA<7> | $OpTx$FX_DC$30 | A<23>.PIN | DQ_SWAP | $OpTx$FX_SC$31 | D<14>.PIN | LAN_SM_FSM_FFd3 | LAN_SM_FSM_FFd4 | $OpTx$FX_DC$10 | D<6>.PIN | $OpTx$INV$5.EXP | LAN_SM_RST
|
|
INPUTMC | 9 | 8 | 5 | 14 | 9 | 0 | 15 | 14 | 12 | 15 | 16 | 10 | 6 | 5 | 10 | 8 | 6 | 11 | 0
|
|
INPUTP | 3 | 161 | 81 | 26
|
|
EXPORTS | 1 | 8 | 4
|
|
IMPORTS | 1 | 8 | 6
|
|
EQ | 14 |
|
|
DQ_DATA<7>.D = DQ_DATA<7> & !$OpTx$FX_DC$30
|
|
# A<23>.PIN & DQ_SWAP & $OpTx$FX_SC$31
|
|
;Imported pterms FB9_7
|
|
# !DQ_SWAP & A<15>.PIN & $OpTx$FX_SC$31
|
|
# D<15>.PIN & DQ_SWAP & !LAN_SM_FSM_FFd3 &
|
|
!LAN_SM_FSM_FFd4 & !$OpTx$FX_DC$10
|
|
# D<7>.PIN & !DQ_SWAP & !LAN_SM_FSM_FFd3 &
|
|
!LAN_SM_FSM_FFd4 & !$OpTx$FX_DC$10;
|
|
DQ_DATA<7>.CLK = CLK_EXT; // GCK
|
|
DQ_DATA<7>.AP = LAN_SM_RST;
|
|
DQ_DATA<7>.EXP = D<14>.PIN & DQ_SWAP & !LAN_SM_FSM_FFd3 &
|
|
!LAN_SM_FSM_FFd4 & !$OpTx$FX_DC$10
|
|
# D<6>.PIN & !DQ_SWAP & !LAN_SM_FSM_FFd3 &
|
|
!LAN_SM_FSM_FFd4 & !$OpTx$FX_DC$10
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 10 | 14 | DQ_DATA<8>
|
|
ATTRIBUTES | 8553344 | 0
|
|
OUTPUTMC | 2 | 9 | 13 | 10 | 14
|
|
INPUTS | 12 | DQ_DATA<8> | $OpTx$FX_DC$30 | DQ_SWAP | A<8>.PIN | $OpTx$FX_SC$31 | A<16>.PIN | D<8>.PIN | LAN_SM_FSM_FFd3 | LAN_SM_FSM_FFd4 | $OpTx$FX_DC$10 | ROM_B_0_OBUF.EXP | LAN_SM_RST
|
|
INPUTMC | 9 | 10 | 14 | 14 | 9 | 0 | 15 | 14 | 12 | 15 | 16 | 10 | 6 | 5 | 10 | 10 | 13 | 11 | 0
|
|
INPUTP | 3 | 106 | 175 | 32
|
|
IMPORTS | 1 | 10 | 13
|
|
EQ | 10 |
|
|
DQ_DATA<8>.D = DQ_DATA<8> & !$OpTx$FX_DC$30
|
|
# A<16>.PIN & !DQ_SWAP & $OpTx$FX_SC$31
|
|
# DQ_SWAP & A<8>.PIN & $OpTx$FX_SC$31
|
|
# D<8>.PIN & !DQ_SWAP & !LAN_SM_FSM_FFd3 &
|
|
!LAN_SM_FSM_FFd4 & !$OpTx$FX_DC$10
|
|
;Imported pterms FB11_14
|
|
# D<0>.PIN & DQ_SWAP & !LAN_SM_FSM_FFd3 &
|
|
!LAN_SM_FSM_FFd4 & !$OpTx$FX_DC$10;
|
|
DQ_DATA<8>.CLK = CLK_EXT; // GCK
|
|
DQ_DATA<8>.AP = LAN_SM_RST;
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 12 | 15 | DQ_DATA<9>
|
|
ATTRIBUTES | 8553344 | 0
|
|
OUTPUTMC | 2 | 11 | 11 | 12 | 15
|
|
INPUTS | 12 | DQ_DATA<9> | $OpTx$FX_DC$30 | DQ_SWAP | A<9>.PIN | $OpTx$FX_SC$31 | A<17>.PIN | D<9>.PIN | LAN_SM_FSM_FFd3 | LAN_SM_FSM_FFd4 | $OpTx$FX_DC$10 | D_OUT<1>.EXP | LAN_SM_RST
|
|
INPUTMC | 9 | 12 | 15 | 14 | 9 | 0 | 15 | 14 | 12 | 15 | 16 | 10 | 6 | 5 | 10 | 12 | 14 | 11 | 0
|
|
INPUTP | 3 | 108 | 172 | 73
|
|
IMPORTS | 1 | 12 | 14
|
|
EQ | 10 |
|
|
DQ_DATA<9>.D = DQ_DATA<9> & !$OpTx$FX_DC$30
|
|
# A<17>.PIN & !DQ_SWAP & $OpTx$FX_SC$31
|
|
# DQ_SWAP & A<9>.PIN & $OpTx$FX_SC$31
|
|
# D<9>.PIN & !DQ_SWAP & !LAN_SM_FSM_FFd3 &
|
|
!LAN_SM_FSM_FFd4 & !$OpTx$FX_DC$10
|
|
;Imported pterms FB13_15
|
|
# D<1>.PIN & DQ_SWAP & !LAN_SM_FSM_FFd3 &
|
|
!LAN_SM_FSM_FFd4 & !$OpTx$FX_DC$10;
|
|
DQ_DATA<9>.CLK = CLK_EXT; // GCK
|
|
DQ_DATA<9>.AP = LAN_SM_RST;
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 11 | 12 | LAN_WR_RST
|
|
ATTRIBUTES | 8553232 | 0
|
|
OUTPUTMC | 2 | 7 | 4 | 12 | 13
|
|
INPUTS | 4 | LAN_RST_SM_FSM_FFd3 | LAN_RST_SM_FSM_FFd2 | LAN_RST_SM_FSM_FFd1 | RESET
|
|
INPUTMC | 3 | 11 | 13 | 11 | 14 | 11 | 15
|
|
INPUTP | 1 | 263
|
|
EQ | 6 |
|
|
LAN_WR_RST.D = LAN_RST_SM_FSM_FFd3 & LAN_RST_SM_FSM_FFd2 &
|
|
!LAN_RST_SM_FSM_FFd1
|
|
# LAN_RST_SM_FSM_FFd3 & !LAN_RST_SM_FSM_FFd2 &
|
|
LAN_RST_SM_FSM_FFd1;
|
|
LAN_WR_RST.CLK = CLK_EXT; // GCK
|
|
LAN_WR_RST.AR = RESET;
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 6 | 9 | SHUT_UP_Z2<0>
|
|
ATTRIBUTES | 8520612 | 0
|
|
OUTPUTMC | 2 | 6 | 9 | 6 | 0
|
|
INPUTS | 4 | SHUT_UP_Z2<0> | $OpTx$FX_DC$34 | SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF | RESET
|
|
INPUTMC | 3 | 6 | 9 | 3 | 2 | 5 | 11
|
|
INPUTP | 1 | 263
|
|
EQ | 3 |
|
|
SHUT_UP_Z2<0>.D = SHUT_UP_Z2<0> & !$OpTx$FX_DC$34;
|
|
SHUT_UP_Z2<0>.CLK = SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF;
|
|
SHUT_UP_Z2<0>.AP = !RESET;
|
|
|
|
MACROCELL | 7 | 3 | SHUT_UP_Z2<1>
|
|
ATTRIBUTES | 8520612 | 0
|
|
OUTPUTMC | 2 | 7 | 3 | 7 | 17
|
|
INPUTS | 4 | SHUT_UP_Z2<1> | $OpTx$FX_DC$35 | SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF | RESET
|
|
INPUTMC | 3 | 7 | 3 | 3 | 17 | 5 | 11
|
|
INPUTP | 1 | 263
|
|
EQ | 3 |
|
|
SHUT_UP_Z2<1>.D = SHUT_UP_Z2<1> & !$OpTx$FX_DC$35;
|
|
SHUT_UP_Z2<1>.CLK = SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF;
|
|
SHUT_UP_Z2<1>.AP = !RESET;
|
|
|
|
MACROCELL | 6 | 0 | CP_ACCESS
|
|
ATTRIBUTES | 8520496 | 0
|
|
OUTPUTMC | 1 | 13 | 13
|
|
INPUTS | 7 | SHUT_UP_Z2<0> | A<16>.PIN | CP_BASEADR<0> | EXP23_.EXP | EXP25_.EXP | AS | RESET
|
|
INPUTMC | 4 | 6 | 9 | 6 | 16 | 6 | 1 | 6 | 17
|
|
INPUTP | 3 | 175 | 152 | 263
|
|
IMPORTS | 2 | 6 | 1 | 6 | 17
|
|
EQ | 23 |
|
|
!CP_ACCESS.D = SHUT_UP_Z2<0>
|
|
# A<16>.PIN & !CP_BASEADR<0>
|
|
# !A<16>.PIN & CP_BASEADR<0>
|
|
;Imported pterms FB7_2
|
|
# A<20>.PIN & !CP_BASEADR<4>
|
|
# !A<20>.PIN & CP_BASEADR<4>
|
|
# !A<19>.PIN & CP_BASEADR<3>
|
|
# CP_BASEADR<5> & !A<21>.PIN
|
|
# !CP_BASEADR<5> & A<21>.PIN
|
|
;Imported pterms FB7_3
|
|
# CP_BASEADR<6> & !A<22>.PIN
|
|
# !CP_BASEADR<6> & A<22>.PIN
|
|
# CP_BASEADR<7> & !A<23>.PIN
|
|
;Imported pterms FB7_18
|
|
# A<19>.PIN & !CP_BASEADR<3>
|
|
# A<18>.PIN & !CP_BASEADR<2>
|
|
# !A<18>.PIN & CP_BASEADR<2>
|
|
# A<17>.PIN & !CP_BASEADR<1>
|
|
# !A<17>.PIN & CP_BASEADR<1>
|
|
;Imported pterms FB7_17
|
|
# !CP_BASEADR<7> & A<23>.PIN;
|
|
CP_ACCESS.CLK = !AS;
|
|
CP_ACCESS.AR = !RESET;
|
|
|
|
MACROCELL | 3 | 0 | D_Z2_OUT<0>
|
|
ATTRIBUTES | 8520612 | 0
|
|
OUTPUTMC | 1 | 4 | 16
|
|
INPUTS | 9 | $OpTx$FX_DC$16 | A<6> | BUF_D_Z2_OUT<3> | A<5> | $OpTx$FX_DC$49 | D_0_IOBUFE.EXP | $OpTx$FX_DC$35.EXP | SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF | RESET
|
|
INPUTMC | 6 | 0 | 0 | 3 | 14 | 13 | 3 | 3 | 1 | 3 | 17 | 5 | 11
|
|
INPUTP | 3 | 98 | 91 | 263
|
|
IMPORTS | 2 | 3 | 1 | 3 | 17
|
|
EQ | 15 |
|
|
D_Z2_OUT<0>.D = !$OpTx$FX_DC$16
|
|
# A<5> & !$OpTx$FX_DC$49
|
|
# A<6> & BUF_D_Z2_OUT<3>
|
|
;Imported pterms FB4_2
|
|
# AUTO_CONFIG_Z2_DONE<1> & A<5> & A<3>
|
|
# AUTO_CONFIG_Z2_DONE<0> & !A<5> & !A<3> &
|
|
BUF_D_Z2_OUT<3>
|
|
# A<1> & !A<6> & BUF_D_Z2_OUT<2> & !BUF_D_Z2_OUT<3>
|
|
;Imported pterms FB4_18
|
|
# !AUTO_CONFIG_Z2_DONE<0> & A<5> & A<3>
|
|
# !A<5> & !A<4> & A<3>
|
|
# A<4> & !A<2> & !A<3>
|
|
# !A<1> & A<3> & BUF_D_Z2_OUT<3>;
|
|
D_Z2_OUT<0>.CLK = SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF;
|
|
D_Z2_OUT<0>.AP = !RESET;
|
|
|
|
MACROCELL | 3 | 15 | D_Z2_OUT<1>
|
|
ATTRIBUTES | 8520612 | 0
|
|
OUTPUTMC | 1 | 6 | 3
|
|
INPUTS | 8 | $OpTx$FX_DC$16 | A<5> | BUF_D_Z2_OUT<3> | A<6> | BUF_D_Z2_OUT<3>.EXP | EXP22_.EXP | SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF | RESET
|
|
INPUTMC | 5 | 0 | 0 | 3 | 14 | 3 | 14 | 3 | 16 | 5 | 11
|
|
INPUTP | 3 | 91 | 98 | 263
|
|
IMPORTS | 2 | 3 | 14 | 3 | 16
|
|
EQ | 14 |
|
|
D_Z2_OUT<1>.D = !$OpTx$FX_DC$16
|
|
# A<5> & BUF_D_Z2_OUT<3>
|
|
# A<6> & BUF_D_Z2_OUT<3>
|
|
;Imported pterms FB4_15
|
|
# !A<4> & A<3>
|
|
;Imported pterms FB4_17
|
|
# A<4> & !A<2> & BUF_D_Z2_OUT<3>
|
|
# A<2> & BUF_D_Z2_OUT<2> & !BUF_D_Z2_OUT<3>
|
|
# AUTO_CONFIG_Z2_DONE<0> & A<4> & !A<3> &
|
|
!BUF_D_Z2_OUT<3>
|
|
# !AUTO_CONFIG_Z2_DONE<0> & A<4> & A<2> & !A<3>
|
|
# !A<4> & A<2> & !BUF_D_Z2_OUT<2> & BUF_D_Z2_OUT<3>;
|
|
D_Z2_OUT<1>.CLK = SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF;
|
|
D_Z2_OUT<1>.AP = !RESET;
|
|
|
|
MACROCELL | 3 | 6 | D_Z2_OUT<2>
|
|
ATTRIBUTES | 8520612 | 0
|
|
OUTPUTMC | 1 | 6 | 4
|
|
INPUTS | 3 | BUF_D_Z2_OUT<2> | SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF | RESET
|
|
INPUTMC | 2 | 3 | 12 | 5 | 11
|
|
INPUTP | 1 | 263
|
|
EQ | 3 |
|
|
!D_Z2_OUT<2>.D = BUF_D_Z2_OUT<2>;
|
|
D_Z2_OUT<2>.CLK = SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF;
|
|
D_Z2_OUT<2>.AP = !RESET;
|
|
|
|
MACROCELL | 3 | 3 | D_Z2_OUT<3>
|
|
ATTRIBUTES | 8520612 | 0
|
|
OUTPUTMC | 1 | 6 | 11
|
|
INPUTS | 3 | BUF_D_Z2_OUT<3> | SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF | RESET
|
|
INPUTMC | 2 | 3 | 14 | 5 | 11
|
|
INPUTP | 1 | 263
|
|
EQ | 3 |
|
|
D_Z2_OUT<3>.D = BUF_D_Z2_OUT<3>;
|
|
D_Z2_OUT<3>.CLK = SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF;
|
|
D_Z2_OUT<3>.AP = !RESET;
|
|
|
|
MACROCELL | 1 | 0 | SHUT_UP
|
|
ATTRIBUTES | 8553408 | 0
|
|
OUTPUTMC | 2 | 0 | 15 | 0 | 8
|
|
INPUTS | 12 | RESET | UDS | RW | FCS | Z3_ADR<2> | Z3_ADR_1 | Z3_ADR_0 | Z3_ADR<6> | AUTOCONFIG_Z3_ACCESS | Z3_ADR<3> | Z3_ADR<4> | Z3_ADR<5>
|
|
INPUTMC | 8 | 13 | 16 | 13 | 7 | 13 | 8 | 13 | 9 | 9 | 12 | 13 | 15 | 13 | 12 | 13 | 11
|
|
INPUTP | 4 | 263 | 155 | 158 | 147
|
|
EQ | 6 |
|
|
SHUT_UP.D = Gnd;
|
|
SHUT_UP.CLK = CLK_EXT; // GCK
|
|
SHUT_UP.AP = !RESET;
|
|
SHUT_UP.CE = !UDS & !RW & !FCS & !Z3_ADR<2> & !Z3_ADR_1 &
|
|
Z3_ADR_0 & !Z3_ADR<6> & AUTOCONFIG_Z3_ACCESS & !Z3_ADR<3> &
|
|
Z3_ADR<4> & !Z3_ADR<5>;
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 0 | 3 | Z3_ADR<10>
|
|
ATTRIBUTES | 8520608 | 0
|
|
OUTPUTMC | 1 | 5 | 7
|
|
INPUTS | 3 | A<12>.PIN | FCS | RESET
|
|
INPUTP | 3 | 115 | 147 | 263
|
|
EQ | 3 |
|
|
Z3_ADR<10>.D = A<12>.PIN;
|
|
Z3_ADR<10>.CLK = !FCS;
|
|
Z3_ADR<10>.AP = !RESET;
|
|
|
|
MACROCELL | 8 | 7 | Z3_ADR<11>
|
|
ATTRIBUTES | 8520608 | 0
|
|
OUTPUTMC | 2 | 5 | 2 | 8 | 6
|
|
INPUTS | 5 | A<13>.PIN | FCS | RESET | D<13>.PIN | LAN_BASEADR<13>
|
|
INPUTMC | 1 | 1 | 8
|
|
INPUTP | 4 | 123 | 147 | 263 | 80
|
|
EXPORTS | 1 | 8 | 6
|
|
EQ | 5 |
|
|
Z3_ADR<11>.D = A<13>.PIN;
|
|
Z3_ADR<11>.CLK = !FCS;
|
|
Z3_ADR<11>.AP = !RESET;
|
|
Z3_ADR<11>.EXP = D<13>.PIN & !LAN_BASEADR<13>
|
|
# !D<13>.PIN & LAN_BASEADR<13>
|
|
|
|
MACROCELL | 8 | 8 | Z3_ADR<12>
|
|
ATTRIBUTES | 8520608 | 0
|
|
OUTPUTMC | 1 | 5 | 4
|
|
INPUTS | 3 | A<14>.PIN | FCS | RESET
|
|
INPUTP | 3 | 125 | 147 | 263
|
|
EQ | 3 |
|
|
Z3_ADR<12>.D = A<14>.PIN;
|
|
Z3_ADR<12>.CLK = !FCS;
|
|
Z3_ADR<12>.AP = !RESET;
|
|
|
|
MACROCELL | 12 | 8 | Z3_ADR<7>
|
|
ATTRIBUTES | 8520608 | 0
|
|
OUTPUTMC | 1 | 5 | 9
|
|
INPUTS | 3 | A<9>.PIN | FCS | RESET
|
|
INPUTP | 3 | 108 | 147 | 263
|
|
EQ | 3 |
|
|
Z3_ADR<7>.D = A<9>.PIN;
|
|
Z3_ADR<7>.CLK = !FCS;
|
|
Z3_ADR<7>.AP = !RESET;
|
|
|
|
MACROCELL | 12 | 6 | Z3_ADR<8>
|
|
ATTRIBUTES | 8520608 | 0
|
|
OUTPUTMC | 1 | 5 | 13
|
|
INPUTS | 3 | A<10>.PIN | FCS | RESET
|
|
INPUTP | 3 | 112 | 147 | 263
|
|
EQ | 3 |
|
|
Z3_ADR<8>.D = A<10>.PIN;
|
|
Z3_ADR<8>.CLK = !FCS;
|
|
Z3_ADR<8>.AP = !RESET;
|
|
|
|
MACROCELL | 0 | 2 | Z3_ADR<9>
|
|
ATTRIBUTES | 8520608 | 0
|
|
OUTPUTMC | 1 | 5 | 5
|
|
INPUTS | 3 | A<11>.PIN | FCS | RESET
|
|
INPUTP | 3 | 114 | 147 | 263
|
|
EQ | 3 |
|
|
Z3_ADR<9>.D = A<11>.PIN;
|
|
Z3_ADR<9>.CLK = !FCS;
|
|
Z3_ADR<9>.AP = !RESET;
|
|
|
|
MACROCELL | 11 | 8 | CONFIG_READY
|
|
ATTRIBUTES | 8553232 | 0
|
|
OUTPUTMC | 1 | 13 | 4
|
|
INPUTS | 2 | BUF_CONFIG_READY | RESET
|
|
INPUTMC | 1 | 13 | 1
|
|
INPUTP | 1 | 263
|
|
EQ | 3 |
|
|
CONFIG_READY.D = BUF_CONFIG_READY;
|
|
CONFIG_READY.CLK = CLK_EXT; // GCK
|
|
CONFIG_READY.AR = !RESET;
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 12 | 5 | D_OUT<0>
|
|
ATTRIBUTES | 8553348 | 0
|
|
OUTPUTMC | 1 | 1 | 16
|
|
INPUTS | 10 | UDS | FCS | Z3_ADR<2> | Z3_ADR_1 | Z3_ADR_0 | AUTOCONFIG_Z3_ACCESS | Z3_ADR<3> | Z3_ADR<4> | Z3_ADR<5> | RESET
|
|
INPUTMC | 7 | 13 | 16 | 13 | 7 | 13 | 8 | 9 | 12 | 13 | 15 | 13 | 12 | 13 | 11
|
|
INPUTP | 3 | 155 | 147 | 263
|
|
EQ | 4 |
|
|
!D_OUT<0>.D = !UDS & !FCS & !Z3_ADR<2> & !Z3_ADR_1 & Z3_ADR_0 &
|
|
AUTOCONFIG_Z3_ACCESS & !Z3_ADR<3> & !Z3_ADR<4> & !Z3_ADR<5>;
|
|
D_OUT<0>.CLK = CLK_EXT; // GCK
|
|
D_OUT<0>.AP = !RESET;
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 12 | 14 | D_OUT<1>
|
|
ATTRIBUTES | 8553348 | 0
|
|
OUTPUTMC | 2 | 4 | 11 | 12 | 15
|
|
INPUTS | 15 | UDS | FCS | Z3_ADR<2> | Z3_ADR_0 | AUTOCONFIG_Z3_ACCESS | Z3_ADR<3> | Z3_ADR<4> | Z3_ADR<5> | Z3_ADR_1 | RESET | D<1>.PIN | DQ_SWAP | LAN_SM_FSM_FFd3 | LAN_SM_FSM_FFd4 | $OpTx$FX_DC$10
|
|
INPUTMC | 11 | 13 | 16 | 13 | 8 | 9 | 12 | 13 | 15 | 13 | 12 | 13 | 11 | 13 | 7 | 0 | 15 | 15 | 16 | 10 | 6 | 5 | 10
|
|
INPUTP | 4 | 155 | 147 | 263 | 30
|
|
EXPORTS | 1 | 12 | 15
|
|
EQ | 10 |
|
|
!D_OUT<1>.D = !UDS & !FCS & !Z3_ADR<2> & !Z3_ADR_1 &
|
|
AUTOCONFIG_Z3_ACCESS & !Z3_ADR<3> & !Z3_ADR<4> & !Z3_ADR<5>
|
|
# !UDS & !FCS & !Z3_ADR<2> & !Z3_ADR_0 &
|
|
AUTOCONFIG_Z3_ACCESS & !Z3_ADR<3> & !Z3_ADR<4> & !Z3_ADR<5>
|
|
# !UDS & !FCS & !Z3_ADR_1 & !Z3_ADR_0 &
|
|
AUTOCONFIG_Z3_ACCESS & !Z3_ADR<3> & !Z3_ADR<4> & !Z3_ADR<5>;
|
|
D_OUT<1>.CLK = CLK_EXT; // GCK
|
|
D_OUT<1>.AP = !RESET;
|
|
D_OUT<1>.EXP = D<1>.PIN & DQ_SWAP & !LAN_SM_FSM_FFd3 &
|
|
!LAN_SM_FSM_FFd4 & !$OpTx$FX_DC$10
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 12 | 9 | D_OUT<2>
|
|
ATTRIBUTES | 8553348 | 0
|
|
OUTPUTMC | 1 | 4 | 13
|
|
INPUTS | 10 | UDS | FCS | Z3_ADR<2> | Z3_ADR_1 | Z3_ADR_0 | AUTOCONFIG_Z3_ACCESS | Z3_ADR<3> | Z3_ADR<4> | Z3_ADR<5> | RESET
|
|
INPUTMC | 7 | 13 | 16 | 13 | 7 | 13 | 8 | 9 | 12 | 13 | 15 | 13 | 12 | 13 | 11
|
|
INPUTP | 3 | 155 | 147 | 263
|
|
EQ | 6 |
|
|
!D_OUT<2>.D = !UDS & !FCS & Z3_ADR<2> & !Z3_ADR_1 & Z3_ADR_0 &
|
|
AUTOCONFIG_Z3_ACCESS & !Z3_ADR<3> & !Z3_ADR<4> & !Z3_ADR<5>
|
|
# !UDS & !FCS & !Z3_ADR<2> & !Z3_ADR_1 & !Z3_ADR_0 &
|
|
AUTOCONFIG_Z3_ACCESS & !Z3_ADR<3> & !Z3_ADR<4> & !Z3_ADR<5>;
|
|
D_OUT<2>.CLK = CLK_EXT; // GCK
|
|
D_OUT<2>.AP = !RESET;
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 12 | 4 | D_OUT<3>
|
|
ATTRIBUTES | 8553348 | 0
|
|
OUTPUTMC | 1 | 4 | 14
|
|
INPUTS | 8 | UDS | FCS | Z3_ADR_1 | AUTOCONFIG_Z3_ACCESS | Z3_ADR<3> | Z3_ADR<4> | Z3_ADR<5> | RESET
|
|
INPUTMC | 5 | 13 | 7 | 9 | 12 | 13 | 15 | 13 | 12 | 13 | 11
|
|
INPUTP | 3 | 155 | 147 | 263
|
|
EQ | 4 |
|
|
!D_OUT<3>.D = !UDS & !FCS & !Z3_ADR_1 & AUTOCONFIG_Z3_ACCESS &
|
|
!Z3_ADR<3> & !Z3_ADR<4> & !Z3_ADR<5>;
|
|
D_OUT<3>.CLK = CLK_EXT; // GCK
|
|
D_OUT<3>.AP = !RESET;
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 12 | 12 | D_OUT<4>
|
|
ATTRIBUTES | 8553348 | 0
|
|
OUTPUTMC | 1 | 4 | 16
|
|
INPUTS | 11 | UDS | FCS | Z3_ADR<2> | Z3_ADR_1 | Z3_ADR_0 | AUTOCONFIG_Z3_ACCESS | Z3_ADR<3> | Z3_ADR<4> | Z3_ADR<5> | Z3_ADR<6> | RESET
|
|
INPUTMC | 8 | 13 | 16 | 13 | 7 | 13 | 8 | 9 | 12 | 13 | 15 | 13 | 12 | 13 | 11 | 13 | 9
|
|
INPUTP | 3 | 155 | 147 | 263
|
|
EQ | 8 |
|
|
!D_OUT<4>.D = !UDS & !FCS & !Z3_ADR<2> & !Z3_ADR_1 & Z3_ADR_0 &
|
|
AUTOCONFIG_Z3_ACCESS & !Z3_ADR<3> & !Z3_ADR<4> & !Z3_ADR<5>
|
|
# !UDS & !FCS & !Z3_ADR<2> & !Z3_ADR_0 & !Z3_ADR<6> &
|
|
AUTOCONFIG_Z3_ACCESS & !Z3_ADR<3> & !Z3_ADR<4> & !Z3_ADR<5>
|
|
# !UDS & !FCS & !Z3_ADR_1 & Z3_ADR_0 & !Z3_ADR<6> &
|
|
AUTOCONFIG_Z3_ACCESS & !Z3_ADR<3> & !Z3_ADR<4> & !Z3_ADR<5>;
|
|
D_OUT<4>.CLK = CLK_EXT; // GCK
|
|
D_OUT<4>.AP = !RESET;
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 4 | 17 | D_OUT<5>
|
|
ATTRIBUTES | 8553348 | 0
|
|
OUTPUTMC | 1 | 6 | 2
|
|
INPUTS | 11 | UDS | FCS | Z3_ADR<2> | Z3_ADR_1 | AUTOCONFIG_Z3_ACCESS | Z3_ADR<3> | Z3_ADR<4> | Z3_ADR<5> | Z3_ADR_0 | Z3_ADR<6> | RESET
|
|
INPUTMC | 8 | 13 | 16 | 13 | 7 | 9 | 12 | 13 | 15 | 13 | 12 | 13 | 11 | 13 | 8 | 13 | 9
|
|
INPUTP | 3 | 155 | 147 | 263
|
|
EQ | 8 |
|
|
!D_OUT<5>.D = !UDS & !FCS & !Z3_ADR<2> & !Z3_ADR_1 &
|
|
AUTOCONFIG_Z3_ACCESS & !Z3_ADR<3> & !Z3_ADR<4> & !Z3_ADR<5>
|
|
# !UDS & !FCS & !Z3_ADR<2> & !Z3_ADR_0 & Z3_ADR<6> &
|
|
AUTOCONFIG_Z3_ACCESS & !Z3_ADR<3> & !Z3_ADR<4> & !Z3_ADR<5>
|
|
# !UDS & !FCS & !Z3_ADR_1 & !Z3_ADR_0 & Z3_ADR<6> &
|
|
AUTOCONFIG_Z3_ACCESS & !Z3_ADR<3> & !Z3_ADR<4> & !Z3_ADR<5>;
|
|
D_OUT<5>.CLK = CLK_EXT; // GCK
|
|
D_OUT<5>.AP = !RESET;
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 4 | 15 | D_OUT<6>
|
|
ATTRIBUTES | 8553348 | 0
|
|
OUTPUTMC | 1 | 6 | 4
|
|
INPUTS | 11 | UDS | FCS | Z3_ADR<2> | Z3_ADR_1 | Z3_ADR<6> | AUTOCONFIG_Z3_ACCESS | Z3_ADR<3> | Z3_ADR<4> | Z3_ADR<5> | Z3_ADR_0 | RESET
|
|
INPUTMC | 8 | 13 | 16 | 13 | 7 | 13 | 9 | 9 | 12 | 13 | 15 | 13 | 12 | 13 | 11 | 13 | 8
|
|
INPUTP | 3 | 155 | 147 | 263
|
|
EQ | 9 |
|
|
!D_OUT<6>.D = !UDS & !FCS & !Z3_ADR<2> & !Z3_ADR_1 & !Z3_ADR_0 &
|
|
AUTOCONFIG_Z3_ACCESS & !Z3_ADR<3> & !Z3_ADR<4> & !Z3_ADR<5>
|
|
# !UDS & !FCS & !Z3_ADR<2> & !Z3_ADR_1 & !Z3_ADR<6> &
|
|
AUTOCONFIG_Z3_ACCESS & !Z3_ADR<3> & !Z3_ADR<4> & !Z3_ADR<5>
|
|
# !UDS & !FCS & Z3_ADR<2> & !Z3_ADR_1 & Z3_ADR_0 &
|
|
Z3_ADR<6> & AUTOCONFIG_Z3_ACCESS & !Z3_ADR<3> & !Z3_ADR<4> &
|
|
!Z3_ADR<5>;
|
|
D_OUT<6>.CLK = CLK_EXT; // GCK
|
|
D_OUT<6>.AP = !RESET;
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 12 | 3 | D_OUT<7>
|
|
ATTRIBUTES | 8553348 | 0
|
|
OUTPUTMC | 1 | 6 | 11
|
|
INPUTS | 9 | UDS | FCS | Z3_ADR_1 | Z3_ADR<6> | AUTOCONFIG_Z3_ACCESS | Z3_ADR<3> | Z3_ADR<4> | Z3_ADR<5> | RESET
|
|
INPUTMC | 6 | 13 | 7 | 13 | 9 | 9 | 12 | 13 | 15 | 13 | 12 | 13 | 11
|
|
INPUTP | 3 | 155 | 147 | 263
|
|
EQ | 4 |
|
|
!D_OUT<7>.D = !UDS & !FCS & !Z3_ADR_1 & Z3_ADR<6> &
|
|
AUTOCONFIG_Z3_ACCESS & !Z3_ADR<3> & !Z3_ADR<4> & !Z3_ADR<5>;
|
|
D_OUT<7>.CLK = CLK_EXT; // GCK
|
|
D_OUT<7>.AP = !RESET;
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 11 | 6 | LAN_A_INIT<6>
|
|
ATTRIBUTES | 8553348 | 0
|
|
OUTPUTMC | 1 | 1 | 4
|
|
INPUTS | 2 | BUF_LAN_D_INIT<1> | RESET
|
|
INPUTMC | 1 | 11 | 10
|
|
INPUTP | 1 | 263
|
|
EQ | 3 |
|
|
!LAN_A_INIT<6>.D = BUF_LAN_D_INIT<1>;
|
|
LAN_A_INIT<6>.CLK = CLK_EXT; // GCK
|
|
LAN_A_INIT<6>.AP = RESET;
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 11 | 17 | LAN_CS_RST
|
|
ATTRIBUTES | 8553232 | 0
|
|
OUTPUTMC | 1 | 7 | 7
|
|
INPUTS | 4 | LAN_RST_SM_FSM_FFd3 | LAN_RST_SM_FSM_FFd2 | LAN_RST_SM_FSM_FFd1 | RESET
|
|
INPUTMC | 3 | 11 | 13 | 11 | 14 | 11 | 15
|
|
INPUTP | 1 | 263
|
|
EQ | 6 |
|
|
!LAN_CS_RST.D = !LAN_RST_SM_FSM_FFd3 & LAN_RST_SM_FSM_FFd2 &
|
|
LAN_RST_SM_FSM_FFd1
|
|
# !LAN_RST_SM_FSM_FFd3 & !LAN_RST_SM_FSM_FFd2 &
|
|
!LAN_RST_SM_FSM_FFd1;
|
|
LAN_CS_RST.CLK = CLK_EXT; // GCK
|
|
LAN_CS_RST.AR = RESET;
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 11 | 2 | LAN_IRQ_D0
|
|
ATTRIBUTES | 8553344 | 0
|
|
OUTPUTMC | 1 | 11 | 16
|
|
INPUTS | 2 | LAN_INT | RESET
|
|
INPUTP | 2 | 201 | 263
|
|
EQ | 3 |
|
|
LAN_IRQ_D0.D = LAN_INT;
|
|
LAN_IRQ_D0.CLK = CLK_EXT; // GCK
|
|
LAN_IRQ_D0.AP = !RESET;
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 10 | 8 | LAN_RD_S
|
|
ATTRIBUTES | 8553232 | 0
|
|
OUTPUTMC | 1 | 7 | 9
|
|
INPUTS | 6 | LAN_SM_FSM_FFd3 | LAN_SM_FSM_FFd2 | LAN_SM_FSM_FFd1 | LAN_SM_FSM_FFd4 | RW | LAN_SM_RST
|
|
INPUTMC | 5 | 15 | 16 | 10 | 7 | 10 | 12 | 10 | 6 | 11 | 0
|
|
INPUTP | 1 | 158
|
|
EQ | 7 |
|
|
LAN_RD_S.D = RW & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4
|
|
# !LAN_SM_FSM_FFd3 & LAN_SM_FSM_FFd2 &
|
|
!LAN_SM_FSM_FFd1
|
|
# LAN_SM_FSM_FFd4 & !LAN_SM_FSM_FFd2 &
|
|
!LAN_SM_FSM_FFd1;
|
|
LAN_RD_S.CLK = CLK_EXT; // GCK
|
|
LAN_RD_S.AR = LAN_SM_RST;
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 5 | 12 | LAN_READY
|
|
ATTRIBUTES | 8553232 | 0
|
|
OUTPUTMC | 1 | 13 | 4
|
|
INPUTS | 2 | BUF_LAN_READY | LAN_SM_RST
|
|
INPUTMC | 2 | 14 | 4 | 11 | 0
|
|
EQ | 3 |
|
|
LAN_READY.D = BUF_LAN_READY;
|
|
LAN_READY.CLK = CLK_EXT; // GCK
|
|
LAN_READY.AR = LAN_SM_RST;
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 14 | 7 | LAN_WRH_S
|
|
ATTRIBUTES | 8553232 | 0
|
|
OUTPUTMC | 1 | 7 | 4
|
|
INPUTS | 7 | DS0 | LAN_SM_FSM_FFd3 | LAN_SM_FSM_FFd2 | LAN_SM_FSM_FFd1 | LDS | LAN_SM_FSM_FFd4 | LAN_SM_RST
|
|
INPUTMC | 5 | 15 | 16 | 10 | 7 | 10 | 12 | 10 | 6 | 11 | 0
|
|
INPUTP | 2 | 170 | 157
|
|
EQ | 6 |
|
|
LAN_WRH_S.D = !LDS & LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 &
|
|
LAN_SM_FSM_FFd1
|
|
# !DS0 & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd2 &
|
|
LAN_SM_FSM_FFd1;
|
|
LAN_WRH_S.CLK = CLK_EXT; // GCK
|
|
LAN_WRH_S.AR = LAN_SM_RST;
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 14 | 8 | LAN_WRL_S
|
|
ATTRIBUTES | 8553232 | 0
|
|
OUTPUTMC | 1 | 12 | 13
|
|
INPUTS | 7 | DS1 | LAN_SM_FSM_FFd3 | LAN_SM_FSM_FFd2 | LAN_SM_FSM_FFd1 | UDS | LAN_SM_FSM_FFd4 | LAN_SM_RST
|
|
INPUTMC | 5 | 15 | 16 | 10 | 7 | 10 | 12 | 10 | 6 | 11 | 0
|
|
INPUTP | 2 | 148 | 155
|
|
EQ | 6 |
|
|
LAN_WRL_S.D = !UDS & LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 &
|
|
LAN_SM_FSM_FFd1
|
|
# !DS1 & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd2 &
|
|
LAN_SM_FSM_FFd1;
|
|
LAN_WRL_S.CLK = CLK_EXT; // GCK
|
|
LAN_WRL_S.AR = LAN_SM_RST;
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 15 | 15 | Z3_A_LOW
|
|
ATTRIBUTES | 8553232 | 0
|
|
OUTPUTMC | 1 | 3 | 5
|
|
INPUTS | 7 | LAN_SM_FSM_FFd4 | LAN_SM_FSM_FFd2 | LAN_SM_FSM_FFd3 | LAN_SM_FSM_FFd1 | $OpTx$FX_DC$10 | Z3_DATA<16>.EXP | LAN_SM_RST
|
|
INPUTMC | 7 | 10 | 6 | 10 | 7 | 15 | 16 | 10 | 12 | 5 | 10 | 15 | 14 | 11 | 0
|
|
IMPORTS | 1 | 15 | 14
|
|
EQ | 12 |
|
|
Z3_A_LOW.D = LAN_SM_FSM_FFd4 & !LAN_SM_FSM_FFd2
|
|
# LAN_SM_FSM_FFd3 & LAN_SM_FSM_FFd4 &
|
|
LAN_SM_FSM_FFd1
|
|
# !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 &
|
|
$OpTx$FX_DC$10
|
|
# !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd2 &
|
|
LAN_SM_FSM_FFd1
|
|
;Imported pterms FB16_15
|
|
# !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 &
|
|
!$OpTx$FX_DC$12;
|
|
Z3_A_LOW.CLK = CLK_EXT; // GCK
|
|
Z3_A_LOW.AR = LAN_SM_RST;
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 11 | 0 | LAN_SM_RST
|
|
ATTRIBUTES | 8553216 | 0
|
|
OUTPUTMC | 57 | 8 | 10 | 15 | 5 | 15 | 2 | 15 | 1 | 14 | 16 | 14 | 14 | 14 | 13 | 8 | 13 | 8 | 16 | 10 | 2 | 10 | 4 | 10 | 9 | 10 | 10 | 12 | 7 | 15 | 10 | 15 | 7 | 15 | 14 | 15 | 13 | 15 | 17 | 15 | 12 | 15 | 11 | 10 | 5 | 10 | 3 | 14 | 5 | 15 | 8 | 15 | 6 | 15 | 4 | 15 | 3 | 15 | 0 | 10 | 1 | 10 | 0 | 14 | 6 | 15 | 16 | 10 | 6 | 10 | 7 | 10 | 12 | 10 | 17 | 10 | 15 | 14 | 0 | 14 | 1 | 8 | 0 | 8 | 1 | 8 | 2 | 12 | 17 | 12 | 16 | 14 | 2 | 14 | 3 | 8 | 3 | 8 | 4 | 8 | 5 | 10 | 14 | 12 | 15 | 10 | 8 | 5 | 12 | 14 | 7 | 14 | 8 | 15 | 15
|
|
INPUTS | 4 | BERR | $OpTx$FX_DC$50 | BUF_CONFIG_READY | $OpTx$FX_DC$44
|
|
INPUTMC | 3 | 13 | 6 | 13 | 1 | 8 | 11
|
|
INPUTP | 1 | 176
|
|
EQ | 3 |
|
|
!LAN_SM_RST.D = BERR & !$OpTx$FX_DC$50 & !BUF_CONFIG_READY &
|
|
$OpTx$FX_DC$44;
|
|
!LAN_SM_RST.CLK = CLK_EXT; // GCK
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 8 | 12 | LAN_A_INIT<3>
|
|
ATTRIBUTES | 8553348 | 0
|
|
OUTPUTMC | 1 | 3 | 7
|
|
INPUTS | 1 | RESET
|
|
INPUTP | 1 | 263
|
|
EQ | 3 |
|
|
LAN_A_INIT<3>.D = Gnd;
|
|
LAN_A_INIT<3>.CLK = CLK_EXT; // GCK
|
|
LAN_A_INIT<3>.AP = RESET;
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 3 | 5 | A_LAN_0_OBUF
|
|
ATTRIBUTES | 264962 | 0
|
|
INPUTS | 2 | RESET | Z3_A_LOW
|
|
INPUTMC | 1 | 15 | 15
|
|
INPUTP | 1 | 263
|
|
EQ | 1 |
|
|
!A_LAN<0> = RESET & !Z3_A_LOW;
|
|
|
|
MACROCELL | 5 | 5 | A_LAN_10_OBUF
|
|
ATTRIBUTES | 264962 | 0
|
|
INPUTS | 2 | RESET | Z3_ADR<9>
|
|
INPUTMC | 1 | 0 | 2
|
|
INPUTP | 1 | 263
|
|
EQ | 1 |
|
|
!A_LAN<10> = RESET & !Z3_ADR<9>;
|
|
|
|
MACROCELL | 5 | 7 | A_LAN_11_OBUF
|
|
ATTRIBUTES | 264962 | 0
|
|
INPUTS | 2 | RESET | Z3_ADR<10>
|
|
INPUTMC | 1 | 0 | 3
|
|
INPUTP | 1 | 263
|
|
EQ | 1 |
|
|
!A_LAN<11> = RESET & !Z3_ADR<10>;
|
|
|
|
MACROCELL | 5 | 2 | A_LAN_12_OBUF
|
|
ATTRIBUTES | 264962 | 0
|
|
INPUTS | 2 | RESET | Z3_ADR<11>
|
|
INPUTMC | 1 | 8 | 7
|
|
INPUTP | 1 | 263
|
|
EQ | 1 |
|
|
!A_LAN<12> = RESET & !Z3_ADR<11>;
|
|
|
|
MACROCELL | 5 | 4 | A_LAN_13_OBUF
|
|
ATTRIBUTES | 264962 | 0
|
|
INPUTS | 2 | RESET | Z3_ADR<12>
|
|
INPUTMC | 1 | 8 | 8
|
|
INPUTP | 1 | 263
|
|
EQ | 1 |
|
|
!A_LAN<13> = RESET & !Z3_ADR<12>;
|
|
|
|
MACROCELL | 3 | 4 | A_LAN_1_OBUF
|
|
ATTRIBUTES | 264962 | 0
|
|
INPUTS | 2 | RESET | Z3_ADR_0
|
|
INPUTMC | 1 | 13 | 8
|
|
INPUTP | 1 | 263
|
|
EQ | 1 |
|
|
!A_LAN<1> = RESET & !Z3_ADR_0;
|
|
|
|
MACROCELL | 3 | 11 | A_LAN_2_OBUF
|
|
ATTRIBUTES | 264962 | 0
|
|
OUTPUTMC | 1 | 3 | 12
|
|
INPUTS | 9 | RESET | Z3_ADR_1 | A<5> | A<1> | A<2> | A<6> | A<3> | $OpTx$FX_DC$16 | A<4>
|
|
INPUTMC | 2 | 13 | 7 | 0 | 0
|
|
INPUTP | 7 | 263 | 91 | 107 | 101 | 98 | 99 | 97
|
|
EXPORTS | 1 | 3 | 12
|
|
EQ | 5 |
|
|
!A_LAN<2> = RESET & !Z3_ADR_1;
|
|
A_LAN_2_OBUF.EXP = !A<5> & A<1> & A<2> & !A<6> & !A<3> &
|
|
$OpTx$FX_DC$16
|
|
# !A<4> & A<1> & A<2> & !A<6> & !A<3> &
|
|
$OpTx$FX_DC$16
|
|
|
|
MACROCELL | 3 | 7 | A_LAN_3_OBUF
|
|
ATTRIBUTES | 264962 | 0
|
|
INPUTS | 3 | RESET | LAN_A_INIT<3> | Z3_ADR<2>
|
|
INPUTMC | 2 | 8 | 12 | 13 | 16
|
|
INPUTP | 1 | 263
|
|
EQ | 2 |
|
|
A_LAN<3> = RESET & Z3_ADR<2>
|
|
# !RESET & LAN_A_INIT<3>;
|
|
|
|
MACROCELL | 1 | 1 | A_LAN_4_OBUF
|
|
ATTRIBUTES | 264962 | 0
|
|
INPUTS | 2 | RESET | Z3_ADR<3>
|
|
INPUTMC | 1 | 13 | 15
|
|
INPUTP | 1 | 263
|
|
EQ | 1 |
|
|
!A_LAN<4> = RESET & !Z3_ADR<3>;
|
|
|
|
MACROCELL | 3 | 13 | A_LAN_5_OBUF
|
|
ATTRIBUTES | 264962 | 0
|
|
OUTPUTMC | 1 | 3 | 14
|
|
INPUTS | 10 | A<4> | A<3> | BUF_D_Z2_OUT<2> | AUTO_CONFIG_Z2_DONE<0> | $OpTx$FX_DC$49 | A<1> | A<2> | A<5> | A<6> | BUF_D_Z2_OUT<2>.EXP
|
|
INPUTMC | 4 | 3 | 12 | 9 | 15 | 13 | 3 | 3 | 12
|
|
INPUTP | 6 | 97 | 99 | 107 | 101 | 91 | 98
|
|
EXPORTS | 1 | 3 | 14
|
|
IMPORTS | 1 | 3 | 12
|
|
EQ | 8 |
|
|
!A_LAN<5> = ;Imported pterms FB4_13
|
|
RESET & !Z3_ADR<4>;
|
|
A_LAN_5_OBUF.EXP = !A<4> & A<3>
|
|
# A<3> & BUF_D_Z2_OUT<2>
|
|
# AUTO_CONFIG_Z2_DONE<0> & BUF_D_Z2_OUT<2> &
|
|
$OpTx$FX_DC$49
|
|
# A<1> & !A<2> & A<3>
|
|
# !A<5> & !A<1> & !A<6> & !A<3>
|
|
|
|
MACROCELL | 1 | 4 | A_LAN_6_OBUF
|
|
ATTRIBUTES | 264962 | 0
|
|
INPUTS | 3 | RESET | LAN_A_INIT<6> | Z3_ADR<5>
|
|
INPUTMC | 2 | 11 | 6 | 13 | 11
|
|
INPUTP | 1 | 263
|
|
EQ | 2 |
|
|
A_LAN<6> = RESET & Z3_ADR<5>
|
|
# !RESET & LAN_A_INIT<6>;
|
|
|
|
MACROCELL | 1 | 2 | A_LAN_7_OBUF
|
|
ATTRIBUTES | 264962 | 0
|
|
INPUTS | 2 | RESET | Z3_ADR<6>
|
|
INPUTMC | 1 | 13 | 9
|
|
INPUTP | 1 | 263
|
|
EQ | 1 |
|
|
!A_LAN<7> = RESET & !Z3_ADR<6>;
|
|
|
|
MACROCELL | 5 | 9 | A_LAN_8_OBUF
|
|
ATTRIBUTES | 264962 | 0
|
|
INPUTS | 2 | RESET | Z3_ADR<7>
|
|
INPUTMC | 1 | 12 | 8
|
|
INPUTP | 1 | 263
|
|
EQ | 1 |
|
|
!A_LAN<8> = RESET & !Z3_ADR<7>;
|
|
|
|
MACROCELL | 5 | 13 | A_LAN_9_OBUF
|
|
ATTRIBUTES | 264962 | 0
|
|
INPUTS | 2 | RESET | Z3_ADR<8>
|
|
INPUTMC | 1 | 12 | 6
|
|
INPUTP | 1 | 263
|
|
EQ | 1 |
|
|
!A_LAN<9> = RESET & !Z3_ADR<8>;
|
|
|
|
MACROCELL | 0 | 16 | IDE_R_OBUF
|
|
ATTRIBUTES | 264962 | 0
|
|
INPUTS | 4 | AS | RW | IDE_ENABLE | IDE_ACCESS
|
|
INPUTMC | 2 | 0 | 10 | 0 | 6
|
|
INPUTP | 2 | 152 | 158
|
|
EQ | 1 |
|
|
!IDE_R = !AS & RW & IDE_ENABLE & IDE_ACCESS;
|
|
|
|
MACROCELL | 7 | 7 | LAN_CS_OBUF
|
|
ATTRIBUTES | 264962 | 0
|
|
INPUTS | 3 | RESET | LAN_CS_RST | LAN_ACCESS
|
|
INPUTMC | 2 | 11 | 17 | 0 | 8
|
|
INPUTP | 1 | 263
|
|
EQ | 2 |
|
|
LAN_CS = RESET & LAN_ACCESS
|
|
# !RESET & LAN_CS_RST;
|
|
|
|
MACROCELL | 7 | 4 | LAN_WRH_OBUF
|
|
ATTRIBUTES | 264962 | 0
|
|
INPUTS | 3 | LAN_WR_RST | $OpTx$FX_DC$44 | LAN_WRH_S
|
|
INPUTMC | 3 | 11 | 12 | 8 | 11 | 14 | 7
|
|
EQ | 2 |
|
|
LAN_WRH = LAN_WR_RST & !$OpTx$FX_DC$44
|
|
# LAN_WRH_S & $OpTx$FX_DC$44;
|
|
|
|
MACROCELL | 12 | 13 | LAN_WRL_OBUF
|
|
ATTRIBUTES | 264962 | 0
|
|
INPUTS | 3 | LAN_WR_RST | $OpTx$FX_DC$44 | LAN_WRL_S
|
|
INPUTMC | 3 | 11 | 12 | 8 | 11 | 14 | 8
|
|
EQ | 2 |
|
|
LAN_WRL = LAN_WR_RST & !$OpTx$FX_DC$44
|
|
# LAN_WRL_S & $OpTx$FX_DC$44;
|
|
|
|
MACROCELL | 4 | 4 | ROM_OE_OBUF
|
|
ATTRIBUTES | 264962 | 0
|
|
INPUTS | 4 | AS | RW | IDE_ENABLE | IDE_ACCESS
|
|
INPUTMC | 2 | 0 | 10 | 0 | 6
|
|
INPUTP | 2 | 152 | 158
|
|
EQ | 1 |
|
|
!ROM_OE = !AS & RW & !IDE_ENABLE & IDE_ACCESS;
|
|
|
|
MACROCELL | 7 | 9 | LAN_RD_OBUF
|
|
ATTRIBUTES | 264962 | 0
|
|
INPUTS | 2 | LAN_RD_S | $OpTx$FX_DC$44
|
|
INPUTMC | 2 | 10 | 8 | 8 | 11
|
|
EQ | 1 |
|
|
LAN_RD = LAN_RD_S & $OpTx$FX_DC$44;
|
|
|
|
MACROCELL | 13 | 13 | SLAVE_OBUF
|
|
ATTRIBUTES | 264962 | 0
|
|
INPUTS | 5 | AUTOCONFIG_Z2_ACCESS | IDE_ACCESS | CP_ACCESS | ROM_B_0_OBUF$BUF2/ROM_B_0_OBUF$BUF2_TRST | AS
|
|
INPUTMC | 4 | 9 | 17 | 0 | 6 | 6 | 0 | 13 | 5
|
|
INPUTP | 1 | 152
|
|
EQ | 3 |
|
|
SLAVE = AS & !ROM_B_0_OBUF$BUF2/ROM_B_0_OBUF$BUF2_TRST
|
|
# !AUTOCONFIG_Z2_ACCESS & !IDE_ACCESS & !CP_ACCESS &
|
|
!ROM_B_0_OBUF$BUF2/ROM_B_0_OBUF$BUF2_TRST;
|
|
|
|
MACROCELL | 13 | 2 | ROM_B_0_OBUF$BUF2
|
|
ATTRIBUTES | 265986 | 0
|
|
INPUTS | 1 | ROM_B_0_OBUF$BUF2/ROM_B_0_OBUF$BUF2_TRST
|
|
INPUTMC | 1 | 13 | 5
|
|
EQ | 2 |
|
|
OVR = Gnd;
|
|
OVR.OE = ROM_B_0_OBUF$BUF2/ROM_B_0_OBUF$BUF2_TRST;
|
|
|
|
MACROCELL | 2 | 13 | ROM_B_0_OBUF$BUF8
|
|
ATTRIBUTES | 265986 | 0
|
|
INPUTS | 2 | LAN_INT_ENABLE | LAN_IRQ_OUT
|
|
INPUTMC | 2 | 0 | 17 | 11 | 16
|
|
EQ | 2 |
|
|
INT_OUT = Gnd;
|
|
INT_OUT.OE = LAN_INT_ENABLE & !LAN_IRQ_OUT;
|
|
|
|
MACROCELL | 14 | 11 | ROM_B_0_OBUF$BUF9
|
|
ATTRIBUTES | 265986 | 0
|
|
INPUTS | 1 | ROM_B_0_OBUF$BUF9/ROM_B_0_OBUF$BUF9_TRST
|
|
INPUTMC | 1 | 13 | 4
|
|
EQ | 2 |
|
|
DTACK = Gnd;
|
|
DTACK.OE = !ROM_B_0_OBUF$BUF9/ROM_B_0_OBUF$BUF9_TRST;
|
|
|
|
MACROCELL | 13 | 10 | CFOUT_OBUF
|
|
ATTRIBUTES | 264962 | 0
|
|
INPUTS | 3 | AUTO_CONFIG_Z2_DONE<0> | AUTO_CONFIG_Z2_DONE<1> | AUTO_CONFIG_DONE
|
|
INPUTMC | 3 | 9 | 15 | 9 | 14 | 12 | 11
|
|
EQ | 2 |
|
|
!CFOUT = AUTO_CONFIG_Z2_DONE<0> & AUTO_CONFIG_Z2_DONE<1> &
|
|
AUTO_CONFIG_DONE;
|
|
|
|
MACROCELL | 0 | 11 | IDE_A_0_OBUF$BUF0
|
|
ATTRIBUTES | 264962 | 0
|
|
INPUTS | 1 | A<9>.PIN
|
|
INPUTP | 1 | 108
|
|
EQ | 1 |
|
|
IDE_A<0> = A<9>.PIN;
|
|
|
|
MACROCELL | 0 | 14 | IDE_A_1_OBUF$BUF0
|
|
ATTRIBUTES | 264962 | 0
|
|
INPUTS | 1 | A<10>.PIN
|
|
INPUTP | 1 | 112
|
|
EQ | 1 |
|
|
IDE_A<1> = A<10>.PIN;
|
|
|
|
MACROCELL | 0 | 13 | IDE_A_2_OBUF$BUF0
|
|
ATTRIBUTES | 264962 | 0
|
|
INPUTS | 1 | A<11>.PIN
|
|
INPUTP | 1 | 114
|
|
EQ | 1 |
|
|
IDE_A<2> = A<11>.PIN;
|
|
|
|
MACROCELL | 0 | 7 | IDE_CS_0_OBUF
|
|
ATTRIBUTES | 264962 | 0
|
|
INPUTS | 1 | A<12>.PIN
|
|
INPUTP | 1 | 115
|
|
EQ | 1 |
|
|
IDE_CS<0> = !A<12>.PIN;
|
|
|
|
MACROCELL | 0 | 9 | IDE_CS_1_OBUF
|
|
ATTRIBUTES | 264962 | 0
|
|
INPUTS | 1 | A<13>.PIN
|
|
INPUTP | 1 | 123
|
|
EQ | 1 |
|
|
IDE_CS<1> = !A<13>.PIN;
|
|
|
|
MACROCELL | 2 | 1 | IDE_W_OBUF
|
|
ATTRIBUTES | 264962 | 0
|
|
INPUTS | 3 | AS | RW | IDE_ACCESS
|
|
INPUTMC | 1 | 0 | 6
|
|
INPUTP | 2 | 152 | 158
|
|
EQ | 1 |
|
|
!IDE_W = !AS & !RW & IDE_ACCESS;
|
|
|
|
MACROCELL | 13 | 14 | ROM_B_0_OBUF$BUF1
|
|
ATTRIBUTES | 265986 | 0
|
|
INPUTS | 0
|
|
EQ | 2 |
|
|
OWN = Gnd;
|
|
OWN.OE = Gnd;
|
|
|
|
MACROCELL | 15 | 9 | ROM_B_0_OBUF$BUF3
|
|
ATTRIBUTES | 265986 | 0
|
|
INPUTS | 0
|
|
EQ | 2 |
|
|
MTACK = Gnd;
|
|
MTACK.OE = Gnd;
|
|
|
|
MACROCELL | 11 | 1 | ROM_B_0_OBUF$BUF4
|
|
ATTRIBUTES | 265986 | 0
|
|
INPUTS | 0
|
|
EQ | 2 |
|
|
LAN_CFG<4> = Gnd;
|
|
LAN_CFG<4>.OE = Gnd;
|
|
|
|
MACROCELL | 1 | 7 | ROM_B_0_OBUF$BUF5
|
|
ATTRIBUTES | 265986 | 0
|
|
INPUTS | 0
|
|
EQ | 2 |
|
|
LAN_CFG<3> = Gnd;
|
|
LAN_CFG<3>.OE = Gnd;
|
|
|
|
MACROCELL | 5 | 1 | ROM_B_0_OBUF$BUF6
|
|
ATTRIBUTES | 265986 | 0
|
|
INPUTS | 0
|
|
EQ | 2 |
|
|
LAN_CFG<2> = Gnd;
|
|
LAN_CFG<2>.OE = Gnd;
|
|
|
|
MACROCELL | 1 | 5 | ROM_B_0_OBUF$BUF7
|
|
ATTRIBUTES | 265986 | 0
|
|
INPUTS | 0
|
|
EQ | 2 |
|
|
LAN_CFG<1> = Gnd;
|
|
LAN_CFG<1>.OE = Gnd;
|
|
|
|
MACROCELL | 10 | 16 | CP_WE_OBUF
|
|
ATTRIBUTES | 264962 | 0
|
|
OUTPUTMC | 1 | 10 | 15
|
|
INPUTS | 5 | D<2>.PIN | DQ_SWAP | LAN_SM_FSM_FFd3 | LAN_SM_FSM_FFd4 | $OpTx$FX_DC$10
|
|
INPUTMC | 4 | 0 | 15 | 15 | 16 | 10 | 6 | 5 | 10
|
|
INPUTP | 1 | 71
|
|
EXPORTS | 1 | 10 | 15
|
|
EQ | 3 |
|
|
CP_WE = Vcc;
|
|
CP_WE_OBUF.EXP = D<2>.PIN & DQ_SWAP & !LAN_SM_FSM_FFd3 &
|
|
!LAN_SM_FSM_FFd4 & !$OpTx$FX_DC$10
|
|
|
|
MACROCELL | 12 | 1 | CP_WE_OBUF$BUF0
|
|
ATTRIBUTES | 264962 | 0
|
|
INPUTS | 0
|
|
EQ | 1 |
|
|
CP_RD = Vcc;
|
|
|
|
MACROCELL | 4 | 1 | CP_WE_OBUF$BUF1
|
|
ATTRIBUTES | 264962 | 0
|
|
INPUTS | 0
|
|
EQ | 1 |
|
|
CP_CS = Vcc;
|
|
|
|
MACROCELL | 10 | 13 | ROM_B_0_OBUF
|
|
ATTRIBUTES | 264962 | 0
|
|
OUTPUTMC | 1 | 10 | 14
|
|
INPUTS | 5 | D<0>.PIN | DQ_SWAP | LAN_SM_FSM_FFd3 | LAN_SM_FSM_FFd4 | $OpTx$FX_DC$10
|
|
INPUTMC | 4 | 0 | 15 | 15 | 16 | 10 | 6 | 5 | 10
|
|
INPUTP | 1 | 4
|
|
EXPORTS | 1 | 10 | 14
|
|
EQ | 3 |
|
|
ROM_B<1> = Gnd;
|
|
ROM_B_0_OBUF.EXP = D<0>.PIN & DQ_SWAP & !LAN_SM_FSM_FFd3 &
|
|
!LAN_SM_FSM_FFd4 & !$OpTx$FX_DC$10
|
|
|
|
MACROCELL | 10 | 11 | ROM_B_0_OBUF$BUF0
|
|
ATTRIBUTES | 264962 | 0
|
|
INPUTS | 0
|
|
EQ | 1 |
|
|
ROM_B<0> = Gnd;
|
|
|
|
MACROCELL | 13 | 6 | $OpTx$FX_DC$50
|
|
ATTRIBUTES | 133888 | 0
|
|
OUTPUTMC | 19 | 8 | 10 | 15 | 5 | 15 | 2 | 15 | 1 | 14 | 16 | 14 | 14 | 14 | 13 | 8 | 13 | 8 | 16 | 10 | 2 | 10 | 4 | 10 | 9 | 10 | 10 | 12 | 7 | 15 | 10 | 15 | 7 | 11 | 0 | 0 | 1 | 14 | 17
|
|
INPUTS | 3 | LAN_ACCESS | $OpTx$FX_DC$10 | $OpTx$FX_DC$12
|
|
INPUTMC | 3 | 0 | 8 | 5 | 10 | 5 | 8
|
|
EQ | 2 |
|
|
$OpTx$FX_DC$50 = !LAN_ACCESS
|
|
# $OpTx$FX_DC$10 & $OpTx$FX_DC$12;
|
|
|
|
MACROCELL | 5 | 10 | $OpTx$FX_DC$10
|
|
ATTRIBUTES | 133888 | 0
|
|
OUTPUTMC | 33 | 15 | 16 | 10 | 7 | 10 | 17 | 10 | 15 | 12 | 17 | 14 | 1 | 14 | 12 | 8 | 0 | 8 | 2 | 12 | 14 | 12 | 16 | 14 | 2 | 14 | 0 | 8 | 3 | 8 | 1 | 8 | 4 | 10 | 14 | 12 | 15 | 15 | 15 | 13 | 6 | 0 | 0 | 0 | 12 | 8 | 5 | 8 | 6 | 8 | 17 | 10 | 0 | 10 | 13 | 10 | 16 | 12 | 0 | 14 | 3 | 14 | 4 | 14 | 17 | 15 | 17
|
|
INPUTS | 2 | UDS | LDS
|
|
INPUTP | 2 | 155 | 157
|
|
EQ | 1 |
|
|
$OpTx$FX_DC$10 = UDS & LDS;
|
|
|
|
MACROCELL | 5 | 8 | $OpTx$FX_DC$12
|
|
ATTRIBUTES | 133888 | 0
|
|
OUTPUTMC | 7 | 15 | 16 | 10 | 7 | 15 | 14 | 13 | 6 | 0 | 12 | 5 | 6 | 14 | 4
|
|
INPUTS | 2 | DS1 | DS0
|
|
INPUTP | 2 | 148 | 170
|
|
EQ | 1 |
|
|
$OpTx$FX_DC$12 = DS1 & DS0;
|
|
|
|
MACROCELL | 5 | 11 | SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF
|
|
ATTRIBUTES | 133888 | 0
|
|
OUTPUTMC | 26 | 9 | 15 | 9 | 14 | 3 | 8 | 3 | 10 | 6 | 16 | 6 | 15 | 6 | 14 | 6 | 13 | 6 | 12 | 6 | 10 | 3 | 9 | 7 | 15 | 7 | 14 | 7 | 13 | 7 | 12 | 7 | 11 | 7 | 10 | 7 | 8 | 7 | 6 | 7 | 5 | 6 | 9 | 7 | 3 | 3 | 0 | 3 | 15 | 3 | 6 | 3 | 3
|
|
INPUTS | 2 | C3 | C1
|
|
INPUTP | 2 | 187 | 188
|
|
EQ | 2 |
|
|
SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF = C3
|
|
$ C1;
|
|
|
|
MACROCELL | 0 | 0 | $OpTx$FX_DC$16
|
|
ATTRIBUTES | 133888 | 0
|
|
OUTPUTMC | 9 | 3 | 8 | 3 | 10 | 3 | 0 | 3 | 15 | 3 | 2 | 3 | 12 | 3 | 17 | 3 | 14 | 3 | 11
|
|
INPUTS | 3 | AS | AUTOCONFIG_Z2_ACCESS | $OpTx$FX_DC$10
|
|
INPUTMC | 2 | 9 | 17 | 5 | 10
|
|
INPUTP | 1 | 152
|
|
EQ | 1 |
|
|
$OpTx$FX_DC$16 = !AS & AUTOCONFIG_Z2_ACCESS & !$OpTx$FX_DC$10;
|
|
|
|
MACROCELL | 7 | 17 | BUF_IDE_ACCESS
|
|
ATTRIBUTES | 133888 | 0
|
|
OUTPUTMC | 2 | 0 | 10 | 0 | 6
|
|
INPUTS | 7 | SHUT_UP_Z2<1> | A<16>.PIN | IDE_BASEADR<0> | A<17>.PIN | IDE_BASEADR<1> | $OpTx$FX_DC$59.EXP | EXP26_.EXP
|
|
INPUTMC | 5 | 7 | 3 | 7 | 14 | 7 | 13 | 7 | 0 | 7 | 16
|
|
INPUTP | 2 | 175 | 172
|
|
IMPORTS | 2 | 7 | 0 | 7 | 16
|
|
EQ | 20 |
|
|
BUF_IDE_ACCESS = SHUT_UP_Z2<1>
|
|
# A<17>.PIN & !IDE_BASEADR<1>
|
|
# !A<17>.PIN & IDE_BASEADR<1>
|
|
# A<16>.PIN & !IDE_BASEADR<0>
|
|
# !A<16>.PIN & IDE_BASEADR<0>
|
|
;Imported pterms FB8_1
|
|
# !A<20>.PIN & IDE_BASEADR<4>
|
|
# IDE_BASEADR<5> & !A<21>.PIN
|
|
# !IDE_BASEADR<5> & A<21>.PIN
|
|
# !IDE_BASEADR<7> & A<23>.PIN
|
|
;Imported pterms FB8_17
|
|
# A<20>.PIN & !IDE_BASEADR<4>
|
|
# A<19>.PIN & !IDE_BASEADR<3>
|
|
# !A<19>.PIN & IDE_BASEADR<3>
|
|
# A<18>.PIN & !IDE_BASEADR<2>
|
|
# !A<18>.PIN & IDE_BASEADR<2>
|
|
;Imported pterms FB8_16
|
|
# IDE_BASEADR<6> & !A<22>.PIN
|
|
# !IDE_BASEADR<6> & A<22>.PIN
|
|
# IDE_BASEADR<7> & !A<23>.PIN;
|
|
|
|
MACROCELL | 3 | 2 | $OpTx$FX_DC$34
|
|
ATTRIBUTES | 133888 | 0
|
|
OUTPUTMC | 9 | 6 | 16 | 6 | 15 | 6 | 14 | 6 | 13 | 6 | 12 | 6 | 10 | 3 | 9 | 7 | 14 | 6 | 9
|
|
INPUTS | 9 | AUTO_CONFIG_Z2_DONE<0> | RW | A<5> | A<4> | A<1> | A<2> | A<6> | $OpTx$FX_DC$16 | BUF_D_Z2_OUT<2>
|
|
INPUTMC | 3 | 9 | 15 | 0 | 0 | 3 | 12
|
|
INPUTP | 6 | 158 | 91 | 97 | 107 | 101 | 98
|
|
EQ | 2 |
|
|
$OpTx$FX_DC$34 = !AUTO_CONFIG_Z2_DONE<0> & !RW & !A<5> & !A<4> &
|
|
!A<1> & !A<2> & A<6> & $OpTx$FX_DC$16 & !BUF_D_Z2_OUT<2>;
|
|
|
|
MACROCELL | 3 | 12 | BUF_D_Z2_OUT<2>
|
|
ATTRIBUTES | 133888 | 0
|
|
OUTPUTMC | 7 | 3 | 14 | 3 | 13 | 3 | 6 | 3 | 2 | 3 | 17 | 3 | 1 | 3 | 16
|
|
INPUTS | 11 | AUTO_CONFIG_Z2_DONE<0> | A<5> | A<4> | A<2> | A<6> | A<3> | $OpTx$FX_DC$16 | A<1> | RESET | Z3_ADR<4> | A_LAN_2_OBUF.EXP
|
|
INPUTMC | 4 | 9 | 15 | 0 | 0 | 13 | 12 | 3 | 11
|
|
INPUTP | 7 | 91 | 97 | 101 | 98 | 99 | 107 | 263
|
|
EXPORTS | 1 | 3 | 13
|
|
IMPORTS | 1 | 3 | 11
|
|
EQ | 14 |
|
|
BUF_D_Z2_OUT<2> = !A<5> & !A<4> & A<1> & !A<2> & !A<3> &
|
|
$OpTx$FX_DC$16
|
|
# !A<5> & !A<4> & !A<2> & A<6> & !A<3> &
|
|
$OpTx$FX_DC$16
|
|
# !AUTO_CONFIG_Z2_DONE<0> & !A<5> & !A<4> & A<2> &
|
|
!A<6> & !A<3> & $OpTx$FX_DC$16
|
|
# !A<5> & A<4> & !A<1> & A<2> & !A<6> & A<3> &
|
|
$OpTx$FX_DC$16
|
|
;Imported pterms FB4_12
|
|
# !A<5> & A<1> & A<2> & !A<6> & !A<3> &
|
|
$OpTx$FX_DC$16
|
|
# !A<4> & A<1> & A<2> & !A<6> & !A<3> &
|
|
$OpTx$FX_DC$16;
|
|
BUF_D_Z2_OUT<2>.EXP = RESET & !Z3_ADR<4>
|
|
|
|
MACROCELL | 3 | 17 | $OpTx$FX_DC$35
|
|
ATTRIBUTES | 133888 | 0
|
|
OUTPUTMC | 10 | 7 | 14 | 7 | 13 | 7 | 12 | 7 | 11 | 7 | 10 | 7 | 8 | 7 | 6 | 7 | 5 | 7 | 3 | 3 | 0
|
|
INPUTS | 12 | AUTO_CONFIG_Z2_DONE<0> | AUTO_CONFIG_Z2_DONE<1> | RW | A<5> | A<4> | A<1> | A<2> | A<6> | $OpTx$FX_DC$16 | BUF_D_Z2_OUT<2> | A<3> | BUF_D_Z2_OUT<3>
|
|
INPUTMC | 5 | 9 | 15 | 9 | 14 | 0 | 0 | 3 | 12 | 3 | 14
|
|
INPUTP | 7 | 158 | 91 | 97 | 107 | 101 | 98 | 99
|
|
EXPORTS | 1 | 3 | 0
|
|
EQ | 7 |
|
|
$OpTx$FX_DC$35 = AUTO_CONFIG_Z2_DONE<0> & !AUTO_CONFIG_Z2_DONE<1> &
|
|
!RW & !A<5> & !A<4> & !A<1> & !A<2> & A<6> &
|
|
$OpTx$FX_DC$16 & !BUF_D_Z2_OUT<2>;
|
|
$OpTx$FX_DC$35.EXP = !AUTO_CONFIG_Z2_DONE<0> & A<5> & A<3>
|
|
# !A<5> & !A<4> & A<3>
|
|
# A<4> & !A<2> & !A<3>
|
|
# !A<1> & A<3> & BUF_D_Z2_OUT<3>
|
|
|
|
MACROCELL | 13 | 1 | BUF_CONFIG_READY
|
|
ATTRIBUTES | 133888 | 0
|
|
OUTPUTMC | 4 | 0 | 17 | 11 | 8 | 11 | 0 | 13 | 0
|
|
INPUTS | 7 | FCS | LAN_ACCESS | Z3_ADR<13> | LAN_BASEADR<5> | A<21>.PIN | LAN_BASEADR<7> | A<23>.PIN
|
|
INPUTMC | 4 | 0 | 8 | 8 | 9 | 4 | 5 | 4 | 2
|
|
INPUTP | 3 | 147 | 163 | 161
|
|
EXPORTS | 1 | 13 | 0
|
|
EQ | 5 |
|
|
BUF_CONFIG_READY = !FCS & LAN_ACCESS & Z3_ADR<13>;
|
|
BUF_CONFIG_READY.EXP = LAN_BASEADR<5> & !A<21>.PIN
|
|
# !LAN_BASEADR<5> & A<21>.PIN
|
|
# LAN_BASEADR<7> & !A<23>.PIN
|
|
# !LAN_BASEADR<7> & A<23>.PIN
|
|
|
|
MACROCELL | 0 | 1 | DQ_5_IOBUFE/DQ_5_IOBUFE_TRST
|
|
ATTRIBUTES | 133888 | 0
|
|
OUTPUTMC | 16 | 9 | 16 | 11 | 9 | 9 | 1 | 9 | 9 | 9 | 13 | 11 | 11 | 9 | 2 | 7 | 1 | 11 | 7 | 7 | 2 | 11 | 4 | 9 | 5 | 9 | 4 | 9 | 7 | 9 | 11 | 9 | 10
|
|
INPUTS | 4 | RESET | FCS | $OpTx$FX_DC$50 | Z3_DATA<9>/Z3_DATA<9>_TRST
|
|
INPUTMC | 2 | 13 | 6 | 14 | 17
|
|
INPUTP | 2 | 263 | 147
|
|
EQ | 3 |
|
|
DQ_5_IOBUFE/DQ_5_IOBUFE_TRST = !RESET
|
|
# !FCS & !$OpTx$FX_DC$50 &
|
|
!Z3_DATA<9>/Z3_DATA<9>_TRST;
|
|
|
|
MACROCELL | 14 | 17 | Z3_DATA<9>/Z3_DATA<9>_TRST
|
|
ATTRIBUTES | 133888 | 0
|
|
OUTPUTMC | 20 | 3 | 1 | 4 | 13 | 4 | 14 | 4 | 16 | 14 | 15 | 6 | 4 | 6 | 11 | 1 | 14 | 4 | 9 | 1 | 11 | 0 | 5 | 0 | 4 | 1 | 9 | 1 | 13 | 1 | 16 | 4 | 11 | 0 | 1 | 0 | 12 | 6 | 3 | 14 | 0
|
|
INPUTS | 9 | RW | FCS | $OpTx$FX_DC$50 | D<11>.PIN | DQ_SWAP | LAN_SM_FSM_FFd3 | LAN_SM_FSM_FFd4 | $OpTx$FX_DC$10 | D<3>.PIN
|
|
INPUTMC | 5 | 13 | 6 | 0 | 15 | 15 | 16 | 10 | 6 | 5 | 10
|
|
INPUTP | 4 | 158 | 147 | 77 | 28
|
|
EXPORTS | 1 | 14 | 0
|
|
EQ | 5 |
|
|
Z3_DATA<9>/Z3_DATA<9>_TRST = RW & !FCS & !$OpTx$FX_DC$50;
|
|
Z3_DATA<9>/Z3_DATA<9>_TRST.EXP = D<11>.PIN & !DQ_SWAP & !LAN_SM_FSM_FFd3 &
|
|
!LAN_SM_FSM_FFd4 & !$OpTx$FX_DC$10
|
|
# D<3>.PIN & DQ_SWAP & !LAN_SM_FSM_FFd3 &
|
|
!LAN_SM_FSM_FFd4 & !$OpTx$FX_DC$10
|
|
|
|
MACROCELL | 0 | 12 | D_9_IOBUFE/D_9_IOBUFE_TRST
|
|
ATTRIBUTES | 133888 | 0
|
|
OUTPUTMC | 16 | 3 | 1 | 4 | 13 | 4 | 14 | 4 | 16 | 6 | 2 | 6 | 4 | 6 | 11 | 1 | 14 | 4 | 9 | 1 | 11 | 0 | 5 | 0 | 4 | 1 | 9 | 1 | 13 | 1 | 16 | 4 | 11
|
|
INPUTS | 8 | Z3_DATA<9>/Z3_DATA<9>_TRST | AS | RW | AUTOCONFIG_Z2_ACCESS | FCS | AUTOCONFIG_Z3_ACCESS | $OpTx$FX_DC$10 | $OpTx$FX_DC$12
|
|
INPUTMC | 5 | 14 | 17 | 9 | 17 | 9 | 12 | 5 | 10 | 5 | 8
|
|
INPUTP | 3 | 152 | 158 | 147
|
|
EQ | 6 |
|
|
D_9_IOBUFE/D_9_IOBUFE_TRST = Z3_DATA<9>/Z3_DATA<9>_TRST
|
|
# !AS & RW & AUTOCONFIG_Z2_ACCESS
|
|
# RW & !FCS & AUTOCONFIG_Z3_ACCESS &
|
|
!$OpTx$FX_DC$10
|
|
# RW & !FCS & AUTOCONFIG_Z3_ACCESS &
|
|
!$OpTx$FX_DC$12;
|
|
|
|
MACROCELL | 14 | 10 | $OpTx$FX_DC$36
|
|
ATTRIBUTES | 133888 | 0
|
|
OUTPUTMC | 8 | 4 | 13 | 4 | 14 | 4 | 16 | 4 | 11 | 6 | 4 | 6 | 11 | 1 | 16 | 6 | 3
|
|
INPUTS | 5 | UDS | RW | FCS | AUTOCONFIG_Z3_ACCESS | $OpTx$FX_DC$37
|
|
INPUTMC | 2 | 9 | 12 | 5 | 6
|
|
INPUTP | 3 | 155 | 158 | 147
|
|
EQ | 3 |
|
|
$OpTx$FX_DC$36 = !UDS & RW & !FCS & AUTOCONFIG_Z3_ACCESS
|
|
# RW & !FCS & AUTOCONFIG_Z3_ACCESS &
|
|
!$OpTx$FX_DC$37;
|
|
|
|
MACROCELL | 5 | 6 | $OpTx$FX_DC$37
|
|
ATTRIBUTES | 133888 | 0
|
|
OUTPUTMC | 2 | 14 | 10 | 14 | 15
|
|
INPUTS | 2 | LDS | $OpTx$FX_DC$12
|
|
INPUTMC | 1 | 5 | 8
|
|
INPUTP | 1 | 157
|
|
EQ | 1 |
|
|
$OpTx$FX_DC$37 = LDS & $OpTx$FX_DC$12;
|
|
|
|
MACROCELL | 14 | 15 | $OpTx$FX_SC$66
|
|
ATTRIBUTES | 133888 | 0
|
|
OUTPUTMC | 4 | 4 | 16 | 6 | 2 | 6 | 4 | 6 | 11
|
|
INPUTS | 6 | RW | FCS | AUTOCONFIG_Z3_ACCESS | Z3_DATA<9>/Z3_DATA<9>_TRST | $OpTx$FX_DC$37 | UDS
|
|
INPUTMC | 3 | 9 | 12 | 14 | 17 | 5 | 6
|
|
INPUTP | 3 | 158 | 147 | 155
|
|
EQ | 4 |
|
|
$OpTx$FX_SC$66 = !UDS & RW & !FCS & AUTOCONFIG_Z3_ACCESS &
|
|
!Z3_DATA<9>/Z3_DATA<9>_TRST
|
|
# RW & !FCS & AUTOCONFIG_Z3_ACCESS &
|
|
!Z3_DATA<9>/Z3_DATA<9>_TRST & !$OpTx$FX_DC$37;
|
|
|
|
MACROCELL | 5 | 15 | $OpTx$FX_DC$62
|
|
ATTRIBUTES | 133888 | 0
|
|
OUTPUTMC | 2 | 0 | 15 | 0 | 8
|
|
INPUTS | 2 | D<8>.PIN | LAN_BASEADR<8>
|
|
INPUTMC | 1 | 4 | 0
|
|
INPUTP | 1 | 32
|
|
EQ | 2 |
|
|
$OpTx$FX_DC$62 = D<8>.PIN
|
|
$ LAN_BASEADR<8>;
|
|
|
|
MACROCELL | 5 | 16 | $OpTx$FX_DC$61
|
|
ATTRIBUTES | 133888 | 0
|
|
OUTPUTMC | 2 | 0 | 15 | 0 | 8
|
|
INPUTS | 2 | D<9>.PIN | LAN_BASEADR<9>
|
|
INPUTMC | 1 | 1 | 3
|
|
INPUTP | 1 | 73
|
|
EQ | 2 |
|
|
$OpTx$FX_DC$61 = D<9>.PIN
|
|
$ LAN_BASEADR<9>;
|
|
|
|
MACROCELL | 5 | 17 | $OpTx$FX_DC$60
|
|
ATTRIBUTES | 133888 | 0
|
|
OUTPUTMC | 2 | 0 | 15 | 0 | 8
|
|
INPUTS | 2 | D<10>.PIN | LAN_BASEADR<10>
|
|
INPUTMC | 1 | 1 | 15
|
|
INPUTP | 1 | 74
|
|
EQ | 2 |
|
|
$OpTx$FX_DC$60 = D<10>.PIN
|
|
$ LAN_BASEADR<10>;
|
|
|
|
MACROCELL | 7 | 0 | $OpTx$FX_DC$59
|
|
ATTRIBUTES | 133888 | 0
|
|
OUTPUTMC | 3 | 0 | 15 | 0 | 8 | 7 | 17
|
|
INPUTS | 8 | D<11>.PIN | A<20>.PIN | IDE_BASEADR<4> | IDE_BASEADR<5> | A<21>.PIN | IDE_BASEADR<7> | A<23>.PIN | DQ_12_IOBUFE.EXP
|
|
INPUTMC | 4 | 7 | 10 | 7 | 8 | 7 | 5 | 7 | 1
|
|
INPUTP | 4 | 77 | 167 | 163 | 161
|
|
EXPORTS | 1 | 7 | 17
|
|
IMPORTS | 1 | 7 | 1
|
|
EQ | 7 |
|
|
$OpTx$FX_DC$59 = D<11>.PIN
|
|
$ ;Imported pterms FB8_2
|
|
LAN_BASEADR<11>;
|
|
$OpTx$FX_DC$59.EXP = !A<20>.PIN & IDE_BASEADR<4>
|
|
# IDE_BASEADR<5> & !A<21>.PIN
|
|
# !IDE_BASEADR<5> & A<21>.PIN
|
|
# !IDE_BASEADR<7> & A<23>.PIN
|
|
|
|
MACROCELL | 5 | 14 | $OpTx$FX_DC$63
|
|
ATTRIBUTES | 133888 | 0
|
|
OUTPUTMC | 2 | 0 | 15 | 0 | 8
|
|
INPUTS | 2 | D<15>.PIN | LAN_BASEADR<15>
|
|
INPUTMC | 1 | 4 | 12
|
|
INPUTP | 1 | 89
|
|
EQ | 2 |
|
|
$OpTx$FX_DC$63 = D<15>.PIN
|
|
$ LAN_BASEADR<15>;
|
|
|
|
MACROCELL | 8 | 6 | $OpTx$INV$5
|
|
ATTRIBUTES | 133888 | 0
|
|
OUTPUTMC | 3 | 0 | 15 | 0 | 8 | 8 | 5
|
|
INPUTS | 11 | LAN_BASEADR<6> | A<22>.PIN | DQ_SWAP | A<15>.PIN | $OpTx$FX_SC$31 | D<15>.PIN | LAN_SM_FSM_FFd3 | LAN_SM_FSM_FFd4 | $OpTx$FX_DC$10 | D<7>.PIN | Z3_ADR<11>.EXP
|
|
INPUTMC | 7 | 4 | 3 | 0 | 15 | 14 | 12 | 15 | 16 | 10 | 6 | 5 | 10 | 8 | 7
|
|
INPUTP | 4 | 162 | 139 | 89 | 29
|
|
EXPORTS | 1 | 8 | 5
|
|
IMPORTS | 1 | 8 | 7
|
|
EQ | 10 |
|
|
$OpTx$INV$5 = LAN_BASEADR<6> & !A<22>.PIN
|
|
# !LAN_BASEADR<6> & A<22>.PIN
|
|
;Imported pterms FB9_8
|
|
# D<13>.PIN & !LAN_BASEADR<13>
|
|
# !D<13>.PIN & LAN_BASEADR<13>;
|
|
$OpTx$INV$5.EXP = !DQ_SWAP & A<15>.PIN & $OpTx$FX_SC$31
|
|
# D<15>.PIN & DQ_SWAP & !LAN_SM_FSM_FFd3 &
|
|
!LAN_SM_FSM_FFd4 & !$OpTx$FX_DC$10
|
|
# D<7>.PIN & !DQ_SWAP & !LAN_SM_FSM_FFd3 &
|
|
!LAN_SM_FSM_FFd4 & !$OpTx$FX_DC$10
|
|
|
|
MACROCELL | 13 | 0 | $OpTx$INV$4
|
|
ATTRIBUTES | 133888 | 0
|
|
OUTPUTMC | 2 | 0 | 15 | 0 | 8
|
|
INPUTS | 8 | A<16>.PIN | LAN_BASEADR<0> | A<17>.PIN | LAN_BASEADR<1> | A<18>.PIN | LAN_BASEADR<2> | BUF_CONFIG_READY.EXP | EXP29_.EXP
|
|
INPUTMC | 5 | 1 | 17 | 4 | 10 | 4 | 8 | 13 | 1 | 13 | 17
|
|
INPUTP | 3 | 175 | 172 | 171
|
|
IMPORTS | 2 | 13 | 1 | 13 | 17
|
|
EQ | 19 |
|
|
$OpTx$INV$4 = A<18>.PIN & !LAN_BASEADR<2>
|
|
# A<17>.PIN & !LAN_BASEADR<1>
|
|
# !A<17>.PIN & LAN_BASEADR<1>
|
|
# A<16>.PIN & !LAN_BASEADR<0>
|
|
# !A<16>.PIN & LAN_BASEADR<0>
|
|
;Imported pterms FB14_2
|
|
# LAN_BASEADR<5> & !A<21>.PIN
|
|
# !LAN_BASEADR<5> & A<21>.PIN
|
|
# LAN_BASEADR<7> & !A<23>.PIN
|
|
# !LAN_BASEADR<7> & A<23>.PIN
|
|
;Imported pterms FB14_18
|
|
# A<20>.PIN & !LAN_BASEADR<4>
|
|
# !A<20>.PIN & LAN_BASEADR<4>
|
|
# A<19>.PIN & !LAN_BASEADR<3>
|
|
# !A<19>.PIN & LAN_BASEADR<3>
|
|
# !A<18>.PIN & LAN_BASEADR<2>
|
|
;Imported pterms FB14_17
|
|
# D<14>.PIN & !LAN_BASEADR<14>
|
|
# !D<14>.PIN & LAN_BASEADR<14>;
|
|
|
|
MACROCELL | 5 | 3 | $OpTx$FX_DC$57
|
|
ATTRIBUTES | 133888 | 0
|
|
OUTPUTMC | 2 | 10 | 6 | 10 | 12
|
|
INPUTS | 2 | LAN_SM_FSM_FFd2 | BUF_LAN_READY
|
|
INPUTMC | 2 | 10 | 7 | 14 | 4
|
|
EQ | 1 |
|
|
$OpTx$FX_DC$57 = LAN_SM_FSM_FFd2 & !BUF_LAN_READY;
|
|
|
|
MACROCELL | 14 | 4 | BUF_LAN_READY
|
|
ATTRIBUTES | 133888 | 0
|
|
OUTPUTMC | 5 | 10 | 6 | 10 | 12 | 5 | 12 | 5 | 3 | 14 | 3
|
|
INPUTS | 10 | LAN_SM_FSM_FFd3 | LAN_SM_FSM_FFd2 | LAN_SM_FSM_FFd4 | $OpTx$FX_DC$12 | LAN_SM_FSM_FFd1 | D<12>.PIN | DQ_SWAP | $OpTx$FX_DC$10 | D<4>.PIN | Z3_DATA<23>.EXP
|
|
INPUTMC | 8 | 15 | 16 | 10 | 7 | 10 | 6 | 5 | 8 | 10 | 12 | 0 | 15 | 5 | 10 | 14 | 5
|
|
INPUTP | 2 | 78 | 38
|
|
EXPORTS | 1 | 14 | 3
|
|
IMPORTS | 1 | 14 | 5
|
|
EQ | 12 |
|
|
BUF_LAN_READY = LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd2
|
|
# LAN_SM_FSM_FFd3 & LAN_SM_FSM_FFd4 &
|
|
LAN_SM_FSM_FFd1
|
|
# !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 &
|
|
$OpTx$FX_DC$12
|
|
;Imported pterms FB15_6
|
|
# !LAN_SM_FSM_FFd4 & !LAN_SM_FSM_FFd2 &
|
|
LAN_SM_FSM_FFd1;
|
|
BUF_LAN_READY.EXP = D<12>.PIN & DQ_SWAP & !LAN_SM_FSM_FFd3 &
|
|
!LAN_SM_FSM_FFd4 & !$OpTx$FX_DC$10
|
|
# D<4>.PIN & !DQ_SWAP & !LAN_SM_FSM_FFd3 &
|
|
!LAN_SM_FSM_FFd4 & !$OpTx$FX_DC$10
|
|
|
|
MACROCELL | 11 | 10 | BUF_LAN_D_INIT<1>
|
|
ATTRIBUTES | 133888 | 0
|
|
OUTPUTMC | 3 | 11 | 5 | 11 | 3 | 11 | 6
|
|
INPUTS | 3 | LAN_RST_SM_FSM_FFd3 | LAN_RST_SM_FSM_FFd2 | LAN_RST_SM_FSM_FFd1
|
|
INPUTMC | 3 | 11 | 13 | 11 | 14 | 11 | 15
|
|
EQ | 2 |
|
|
BUF_LAN_D_INIT<1> = LAN_RST_SM_FSM_FFd3 & !LAN_RST_SM_FSM_FFd1
|
|
# !LAN_RST_SM_FSM_FFd3 & LAN_RST_SM_FSM_FFd2;
|
|
|
|
MACROCELL | 14 | 9 | $OpTx$FX_DC$30
|
|
ATTRIBUTES | 133888 | 0
|
|
OUTPUTMC | 16 | 10 | 17 | 10 | 15 | 14 | 0 | 14 | 1 | 8 | 0 | 8 | 1 | 8 | 2 | 12 | 17 | 12 | 16 | 14 | 2 | 14 | 3 | 8 | 3 | 8 | 4 | 8 | 5 | 10 | 14 | 12 | 15
|
|
INPUTS | 4 | LAN_SM_FSM_FFd3 | LAN_SM_FSM_FFd4 | LAN_SM_FSM_FFd2 | LAN_SM_FSM_FFd1
|
|
INPUTMC | 4 | 15 | 16 | 10 | 6 | 10 | 7 | 10 | 12
|
|
EQ | 4 |
|
|
$OpTx$FX_DC$30 = LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 &
|
|
LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1
|
|
# !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 &
|
|
!LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1;
|
|
|
|
MACROCELL | 14 | 12 | $OpTx$FX_SC$31
|
|
ATTRIBUTES | 133888 | 0
|
|
OUTPUTMC | 18 | 10 | 17 | 10 | 15 | 14 | 0 | 14 | 1 | 8 | 0 | 8 | 1 | 8 | 2 | 12 | 17 | 12 | 16 | 14 | 2 | 14 | 3 | 8 | 3 | 8 | 4 | 8 | 5 | 10 | 14 | 12 | 15 | 8 | 6 | 8 | 17
|
|
INPUTS | 5 | LAN_SM_FSM_FFd3 | LAN_SM_FSM_FFd4 | $OpTx$FX_DC$10 | LAN_SM_FSM_FFd2 | LAN_SM_FSM_FFd1
|
|
INPUTMC | 5 | 15 | 16 | 10 | 6 | 5 | 10 | 10 | 7 | 10 | 12
|
|
EQ | 4 |
|
|
$OpTx$FX_SC$31 = !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 &
|
|
$OpTx$FX_DC$10
|
|
# !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 &
|
|
!LAN_SM_FSM_FFd1;
|
|
|
|
MACROCELL | 3 | 14 | BUF_D_Z2_OUT<3>
|
|
ATTRIBUTES | 133888 | 0
|
|
OUTPUTMC | 6 | 3 | 0 | 3 | 15 | 3 | 3 | 3 | 1 | 3 | 16 | 3 | 17
|
|
INPUTS | 8 | $OpTx$FX_DC$16 | A<5> | BUF_D_Z2_OUT<2> | $OpTx$FX_DC$49 | A<6> | A<4> | A<3> | A_LAN_5_OBUF.EXP
|
|
INPUTMC | 4 | 0 | 0 | 3 | 12 | 13 | 3 | 3 | 13
|
|
INPUTP | 4 | 91 | 98 | 97 | 99
|
|
EXPORTS | 1 | 3 | 15
|
|
IMPORTS | 1 | 3 | 13
|
|
EQ | 12 |
|
|
BUF_D_Z2_OUT<3> = !$OpTx$FX_DC$16
|
|
# A<5> & BUF_D_Z2_OUT<2>
|
|
# A<5> & !$OpTx$FX_DC$49
|
|
# A<6> & !BUF_D_Z2_OUT<2>
|
|
;Imported pterms FB4_14
|
|
# !A<4> & A<3>
|
|
# A<3> & BUF_D_Z2_OUT<2>
|
|
# AUTO_CONFIG_Z2_DONE<0> & BUF_D_Z2_OUT<2> &
|
|
$OpTx$FX_DC$49
|
|
# A<1> & !A<2> & A<3>
|
|
# !A<5> & !A<1> & !A<6> & !A<3>;
|
|
BUF_D_Z2_OUT<3>.EXP = !A<4> & A<3>
|
|
|
|
MACROCELL | 13 | 3 | $OpTx$FX_DC$49
|
|
ATTRIBUTES | 133888 | 0
|
|
OUTPUTMC | 3 | 3 | 0 | 3 | 14 | 3 | 13
|
|
INPUTS | 2 | A<4> | A<2>
|
|
INPUTP | 2 | 97 | 101
|
|
EQ | 1 |
|
|
$OpTx$FX_DC$49 = !A<4> & A<2>;
|
|
|
|
MACROCELL | 8 | 11 | $OpTx$FX_DC$44
|
|
ATTRIBUTES | 133888 | 0
|
|
OUTPUTMC | 4 | 11 | 0 | 7 | 4 | 12 | 13 | 7 | 9
|
|
INPUTS | 2 | RESET | FCS
|
|
INPUTP | 2 | 263 | 147
|
|
EQ | 1 |
|
|
$OpTx$FX_DC$44 = RESET & !FCS;
|
|
|
|
MACROCELL | 13 | 5 | ROM_B_0_OBUF$BUF2/ROM_B_0_OBUF$BUF2_TRST
|
|
ATTRIBUTES | 133888 | 0
|
|
OUTPUTMC | 2 | 13 | 13 | 13 | 2
|
|
INPUTS | 3 | FCS | LAN_ACCESS | AUTOCONFIG_Z3_ACCESS
|
|
INPUTMC | 2 | 0 | 8 | 9 | 12
|
|
INPUTP | 1 | 147
|
|
EQ | 2 |
|
|
ROM_B_0_OBUF$BUF2/ROM_B_0_OBUF$BUF2_TRST = !FCS & LAN_ACCESS
|
|
# !FCS & AUTOCONFIG_Z3_ACCESS;
|
|
|
|
MACROCELL | 13 | 4 | ROM_B_0_OBUF$BUF9/ROM_B_0_OBUF$BUF9_TRST
|
|
ATTRIBUTES | 133888 | 0
|
|
OUTPUTMC | 1 | 14 | 11
|
|
INPUTS | 4 | FCS | AUTOCONFIG_Z3_ACCESS | CONFIG_READY | LAN_READY
|
|
INPUTMC | 3 | 9 | 12 | 11 | 8 | 5 | 12
|
|
INPUTP | 1 | 147
|
|
EQ | 2 |
|
|
ROM_B_0_OBUF$BUF9/ROM_B_0_OBUF$BUF9_TRST = FCS
|
|
# !AUTOCONFIG_Z3_ACCESS & !CONFIG_READY & !LAN_READY;
|
|
|
|
MACROCELL | 3 | 16 | EXP22_
|
|
ATTRIBUTES | 2048 | 0
|
|
OUTPUTMC | 1 | 3 | 15
|
|
INPUTS | 6 | A<4> | A<2> | BUF_D_Z2_OUT<3> | BUF_D_Z2_OUT<2> | AUTO_CONFIG_Z2_DONE<0> | A<3>
|
|
INPUTMC | 3 | 3 | 14 | 3 | 12 | 9 | 15
|
|
INPUTP | 3 | 97 | 101 | 99
|
|
EXPORTS | 1 | 3 | 15
|
|
EQ | 6 |
|
|
EXP22_.EXP = A<4> & !A<2> & BUF_D_Z2_OUT<3>
|
|
# A<2> & BUF_D_Z2_OUT<2> & !BUF_D_Z2_OUT<3>
|
|
# AUTO_CONFIG_Z2_DONE<0> & A<4> & !A<3> &
|
|
!BUF_D_Z2_OUT<3>
|
|
# !AUTO_CONFIG_Z2_DONE<0> & A<4> & A<2> & !A<3>
|
|
# !A<4> & A<2> & !BUF_D_Z2_OUT<2> & BUF_D_Z2_OUT<3>
|
|
|
|
MACROCELL | 6 | 1 | EXP23_
|
|
ATTRIBUTES | 2048 | 0
|
|
OUTPUTMC | 1 | 6 | 0
|
|
INPUTS | 7 | A<20>.PIN | CP_BASEADR<4> | A<19>.PIN | CP_BASEADR<3> | CP_BASEADR<5> | A<21>.PIN | D_13_IOBUFE.EXP
|
|
INPUTMC | 4 | 6 | 12 | 6 | 13 | 6 | 10 | 6 | 2
|
|
INPUTP | 3 | 167 | 169 | 163
|
|
EXPORTS | 1 | 6 | 0
|
|
IMPORTS | 1 | 6 | 2
|
|
EQ | 9 |
|
|
EXP23_.EXP = A<20>.PIN & !CP_BASEADR<4>
|
|
# !A<20>.PIN & CP_BASEADR<4>
|
|
# !A<19>.PIN & CP_BASEADR<3>
|
|
# CP_BASEADR<5> & !A<21>.PIN
|
|
# !CP_BASEADR<5> & A<21>.PIN
|
|
;Imported pterms FB7_3
|
|
# CP_BASEADR<6> & !A<22>.PIN
|
|
# !CP_BASEADR<6> & A<22>.PIN
|
|
# CP_BASEADR<7> & !A<23>.PIN
|
|
|
|
MACROCELL | 6 | 3 | EXP24_
|
|
ATTRIBUTES | 2048 | 0
|
|
OUTPUTMC | 1 | 6 | 2
|
|
INPUTS | 4 | Z3_DATA<29> | Z3_DATA<9>/Z3_DATA<9>_TRST | D_Z2_OUT<1> | $OpTx$FX_DC$36
|
|
INPUTMC | 4 | 10 | 1 | 14 | 17 | 3 | 15 | 14 | 10
|
|
EXPORTS | 1 | 6 | 2
|
|
EQ | 3 |
|
|
EXP24_.EXP = Z3_DATA<29> & Z3_DATA<9>/Z3_DATA<9>_TRST
|
|
# D_Z2_OUT<1> & !Z3_DATA<9>/Z3_DATA<9>_TRST &
|
|
!$OpTx$FX_DC$36
|
|
|
|
MACROCELL | 6 | 17 | EXP25_
|
|
ATTRIBUTES | 2048 | 0
|
|
OUTPUTMC | 1 | 6 | 0
|
|
INPUTS | 7 | A<19>.PIN | CP_BASEADR<3> | A<18>.PIN | CP_BASEADR<2> | A<17>.PIN | CP_BASEADR<1> | CP_BASEADR<0>.EXP
|
|
INPUTMC | 4 | 6 | 13 | 6 | 14 | 6 | 15 | 6 | 16
|
|
INPUTP | 3 | 169 | 171 | 172
|
|
EXPORTS | 1 | 6 | 0
|
|
IMPORTS | 1 | 6 | 16
|
|
EQ | 7 |
|
|
EXP25_.EXP = A<19>.PIN & !CP_BASEADR<3>
|
|
# A<18>.PIN & !CP_BASEADR<2>
|
|
# !A<18>.PIN & CP_BASEADR<2>
|
|
# A<17>.PIN & !CP_BASEADR<1>
|
|
# !A<17>.PIN & CP_BASEADR<1>
|
|
;Imported pterms FB7_17
|
|
# !CP_BASEADR<7> & A<23>.PIN
|
|
|
|
MACROCELL | 7 | 16 | EXP26_
|
|
ATTRIBUTES | 2048 | 0
|
|
OUTPUTMC | 1 | 7 | 17
|
|
INPUTS | 7 | A<20>.PIN | IDE_BASEADR<4> | A<19>.PIN | IDE_BASEADR<3> | A<18>.PIN | IDE_BASEADR<2> | CP_BASEADR<7>.EXP
|
|
INPUTMC | 4 | 7 | 10 | 7 | 11 | 7 | 12 | 7 | 15
|
|
INPUTP | 3 | 167 | 169 | 171
|
|
EXPORTS | 1 | 7 | 17
|
|
IMPORTS | 1 | 7 | 15
|
|
EQ | 9 |
|
|
EXP26_.EXP = A<20>.PIN & !IDE_BASEADR<4>
|
|
# A<19>.PIN & !IDE_BASEADR<3>
|
|
# !A<19>.PIN & IDE_BASEADR<3>
|
|
# A<18>.PIN & !IDE_BASEADR<2>
|
|
# !A<18>.PIN & IDE_BASEADR<2>
|
|
;Imported pterms FB8_16
|
|
# IDE_BASEADR<6> & !A<22>.PIN
|
|
# !IDE_BASEADR<6> & A<22>.PIN
|
|
# IDE_BASEADR<7> & !A<23>.PIN
|
|
|
|
MACROCELL | 8 | 17 | EXP27_
|
|
ATTRIBUTES | 2048 | 0
|
|
OUTPUTMC | 1 | 8 | 0
|
|
INPUTS | 8 | A<21>.PIN | DQ_SWAP | $OpTx$FX_SC$31 | D<13>.PIN | LAN_SM_FSM_FFd3 | LAN_SM_FSM_FFd4 | $OpTx$FX_DC$10 | D<5>.PIN
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INPUTMC | 5 | 0 | 15 | 14 | 12 | 15 | 16 | 10 | 6 | 5 | 10
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INPUTP | 3 | 163 | 80 | 37
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EXPORTS | 1 | 8 | 0
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EQ | 5 |
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EXP27_.EXP = A<21>.PIN & !DQ_SWAP & $OpTx$FX_SC$31
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# D<13>.PIN & !DQ_SWAP & !LAN_SM_FSM_FFd3 &
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!LAN_SM_FSM_FFd4 & !$OpTx$FX_DC$10
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# D<5>.PIN & DQ_SWAP & !LAN_SM_FSM_FFd3 &
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!LAN_SM_FSM_FFd4 & !$OpTx$FX_DC$10
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MACROCELL | 12 | 0 | EXP28_
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ATTRIBUTES | 2048 | 0
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OUTPUTMC | 1 | 12 | 17
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INPUTS | 6 | D<9>.PIN | DQ_SWAP | LAN_SM_FSM_FFd3 | LAN_SM_FSM_FFd4 | $OpTx$FX_DC$10 | D<1>.PIN
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INPUTMC | 4 | 0 | 15 | 15 | 16 | 10 | 6 | 5 | 10
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INPUTP | 2 | 73 | 30
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EXPORTS | 1 | 12 | 17
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EQ | 4 |
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EXP28_.EXP = D<9>.PIN & DQ_SWAP & !LAN_SM_FSM_FFd3 &
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!LAN_SM_FSM_FFd4 & !$OpTx$FX_DC$10
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# D<1>.PIN & !DQ_SWAP & !LAN_SM_FSM_FFd3 &
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!LAN_SM_FSM_FFd4 & !$OpTx$FX_DC$10
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MACROCELL | 13 | 17 | EXP29_
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ATTRIBUTES | 2048 | 0
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OUTPUTMC | 1 | 13 | 0
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INPUTS | 7 | A<20>.PIN | LAN_BASEADR<4> | A<19>.PIN | LAN_BASEADR<3> | A<18>.PIN | LAN_BASEADR<2> | Z3_ADR<2>.EXP
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INPUTMC | 4 | 4 | 6 | 4 | 7 | 4 | 8 | 13 | 16
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INPUTP | 3 | 167 | 169 | 171
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EXPORTS | 1 | 13 | 0
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IMPORTS | 1 | 13 | 16
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EQ | 8 |
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EXP29_.EXP = A<20>.PIN & !LAN_BASEADR<4>
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# !A<20>.PIN & LAN_BASEADR<4>
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# A<19>.PIN & !LAN_BASEADR<3>
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# !A<19>.PIN & LAN_BASEADR<3>
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# !A<18>.PIN & LAN_BASEADR<2>
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;Imported pterms FB14_17
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# D<14>.PIN & !LAN_BASEADR<14>
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# !D<14>.PIN & LAN_BASEADR<14>
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PIN | Z3 | 64 | 0 | N/A | 151 | 3 | 0 | 15 | 0 | 8 | 9 | 12
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PIN | CFIN | 64 | 0 | N/A | 190 | 2 | 9 | 17 | 9 | 12
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PIN | CLK_EXT | 4096 | 0 | N/A | 57 | 98 | 8 | 10 | 15 | 5 | 15 | 2 | 15 | 1 | 14 | 16 | 14 | 14 | 14 | 13 | 8 | 13 | 8 | 16 | 10 | 2 | 10 | 4 | 10 | 9 | 10 | 10 | 12 | 7 | 15 | 10 | 15 | 7 | 12 | 11 | 12 | 10 | 1 | 17 | 1 | 15 | 1 | 12 | 1 | 10 | 1 | 8 | 1 | 6 | 4 | 12 | 4 | 10 | 4 | 8 | 4 | 7 | 4 | 6 | 4 | 5 | 4 | 3 | 4 | 2 | 4 | 0 | 1 | 3 | 0 | 17 | 11 | 16 | 15 | 14 | 15 | 13 | 15 | 17 | 15 | 12 | 15 | 11 | 10 | 5 | 10 | 3 | 14 | 5 | 15 | 8 | 15 | 6 | 15 | 4 | 15 | 3 | 15 | 0 | 10 | 1 | 10 | 0 | 14 | 6 | 15 | 16 | 10 | 6 | 10 | 7 | 10 | 12 | 11 | 13 | 11 | 14 | 11 | 15 | 11 | 5 | 11 | 3 | 10 | 17 | 10 | 15 | 14 | 0 | 14 | 1 | 8 | 0 | 8 | 1 | 8 | 2 | 12 | 17 | 12 | 16 | 14 | 2 | 14 | 3 | 8 | 3 | 8 | 4 | 8 | 5 | 10 | 14 | 12 | 15 | 11 | 12 | 1 | 0 | 11 | 8 | 12 | 5 | 12 | 14 | 12 | 9 | 12 | 4 | 12 | 12 | 4 | 17 | 4 | 15 | 12 | 3 | 11 | 6 | 11 | 17 | 11 | 2 | 10 | 8 | 5 | 12 | 14 | 7 | 14 | 8 | 15 | 15 | 8 | 12 | 11 | 0
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PIN | FCS | 64 | 0 | N/A | 147 | 69 | 8 | 10 | 15 | 5 | 15 | 2 | 15 | 1 | 14 | 16 | 14 | 14 | 14 | 13 | 8 | 13 | 8 | 16 | 10 | 2 | 10 | 4 | 10 | 9 | 10 | 10 | 12 | 7 | 15 | 10 | 15 | 7 | 12 | 11 | 12 | 10 | 1 | 17 | 1 | 15 | 1 | 12 | 1 | 10 | 1 | 8 | 1 | 6 | 4 | 12 | 4 | 10 | 4 | 8 | 4 | 7 | 4 | 6 | 4 | 5 | 4 | 3 | 4 | 2 | 4 | 0 | 1 | 3 | 0 | 15 | 13 | 16 | 13 | 7 | 13 | 8 | 13 | 9 | 0 | 8 | 9 | 12 | 13 | 15 | 13 | 12 | 13 | 11 | 8 | 9 | 1 | 0 | 0 | 3 | 8 | 7 | 8 | 8 | 12 | 8 | 12 | 6 | 0 | 2 | 12 | 5 | 12 | 14 | 12 | 9 | 12 | 4 | 12 | 12 | 4 | 17 | 4 | 15 | 12 | 3 | 13 | 1 | 0 | 1 | 14 | 17 | 0 | 12 | 14 | 10 | 14 | 15 | 8 | 11 | 13 | 5 | 13 | 4
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PIN | RW | 64 | 0 | N/A | 158 | 50 | 8 | 10 | 15 | 5 | 15 | 2 | 15 | 1 | 14 | 16 | 14 | 14 | 14 | 13 | 8 | 13 | 8 | 16 | 10 | 2 | 10 | 4 | 10 | 9 | 10 | 10 | 12 | 7 | 15 | 10 | 15 | 7 | 3 | 8 | 3 | 10 | 0 | 10 | 12 | 10 | 1 | 17 | 1 | 15 | 1 | 12 | 1 | 10 | 1 | 8 | 1 | 6 | 4 | 12 | 4 | 10 | 4 | 8 | 4 | 7 | 4 | 6 | 4 | 5 | 4 | 3 | 4 | 2 | 4 | 0 | 1 | 3 | 0 | 17 | 15 | 16 | 10 | 12 | 1 | 0 | 10 | 8 | 0 | 16 | 4 | 4 | 2 | 1 | 3 | 2 | 3 | 17 | 14 | 17 | 0 | 12 | 14 | 10 | 14 | 15
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PIN | AS | 64 | 0 | N/A | 152 | 12 | 9 | 15 | 9 | 14 | 0 | 10 | 9 | 17 | 0 | 6 | 6 | 0 | 0 | 16 | 4 | 4 | 13 | 13 | 2 | 1 | 0 | 0 | 0 | 12
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PIN | RESET | 64 | 0 | N/A | 263 | 120 | 9 | 15 | 9 | 14 | 3 | 8 | 3 | 10 | 0 | 10 | 12 | 11 | 12 | 10 | 6 | 16 | 6 | 15 | 6 | 14 | 6 | 13 | 6 | 12 | 6 | 10 | 3 | 9 | 7 | 15 | 7 | 14 | 7 | 13 | 7 | 12 | 7 | 11 | 7 | 10 | 7 | 8 | 7 | 6 | 7 | 5 | 1 | 17 | 1 | 15 | 1 | 12 | 1 | 10 | 1 | 8 | 1 | 6 | 4 | 12 | 4 | 10 | 4 | 8 | 4 | 7 | 4 | 6 | 4 | 5 | 4 | 3 | 4 | 2 | 4 | 0 | 1 | 3 | 0 | 17 | 11 | 16 | 9 | 16 | 11 | 9 | 9 | 1 | 9 | 9 | 9 | 13 | 11 | 11 | 9 | 2 | 7 | 1 | 11 | 7 | 7 | 2 | 11 | 4 | 9 | 5 | 9 | 4 | 9 | 7 | 9 | 11 | 9 | 10 | 0 | 15 | 13 | 16 | 13 | 7 | 13 | 8 | 11 | 13 | 11 | 14 | 13 | 9 | 11 | 15 | 0 | 8 | 9 | 17 | 9 | 12 | 13 | 15 | 13 | 12 | 13 | 11 | 0 | 6 | 8 | 9 | 11 | 5 | 11 | 3 | 11 | 12 | 6 | 9 | 7 | 3 | 6 | 0 | 3 | 0 | 3 | 15 | 3 | 6 | 3 | 3 | 1 | 0 | 0 | 3 | 8 | 7 | 8 | 8 | 12 | 8 | 12 | 6 | 0 | 2 | 11 | 8 | 12 | 5 | 12 | 14 | 12 | 9 | 12 | 4 | 12 | 12 | 4 | 17 | 4 | 15 | 12 | 3 | 11 | 6 | 11 | 17 | 11 | 2 | 8 | 12 | 3 | 5 | 5 | 5 | 5 | 7 | 5 | 2 | 5 | 4 | 3 | 4 | 3 | 11 | 3 | 7 | 1 | 1 | 3 | 12 | 1 | 4 | 1 | 2 | 5 | 9 | 5 | 13 | 7 | 7 | 0 | 1 | 8 | 11
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PIN | UDS | 64 | 0 | N/A | 155 | 31 | 12 | 10 | 1 | 17 | 1 | 15 | 1 | 12 | 1 | 10 | 1 | 8 | 1 | 6 | 4 | 12 | 4 | 10 | 4 | 8 | 4 | 7 | 4 | 6 | 4 | 5 | 4 | 3 | 4 | 2 | 4 | 0 | 1 | 3 | 0 | 17 | 1 | 0 | 12 | 5 | 12 | 14 | 12 | 9 | 12 | 4 | 12 | 12 | 4 | 17 | 4 | 15 | 12 | 3 | 14 | 8 | 5 | 10 | 14 | 10 | 14 | 15
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PIN | LDS | 64 | 0 | N/A | 157 | 4 | 0 | 17 | 14 | 7 | 5 | 10 | 5 | 6
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PIN | DS1 | 64 | 0 | N/A | 148 | 2 | 14 | 8 | 5 | 8
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PIN | DS0 | 64 | 0 | N/A | 170 | 2 | 14 | 7 | 5 | 8
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PIN | A<4> | 64 | 0 | N/A | 97 | 11 | 3 | 8 | 3 | 10 | 13 | 16 | 13 | 3 | 3 | 14 | 3 | 2 | 3 | 12 | 3 | 17 | 3 | 13 | 3 | 11 | 3 | 16
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PIN | A<5> | 64 | 0 | N/A | 91 | 12 | 3 | 8 | 3 | 10 | 13 | 15 | 3 | 0 | 3 | 15 | 3 | 2 | 3 | 12 | 3 | 17 | 3 | 14 | 3 | 1 | 3 | 11 | 3 | 13
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PIN | A<3> | 64 | 0 | N/A | 99 | 10 | 3 | 8 | 3 | 10 | 13 | 7 | 3 | 13 | 3 | 14 | 3 | 12 | 3 | 1 | 3 | 11 | 3 | 16 | 3 | 17
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PIN | A<1> | 64 | 0 | N/A | 107 | 8 | 3 | 8 | 3 | 10 | 3 | 13 | 3 | 2 | 3 | 12 | 3 | 17 | 3 | 1 | 3 | 11
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PIN | A<6> | 64 | 0 | N/A | 98 | 12 | 3 | 8 | 3 | 10 | 13 | 12 | 3 | 0 | 3 | 15 | 3 | 2 | 3 | 12 | 3 | 17 | 3 | 14 | 3 | 1 | 3 | 11 | 3 | 13
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PIN | A<2> | 64 | 0 | N/A | 101 | 9 | 3 | 10 | 13 | 8 | 13 | 3 | 3 | 11 | 3 | 2 | 3 | 12 | 3 | 17 | 3 | 13 | 3 | 16
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PIN | LAN_INT | 64 | 0 | N/A | 201 | 2 | 11 | 16 | 11 | 2
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PIN | A<7> | 64 | 0 | N/A | 100 | 1 | 13 | 11
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PIN | BERR | 64 | 0 | N/A | 176 | 1 | 11 | 0
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PIN | C1 | 64 | 0 | N/A | 188 | 1 | 5 | 11
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PIN | C3 | 64 | 0 | N/A | 187 | 1 | 5 | 11
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PIN | A_LAN<0> | 536871040 | 0 | N/A | 7
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PIN | A_LAN<10> | 536871040 | 0 | N/A | 255
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PIN | A_LAN<11> | 536871040 | 0 | N/A | 256
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PIN | A_LAN<12> | 536871040 | 0 | N/A | 253
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PIN | A_LAN<13> | 536871040 | 0 | N/A | 254
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PIN | A_LAN<1> | 536871040 | 0 | N/A | 6
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PIN | A_LAN<2> | 536871040 | 0 | N/A | 12
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PIN | A_LAN<3> | 536871040 | 0 | N/A | 8
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PIN | A_LAN<4> | 536871040 | 0 | N/A | 20
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PIN | A_LAN<5> | 536871040 | 0 | N/A | 13
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PIN | A_LAN<6> | 536871040 | 0 | N/A | 22
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PIN | A_LAN<7> | 536871040 | 0 | N/A | 21
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PIN | A_LAN<8> | 536871040 | 0 | N/A | 258
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PIN | A_LAN<9> | 536871040 | 0 | N/A | 262
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PIN | IDE_R | 536871040 | 0 | N/A | 46
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PIN | LAN_CS | 536871040 | 0 | N/A | 240
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PIN | LAN_WRH | 536871040 | 0 | N/A | 237
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PIN | LAN_WRL | 536871040 | 0 | N/A | 145
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PIN | ROM_OE | 536871040 | 0 | N/A | 65
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PIN | LAN_RD | 536871040 | 0 | N/A | 242
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PIN | SLAVE | 536871040 | 0 | N/A | 193
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PIN | OVR | 536871040 | 0 | N/A | 185
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PIN | INT_OUT | 536871040 | 0 | N/A | 60
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PIN | DTACK | 536871040 | 0 | N/A | 160
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PIN | CFOUT | 536871040 | 0 | N/A | 191
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PIN | IDE_A<0> | 536871040 | 0 | N/A | 43
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PIN | IDE_A<1> | 536871040 | 0 | N/A | 45
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PIN | IDE_A<2> | 536871040 | 0 | N/A | 44
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PIN | IDE_CS<0> | 536871040 | 0 | N/A | 39
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PIN | IDE_CS<1> | 536871040 | 0 | N/A | 41
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PIN | IDE_W | 536871040 | 0 | N/A | 47
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PIN | OWN | 536871040 | 0 | N/A | 195
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PIN | MTACK | 536871040 | 0 | N/A | 174
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PIN | LAN_CFG<4> | 536871040 | 0 | N/A | 199
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PIN | LAN_CFG<3> | 536871040 | 0 | N/A | 24
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PIN | LAN_CFG<2> | 536871040 | 0 | N/A | 251
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PIN | LAN_CFG<1> | 536871040 | 0 | N/A | 23
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PIN | CP_WE | 536871040 | 0 | N/A | 131
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PIN | CP_RD | 536871040 | 0 | N/A | 132
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PIN | CP_CS | 536871040 | 0 | N/A | 63
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PIN | ROM_B<1> | 536871040 | 0 | N/A | 129
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PIN | ROM_B<0> | 536871040 | 0 | N/A | 127
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PIN | A<8> | 536870976 | 0 | N/A | 106 | 3 | 13 | 9 | 10 | 17 | 10 | 14
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PIN | A<18> | 536870976 | 0 | N/A | 171 | 8 | 9 | 17 | 9 | 12 | 10 | 15 | 12 | 16 | 13 | 0 | 7 | 16 | 6 | 17 | 13 | 17
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PIN | A<19> | 536870976 | 0 | N/A | 169 | 8 | 9 | 17 | 9 | 12 | 14 | 0 | 14 | 2 | 6 | 17 | 7 | 16 | 6 | 1 | 13 | 17
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PIN | A<20> | 536870976 | 0 | N/A | 167 | 8 | 9 | 17 | 9 | 12 | 14 | 1 | 14 | 3 | 7 | 0 | 7 | 16 | 6 | 1 | 13 | 17
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PIN | A<21> | 536870976 | 0 | N/A | 163 | 7 | 9 | 17 | 9 | 12 | 6 | 1 | 8 | 3 | 8 | 17 | 7 | 0 | 13 | 1
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PIN | A<22> | 536870976 | 0 | N/A | 162 | 7 | 9 | 17 | 9 | 12 | 8 | 1 | 8 | 4 | 8 | 6 | 7 | 15 | 6 | 2
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PIN | A<23> | 536870976 | 0 | N/A | 161 | 10 | 0 | 17 | 9 | 17 | 9 | 12 | 8 | 2 | 8 | 5 | 7 | 0 | 7 | 15 | 6 | 2 | 6 | 16 | 13 | 1
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PIN | A<9> | 536870976 | 0 | N/A | 108 | 4 | 12 | 17 | 12 | 15 | 12 | 8 | 0 | 11
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PIN | A<10> | 536870976 | 0 | N/A | 112 | 4 | 10 | 15 | 12 | 16 | 12 | 6 | 0 | 14
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PIN | A<11> | 536870976 | 0 | N/A | 114 | 4 | 14 | 0 | 14 | 2 | 0 | 2 | 0 | 13
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PIN | A<12> | 536870976 | 0 | N/A | 115 | 4 | 14 | 1 | 14 | 3 | 0 | 3 | 0 | 7
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PIN | A<13> | 536870976 | 0 | N/A | 123 | 5 | 0 | 15 | 8 | 0 | 8 | 3 | 8 | 7 | 0 | 9
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PIN | A<14> | 536870976 | 0 | N/A | 125 | 4 | 0 | 15 | 8 | 1 | 8 | 4 | 8 | 8
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PIN | A<15> | 536870976 | 0 | N/A | 139 | 3 | 8 | 9 | 8 | 2 | 8 | 6
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PIN | A<16> | 536870976 | 0 | N/A | 175 | 7 | 9 | 17 | 9 | 12 | 10 | 17 | 10 | 14 | 6 | 0 | 7 | 17 | 13 | 0
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PIN | A<17> | 536870976 | 0 | N/A | 172 | 7 | 9 | 17 | 9 | 12 | 12 | 17 | 12 | 15 | 13 | 0 | 7 | 17 | 6 | 17
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PIN | DQ<10> | 536870976 | 0 | N/A | 234 | 4 | 15 | 5 | 8 | 16 | 15 | 17 | 15 | 4
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PIN | DQ<11> | 536870976 | 0 | N/A | 207 | 4 | 15 | 2 | 10 | 2 | 15 | 12 | 15 | 3
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PIN | DQ<1> | 536870976 | 0 | N/A | 216 | 4 | 8 | 13 | 15 | 7 | 15 | 13 | 15 | 6
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PIN | DQ<4> | 536870976 | 0 | N/A | 225 | 4 | 15 | 1 | 10 | 4 | 15 | 11 | 15 | 0
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PIN | DQ<8> | 536870976 | 0 | N/A | 231 | 4 | 8 | 10 | 15 | 10 | 15 | 14 | 15 | 8
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PIN | DQ<9> | 536870976 | 0 | N/A | 209 | 4 | 8 | 13 | 15 | 7 | 15 | 13 | 15 | 6
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PIN | D<0> | 536870976 | 0 | N/A | 4 | 3 | 1 | 17 | 10 | 17 | 10 | 13
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PIN | D<10> | 536870976 | 0 | N/A | 74 | 7 | 6 | 14 | 7 | 12 | 1 | 15 | 9 | 12 | 10 | 15 | 5 | 17 | 12 | 17
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PIN | D<11> | 536870976 | 0 | N/A | 77 | 7 | 6 | 13 | 7 | 11 | 1 | 12 | 9 | 12 | 7 | 0 | 14 | 3 | 14 | 17
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PIN | D<12> | 536870976 | 0 | N/A | 78 | 8 | 6 | 12 | 7 | 10 | 1 | 10 | 0 | 15 | 0 | 8 | 9 | 12 | 14 | 1 | 14 | 4
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PIN | D<13> | 536870976 | 0 | N/A | 80 | 7 | 6 | 10 | 7 | 8 | 1 | 8 | 9 | 12 | 8 | 4 | 8 | 7 | 8 | 17
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PIN | D<14> | 536870976 | 0 | N/A | 81 | 7 | 3 | 9 | 7 | 6 | 1 | 6 | 9 | 12 | 8 | 0 | 8 | 5 | 13 | 16
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PIN | D<15> | 536870976 | 0 | N/A | 89 | 8 | 7 | 14 | 7 | 5 | 4 | 12 | 0 | 17 | 9 | 12 | 8 | 2 | 5 | 14 | 8 | 6
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PIN | D<1> | 536870976 | 0 | N/A | 30 | 3 | 4 | 10 | 12 | 0 | 12 | 14
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PIN | D<2> | 536870976 | 0 | N/A | 71 | 3 | 4 | 8 | 12 | 16 | 10 | 16
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PIN | D<3> | 536870976 | 0 | N/A | 28 | 3 | 4 | 7 | 14 | 2 | 14 | 17
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PIN | D<4> | 536870976 | 0 | N/A | 38 | 3 | 4 | 6 | 14 | 0 | 14 | 4
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PIN | D<5> | 536870976 | 0 | N/A | 37 | 3 | 4 | 5 | 8 | 3 | 8 | 17
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PIN | D<6> | 536870976 | 0 | N/A | 26 | 3 | 4 | 3 | 8 | 0 | 8 | 5
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PIN | D<7> | 536870976 | 0 | N/A | 29 | 3 | 4 | 2 | 8 | 1 | 8 | 6
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PIN | D<8> | 536870976 | 0 | N/A | 32 | 7 | 6 | 16 | 7 | 14 | 4 | 0 | 9 | 12 | 10 | 0 | 10 | 14 | 5 | 15
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PIN | D<9> | 536870976 | 0 | N/A | 73 | 7 | 6 | 15 | 7 | 13 | 1 | 3 | 9 | 12 | 12 | 0 | 12 | 15 | 5 | 16
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PIN | DQ<0> | 536870976 | 0 | N/A | 217 | 4 | 8 | 10 | 15 | 10 | 15 | 14 | 15 | 8
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PIN | DQ<12> | 536870976 | 0 | N/A | 235 | 4 | 15 | 1 | 10 | 4 | 15 | 11 | 15 | 0
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PIN | DQ<13> | 536870976 | 0 | N/A | 204 | 4 | 14 | 16 | 10 | 9 | 10 | 5 | 10 | 1
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PIN | DQ<14> | 536870976 | 0 | N/A | 236 | 4 | 14 | 14 | 10 | 10 | 10 | 3 | 10 | 0
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PIN | DQ<15> | 536870976 | 0 | N/A | 202 | 4 | 14 | 13 | 12 | 7 | 14 | 5 | 14 | 6
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PIN | DQ<2> | 536870976 | 0 | N/A | 220 | 4 | 15 | 5 | 8 | 16 | 15 | 17 | 15 | 4
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PIN | DQ<3> | 536870976 | 0 | N/A | 219 | 4 | 15 | 2 | 10 | 2 | 15 | 12 | 15 | 3
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PIN | DQ<5> | 536870976 | 0 | N/A | 221 | 4 | 14 | 16 | 10 | 9 | 10 | 5 | 10 | 1
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PIN | DQ<6> | 536870976 | 0 | N/A | 227 | 4 | 14 | 14 | 10 | 10 | 10 | 3 | 10 | 0
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PIN | DQ<7> | 536870976 | 0 | N/A | 226 | 4 | 14 | 13 | 12 | 7 | 14 | 5 | 14 | 6
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