305 lines
14 KiB
Plaintext
305 lines
14 KiB
Plaintext
Release 14.6 - xst P.68d (nt64)
|
|
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
|
|
--> Parameter TMPDIR set to xst/projnav.tmp
|
|
|
|
|
|
Total REAL time to Xst completion: 0.00 secs
|
|
Total CPU time to Xst completion: 0.11 secs
|
|
|
|
--> Parameter xsthdpdir set to xst
|
|
|
|
|
|
Total REAL time to Xst completion: 0.00 secs
|
|
Total CPU time to Xst completion: 0.11 secs
|
|
|
|
--> Reading design: LAN_IDE_CP.prj
|
|
|
|
TABLE OF CONTENTS
|
|
1) Synthesis Options Summary
|
|
2) HDL Compilation
|
|
3) Design Hierarchy Analysis
|
|
4) HDL Analysis
|
|
5) HDL Synthesis
|
|
5.1) HDL Synthesis Report
|
|
6) Advanced HDL Synthesis
|
|
6.1) Advanced HDL Synthesis Report
|
|
7) Low Level Synthesis
|
|
8) Partition Report
|
|
9) Final Report
|
|
|
|
=========================================================================
|
|
* Synthesis Options Summary *
|
|
=========================================================================
|
|
---- Source Parameters
|
|
Input File Name : "LAN_IDE_CP.prj"
|
|
Input Format : mixed
|
|
Ignore Synthesis Constraint File : NO
|
|
|
|
---- Target Parameters
|
|
Output File Name : "LAN_IDE_CP"
|
|
Output Format : NGC
|
|
Target Device : XC9500XL CPLDs
|
|
|
|
---- Source Options
|
|
Top Module Name : LAN_IDE_CP
|
|
Automatic FSM Extraction : YES
|
|
FSM Encoding Algorithm : Auto
|
|
Safe Implementation : Yes
|
|
Mux Extraction : No
|
|
Resource Sharing : YES
|
|
|
|
---- Target Options
|
|
Add IO Buffers : YES
|
|
MACRO Preserve : YES
|
|
XOR Preserve : YES
|
|
Equivalent register Removal : YES
|
|
|
|
---- General Options
|
|
Optimization Goal : Area
|
|
Optimization Effort : 1
|
|
Keep Hierarchy : Yes
|
|
Netlist Hierarchy : Rebuilt
|
|
RTL Output : Yes
|
|
Hierarchy Separator : /
|
|
Bus Delimiter : <>
|
|
Case Specifier : Maintain
|
|
Verilog 2001 : YES
|
|
|
|
---- Other Options
|
|
Clock Enable : YES
|
|
wysiwyg : NO
|
|
|
|
=========================================================================
|
|
|
|
|
|
=========================================================================
|
|
* HDL Compilation *
|
|
=========================================================================
|
|
Compiling vhdl file "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.vhd" in Library work.
|
|
Entity <lan_ide_cp> compiled.
|
|
Entity <lan_ide_cp> (Architecture <behavioral>) compiled.
|
|
|
|
=========================================================================
|
|
* Design Hierarchy Analysis *
|
|
=========================================================================
|
|
Analyzing hierarchy for entity <LAN_IDE_CP> in library <work> (architecture <behavioral>).
|
|
|
|
|
|
=========================================================================
|
|
* HDL Analysis *
|
|
=========================================================================
|
|
Analyzing Entity <LAN_IDE_CP> in library <work> (Architecture <behavioral>).
|
|
Entity <LAN_IDE_CP> analyzed. Unit <LAN_IDE_CP> generated.
|
|
|
|
|
|
=========================================================================
|
|
* HDL Synthesis *
|
|
=========================================================================
|
|
|
|
Performing bidirectional port resolution...
|
|
INFO:Xst:2561 - Always blocking tristate driving signal <A> in unit <LAN_IDE_CP> is removed.
|
|
|
|
Synthesizing Unit <LAN_IDE_CP>.
|
|
Related source file is "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.vhd".
|
|
WARNING:Xst:647 - Input <DS0> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <DS1> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <FCS> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <Z3> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <MTCR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:1780 - Signal <LAN_INT_D0> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
|
|
WARNING:Xst:1780 - Signal <DTACK_S> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
|
|
WARNING:Xst - You have specified state <nop> as a recovery-only state for the safe implementation of FSM <LAN_RST_SM>. Due to a limitation in this version of the software, the logic required to implement this recovery-only state might not be properly generated. Please refer to the Xilinx Answers Database for more details.
|
|
Found finite state machine <FSM_0> for signal <LAN_RST_SM>.
|
|
-----------------------------------------------------------------------
|
|
| States | 8 |
|
|
| Transitions | 8 |
|
|
| Inputs | 0 |
|
|
| Outputs | 8 |
|
|
| Clock | CLK_EXT (rising_edge) |
|
|
| Reset | RESET (positive) |
|
|
| Reset type | synchronous |
|
|
| Reset State | nop |
|
|
| Power Up State | nop |
|
|
| Recovery State | nop |
|
|
| Encoding | automatic |
|
|
| Implementation | automatic |
|
|
-----------------------------------------------------------------------
|
|
Found 16-bit tristate buffer for signal <D>.
|
|
Found 16-bit tristate buffer for signal <DQ>.
|
|
Found 1-bit tristate buffer for signal <OWN>.
|
|
Found 1-bit tristate buffer for signal <CFOUT>.
|
|
Found 1-bit tristate buffer for signal <OVR>.
|
|
Found 1-bit tristate buffer for signal <MTACK>.
|
|
Found 1-bit tristate buffer for signal <DTACK>.
|
|
Found 1-bit tristate buffer for signal <INT_OUT>.
|
|
Found 4-bit tristate buffer for signal <LAN_CFG>.
|
|
Found 1-bit xor2 for signal <AMIGA_CLK$xor0000> created at line 139.
|
|
Found 2-bit register for signal <AUTO_CONFIG_DONE>.
|
|
Found 2-bit register for signal <AUTO_CONFIG_DONE_CYCLE>.
|
|
Found 2-bit adder for signal <AUTO_CONFIG_DONE_CYCLE$share0000> created at line 319.
|
|
Found 1-bit register for signal <autoconfig>.
|
|
Found 1-bit register for signal <cp>.
|
|
Found 8-bit comparator equal for signal <cp$cmp_eq0001> created at line 203.
|
|
Found 8-bit comparator equal for signal <cp$cmp_eq0002> created at line 208.
|
|
Found 2-bit comparator less for signal <cp$cmp_lt0000> created at line 199.
|
|
Found 8-bit register for signal <CP_BASEADR>.
|
|
Found 1-bit register for signal <CP_RD_S>.
|
|
Found 1-bit register for signal <CP_WE_S>.
|
|
Found 4-bit register for signal <Dout1>.
|
|
Found 3-bit comparator less for signal <Dout1$cmp_lt0000> created at line 321.
|
|
Found 1-bit register for signal <DS_D>.
|
|
Found 1-bit register for signal <ide>.
|
|
Found 8-bit comparator equal for signal <ide$cmp_eq0000> created at line 213.
|
|
Found 8-bit register for signal <IDE_BASEADR>.
|
|
Found 1-bit register for signal <IDE_ENABLE>.
|
|
Found 1-bit register for signal <IDE_R_S>.
|
|
Found 1-bit register for signal <IDE_W_S>.
|
|
Found 1-bit register for signal <lan_adr>.
|
|
Found 8-bit register for signal <LAN_BASEADR>.
|
|
Found 1-bit register for signal <LAN_CS_RST>.
|
|
Found 1-bit register for signal <LAN_INT_ENABLE>.
|
|
Found 1-bit register for signal <LAN_RD_S>.
|
|
Found 1-bit register for signal <LAN_WR_RST>.
|
|
Found 1-bit register for signal <LAN_WRH_S>.
|
|
Found 1-bit register for signal <LAN_WRL_S>.
|
|
Found 1-bit register for signal <ROM_OE_S>.
|
|
Found 3-bit register for signal <SHUT_UP>.
|
|
Summary:
|
|
inferred 1 Finite State Machine(s).
|
|
inferred 6 D-type flip-flop(s).
|
|
inferred 1 Adder/Subtractor(s).
|
|
inferred 5 Comparator(s).
|
|
inferred 1 Xor(s).
|
|
inferred 42 Tristate(s).
|
|
Unit <LAN_IDE_CP> synthesized.
|
|
|
|
|
|
=========================================================================
|
|
HDL Synthesis Report
|
|
|
|
Macro Statistics
|
|
# Adders/Subtractors : 1
|
|
2-bit adder : 1
|
|
# Registers : 26
|
|
1-bit register : 20
|
|
2-bit register : 2
|
|
4-bit register : 1
|
|
8-bit register : 3
|
|
# Comparators : 5
|
|
2-bit comparator less : 1
|
|
3-bit comparator less : 1
|
|
8-bit comparator equal : 3
|
|
# Tristates : 12
|
|
1-bit tristate buffer : 10
|
|
16-bit tristate buffer : 2
|
|
# Xors : 1
|
|
1-bit xor2 : 1
|
|
|
|
=========================================================================
|
|
|
|
=========================================================================
|
|
* Advanced HDL Synthesis *
|
|
=========================================================================
|
|
|
|
Analyzing FSM <FSM_0> for best encoding.
|
|
Optimizing FSM <LAN_RST_SM/FSM> on signal <LAN_RST_SM[1:3]> with gray encoding.
|
|
------------------------
|
|
State | Encoding
|
|
------------------------
|
|
nop | 000
|
|
wait0 | 001
|
|
clr | 011
|
|
clr_commit | 010
|
|
wait1 | 110
|
|
set | 111
|
|
set_commit | 101
|
|
done | 100
|
|
------------------------
|
|
|
|
=========================================================================
|
|
Advanced HDL Synthesis Report
|
|
|
|
Macro Statistics
|
|
# FSMs : 1
|
|
# Adders/Subtractors : 1
|
|
2-bit adder : 1
|
|
# Registers : 6
|
|
Flip-Flops : 6
|
|
# Comparators : 3
|
|
8-bit comparator equal : 3
|
|
|
|
=========================================================================
|
|
|
|
=========================================================================
|
|
* Low Level Synthesis *
|
|
=========================================================================
|
|
|
|
Optimizing unit <LAN_IDE_CP> ...
|
|
implementation constraint: INIT=r : LAN_RST_SM_FSM_FFd1
|
|
implementation constraint: INIT=r : LAN_RST_SM_FSM_FFd2
|
|
implementation constraint: INIT=r : LAN_RST_SM_FSM_FFd3
|
|
|
|
=========================================================================
|
|
* Partition Report *
|
|
=========================================================================
|
|
|
|
Partition Implementation Status
|
|
-------------------------------
|
|
|
|
No Partitions were found in this design.
|
|
|
|
-------------------------------
|
|
|
|
=========================================================================
|
|
* Final Report *
|
|
=========================================================================
|
|
Final Results
|
|
RTL Top Level Output File Name : LAN_IDE_CP.ngr
|
|
Top Level Output File Name : LAN_IDE_CP
|
|
Output Format : NGC
|
|
Optimization Goal : Area
|
|
Keep Hierarchy : Yes
|
|
Target Technology : XC9500XL CPLDs
|
|
Macro Preserve : YES
|
|
XOR Preserve : YES
|
|
Clock Enable : YES
|
|
wysiwyg : NO
|
|
|
|
Design Statistics
|
|
# IOs : 116
|
|
|
|
Cell Usage :
|
|
# BELS : 552
|
|
# AND2 : 156
|
|
# AND3 : 13
|
|
# AND4 : 1
|
|
# GND : 1
|
|
# INV : 203
|
|
# OR2 : 130
|
|
# OR3 : 20
|
|
# OR4 : 2
|
|
# XOR2 : 26
|
|
# FlipFlops/Latches : 55
|
|
# FD : 14
|
|
# FDC : 4
|
|
# FDCE : 37
|
|
# IO Buffers : 111
|
|
# IBUF : 37
|
|
# IOBUFE : 32
|
|
# OBUF : 32
|
|
# OBUFE : 10
|
|
=========================================================================
|
|
|
|
|
|
Total REAL time to Xst completion: 8.00 secs
|
|
Total CPU time to Xst completion: 7.97 secs
|
|
|
|
-->
|
|
|
|
Total memory usage is 306216 kilobytes
|
|
|
|
Number of errors : 0 ( 0 filtered)
|
|
Number of warnings : 8 ( 0 filtered)
|
|
Number of infos : 1 ( 0 filtered)
|
|
|