126 lines
3.3 KiB
OpenEdge ABL
126 lines
3.3 KiB
OpenEdge ABL
; ------------------------------------------------------------------------------
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; | Lowlevel Access to memory mapped ENC624J600 in PSP mode |
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; | Henryk Richter <henryk.richter@gmx.net> |
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; ------------------------------------------------------------------------------
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; macro section
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;------------------ options, some depend on hardware (CPLD) configuration -------------------------
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_OPT_BUFFER_SWAP EQU 0 ;perform byte swap on buffer ops (1) or assume native endian (0)
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_OPT_REG_SWAP EQU 0 ;perform byte swap on register ops (1) or assume native endian (0)
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_OPT_ADR_QUIRK EQU 0 ;address lines 12/13 are swapped (1) or linear addressing (0)
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_OPT_FLOWCONTROL EQU 0 ;perform flow control on RX (1) or not (0)
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_OPT_RECV EQU 1 ;faster recv (1) or generic (0)
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_OPT_CHECKLINK_TX EQU 0 ;check for link changes in TX (1) or expect from outside (0) -> see server.c
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;\1 register offset (without CLEAR offset)
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;\2 address register of board I/O base
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;\3 register with clear mask
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ifne _OPT_REG_SWAP
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CLRREG macro
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rol.w #8,\3
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move.w \3,\1+CLR_OFFSET(\2)
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rol.w #8,\3
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endm
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;\1 register offset (without SET offset)
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;\2 address register of board I/O base
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;\3 register with set mask
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SETREG macro
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rol.w #8,\3
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move.w \3,\1+SET_OFFSET(\2)
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rol.w #8,\3
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endm
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;\1 register offset (e.g. ESTAT)
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;\2 address register of board I/O base (e.g. a0)
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;\3 destination register to be written (e.g. d0)
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;
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;important: when changing this, make sure the flags
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;are set according to the return value
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READREG macro
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rol.w #8,\3
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move.w \1(\2),\3
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rol.w #8,\3
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endm
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;\1 register offset (e.g. ESTAT)
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;\2 address register of board I/O base (e.g. a0)
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;\3 soure register copied to HW register (e.g. d0)
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WRITEREG macro
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rol.w #8,\3
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move.w \3,\1(\2)
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rol.w #8,\3
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endm
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else
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CLRREG macro
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move.w \3,\1+CLR_OFFSET(\2)
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endm
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;\1 register offset (without SET offset)
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;\2 address register of board I/O base
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;\3 register with set mask
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SETREG macro
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move.w \3,\1+SET_OFFSET(\2)
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endm
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;\1 register offset (e.g. ESTAT)
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;\2 address register of board I/O base (e.g. a0)
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;\3 destination register to be written (e.g. d0)
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;
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;important: when changing this, make sure the flags
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;are set according to the return value
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READREG macro
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move.w \1(\2),\3
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endm
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;\1 register offset (e.g. ESTAT)
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;\2 address register of board I/O base (e.g. a0)
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;\3 soure register copied to HW register (e.g. d0)
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WRITEREG macro
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move.w \3,\1(\2)
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endm
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endc
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;read with address shuffling or direct from SRAM (affects $2000-$5000)
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ifne _OPT_ADR_QUIRK
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;\1 = address register
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;\2 = data register, offset
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;\3 = destination
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READSRAM macro
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eor.w #$6000,\2
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move.w (\1,\2.w),\3
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eor.w #$6000,\2
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endm
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else
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READSRAM macro
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move.w (\1,\2),\3
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endm
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endc
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;read with address shuffling or direct from SRAM (affects $2000-$5000)
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ifne _OPT_ADR_QUIRK
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;\1 = address register
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;\2 = data register, offset
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;\3 = destination
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READSRAM_LONG macro
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eor.w #$6000,\2
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move.l (\1,\2.w),\3
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eor.w #$6000,\2
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endm
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else
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READSRAM_LONG macro
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move.l (\1,\2),\3
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endm
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endc
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; wrap position index (in bytes) \1 (data register .w)
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;
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; if position >RXSTOP_INIT-1
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; position = (position-RXSTOP_INIT+RXSTART_INIT)
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; endif
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WRAPINDEX macro
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cmp.w #RXSTOP_INIT&$fffe,\1 ;wrap Dn if beyond buffer
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ble.s .nowrap\0\@
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add.w #RXSTART_INIT-RXSTOP_INIT-1,\1
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.nowrap\0\@
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endm |