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Zorro-LAN-IDE/Logic/LAN_IDE_V2/LAN_IDE_CP.rpt
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cpldfit: version P.20131013 Xilinx Inc.
Fitter Report
Design Name: LAN_IDE_CP Date: 3- 8-2022, 1:48PM
Device Used: XC95288XL-10-TQ144
Fitting Status: Successful
************************* Mapped Resource Summary **************************
Macrocells Product Terms Function Block Registers Pins
Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot
181/288 ( 63%) 543 /1440 ( 38%) 430/864 ( 50%) 112/288 ( 39%) 106/117 ( 91%)
** Function Block Resources **
Function Mcells FB Inps Pterms IO
Block Used/Tot Used/Tot Used/Tot Used/Tot
FB1 16/18 25/54 33/90 8/ 8*
FB2 8/18 33/54 30/90 8/10
FB3 11/18 26/54 39/90 4/ 5
FB4 7/18 25/54 20/90 6/ 6*
FB5 7/18 42/54 42/90 7/ 8
FB6 14/18 25/54 31/90 8/ 8*
FB7 7/18 25/54 23/90 4/ 4*
FB8 12/18 25/54 31/90 5/ 5*
FB9 8/18 26/54 31/90 9/ 9*
FB10 17/18 26/54 40/90 10/10*
FB11 7/18 26/54 29/90 7/ 7*
FB12 18/18* 25/54 39/90 5/ 6
FB13 13/18 26/54 47/90 4/ 6
FB14 13/18 26/54 58/90 7/ 8
FB15 10/18 25/54 27/90 8/ 9
FB16 13/18 24/54 23/90 6/ 8
----- ----- ----- -----
181/288 430/864 543/1440 106/117
* - Resource is exhausted
** Global Control Resources **
Signal 'CLK_EXT' mapped onto global clock net GCK1.
Global output enable net(s) unused.
Global set/reset net(s) unused.
** Pin Resources **
Signal Type Required Mapped | Pin Type Used Total
------------------------------------|------------------------------------
Input : 34 34 | I/O : 99 109
Output : 39 39 | GCK/IO : 2 3
Bidirectional : 32 32 | GTS/IO : 4 4
GCK : 1 1 | GSR/IO : 1 1
GTS : 0 0 |
GSR : 0 0 |
---- ----
Total 106 106
** Power Data **
There are 181 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
End of Mapped Resource Summary
************************** Errors and Warnings ***************************
WARNING:Cpld - Unable to retrieve the path to the iSE Project Repository. Will
use the default filename of 'LAN_IDE_CP.ise'.
INFO:Cpld - Inferring BUFG constraint for signal 'CLK_EXT' based upon the LOC
constraint 'P30'. It is recommended that you declare this BUFG explicitedly
in your design. Note that for certain device families the output of a BUFG
constraint can not drive a gated clock, and the BUFG constraint will be
ignored.
WARNING:Cpld:1007 - Removing unused input(s) 'BERR'. The input(s) are unused
after optimization. Please verify functionality via simulation.
WARNING:Cpld:1007 - Removing unused input(s) 'DS0'. The input(s) are unused
after optimization. Please verify functionality via simulation.
WARNING:Cpld:1007 - Removing unused input(s) 'DS1'. The input(s) are unused
after optimization. Please verify functionality via simulation.
WARNING:Cpld:1007 - Removing unused input(s) 'FCS'. The input(s) are unused
after optimization. Please verify functionality via simulation.
WARNING:Cpld:1007 - Removing unused input(s) 'IDE_WAIT'. The input(s) are
unused after optimization. Please verify functionality via simulation.
WARNING:Cpld:1007 - Removing unused input(s) 'MTCR'. The input(s) are unused
after optimization. Please verify functionality via simulation.
WARNING:Cpld:1007 - Removing unused input(s) 'Z3'. The input(s) are unused
after optimization. Please verify functionality via simulation.
INFO:Cpld:994 - Exhaustive fitting is trying pterm limit: 90 and input limit: 54
************************* Summary of Mapped Logic ************************
** 71 Outputs **
Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init
Name Pts Inps No. Type Use Mode Rate State
D<5> 4 8 FB1_5 20 I/O I/O STD FAST SET
D<4> 4 8 FB1_6 21 I/O I/O STD FAST SET
IDE_CS<0> 1 1 FB1_8 22 I/O O STD FAST
IDE_CS<1> 1 1 FB1_10 23 I/O O STD FAST
IDE_A<0> 1 1 FB1_12 24 I/O O STD FAST
IDE_A<2> 1 1 FB1_14 25 I/O O STD FAST
IDE_A<1> 1 1 FB1_15 26 I/O O STD FAST
IDE_R 1 2 FB1_17 27 I/O O STD FAST
A_LAN<4> 3 6 FB2_2 9 I/O O STD FAST SET
A_LAN<7> 3 6 FB2_3 10 I/O O STD FAST SET
A_LAN<6> 4 7 FB2_5 11 I/O O STD FAST SET
D<6> 4 8 FB2_10 14 I/O I/O STD FAST SET
D<3> 4 8 FB2_12 15 I/O I/O STD FAST SET
D<7> 4 8 FB2_14 16 I/O I/O STD FAST SET
D<1> 4 8 FB2_15 17 I/O I/O STD FAST SET
D<8> 4 8 FB2_17 19 I/O I/O STD FAST SET
IDE_W 1 2 FB3_2 28 I/O O STD FAST
INT2_OUT 1 2 FB3_14 32 GCK/I/O O STD FAST
D<0> 4 8 FB4_2 2 GTS/I/O I/O STD FAST SET
A_LAN<1> 3 5 FB4_5 3 GTS/I/O O STD FAST SET
A_LAN<0> 3 5 FB4_6 4 I/O O STD FAST SET
A_LAN<3> 3 6 FB4_8 5 GTS/I/O O STD FAST SET
A_LAN<2> 3 6 FB4_12 6 GTS/I/O O STD FAST SET
A_LAN<5> 3 6 FB4_14 7 I/O O STD FAST SET
CP_CS 19 19 FB5_2 34 I/O O STD FAST SET
ROM_OE 2 3 FB5_5 35 I/O O STD FAST
D<2> 4 8 FB5_10 39 I/O I/O STD FAST SET
D<9> 4 8 FB5_12 40 I/O I/O STD FAST SET
D<10> 4 8 FB5_14 41 I/O I/O STD FAST SET
D<11> 4 8 FB5_15 43 I/O I/O STD FAST SET
D<12> 5 9 FB5_17 44 I/O I/O STD FAST SET
INT6_OUT 1 1 FB6_2 135 I/O O STD FAST
A_LAN<12> 3 6 FB6_3 136 I/O O STD FAST SET
A_LAN<13> 3 6 FB6_5 137 I/O O STD FAST SET
A_LAN<10> 3 6 FB6_6 138 I/O O STD FAST SET
A_LAN<11> 3 6 FB6_8 139 I/O O STD FAST SET
A_LAN<8> 3 6 FB6_10 140 I/O O STD FAST SET
A_LAN<9> 3 6 FB6_14 142 I/O O STD FAST SET
D<13> 5 9 FB7_3 45 I/O I/O STD FAST SET
D<14> 5 9 FB7_5 46 I/O I/O STD FAST SET
Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init
Name Pts Inps No. Type Use Mode Rate State
D<15> 5 9 FB7_12 48 I/O I/O STD FAST SET
DQ<12> 2 3 FB8_2 130 I/O I/O STD FAST
DQ<14> 2 3 FB8_3 131 I/O I/O STD FAST
LAN_WRH 2 3 FB8_5 132 I/O O STD FAST
LAN_CS 2 3 FB8_8 133 I/O O STD FAST
LAN_RD 2 4 FB8_10 134 I/O O STD FAST
DQ<1> 2 3 FB10_2 117 I/O I/O STD FAST
DQ<0> 2 3 FB10_3 118 I/O I/O STD FAST
DQ<3> 2 3 FB10_5 119 I/O I/O STD FAST
DQ<2> 2 3 FB10_6 120 I/O I/O STD FAST
DQ<5> 2 3 FB10_8 121 I/O I/O STD FAST
DQ<4> 2 3 FB10_10 124 I/O I/O STD FAST
DQ<7> 2 3 FB10_11 125 I/O I/O STD FAST
DQ<6> 2 3 FB10_12 126 I/O I/O STD FAST
DQ<8> 2 3 FB10_14 128 I/O I/O STD FAST
DQ<10> 2 3 FB10_17 129 I/O I/O STD FAST
ROM_B<0> 0 0 FB11_12 68 I/O O STD FAST
ROM_B<1> 0 0 FB11_14 69 I/O O STD FAST
CP_WE 1 3 FB11_17 70 I/O O STD FAST
DQ<15> 2 3 FB12_5 112 I/O I/O STD FAST
DQ<13> 2 3 FB12_8 113 I/O I/O STD FAST
DQ<11> 2 3 FB12_10 115 I/O I/O STD FAST
DQ<9> 2 3 FB12_12 116 I/O I/O STD FAST
CP_RD 2 3 FB13_2 71 I/O O STD FAST
LAN_WRL 2 3 FB13_14 76 I/O O STD FAST
OVR 0 0 FB14_3 100 I/O O STD FAST
CFOUT 1 2 FB14_11 105 I/O O STD FAST
SLAVE 2 6 FB14_14 106 I/O O STD FAST
OWN 0 0 FB14_15 107 I/O O STD FAST
DTACK 0 0 FB15_12 85 I/O O STD FAST
MTACK 0 0 FB16_10 96 I/O O STD FAST
** 110 Buried Nodes **
Signal Total Total Loc Pwr Reg Init
Name Pts Inps Mode State
AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2 1 3 FB1_3 STD
$OpTx$FX_DC$34 1 4 FB1_4 STD
AS_D 2 3 FB1_7 STD SET
ROM_OE_S 3 6 FB1_9 STD SET
LAN_RD_S 3 6 FB1_11 STD SET
IDE_W_S 3 5 FB1_13 STD SET
IDE_R_S 3 6 FB1_16 STD SET
IDE_ENABLE 3 5 FB1_18 STD SET
SHUT_UP<1> 3 4 FB3_9 STD SET
LAN_IRQ_D0 3 3 FB3_10 STD SET
IDE_BASEADR<6> 4 5 FB3_11 STD SET
IDE_BASEADR<1> 4 5 FB3_12 STD SET
IDE_BASEADR<0> 4 5 FB3_13 STD SET
CP_BASEADR<6> 4 5 FB3_15 STD SET
CP_BASEADR<1> 4 5 FB3_16 STD SET
CP_BASEADR<0> 4 5 FB3_17 STD SET
LAN_IRQ_OUT 7 13 FB3_18 STD SET
CP_BASEADR_not0001/CP_BASEADR_not0001_D2 1 10 FB4_18 STD
$OpTx$FX_SC$321 1 4 FB6_11 STD
$OpTx$FX_DC$30 1 2 FB6_12 STD
$OpTx$FX_DC$3 1 2 FB6_13 STD
$OpTx$FX_DC$1 1 2 FB6_15 STD
$OpTx$FX_SC$52 2 4 FB6_16 STD
D_IN<0> 3 6 FB6_17 STD SET
DQ_or0001/DQ_or0001_D2 3 6 FB6_18 STD
LAN_RST_SM_FSM_FFd8 1 2 FB7_15 STD SET
D_IN<13> 1 1 FB7_16 STD SET
D_IN<5> 3 7 FB7_17 STD SET
BUF_D_IN<13> 3 5 FB7_18 STD
D_IN<9> 3 6 FB8_12 STD SET
D_IN<8> 3 6 FB8_13 STD SET
D_IN<3> 3 6 FB8_14 STD SET
D_IN<2> 3 6 FB8_15 STD SET
D_IN<1> 3 6 FB8_16 STD SET
D_IN<11> 3 6 FB8_17 STD SET
D_IN<10> 3 6 FB8_18 STD SET
LAN_BASEADR_not0001/LAN_BASEADR_not0001_D2 1 10 FB9_11 STD
$OpTx$FX_DC$31 1 8 FB9_12 STD
LAN_BASEADR<4> 4 5 FB9_13 STD SET
LAN_BASEADR<3> 4 5 FB9_14 STD SET
Signal Total Total Loc Pwr Reg Init
Name Pts Inps Mode State
LAN_BASEADR<2> 4 5 FB9_15 STD SET
LAN_BASEADR<1> 4 5 FB9_16 STD SET
LAN_BASEADR<0> 4 5 FB9_17 STD SET
Dout1<3> 9 11 FB9_18 STD SET
$OpTx$FX_DC$19 1 2 FB10_4 STD
DQ_9_IOBUFE/DQ_9_IOBUFE_TRST 2 4 FB10_7 STD
LAN_WRL_S 3 6 FB10_9 STD SET
LAN_WRH_S 3 6 FB10_13 STD SET
CP_WE_S 3 5 FB10_15 STD SET
CP_RD_S 3 5 FB10_16 STD SET
LAN_INT_ENABLE 5 10 FB10_18 STD SET
autoconfig 3 12 FB11_13 STD SET
SHUT_UP<0> 3 4 FB11_15 STD SET
CP_WE_QUIRK 3 3 FB11_16 STD SET
ide 19 19 FB11_18 STD SET
SET_FREQUENCY 1 3 FB12_1 STD SET
D_IN<15> 1 1 FB12_2 STD SET
D_IN<14> 1 1 FB12_3 STD SET
D_IN<12> 1 1 FB12_4 STD SET
LAN_RST_SM_FSM_FFd7 2 3 FB12_6 STD RESET
LAN_RST_SM_FSM_FFd4 2 3 FB12_7 STD RESET
LAN_CS_RST 2 4 FB12_9 STD SET
CLEAR_REGISTER 2 4 FB12_11 STD SET
D_IN<7> 3 7 FB12_13 STD SET
D_IN<6> 3 7 FB12_14 STD SET
BUF_D_IN<15> 3 5 FB12_15 STD
BUF_D_IN<14> 3 5 FB12_16 STD
BUF_D_IN<12> 3 5 FB12_17 STD
D_IN<4> 4 8 FB12_18 STD SET
SHUT_UP<2> 3 4 FB13_7 STD SET
IDE_BASEADR<7> 4 5 FB13_8 STD SET
IDE_BASEADR<5> 4 5 FB13_9 STD SET
IDE_BASEADR<4> 4 5 FB13_10 STD SET
IDE_BASEADR<3> 4 5 FB13_11 STD SET
IDE_BASEADR<2> 4 5 FB13_12 STD SET
CP_BASEADR<7> 4 5 FB13_13 STD SET
CP_BASEADR<5> 4 5 FB13_15 STD SET
CP_BASEADR<4> 4 5 FB13_16 STD SET
CP_BASEADR<3> 4 5 FB13_17 STD SET
CP_BASEADR<2> 4 5 FB13_18 STD SET
Signal Total Total Loc Pwr Reg Init
Name Pts Inps Mode State
Dout1<0> 11 12 FB14_1 STD SET
Dout1<2> 11 12 FB14_4 STD SET
D_OUT_or0002/D_OUT_or0002_D2 2 5 FB14_5 STD
AUTO_CONFIG_DONE_CYCLE<0> 5 14 FB14_6 STD SET
AUTO_CONFIG_DONE_CYCLE<1> 5 14 FB14_7 STD SET
AUTO_CONFIG_DONE<0> 4 4 FB14_8 STD SET
AUTO_CONFIG_DONE<1> 4 4 FB14_9 STD SET
IDE_BASEADR_not0001/IDE_BASEADR_not0001_D2 1 3 FB14_10 STD
Dout1<1> 12 12 FB14_16 STD SET
LAN_WR_RST 2 4 FB15_9 STD SET
LAN_RST_SM_FSM_FFd5 2 3 FB15_10 STD RESET
LAN_RST_SM_FSM_FFd2 2 3 FB15_11 STD RESET
LAN_RST_SM_FSM_FFd1 2 4 FB15_13 STD RESET
lan_adr 3 11 FB15_14 STD SET
lan_adr_sw 4 13 FB15_15 STD SET
LAN_BASEADR<7> 4 5 FB15_16 STD SET
LAN_BASEADR<6> 4 5 FB15_17 STD SET
LAN_BASEADR<5> 4 5 FB15_18 STD SET
D_OUT_and0001/D_OUT_and0001_D2 1 2 FB16_6 STD
lan_adr_sw/lan_adr_sw_CLKF 2 2 FB16_7 STD
LAN_RST_SM_FSM_FFd6 2 3 FB16_8 STD RESET
LAN_RST_SM_FSM_FFd3 2 3 FB16_9 STD RESET
$OpTx$FX_DC$45 2 2 FB16_11 STD
$OpTx$FX_DC$44 2 2 FB16_12 STD
$OpTx$FX_DC$43 2 2 FB16_13 STD
$OpTx$FX_DC$42 2 2 FB16_14 STD
$OpTx$FX_DC$41 2 2 FB16_15 STD
$OpTx$FX_DC$40 2 2 FB16_16 STD
$OpTx$FX_DC$39 2 2 FB16_17 STD
$OpTx$FX_DC$38 2 2 FB16_18 STD
** 35 Inputs **
Signal Loc Pin Pin Pin
Name No. Type Use
CLK_EXT FB3_10 30 GCK/I/O GCK
CP_IRQ FB3_12 31 I/O I
RESET FB6_15 143 GSR/I/O I
A<5> FB7_15 49 I/O I
A<4> FB9_2 50 I/O I
A<6> FB9_3 51 I/O I
A<3> FB9_5 52 I/O I
A<7> FB9_6 53 I/O I
A<2> FB9_8 54 I/O I
A<8> FB9_11 56 I/O I
A<1> FB9_12 57 I/O I
A<9> FB9_14 58 I/O I
A<10> FB9_17 59 I/O I
A<11> FB11_3 60 I/O I
A<12> FB11_5 61 I/O I
A<13> FB11_10 64 I/O I
A<14> FB11_11 66 I/O I
LAN_INT FB12_3 111 I/O I
A<15> FB13_8 74 I/O I
IDE_OFF FB13_11 75 I/O I
C3 FB14_6 102 I/O I
C1 FB14_8 103 I/O I
CFIN FB14_10 104 I/O I
AS FB15_3 80 I/O I
UDS FB15_8 81 I/O I
LDS FB15_10 82 I/O I
RW FB15_11 83 I/O I
A<23> FB15_14 86 I/O I
A<22> FB15_15 87 I/O I
A<21> FB15_17 88 I/O I
A<20> FB16_2 91 I/O I
A<19> FB16_3 92 I/O I
A<18> FB16_6 94 I/O I
A<17> FB16_8 95 I/O I
A<16> FB16_11 97 I/O I
Legend:
Pin No. - ~ - User Assigned
************************** Function Block Details ************************
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X - Signal used as input to the macrocell logic.
Pin No. - ~ - User Assigned
*********************************** FB1 ***********************************
Number of function block inputs used/remaining: 25/29
Number of signals used by logic mapping into function block: 25
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB1_1 (b)
(unused) 0 0 0 5 FB1_2 (b)
AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2
1 0 0 4 FB1_3 (b) (b)
$OpTx$FX_DC$34 1 0 0 4 FB1_4 (b) (b)
D<5> 4 0 0 1 FB1_5 20 I/O I/O
D<4> 4 0 0 1 FB1_6 21 I/O I/O
AS_D 2 0 0 3 FB1_7 (b) (b)
IDE_CS<0> 1 0 0 4 FB1_8 22 I/O O
ROM_OE_S 3 0 0 2 FB1_9 (b) (b)
IDE_CS<1> 1 0 0 4 FB1_10 23 I/O O
LAN_RD_S 3 0 0 2 FB1_11 (b) (b)
IDE_A<0> 1 0 0 4 FB1_12 24 I/O O
IDE_W_S 3 0 0 2 FB1_13 (b) (b)
IDE_A<2> 1 0 0 4 FB1_14 25 I/O O
IDE_A<1> 1 0 0 4 FB1_15 26 I/O O
IDE_R_S 3 0 0 2 FB1_16 (b) (b)
IDE_R 1 0 0 4 FB1_17 27 I/O O
IDE_ENABLE 3 0 0 2 FB1_18 (b) (b)
Signals Used by Logic in Function Block
1: $OpTx$FX_DC$19 10: A<9> 18: DQ<12>.PIN
2: $OpTx$FX_DC$3 11: A<10> 19: RESET
3: AS 12: A<11> 20: RW
4: A<12> 13: IDE_ENABLE 21: SLAVE
5: A<13> 14: IDE_R_S 22: autoconfig
6: A<15> 15: DQ<5>.PIN 23: ide
7: D<4> 16: DQ<4>.PIN 24: lan_adr
8: D<5> 17: DQ<13>.PIN 25: lan_adr_sw/lan_adr_sw_CLKF
9: D_OUT_or0002/D_OUT_or0002_D2
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2
X.X..................X.................. 3
$OpTx$FX_DC$34 X....X.............X...X................ 4
D<5> .X.....XX.....X.X..XXX.................. 8
D<4> .X....X.X......X.X.XXX.................. 8
AS_D ..X...............X.....X............... 3
IDE_CS<0> ...X.................................... 1
ROM_OE_S X...........X.....XX..X.X............... 6
IDE_CS<1> ....X................................... 1
LAN_RD_S X....X............XX...XX............... 6
IDE_A<0> .........X.............................. 1
IDE_W_S X.................XX..X.X............... 5
IDE_A<2> ...........X............................ 1
IDE_A<1> ..........X............................. 1
IDE_R_S X...........X.....XX..X.X............... 6
IDE_R ..X..........X.......................... 2
IDE_ENABLE ..X...............XX..X.X............... 5
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB2 ***********************************
Number of function block inputs used/remaining: 33/21
Number of signals used by logic mapping into function block: 33
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB2_1 (b)
A_LAN<4> 3 0 0 2 FB2_2 9 I/O O
A_LAN<7> 3 0 0 2 FB2_3 10 I/O O
(unused) 0 0 0 5 FB2_4 (b)
A_LAN<6> 4 0 0 1 FB2_5 11 I/O O
(unused) 0 0 0 5 FB2_6 12 I/O
(unused) 0 0 0 5 FB2_7 (b)
(unused) 0 0 0 5 FB2_8 13 I/O
(unused) 0 0 0 5 FB2_9 (b)
D<6> 4 0 0 1 FB2_10 14 I/O I/O
(unused) 0 0 0 5 FB2_11 (b)
D<3> 4 0 0 1 FB2_12 15 I/O I/O
(unused) 0 0 0 5 FB2_13 (b)
D<7> 4 0 0 1 FB2_14 16 I/O I/O
D<1> 4 0 0 1 FB2_15 17 I/O I/O
(unused) 0 0 0 5 FB2_16 (b)
D<8> 4 0 0 1 FB2_17 19 I/O I/O
(unused) 0 0 0 5 FB2_18 (b)
Signals Used by Logic in Function Block
1: $OpTx$FX_DC$1 12: CP_CS 23: DQ<0>.PIN
2: $OpTx$FX_DC$3 13: D<1> 24: DQ<11>.PIN
3: A<3> 14: D<3> 25: DQ<9>.PIN
4: A<5> 15: D<6> 26: DQ<8>.PIN
5: A<6> 16: D<7> 27: DQ<7>.PIN
6: A<7> 17: D<8> 28: DQ<6>.PIN
7: A<8> 18: D_OUT_or0002/D_OUT_or0002_D2 29: RW
8: A_LAN<4> 19: DQ<15>.PIN 30: SET_FREQUENCY
9: A_LAN<6> 20: DQ<14>.PIN 31: SLAVE
10: A_LAN<7> 21: DQ<3>.PIN 32: autoconfig
11: CLEAR_REGISTER 22: DQ<1>.PIN 33: lan_adr
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
A_LAN<4> ..XX...X...X.................X..X....... 6
A_LAN<7> ....X.X..X.X.................X..X....... 6
A_LAN<6> ...X.X..X.XX.................X..X....... 7
D<6> .X............X..X.X.......XX.XX........ 8
D<3> .X...........X...X..X..X....X.XX........ 8
D<7> .X.............X.XX.......X.X.XX........ 8
D<1> .X..........X....X...X..X...X.XX........ 8
D<8> X...............XX....X..X..X.XX........ 8
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB3 ***********************************
Number of function block inputs used/remaining: 26/28
Number of signals used by logic mapping into function block: 26
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 /\1 4 FB3_1 (b) (b)
IDE_W 1 0 0 4 FB3_2 28 I/O O
(unused) 0 0 0 5 FB3_3 (b)
(unused) 0 0 0 5 FB3_4 (b)
(unused) 0 0 0 5 FB3_5 (b)
(unused) 0 0 0 5 FB3_6 (b)
(unused) 0 0 0 5 FB3_7 (b)
(unused) 0 0 0 5 FB3_8 (b)
SHUT_UP<1> 3 0 0 2 FB3_9 (b) (b)
LAN_IRQ_D0 3 0 0 2 FB3_10 30 GCK/I/O GCK
IDE_BASEADR<6> 4 0 0 1 FB3_11 (b) (b)
IDE_BASEADR<1> 4 0 0 1 FB3_12 31 I/O I
IDE_BASEADR<0> 4 0 0 1 FB3_13 (b) (b)
INT2_OUT 1 0 0 4 FB3_14 32 GCK/I/O O
CP_BASEADR<6> 4 0 0 1 FB3_15 33 I/O (b)
CP_BASEADR<1> 4 0 0 1 FB3_16 (b) (b)
CP_BASEADR<0> 4 0 \/1 0 FB3_17 (b) (b)
LAN_IRQ_OUT 7 2<- 0 0 FB3_18 (b) (b)
Signals Used by Logic in Function Block
1: $OpTx$FX_DC$34 10: IDE_BASEADR<6> 19: D<9>.PIN
2: AS 11: IDE_BASEADR_not0001/IDE_BASEADR_not0001_D2 20: D<8>.PIN
3: A<15> 12: IDE_W_S 21: RESET
4: CP_BASEADR<0> 13: LAN_INT_ENABLE 22: RW
5: CP_BASEADR<1> 14: LAN_INT 23: SHUT_UP<1>
6: CP_BASEADR<6> 15: LAN_IRQ_D0 24: UDS
7: CP_BASEADR_not0001/CP_BASEADR_not0001_D2 16: LAN_IRQ_OUT 25: lan_adr
8: IDE_BASEADR<0> 17: LDS 26: lan_adr_sw/lan_adr_sw_CLKF
9: IDE_BASEADR<1> 18: D<14>.PIN
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
IDE_W .X.........X............................ 2
SHUT_UP<1> ......X.............X.X..X.............. 4
LAN_IRQ_D0 .............X......X....X.............. 3
IDE_BASEADR<6> .........XX......X..X....X.............. 5
IDE_BASEADR<1> ........X.X.......X.X....X.............. 5
IDE_BASEADR<0> .......X..X........XX....X.............. 5
INT2_OUT ............X..X........................ 2
CP_BASEADR<6> .....XX..........X..X....X.............. 5
CP_BASEADR<1> ....X.X...........X.X....X.............. 5
CP_BASEADR<0> ...X..X............XX....X.............. 5
LAN_IRQ_OUT X.X.........XXXXXX..XX.XXX.............. 13
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB4 ***********************************
Number of function block inputs used/remaining: 25/29
Number of signals used by logic mapping into function block: 25
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB4_1 (b)
D<0> 4 0 0 1 FB4_2 2 GTS/I/O I/O
(unused) 0 0 0 5 FB4_3 (b)
(unused) 0 0 0 5 FB4_4 (b)
A_LAN<1> 3 0 0 2 FB4_5 3 GTS/I/O O
A_LAN<0> 3 0 0 2 FB4_6 4 I/O O
(unused) 0 0 0 5 FB4_7 (b)
A_LAN<3> 3 0 0 2 FB4_8 5 GTS/I/O O
(unused) 0 0 0 5 FB4_9 (b)
(unused) 0 0 0 5 FB4_10 (b)
(unused) 0 0 0 5 FB4_11 (b)
A_LAN<2> 3 0 0 2 FB4_12 6 GTS/I/O O
(unused) 0 0 0 5 FB4_13 (b)
A_LAN<5> 3 0 0 2 FB4_14 7 I/O O
(unused) 0 0 0 5 FB4_15 (b)
(unused) 0 0 0 5 FB4_16 (b)
(unused) 0 0 0 5 FB4_17 (b)
CP_BASEADR_not0001/CP_BASEADR_not0001_D2
1 0 0 4 FB4_18 (b) (b)
Signals Used by Logic in Function Block
1: $OpTx$FX_DC$3 10: A<6> 18: D_OUT_or0002/D_OUT_or0002_D2
2: AUTO_CONFIG_DONE<0> 11: A_LAN<0> 19: DQ<0>.PIN
3: AUTO_CONFIG_DONE<1> 12: A_LAN<1> 20: DQ<8>.PIN
4: AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2 13: A_LAN<2> 21: RW
5: A<1> 14: A_LAN<3> 22: SET_FREQUENCY
6: A<2> 15: A_LAN<5> 23: SLAVE
7: A<3> 16: CP_CS 24: autoconfig
8: A<4> 17: D<0> 25: lan_adr
9: A<5>
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
D<0> X...............XXXXX.XX................ 8
A_LAN<1> .....X.....X...X.....X..X............... 5
A_LAN<0> ....X.....X....X.....X..X............... 5
A_LAN<3> .....X.X.....X.X.....X..X............... 6
A_LAN<2> ....X.X.....X..X.....X..X............... 6
A_LAN<5> .......X.X....XX.....X..X............... 6
CP_BASEADR_not0001/CP_BASEADR_not0001_D2
.XXXXXXXXX..........X................... 10
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB5 ***********************************
Number of function block inputs used/remaining: 42/12
Number of signals used by logic mapping into function block: 42
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 \/5 0 FB5_1 (b) (b)
CP_CS 19 14<- 0 0 FB5_2 34 I/O O
(unused) 0 0 /\5 0 FB5_3 (b) (b)
(unused) 0 0 /\4 1 FB5_4 (b) (b)
ROM_OE 2 0 0 3 FB5_5 35 I/O O
(unused) 0 0 0 5 FB5_6 (b)
(unused) 0 0 0 5 FB5_7 (b)
(unused) 0 0 0 5 FB5_8 38 GCK/I/O
(unused) 0 0 0 5 FB5_9 (b)
D<2> 4 0 0 1 FB5_10 39 I/O I/O
(unused) 0 0 0 5 FB5_11 (b)
D<9> 4 0 0 1 FB5_12 40 I/O I/O
(unused) 0 0 0 5 FB5_13 (b)
D<10> 4 0 0 1 FB5_14 41 I/O I/O
D<11> 4 0 0 1 FB5_15 43 I/O I/O
(unused) 0 0 0 5 FB5_16 (b)
D<12> 5 0 0 0 FB5_17 44 I/O I/O
(unused) 0 0 0 5 FB5_18 (b)
Signals Used by Logic in Function Block
1: $OpTx$FX_DC$1 15: CP_BASEADR<2> 29: DQ<3>.PIN
2: $OpTx$FX_DC$3 16: CP_BASEADR<3> 30: DQ<2>.PIN
3: AS_D 17: CP_BASEADR<4> 31: DQ<1>.PIN
4: AS 18: CP_BASEADR<5> 32: DQ<12>.PIN
5: A<16> 19: CP_BASEADR<6> 33: DQ<11>.PIN
6: A<17> 20: CP_BASEADR<7> 34: DQ<10>.PIN
7: A<18> 21: D<10> 35: DQ<9>.PIN
8: A<19> 22: D<11> 36: RESET
9: A<20> 23: D<12> 37: ROM_OE_S
10: A<21> 24: D<2> 38: RW
11: A<22> 25: D<9> 39: SHUT_UP<1>
12: A<23> 26: D_OUT_or0002/D_OUT_or0002_D2 40: SLAVE
13: CP_BASEADR<0> 27: Dout1<0> 41: autoconfig
14: CP_BASEADR<1> 28: DQ<4>.PIN 42: lan_adr_sw/lan_adr_sw_CLKF
Signal 1 2 3 4 5 FB
Name 0----+----0----+----0----+----0----+----0----+----0 Inputs
CP_CS ....XXXXXXXXXXXXXXXX...............X..X..X........ 19
ROM_OE ..XX................................X............. 3
D<2> .X.....................X.X...X...X...X.XX......... 8
D<9> X.......................XX....X...X..X.XX......... 8
D<10> X...................X....X...X...X...X.XX......... 8
D<11> X....................X...X..X...X....X.XX......... 8
D<12> X.....................X..XXX...X.....X.XX......... 9
0----+----1----+----2----+----3----+----4----+----5
0 0 0 0 0
*********************************** FB6 ***********************************
Number of function block inputs used/remaining: 25/29
Number of signals used by logic mapping into function block: 25
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB6_1 (b)
INT6_OUT 1 0 0 4 FB6_2 135 I/O O
A_LAN<12> 3 0 0 2 FB6_3 136 I/O O
(unused) 0 0 0 5 FB6_4 (b)
A_LAN<13> 3 0 0 2 FB6_5 137 I/O O
A_LAN<10> 3 0 0 2 FB6_6 138 I/O O
(unused) 0 0 0 5 FB6_7 (b)
A_LAN<11> 3 0 0 2 FB6_8 139 I/O O
(unused) 0 0 0 5 FB6_9 (b)
A_LAN<8> 3 0 0 2 FB6_10 140 I/O O
$OpTx$FX_SC$321 1 0 0 4 FB6_11 (b) (b)
$OpTx$FX_DC$30 1 0 0 4 FB6_12 (b) (b)
$OpTx$FX_DC$3 1 0 0 4 FB6_13 (b) (b)
A_LAN<9> 3 0 0 2 FB6_14 142 I/O O
$OpTx$FX_DC$1 1 0 0 4 FB6_15 143 GSR/I/O I
$OpTx$FX_SC$52 2 0 0 3 FB6_16 (b) (b)
D_IN<0> 3 0 0 2 FB6_17 (b) (b)
DQ_or0001/DQ_or0001_D2
3 0 0 2 FB6_18 (b) (b)
Signals Used by Logic in Function Block
1: $OpTx$FX_DC$1 10: A_LAN<12> 18: A<10>
2: AS 11: A_LAN<13> 19: A<11>
3: A<12> 12: A_LAN<8> 20: D<8>.PIN
4: A<13> 13: A_LAN<9> 21: D<0>.PIN
5: A<14> 14: CP_CS 22: RW
6: A<7> 15: CP_IRQ 23: SET_FREQUENCY
7: A<8> 16: D_OUT_and0001/D_OUT_and0001_D2 24: ide
8: A_LAN<10> 17: A<9> 25: lan_adr
9: A_LAN<11>
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
INT6_OUT ..............X......................... 1
A_LAN<12> ...X.....X...X....X...X.X............... 6
A_LAN<13> ..X.X.....X..X........X.X............... 6
A_LAN<10> .......X.....X..X.X...X.X............... 6
A_LAN<11> ..X.....X....X...X....X.X............... 6
A_LAN<8> .....X.....X.X..X.....X.X............... 6
$OpTx$FX_SC$321 .............X........XXX............... 4
$OpTx$FX_DC$30 .X....................X................. 2
$OpTx$FX_DC$3 .............X.X........................ 2
A_LAN<9> ......X.....XX...X....X.X............... 6
$OpTx$FX_DC$1 .............X.X........................ 2
$OpTx$FX_SC$52 .............X.X.......XX............... 4
D_IN<0> X..................XX.XXX............... 6
DQ_or0001/DQ_or0001_D2
.X...........X.......XXXX............... 6
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB7 ***********************************
Number of function block inputs used/remaining: 25/29
Number of signals used by logic mapping into function block: 25
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB7_1 (b)
(unused) 0 0 0 5 FB7_2 (b)
D<13> 5 0 0 0 FB7_3 45 I/O I/O
(unused) 0 0 0 5 FB7_4 (b)
D<14> 5 0 0 0 FB7_5 46 I/O I/O
(unused) 0 0 0 5 FB7_6 (b)
(unused) 0 0 0 5 FB7_7 (b)
(unused) 0 0 0 5 FB7_8 (b)
(unused) 0 0 0 5 FB7_9 (b)
(unused) 0 0 0 5 FB7_10 (b)
(unused) 0 0 0 5 FB7_11 (b)
D<15> 5 0 0 0 FB7_12 48 I/O I/O
(unused) 0 0 0 5 FB7_13 (b)
(unused) 0 0 0 5 FB7_14 (b)
LAN_RST_SM_FSM_FFd8 1 0 0 4 FB7_15 49 I/O I
D_IN<13> 1 0 0 4 FB7_16 (b) (b)
D_IN<5> 3 0 0 2 FB7_17 (b) (b)
BUF_D_IN<13> 3 0 0 2 FB7_18 (b) (b)
Signals Used by Logic in Function Block
1: $OpTx$FX_DC$1 10: Dout1<1> 18: D<5>.PIN
2: $OpTx$FX_SC$321 11: Dout1<2> 19: DQ<7>.PIN
3: $OpTx$FX_SC$52 12: Dout1<3> 20: DQ<6>.PIN
4: BUF_D_IN<13> 13: DQ<15>.PIN 21: RESET
5: D<13> 14: DQ<5>.PIN 22: RW
6: D<14> 15: DQ<14>.PIN 23: SET_FREQUENCY
7: D<15> 16: D<13>.PIN 24: SLAVE
8: D_OUT_and0001/D_OUT_and0001_D2 17: DQ<13>.PIN 25: autoconfig
9: D_OUT_or0002/D_OUT_or0002_D2
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
D<13> X...X...XX...X..X....X.XX............... 9
D<14> X....X..X.X...X....X.X.XX............... 9
D<15> X.....X.X..XX.....X..X.XX............... 9
LAN_RST_SM_FSM_FFd8 ....................X.X................. 2
D_IN<13> ...X.................................... 1
D_IN<5> X.XX...X.......X.X....X................. 7
BUF_D_IN<13> .X.....X.......X.X....X................. 5
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB8 ***********************************
Number of function block inputs used/remaining: 25/29
Number of signals used by logic mapping into function block: 25
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB8_1 (b)
DQ<12> 2 0 0 3 FB8_2 130 I/O I/O
DQ<14> 2 0 0 3 FB8_3 131 I/O I/O
(unused) 0 0 0 5 FB8_4 (b)
LAN_WRH 2 0 0 3 FB8_5 132 I/O O
(unused) 0 0 0 5 FB8_6 (b)
(unused) 0 0 0 5 FB8_7 (b)
LAN_CS 2 0 0 3 FB8_8 133 I/O O
(unused) 0 0 0 5 FB8_9 (b)
LAN_RD 2 0 0 3 FB8_10 134 I/O O
(unused) 0 0 0 5 FB8_11 (b)
D_IN<9> 3 0 0 2 FB8_12 (b) (b)
D_IN<8> 3 0 0 2 FB8_13 (b) (b)
D_IN<3> 3 0 0 2 FB8_14 (b) (b)
D_IN<2> 3 0 0 2 FB8_15 (b) (b)
D_IN<1> 3 0 0 2 FB8_16 (b) (b)
D_IN<11> 3 0 0 2 FB8_17 (b) (b)
D_IN<10> 3 0 0 2 FB8_18 (b) (b)
Signals Used by Logic in Function Block
1: $OpTx$FX_DC$1 10: D_OUT_and0001/D_OUT_and0001_D2 18: D<8>.PIN
2: $OpTx$FX_DC$30 11: LAN_CS_RST 19: D<3>.PIN
3: $OpTx$FX_SC$321 12: LAN_RD_S 20: D<2>.PIN
4: AS_D 13: LAN_WRH_S 21: D<1>.PIN
5: CLEAR_REGISTER 14: LAN_WR_RST 22: D<0>.PIN
6: DQ_9_IOBUFE/DQ_9_IOBUFE_TRST 15: D<11>.PIN 23: SET_FREQUENCY
7: DQ_or0001/DQ_or0001_D2 16: D<10>.PIN 24: ide
8: D_IN<12> 17: D<9>.PIN 25: lan_adr
9: D_IN<14>
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
DQ<12> .....XXX................................ 3
DQ<14> .....XX.X............................... 3
LAN_WRH .X..........XX.......................... 3
LAN_CS ..........X...........X.X............... 3
LAN_RD .X.X.......X..........X................. 4
D_IN<9> ..X.X....X......X...X.X................. 6
D_IN<8> ..X.X....X.......X...XX................. 6
D_IN<3> X.............X...X...XXX............... 6
D_IN<2> X..............X...X..XXX............... 6
D_IN<1> X...............X...X.XXX............... 6
D_IN<11> ..X.X....X....X...X...X................. 6
D_IN<10> ..X.X....X.....X...X..X................. 6
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB9 ***********************************
Number of function block inputs used/remaining: 26/28
Number of signals used by logic mapping into function block: 26
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 /\3 2 FB9_1 (b) (b)
(unused) 0 0 0 5 FB9_2 50 I/O I
(unused) 0 0 0 5 FB9_3 51 I/O I
(unused) 0 0 0 5 FB9_4 (b)
(unused) 0 0 0 5 FB9_5 52 I/O I
(unused) 0 0 0 5 FB9_6 53 I/O I
(unused) 0 0 0 5 FB9_7 (b)
(unused) 0 0 0 5 FB9_8 54 I/O I
(unused) 0 0 0 5 FB9_9 (b)
(unused) 0 0 0 5 FB9_10 (b)
LAN_BASEADR_not0001/LAN_BASEADR_not0001_D2
1 0 0 4 FB9_11 56 I/O I
$OpTx$FX_DC$31 1 0 0 4 FB9_12 57 I/O I
LAN_BASEADR<4> 4 0 0 1 FB9_13 (b) (b)
LAN_BASEADR<3> 4 0 0 1 FB9_14 58 I/O I
LAN_BASEADR<2> 4 0 0 1 FB9_15 (b) (b)
LAN_BASEADR<1> 4 0 0 1 FB9_16 (b) (b)
LAN_BASEADR<0> 4 0 \/1 0 FB9_17 59 I/O I
Dout1<3> 9 4<- 0 0 FB9_18 (b) (b)
Signals Used by Logic in Function Block
1: AUTO_CONFIG_DONE<0> 10: CFOUT 19: D<12>.PIN
2: AUTO_CONFIG_DONE<1> 11: Dout1<3> 20: D<11>.PIN
3: AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2 12: IDE_BASEADR_not0001/IDE_BASEADR_not0001_D2 21: D<10>.PIN
4: A<1> 13: LAN_BASEADR<0> 22: D<9>.PIN
5: A<2> 14: LAN_BASEADR<1> 23: D<8>.PIN
6: A<3> 15: LAN_BASEADR<2> 24: RESET
7: A<4> 16: LAN_BASEADR<3> 25: RW
8: A<5> 17: LAN_BASEADR<4> 26: lan_adr_sw/lan_adr_sw_CLKF
9: A<6> 18: LAN_BASEADR_not0001/LAN_BASEADR_not0001_D2
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
LAN_BASEADR_not0001/LAN_BASEADR_not0001_D2
X.XXXXXXX..X............X............... 10
$OpTx$FX_DC$31 ..XX.XXXXX..............X............... 8
LAN_BASEADR<4> ................XXX....X.X.............. 5
LAN_BASEADR<3> ...............X.X.X...X.X.............. 5
LAN_BASEADR<2> ..............X..X..X..X.X.............. 5
LAN_BASEADR<1> .............X...X...X.X.X.............. 5
LAN_BASEADR<0> ............X....X....XX.X.............. 5
Dout1<3> .XXXXXXXX.X............X.X.............. 11
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB10 ***********************************
Number of function block inputs used/remaining: 26/28
Number of signals used by logic mapping into function block: 26
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB10_1 (b)
DQ<1> 2 0 0 3 FB10_2 117 I/O I/O
DQ<0> 2 0 0 3 FB10_3 118 I/O I/O
$OpTx$FX_DC$19 1 0 0 4 FB10_4 (b) (b)
DQ<3> 2 0 0 3 FB10_5 119 I/O I/O
DQ<2> 2 0 0 3 FB10_6 120 I/O I/O
DQ_9_IOBUFE/DQ_9_IOBUFE_TRST
2 0 0 3 FB10_7 (b) (b)
DQ<5> 2 0 0 3 FB10_8 121 I/O I/O
LAN_WRL_S 3 0 0 2 FB10_9 (b) (b)
DQ<4> 2 0 0 3 FB10_10 124 I/O I/O
DQ<7> 2 0 0 3 FB10_11 125 I/O I/O
DQ<6> 2 0 0 3 FB10_12 126 I/O I/O
LAN_WRH_S 3 0 0 2 FB10_13 (b) (b)
DQ<8> 2 0 0 3 FB10_14 128 I/O I/O
CP_WE_S 3 0 0 2 FB10_15 (b) (b)
CP_RD_S 3 0 0 2 FB10_16 (b) (b)
DQ<10> 2 0 0 3 FB10_17 129 I/O I/O
LAN_INT_ENABLE 5 0 0 0 FB10_18 (b) (b)
Signals Used by Logic in Function Block
1: $OpTx$FX_DC$19 10: D_IN<1> 19: LDS
2: $OpTx$FX_DC$34 11: D_IN<2> 20: D<15>.PIN
3: AS 12: D_IN<3> 21: RESET
4: A<15> 13: D_IN<4> 22: RW
5: CP_CS 14: D_IN<5> 23: UDS
6: DQ_9_IOBUFE/DQ_9_IOBUFE_TRST 15: D_IN<6> 24: ide
7: DQ_or0001/DQ_or0001_D2 16: D_IN<7> 25: lan_adr
8: D_IN<0> 17: D_IN<8> 26: lan_adr_sw/lan_adr_sw_CLKF
9: D_IN<10> 18: LAN_INT_ENABLE
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
DQ<1> .....XX..X.............................. 3
DQ<0> .....XXX................................ 3
$OpTx$FX_DC$19 ..................X...X................. 2
DQ<3> .....XX....X............................ 3
DQ<2> .....XX...X............................. 3
DQ_9_IOBUFE/DQ_9_IOBUFE_TRST
..X...X..............X.X................ 4
DQ<5> .....XX......X.......................... 3
LAN_WRL_S ...X................XXX.XX.............. 6
DQ<4> .....XX.....X........................... 3
DQ<7> .....XX........X........................ 3
DQ<6> .....XX.......X......................... 3
LAN_WRH_S ...X..............X.XX..XX.............. 6
DQ<8> .....XX.........X....................... 3
CP_WE_S X...X...............XX...X.............. 5
CP_RD_S ..X.X...............XX...X.............. 5
DQ<10> .....XX.X............................... 3
LAN_INT_ENABLE .X.X.............XXXXXX.XX.............. 10
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB11 ***********************************
Number of function block inputs used/remaining: 26/28
Number of signals used by logic mapping into function block: 26
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 /\5 0 FB11_1 (b) (b)
(unused) 0 0 /\4 1 FB11_2 (b) (b)
(unused) 0 0 0 5 FB11_3 60 I/O I
(unused) 0 0 0 5 FB11_4 (b)
(unused) 0 0 0 5 FB11_5 61 I/O I
(unused) 0 0 0 5 FB11_6 (b)
(unused) 0 0 0 5 FB11_7 (b)
(unused) 0 0 0 5 FB11_8 (b)
(unused) 0 0 0 5 FB11_9 (b)
(unused) 0 0 0 5 FB11_10 64 I/O I
(unused) 0 0 0 5 FB11_11 66 I/O I
ROM_B<0> 0 0 0 5 FB11_12 68 I/O O
autoconfig 3 0 0 2 FB11_13 (b) (b)
ROM_B<1> 0 0 0 5 FB11_14 69 I/O O
SHUT_UP<0> 3 0 0 2 FB11_15 (b) (b)
CP_WE_QUIRK 3 0 \/1 1 FB11_16 (b) (b)
CP_WE 1 1<- \/5 0 FB11_17 70 I/O O
ide 19 14<- 0 0 FB11_18 (b) (b)
Signals Used by Logic in Function Block
1: AS 10: CFIN 19: IDE_BASEADR<5>
2: A<16> 11: CFOUT 20: IDE_BASEADR<6>
3: A<17> 12: CP_WE_QUIRK 21: IDE_BASEADR<7>
4: A<18> 13: CP_WE_S 22: LAN_BASEADR_not0001/LAN_BASEADR_not0001_D2
5: A<19> 14: IDE_BASEADR<0> 23: RESET
6: A<20> 15: IDE_BASEADR<1> 24: SHUT_UP<0>
7: A<21> 16: IDE_BASEADR<2> 25: SHUT_UP<2>
8: A<22> 17: IDE_BASEADR<3> 26: lan_adr_sw/lan_adr_sw_CLKF
9: A<23> 18: IDE_BASEADR<4>
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
ROM_B<0> ........................................ 0
autoconfig .XXXXXXXXXX...........X..X.............. 12
ROM_B<1> ........................................ 0
SHUT_UP<0> .....................XXX.X.............. 4
CP_WE_QUIRK ............X.........X..X.............. 3
CP_WE X..........XX........................... 3
ide .XXXXXXXX....XXXXXXXX.X.XX.............. 19
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB12 ***********************************
Number of function block inputs used/remaining: 25/29
Number of signals used by logic mapping into function block: 25
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
SET_FREQUENCY 1 0 0 4 FB12_1 (b) (b)
D_IN<15> 1 0 0 4 FB12_2 110 I/O (b)
D_IN<14> 1 0 0 4 FB12_3 111 I/O I
D_IN<12> 1 0 0 4 FB12_4 (b) (b)
DQ<15> 2 0 0 3 FB12_5 112 I/O I/O
LAN_RST_SM_FSM_FFd7 2 0 0 3 FB12_6 (b) (b)
LAN_RST_SM_FSM_FFd4 2 0 0 3 FB12_7 (b) (b)
DQ<13> 2 0 0 3 FB12_8 113 I/O I/O
LAN_CS_RST 2 0 0 3 FB12_9 (b) (b)
DQ<11> 2 0 0 3 FB12_10 115 I/O I/O
CLEAR_REGISTER 2 0 0 3 FB12_11 (b) (b)
DQ<9> 2 0 0 3 FB12_12 116 I/O I/O
D_IN<7> 3 0 0 2 FB12_13 (b) (b)
D_IN<6> 3 0 0 2 FB12_14 (b) (b)
BUF_D_IN<15> 3 0 0 2 FB12_15 (b) (b)
BUF_D_IN<14> 3 0 0 2 FB12_16 (b) (b)
BUF_D_IN<12> 3 0 0 2 FB12_17 (b) (b)
D_IN<4> 4 0 0 1 FB12_18 (b) (b)
Signals Used by Logic in Function Block
1: $OpTx$FX_DC$1 10: D_IN<11> 18: D<15>.PIN
2: $OpTx$FX_SC$321 11: D_IN<13> 19: D<14>.PIN
3: $OpTx$FX_SC$52 12: D_IN<15> 20: D<12>.PIN
4: BUF_D_IN<12> 13: D_IN<9> 21: D<7>.PIN
5: BUF_D_IN<14> 14: D_OUT_and0001/D_OUT_and0001_D2 22: D<6>.PIN
6: BUF_D_IN<15> 15: LAN_RST_SM_FSM_FFd1 23: D<4>.PIN
7: CLEAR_REGISTER 16: LAN_RST_SM_FSM_FFd5 24: RESET
8: DQ_9_IOBUFE/DQ_9_IOBUFE_TRST 17: LAN_RST_SM_FSM_FFd8 25: SET_FREQUENCY
9: DQ_or0001/DQ_or0001_D2
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
SET_FREQUENCY ..............X........XX............... 3
D_IN<15> .....X.................................. 1
D_IN<14> ....X................................... 1
D_IN<12> ...X.................................... 1
DQ<15> .......XX..X............................ 3
LAN_RST_SM_FSM_FFd7 ................X......XX............... 3
LAN_RST_SM_FSM_FFd4 ...............X.......XX............... 3
DQ<13> .......XX.X............................. 3
LAN_CS_RST ..............X.X......XX............... 4
DQ<11> .......XXX.............................. 3
CLEAR_REGISTER ......X........X.......XX............... 4
DQ<9> .......XX...X........................... 3
D_IN<7> X.X..X.......X...X..X...X............... 7
D_IN<6> X.X.X........X....X..X..X............... 7
BUF_D_IN<15> .X...........X...X..X...X............... 5
BUF_D_IN<14> .X...........X....X..X..X............... 5
BUF_D_IN<12> .X...........X.....X..X.X............... 5
D_IN<4> X.XX..X......X.....X..X.X............... 8
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB13 ***********************************
Number of function block inputs used/remaining: 26/28
Number of signals used by logic mapping into function block: 26
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB13_1 (b)
CP_RD 2 0 0 3 FB13_2 71 I/O O
(unused) 0 0 0 5 FB13_3 (b)
(unused) 0 0 0 5 FB13_4 (b)
(unused) 0 0 0 5 FB13_5 (b)
(unused) 0 0 0 5 FB13_6 (b)
SHUT_UP<2> 3 0 0 2 FB13_7 (b) (b)
IDE_BASEADR<7> 4 0 0 1 FB13_8 74 I/O I
IDE_BASEADR<5> 4 0 0 1 FB13_9 (b) (b)
IDE_BASEADR<4> 4 0 0 1 FB13_10 (b) (b)
IDE_BASEADR<3> 4 0 0 1 FB13_11 75 I/O I
IDE_BASEADR<2> 4 0 0 1 FB13_12 (b) (b)
CP_BASEADR<7> 4 0 0 1 FB13_13 (b) (b)
LAN_WRL 2 0 0 3 FB13_14 76 I/O O
CP_BASEADR<5> 4 0 0 1 FB13_15 77 I/O (b)
CP_BASEADR<4> 4 0 0 1 FB13_16 (b) (b)
CP_BASEADR<3> 4 0 0 1 FB13_17 78 I/O (b)
CP_BASEADR<2> 4 0 0 1 FB13_18 (b) (b)
Signals Used by Logic in Function Block
1: $OpTx$FX_DC$30 10: CP_RD_S 19: D<15>.PIN
2: AS_D 11: IDE_BASEADR<2> 20: D<13>.PIN
3: AS 12: IDE_BASEADR<3> 21: D<12>.PIN
4: CP_BASEADR<2> 13: IDE_BASEADR<4> 22: D<11>.PIN
5: CP_BASEADR<3> 14: IDE_BASEADR<5> 23: D<10>.PIN
6: CP_BASEADR<4> 15: IDE_BASEADR<7> 24: RESET
7: CP_BASEADR<5> 16: IDE_BASEADR_not0001/IDE_BASEADR_not0001_D2 25: SHUT_UP<2>
8: CP_BASEADR<7> 17: LAN_WRL_S 26: lan_adr_sw/lan_adr_sw_CLKF
9: CP_BASEADR_not0001/CP_BASEADR_not0001_D2 18: LAN_WR_RST
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
CP_RD .XX......X.............................. 3
SHUT_UP<2> ...............X.......XXX.............. 4
IDE_BASEADR<7> ..............XX..X....X.X.............. 5
IDE_BASEADR<5> .............X.X...X...X.X.............. 5
IDE_BASEADR<4> ............X..X....X..X.X.............. 5
IDE_BASEADR<3> ...........X...X.....X.X.X.............. 5
IDE_BASEADR<2> ..........X....X......XX.X.............. 5
CP_BASEADR<7> .......XX.........X....X.X.............. 5
LAN_WRL X...............XX...................... 3
CP_BASEADR<5> ......X.X..........X...X.X.............. 5
CP_BASEADR<4> .....X..X...........X..X.X.............. 5
CP_BASEADR<3> ....X...X............X.X.X.............. 5
CP_BASEADR<2> ...X....X.............XX.X.............. 5
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB14 ***********************************
Number of function block inputs used/remaining: 26/28
Number of signals used by logic mapping into function block: 26
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
Dout1<0> 11 6<- 0 0 FB14_1 (b) (b)
(unused) 0 0 /\5 0 FB14_2 (b) (b)
OVR 0 0 \/3 2 FB14_3 100 I/O O
Dout1<2> 11 6<- 0 0 FB14_4 (b) (b)
D_OUT_or0002/D_OUT_or0002_D2
2 0 /\3 0 FB14_5 101 I/O (b)
AUTO_CONFIG_DONE_CYCLE<0>
5 0 0 0 FB14_6 102 I/O I
AUTO_CONFIG_DONE_CYCLE<1>
5 0 0 0 FB14_7 (b) (b)
AUTO_CONFIG_DONE<0> 4 0 0 1 FB14_8 103 I/O I
AUTO_CONFIG_DONE<1> 4 0 0 1 FB14_9 (b) (b)
IDE_BASEADR_not0001/IDE_BASEADR_not0001_D2
1 0 0 4 FB14_10 104 I/O I
CFOUT 1 0 0 4 FB14_11 105 I/O O
(unused) 0 0 0 5 FB14_12 (b)
(unused) 0 0 0 5 FB14_13 (b)
SLAVE 2 0 0 3 FB14_14 106 I/O O
OWN 0 0 \/4 1 FB14_15 107 I/O O
Dout1<1> 12 7<- 0 0 FB14_16 (b) (b)
(unused) 0 0 /\3 2 FB14_17 (b) (b)
(unused) 0 0 \/1 4 FB14_18 (b) (b)
Signals Used by Logic in Function Block
1: $OpTx$FX_DC$19 10: A<1> 19: Dout1<2>
2: $OpTx$FX_DC$31 11: A<2> 20: IDE_OFF
3: AS_D 12: A<3> 21: RESET
4: AS 13: A<4> 22: RW
5: AUTO_CONFIG_DONE<0> 14: A<5> 23: autoconfig
6: AUTO_CONFIG_DONE<1> 15: A<6> 24: ide
7: AUTO_CONFIG_DONE_CYCLE<0> 16: CP_CS 25: lan_adr
8: AUTO_CONFIG_DONE_CYCLE<1> 17: Dout1<0> 26: lan_adr_sw/lan_adr_sw_CLKF
9: AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2 18: Dout1<1>
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
Dout1<0> ....XX..XXXXXXX.X...X....X.............. 12
OVR ........................................ 0
Dout1<2> ....XX..XXXXXXX...X.X....X.............. 12
D_OUT_or0002/D_OUT_or0002_D2
X..............X......XXX............... 5
AUTO_CONFIG_DONE_CYCLE<0>
.X..X.X.XXXXXXX....XXX...X.............. 14
AUTO_CONFIG_DONE_CYCLE<1>
.X..XX.XXXXXXXX.....XX...X.............. 14
AUTO_CONFIG_DONE<0> ...X..X.............X....X.............. 4
AUTO_CONFIG_DONE<1> ...X...X............X....X.............. 4
IDE_BASEADR_not0001/IDE_BASEADR_not0001_D2
.X...X....X............................. 3
CFOUT ....XX.................................. 2
SLAVE ..XX...........X......XXX............... 6
OWN ........................................ 0
Dout1<1> ....XX..XXXXXXX..X..X....X.............. 12
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB15 ***********************************
Number of function block inputs used/remaining: 25/29
Number of signals used by logic mapping into function block: 25
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB15_1 (b)
(unused) 0 0 0 5 FB15_2 79 I/O
(unused) 0 0 0 5 FB15_3 80 I/O I
(unused) 0 0 0 5 FB15_4 (b)
(unused) 0 0 0 5 FB15_5 (b)
(unused) 0 0 0 5 FB15_6 (b)
(unused) 0 0 0 5 FB15_7 (b)
(unused) 0 0 0 5 FB15_8 81 I/O I
LAN_WR_RST 2 0 0 3 FB15_9 (b) (b)
LAN_RST_SM_FSM_FFd5 2 0 0 3 FB15_10 82 I/O I
LAN_RST_SM_FSM_FFd2 2 0 0 3 FB15_11 83 I/O I
DTACK 0 0 0 5 FB15_12 85 I/O O
LAN_RST_SM_FSM_FFd1 2 0 0 3 FB15_13 (b) (b)
lan_adr 3 0 0 2 FB15_14 86 I/O I
lan_adr_sw 4 0 0 1 FB15_15 87 I/O I
LAN_BASEADR<7> 4 0 0 1 FB15_16 (b) (b)
LAN_BASEADR<6> 4 0 0 1 FB15_17 88 I/O I
LAN_BASEADR<5> 4 0 0 1 FB15_18 (b) (b)
Signals Used by Logic in Function Block
1: $OpTx$FX_DC$38 10: A<14> 18: LAN_RST_SM_FSM_FFd6
2: $OpTx$FX_DC$39 11: LAN_BASEADR<5> 19: D<15>.PIN
3: $OpTx$FX_DC$40 12: LAN_BASEADR<6> 20: D<14>.PIN
4: $OpTx$FX_DC$41 13: LAN_BASEADR<7> 21: D<13>.PIN
5: $OpTx$FX_DC$42 14: LAN_BASEADR_not0001/LAN_BASEADR_not0001_D2 22: RESET
6: $OpTx$FX_DC$43 15: LAN_RST_SM_FSM_FFd1 23: SET_FREQUENCY
7: $OpTx$FX_DC$44 16: LAN_RST_SM_FSM_FFd2 24: SHUT_UP<0>
8: $OpTx$FX_DC$45 17: LAN_RST_SM_FSM_FFd3 25: lan_adr_sw/lan_adr_sw_CLKF
9: A<13>
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
LAN_WR_RST ................XX...XX................. 4
LAN_RST_SM_FSM_FFd5 .................X...XX................. 3
LAN_RST_SM_FSM_FFd2 ................X....XX................. 3
DTACK ........................................ 0
LAN_RST_SM_FSM_FFd1 ..............XX.....XX................. 4
lan_adr XXXXXXXX.............X.XX............... 11
lan_adr_sw XXXXXXXXXX...........X.XX............... 13
LAN_BASEADR<7> ............XX....X..X..X............... 5
LAN_BASEADR<6> ...........X.X.....X.X..X............... 5
LAN_BASEADR<5> ..........X..X......XX..X............... 5
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB16 ***********************************
Number of function block inputs used/remaining: 24/30
Number of signals used by logic mapping into function block: 24
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB16_1 (b)
(unused) 0 0 0 5 FB16_2 91 I/O I
(unused) 0 0 0 5 FB16_3 92 I/O I
(unused) 0 0 0 5 FB16_4 (b)
(unused) 0 0 0 5 FB16_5 93 I/O
D_OUT_and0001/D_OUT_and0001_D2
1 0 0 4 FB16_6 94 I/O I
lan_adr_sw/lan_adr_sw_CLKF
2 0 0 3 FB16_7 (b) (b)
LAN_RST_SM_FSM_FFd6 2 0 0 3 FB16_8 95 I/O I
LAN_RST_SM_FSM_FFd3 2 0 0 3 FB16_9 (b) (b)
MTACK 0 0 0 5 FB16_10 96 I/O O
$OpTx$FX_DC$45 2 0 0 3 FB16_11 97 I/O I
$OpTx$FX_DC$44 2 0 0 3 FB16_12 98 I/O (b)
$OpTx$FX_DC$43 2 0 0 3 FB16_13 (b) (b)
$OpTx$FX_DC$42 2 0 0 3 FB16_14 (b) (b)
$OpTx$FX_DC$41 2 0 0 3 FB16_15 (b) (b)
$OpTx$FX_DC$40 2 0 0 3 FB16_16 (b) (b)
$OpTx$FX_DC$39 2 0 0 3 FB16_17 (b) (b)
$OpTx$FX_DC$38 2 0 0 3 FB16_18 (b) (b)
Signals Used by Logic in Function Block
1: A<16> 9: C1 17: LAN_BASEADR<6>
2: A<17> 10: C3 18: LAN_BASEADR<7>
3: A<18> 11: LAN_BASEADR<0> 19: LAN_RST_SM_FSM_FFd4
4: A<19> 12: LAN_BASEADR<1> 20: LAN_RST_SM_FSM_FFd7
5: A<20> 13: LAN_BASEADR<2> 21: RESET
6: A<21> 14: LAN_BASEADR<3> 22: SET_FREQUENCY
7: A<22> 15: LAN_BASEADR<4> 23: lan_adr
8: A<23> 16: LAN_BASEADR<5> 24: lan_adr_sw
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
D_OUT_and0001/D_OUT_and0001_D2
......................XX................ 2
lan_adr_sw/lan_adr_sw_CLKF
........XX.............................. 2
LAN_RST_SM_FSM_FFd6 ...................XXX.................. 3
LAN_RST_SM_FSM_FFd3 ..................X.XX.................. 3
MTACK ........................................ 0
$OpTx$FX_DC$45 .......X.........X...................... 2
$OpTx$FX_DC$44 ......X.........X....................... 2
$OpTx$FX_DC$43 .....X.........X........................ 2
$OpTx$FX_DC$42 ....X.........X......................... 2
$OpTx$FX_DC$41 ...X.........X.......................... 2
$OpTx$FX_DC$40 ..X.........X........................... 2
$OpTx$FX_DC$39 .X.........X............................ 2
$OpTx$FX_DC$38 X.........X............................. 2
0----+----1----+----2----+----3----+----4
0 0 0 0
******************************* Equations ********************************
********** Mapped Logic **********
$OpTx$FX_DC$1 <= (CP_CS AND NOT D_OUT_and0001/D_OUT_and0001_D2);
$OpTx$FX_DC$19 <= (UDS AND LDS);
$OpTx$FX_DC$3 <= (CP_CS AND D_OUT_and0001/D_OUT_and0001_D2);
$OpTx$FX_DC$30 <= (NOT AS AND NOT SET_FREQUENCY);
$OpTx$FX_DC$31 <= (NOT RW AND NOT A(5) AND NOT A(4) AND NOT A(1) AND A(6) AND A(3) AND
CFOUT AND
AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2);
$OpTx$FX_DC$34 <= (A(15) AND NOT RW AND NOT lan_adr AND NOT $OpTx$FX_DC$19);
$OpTx$FX_DC$38 <= A(16)
XOR
$OpTx$FX_DC$38 <= LAN_BASEADR(0);
$OpTx$FX_DC$39 <= A(17)
XOR
$OpTx$FX_DC$39 <= LAN_BASEADR(1);
$OpTx$FX_DC$40 <= A(18)
XOR
$OpTx$FX_DC$40 <= LAN_BASEADR(2);
$OpTx$FX_DC$41 <= A(19)
XOR
$OpTx$FX_DC$41 <= LAN_BASEADR(3);
$OpTx$FX_DC$42 <= A(20)
XOR
$OpTx$FX_DC$42 <= LAN_BASEADR(4);
$OpTx$FX_DC$43 <= A(21)
XOR
$OpTx$FX_DC$43 <= LAN_BASEADR(5);
$OpTx$FX_DC$44 <= A(22)
XOR
$OpTx$FX_DC$44 <= LAN_BASEADR(6);
$OpTx$FX_DC$45 <= A(23)
XOR
$OpTx$FX_DC$45 <= LAN_BASEADR(7);
$OpTx$FX_SC$321 <= (CP_CS AND lan_adr AND ide AND NOT SET_FREQUENCY);
$OpTx$FX_SC$52 <= ((NOT CP_CS AND NOT D_OUT_and0001/D_OUT_and0001_D2)
OR (lan_adr AND ide AND NOT D_OUT_and0001/D_OUT_and0001_D2));
FDCPE_AS_D: FDCPE port map (AS_D,AS_D_D,lan_adr_sw/lan_adr_sw_CLKF,'0','0');
AS_D_D <= (NOT AS AND RESET);
FDCPE_AUTO_CONFIG_DONE0: FDCPE port map (AUTO_CONFIG_DONE(0),AUTO_CONFIG_DONE_CYCLE(0),NOT lan_adr_sw/lan_adr_sw_CLKF,'0',NOT RESET,AS);
FDCPE_AUTO_CONFIG_DONE1: FDCPE port map (AUTO_CONFIG_DONE(1),AUTO_CONFIG_DONE_CYCLE(1),NOT lan_adr_sw/lan_adr_sw_CLKF,'0',NOT RESET,AS);
FDCPE_AUTO_CONFIG_DONE_CYCLE0: FDCPE port map (AUTO_CONFIG_DONE_CYCLE(0),AUTO_CONFIG_DONE_CYCLE_D(0),NOT lan_adr_sw/lan_adr_sw_CLKF,'0',NOT RESET);
AUTO_CONFIG_DONE_CYCLE_D(0) <= ((AUTO_CONFIG_DONE_CYCLE(0) AND NOT $OpTx$FX_DC$31)
OR (NOT AUTO_CONFIG_DONE(0) AND IDE_OFF AND $OpTx$FX_DC$31)
OR (NOT AUTO_CONFIG_DONE(0) AND NOT RW AND NOT A(5) AND NOT A(4) AND A(2) AND
NOT A(1) AND A(6) AND A(3) AND
AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2));
FDCPE_AUTO_CONFIG_DONE_CYCLE1: FDCPE port map (AUTO_CONFIG_DONE_CYCLE(1),AUTO_CONFIG_DONE_CYCLE_D(1),NOT lan_adr_sw/lan_adr_sw_CLKF,'0',NOT RESET);
AUTO_CONFIG_DONE_CYCLE_D(1) <= ((AUTO_CONFIG_DONE_CYCLE(1) AND NOT $OpTx$FX_DC$31)
OR (AUTO_CONFIG_DONE(1) AND AUTO_CONFIG_DONE(0) AND NOT RW AND
NOT A(5) AND NOT A(4) AND NOT A(1) AND A(6) AND A(3) AND
AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2)
OR (NOT AUTO_CONFIG_DONE(1) AND NOT AUTO_CONFIG_DONE(0) AND NOT RW AND
NOT A(5) AND NOT A(4) AND A(2) AND NOT A(1) AND A(6) AND A(3) AND
AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2));
AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2 <= (NOT AS AND NOT autoconfig AND NOT $OpTx$FX_DC$19);
FDCPE_A_LAN0: FDCPE port map (A_LAN(0),A_LAN_D(0),NOT CLK_EXT,'0','0');
A_LAN_D(0) <= ((NOT CP_CS)
OR (NOT A(1) AND NOT lan_adr)
OR (lan_adr AND NOT A_LAN(0) AND NOT SET_FREQUENCY));
FDCPE_A_LAN1: FDCPE port map (A_LAN(1),A_LAN_D(1),NOT CLK_EXT,'0','0');
A_LAN_D(1) <= ((NOT CP_CS)
OR (NOT A(2) AND NOT lan_adr)
OR (lan_adr AND NOT A_LAN(1) AND NOT SET_FREQUENCY));
FDCPE_A_LAN2: FDCPE port map (A_LAN(2),A_LAN_D(2),NOT CLK_EXT,'0','0');
A_LAN_D(2) <= ((NOT A(1) AND NOT CP_CS)
OR (NOT A(3) AND CP_CS AND NOT lan_adr)
OR (CP_CS AND lan_adr AND NOT A_LAN(2) AND NOT SET_FREQUENCY));
FDCPE_A_LAN3: FDCPE port map (A_LAN(3),A_LAN_D(3),NOT CLK_EXT,'0','0');
A_LAN_D(3) <= ((A(2) AND NOT CP_CS)
OR (A(4) AND CP_CS AND NOT lan_adr)
OR (CP_CS AND lan_adr AND A_LAN(3) AND NOT SET_FREQUENCY));
FDCPE_A_LAN4: FDCPE port map (A_LAN(4),A_LAN_D(4),NOT CLK_EXT,'0','0');
A_LAN_D(4) <= ((NOT A(3) AND NOT CP_CS)
OR (NOT A(5) AND CP_CS AND NOT lan_adr)
OR (CP_CS AND lan_adr AND NOT A_LAN(4) AND NOT SET_FREQUENCY));
FDCPE_A_LAN5: FDCPE port map (A_LAN(5),A_LAN_D(5),NOT CLK_EXT,'0','0');
A_LAN_D(5) <= ((NOT A(4) AND NOT CP_CS)
OR (NOT A(6) AND CP_CS AND NOT lan_adr)
OR (CP_CS AND lan_adr AND NOT A_LAN(5) AND NOT SET_FREQUENCY));
FDCPE_A_LAN6: FDCPE port map (A_LAN(6),A_LAN_D(6),NOT CLK_EXT,'0','0');
A_LAN_D(6) <= ((A(5) AND NOT CP_CS)
OR (CP_CS AND NOT lan_adr AND A(7))
OR (CP_CS AND lan_adr AND A_LAN(6) AND NOT SET_FREQUENCY)
OR (CP_CS AND lan_adr AND SET_FREQUENCY AND
CLEAR_REGISTER));
FDCPE_A_LAN7: FDCPE port map (A_LAN(7),A_LAN_D(7),NOT CLK_EXT,'0','0');
A_LAN_D(7) <= ((NOT A(6) AND NOT CP_CS)
OR (CP_CS AND NOT lan_adr AND NOT A(8))
OR (CP_CS AND lan_adr AND NOT A_LAN(7) AND NOT SET_FREQUENCY));
FDCPE_A_LAN8: FDCPE port map (A_LAN(8),A_LAN_D(8),NOT CLK_EXT,'0','0');
A_LAN_D(8) <= ((NOT CP_CS AND NOT A(7))
OR (CP_CS AND NOT lan_adr AND NOT A(9))
OR (CP_CS AND lan_adr AND NOT A_LAN(8) AND NOT SET_FREQUENCY));
FDCPE_A_LAN9: FDCPE port map (A_LAN(9),A_LAN_D(9),NOT CLK_EXT,'0','0');
A_LAN_D(9) <= ((NOT CP_CS AND NOT A(8))
OR (CP_CS AND NOT lan_adr AND NOT A(10))
OR (CP_CS AND lan_adr AND NOT A_LAN(9) AND NOT SET_FREQUENCY));
FDCPE_A_LAN10: FDCPE port map (A_LAN(10),A_LAN_D(10),NOT CLK_EXT,'0','0');
A_LAN_D(10) <= ((NOT CP_CS AND NOT A(9))
OR (CP_CS AND NOT lan_adr AND NOT A(11))
OR (CP_CS AND lan_adr AND NOT A_LAN(10) AND NOT SET_FREQUENCY));
FDCPE_A_LAN11: FDCPE port map (A_LAN(11),A_LAN_D(11),NOT CLK_EXT,'0','0');
A_LAN_D(11) <= ((NOT CP_CS AND NOT A(10))
OR (CP_CS AND NOT lan_adr AND NOT A(12))
OR (CP_CS AND lan_adr AND NOT A_LAN(11) AND NOT SET_FREQUENCY));
FDCPE_A_LAN12: FDCPE port map (A_LAN(12),A_LAN_D(12),NOT CLK_EXT,'0','0');
A_LAN_D(12) <= ((NOT CP_CS AND NOT A(11))
OR (CP_CS AND NOT lan_adr AND NOT A(13))
OR (CP_CS AND lan_adr AND NOT A_LAN(12) AND NOT SET_FREQUENCY));
FDCPE_A_LAN13: FDCPE port map (A_LAN(13),A_LAN_D(13),NOT CLK_EXT,'0','0');
A_LAN_D(13) <= ((NOT CP_CS AND NOT A(12))
OR (CP_CS AND NOT lan_adr AND NOT A(14))
OR (CP_CS AND lan_adr AND NOT A_LAN(13) AND NOT SET_FREQUENCY));
BUF_D_IN(12) <= (($OpTx$FX_SC$321)
OR (D(12).PIN AND NOT SET_FREQUENCY AND
NOT D_OUT_and0001/D_OUT_and0001_D2)
OR (NOT SET_FREQUENCY AND D(4).PIN AND
D_OUT_and0001/D_OUT_and0001_D2));
BUF_D_IN(13) <= (($OpTx$FX_SC$321)
OR (D(13).PIN AND NOT SET_FREQUENCY AND
NOT D_OUT_and0001/D_OUT_and0001_D2)
OR (NOT SET_FREQUENCY AND D(5).PIN AND
D_OUT_and0001/D_OUT_and0001_D2));
BUF_D_IN(14) <= (($OpTx$FX_SC$321)
OR (D(14).PIN AND NOT SET_FREQUENCY AND
NOT D_OUT_and0001/D_OUT_and0001_D2)
OR (NOT SET_FREQUENCY AND D(6).PIN AND
D_OUT_and0001/D_OUT_and0001_D2));
BUF_D_IN(15) <= (($OpTx$FX_SC$321)
OR (D(15).PIN AND NOT SET_FREQUENCY AND
NOT D_OUT_and0001/D_OUT_and0001_D2)
OR (NOT SET_FREQUENCY AND D(7).PIN AND
D_OUT_and0001/D_OUT_and0001_D2));
CFOUT <= NOT ((NOT AUTO_CONFIG_DONE(1) AND NOT AUTO_CONFIG_DONE(0)));
FDCPE_CLEAR_REGISTER: FDCPE port map (CLEAR_REGISTER,CLEAR_REGISTER_D,CLK_EXT,'0','0');
CLEAR_REGISTER_D <= ((NOT LAN_RST_SM_FSM_FFd5 AND CLEAR_REGISTER)
OR (NOT RESET AND SET_FREQUENCY AND CLEAR_REGISTER));
FDCPE_CP_BASEADR0: FDCPE port map (CP_BASEADR(0),CP_BASEADR_D(0),NOT lan_adr_sw/lan_adr_sw_CLKF,'0',NOT RESET);
CP_BASEADR_D(0) <= ((D(8).PIN AND
CP_BASEADR_not0001/CP_BASEADR_not0001_D2)
OR (CP_BASEADR(0) AND
NOT CP_BASEADR_not0001/CP_BASEADR_not0001_D2));
FDCPE_CP_BASEADR1: FDCPE port map (CP_BASEADR(1),CP_BASEADR_D(1),NOT lan_adr_sw/lan_adr_sw_CLKF,'0',NOT RESET);
CP_BASEADR_D(1) <= ((D(9).PIN AND
CP_BASEADR_not0001/CP_BASEADR_not0001_D2)
OR (CP_BASEADR(1) AND
NOT CP_BASEADR_not0001/CP_BASEADR_not0001_D2));
FDCPE_CP_BASEADR2: FDCPE port map (CP_BASEADR(2),CP_BASEADR_D(2),NOT lan_adr_sw/lan_adr_sw_CLKF,'0',NOT RESET);
CP_BASEADR_D(2) <= ((D(10).PIN AND
CP_BASEADR_not0001/CP_BASEADR_not0001_D2)
OR (CP_BASEADR(2) AND
NOT CP_BASEADR_not0001/CP_BASEADR_not0001_D2));
FDCPE_CP_BASEADR3: FDCPE port map (CP_BASEADR(3),CP_BASEADR_D(3),NOT lan_adr_sw/lan_adr_sw_CLKF,'0',NOT RESET);
CP_BASEADR_D(3) <= ((D(11).PIN AND
CP_BASEADR_not0001/CP_BASEADR_not0001_D2)
OR (CP_BASEADR(3) AND
NOT CP_BASEADR_not0001/CP_BASEADR_not0001_D2));
FDCPE_CP_BASEADR4: FDCPE port map (CP_BASEADR(4),CP_BASEADR_D(4),NOT lan_adr_sw/lan_adr_sw_CLKF,'0',NOT RESET);
CP_BASEADR_D(4) <= ((D(12).PIN AND
CP_BASEADR_not0001/CP_BASEADR_not0001_D2)
OR (CP_BASEADR(4) AND
NOT CP_BASEADR_not0001/CP_BASEADR_not0001_D2));
FDCPE_CP_BASEADR5: FDCPE port map (CP_BASEADR(5),CP_BASEADR_D(5),NOT lan_adr_sw/lan_adr_sw_CLKF,'0',NOT RESET);
CP_BASEADR_D(5) <= ((D(13).PIN AND
CP_BASEADR_not0001/CP_BASEADR_not0001_D2)
OR (CP_BASEADR(5) AND
NOT CP_BASEADR_not0001/CP_BASEADR_not0001_D2));
FDCPE_CP_BASEADR6: FDCPE port map (CP_BASEADR(6),CP_BASEADR_D(6),NOT lan_adr_sw/lan_adr_sw_CLKF,'0',NOT RESET);
CP_BASEADR_D(6) <= ((D(14).PIN AND
CP_BASEADR_not0001/CP_BASEADR_not0001_D2)
OR (CP_BASEADR(6) AND
NOT CP_BASEADR_not0001/CP_BASEADR_not0001_D2));
FDCPE_CP_BASEADR7: FDCPE port map (CP_BASEADR(7),CP_BASEADR_D(7),NOT lan_adr_sw/lan_adr_sw_CLKF,'0',NOT RESET);
CP_BASEADR_D(7) <= ((D(15).PIN AND
CP_BASEADR_not0001/CP_BASEADR_not0001_D2)
OR (CP_BASEADR(7) AND
NOT CP_BASEADR_not0001/CP_BASEADR_not0001_D2));
CP_BASEADR_not0001/CP_BASEADR_not0001_D2 <= (AUTO_CONFIG_DONE(1) AND NOT AUTO_CONFIG_DONE(0) AND NOT RW AND
NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND A(6) AND A(3) AND
AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2);
FDCPE_CP_CS: FDCPE port map (CP_CS,CP_CS_D,lan_adr_sw/lan_adr_sw_CLKF,'0',NOT RESET);
CP_CS_D <= ((SHUT_UP(1))
OR (CP_BASEADR(0) AND NOT A(16))
OR (NOT CP_BASEADR(0) AND A(16))
OR (CP_BASEADR(1) AND NOT A(17))
OR (NOT CP_BASEADR(1) AND A(17))
OR (NOT CP_BASEADR(2) AND A(18))
OR (EXP25_.EXP)
OR (CP_BASEADR(2) AND NOT A(18))
OR (CP_BASEADR(3) AND NOT A(19))
OR (NOT CP_BASEADR(3) AND A(19))
OR (CP_BASEADR(4) AND NOT A(20))
OR (NOT CP_BASEADR(4) AND A(20))
OR (CP_BASEADR(6) AND NOT A(22))
OR (NOT CP_BASEADR(6) AND A(22)));
CP_RD <= ((CP_RD_S)
OR (AS AND AS_D));
FDCPE_CP_RD_S: FDCPE port map (CP_RD_S,CP_RD_S_D,NOT lan_adr_sw/lan_adr_sw_CLKF,'0',NOT RESET);
CP_RD_S_D <= (NOT AS AND RW AND NOT CP_CS);
CP_WE <= NOT ((NOT AS AND NOT CP_WE_S AND CP_WE_QUIRK));
FDCPE_CP_WE_QUIRK: FDCPE port map (CP_WE_QUIRK,CP_WE_S,NOT lan_adr_sw/lan_adr_sw_CLKF,'0',NOT RESET);
FDCPE_CP_WE_S: FDCPE port map (CP_WE_S,CP_WE_S_D,NOT lan_adr_sw/lan_adr_sw_CLKF,'0',NOT RESET);
CP_WE_S_D <= (NOT RW AND NOT CP_CS AND NOT $OpTx$FX_DC$19);
FDCPE_D0: FDCPE port map (D_I(0),D(0),NOT CLK_EXT,'0','0');
D(0) <= ((NOT D(0) AND D_OUT_or0002/D_OUT_or0002_D2)
OR (autoconfig AND NOT DQ(8).PIN AND
NOT D_OUT_or0002/D_OUT_or0002_D2 AND $OpTx$FX_DC$3)
OR (autoconfig AND NOT DQ(0).PIN AND
NOT D_OUT_or0002/D_OUT_or0002_D2 AND NOT $OpTx$FX_DC$3));
D(0) <= D_I(0) when D_OE(0) = '1' else 'Z';
D_OE(0) <= (RW AND NOT SLAVE);
FDCPE_D1: FDCPE port map (D_I(1),D(1),NOT CLK_EXT,'0','0');
D(1) <= ((NOT D(1) AND D_OUT_or0002/D_OUT_or0002_D2)
OR (autoconfig AND NOT DQ(9).PIN AND
NOT D_OUT_or0002/D_OUT_or0002_D2 AND $OpTx$FX_DC$3)
OR (autoconfig AND NOT DQ(1).PIN AND
NOT D_OUT_or0002/D_OUT_or0002_D2 AND NOT $OpTx$FX_DC$3));
D(1) <= D_I(1) when D_OE(1) = '1' else 'Z';
D_OE(1) <= (RW AND NOT SLAVE);
FDCPE_D2: FDCPE port map (D_I(2),D(2),NOT CLK_EXT,'0','0');
D(2) <= ((NOT D(2) AND D_OUT_or0002/D_OUT_or0002_D2)
OR (autoconfig AND NOT DQ(10).PIN AND
NOT D_OUT_or0002/D_OUT_or0002_D2 AND $OpTx$FX_DC$3)
OR (autoconfig AND NOT DQ(2).PIN AND
NOT D_OUT_or0002/D_OUT_or0002_D2 AND NOT $OpTx$FX_DC$3));
D(2) <= D_I(2) when D_OE(2) = '1' else 'Z';
D_OE(2) <= (RW AND NOT SLAVE);
FDCPE_D3: FDCPE port map (D_I(3),D(3),NOT CLK_EXT,'0','0');
D(3) <= ((NOT D(3) AND D_OUT_or0002/D_OUT_or0002_D2)
OR (autoconfig AND NOT DQ(11).PIN AND
NOT D_OUT_or0002/D_OUT_or0002_D2 AND $OpTx$FX_DC$3)
OR (autoconfig AND NOT DQ(3).PIN AND
NOT D_OUT_or0002/D_OUT_or0002_D2 AND NOT $OpTx$FX_DC$3));
D(3) <= D_I(3) when D_OE(3) = '1' else 'Z';
D_OE(3) <= (RW AND NOT SLAVE);
FDCPE_D4: FDCPE port map (D_I(4),D(4),NOT CLK_EXT,'0','0');
D(4) <= ((NOT D(4) AND D_OUT_or0002/D_OUT_or0002_D2)
OR (autoconfig AND NOT DQ(12).PIN AND
NOT D_OUT_or0002/D_OUT_or0002_D2 AND $OpTx$FX_DC$3)
OR (autoconfig AND NOT DQ(4).PIN AND
NOT D_OUT_or0002/D_OUT_or0002_D2 AND NOT $OpTx$FX_DC$3));
D(4) <= D_I(4) when D_OE(4) = '1' else 'Z';
D_OE(4) <= (RW AND NOT SLAVE);
FDCPE_D5: FDCPE port map (D_I(5),D(5),NOT CLK_EXT,'0','0');
D(5) <= ((NOT D(5) AND D_OUT_or0002/D_OUT_or0002_D2)
OR (autoconfig AND NOT DQ(13).PIN AND
NOT D_OUT_or0002/D_OUT_or0002_D2 AND $OpTx$FX_DC$3)
OR (autoconfig AND NOT DQ(5).PIN AND
NOT D_OUT_or0002/D_OUT_or0002_D2 AND NOT $OpTx$FX_DC$3));
D(5) <= D_I(5) when D_OE(5) = '1' else 'Z';
D_OE(5) <= (RW AND NOT SLAVE);
FDCPE_D6: FDCPE port map (D_I(6),D(6),NOT CLK_EXT,'0','0');
D(6) <= ((NOT D(6) AND D_OUT_or0002/D_OUT_or0002_D2)
OR (autoconfig AND NOT DQ(14).PIN AND
NOT D_OUT_or0002/D_OUT_or0002_D2 AND $OpTx$FX_DC$3)
OR (autoconfig AND NOT DQ(6).PIN AND
NOT D_OUT_or0002/D_OUT_or0002_D2 AND NOT $OpTx$FX_DC$3));
D(6) <= D_I(6) when D_OE(6) = '1' else 'Z';
D_OE(6) <= (RW AND NOT SLAVE);
FDCPE_D7: FDCPE port map (D_I(7),D(7),NOT CLK_EXT,'0','0');
D(7) <= ((NOT D(7) AND D_OUT_or0002/D_OUT_or0002_D2)
OR (autoconfig AND NOT DQ(15).PIN AND
NOT D_OUT_or0002/D_OUT_or0002_D2 AND $OpTx$FX_DC$3)
OR (autoconfig AND NOT DQ(7).PIN AND
NOT D_OUT_or0002/D_OUT_or0002_D2 AND NOT $OpTx$FX_DC$3));
D(7) <= D_I(7) when D_OE(7) = '1' else 'Z';
D_OE(7) <= (RW AND NOT SLAVE);
FDCPE_D8: FDCPE port map (D_I(8),D(8),NOT CLK_EXT,'0','0');
D(8) <= ((NOT D(8) AND D_OUT_or0002/D_OUT_or0002_D2)
OR (autoconfig AND NOT DQ(8).PIN AND
NOT D_OUT_or0002/D_OUT_or0002_D2 AND $OpTx$FX_DC$1)
OR (autoconfig AND NOT DQ(0).PIN AND
NOT D_OUT_or0002/D_OUT_or0002_D2 AND NOT $OpTx$FX_DC$1));
D(8) <= D_I(8) when D_OE(8) = '1' else 'Z';
D_OE(8) <= (RW AND NOT SLAVE);
FDCPE_D9: FDCPE port map (D_I(9),D(9),NOT CLK_EXT,'0','0');
D(9) <= ((NOT D(9) AND D_OUT_or0002/D_OUT_or0002_D2)
OR (autoconfig AND NOT DQ(9).PIN AND
NOT D_OUT_or0002/D_OUT_or0002_D2 AND $OpTx$FX_DC$1)
OR (autoconfig AND NOT DQ(1).PIN AND
NOT D_OUT_or0002/D_OUT_or0002_D2 AND NOT $OpTx$FX_DC$1));
D(9) <= D_I(9) when D_OE(9) = '1' else 'Z';
D_OE(9) <= (RW AND NOT SLAVE);
FDCPE_D10: FDCPE port map (D_I(10),D(10),NOT CLK_EXT,'0','0');
D(10) <= ((NOT D(10) AND D_OUT_or0002/D_OUT_or0002_D2)
OR (autoconfig AND NOT DQ(10).PIN AND
NOT D_OUT_or0002/D_OUT_or0002_D2 AND $OpTx$FX_DC$1)
OR (autoconfig AND NOT DQ(2).PIN AND
NOT D_OUT_or0002/D_OUT_or0002_D2 AND NOT $OpTx$FX_DC$1));
D(10) <= D_I(10) when D_OE(10) = '1' else 'Z';
D_OE(10) <= (RW AND NOT SLAVE);
FDCPE_D11: FDCPE port map (D_I(11),D(11),NOT CLK_EXT,'0','0');
D(11) <= ((NOT D(11) AND D_OUT_or0002/D_OUT_or0002_D2)
OR (autoconfig AND NOT DQ(11).PIN AND
NOT D_OUT_or0002/D_OUT_or0002_D2 AND $OpTx$FX_DC$1)
OR (autoconfig AND NOT DQ(3).PIN AND
NOT D_OUT_or0002/D_OUT_or0002_D2 AND NOT $OpTx$FX_DC$1));
D(11) <= D_I(11) when D_OE(11) = '1' else 'Z';
D_OE(11) <= (RW AND NOT SLAVE);
FDCPE_D12: FDCPE port map (D_I(12),D(12),NOT CLK_EXT,'0','0');
D(12) <= ((D(12) AND D_OUT_or0002/D_OUT_or0002_D2)
OR (Dout1(0) AND NOT autoconfig AND
NOT D_OUT_or0002/D_OUT_or0002_D2)
OR (autoconfig AND DQ(12).PIN AND
NOT D_OUT_or0002/D_OUT_or0002_D2 AND $OpTx$FX_DC$1)
OR (autoconfig AND DQ(4).PIN AND
NOT D_OUT_or0002/D_OUT_or0002_D2 AND NOT $OpTx$FX_DC$1));
D(12) <= D_I(12) when D_OE(12) = '1' else 'Z';
D_OE(12) <= (RW AND NOT SLAVE);
FDCPE_D13: FDCPE port map (D_I(13),D(13),NOT CLK_EXT,'0','0');
D(13) <= ((D(13) AND D_OUT_or0002/D_OUT_or0002_D2)
OR (Dout1(1) AND NOT autoconfig AND
NOT D_OUT_or0002/D_OUT_or0002_D2)
OR (autoconfig AND DQ(13).PIN AND
NOT D_OUT_or0002/D_OUT_or0002_D2 AND $OpTx$FX_DC$1)
OR (autoconfig AND DQ(5).PIN AND
NOT D_OUT_or0002/D_OUT_or0002_D2 AND NOT $OpTx$FX_DC$1));
D(13) <= D_I(13) when D_OE(13) = '1' else 'Z';
D_OE(13) <= (RW AND NOT SLAVE);
FDCPE_D14: FDCPE port map (D_I(14),D(14),NOT CLK_EXT,'0','0');
D(14) <= ((D(14) AND D_OUT_or0002/D_OUT_or0002_D2)
OR (Dout1(2) AND NOT autoconfig AND
NOT D_OUT_or0002/D_OUT_or0002_D2)
OR (autoconfig AND DQ(14).PIN AND
NOT D_OUT_or0002/D_OUT_or0002_D2 AND $OpTx$FX_DC$1)
OR (autoconfig AND DQ(6).PIN AND
NOT D_OUT_or0002/D_OUT_or0002_D2 AND NOT $OpTx$FX_DC$1));
D(14) <= D_I(14) when D_OE(14) = '1' else 'Z';
D_OE(14) <= (RW AND NOT SLAVE);
FDCPE_D15: FDCPE port map (D_I(15),D(15),NOT CLK_EXT,'0','0');
D(15) <= ((D(15) AND D_OUT_or0002/D_OUT_or0002_D2)
OR (Dout1(3) AND NOT autoconfig AND
NOT D_OUT_or0002/D_OUT_or0002_D2)
OR (autoconfig AND DQ(15).PIN AND
NOT D_OUT_or0002/D_OUT_or0002_D2 AND $OpTx$FX_DC$1)
OR (autoconfig AND DQ(7).PIN AND
NOT D_OUT_or0002/D_OUT_or0002_D2 AND NOT $OpTx$FX_DC$1));
D(15) <= D_I(15) when D_OE(15) = '1' else 'Z';
D_OE(15) <= (RW AND NOT SLAVE);
DQ_I(0) <= NOT ((NOT D_IN(0) AND NOT DQ_or0001/DQ_or0001_D2));
DQ(0) <= DQ_I(0) when DQ_OE(0) = '1' else 'Z';
DQ_OE(0) <= DQ_9_IOBUFE/DQ_9_IOBUFE_TRST;
DQ_I(1) <= NOT ((NOT D_IN(1) AND NOT DQ_or0001/DQ_or0001_D2));
DQ(1) <= DQ_I(1) when DQ_OE(1) = '1' else 'Z';
DQ_OE(1) <= DQ_9_IOBUFE/DQ_9_IOBUFE_TRST;
DQ_I(2) <= NOT ((NOT D_IN(2) AND NOT DQ_or0001/DQ_or0001_D2));
DQ(2) <= DQ_I(2) when DQ_OE(2) = '1' else 'Z';
DQ_OE(2) <= DQ_9_IOBUFE/DQ_9_IOBUFE_TRST;
DQ_I(3) <= NOT ((NOT D_IN(3) AND NOT DQ_or0001/DQ_or0001_D2));
DQ(3) <= DQ_I(3) when DQ_OE(3) = '1' else 'Z';
DQ_OE(3) <= DQ_9_IOBUFE/DQ_9_IOBUFE_TRST;
DQ_I(4) <= NOT ((NOT D_IN(4) AND NOT DQ_or0001/DQ_or0001_D2));
DQ(4) <= DQ_I(4) when DQ_OE(4) = '1' else 'Z';
DQ_OE(4) <= DQ_9_IOBUFE/DQ_9_IOBUFE_TRST;
DQ_I(5) <= NOT ((NOT D_IN(5) AND NOT DQ_or0001/DQ_or0001_D2));
DQ(5) <= DQ_I(5) when DQ_OE(5) = '1' else 'Z';
DQ_OE(5) <= DQ_9_IOBUFE/DQ_9_IOBUFE_TRST;
DQ_I(6) <= NOT ((NOT D_IN(6) AND NOT DQ_or0001/DQ_or0001_D2));
DQ(6) <= DQ_I(6) when DQ_OE(6) = '1' else 'Z';
DQ_OE(6) <= DQ_9_IOBUFE/DQ_9_IOBUFE_TRST;
DQ_I(7) <= NOT ((NOT D_IN(7) AND NOT DQ_or0001/DQ_or0001_D2));
DQ(7) <= DQ_I(7) when DQ_OE(7) = '1' else 'Z';
DQ_OE(7) <= DQ_9_IOBUFE/DQ_9_IOBUFE_TRST;
DQ_I(8) <= NOT ((NOT D_IN(8) AND NOT DQ_or0001/DQ_or0001_D2));
DQ(8) <= DQ_I(8) when DQ_OE(8) = '1' else 'Z';
DQ_OE(8) <= DQ_9_IOBUFE/DQ_9_IOBUFE_TRST;
DQ_I(9) <= NOT ((NOT D_IN(9) AND NOT DQ_or0001/DQ_or0001_D2));
DQ(9) <= DQ_I(9) when DQ_OE(9) = '1' else 'Z';
DQ_OE(9) <= DQ_9_IOBUFE/DQ_9_IOBUFE_TRST;
DQ_I(10) <= NOT ((NOT D_IN(10) AND NOT DQ_or0001/DQ_or0001_D2));
DQ(10) <= DQ_I(10) when DQ_OE(10) = '1' else 'Z';
DQ_OE(10) <= DQ_9_IOBUFE/DQ_9_IOBUFE_TRST;
DQ_I(11) <= NOT ((NOT D_IN(11) AND NOT DQ_or0001/DQ_or0001_D2));
DQ(11) <= DQ_I(11) when DQ_OE(11) = '1' else 'Z';
DQ_OE(11) <= DQ_9_IOBUFE/DQ_9_IOBUFE_TRST;
DQ_I(12) <= NOT ((NOT D_IN(12) AND NOT DQ_or0001/DQ_or0001_D2));
DQ(12) <= DQ_I(12) when DQ_OE(12) = '1' else 'Z';
DQ_OE(12) <= DQ_9_IOBUFE/DQ_9_IOBUFE_TRST;
DQ_I(13) <= NOT ((NOT D_IN(13) AND NOT DQ_or0001/DQ_or0001_D2));
DQ(13) <= DQ_I(13) when DQ_OE(13) = '1' else 'Z';
DQ_OE(13) <= DQ_9_IOBUFE/DQ_9_IOBUFE_TRST;
DQ_I(14) <= NOT ((NOT D_IN(14) AND NOT DQ_or0001/DQ_or0001_D2));
DQ(14) <= DQ_I(14) when DQ_OE(14) = '1' else 'Z';
DQ_OE(14) <= DQ_9_IOBUFE/DQ_9_IOBUFE_TRST;
DQ_I(15) <= NOT ((NOT D_IN(15) AND NOT DQ_or0001/DQ_or0001_D2));
DQ(15) <= DQ_I(15) when DQ_OE(15) = '1' else 'Z';
DQ_OE(15) <= DQ_9_IOBUFE/DQ_9_IOBUFE_TRST;
DQ_9_IOBUFE/DQ_9_IOBUFE_TRST <= ((NOT DQ_or0001/DQ_or0001_D2)
OR (AS AND RW AND NOT ide));
DQ_or0001/DQ_or0001_D2 <= ((AS AND NOT SET_FREQUENCY)
OR (RW AND NOT SET_FREQUENCY)
OR (CP_CS AND lan_adr AND ide AND NOT SET_FREQUENCY));
DTACK_I <= '0';
DTACK <= DTACK_I when DTACK_OE = '1' else 'Z';
DTACK_OE <= '0';
FDCPE_D_IN0: FDCPE port map (D_IN(0),D_IN_D(0),NOT CLK_EXT,'0','0');
D_IN_D(0) <= ((D(8).PIN AND NOT SET_FREQUENCY AND NOT $OpTx$FX_DC$1)
OR (NOT SET_FREQUENCY AND D(0).PIN AND $OpTx$FX_DC$1)
OR (lan_adr AND ide AND NOT SET_FREQUENCY AND $OpTx$FX_DC$1));
FDCPE_D_IN1: FDCPE port map (D_IN(1),D_IN_D(1),NOT CLK_EXT,'0','0');
D_IN_D(1) <= ((D(9).PIN AND NOT SET_FREQUENCY AND NOT $OpTx$FX_DC$1)
OR (NOT SET_FREQUENCY AND D(1).PIN AND $OpTx$FX_DC$1)
OR (lan_adr AND ide AND NOT SET_FREQUENCY AND $OpTx$FX_DC$1));
FDCPE_D_IN2: FDCPE port map (D_IN(2),D_IN_D(2),NOT CLK_EXT,'0','0');
D_IN_D(2) <= ((D(10).PIN AND NOT SET_FREQUENCY AND NOT $OpTx$FX_DC$1)
OR (NOT SET_FREQUENCY AND D(2).PIN AND $OpTx$FX_DC$1)
OR (lan_adr AND ide AND NOT SET_FREQUENCY AND $OpTx$FX_DC$1));
FDCPE_D_IN3: FDCPE port map (D_IN(3),D_IN_D(3),NOT CLK_EXT,'0','0');
D_IN_D(3) <= ((D(11).PIN AND NOT SET_FREQUENCY AND NOT $OpTx$FX_DC$1)
OR (NOT SET_FREQUENCY AND D(3).PIN AND $OpTx$FX_DC$1)
OR (lan_adr AND ide AND NOT SET_FREQUENCY AND $OpTx$FX_DC$1));
FDCPE_D_IN4: FDCPE port map (D_IN(4),D_IN_D(4),NOT CLK_EXT,'0','0');
D_IN_D(4) <= ((SET_FREQUENCY AND NOT CLEAR_REGISTER)
OR (BUF_D_IN(12) AND $OpTx$FX_SC$52)
OR (D(12).PIN AND NOT SET_FREQUENCY AND
D_OUT_and0001/D_OUT_and0001_D2)
OR (NOT SET_FREQUENCY AND D(4).PIN AND $OpTx$FX_DC$1));
FDCPE_D_IN5: FDCPE port map (D_IN(5),D_IN_D(5),NOT CLK_EXT,'0','0');
D_IN_D(5) <= ((BUF_D_IN(13) AND $OpTx$FX_SC$52)
OR (D(13).PIN AND NOT SET_FREQUENCY AND
D_OUT_and0001/D_OUT_and0001_D2)
OR (NOT SET_FREQUENCY AND D(5).PIN AND $OpTx$FX_DC$1));
FDCPE_D_IN6: FDCPE port map (D_IN(6),D_IN_D(6),NOT CLK_EXT,'0','0');
D_IN_D(6) <= ((BUF_D_IN(14) AND $OpTx$FX_SC$52)
OR (D(14).PIN AND NOT SET_FREQUENCY AND
D_OUT_and0001/D_OUT_and0001_D2)
OR (NOT SET_FREQUENCY AND D(6).PIN AND $OpTx$FX_DC$1));
FDCPE_D_IN7: FDCPE port map (D_IN(7),D_IN_D(7),NOT CLK_EXT,'0','0');
D_IN_D(7) <= ((BUF_D_IN(15) AND $OpTx$FX_SC$52)
OR (D(15).PIN AND NOT SET_FREQUENCY AND
D_OUT_and0001/D_OUT_and0001_D2)
OR (NOT SET_FREQUENCY AND D(7).PIN AND $OpTx$FX_DC$1));
FDCPE_D_IN8: FDCPE port map (D_IN(8),D_IN_D(8),NOT CLK_EXT,'0','0');
D_IN_D(8) <= ((SET_FREQUENCY AND CLEAR_REGISTER AND NOT $OpTx$FX_SC$321)
OR (NOT D(8).PIN AND NOT SET_FREQUENCY AND
NOT D_OUT_and0001/D_OUT_and0001_D2 AND NOT $OpTx$FX_SC$321)
OR (NOT SET_FREQUENCY AND NOT D(0).PIN AND
D_OUT_and0001/D_OUT_and0001_D2 AND NOT $OpTx$FX_SC$321));
FDCPE_D_IN9: FDCPE port map (D_IN(9),D_IN_D(9),NOT CLK_EXT,'0','0');
D_IN_D(9) <= ((SET_FREQUENCY AND NOT CLEAR_REGISTER AND NOT $OpTx$FX_SC$321)
OR (NOT D(9).PIN AND NOT SET_FREQUENCY AND
NOT D_OUT_and0001/D_OUT_and0001_D2 AND NOT $OpTx$FX_SC$321)
OR (NOT SET_FREQUENCY AND NOT D(1).PIN AND
D_OUT_and0001/D_OUT_and0001_D2 AND NOT $OpTx$FX_SC$321));
FDCPE_D_IN10: FDCPE port map (D_IN(10),D_IN_D(10),NOT CLK_EXT,'0','0');
D_IN_D(10) <= ((SET_FREQUENCY AND NOT CLEAR_REGISTER AND NOT $OpTx$FX_SC$321)
OR (NOT D(10).PIN AND NOT SET_FREQUENCY AND
NOT D_OUT_and0001/D_OUT_and0001_D2 AND NOT $OpTx$FX_SC$321)
OR (NOT SET_FREQUENCY AND NOT D(2).PIN AND
D_OUT_and0001/D_OUT_and0001_D2 AND NOT $OpTx$FX_SC$321));
FDCPE_D_IN11: FDCPE port map (D_IN(11),D_IN_D(11),NOT CLK_EXT,'0','0');
D_IN_D(11) <= ((SET_FREQUENCY AND NOT CLEAR_REGISTER AND NOT $OpTx$FX_SC$321)
OR (NOT D(11).PIN AND NOT SET_FREQUENCY AND
NOT D_OUT_and0001/D_OUT_and0001_D2 AND NOT $OpTx$FX_SC$321)
OR (NOT SET_FREQUENCY AND NOT D(3).PIN AND
D_OUT_and0001/D_OUT_and0001_D2 AND NOT $OpTx$FX_SC$321));
FDCPE_D_IN12: FDCPE port map (D_IN(12),BUF_D_IN(12),NOT CLK_EXT,'0','0');
FDCPE_D_IN13: FDCPE port map (D_IN(13),BUF_D_IN(13),NOT CLK_EXT,'0','0');
FDCPE_D_IN14: FDCPE port map (D_IN(14),BUF_D_IN(14),NOT CLK_EXT,'0','0');
FDCPE_D_IN15: FDCPE port map (D_IN(15),BUF_D_IN(15),NOT CLK_EXT,'0','0');
D_OUT_and0001/D_OUT_and0001_D2 <= (NOT lan_adr AND NOT lan_adr_sw);
D_OUT_or0002/D_OUT_or0002_D2 <= (($OpTx$FX_DC$19)
OR (CP_CS AND autoconfig AND lan_adr AND ide));
FDCPE_Dout10: FDCPE port map (Dout1(0),Dout1_D(0),NOT lan_adr_sw/lan_adr_sw_CLKF,'0',NOT RESET);
Dout1_D(0) <= ((A(5) AND NOT A(4) AND A(2) AND A(1) AND NOT A(6) AND
AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2)
OR (A(5) AND NOT A(4) AND A(2) AND NOT A(6) AND NOT A(3) AND
AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2)
OR (NOT A(5) AND A(4) AND NOT A(2) AND NOT A(6) AND A(3) AND
AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2)
OR (NOT A(5) AND A(4) AND A(1) AND NOT A(6) AND A(3) AND
AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2)
OR (AUTO_CONFIG_DONE(1) AND AUTO_CONFIG_DONE(0) AND NOT A(4) AND
A(2) AND NOT A(6) AND NOT A(3) AND
AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2)
OR (AUTO_CONFIG_DONE(1) AND NOT A(5) AND A(2) AND NOT A(1) AND
NOT A(6) AND NOT A(3) AND
AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2)
OR (NOT Dout1(0) AND
NOT AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2)
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND A(6) AND NOT A(3) AND
AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2)
OR (AUTO_CONFIG_DONE(1) AND NOT A(5) AND NOT A(4) AND NOT A(2) AND
NOT A(1) AND NOT A(3) AND
AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2));
FDCPE_Dout11: FDCPE port map (Dout1(1),Dout1_D(1),NOT lan_adr_sw/lan_adr_sw_CLKF,'0',NOT RESET);
Dout1_D(1) <= ((NOT A(5) AND A(4) AND NOT A(1) AND NOT A(6) AND A(3) AND
AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2)
OR (AUTO_CONFIG_DONE(1) AND NOT A(5) AND NOT A(2) AND A(1) AND
NOT A(6) AND NOT A(3) AND
AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2)
OR (AUTO_CONFIG_DONE(1) AND NOT A(4) AND A(2) AND NOT A(1) AND
NOT A(6) AND NOT A(3) AND
AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2)
OR (A(5) AND NOT A(4) AND A(2) AND NOT A(1) AND NOT A(6) AND NOT A(3) AND
AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2)
OR (NOT AUTO_CONFIG_DONE(1) AND NOT A(5) AND A(4) AND A(2) AND
NOT A(1) AND NOT A(6) AND
AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2)
OR (NOT AUTO_CONFIG_DONE(1) AND NOT A(5) AND NOT A(4) AND A(1) AND
NOT A(6) AND NOT A(3) AND
AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2)
OR (AUTO_CONFIG_DONE(0) AND NOT A(5) AND NOT A(4) AND A(1) AND
NOT A(6) AND NOT A(3) AND
AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2)
OR (NOT Dout1(1) AND
NOT AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2)
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(3) AND
AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2)
OR (NOT A(5) AND A(4) AND A(2) AND NOT A(6) AND A(3) AND
AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2));
FDCPE_Dout12: FDCPE port map (Dout1(2),Dout1_D(2),NOT lan_adr_sw/lan_adr_sw_CLKF,'0',NOT RESET);
Dout1_D(2) <= ((NOT AUTO_CONFIG_DONE(1) AND NOT A(4) AND A(2) AND A(1) AND
NOT A(6) AND NOT A(3) AND
AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2)
OR (NOT A(5) AND A(4) AND A(2) AND A(1) AND NOT A(6) AND NOT A(3) AND
AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2)
OR (NOT A(5) AND A(4) AND A(2) AND NOT A(1) AND NOT A(6) AND A(3) AND
AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2)
OR (NOT AUTO_CONFIG_DONE(0) AND NOT A(4) AND A(2) AND A(1) AND
NOT A(6) AND NOT A(3) AND
AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2)
OR (A(5) AND NOT A(4) AND A(2) AND A(1) AND NOT A(6) AND NOT A(3) AND
AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2)
OR (AUTO_CONFIG_DONE(1) AND NOT A(5) AND NOT A(4) AND A(2) AND
NOT A(1) AND NOT A(6) AND NOT A(3) AND
AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2)
OR (NOT Dout1(2) AND
NOT AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2)
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND A(1) AND NOT A(3) AND
AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2)
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND A(6) AND NOT A(3) AND
AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2));
FDCPE_Dout13: FDCPE port map (Dout1(3),Dout1_D(3),NOT lan_adr_sw/lan_adr_sw_CLKF,'0',NOT RESET);
Dout1_D(3) <= ((NOT A(5) AND NOT A(4) AND NOT A(2) AND A(6) AND NOT A(3) AND
AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2)
OR (A(5) AND NOT A(4) AND A(2) AND NOT A(1) AND NOT A(6) AND NOT A(3) AND
AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2)
OR (NOT A(5) AND A(4) AND NOT A(2) AND NOT A(1) AND NOT A(6) AND A(3) AND
AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2)
OR (NOT A(5) AND A(4) AND A(2) AND A(1) AND NOT A(6) AND
AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2)
OR (NOT Dout1(3) AND
NOT AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2)
OR (AUTO_CONFIG_DONE(1) AND NOT A(5) AND A(1) AND NOT A(6) AND
NOT A(3) AND
AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2)
OR (NOT A(5) AND NOT A(2) AND A(1) AND NOT A(6) AND NOT A(3) AND
AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2));
IDE_A(0) <= A(9);
IDE_A(1) <= A(10);
IDE_A(2) <= A(11);
FDCPE_IDE_BASEADR0: FDCPE port map (IDE_BASEADR(0),IDE_BASEADR_D(0),NOT lan_adr_sw/lan_adr_sw_CLKF,'0',NOT RESET);
IDE_BASEADR_D(0) <= ((D(8).PIN AND
IDE_BASEADR_not0001/IDE_BASEADR_not0001_D2)
OR (IDE_BASEADR(0) AND
NOT IDE_BASEADR_not0001/IDE_BASEADR_not0001_D2));
FDCPE_IDE_BASEADR1: FDCPE port map (IDE_BASEADR(1),IDE_BASEADR_D(1),NOT lan_adr_sw/lan_adr_sw_CLKF,'0',NOT RESET);
IDE_BASEADR_D(1) <= ((D(9).PIN AND
IDE_BASEADR_not0001/IDE_BASEADR_not0001_D2)
OR (IDE_BASEADR(1) AND
NOT IDE_BASEADR_not0001/IDE_BASEADR_not0001_D2));
FDCPE_IDE_BASEADR2: FDCPE port map (IDE_BASEADR(2),IDE_BASEADR_D(2),NOT lan_adr_sw/lan_adr_sw_CLKF,'0',NOT RESET);
IDE_BASEADR_D(2) <= ((D(10).PIN AND
IDE_BASEADR_not0001/IDE_BASEADR_not0001_D2)
OR (IDE_BASEADR(2) AND
NOT IDE_BASEADR_not0001/IDE_BASEADR_not0001_D2));
FDCPE_IDE_BASEADR3: FDCPE port map (IDE_BASEADR(3),IDE_BASEADR_D(3),NOT lan_adr_sw/lan_adr_sw_CLKF,'0',NOT RESET);
IDE_BASEADR_D(3) <= ((D(11).PIN AND
IDE_BASEADR_not0001/IDE_BASEADR_not0001_D2)
OR (IDE_BASEADR(3) AND
NOT IDE_BASEADR_not0001/IDE_BASEADR_not0001_D2));
FDCPE_IDE_BASEADR4: FDCPE port map (IDE_BASEADR(4),IDE_BASEADR_D(4),NOT lan_adr_sw/lan_adr_sw_CLKF,'0',NOT RESET);
IDE_BASEADR_D(4) <= ((D(12).PIN AND
IDE_BASEADR_not0001/IDE_BASEADR_not0001_D2)
OR (IDE_BASEADR(4) AND
NOT IDE_BASEADR_not0001/IDE_BASEADR_not0001_D2));
FDCPE_IDE_BASEADR5: FDCPE port map (IDE_BASEADR(5),IDE_BASEADR_D(5),NOT lan_adr_sw/lan_adr_sw_CLKF,'0',NOT RESET);
IDE_BASEADR_D(5) <= ((D(13).PIN AND
IDE_BASEADR_not0001/IDE_BASEADR_not0001_D2)
OR (IDE_BASEADR(5) AND
NOT IDE_BASEADR_not0001/IDE_BASEADR_not0001_D2));
FDCPE_IDE_BASEADR6: FDCPE port map (IDE_BASEADR(6),IDE_BASEADR_D(6),NOT lan_adr_sw/lan_adr_sw_CLKF,'0',NOT RESET);
IDE_BASEADR_D(6) <= ((D(14).PIN AND
IDE_BASEADR_not0001/IDE_BASEADR_not0001_D2)
OR (IDE_BASEADR(6) AND
NOT IDE_BASEADR_not0001/IDE_BASEADR_not0001_D2));
FDCPE_IDE_BASEADR7: FDCPE port map (IDE_BASEADR(7),IDE_BASEADR_D(7),NOT lan_adr_sw/lan_adr_sw_CLKF,'0',NOT RESET);
IDE_BASEADR_D(7) <= ((D(15).PIN AND
IDE_BASEADR_not0001/IDE_BASEADR_not0001_D2)
OR (IDE_BASEADR(7) AND
NOT IDE_BASEADR_not0001/IDE_BASEADR_not0001_D2));
IDE_BASEADR_not0001/IDE_BASEADR_not0001_D2 <= (NOT AUTO_CONFIG_DONE(1) AND NOT A(2) AND $OpTx$FX_DC$31);
IDE_CS(0) <= NOT A(12);
IDE_CS(1) <= NOT A(13);
FDCPE_IDE_ENABLE: FDCPE port map (IDE_ENABLE,'0',NOT lan_adr_sw/lan_adr_sw_CLKF,'0',NOT RESET,IDE_ENABLE_CE);
IDE_ENABLE_CE <= (NOT AS AND NOT RW AND NOT ide);
IDE_R <= NOT ((NOT AS AND NOT IDE_R_S));
FDCPE_IDE_R_S: FDCPE port map (IDE_R_S,IDE_R_S_D,NOT lan_adr_sw/lan_adr_sw_CLKF,'0',NOT RESET);
IDE_R_S_D <= (RW AND NOT ide AND NOT IDE_ENABLE AND NOT $OpTx$FX_DC$19);
IDE_W <= NOT ((NOT AS AND NOT IDE_W_S));
FDCPE_IDE_W_S: FDCPE port map (IDE_W_S,IDE_W_S_D,NOT lan_adr_sw/lan_adr_sw_CLKF,'0',NOT RESET);
IDE_W_S_D <= (NOT RW AND NOT ide AND NOT $OpTx$FX_DC$19);
INT2_OUT_I <= '0';
INT2_OUT <= INT2_OUT_I when INT2_OUT_OE = '1' else 'Z';
INT2_OUT_OE <= (NOT LAN_INT_ENABLE AND NOT LAN_IRQ_OUT);
INT6_OUT_I <= '0';
INT6_OUT <= INT6_OUT_I when INT6_OUT_OE = '1' else 'Z';
INT6_OUT_OE <= NOT CP_IRQ;
FDCPE_LAN_BASEADR0: FDCPE port map (LAN_BASEADR(0),LAN_BASEADR_D(0),NOT lan_adr_sw/lan_adr_sw_CLKF,'0',NOT RESET);
LAN_BASEADR_D(0) <= ((D(8).PIN AND
LAN_BASEADR_not0001/LAN_BASEADR_not0001_D2)
OR (LAN_BASEADR(0) AND
NOT LAN_BASEADR_not0001/LAN_BASEADR_not0001_D2));
FDCPE_LAN_BASEADR1: FDCPE port map (LAN_BASEADR(1),LAN_BASEADR_D(1),NOT lan_adr_sw/lan_adr_sw_CLKF,'0',NOT RESET);
LAN_BASEADR_D(1) <= ((D(9).PIN AND
LAN_BASEADR_not0001/LAN_BASEADR_not0001_D2)
OR (LAN_BASEADR(1) AND
NOT LAN_BASEADR_not0001/LAN_BASEADR_not0001_D2));
FDCPE_LAN_BASEADR2: FDCPE port map (LAN_BASEADR(2),LAN_BASEADR_D(2),NOT lan_adr_sw/lan_adr_sw_CLKF,'0',NOT RESET);
LAN_BASEADR_D(2) <= ((D(10).PIN AND
LAN_BASEADR_not0001/LAN_BASEADR_not0001_D2)
OR (LAN_BASEADR(2) AND
NOT LAN_BASEADR_not0001/LAN_BASEADR_not0001_D2));
FDCPE_LAN_BASEADR3: FDCPE port map (LAN_BASEADR(3),LAN_BASEADR_D(3),NOT lan_adr_sw/lan_adr_sw_CLKF,'0',NOT RESET);
LAN_BASEADR_D(3) <= ((D(11).PIN AND
LAN_BASEADR_not0001/LAN_BASEADR_not0001_D2)
OR (LAN_BASEADR(3) AND
NOT LAN_BASEADR_not0001/LAN_BASEADR_not0001_D2));
FDCPE_LAN_BASEADR4: FDCPE port map (LAN_BASEADR(4),LAN_BASEADR_D(4),NOT lan_adr_sw/lan_adr_sw_CLKF,'0',NOT RESET);
LAN_BASEADR_D(4) <= ((D(12).PIN AND
LAN_BASEADR_not0001/LAN_BASEADR_not0001_D2)
OR (LAN_BASEADR(4) AND
NOT LAN_BASEADR_not0001/LAN_BASEADR_not0001_D2));
FDCPE_LAN_BASEADR5: FDCPE port map (LAN_BASEADR(5),LAN_BASEADR_D(5),NOT lan_adr_sw/lan_adr_sw_CLKF,'0',NOT RESET);
LAN_BASEADR_D(5) <= ((D(13).PIN AND
LAN_BASEADR_not0001/LAN_BASEADR_not0001_D2)
OR (LAN_BASEADR(5) AND
NOT LAN_BASEADR_not0001/LAN_BASEADR_not0001_D2));
FDCPE_LAN_BASEADR6: FDCPE port map (LAN_BASEADR(6),LAN_BASEADR_D(6),NOT lan_adr_sw/lan_adr_sw_CLKF,'0',NOT RESET);
LAN_BASEADR_D(6) <= ((D(14).PIN AND
LAN_BASEADR_not0001/LAN_BASEADR_not0001_D2)
OR (LAN_BASEADR(6) AND
NOT LAN_BASEADR_not0001/LAN_BASEADR_not0001_D2));
FDCPE_LAN_BASEADR7: FDCPE port map (LAN_BASEADR(7),LAN_BASEADR_D(7),NOT lan_adr_sw/lan_adr_sw_CLKF,'0',NOT RESET);
LAN_BASEADR_D(7) <= ((D(15).PIN AND
LAN_BASEADR_not0001/LAN_BASEADR_not0001_D2)
OR (LAN_BASEADR(7) AND
NOT LAN_BASEADR_not0001/LAN_BASEADR_not0001_D2));
LAN_BASEADR_not0001/LAN_BASEADR_not0001_D2 <= (AUTO_CONFIG_DONE(0) AND NOT RW AND NOT A(5) AND NOT A(4) AND NOT A(2) AND
NOT A(1) AND A(6) AND A(3) AND
AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2 AND NOT IDE_BASEADR_not0001/IDE_BASEADR_not0001_D2);
LAN_CS <= ((NOT lan_adr AND NOT SET_FREQUENCY)
OR (NOT LAN_CS_RST AND SET_FREQUENCY));
FDCPE_LAN_CS_RST: FDCPE port map (LAN_CS_RST,LAN_CS_RST_D,CLK_EXT,'0',LAN_CS_RST_PRE);
LAN_CS_RST_D <= (NOT LAN_RST_SM_FSM_FFd1 AND NOT LAN_RST_SM_FSM_FFd8);
LAN_CS_RST_PRE <= (NOT RESET AND SET_FREQUENCY);
FDCPE_LAN_INT_ENABLE: FDCPE port map (LAN_INT_ENABLE,LAN_INT_ENABLE_D,NOT lan_adr_sw/lan_adr_sw_CLKF,'0',NOT RESET);
LAN_INT_ENABLE_D <= ((LAN_INT_ENABLE AND NOT $OpTx$FX_DC$34)
OR (NOT D(15).PIN AND A(15) AND NOT RW AND NOT lan_adr AND NOT UDS)
OR (NOT D(15).PIN AND A(15) AND NOT RW AND NOT lan_adr AND NOT LDS));
FDCPE_LAN_IRQ_D0: FDCPE port map (LAN_IRQ_D0,LAN_INT,NOT lan_adr_sw/lan_adr_sw_CLKF,'0',NOT RESET);
FDCPE_LAN_IRQ_OUT: FDCPE port map (LAN_IRQ_OUT,LAN_IRQ_OUT_D,NOT lan_adr_sw/lan_adr_sw_CLKF,'0',NOT RESET);
LAN_IRQ_OUT_D <= ((LAN_INT)
OR (A(15) AND NOT RW AND D(14).PIN AND NOT lan_adr AND NOT LAN_IRQ_D0 AND
NOT UDS)
OR (A(15) AND NOT RW AND D(14).PIN AND NOT lan_adr AND NOT LAN_IRQ_D0 AND
NOT LDS)
OR (LAN_INT_ENABLE AND NOT LAN_IRQ_D0)
OR (LAN_IRQ_OUT AND NOT LAN_IRQ_D0 AND NOT $OpTx$FX_DC$34));
LAN_RD <= ((NOT LAN_RD_S AND $OpTx$FX_DC$30)
OR (NOT LAN_RD_S AND NOT SET_FREQUENCY AND NOT AS_D));
FDCPE_LAN_RD_S: FDCPE port map (LAN_RD_S,LAN_RD_S_D,NOT lan_adr_sw/lan_adr_sw_CLKF,'0',NOT RESET);
LAN_RD_S_D <= (NOT A(15) AND RW AND NOT lan_adr AND NOT $OpTx$FX_DC$19);
FDCPE_LAN_RST_SM_FSM_FFd1: FDCPE port map (LAN_RST_SM_FSM_FFd1,LAN_RST_SM_FSM_FFd1_D,CLK_EXT,LAN_RST_SM_FSM_FFd1_CLR,'0');
LAN_RST_SM_FSM_FFd1_D <= (NOT LAN_RST_SM_FSM_FFd1 AND NOT LAN_RST_SM_FSM_FFd2);
LAN_RST_SM_FSM_FFd1_CLR <= (NOT RESET AND SET_FREQUENCY);
FDCPE_LAN_RST_SM_FSM_FFd2: FDCPE port map (LAN_RST_SM_FSM_FFd2,LAN_RST_SM_FSM_FFd3,CLK_EXT,LAN_RST_SM_FSM_FFd2_CLR,'0');
LAN_RST_SM_FSM_FFd2_CLR <= (NOT RESET AND SET_FREQUENCY);
FDCPE_LAN_RST_SM_FSM_FFd3: FDCPE port map (LAN_RST_SM_FSM_FFd3,LAN_RST_SM_FSM_FFd4,CLK_EXT,LAN_RST_SM_FSM_FFd3_CLR,'0');
LAN_RST_SM_FSM_FFd3_CLR <= (NOT RESET AND SET_FREQUENCY);
FDCPE_LAN_RST_SM_FSM_FFd4: FDCPE port map (LAN_RST_SM_FSM_FFd4,LAN_RST_SM_FSM_FFd5,CLK_EXT,LAN_RST_SM_FSM_FFd4_CLR,'0');
LAN_RST_SM_FSM_FFd4_CLR <= (NOT RESET AND SET_FREQUENCY);
FDCPE_LAN_RST_SM_FSM_FFd5: FDCPE port map (LAN_RST_SM_FSM_FFd5,LAN_RST_SM_FSM_FFd6,CLK_EXT,LAN_RST_SM_FSM_FFd5_CLR,'0');
LAN_RST_SM_FSM_FFd5_CLR <= (NOT RESET AND SET_FREQUENCY);
FDCPE_LAN_RST_SM_FSM_FFd6: FDCPE port map (LAN_RST_SM_FSM_FFd6,LAN_RST_SM_FSM_FFd7,CLK_EXT,LAN_RST_SM_FSM_FFd6_CLR,'0');
LAN_RST_SM_FSM_FFd6_CLR <= (NOT RESET AND SET_FREQUENCY);
FDCPE_LAN_RST_SM_FSM_FFd7: FDCPE port map (LAN_RST_SM_FSM_FFd7,LAN_RST_SM_FSM_FFd8,CLK_EXT,LAN_RST_SM_FSM_FFd7_CLR,'0');
LAN_RST_SM_FSM_FFd7_CLR <= (NOT RESET AND SET_FREQUENCY);
FDCPE_LAN_RST_SM_FSM_FFd8: FDCPE port map (LAN_RST_SM_FSM_FFd8,'0',CLK_EXT,'0',LAN_RST_SM_FSM_FFd8_PRE);
LAN_RST_SM_FSM_FFd8_PRE <= (NOT RESET AND SET_FREQUENCY);
LAN_WRH <= ((NOT LAN_WR_RST AND NOT $OpTx$FX_DC$30)
OR (NOT LAN_WRH_S AND $OpTx$FX_DC$30));
FDCPE_LAN_WRH_S: FDCPE port map (LAN_WRH_S,LAN_WRH_S_D,NOT lan_adr_sw/lan_adr_sw_CLKF,'0',NOT RESET);
LAN_WRH_S_D <= (NOT A(15) AND NOT RW AND NOT lan_adr AND NOT LDS);
LAN_WRL <= ((NOT LAN_WR_RST AND NOT $OpTx$FX_DC$30)
OR (NOT LAN_WRL_S AND $OpTx$FX_DC$30));
FDCPE_LAN_WRL_S: FDCPE port map (LAN_WRL_S,LAN_WRL_S_D,NOT lan_adr_sw/lan_adr_sw_CLKF,'0',NOT RESET);
LAN_WRL_S_D <= (NOT A(15) AND NOT RW AND NOT lan_adr AND NOT UDS);
FDCPE_LAN_WR_RST: FDCPE port map (LAN_WR_RST,LAN_WR_RST_D,CLK_EXT,'0',LAN_WR_RST_PRE);
LAN_WR_RST_D <= (NOT LAN_RST_SM_FSM_FFd3 AND NOT LAN_RST_SM_FSM_FFd6);
LAN_WR_RST_PRE <= (NOT RESET AND SET_FREQUENCY);
MTACK_I <= '0';
MTACK <= MTACK_I when MTACK_OE = '1' else 'Z';
MTACK_OE <= '0';
OVR_I <= '0';
OVR <= OVR_I when OVR_OE = '1' else 'Z';
OVR_OE <= '0';
OWN_I <= '0';
OWN <= OWN_I when OWN_OE = '1' else 'Z';
OWN_OE <= '0';
ROM_B(0) <= '0';
ROM_B(1) <= '0';
ROM_OE <= ((ROM_OE_S)
OR (AS AND AS_D));
FDCPE_ROM_OE_S: FDCPE port map (ROM_OE_S,ROM_OE_S_D,NOT lan_adr_sw/lan_adr_sw_CLKF,'0',NOT RESET);
ROM_OE_S_D <= (RW AND NOT ide AND IDE_ENABLE AND NOT $OpTx$FX_DC$19);
FTCPE_SET_FREQUENCY: FTCPE port map (SET_FREQUENCY,SET_FREQUENCY_T,CLK_EXT,'0','0');
SET_FREQUENCY_T <= (RESET AND LAN_RST_SM_FSM_FFd1 AND SET_FREQUENCY);
FDCPE_SHUT_UP0: FDCPE port map (SHUT_UP(0),SHUT_UP_D(0),NOT lan_adr_sw/lan_adr_sw_CLKF,'0',NOT RESET);
SHUT_UP_D(0) <= (SHUT_UP(0) AND
NOT LAN_BASEADR_not0001/LAN_BASEADR_not0001_D2);
FDCPE_SHUT_UP1: FDCPE port map (SHUT_UP(1),SHUT_UP_D(1),NOT lan_adr_sw/lan_adr_sw_CLKF,'0',NOT RESET);
SHUT_UP_D(1) <= (SHUT_UP(1) AND
NOT CP_BASEADR_not0001/CP_BASEADR_not0001_D2);
FDCPE_SHUT_UP2: FDCPE port map (SHUT_UP(2),SHUT_UP_D(2),NOT lan_adr_sw/lan_adr_sw_CLKF,'0',NOT RESET);
SHUT_UP_D(2) <= (SHUT_UP(2) AND
NOT IDE_BASEADR_not0001/IDE_BASEADR_not0001_D2);
SLAVE <= ((AS AND AS_D)
OR (CP_CS AND autoconfig AND lan_adr AND ide));
FDCPE_autoconfig: FDCPE port map (autoconfig,autoconfig_D,lan_adr_sw/lan_adr_sw_CLKF,'0',NOT RESET);
autoconfig_D <= (A(23) AND A(22) AND A(21) AND A(19) AND NOT A(18) AND NOT A(17) AND
NOT A(16) AND NOT A(20) AND NOT CFIN AND CFOUT);
FDCPE_ide: FDCPE port map (ide,ide_D,lan_adr_sw/lan_adr_sw_CLKF,'0',NOT RESET);
ide_D <= ((SHUT_UP(2))
OR (EXP28_.EXP)
OR (IDE_BASEADR(2) AND NOT A(18))
OR (IDE_BASEADR(3) AND NOT A(19))
OR (NOT IDE_BASEADR(3) AND A(19))
OR (IDE_BASEADR(5) AND NOT A(21))
OR (NOT IDE_BASEADR(5) AND A(21))
OR (IDE_BASEADR(0) AND NOT A(16))
OR (NOT IDE_BASEADR(0) AND A(16))
OR (IDE_BASEADR(1) AND NOT A(17))
OR (NOT IDE_BASEADR(1) AND A(17))
OR (NOT IDE_BASEADR(2) AND A(18))
OR (IDE_BASEADR(6) AND NOT A(22))
OR (NOT IDE_BASEADR(6) AND A(22)));
FDCPE_lan_adr: FDCPE port map (lan_adr,lan_adr_D,lan_adr_sw/lan_adr_sw_CLKF,'0',NOT RESET);
lan_adr_D <= (NOT SHUT_UP(0) AND NOT $OpTx$FX_DC$38 AND NOT $OpTx$FX_DC$39 AND
NOT $OpTx$FX_DC$40 AND NOT $OpTx$FX_DC$44 AND NOT $OpTx$FX_DC$41 AND NOT $OpTx$FX_DC$42 AND
NOT $OpTx$FX_DC$43 AND NOT $OpTx$FX_DC$45);
FDCPE_lan_adr_sw: FDCPE port map (lan_adr_sw,lan_adr_sw_D,lan_adr_sw/lan_adr_sw_CLKF,'0',NOT RESET);
lan_adr_sw_D <= ((NOT SHUT_UP(0) AND NOT A(13) AND NOT $OpTx$FX_DC$38 AND
NOT $OpTx$FX_DC$39 AND NOT $OpTx$FX_DC$40 AND NOT $OpTx$FX_DC$44 AND NOT $OpTx$FX_DC$41 AND
NOT $OpTx$FX_DC$42 AND NOT $OpTx$FX_DC$43 AND NOT $OpTx$FX_DC$45)
OR (NOT SHUT_UP(0) AND NOT A(14) AND NOT $OpTx$FX_DC$38 AND
NOT $OpTx$FX_DC$39 AND NOT $OpTx$FX_DC$40 AND NOT $OpTx$FX_DC$44 AND NOT $OpTx$FX_DC$41 AND
NOT $OpTx$FX_DC$42 AND NOT $OpTx$FX_DC$43 AND NOT $OpTx$FX_DC$45));
lan_adr_sw/lan_adr_sw_CLKF <= NOT (C3
XOR
lan_adr_sw/lan_adr_sw_CLKF <= NOT (C1);
Register Legend:
FDCPE (Q,D,C,CLR,PRE,CE);
FTCPE (Q,D,C,CLR,PRE,CE);
LDCP (Q,D,G,CLR,PRE);
****************************** Device Pin Out *****************************
Device : XC95288XL-10-TQ144
Pin Signal Pin Signal
No. Name No. Name
1 VCC 73 VCC
2 D<0> 74 A<15>
3 A_LAN<1> 75 IDE_OFF
4 A_LAN<0> 76 LAN_WRL
5 A_LAN<3> 77 KPR
6 A_LAN<2> 78 KPR
7 A_LAN<5> 79 KPR
8 VCC 80 AS
9 A_LAN<4> 81 UDS
10 A_LAN<7> 82 LDS
11 A_LAN<6> 83 RW
12 KPR 84 VCC
13 KPR 85 DTACK
14 D<6> 86 A<23>
15 D<3> 87 A<22>
16 D<7> 88 A<21>
17 D<1> 89 GND
18 GND 90 GND
19 D<8> 91 A<20>
20 D<5> 92 A<19>
21 D<4> 93 KPR
22 IDE_CS<0> 94 A<18>
23 IDE_CS<1> 95 A<17>
24 IDE_A<0> 96 MTACK
25 IDE_A<2> 97 A<16>
26 IDE_A<1> 98 KPR
27 IDE_R 99 GND
28 IDE_W 100 OVR
29 GND 101 KPR
30 CLK_EXT 102 C3
31 CP_IRQ 103 C1
32 INT2_OUT 104 CFIN
33 KPR 105 CFOUT
34 CP_CS 106 SLAVE
35 ROM_OE 107 OWN
36 GND 108 GND
37 VCC 109 VCC
38 KPR 110 KPR
39 D<2> 111 LAN_INT
40 D<9> 112 DQ<15>
41 D<10> 113 DQ<13>
42 VCC 114 GND
43 D<11> 115 DQ<11>
44 D<12> 116 DQ<9>
45 D<13> 117 DQ<1>
46 D<14> 118 DQ<0>
47 GND 119 DQ<3>
48 D<15> 120 DQ<2>
49 A<5> 121 DQ<5>
50 A<4> 122 TDO
51 A<6> 123 GND
52 A<3> 124 DQ<4>
53 A<7> 125 DQ<7>
54 A<2> 126 DQ<6>
55 VCC 127 VCC
56 A<8> 128 DQ<8>
57 A<1> 129 DQ<10>
58 A<9> 130 DQ<12>
59 A<10> 131 DQ<14>
60 A<11> 132 LAN_WRH
61 A<12> 133 LAN_CS
62 GND 134 LAN_RD
63 TDI 135 INT6_OUT
64 A<13> 136 A_LAN<12>
65 TMS 137 A_LAN<13>
66 A<14> 138 A_LAN<10>
67 TCK 139 A_LAN<11>
68 ROM_B<0> 140 A_LAN<8>
69 ROM_B<1> 141 VCC
70 CP_WE 142 A_LAN<9>
71 CP_RD 143 RESET
72 GND 144 GND
Legend : NC = Not Connected, unbonded pin
PGND = Unused I/O configured as additional Ground pin
TIE = Unused I/O floating -- must tie to VCC, GND or other signal
KPR = Unused I/O with weak keeper (leave unconnected)
VCC = Dedicated Power Pin
GND = Dedicated Ground Pin
TDI = Test Data In, JTAG pin
TDO = Test Data Out, JTAG pin
TCK = Test Clock, JTAG pin
TMS = Test Mode Select, JTAG pin
PROHIBITED = User reserved pin
**************************** Compiler Options ****************************
Following is a list of all global compiler options used by the fitter run.
Device(s) Specified : xc95288xl-10-TQ144
Optimization Method : DENSITY
Multi-Level Logic Optimization : ON
Ignore Timing Specifications : OFF
Default Register Power Up Value : HIGH
Keep User Location Constraints : ON
What-You-See-Is-What-You-Get : OFF
Exhaustive Fitting : ON
Keep Unused Inputs : OFF
Slew Rate : FAST
Power Mode : STD
Ground on Unused IOs : OFF
Set I/O Pin Termination : KEEPER
Global Clock Optimization : ON
Global Set/Reset Optimization : ON
Global Ouput Enable Optimization : ON
Input Limit : 54
Pterm Limit : 90
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