25 lines
1.6 KiB
Plaintext
25 lines
1.6 KiB
Plaintext
WARNING:Cpld - Unable to retrieve the path to the iSE Project Repository. Will
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use the default filename of 'LAN_IDE_CP.ise'.
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INFO:Cpld - Inferring BUFG constraint for signal 'CLK_EXT' based upon the LOC
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constraint 'P30'. It is recommended that you declare this BUFG explicitedly
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in your design. Note that for certain device families the output of a BUFG
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constraint can not drive a gated clock, and the BUFG constraint will be
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ignored.
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WARNING:Cpld:1007 - Removing unused input(s) 'BERR'. The input(s) are unused
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after optimization. Please verify functionality via simulation.
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WARNING:Cpld:1007 - Removing unused input(s) 'IDE_WAIT'. The input(s) are
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unused after optimization. Please verify functionality via simulation.
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WARNING:Cpld:1007 - Removing unused input(s) 'MTCR'. The input(s) are unused
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after optimization. Please verify functionality via simulation.
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WARNING:Cpld:896 - Unable to map all desired signals into function block, FB5,
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because too many function block product terms are required. Buffering output
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signal CP_CS to allow all signals assigned to this function block to be
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placed.
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ERROR:Cpld:886 - Function block FB1 was too congested to route successfully.
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This occurs due to excessive (>= 50) product term input fanins to this
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function block. Consider moving output signals in this function block to less
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congested function blocks, buffering output signals that must remain in this
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function block, or selecting a larger package.
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ERROR:Cpld:868 - Cannot fit the design into any of the specified devices with
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the selected implementation options.
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