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8230e4fca288b6fc67569ddb6cbb29b8f20dd420
Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.rpt
T
MHeinrichs 8230e4fca2 try for CP in Z3
2019-02-26 21:59:05 +01:00

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cpldfit: version P.20131013 Xilinx Inc.
No Fit Report
Design Name: LAN_IDE_CP Date: 2-24-2019, 3:25PM
Device Used: XC95288XL-10-TQ144
Fitting Status: Placement Failed
************************** Errors and Warnings ***************************
WARNING:Cpld - Unable to retrieve the path to the iSE Project Repository. Will
use the default filename of 'LAN_IDE_CP.ise'.
INFO:Cpld - Inferring BUFG constraint for signal 'CLK_EXT' based upon the LOC
constraint 'P30'. It is recommended that you declare this BUFG explicitedly
in your design. Note that for certain device families the output of a BUFG
constraint can not drive a gated clock, and the BUFG constraint will be
ignored.
WARNING:Cpld:1007 - Removing unused input(s) 'BERR'. The input(s) are unused
after optimization. Please verify functionality via simulation.
WARNING:Cpld:1007 - Removing unused input(s) 'IDE_WAIT'. The input(s) are
unused after optimization. Please verify functionality via simulation.
WARNING:Cpld:1007 - Removing unused input(s) 'MTCR'. The input(s) are unused
after optimization. Please verify functionality via simulation.
WARNING:Cpld:896 - Unable to map all desired signals into function block, FB5,
because too many function block product terms are required. Buffering output
signal CP_CS to allow all signals assigned to this function block to be
placed.
ERROR:Cpld:886 - Function block FB1 was too congested to route successfully.
This occurs due to excessive (>= 50) product term input fanins to this
function block. Consider moving output signals in this function block to less
congested function blocks, buffering output signals that must remain in this
function block, or selecting a larger package.
ERROR:Cpld:868 - Cannot fit the design into any of the specified devices with
the selected implementation options.
************************* Mapped Resource Summary **************************
Macrocells Product Terms Function Block Registers Pins
Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot
238/288 ( 83%) 1259/1440 ( 87%) 818/864 ( 95%) 153/288 ( 53%) 114/117 ( 97%)
** Function Block Resources **
Function Mcells FB Inps Pterms IO
Block Used/Tot Used/Tot Used/Tot Used/Tot
FB1 16/18 54/54* 67/90 8/ 8*
FB2 18/18* 43/54 68/90 10/10*
FB3 15/18 54/54* 80/90 5/ 5*
FB4 16/18 51/54 74/90 6/ 6*
FB5 14/18 53/54 86/90 7/ 8
FB6 15/18 42/54 79/90 8/ 8*
FB7 11/18 50/54 90/90* 4/ 4*
FB8 13/18 52/54 68/90 5/ 5*
FB9 12/18 52/54 90/90* 9/ 9*
FB10 16/18 44/54 76/90 10/10*
FB11 17/18 54/54* 82/90 7/ 7*
FB12 13/18 54/54* 70/90 6/ 6*
FB13 18/18* 54/54* 72/90 6/ 6*
FB14 18/18* 53/54 82/90 7/ 8
FB15 15/18 54/54* 86/90 9/ 9*
FB16 11/18 54/54* 89/90 7/ 8
----- ----- ----- -----
238/288 818/864 1259/1440 114/117
* - Resource is exhausted
** Global Control Resources **
Global clock net(s) unused.
Global output enable net(s) unused.
Global set/reset net(s) unused.
** Pin Resources **
Signal Type Required Mapped | Pin Type Used Total
------------------------------------|------------------------------------
Input : 22 22 | I/O : 107 109
Output : 43 43 | GCK/IO : 2 3
Bidirectional : 48 48 | GTS/IO : 4 4
GCK : 1 1 | GSR/IO : 1 1
GTS : 0 0 |
GSR : 0 0 |
---- ----
Total 114 114
** Power Data **
There are 238 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
End of Mapped Resource Summary
************************* Summary of Mapped Logic ************************
** 91 Outputs **
Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init
Name Pts Inps No. Type Use Mode Rate State
D<5> 3 6 FB1_5 20 I/O I/O STD FAST
D<4> 3 6 FB1_6 21 I/O I/O STD FAST
IDE_CS<0> 1 1 FB1_8 22 I/O O STD FAST
IDE_CS<1> 1 1 FB1_10 23 I/O O STD FAST
IDE_A<0> 1 1 FB1_12 24 I/O O STD FAST
IDE_A<2> 1 1 FB1_14 25 I/O O STD FAST
IDE_A<1> 1 1 FB1_15 26 I/O O STD FAST
IDE_R 1 2 FB1_17 27 I/O O STD FAST
A_LAN<4> 2 4 FB2_2 9 I/O O STD FAST
A_LAN<7> 1 2 FB2_3 10 I/O O STD FAST
A_LAN<6> 2 3 FB2_5 11 I/O O STD FAST
LAN_CFG<1> 0 0 FB2_6 12 I/O O STD FAST
LAN_CFG<3> 0 0 FB2_8 13 I/O O STD FAST
D<6> 3 6 FB2_10 14 I/O I/O STD FAST
D<3> 3 6 FB2_12 15 I/O I/O STD FAST
D<7> 3 6 FB2_14 16 I/O I/O STD FAST
D<1> 3 6 FB2_15 17 I/O I/O STD FAST
D<8> 3 6 FB2_17 19 I/O I/O STD FAST
IDE_W 1 2 FB3_2 28 I/O O STD FAST
INT2_OUT 1 2 FB3_14 32 GCK/I/O O STD FAST
ROM_B<0> 0 0 FB3_15 33 I/O O STD FAST
D<0> 3 6 FB4_2 2 GTS/I/O I/O STD FAST
A_LAN<1> 1 2 FB4_5 3 GTS/I/O O STD FAST
A_LAN<0> 1 2 FB4_6 4 I/O O STD FAST
A_LAN<3> 3 5 FB4_8 5 GTS/I/O O STD FAST
A_LAN<2> 2 4 FB4_12 6 GTS/I/O O STD FAST
A_LAN<5> 2 4 FB4_14 7 I/O O STD FAST
CP_CS 1 1 FB5_2 34 I/O O STD FAST
ROM_OE 1 3 FB5_5 35 I/O O STD FAST
D<2> 3 6 FB5_10 39 I/O I/O STD FAST
D<9> 3 6 FB5_12 40 I/O I/O STD FAST
D<10> 3 6 FB5_14 41 I/O I/O STD FAST
D<11> 3 6 FB5_15 43 I/O I/O STD FAST
D<12> 6 7 FB5_17 44 I/O I/O STD FAST
LAN_CFG<2> 0 0 FB6_2 135 I/O O STD FAST
A_LAN<12> 1 2 FB6_3 136 I/O O STD FAST
A_LAN<13> 1 2 FB6_5 137 I/O O STD FAST
A_LAN<10> 1 2 FB6_6 138 I/O O STD FAST
A_LAN<11> 1 2 FB6_8 139 I/O O STD FAST
A_LAN<8> 1 2 FB6_10 140 I/O O STD FAST
Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init
Name Pts Inps No. Type Use Mode Rate State
A_LAN<9> 1 2 FB6_14 142 I/O O STD FAST
D<13> 6 7 FB7_3 45 I/O I/O STD FAST
D<14> 6 7 FB7_5 46 I/O I/O STD FAST
D<15> 6 7 FB7_12 48 I/O I/O STD FAST
DQ<12> 2 3 FB8_2 130 I/O I/O STD FAST
DQ<14> 2 3 FB8_3 131 I/O I/O STD FAST
LAN_WRH 3 4 FB8_5 132 I/O O STD FAST
LAN_CS 3 4 FB8_8 133 I/O O STD FAST
LAN_RD 1 3 FB8_10 134 I/O O STD FAST
A<8> 8 16 FB9_11 56 I/O I/O STD FAST RESET
A<9> 8 16 FB9_14 58 I/O I/O STD FAST RESET
A<10> 8 16 FB9_17 59 I/O I/O STD FAST RESET
DQ<1> 3 4 FB10_2 117 I/O I/O STD FAST
DQ<0> 2 3 FB10_3 118 I/O I/O STD FAST
DQ<3> 2 3 FB10_5 119 I/O I/O STD FAST
DQ<2> 2 3 FB10_6 120 I/O I/O STD FAST
DQ<5> 2 3 FB10_8 121 I/O I/O STD FAST
DQ<4> 3 4 FB10_10 124 I/O I/O STD FAST
DQ<7> 2 3 FB10_11 125 I/O I/O STD FAST
DQ<6> 2 3 FB10_12 126 I/O I/O STD FAST
DQ<8> 3 4 FB10_14 128 I/O I/O STD FAST
DQ<10> 3 4 FB10_17 129 I/O I/O STD FAST
A<11> 8 16 FB11_3 60 I/O I/O STD FAST RESET
A<12> 8 16 FB11_5 61 I/O I/O STD FAST RESET
A<13> 8 16 FB11_10 64 I/O I/O STD FAST RESET
A<14> 8 16 FB11_11 66 I/O I/O STD FAST RESET
INT6_OUT 1 1 FB11_12 68 I/O O STD FAST
ROM_B<1> 0 0 FB11_14 69 I/O O STD FAST
CP_WE 1 2 FB11_17 70 I/O O STD FAST
LAN_CFG<4> 0 0 FB12_2 110 I/O O STD FAST
DQ<15> 2 3 FB12_5 112 I/O I/O STD FAST
DQ<13> 2 3 FB12_8 113 I/O I/O STD FAST
DQ<11> 3 4 FB12_10 115 I/O I/O STD FAST
DQ<9> 3 4 FB12_12 116 I/O I/O STD FAST
CP_RD 1 2 FB13_2 71 I/O O STD FAST
A<15> 8 16 FB13_8 74 I/O I/O STD FAST RESET
LAN_WRL 3 4 FB13_14 76 I/O O STD FAST
OVR 1 2 FB14_3 100 I/O O STD FAST
CFOUT 1 3 FB14_11 105 I/O O STD FAST
SLAVE 4 6 FB14_14 106 I/O O STD FAST
Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init
Name Pts Inps No. Type Use Mode Rate State
OWN 0 0 FB14_15 107 I/O O STD FAST
DTACK 1 2 FB15_12 85 I/O O STD FAST
A<23> 8 16 FB15_14 86 I/O I/O STD FAST RESET
A<22> 8 16 FB15_15 87 I/O I/O STD FAST RESET
A<21> 8 16 FB15_17 88 I/O I/O STD FAST RESET
A<20> 8 16 FB16_2 91 I/O I/O STD FAST RESET
A<19> 8 16 FB16_3 92 I/O I/O STD FAST RESET
A<18> 8 16 FB16_6 94 I/O I/O STD FAST RESET
A<17> 8 16 FB16_8 95 I/O I/O STD FAST RESET
MTACK 0 0 FB16_10 96 I/O O STD FAST
A<16> 8 16 FB16_11 97 I/O I/O STD FAST RESET
** 147 Buried Nodes **
Signal Total Total Loc Pwr Reg Init
Name Pts Inps Mode State
D_Z2_OUT<0> 15 14 FB1_1 STD SET
Z3_ADR<10> 3 3 FB1_3 STD RESET
LAN_WRH_S 3 6 FB1_4 STD RESET
D_8_IOBUFE/D_8_IOBUFE_TRST 3 6 FB1_7 STD
AUTOCONFIG_Z2_ACCESS 5 14 FB1_9 STD RESET
LAN_BASEADR<9> 6 16 FB1_11 STD RESET
DQ_DATA<10> 10 14 FB1_13 STD RESET
DQ_DATA<0> 10 14 FB1_16 STD RESET
CP_BASEADR<6> 6 17 FB2_1 STD RESET
CP_BASEADR<5> 6 17 FB2_4 STD RESET
CP_BASEADR<4> 6 17 FB2_7 STD RESET
CP_BASEADR<3> 6 17 FB2_9 STD RESET
CP_BASEADR<2> 6 17 FB2_11 STD RESET
CP_BASEADR<1> 6 17 FB2_13 STD RESET
CP_BASEADR<15> 6 17 FB2_16 STD RESET
CP_BASEADR<14> 6 17 FB2_18 STD RESET
$OpTx$INV$125 15 15 FB3_1 STD
Z3_ADR<4> 3 3 FB3_3 STD RESET
Z3_ADR<12> 3 3 FB3_4 STD RESET
Z3_ADR<11> 3 3 FB3_5 STD RESET
AUTO_CONFIG_Z2_DONE<1> 4 5 FB3_6 STD RESET
LAN_WRL_S 3 6 FB3_7 STD RESET
$OpTx$FX_DC$172 6 9 FB3_8 STD
LAN_ACCESS 6 8 FB3_9 STD RESET
LAN_SM_FSM_FFd4 8 11 FB3_10 STD RESET
Z3_DATA<31> 8 13 FB3_11 STD RESET
DQ_SWAP 9 10 FB3_13 STD RESET
LAN_READY 10 12 FB3_17 STD RESET
D_Z2_OUT<3> 14 14 FB4_4 STD SET
CP_BASEADR<0> 6 17 FB4_7 STD RESET
CP_BASEADR<10> 6 17 FB4_9 STD RESET
IDE_BASEADR<6> 6 18 FB4_10 STD RESET
IDE_BASEADR<7> 6 18 FB4_11 STD RESET
IDE_R_S 3 6 FB4_13 STD RESET
ROM_OE_S 3 6 FB4_15 STD RESET
LAN_RST_SM_FSM_FFd2 2 2 FB4_16 STD RESET
SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF 2 2 FB4_17 STD
$OpTx$INV$123 14 14 FB4_18 STD
DQ_DATA<13> 10 14 FB5_3 STD RESET
Z3_DATA<30> 8 13 FB5_4 STD RESET
Signal Total Total Loc Pwr Reg Init
Name Pts Inps Mode State
DQ_DATA<1> 10 14 FB5_7 STD RESET
DQ_DATA<15> 10 14 FB5_9 STD RESET
DQ_DATA<14> 10 14 FB5_11 STD RESET
LAN_INT_ENABLE 4 15 FB5_13 STD RESET
LAN_SM_FSM_FFd3 14 16 FB5_18 STD RESET
Z3_A_LOW 10 13 FB6_4 STD RESET
Z3_DATA<16> 8 13 FB6_7 STD RESET
Z3_DATA<17> 8 13 FB6_9 STD RESET
Z3_DATA<18> 8 13 FB6_11 STD RESET
Z3_DATA<19> 8 13 FB6_12 STD RESET
Z3_DATA<20> 8 13 FB6_13 STD RESET
Z3_DATA<21> 8 13 FB6_15 STD RESET
LAN_SM_FSM_FFd8 15 16 FB6_18 STD RESET
DQ_11_IOBUFE/DQ_11_IOBUFE_TRST__$INT 4 9 FB7_1 STD
LAN_RD_S 8 14 FB7_4 STD RESET
DQ_DATA<9> 10 14 FB7_7 STD RESET
DQ_DATA<12> 10 14 FB7_9 STD RESET
LAN_SM_FSM_FFd1 11 13 FB7_11 STD RESET
LAN_SM_FSM_FFd7 13 17 FB7_13 STD RESET
D_Z2_OUT<1> 14 13 FB7_17 STD SET
$OpTx$$OpTx$FX_DC$168_INV$2057 2 8 FB7_18 STD
Z3_ADR_0 3 3 FB8_4 STD RESET
Z3_ADR<9> 3 3 FB8_6 STD RESET
Z3_ADR<8> 3 3 FB8_7 STD RESET
Z3_ADR<7> 3 3 FB8_9 STD RESET
Z3_ADR<6> 3 3 FB8_11 STD RESET
Z3_ADR<5> 3 3 FB8_12 STD RESET
Z3_ADR_1 3 3 FB8_13 STD RESET
CP_CS_BUFR 36 36 FB8_17 STD SET
LAN_A_INIT<3> 1 1 FB9_1 STD SET
Z3_DATA<26> 8 13 FB9_2 STD RESET
CP_WAIT<3> 3 6 FB9_3 STD RESET
Z3_DATA<25> 8 13 FB9_4 STD RESET
Z3_DATA<24> 8 13 FB9_6 STD RESET
Z3_DATA<23> 8 13 FB9_8 STD RESET
Z3_DATA<22> 8 13 FB9_9 STD RESET
LAN_SM_FSM_FFd2 16 17 FB9_13 STD RESET
CP_BASEADR<13> 6 17 FB9_16 STD RESET
CP_WAIT<0> 2 3 FB10_1 STD RESET
DQ_DATA<8> 10 14 FB10_4 STD RESET
Signal Total Total Loc Pwr Reg Init
Name Pts Inps Mode State
DQ_DATA<6> 10 14 FB10_9 STD RESET
DQ_DATA<5> 10 14 FB10_13 STD RESET
DQ_DATA<4> 10 14 FB10_16 STD RESET
DQ_DATA<3> 10 14 FB10_18 STD RESET
LAN_D_INIT<8> 2 2 FB11_1 STD RESET
LAN_D_INIT<1> 2 2 FB11_2 STD RESET
LAN_BASEADR<8> 6 16 FB11_6 STD RESET
LAN_A_INIT<6> 2 2 FB11_7 STD SET
LAN_BASEADR<7> 6 16 FB11_8 STD RESET
LAN_BASEADR<6> 6 16 FB11_9 STD RESET
LAN_BASEADR<5> 6 16 FB11_13 STD RESET
LAN_BASEADR<4> 6 16 FB11_15 STD RESET
LAN_BASEADR<3> 6 16 FB11_16 STD RESET
LAN_BASEADR<2> 6 16 FB11_18 STD RESET
DQ_DATA<2> 10 14 FB12_3 STD RESET
DQ_DATA<7> 10 14 FB12_6 STD RESET
LAN_RST_SM_FSM_FFd3 2 2 FB12_7 STD RESET
LAN_BASEADR<15> 6 16 FB12_9 STD RESET
LAN_BASEADR<1> 6 16 FB12_11 STD RESET
AUTO_CONFIG_Z2_DONE<0> 4 5 FB12_13 STD RESET
LAN_BASEADR<14> 6 16 FB12_14 STD RESET
$OpTx$INV$124 16 16 FB12_18 STD
LAN_SM_FSM_FFd6 11 18 FB13_1 STD RESET
CP_BASEADR<11> 6 17 FB13_3 STD RESET
AUTO_CONFIG_Z2_DONE<2> 4 5 FB13_4 STD RESET
CP_BASEADR<12> 6 17 FB13_5 STD RESET
IDE_ACCESS 4 5 FB13_6 STD RESET
CP_WAIT<1> 3 4 FB13_7 STD RESET
CP_WAIT<2> 3 5 FB13_9 STD RESET
IDE_ENABLE 3 5 FB13_10 STD RESET
IDE_W_S 3 5 FB13_11 STD RESET
LAN_RST_SM_FSM_FFd1 3 5 FB13_12 STD RESET
LAN_WR_RST 3 4 FB13_13 STD RESET
Z3_ADR<13> 3 3 FB13_15 STD RESET
Z3_ADR<2> 3 3 FB13_16 STD RESET
LAN_CS_RST 2 4 FB13_17 STD RESET
Z3_ADR<3> 3 3 FB13_18 STD RESET
SHUT_UP_Z2<2> 4 17 FB14_1 STD SET
SHUT_UP_Z2<1> 4 16 FB14_2 STD SET
SHUT_UP_Z2<0> 4 15 FB14_4 STD SET
Signal Total Total Loc Pwr Reg Init
Name Pts Inps Mode State
IDE_BASEADR<5> 6 18 FB14_5 STD RESET
AUTO_CONFIG_Z2_DONE_CYCLE<2> 4 16 FB14_6 STD RESET
AUTO_CONFIG_Z2_DONE_CYCLE<1> 4 15 FB14_7 STD RESET
IDE_BASEADR<4> 6 18 FB14_8 STD RESET
AUTO_CONFIG_Z2_DONE_CYCLE<0> 4 14 FB14_9 STD RESET
IDE_BASEADR<3> 6 18 FB14_10 STD RESET
IDE_BASEADR<2> 6 18 FB14_12 STD RESET
IDE_BASEADR<1> 6 18 FB14_13 STD RESET
IDE_BASEADR<0> 6 18 FB14_16 STD RESET
Z3_DATA<28> 8 13 FB14_17 STD RESET
Z3_DATA<27> 8 13 FB14_18 STD RESET
LAN_BASEADR<12> 6 16 FB15_1 STD RESET
$OpTx$$OpTx$FX_DC$134_INV$2056 1 2 FB15_2 STD
LAN_BASEADR<11> 6 16 FB15_3 STD RESET
LAN_BASEADR<10> 6 16 FB15_4 STD RESET
LAN_BASEADR<0> 6 16 FB15_5 STD RESET
CP_WE_S 6 17 FB15_6 STD RESET
CP_RD_S 6 17 FB15_8 STD RESET
CP_BASEADR<9> 6 17 FB15_9 STD RESET
CP_BASEADR<8> 6 17 FB15_10 STD RESET
CP_BASEADR<7> 6 17 FB15_11 STD RESET
LAN_BASEADR<13> 6 16 FB15_18 STD RESET
D_Z2_OUT<2> 15 14 FB16_1 STD SET
$OpTx$$OpTx$FX_DC$128_INV$2055 1 2 FB16_5 STD
Z3_DATA<29> 8 13 FB16_9 STD RESET
DQ_DATA<11> 10 14 FB16_13 STD RESET
LAN_SM_FSM_FFd5 15 18 FB16_16 STD RESET
** 23 Inputs **
Signal Loc Pin Pin Pin
Name No. Type Use
CLK_EXT FB3_10 30 GCK/I/O GCK
CP_IRQ FB3_12 31 I/O I
RESET FB6_15 143 GSR/I/O I
A<5> FB7_15 49 I/O I
A<4> FB9_2 50 I/O I
A<6> FB9_3 51 I/O I
A<3> FB9_5 52 I/O I
A<7> FB9_6 53 I/O I
A<2> FB9_8 54 I/O I
A<1> FB9_12 57 I/O I
LAN_INT FB12_3 111 I/O I
AUTOBOOT_OFF FB13_11 75 I/O I
FCS FB13_15 77 I/O I
DS1 FB13_17 78 I/O I
C3 FB14_6 102 I/O I
C1 FB14_8 103 I/O I
CFIN FB14_10 104 I/O I
Z3 FB15_2 79 I/O I
AS FB15_3 80 I/O I
UDS FB15_8 81 I/O I
LDS FB15_10 82 I/O I
RW FB15_11 83 I/O I
DS0 FB16_5 93 I/O I
Legend:
Pin No. - ~ - User Assigned
************************** Function Block Details ************************
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X - Signal used as input to the macrocell logic.
Pin No. - ~ - User Assigned
*********************************** FB1 ***********************************
Number of function block inputs used/remaining: 54/0
Number of signals used by logic mapping into function block: 54
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
D_Z2_OUT<0> 15 10<- 0 0 FB1_1 (b) (b)
(unused) 0 0 /\5 0 FB1_2 (b) (b)
Z3_ADR<10> 3 0 0 2 FB1_3 (b) (b)
LAN_WRH_S 3 0 0 2 FB1_4 (b) (b)
D<5> 3 0 0 2 FB1_5 20 I/O I/O
D<4> 3 0 0 2 FB1_6 21 I/O I/O
D_8_IOBUFE/D_8_IOBUFE_TRST
3 0 0 2 FB1_7 (b) (b)
IDE_CS<0> 1 0 0 4 FB1_8 22 I/O O
AUTOCONFIG_Z2_ACCESS
5 0 0 0 FB1_9 (b) (b)
IDE_CS<1> 1 0 \/1 3 FB1_10 23 I/O O
LAN_BASEADR<9> 6 1<- 0 0 FB1_11 (b) (b)
IDE_A<0> 1 0 \/3 1 FB1_12 24 I/O O
DQ_DATA<10> 10 5<- 0 0 FB1_13 (b) (b)
IDE_A<2> 1 0 /\2 2 FB1_14 25 I/O O
IDE_A<1> 1 0 \/3 1 FB1_15 26 I/O O
DQ_DATA<0> 10 5<- 0 0 FB1_16 (b) (b)
IDE_R 1 0 /\2 2 FB1_17 27 I/O O
(unused) 0 0 \/5 0 FB1_18 (b) (b)
Signals Used by Logic in Function Block
1: $OpTx$$OpTx$FX_DC$168_INV$2057 19: D_8_IOBUFE/D_8_IOBUFE_TRST 37: A<8>.PIN
2: AS 20: FCS 38: A<12>.PIN
3: AUTOCONFIG_Z2_ACCESS 21: A<9>.PIN 39: A<13>.PIN
4: AUTO_CONFIG_Z2_DONE<0> 22: A<10>.PIN 40: D<10>.PIN
5: AUTO_CONFIG_Z2_DONE<1> 23: A<11>.PIN 41: D<9>.PIN
6: AUTO_CONFIG_Z2_DONE<2> 24: IDE_R_S 42: D<8>.PIN
7: A<1> 25: LAN_ACCESS 43: D<2>.PIN
8: A<2> 26: LAN_BASEADR<9> 44: D<0>.PIN
9: A<3> 27: LAN_SM_FSM_FFd2 45: A<20>.PIN
10: A<4> 28: LAN_SM_FSM_FFd3 46: A<21>.PIN
11: A<5> 29: LAN_SM_FSM_FFd4 47: A<16>.PIN
12: A<6> 30: LAN_SM_FSM_FFd5 48: A<22>.PIN
13: CFIN 31: LAN_SM_FSM_FFd8 49: RESET
14: CP_CS_BUFR 32: LDS 50: RW
15: DQ_DATA<0> 33: A<17>.PIN 51: SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF
16: DQ_DATA<10> 34: A<23>.PIN 52: UDS
17: DQ_SWAP 35: A<18>.PIN 53: Z3_DATA<20>
18: DS0 36: A<19>.PIN 54: Z3_DATA<21>
Signal 1 2 3 4 5 6 FB
Name 0----+----0----+----0----+----0----+----0----+----0----+----0 Inputs
D_Z2_OUT<0> .XXXX.XXXXXX...................X................X.XX........ 14
Z3_ADR<10> ...................X.................X..........X........... 3
LAN_WRH_S .................X.........XXX.X................X........... 6
D<5> .............X....XX....X........................X...X...... 6
D<4> .............X....XX....X........................X..X....... 6
D_8_IOBUFE/D_8_IOBUFE_TRST
.XX..........X.....X....X........................X.......... 6
IDE_CS<0> .....................................X...................... 1
AUTOCONFIG_Z2_ACCESS
.X.XXX......X...................XXXX........XXXXX........... 14
IDE_CS<1> ......................................X..................... 1
LAN_BASEADR<9> .XXX..XXXXXX.............X.....X........X.......XXXX........ 16
IDE_A<0> ....................X....................................... 1
DQ_DATA<10> X..............XX....X....XXX.XX..X....X..X.....X..X........ 14
IDE_A<2> ......................X..................................... 1
IDE_A<1> .....................X...................................... 1
DQ_DATA<0> X.............X.X.........XXX.XX....X....X.X..X.X..X........ 14
IDE_R .X.....................X.................................... 2
0----+----1----+----2----+----3----+----4----+----5----+----6
0 0 0 0 0 0
*********************************** FB2 ***********************************
Number of function block inputs used/remaining: 43/11
Number of signals used by logic mapping into function block: 43
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
CP_BASEADR<6> 6 1<- 0 0 FB2_1 (b) (b)
A_LAN<4> 2 0 /\1 2 FB2_2 9 I/O O
A_LAN<7> 1 0 \/1 3 FB2_3 10 I/O O
CP_BASEADR<5> 6 1<- 0 0 FB2_4 (b) (b)
A_LAN<6> 2 0 0 3 FB2_5 11 I/O O
LAN_CFG<1> 0 0 \/1 4 FB2_6 12 I/O O
CP_BASEADR<4> 6 1<- 0 0 FB2_7 (b) (b)
LAN_CFG<3> 0 0 \/1 4 FB2_8 13 I/O O
CP_BASEADR<3> 6 1<- 0 0 FB2_9 (b) (b)
D<6> 3 0 \/1 1 FB2_10 14 I/O I/O
CP_BASEADR<2> 6 1<- 0 0 FB2_11 (b) (b)
D<3> 3 0 \/1 1 FB2_12 15 I/O I/O
CP_BASEADR<1> 6 1<- 0 0 FB2_13 (b) (b)
D<7> 3 0 0 2 FB2_14 16 I/O I/O
D<1> 3 0 \/1 1 FB2_15 17 I/O I/O
CP_BASEADR<15> 6 1<- 0 0 FB2_16 (b) (b)
D<8> 3 0 \/1 1 FB2_17 19 I/O I/O
CP_BASEADR<14> 6 1<- 0 0 FB2_18 (b) (b)
Signals Used by Logic in Function Block
1: AS 16: CP_BASEADR<4> 30: D<10>.PIN
2: AUTOCONFIG_Z2_ACCESS 17: CP_BASEADR<5> 31: D<9>.PIN
3: AUTO_CONFIG_Z2_DONE<0> 18: CP_BASEADR<6> 32: RESET
4: AUTO_CONFIG_Z2_DONE<1> 19: CP_CS_BUFR 33: RW
5: A<1> 20: D_8_IOBUFE/D_8_IOBUFE_TRST 34: SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF
6: A<2> 21: FCS 35: UDS
7: A<3> 22: LAN_ACCESS 36: Z3_ADR<3>
8: A<4> 23: LAN_A_INIT<6> 37: Z3_ADR<5>
9: A<5> 24: LDS 38: Z3_ADR<6>
10: A<6> 25: D<15>.PIN 39: Z3_DATA<17>
11: CP_BASEADR<14> 26: D<14>.PIN 40: Z3_DATA<19>
12: CP_BASEADR<15> 27: D<13>.PIN 41: Z3_DATA<22>
13: CP_BASEADR<1> 28: D<12>.PIN 42: Z3_DATA<23>
14: CP_BASEADR<2> 29: D<11>.PIN 43: Z3_DATA<24>
15: CP_BASEADR<3>
Signal 1 2 3 4 5 FB
Name 0----+----0----+----0----+----0----+----0----+----0 Inputs
CP_BASEADR<6> XXXXXXXXXX.......X.....X.X.....XXXX............... 17
A_LAN<4> .......X..........X............X...X.............. 4
A_LAN<7> ...............................X.....X............ 2
CP_BASEADR<5> XXXXXXXXXX......X......X..X....XXXX............... 17
A_LAN<6> ......................X........X....X............. 3
LAN_CFG<1> .................................................. 0
CP_BASEADR<4> XXXXXXXXXX.....X.......X...X...XXXX............... 17
LAN_CFG<3> .................................................. 0
CP_BASEADR<3> XXXXXXXXXX....X........X....X..XXXX............... 17
D<6> ..................XXXX..........X.......X......... 6
CP_BASEADR<2> XXXXXXXXXX...X.........X.....X.XXXX............... 17
D<3> ..................XXXX..........X......X.......... 6
CP_BASEADR<1> XXXXXXXXXX..X..........X......XXXXX............... 17
D<7> ..................XXXX..........X........X........ 6
D<1> ..................XXXX..........X.....X........... 6
CP_BASEADR<15> XXXXXXXXXX.X...........XX......XXXX............... 17
D<8> ..................XXXX..........X.........X....... 6
CP_BASEADR<14> XXXXXXXXXXX............X.X.....XXXX............... 17
0----+----1----+----2----+----3----+----4----+----5
0 0 0 0 0
*********************************** FB3 ***********************************
Number of function block inputs used/remaining: 54/0
Number of signals used by logic mapping into function block: 54
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
$OpTx$INV$125 15 10<- 0 0 FB3_1 (b) (b)
IDE_W 1 1<- /\5 0 FB3_2 28 I/O O
Z3_ADR<4> 3 0 /\1 1 FB3_3 (b) (b)
Z3_ADR<12> 3 0 0 2 FB3_4 (b) (b)
Z3_ADR<11> 3 0 0 2 FB3_5 (b) (b)
AUTO_CONFIG_Z2_DONE<1>
4 0 \/1 0 FB3_6 (b) (b)
LAN_WRL_S 3 1<- \/3 0 FB3_7 (b) (b)
$OpTx$FX_DC$172 6 3<- \/2 0 FB3_8 (b) (b)
LAN_ACCESS 6 2<- \/1 0 FB3_9 (b) (b)
LAN_SM_FSM_FFd4 8 3<- 0 0 FB3_10 30 GCK/I/O GCK
Z3_DATA<31> 8 5<- /\2 0 FB3_11 (b) (b)
(unused) 0 0 /\5 0 FB3_12 31 I/O I
DQ_SWAP 9 4<- 0 0 FB3_13 (b) (b)
INT2_OUT 1 0 /\4 0 FB3_14 32 GCK/I/O O
ROM_B<0> 0 0 0 5 FB3_15 33 I/O O
(unused) 0 0 \/5 0 FB3_16 (b) (b)
LAN_READY 10 5<- 0 0 FB3_17 (b) (b)
(unused) 0 0 \/5 0 FB3_18 (b) (b)
Signals Used by Logic in Function Block
1: $OpTx$FX_DC$172 19: IDE_BASEADR<6> 37: A<23>.PIN
2: $OpTx$INV$123 20: IDE_BASEADR<7> 38: A<18>.PIN
3: $OpTx$INV$124 21: IDE_W_S 39: A<19>.PIN
4: AS 22: LAN_ACCESS 40: DQ<15>.PIN
5: AUTO_CONFIG_Z2_DONE<1> 23: LAN_BASEADR<13> 41: DQ<7>.PIN
6: AUTO_CONFIG_Z2_DONE_CYCLE<1> 24: LAN_BASEADR<6> 42: A<13>.PIN
7: A<6> 25: LAN_INT_ENABLE 43: D<13>.PIN
8: CP_CS_BUFR 26: LAN_INT 44: A<14>.PIN
9: CP_WAIT<3> 27: LAN_SM_FSM_FFd1 45: A<21>.PIN
10: DQ_SWAP 28: LAN_SM_FSM_FFd2 46: A<16>.PIN
11: DS0 29: LAN_SM_FSM_FFd3 47: A<22>.PIN
12: DS1 30: LAN_SM_FSM_FFd4 48: RESET
13: FCS 31: LAN_SM_FSM_FFd5 49: RW
14: IDE_BASEADR<0> 32: LAN_SM_FSM_FFd6 50: SHUT_UP_Z2<2>
15: IDE_BASEADR<1> 33: LAN_SM_FSM_FFd7 51: SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF
16: IDE_BASEADR<2> 34: LAN_SM_FSM_FFd8 52: UDS
17: IDE_BASEADR<3> 35: LDS 53: Z3_ADR<13>
18: IDE_BASEADR<5> 36: A<17>.PIN 54: Z3_DATA<31>
Signal 1 2 3 4 5 6 FB
Name 0----+----0----+----0----+----0----+----0----+----0----+----0 Inputs
$OpTx$INV$125 .............XXXXXXX...............XXXX.....XXX..X.......... 15
IDE_W ...X................X....................................... 2
Z3_ADR<4> ......X.....X..................................X............ 3
Z3_ADR<12> ............X..............................X...X............ 3
Z3_ADR<11> ............X............................X.....X............ 3
AUTO_CONFIG_Z2_DONE<1>
...XXX.........................................X..X......... 5
LAN_WRL_S ...........X................XXX................X...X........ 6
$OpTx$FX_DC$172 .......X..XXX........X............X.............X..XX....... 9
LAN_ACCESS .XX.........X.........XX..................X...XX............ 8
LAN_SM_FSM_FFd4 X...........X.............XXXXXXXX.............X............ 11
Z3_DATA<31> .........X................XXXXXXXX.....XX......X.....X...... 13
DQ_SWAP .XX.........X.........XX.................XXX..XX............ 10
INT2_OUT ........................XX.................................. 2
ROM_B<0> ............................................................ 0
LAN_READY ........X.XX..............XXXXXXXX.............X............ 12
0----+----1----+----2----+----3----+----4----+----5----+----6
0 0 0 0 0 0
*********************************** FB4 ***********************************
Number of function block inputs used/remaining: 51/3
Number of signals used by logic mapping into function block: 51
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 /\5 0 FB4_1 (b) (b)
D<0> 3 0 /\1 1 FB4_2 2 GTS/I/O I/O
(unused) 0 0 \/5 0 FB4_3 (b) (b)
D_Z2_OUT<3> 14 9<- 0 0 FB4_4 (b) (b)
A_LAN<1> 1 0 /\4 0 FB4_5 3 GTS/I/O O
A_LAN<0> 1 0 \/1 3 FB4_6 4 I/O O
CP_BASEADR<0> 6 1<- 0 0 FB4_7 (b) (b)
A_LAN<3> 3 0 \/2 0 FB4_8 5 GTS/I/O O
CP_BASEADR<10> 6 2<- \/1 0 FB4_9 (b) (b)
IDE_BASEADR<6> 6 1<- 0 0 FB4_10 (b) (b)
IDE_BASEADR<7> 6 1<- 0 0 FB4_11 (b) (b)
A_LAN<2> 2 0 /\1 2 FB4_12 6 GTS/I/O O
IDE_R_S 3 0 0 2 FB4_13 (b) (b)
A_LAN<5> 2 0 0 3 FB4_14 7 I/O O
ROM_OE_S 3 0 0 2 FB4_15 (b) (b)
LAN_RST_SM_FSM_FFd2 2 0 0 3 FB4_16 (b) (b)
SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF
2 0 \/3 0 FB4_17 (b) (b)
$OpTx$INV$123 14 9<- 0 0 FB4_18 (b) (b)
Signals Used by Logic in Function Block
1: AS 18: FCS 35: D<12>.PIN
2: AUTOCONFIG_Z2_ACCESS 19: IDE_ACCESS 36: D<11>.PIN
3: AUTO_CONFIG_Z2_DONE<0> 20: IDE_BASEADR<6> 37: D<10>.PIN
4: AUTO_CONFIG_Z2_DONE<1> 21: IDE_BASEADR<7> 38: D<9>.PIN
5: AUTO_CONFIG_Z2_DONE<2> 22: IDE_ENABLE 39: D<8>.PIN
6: A<1> 23: LAN_ACCESS 40: RESET
7: A<2> 24: LAN_A_INIT<3> 41: RW
8: A<3> 25: LAN_BASEADR<10> 42: SHUT_UP_Z2<0>
9: A<4> 26: LAN_BASEADR<11> 43: SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF
10: A<5> 27: LAN_BASEADR<12> 44: UDS
11: A<6> 28: LAN_BASEADR<15> 45: Z3_ADR<2>
12: C1 29: LAN_BASEADR<8> 46: Z3_ADR<4>
13: C3 30: LAN_BASEADR<9> 47: Z3_ADR_0
14: CP_BASEADR<0> 31: LAN_RST_SM_FSM_FFd3 48: Z3_ADR_1
15: CP_BASEADR<10> 32: LDS 49: Z3_A_LOW
16: CP_CS_BUFR 33: D<15>.PIN 50: Z3_DATA<16>
17: D_8_IOBUFE/D_8_IOBUFE_TRST 34: D<14>.PIN 51: Z3
Signal 1 2 3 4 5 6 FB
Name 0----+----0----+----0----+----0----+----0----+----0----+----0 Inputs
D<0> ...............XXX....X.................X........X.......... 6
D_Z2_OUT<3> XXXX.XXXXXX....................X.......X..XX................ 14
A_LAN<1> .......................................X......X............. 2
A_LAN<0> .......................................X........X........... 2
CP_BASEADR<0> XXXX.XXXXXX..X.................X......XXX.XX................ 17
A_LAN<3> .......X.......X.......X...............X....X............... 5
CP_BASEADR<10> XXXX.XXXXXX...X................X....X..XX.XX................ 17
IDE_BASEADR<6> XXXXXXXXXXX........X...........X.X.....XX.XX................ 18
IDE_BASEADR<7> XXXXXXXXXXX.........X..........XX......XX.XX................ 18
A_LAN<2> ......X........X.......................X.......X............ 4
IDE_R_S X.................X..X.................XX.X................. 6
A_LAN<5> .........X.....X.......................X.....X.............. 4
ROM_OE_S X.................X..X.................XX.X................. 6
LAN_RST_SM_FSM_FFd2 ..............................X........X.................... 2
SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF
...........XX............................................... 2
$OpTx$INV$123 ........................XXXXXX..X.XXXXX..X........X......... 14
0----+----1----+----2----+----3----+----4----+----5----+----6
0 0 0 0 0 0
*********************************** FB5 ***********************************
Number of function block inputs used/remaining: 53/1
Number of signals used by logic mapping into function block: 53
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 /\5 0 FB5_1 (b) (b)
CP_CS 1 0 \/4 0 FB5_2 34 I/O O
DQ_DATA<13> 10 5<- 0 0 FB5_3 (b) (b)
Z3_DATA<30> 8 4<- /\1 0 FB5_4 (b) (b)
ROM_OE 1 0 /\4 0 FB5_5 35 I/O O
(unused) 0 0 \/5 0 FB5_6 (b) (b)
DQ_DATA<1> 10 5<- 0 0 FB5_7 (b) (b)
(unused) 0 0 \/5 0 FB5_8 38 GCK/I/O (b)
DQ_DATA<15> 10 5<- 0 0 FB5_9 (b) (b)
D<2> 3 0 \/2 0 FB5_10 39 I/O I/O
DQ_DATA<14> 10 5<- 0 0 FB5_11 (b) (b)
D<9> 3 1<- /\3 0 FB5_12 40 I/O I/O
LAN_INT_ENABLE 4 0 /\1 0 FB5_13 (b) (b)
D<10> 3 0 0 2 FB5_14 41 I/O I/O
D<11> 3 0 0 2 FB5_15 43 I/O I/O
(unused) 0 0 \/5 0 FB5_16 (b) (b)
D<12> 6 5<- \/4 0 FB5_17 44 I/O I/O
LAN_SM_FSM_FFd3 14 9<- 0 0 FB5_18 (b) (b)
Signals Used by Logic in Function Block
1: $OpTx$$OpTx$FX_DC$168_INV$2057 19: LAN_SM_FSM_FFd2 37: D<7>.PIN
2: AS 20: LAN_SM_FSM_FFd3 38: D<6>.PIN
3: AUTOBOOT_OFF 21: LAN_SM_FSM_FFd4 39: D<5>.PIN
4: CP_CS_BUFR 22: LAN_SM_FSM_FFd5 40: D<1>.PIN
5: DQ_DATA<13> 23: LAN_SM_FSM_FFd6 41: A<15>.PIN
6: DQ_DATA<14> 24: LAN_SM_FSM_FFd7 42: A<21>.PIN
7: DQ_DATA<15> 25: LAN_SM_FSM_FFd8 43: A<22>.PIN
8: DQ_DATA<1> 26: LDS 44: RESET
9: DQ_SWAP 27: A<17>.PIN 45: ROM_OE_S
10: DS0 28: A<23>.PIN 46: RW
11: DS1 29: DQ<14>.PIN 47: UDS
12: D_8_IOBUFE/D_8_IOBUFE_TRST 30: DQ<6>.PIN 48: Z3_DATA<18>
13: D_Z2_OUT<0> 31: A<13>.PIN 49: Z3_DATA<25>
14: FCS 32: D<15>.PIN 50: Z3_DATA<26>
15: A<9>.PIN 33: D<14>.PIN 51: Z3_DATA<27>
16: LAN_ACCESS 34: D<13>.PIN 52: Z3_DATA<28>
17: LAN_INT_ENABLE 35: D<9>.PIN 53: Z3_DATA<30>
18: LAN_SM_FSM_FFd1 36: A<14>.PIN
Signal 1 2 3 4 5 6 FB
Name 0----+----0----+----0----+----0----+----0----+----0----+----0 Inputs
CP_CS ...X........................................................ 1
DQ_DATA<13> X...X...X.........XXX...XX....X..X....X..X.X..X............. 14
Z3_DATA<30> ........X........XXXXXXXX...XX.............X........X....... 13
ROM_OE .XX.........................................X............... 3
DQ_DATA<1> X......XX.....X...XXX...XXX.......X....X...X..X............. 14
DQ_DATA<15> X.....X.X.........XXX...XX.X...X....X...X..X..X............. 14
D<2> ...X.......X.X.X.............................X.X............ 6
DQ_DATA<14> X....X..X.........XXX...XX......X..X.X....XX..X............. 14
D<9> ...X.......X.X.X.............................X..X........... 6
LAN_INT_ENABLE ..........X.....XXXXXXXXX..X...X...........X.XX............. 15
D<10> ...X.......X.X.X.............................X...X.......... 6
D<11> ...X.......X.X.X.............................X....X......... 6
D<12> ...X.......XXX.X.............................X.....X........ 7
LAN_SM_FSM_FFd3 ...X.....XX..X.X.XXXXXXXXX.................X..X............. 16
0----+----1----+----2----+----3----+----4----+----5----+----6
0 0 0 0 0 0
*********************************** FB6 ***********************************
Number of function block inputs used/remaining: 42/12
Number of signals used by logic mapping into function block: 42
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 /\5 0 FB6_1 (b) (b)
LAN_CFG<2> 0 0 0 5 FB6_2 135 I/O O
A_LAN<12> 1 0 \/3 1 FB6_3 136 I/O O
Z3_A_LOW 10 5<- 0 0 FB6_4 (b) (b)
A_LAN<13> 1 0 /\2 2 FB6_5 137 I/O O
A_LAN<10> 1 0 \/3 1 FB6_6 138 I/O O
Z3_DATA<16> 8 3<- 0 0 FB6_7 (b) (b)
A_LAN<11> 1 0 \/4 0 FB6_8 139 I/O O
Z3_DATA<17> 8 4<- \/1 0 FB6_9 (b) (b)
A_LAN<8> 1 1<- \/5 0 FB6_10 140 I/O O
Z3_DATA<18> 8 5<- \/2 0 FB6_11 (b) (b)
Z3_DATA<19> 8 3<- 0 0 FB6_12 (b) (b)
Z3_DATA<20> 8 4<- /\1 0 FB6_13 (b) (b)
A_LAN<9> 1 0 /\4 0 FB6_14 142 I/O O
Z3_DATA<21> 8 3<- 0 0 FB6_15 143 GSR/I/O I
(unused) 0 0 /\3 2 FB6_16 (b) (b)
(unused) 0 0 \/5 0 FB6_17 (b) (b)
LAN_SM_FSM_FFd8 15 10<- 0 0 FB6_18 (b) (b)
Signals Used by Logic in Function Block
1: CP_CS_BUFR 15: LAN_SM_FSM_FFd8 29: RESET
2: CP_WAIT<3> 16: LDS 30: UDS
3: DQ_SWAP 17: DQ<13>.PIN 31: Z3_ADR<10>
4: DS0 18: DQ<12>.PIN 32: Z3_ADR<11>
5: DS1 19: DQ<11>.PIN 33: Z3_ADR<12>
6: FCS 20: DQ<10>.PIN 34: Z3_ADR<7>
7: LAN_ACCESS 21: DQ<9>.PIN 35: Z3_ADR<8>
8: LAN_SM_FSM_FFd1 22: DQ<8>.PIN 36: Z3_ADR<9>
9: LAN_SM_FSM_FFd2 23: DQ<5>.PIN 37: Z3_DATA<16>
10: LAN_SM_FSM_FFd3 24: DQ<4>.PIN 38: Z3_DATA<17>
11: LAN_SM_FSM_FFd4 25: DQ<3>.PIN 39: Z3_DATA<18>
12: LAN_SM_FSM_FFd5 26: DQ<2>.PIN 40: Z3_DATA<19>
13: LAN_SM_FSM_FFd6 27: DQ<1>.PIN 41: Z3_DATA<20>
14: LAN_SM_FSM_FFd7 28: DQ<0>.PIN 42: Z3_DATA<21>
Signal 1 2 3 4 5 FB
Name 0----+----0----+----0----+----0----+----0----+----0 Inputs
LAN_CFG<2> .................................................. 0
A_LAN<12> ............................X..X.................. 2
Z3_A_LOW ...XX..XXXXXXXXX............XX.................... 13
A_LAN<13> ............................X...X................. 2
A_LAN<10> ............................X......X.............. 2
Z3_DATA<16> ..X....XXXXXXXX......X.....XX.......X............. 13
A_LAN<11> ............................X.X................... 2
Z3_DATA<17> ..X....XXXXXXXX.....X.....X.X........X............ 13
A_LAN<8> ............................X....X................ 2
Z3_DATA<18> ..X....XXXXXXXX....X.....X..X.........X........... 13
Z3_DATA<19> ..X....XXXXXXXX...X.....X...X..........X.......... 13
Z3_DATA<20> ..X....XXXXXXXX..X.....X....X...........X......... 13
A_LAN<9> ............................X.....X............... 2
Z3_DATA<21> ..X....XXXXXXXX.X.....X.....X............X........ 13
LAN_SM_FSM_FFd8 XX.XXXXXXXX.XXXX............XX.................... 16
0----+----1----+----2----+----3----+----4----+----5
0 0 0 0 0
*********************************** FB7 ***********************************
Number of function block inputs used/remaining: 50/4
Number of signals used by logic mapping into function block: 50
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
DQ_11_IOBUFE/DQ_11_IOBUFE_TRST__$INT
4 0 /\1 0 FB7_1 (b) (b)
(unused) 0 0 \/5 0 FB7_2 (b) (b)
D<13> 6 5<- \/4 0 FB7_3 45 I/O I/O
LAN_RD_S 8 4<- \/1 0 FB7_4 (b) (b)
D<14> 6 1<- 0 0 FB7_5 46 I/O I/O
(unused) 0 0 \/5 0 FB7_6 (b) (b)
DQ_DATA<9> 10 5<- 0 0 FB7_7 (b) (b)
(unused) 0 0 \/5 0 FB7_8 (b) (b)
DQ_DATA<12> 10 5<- 0 0 FB7_9 (b) (b)
(unused) 0 0 \/5 0 FB7_10 (b) (b)
LAN_SM_FSM_FFd1 11 6<- 0 0 FB7_11 (b) (b)
D<15> 6 2<- /\1 0 FB7_12 48 I/O I/O
LAN_SM_FSM_FFd7 13 10<- /\2 0 FB7_13 (b) (b)
(unused) 0 0 /\5 0 FB7_14 (b) (b)
(unused) 0 0 /\5 0 FB7_15 49 I/O I
(unused) 0 0 \/5 0 FB7_16 (b) (b)
D_Z2_OUT<1> 14 9<- 0 0 FB7_17 (b) (b)
$OpTx$$OpTx$FX_DC$168_INV$2057
2 1<- /\4 0 FB7_18 (b) (b)
Signals Used by Logic in Function Block
1: $OpTx$$OpTx$FX_DC$128_INV$2055 18: DS0 35: LDS
2: $OpTx$$OpTx$FX_DC$168_INV$2057 19: DS1 36: A<17>.PIN
3: AS 20: D_8_IOBUFE/D_8_IOBUFE_TRST 37: A<12>.PIN
4: AUTOCONFIG_Z2_ACCESS 21: D_Z2_OUT<1> 38: D<12>.PIN
5: AUTO_CONFIG_Z2_DONE<0> 22: D_Z2_OUT<2> 39: D<9>.PIN
6: AUTO_CONFIG_Z2_DONE<1> 23: D_Z2_OUT<3> 40: D<4>.PIN
7: A<1> 24: FCS 41: D<1>.PIN
8: A<2> 25: A<9>.PIN 42: A<20>.PIN
9: A<3> 26: LAN_ACCESS 43: RESET
10: A<4> 27: LAN_SM_FSM_FFd1 44: RW
11: A<5> 28: LAN_SM_FSM_FFd2 45: SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF
12: A<6> 29: LAN_SM_FSM_FFd3 46: UDS
13: CP_CS_BUFR 30: LAN_SM_FSM_FFd4 47: Z3_ADR<13>
14: CP_WAIT<3> 31: LAN_SM_FSM_FFd5 48: Z3_DATA<29>
15: DQ_DATA<12> 32: LAN_SM_FSM_FFd6 49: Z3_DATA<30>
16: DQ_DATA<9> 33: LAN_SM_FSM_FFd7 50: Z3_DATA<31>
17: DQ_SWAP 34: LAN_SM_FSM_FFd8
Signal 1 2 3 4 5 6 FB
Name 0----+----0----+----0----+----0----+----0----+----0----+----0 Inputs
DQ_11_IOBUFE/DQ_11_IOBUFE_TRST__$INT
............X....XX....X.X........X.......XX.X.............. 9
D<13> ............X......XX..X.X.................X...X............ 7
LAN_RD_S .................XX....X.X.X..XXXXX.......XX.XX............. 14
D<14> ............X......X.X.X.X.................X....X........... 7
DQ_DATA<9> .X.............XX.......X..XXX...XXX..X.X.X..X.............. 14
DQ_DATA<12> .X............X.X..........XXX...XX.XX.X.XX..X.............. 14
LAN_SM_FSM_FFd1 .............X...XX....X..XXXXXXXX........X................. 13
D<15> ............X......X..XX.X.................X.....X.......... 7
LAN_SM_FSM_FFd7 ............X....XX....X.XXXXXXXXXX.......X..XX............. 17
D_Z2_OUT<1> X.XXXXXXXXXX..............................X.X............... 13
$OpTx$$OpTx$FX_DC$168_INV$2057
..........................XXXXXXXX.......................... 8
0----+----1----+----2----+----3----+----4----+----5----+----6
0 0 0 0 0 0
*********************************** FB8 ***********************************
Number of function block inputs used/remaining: 52/2
Number of signals used by logic mapping into function block: 52
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 /\5 0 FB8_1 (b) (b)
DQ<12> 2 1<- /\4 0 FB8_2 130 I/O I/O
DQ<14> 2 0 /\1 2 FB8_3 131 I/O I/O
Z3_ADR_0 3 0 0 2 FB8_4 (b) (b)
LAN_WRH 3 0 0 2 FB8_5 132 I/O O
Z3_ADR<9> 3 0 0 2 FB8_6 (b) (b)
Z3_ADR<8> 3 0 0 2 FB8_7 (b) (b)
LAN_CS 3 0 0 2 FB8_8 133 I/O O
Z3_ADR<7> 3 0 0 2 FB8_9 (b) (b)
LAN_RD 1 0 0 4 FB8_10 134 I/O O
Z3_ADR<6> 3 0 0 2 FB8_11 (b) (b)
Z3_ADR<5> 3 0 0 2 FB8_12 (b) (b)
Z3_ADR_1 3 0 \/2 0 FB8_13 (b) (b)
(unused) 0 0 \/5 0 FB8_14 (b) (b)
(unused) 0 0 \/5 0 FB8_15 (b) (b)
(unused) 0 0 \/5 0 FB8_16 (b) (b)
CP_CS_BUFR 36 31<- 0 0 FB8_17 (b) (b)
(unused) 0 0 /\5 0 FB8_18 (b) (b)
Signals Used by Logic in Function Block
1: A<2> 19: CP_BASEADR<9> 36: A<8>.PIN
2: A<3> 20: DQ_11_IOBUFE/DQ_11_IOBUFE_TRST__$INT 37: D<15>.PIN
3: A<7> 21: DQ_DATA<12> 38: D<14>.PIN
4: CP_BASEADR<0> 22: DQ_DATA<14> 39: D<13>.PIN
5: CP_BASEADR<10> 23: FCS 40: D<12>.PIN
6: CP_BASEADR<11> 24: A<9>.PIN 41: D<11>.PIN
7: CP_BASEADR<12> 25: A<10>.PIN 42: D<10>.PIN
8: CP_BASEADR<13> 26: A<11>.PIN 43: D<9>.PIN
9: CP_BASEADR<14> 27: LAN_ACCESS 44: D<8>.PIN
10: CP_BASEADR<15> 28: LAN_CS_RST 45: A<20>.PIN
11: CP_BASEADR<1> 29: LAN_RD_S 46: A<21>.PIN
12: CP_BASEADR<2> 30: LAN_WRH_S 47: A<16>.PIN
13: CP_BASEADR<3> 31: LAN_WR_RST 48: A<22>.PIN
14: CP_BASEADR<4> 32: A<17>.PIN 49: RESET
15: CP_BASEADR<5> 33: A<23>.PIN 50: SHUT_UP_Z2<1>
16: CP_BASEADR<6> 34: A<18>.PIN 51: Z3_ADR<13>
17: CP_BASEADR<7> 35: A<19>.PIN 52: Z3
18: CP_BASEADR<8>
Signal 1 2 3 4 5 6 FB
Name 0----+----0----+----0----+----0----+----0----+----0----+----0 Inputs
DQ<12> ...................XX...........................X........... 3
DQ<14> ...................X.X..........................X........... 3
Z3_ADR_0 X.....................X.........................X........... 3
LAN_WRH ......................X......XX.................X........... 4
Z3_ADR<9> ......................X..X......................X........... 3
Z3_ADR<8> ......................X.X.......................X........... 3
LAN_CS ..........................XX....................X.X......... 4
Z3_ADR<7> ......................XX........................X........... 3
LAN_RD ......................X.....X...................X........... 3
Z3_ADR<6> ......................X............X............X........... 3
Z3_ADR<5> ..X...................X.........................X........... 3
Z3_ADR_1 .X....................X.........................X........... 3
CP_CS_BUFR ...XXXXXXXXXXXXXXXX...X........XXXX.XXXXXXXXXXXXXX.X........ 36
0----+----1----+----2----+----3----+----4----+----5----+----6
0 0 0 0 0 0
*********************************** FB9 ***********************************
Number of function block inputs used/remaining: 52/2
Number of signals used by logic mapping into function block: 52
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
LAN_A_INIT<3> 1 0 \/4 0 FB9_1 (b) (b)
Z3_DATA<26> 8 4<- \/1 0 FB9_2 50 I/O I
CP_WAIT<3> 3 1<- \/3 0 FB9_3 51 I/O I
Z3_DATA<25> 8 3<- 0 0 FB9_4 (b) (b)
(unused) 0 0 \/5 0 FB9_5 52 I/O I
Z3_DATA<24> 8 5<- \/2 0 FB9_6 53 I/O I
(unused) 0 0 \/5 0 FB9_7 (b) (b)
Z3_DATA<23> 8 7<- \/4 0 FB9_8 54 I/O I
Z3_DATA<22> 8 4<- \/1 0 FB9_9 (b) (b)
(unused) 0 0 \/5 0 FB9_10 (b) (b)
A<8> 8 6<- \/3 0 FB9_11 56 I/O I/O
(unused) 0 0 \/5 0 FB9_12 57 I/O I
LAN_SM_FSM_FFd2 16 11<- 0 0 FB9_13 (b) (b)
A<9> 8 6<- /\3 0 FB9_14 58 I/O I/O
(unused) 0 0 /\5 0 FB9_15 (b) (b)
CP_BASEADR<13> 6 2<- /\1 0 FB9_16 (b) (b)
A<10> 8 5<- /\2 0 FB9_17 59 I/O I/O
(unused) 0 0 /\5 0 FB9_18 (b) (b)
Signals Used by Logic in Function Block
1: $OpTx$$OpTx$FX_DC$134_INV$2056 19: CP_WAIT<2> 36: DQ<9>.PIN
2: A<10> 20: CP_WAIT<3> 37: DQ<8>.PIN
3: A<8> 21: DQ_SWAP 38: DQ<7>.PIN
4: A<9> 22: FCS 39: DQ<6>.PIN
5: AS 23: LAN_ACCESS 40: DQ<2>.PIN
6: AUTOCONFIG_Z2_ACCESS 24: LAN_SM_FSM_FFd1 41: DQ<1>.PIN
7: AUTO_CONFIG_Z2_DONE<0> 25: LAN_SM_FSM_FFd2 42: DQ<0>.PIN
8: AUTO_CONFIG_Z2_DONE<1> 26: LAN_SM_FSM_FFd3 43: D<13>.PIN
9: A<1> 27: LAN_SM_FSM_FFd4 44: RESET
10: A<2> 28: LAN_SM_FSM_FFd5 45: RW
11: A<3> 29: LAN_SM_FSM_FFd6 46: SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF
12: A<4> 30: LAN_SM_FSM_FFd7 47: UDS
13: A<5> 31: LAN_SM_FSM_FFd8 48: Z3_DATA<22>
14: A<6> 32: LDS 49: Z3_DATA<23>
15: CP_BASEADR<13> 33: DQ<15>.PIN 50: Z3_DATA<24>
16: CP_CS_BUFR 34: DQ<14>.PIN 51: Z3_DATA<25>
17: CP_WAIT<0> 35: DQ<10>.PIN 52: Z3_DATA<26>
18: CP_WAIT<1>
Signal 1 2 3 4 5 6 FB
Name 0----+----0----+----0----+----0----+----0----+----0----+----0 Inputs
LAN_A_INIT<3> ...........................................X................ 1
Z3_DATA<26> ....................X..XXXXXXXX...X....X...X.......X........ 13
CP_WAIT<3> ...............XXXXX.......................X................ 6
Z3_DATA<25> ....................X..XXXXXXXX....X....X..X......X......... 13
Z3_DATA<24> ....................X..XXXXXXXX.....X....X.X.....X.......... 13
Z3_DATA<23> ....................X..XXXXXXXX.X....X.....X....X........... 13
Z3_DATA<22> ....................X..XXXXXXXX..X....X....X...X............ 13
A<8> ..X.................XXXXXXXXXXX.....X....X.XX............... 16
LAN_SM_FSM_FFd2 X..............X...X.XXXXXXXXXXX...........XX.X............. 17
A<9> ...X................XXXXXXXXXXX....X....X..XX............... 16
CP_BASEADR<13> ....XXXXXXXXXXX................X..........XXXXX............. 17
A<10> .X..................XXXXXXXXXXX...X....X...XX............... 16
0----+----1----+----2----+----3----+----4----+----5----+----6
0 0 0 0 0 0
*********************************** FB10 ***********************************
Number of function block inputs used/remaining: 44/10
Number of signals used by logic mapping into function block: 44
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
CP_WAIT<0> 2 0 /\3 0 FB10_1 (b) (b)
DQ<1> 3 0 0 2 FB10_2 117 I/O I/O
DQ<0> 2 0 \/3 0 FB10_3 118 I/O I/O
DQ_DATA<8> 10 5<- 0 0 FB10_4 (b) (b)
DQ<3> 2 0 /\2 1 FB10_5 119 I/O I/O
DQ<2> 2 0 0 3 FB10_6 120 I/O I/O
(unused) 0 0 0 5 FB10_7 (b)
DQ<5> 2 0 \/3 0 FB10_8 121 I/O I/O
DQ_DATA<6> 10 5<- 0 0 FB10_9 (b) (b)
DQ<4> 3 0 /\2 0 FB10_10 124 I/O I/O
DQ<7> 2 0 0 3 FB10_11 125 I/O I/O
DQ<6> 2 0 \/3 0 FB10_12 126 I/O I/O
DQ_DATA<5> 10 5<- 0 0 FB10_13 (b) (b)
DQ<8> 3 0 /\2 0 FB10_14 128 I/O I/O
(unused) 0 0 \/5 0 FB10_15 (b) (b)
DQ_DATA<4> 10 5<- 0 0 FB10_16 (b) (b)
DQ<10> 3 0 \/2 0 FB10_17 129 I/O I/O
DQ_DATA<3> 10 5<- 0 0 FB10_18 (b) (b)
Signals Used by Logic in Function Block
1: $OpTx$$OpTx$FX_DC$168_INV$2057 16: A<11>.PIN 31: D<11>.PIN
2: CP_CS_BUFR 17: LAN_D_INIT<1> 32: D<8>.PIN
3: CP_WAIT<0> 18: LAN_D_INIT<8> 33: A<14>.PIN
4: DQ_11_IOBUFE/DQ_11_IOBUFE_TRST__$INT 19: LAN_SM_FSM_FFd2 34: D<6>.PIN
5: DQ_DATA<0> 20: LAN_SM_FSM_FFd3 35: D<5>.PIN
6: DQ_DATA<10> 21: LAN_SM_FSM_FFd4 36: D<4>.PIN
7: DQ_DATA<1> 22: LAN_SM_FSM_FFd8 37: D<3>.PIN
8: DQ_DATA<2> 23: LDS 38: D<0>.PIN
9: DQ_DATA<3> 24: A<19>.PIN 39: A<20>.PIN
10: DQ_DATA<4> 25: A<8>.PIN 40: A<21>.PIN
11: DQ_DATA<5> 26: A<12>.PIN 41: A<16>.PIN
12: DQ_DATA<6> 27: A<13>.PIN 42: A<22>.PIN
13: DQ_DATA<7> 28: D<14>.PIN 43: RESET
14: DQ_DATA<8> 29: D<13>.PIN 44: UDS
15: DQ_SWAP 30: D<12>.PIN
Signal 1 2 3 4 5 FB
Name 0----+----0----+----0----+----0----+----0----+----0 Inputs
CP_WAIT<0> .XX.......................................X....... 3
DQ<1> ...X..X.........X.........................X....... 4
DQ<0> ...XX.....................................X....... 3
DQ_DATA<8> X............XX...XXXXX.X......X.....X..X.XX...... 14
DQ<3> ...X....X.................................X....... 3
DQ<2> ...X...X..................................X....... 3
DQ<5> ...X......X...............................X....... 3
DQ_DATA<6> X..........X..X...XXXXX....X....XX.......XXX...... 14
DQ<4> ...X.....X......X.........................X....... 4
DQ<7> ...X........X.............................X....... 3
DQ<6> ...X.......X..............................X....... 3
DQ_DATA<5> X.........X...X...XXXXX...X.X.....X....X..XX...... 14
DQ<8> ...X.........X...X........................X....... 4
DQ_DATA<4> X........X....X...XXXXX..X...X.....X..X...XX...... 14
DQ<10> ...X.X...........X........................X....... 4
DQ_DATA<3> X.......X.....XX..XXXXXX......X.....X.....XX...... 14
0----+----1----+----2----+----3----+----4----+----5
0 0 0 0 0
*********************************** FB11 ***********************************
Number of function block inputs used/remaining: 54/0
Number of signals used by logic mapping into function block: 54
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
LAN_D_INIT<8> 2 0 /\1 2 FB11_1 (b) (b)
LAN_D_INIT<1> 2 0 \/3 0 FB11_2 (b) (b)
A<11> 8 3<- 0 0 FB11_3 60 I/O I/O
(unused) 0 0 \/5 0 FB11_4 (b) (b)
A<12> 8 5<- \/2 0 FB11_5 61 I/O I/O
LAN_BASEADR<8> 6 2<- \/1 0 FB11_6 (b) (b)
LAN_A_INIT<6> 2 1<- \/4 0 FB11_7 (b) (b)
LAN_BASEADR<7> 6 4<- \/3 0 FB11_8 (b) (b)
LAN_BASEADR<6> 6 3<- \/2 0 FB11_9 (b) (b)
A<13> 8 3<- 0 0 FB11_10 64 I/O I/O
A<14> 8 4<- /\1 0 FB11_11 66 I/O I/O
INT6_OUT 1 0 /\4 0 FB11_12 68 I/O O
LAN_BASEADR<5> 6 1<- 0 0 FB11_13 (b) (b)
ROM_B<1> 0 0 /\1 4 FB11_14 69 I/O O
LAN_BASEADR<4> 6 1<- 0 0 FB11_15 (b) (b)
LAN_BASEADR<3> 6 2<- /\1 0 FB11_16 (b) (b)
CP_WE 1 0 /\2 2 FB11_17 70 I/O O
LAN_BASEADR<2> 6 1<- 0 0 FB11_18 (b) (b)
Signals Used by Logic in Function Block
1: A<11> 19: LAN_BASEADR<2> 37: DQ<13>.PIN
2: A<12> 20: LAN_BASEADR<3> 38: DQ<12>.PIN
3: A<13> 21: LAN_BASEADR<4> 39: DQ<11>.PIN
4: A<14> 22: LAN_BASEADR<5> 40: DQ<6>.PIN
5: AS 23: LAN_BASEADR<6> 41: DQ<5>.PIN
6: AUTOCONFIG_Z2_ACCESS 24: LAN_BASEADR<7> 42: DQ<4>.PIN
7: AUTO_CONFIG_Z2_DONE<0> 25: LAN_BASEADR<8> 43: DQ<3>.PIN
8: A<1> 26: LAN_RST_SM_FSM_FFd1 44: D<15>.PIN
9: A<2> 27: LAN_SM_FSM_FFd1 45: D<14>.PIN
10: A<3> 28: LAN_SM_FSM_FFd2 46: D<13>.PIN
11: A<4> 29: LAN_SM_FSM_FFd3 47: D<12>.PIN
12: A<5> 30: LAN_SM_FSM_FFd4 48: D<11>.PIN
13: A<6> 31: LAN_SM_FSM_FFd5 49: D<10>.PIN
14: CP_IRQ 32: LAN_SM_FSM_FFd6 50: D<8>.PIN
15: CP_WE_S 33: LAN_SM_FSM_FFd7 51: RESET
16: DQ_SWAP 34: LAN_SM_FSM_FFd8 52: RW
17: FCS 35: LDS 53: SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF
18: LAN_ACCESS 36: DQ<14>.PIN 54: UDS
Signal 1 2 3 4 5 6 FB
Name 0----+----0----+----0----+----0----+----0----+----0----+----0 Inputs
LAN_D_INIT<8> .........................X........................X......... 2
LAN_D_INIT<1> .........................X........................X......... 2
A<11> X..............XXX........XXXXXXXX....X...X.......XX........ 16
A<12> .X.............XXX........XXXXXXXX...X...X........XX........ 16
LAN_BASEADR<8> ....XXXXXXXXX...........X.........X..............XXXXX...... 16
LAN_A_INIT<6> .........................X........................X......... 2
LAN_BASEADR<7> ....XXXXXXXXX..........X..........X........X......XXXX...... 16
LAN_BASEADR<6> ....XXXXXXXXX.........X...........X.........X.....XXXX...... 16
A<13> ..X............XXX........XXXXXXXX..X...X.........XX........ 16
A<14> ...X...........XXX........XXXXXXXX.X...X..........XX........ 16
INT6_OUT .............X.............................................. 1
LAN_BASEADR<5> ....XXXXXXXXX........X............X..........X....XXXX...... 16
ROM_B<1> ............................................................ 0
LAN_BASEADR<4> ....XXXXXXXXX.......X.............X...........X...XXXX...... 16
LAN_BASEADR<3> ....XXXXXXXXX......X..............X............X..XXXX...... 16
CP_WE ..............X.X........................................... 2
LAN_BASEADR<2> ....XXXXXXXXX.....X...............X.............X.XXXX...... 16
0----+----1----+----2----+----3----+----4----+----5----+----6
0 0 0 0 0 0
*********************************** FB12 ***********************************
Number of function block inputs used/remaining: 54/0
Number of signals used by logic mapping into function block: 54
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 /\5 0 FB12_1 (b) (b)
LAN_CFG<4> 0 0 \/4 1 FB12_2 110 I/O O
DQ_DATA<2> 10 5<- 0 0 FB12_3 111 I/O I
(unused) 0 0 /\1 4 FB12_4 (b) (b)
DQ<15> 2 0 \/2 1 FB12_5 112 I/O I/O
DQ_DATA<7> 10 5<- 0 0 FB12_6 (b) (b)
LAN_RST_SM_FSM_FFd3 2 0 /\3 0 FB12_7 (b) (b)
DQ<13> 2 0 0 3 FB12_8 113 I/O I/O
LAN_BASEADR<15> 6 1<- 0 0 FB12_9 (b) (b)
DQ<11> 3 0 /\1 1 FB12_10 115 I/O I/O
LAN_BASEADR<1> 6 1<- 0 0 FB12_11 (b) (b)
DQ<9> 3 0 /\1 1 FB12_12 116 I/O I/O
AUTO_CONFIG_Z2_DONE<0>
4 0 \/1 0 FB12_13 (b) (b)
LAN_BASEADR<14> 6 1<- 0 0 FB12_14 (b) (b)
(unused) 0 0 0 5 FB12_15 (b)
(unused) 0 0 \/1 4 FB12_16 (b) (b)
(unused) 0 0 \/5 0 FB12_17 (b) (b)
$OpTx$INV$124 16 11<- 0 0 FB12_18 (b) (b)
Signals Used by Logic in Function Block
1: $OpTx$$OpTx$FX_DC$168_INV$2057 19: DQ_SWAP 37: A<17>.PIN
2: AS 20: A<10>.PIN 38: A<23>.PIN
3: AUTOCONFIG_Z2_ACCESS 21: LAN_BASEADR<0> 39: A<18>.PIN
4: AUTO_CONFIG_Z2_DONE<0> 22: LAN_BASEADR<14> 40: A<19>.PIN
5: AUTO_CONFIG_Z2_DONE_CYCLE<0> 23: LAN_BASEADR<15> 41: D<15>.PIN
6: A<1> 24: LAN_BASEADR<1> 42: D<14>.PIN
7: A<2> 25: LAN_BASEADR<2> 43: D<10>.PIN
8: A<3> 26: LAN_BASEADR<3> 44: D<9>.PIN
9: A<4> 27: LAN_BASEADR<4> 45: D<7>.PIN
10: A<5> 28: LAN_BASEADR<5> 46: D<2>.PIN
11: A<6> 29: LAN_BASEADR<7> 47: A<20>.PIN
12: DQ_11_IOBUFE/DQ_11_IOBUFE_TRST__$INT 30: LAN_D_INIT<1> 48: A<15>.PIN
13: DQ_DATA<11> 31: LAN_D_INIT<8> 49: A<21>.PIN
14: DQ_DATA<13> 32: LAN_SM_FSM_FFd2 50: A<16>.PIN
15: DQ_DATA<15> 33: LAN_SM_FSM_FFd3 51: RESET
16: DQ_DATA<2> 34: LAN_SM_FSM_FFd4 52: RW
17: DQ_DATA<7> 35: LAN_SM_FSM_FFd8 53: SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF
18: DQ_DATA<9> 36: LDS 54: UDS
Signal 1 2 3 4 5 6 FB
Name 0----+----0----+----0----+----0----+----0----+----0----+----0 Inputs
LAN_CFG<4> ............................................................ 0
DQ_DATA<2> X..............X..XX...........XXXXX..X...X..X....X..X...... 14
DQ<15> ...........X..X...................................X......... 3
DQ_DATA<7> X...............X.X............XXXXX.X..X...X..X..X..X...... 14
LAN_RST_SM_FSM_FFd3 ..............................X...................X......... 2
DQ<13> ...........X.X....................................X......... 3
LAN_BASEADR<15> .XXX.XXXXXX...........X............X....X.........XXXX...... 16
DQ<11> ...........XX.................X...................X......... 4
LAN_BASEADR<1> .XXX.XXXXXX............X...........X.......X......XXXX...... 16
DQ<9> ...........X.....X...........X....................X......... 4
AUTO_CONFIG_Z2_DONE<0>
.X.XX.............................................X.X....... 5
LAN_BASEADR<14> .XXX.XXXXXX..........X.............X.....X........XXXX...... 16
$OpTx$INV$124 ....................XX.XXXXXX.......XXXX.X....X.XX.......... 16
0----+----1----+----2----+----3----+----4----+----5----+----6
0 0 0 0 0 0
*********************************** FB13 ***********************************
Number of function block inputs used/remaining: 54/0
Number of signals used by logic mapping into function block: 54
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
LAN_SM_FSM_FFd6 11 6<- 0 0 FB13_1 (b) (b)
CP_RD 1 0 /\4 0 FB13_2 71 I/O O
CP_BASEADR<11> 6 1<- 0 0 FB13_3 (b) (b)
AUTO_CONFIG_Z2_DONE<2>
4 0 /\1 0 FB13_4 (b) (b)
CP_BASEADR<12> 6 1<- 0 0 FB13_5 (b) (b)
IDE_ACCESS 4 0 /\1 0 FB13_6 (b) (b)
CP_WAIT<1> 3 0 \/2 0 FB13_7 (b) (b)
A<15> 8 3<- 0 0 FB13_8 74 I/O I/O
CP_WAIT<2> 3 0 /\1 1 FB13_9 (b) (b)
IDE_ENABLE 3 0 0 2 FB13_10 (b) (b)
IDE_W_S 3 0 0 2 FB13_11 75 I/O I
LAN_RST_SM_FSM_FFd1 3 0 0 2 FB13_12 (b) (b)
LAN_WR_RST 3 0 0 2 FB13_13 (b) (b)
LAN_WRL 3 0 0 2 FB13_14 76 I/O O
Z3_ADR<13> 3 0 0 2 FB13_15 77 I/O I
Z3_ADR<2> 3 0 0 2 FB13_16 (b) (b)
LAN_CS_RST 2 0 0 3 FB13_17 78 I/O I
Z3_ADR<3> 3 0 \/2 0 FB13_18 (b) (b)
Signals Used by Logic in Function Block
1: $OpTx$INV$125 19: CP_WAIT<0> 37: LAN_SM_FSM_FFd5
2: A<15> 20: CP_WAIT<1> 38: LAN_SM_FSM_FFd6
3: AS 21: CP_WAIT<2> 39: LAN_SM_FSM_FFd7
4: AUTOCONFIG_Z2_ACCESS 22: DQ_SWAP 40: LAN_SM_FSM_FFd8
5: AUTO_CONFIG_Z2_DONE<0> 23: DS0 41: LAN_WRL_S
6: AUTO_CONFIG_Z2_DONE<1> 24: DS1 42: LAN_WR_RST
7: AUTO_CONFIG_Z2_DONE<2> 25: FCS 43: LDS
8: AUTO_CONFIG_Z2_DONE_CYCLE<2> 26: IDE_ACCESS 44: DQ<15>.PIN
9: A<1> 27: IDE_BASEADR<4> 45: DQ<7>.PIN
10: A<2> 28: LAN_ACCESS 46: D<12>.PIN
11: A<3> 29: LAN_D_INIT<8> 47: D<11>.PIN
12: A<4> 30: LAN_RST_SM_FSM_FFd1 48: A<20>.PIN
13: A<5> 31: LAN_RST_SM_FSM_FFd2 49: A<15>.PIN
14: A<6> 32: LAN_RST_SM_FSM_FFd3 50: RESET
15: CP_BASEADR<11> 33: LAN_SM_FSM_FFd1 51: RW
16: CP_BASEADR<12> 34: LAN_SM_FSM_FFd2 52: SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF
17: CP_CS_BUFR 35: LAN_SM_FSM_FFd3 53: UDS
18: CP_RD_S 36: LAN_SM_FSM_FFd4 54: Z3_ADR<13>
Signal 1 2 3 4 5 6 FB
Name 0----+----0----+----0----+----0----+----0----+----0----+----0 Inputs
LAN_SM_FSM_FFd6 ................X.....XXX..X....XXXXXXXX..X......XX.XX...... 18
CP_RD .................X......X................................... 2
CP_BASEADR<11> ..XXXX..XXXXXXX...........................X...X..XXXX....... 17
AUTO_CONFIG_Z2_DONE<2>
..X...XX.........................................X.X........ 5
CP_BASEADR<12> ..XXXX..XXXXXX.X..........................X..X...XXXX....... 17
IDE_ACCESS X.X.......................X....................X.X.......... 5
CP_WAIT<1> ................X.XX.............................X.......... 4
A<15> .X...................X..X..X....XXXXXXXX...XX....XX......... 16
CP_WAIT<2> ................X.XXX............................X.......... 5
IDE_ENABLE ..X......................X.......................XXX........ 5
IDE_W_S ..X......................X.......................XXX........ 5
LAN_RST_SM_FSM_FFd1 ............................XXXX.................X.......... 5
LAN_WR_RST ............................X.XX.................X.......... 4
LAN_WRL ........................X...............XX.......X.......... 4
Z3_ADR<13> ........................X.......................XX.......... 3
Z3_ADR<2> ...........X............X........................X.......... 3
LAN_CS_RST ............................X.XX.................X.......... 4
Z3_ADR<3> ............X...........X........................X.......... 3
0----+----1----+----2----+----3----+----4----+----5----+----6
0 0 0 0 0 0
*********************************** FB14 ***********************************
Number of function block inputs used/remaining: 53/1
Number of signals used by logic mapping into function block: 53
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
SHUT_UP_Z2<2> 4 2<- /\3 0 FB14_1 (b) (b)
SHUT_UP_Z2<1> 4 1<- /\2 0 FB14_2 (b) (b)
OVR 1 0 /\1 3 FB14_3 100 I/O O
SHUT_UP_Z2<0> 4 0 \/1 0 FB14_4 (b) (b)
IDE_BASEADR<5> 6 1<- 0 0 FB14_5 101 I/O (b)
AUTO_CONFIG_Z2_DONE_CYCLE<2>
4 0 0 1 FB14_6 102 I/O I
AUTO_CONFIG_Z2_DONE_CYCLE<1>
4 0 \/1 0 FB14_7 (b) (b)
IDE_BASEADR<4> 6 1<- 0 0 FB14_8 103 I/O I
AUTO_CONFIG_Z2_DONE_CYCLE<0>
4 0 \/1 0 FB14_9 (b) (b)
IDE_BASEADR<3> 6 1<- 0 0 FB14_10 104 I/O I
CFOUT 1 0 \/1 3 FB14_11 105 I/O O
IDE_BASEADR<2> 6 1<- 0 0 FB14_12 (b) (b)
IDE_BASEADR<1> 6 1<- 0 0 FB14_13 (b) (b)
SLAVE 4 0 /\1 0 FB14_14 106 I/O O
OWN 0 0 \/4 1 FB14_15 107 I/O O
IDE_BASEADR<0> 6 4<- \/3 0 FB14_16 (b) (b)
Z3_DATA<28> 8 3<- 0 0 FB14_17 (b) (b)
Z3_DATA<27> 8 3<- 0 0 FB14_18 (b) (b)
Signals Used by Logic in Function Block
1: AS 19: IDE_BASEADR<0> 37: DQ<4>.PIN
2: AUTOCONFIG_Z2_ACCESS 20: IDE_BASEADR<1> 38: DQ<3>.PIN
3: AUTO_CONFIG_Z2_DONE<0> 21: IDE_BASEADR<2> 39: D<13>.PIN
4: AUTO_CONFIG_Z2_DONE<1> 22: IDE_BASEADR<3> 40: D<12>.PIN
5: AUTO_CONFIG_Z2_DONE<2> 23: IDE_BASEADR<4> 41: D<11>.PIN
6: AUTO_CONFIG_Z2_DONE_CYCLE<0> 24: IDE_BASEADR<5> 42: D<10>.PIN
7: AUTO_CONFIG_Z2_DONE_CYCLE<1> 25: LAN_ACCESS 43: D<9>.PIN
8: AUTO_CONFIG_Z2_DONE_CYCLE<2> 26: LAN_SM_FSM_FFd1 44: D<8>.PIN
9: A<1> 27: LAN_SM_FSM_FFd2 45: RESET
10: A<2> 28: LAN_SM_FSM_FFd3 46: RW
11: A<3> 29: LAN_SM_FSM_FFd4 47: SHUT_UP_Z2<0>
12: A<4> 30: LAN_SM_FSM_FFd5 48: SHUT_UP_Z2<1>
13: A<5> 31: LAN_SM_FSM_FFd6 49: SHUT_UP_Z2<2>
14: A<6> 32: LAN_SM_FSM_FFd7 50: SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF
15: CP_CS_BUFR 33: LAN_SM_FSM_FFd8 51: UDS
16: DQ_SWAP 34: LDS 52: Z3_DATA<27>
17: FCS 35: DQ<12>.PIN 53: Z3_DATA<28>
18: IDE_ACCESS 36: DQ<11>.PIN
Signal 1 2 3 4 5 6 FB
Name 0----+----0----+----0----+----0----+----0----+----0----+----0 Inputs
SHUT_UP_Z2<2> XXXXX...XXXXXX...................X..........XX..XXX......... 17
SHUT_UP_Z2<1> XXXX....XXXXXX...................X..........XX.X.XX......... 16
OVR ................X.......X................................... 2
SHUT_UP_Z2<0> XXX.....XXXXXX...................X..........XXX..XX......... 15
IDE_BASEADR<5> XXXXX...XXXXXX.........X.........X....X.....XX...XX......... 18
AUTO_CONFIG_Z2_DONE_CYCLE<2>
XXXXX..XX.XXXX...................X..........XX...XX......... 16
AUTO_CONFIG_Z2_DONE_CYCLE<1>
XXXX..X.X.XXXX...................X..........XX...XX......... 15
IDE_BASEADR<4> XXXXX...XXXXXX........X..........X.....X....XX...XX......... 18
AUTO_CONFIG_Z2_DONE_CYCLE<0>
XXX..X..X.XXXX...................X..........XX...XX......... 14
IDE_BASEADR<3> XXXXX...XXXXXX.......X...........X......X...XX...XX......... 18
CFOUT ..XXX....................................................... 3
IDE_BASEADR<2> XXXXX...XXXXXX......X............X.......X..XX...XX......... 18
IDE_BASEADR<1> XXXXX...XXXXXX.....X.............X........X.XX...XX......... 18
SLAVE XX............X.XX......X................................... 6
OWN ............................................................ 0
IDE_BASEADR<0> XXXXX...XXXXXX....X..............X.........XXX...XX......... 18
Z3_DATA<28> ...............X.........XXXXXXXX.X.X.......X.......X....... 13
Z3_DATA<27> ...............X.........XXXXXXXX..X.X......X......X........ 13
0----+----1----+----2----+----3----+----4----+----5----+----6
0 0 0 0 0 0
*********************************** FB15 ***********************************
Number of function block inputs used/remaining: 54/0
Number of signals used by logic mapping into function block: 54
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
LAN_BASEADR<12> 6 1<- 0 0 FB15_1 (b) (b)
$OpTx$$OpTx$FX_DC$134_INV$2056
1 0 \/4 0 FB15_2 79 I/O I
LAN_BASEADR<11> 6 4<- \/3 0 FB15_3 80 I/O I
LAN_BASEADR<10> 6 3<- \/2 0 FB15_4 (b) (b)
LAN_BASEADR<0> 6 2<- \/1 0 FB15_5 (b) (b)
CP_WE_S 6 1<- 0 0 FB15_6 (b) (b)
(unused) 0 0 \/4 1 FB15_7 (b) (b)
CP_RD_S 6 4<- \/3 0 FB15_8 81 I/O I
CP_BASEADR<9> 6 3<- \/2 0 FB15_9 (b) (b)
CP_BASEADR<8> 6 2<- \/1 0 FB15_10 82 I/O I
CP_BASEADR<7> 6 1<- 0 0 FB15_11 83 I/O I
DTACK 1 0 \/1 3 FB15_12 85 I/O O
(unused) 0 0 \/5 0 FB15_13 (b) (b)
A<23> 8 6<- \/3 0 FB15_14 86 I/O I/O
A<22> 8 3<- 0 0 FB15_15 87 I/O I/O
(unused) 0 0 \/5 0 FB15_16 (b) (b)
A<21> 8 5<- \/2 0 FB15_17 88 I/O I/O
LAN_BASEADR<13> 6 2<- \/1 0 FB15_18 (b) (b)
Signals Used by Logic in Function Block
1: A<21> 19: DS0 37: LDS
2: A<22> 20: DS1 38: DQ<15>.PIN
3: A<23> 21: FCS 39: DQ<14>.PIN
4: AS 22: LAN_ACCESS 40: DQ<13>.PIN
5: AUTOCONFIG_Z2_ACCESS 23: LAN_BASEADR<0> 41: DQ<7>.PIN
6: AUTO_CONFIG_Z2_DONE<0> 24: LAN_BASEADR<10> 42: DQ<6>.PIN
7: AUTO_CONFIG_Z2_DONE<1> 25: LAN_BASEADR<11> 43: DQ<5>.PIN
8: A<1> 26: LAN_BASEADR<12> 44: D<15>.PIN
9: A<2> 27: LAN_BASEADR<13> 45: D<13>.PIN
10: A<3> 28: LAN_READY 46: D<12>.PIN
11: A<4> 29: LAN_SM_FSM_FFd1 47: D<11>.PIN
12: A<5> 30: LAN_SM_FSM_FFd2 48: D<10>.PIN
13: A<6> 31: LAN_SM_FSM_FFd3 49: D<9>.PIN
14: CP_BASEADR<7> 32: LAN_SM_FSM_FFd4 50: D<8>.PIN
15: CP_BASEADR<8> 33: LAN_SM_FSM_FFd5 51: RESET
16: CP_BASEADR<9> 34: LAN_SM_FSM_FFd6 52: RW
17: CP_CS_BUFR 35: LAN_SM_FSM_FFd7 53: SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF
18: DQ_SWAP 36: LAN_SM_FSM_FFd8 54: UDS
Signal 1 2 3 4 5 6 FB
Name 0----+----0----+----0----+----0----+----0----+----0----+----0 Inputs
LAN_BASEADR<12> ...XXX.XXXXXX............X..........X........X....XXXX...... 16
$OpTx$$OpTx$FX_DC$134_INV$2056
..................XX........................................ 2
LAN_BASEADR<11> ...XXX.XXXXXX...........X...........X.........X...XXXX...... 16
LAN_BASEADR<10> ...XXX.XXXXXX..........X............X..........X..XXXX...... 16
LAN_BASEADR<0> ...XXX.XXXXXX.........X.............X............XXXXX...... 16
CP_WE_S ................X.XXXX......XXXXXXXXX.............XX.X...... 17
CP_RD_S ................X.XXXX......XXXXXXXXX.............XX.X...... 17
CP_BASEADR<9> ...XXXXXXXXXX..X....................X...........X.XXXX...... 17
CP_BASEADR<8> ...XXXXXXXXXX.X.....................X............XXXXX...... 17
CP_BASEADR<7> ...XXXXXXXXXXX......................X......X......XXXX...... 17
DTACK ....................X......X................................ 2
A<23> ..X..............X..XX......XXXXXXXX.X..X.........XX........ 16
A<22> .X...............X..XX......XXXXXXXX..X..X........XX........ 16
A<21> X................X..XX......XXXXXXXX...X..X.......XX........ 16
LAN_BASEADR<13> ...XXX.XXXXXX.............X.........X.......X.....XXXX...... 16
0----+----1----+----2----+----3----+----4----+----5----+----6
0 0 0 0 0 0
*********************************** FB16 ***********************************
Number of function block inputs used/remaining: 54/0
Number of signals used by logic mapping into function block: 54
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
D_Z2_OUT<2> 15 11<- \/1 0 FB16_1 (b) (b)
A<20> 8 3<- 0 0 FB16_2 91 I/O I/O
A<19> 8 5<- /\2 0 FB16_3 92 I/O I/O
(unused) 0 0 /\5 0 FB16_4 (b) (b)
$OpTx$$OpTx$FX_DC$128_INV$2055
1 0 \/4 0 FB16_5 93 I/O I
A<18> 8 4<- \/1 0 FB16_6 94 I/O I/O
(unused) 0 0 \/5 0 FB16_7 (b) (b)
A<17> 8 6<- \/3 0 FB16_8 95 I/O I/O
Z3_DATA<29> 8 3<- 0 0 FB16_9 (b) (b)
MTACK 0 0 \/4 1 FB16_10 96 I/O O
A<16> 8 4<- \/1 0 FB16_11 97 I/O I/O
(unused) 0 0 \/5 0 FB16_12 98 I/O (b)
DQ_DATA<11> 10 6<- \/1 0 FB16_13 (b) (b)
(unused) 0 0 \/5 0 FB16_14 (b) (b)
(unused) 0 0 \/5 0 FB16_15 (b) (b)
LAN_SM_FSM_FFd5 15 11<- \/1 0 FB16_16 (b) (b)
(unused) 0 0 \/5 0 FB16_17 (b) (b)
(unused) 0 0 \/5 0 FB16_18 (b) (b)
Signals Used by Logic in Function Block
1: $OpTx$$OpTx$FX_DC$168_INV$2057 19: DQ_SWAP 37: DQ<11>.PIN
2: A<16> 20: DS0 38: DQ<10>.PIN
3: A<17> 21: DS1 39: DQ<9>.PIN
4: A<18> 22: FCS 40: DQ<8>.PIN
5: A<19> 23: A<11>.PIN 41: DQ<5>.PIN
6: A<20> 24: LAN_ACCESS 42: DQ<4>.PIN
7: AS 25: LAN_SM_FSM_FFd1 43: DQ<3>.PIN
8: AUTOCONFIG_Z2_ACCESS 26: LAN_SM_FSM_FFd2 44: DQ<2>.PIN
9: AUTO_CONFIG_Z2_DONE<0> 27: LAN_SM_FSM_FFd3 45: DQ<1>.PIN
10: AUTO_CONFIG_Z2_DONE<1> 28: LAN_SM_FSM_FFd4 46: DQ<0>.PIN
11: A<1> 29: LAN_SM_FSM_FFd5 47: D<11>.PIN
12: A<2> 30: LAN_SM_FSM_FFd6 48: D<3>.PIN
13: A<3> 31: LAN_SM_FSM_FFd7 49: RESET
14: A<4> 32: LAN_SM_FSM_FFd8 50: RW
15: A<5> 33: LDS 51: SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF
16: A<6> 34: A<19>.PIN 52: UDS
17: CP_CS_BUFR 35: DQ<13>.PIN 53: Z3_ADR<13>
18: DQ_DATA<11> 36: DQ<12>.PIN 54: Z3_DATA<29>
Signal 1 2 3 4 5 6 FB
Name 0----+----0----+----0----+----0----+----0----+----0----+----0 Inputs
D_Z2_OUT<2> ......XXXXXXXXXX................X...............X.XX........ 14
A<20> .....X............X..X.XXXXXXXXX...X.....X......XX.......... 16
A<19> ....X.............X..X.XXXXXXXXX....X.....X.....XX.......... 16
$OpTx$$OpTx$FX_DC$128_INV$2055
................................X..................X........ 2
A<18> ...X..............X..X.XXXXXXXXX.....X.....X....XX.......... 16
A<17> ..X...............X..X.XXXXXXXXX......X.....X...XX.......... 16
Z3_DATA<29> ..................X.....XXXXXXXX..X.....X.......X....X...... 13
MTACK ............................................................ 0
A<16> .X................X..X.XXXXXXXXX.......X.....X..XX.......... 16
DQ_DATA<11> X................XX...X..XXX...XXX............XXX..X........ 14
LAN_SM_FSM_FFd5 ................X..XXX.XXXXXXXXXX...............XX.XX....... 18
0----+----1----+----2----+----3----+----4----+----5----+----6
0 0 0 0 0 0
******************************* Equations ********************************
********** Mapped Logic **********
$OpTx$$OpTx$FX_DC$128_INV$2055 <= (UDS AND LDS);
$OpTx$$OpTx$FX_DC$134_INV$2056 <= (DS1 AND DS0);
$OpTx$$OpTx$FX_DC$168_INV$2057 <= ((LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd6 AND LAN_SM_FSM_FFd1 AND
NOT LAN_SM_FSM_FFd7 AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd5)
OR (NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
NOT LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd6 AND NOT LAN_SM_FSM_FFd7 AND
NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd5));
$OpTx$FX_DC$172 <= ((NOT FCS AND NOT DS1 AND NOT LAN_ACCESS AND NOT CP_CS_BUFR)
OR (NOT RW AND NOT FCS AND UDS AND LDS AND NOT DS1 AND LAN_ACCESS AND
NOT Z3_ADR(13))
OR (NOT RW AND NOT FCS AND UDS AND LDS AND NOT DS0 AND LAN_ACCESS AND
NOT Z3_ADR(13))
OR (NOT FCS AND NOT UDS AND NOT LAN_ACCESS AND NOT CP_CS_BUFR)
OR (NOT FCS AND NOT LDS AND NOT LAN_ACCESS AND NOT CP_CS_BUFR)
OR (NOT FCS AND NOT DS0 AND NOT LAN_ACCESS AND NOT CP_CS_BUFR));
$OpTx$INV$123 <= ((NOT Z3)
OR (SHUT_UP_Z2(0))
OR (D_0_IOBUFE.EXP)
OR (D(11).PIN AND NOT LAN_BASEADR(11))
OR (NOT D(11).PIN AND LAN_BASEADR(11))
OR (D(12).PIN AND NOT LAN_BASEADR(12))
OR (NOT D(12).PIN AND LAN_BASEADR(12))
OR (D(15).PIN AND NOT LAN_BASEADR(15))
OR (D(10).PIN AND NOT LAN_BASEADR(10))
OR (NOT D(10).PIN AND LAN_BASEADR(10))
OR (NOT D(9).PIN AND LAN_BASEADR(9))
OR (D(8).PIN AND NOT LAN_BASEADR(8))
OR (NOT D(8).PIN AND LAN_BASEADR(8))
OR (D(9).PIN AND NOT LAN_BASEADR(9)));
$OpTx$INV$124 <= ((D(14).PIN AND NOT LAN_BASEADR(14))
OR (LAN_BASEADR(5) AND NOT A(21).PIN)
OR (NOT LAN_BASEADR(5) AND A(21).PIN)
OR (LAN_BASEADR(7) AND NOT A(23).PIN)
OR (NOT LAN_BASEADR(7) AND A(23).PIN)
OR (EXP59_.EXP)
OR (LAN_BASEADR(2) AND NOT A(18).PIN)
OR (LAN_BASEADR(3) AND NOT A(19).PIN)
OR (NOT LAN_BASEADR(3) AND A(19).PIN)
OR (LAN_BASEADR(4) AND NOT A(20).PIN)
OR (NOT LAN_BASEADR(4) AND A(20).PIN)
OR (LAN_BASEADR(0) AND NOT A(16).PIN)
OR (NOT LAN_BASEADR(0) AND A(16).PIN)
OR (LAN_BASEADR(1) AND NOT A(17).PIN)
OR (NOT LAN_BASEADR(1) AND A(17).PIN)
OR (NOT LAN_BASEADR(2) AND A(18).PIN));
$OpTx$INV$125 <= ((SHUT_UP_Z2(2))
OR (IDE_BASEADR(5) AND NOT A(21).PIN)
OR (IDE_BASEADR(6) AND NOT A(22).PIN)
OR (NOT IDE_BASEADR(6) AND A(22).PIN)
OR (IDE_BASEADR(7) AND NOT A(23).PIN)
OR (NOT IDE_BASEADR(7) AND A(23).PIN)
OR (IDE_BASEADR(2) AND NOT A(18).PIN)
OR (NOT IDE_BASEADR(2) AND A(18).PIN)
OR (IDE_BASEADR(3) AND NOT A(19).PIN)
OR (NOT IDE_BASEADR(3) AND A(19).PIN)
OR (NOT IDE_BASEADR(5) AND A(21).PIN)
OR (IDE_BASEADR(0) AND NOT A(16).PIN)
OR (NOT IDE_BASEADR(0) AND A(16).PIN)
OR (IDE_BASEADR(1) AND NOT A(17).PIN)
OR (NOT IDE_BASEADR(1) AND A(17).PIN));
FTCPE_A8: FTCPE port map (A_I(8),A_T(8),CLK_EXT,'0',NOT RESET);
A_T(8) <= ((Z3_DATA(22).EXP)
OR (NOT A(8) AND NOT LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd3 AND
DQ(0).PIN)
OR (NOT A(8) AND DQ_SWAP AND NOT LAN_SM_FSM_FFd6 AND
LAN_SM_FSM_FFd5 AND DQ(8).PIN)
OR (NOT A(8) AND NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd6 AND
LAN_SM_FSM_FFd5 AND DQ(0).PIN)
OR (A(8) AND NOT LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd8 AND
LAN_SM_FSM_FFd3 AND LAN_SM_FSM_FFd6 AND NOT LAN_SM_FSM_FFd1 AND
LAN_SM_FSM_FFd7 AND LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5 AND NOT DQ(0).PIN)
OR (A(8) AND LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
LAN_SM_FSM_FFd3 AND DQ_SWAP AND NOT LAN_SM_FSM_FFd6 AND LAN_SM_FSM_FFd1 AND
NOT LAN_SM_FSM_FFd7 AND LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5 AND NOT DQ(8).PIN));
A(8) <= A_I(8) when A_OE(8) = '1' else 'Z';
A_OE(8) <= (RW AND NOT FCS AND LAN_ACCESS);
FTCPE_A9: FTCPE port map (A_I(9),A_T(9),CLK_EXT,'0',NOT RESET);
A_T(9) <= ((CP_BASEADR(13).EXP)
OR (NOT A(9) AND NOT LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd3 AND
DQ(1).PIN)
OR (NOT A(9) AND DQ_SWAP AND NOT LAN_SM_FSM_FFd6 AND
LAN_SM_FSM_FFd5 AND DQ(9).PIN)
OR (NOT A(9) AND NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd6 AND
LAN_SM_FSM_FFd5 AND DQ(1).PIN)
OR (A(9) AND NOT LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd8 AND
LAN_SM_FSM_FFd3 AND LAN_SM_FSM_FFd6 AND NOT LAN_SM_FSM_FFd1 AND
LAN_SM_FSM_FFd7 AND LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5 AND NOT DQ(1).PIN)
OR (A(9) AND LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
LAN_SM_FSM_FFd3 AND NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd6 AND LAN_SM_FSM_FFd1 AND
NOT LAN_SM_FSM_FFd7 AND LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5 AND NOT DQ(1).PIN));
A(9) <= A_I(9) when A_OE(9) = '1' else 'Z';
A_OE(9) <= (RW AND NOT FCS AND LAN_ACCESS);
FTCPE_A10: FTCPE port map (A_I(10),A_T(10),CLK_EXT,'0',NOT RESET);
A_T(10) <= ((NOT A(10) AND DQ_SWAP AND NOT LAN_SM_FSM_FFd6 AND
LAN_SM_FSM_FFd5 AND DQ(10).PIN)
OR (NOT A(10) AND NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd6 AND
LAN_SM_FSM_FFd5 AND DQ(2).PIN)
OR (A(10) AND NOT LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd8 AND
LAN_SM_FSM_FFd3 AND LAN_SM_FSM_FFd6 AND NOT LAN_SM_FSM_FFd1 AND
LAN_SM_FSM_FFd7 AND LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5 AND NOT DQ(2).PIN)
OR (A(10) AND LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
LAN_SM_FSM_FFd3 AND DQ_SWAP AND NOT LAN_SM_FSM_FFd6 AND LAN_SM_FSM_FFd1 AND
NOT LAN_SM_FSM_FFd7 AND LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5 AND NOT DQ(10).PIN)
OR (A(10) AND LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
LAN_SM_FSM_FFd3 AND NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd6 AND LAN_SM_FSM_FFd1 AND
NOT LAN_SM_FSM_FFd7 AND LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5 AND NOT DQ(2).PIN)
OR (NOT A(10) AND NOT LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd3 AND
DQ(2).PIN));
A(10) <= A_I(10) when A_OE(10) = '1' else 'Z';
A_OE(10) <= (RW AND NOT FCS AND LAN_ACCESS);
FTCPE_A11: FTCPE port map (A_I(11),A_T(11),CLK_EXT,'0',NOT RESET);
A_T(11) <= ((A(11) AND NOT LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd8 AND
LAN_SM_FSM_FFd3 AND LAN_SM_FSM_FFd6 AND NOT LAN_SM_FSM_FFd1 AND
LAN_SM_FSM_FFd7 AND LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5 AND NOT DQ(3).PIN)
OR (A(11) AND LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
LAN_SM_FSM_FFd3 AND DQ_SWAP AND NOT LAN_SM_FSM_FFd6 AND LAN_SM_FSM_FFd1 AND
NOT LAN_SM_FSM_FFd7 AND LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5 AND NOT DQ(11).PIN)
OR (A(11) AND LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
LAN_SM_FSM_FFd3 AND NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd6 AND LAN_SM_FSM_FFd1 AND
NOT LAN_SM_FSM_FFd7 AND LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5 AND NOT DQ(3).PIN)
OR (NOT A(11) AND NOT LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd3 AND
DQ(3).PIN)
OR (NOT A(11) AND DQ_SWAP AND NOT LAN_SM_FSM_FFd6 AND
LAN_SM_FSM_FFd5 AND DQ(11).PIN)
OR (NOT A(11) AND NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd6 AND
LAN_SM_FSM_FFd5 AND DQ(3).PIN));
A(11) <= A_I(11) when A_OE(11) = '1' else 'Z';
A_OE(11) <= (RW AND NOT FCS AND LAN_ACCESS);
FTCPE_A12: FTCPE port map (A_I(12),A_T(12),CLK_EXT,'0',NOT RESET);
A_T(12) <= ((NOT A(12) AND DQ_SWAP AND NOT LAN_SM_FSM_FFd6 AND
LAN_SM_FSM_FFd5 AND DQ(12).PIN)
OR (NOT A(12) AND NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd6 AND
LAN_SM_FSM_FFd5 AND DQ(4).PIN)
OR (A(12) AND NOT LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd8 AND
LAN_SM_FSM_FFd3 AND LAN_SM_FSM_FFd6 AND NOT LAN_SM_FSM_FFd1 AND
LAN_SM_FSM_FFd7 AND LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5 AND NOT DQ(4).PIN)
OR (A(12) AND LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
LAN_SM_FSM_FFd3 AND DQ_SWAP AND NOT LAN_SM_FSM_FFd6 AND LAN_SM_FSM_FFd1 AND
NOT LAN_SM_FSM_FFd7 AND LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5 AND NOT DQ(12).PIN)
OR (A(12) AND LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
LAN_SM_FSM_FFd3 AND NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd6 AND LAN_SM_FSM_FFd1 AND
NOT LAN_SM_FSM_FFd7 AND LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5 AND NOT DQ(4).PIN)
OR (NOT A(12) AND NOT LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd3 AND
DQ(4).PIN));
A(12) <= A_I(12) when A_OE(12) = '1' else 'Z';
A_OE(12) <= (RW AND NOT FCS AND LAN_ACCESS);
FTCPE_A13: FTCPE port map (A_I(13),A_T(13),CLK_EXT,'0',NOT RESET);
A_T(13) <= ((A(13) AND NOT LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd8 AND
LAN_SM_FSM_FFd3 AND LAN_SM_FSM_FFd6 AND NOT LAN_SM_FSM_FFd1 AND
LAN_SM_FSM_FFd7 AND LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5 AND NOT DQ(5).PIN)
OR (A(13) AND LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
LAN_SM_FSM_FFd3 AND DQ_SWAP AND NOT LAN_SM_FSM_FFd6 AND LAN_SM_FSM_FFd1 AND
NOT LAN_SM_FSM_FFd7 AND LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5 AND NOT DQ(13).PIN)
OR (A(13) AND LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
LAN_SM_FSM_FFd3 AND NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd6 AND LAN_SM_FSM_FFd1 AND
NOT LAN_SM_FSM_FFd7 AND LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5 AND NOT DQ(5).PIN)
OR (NOT A(13) AND NOT LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd3 AND
DQ(5).PIN)
OR (NOT A(13) AND DQ_SWAP AND NOT LAN_SM_FSM_FFd6 AND
LAN_SM_FSM_FFd5 AND DQ(13).PIN)
OR (NOT A(13) AND NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd6 AND
LAN_SM_FSM_FFd5 AND DQ(5).PIN));
A(13) <= A_I(13) when A_OE(13) = '1' else 'Z';
A_OE(13) <= (RW AND NOT FCS AND LAN_ACCESS);
FTCPE_A14: FTCPE port map (A_I(14),A_T(14),CLK_EXT,'0',NOT RESET);
A_T(14) <= ((NOT A(14) AND NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd6 AND
LAN_SM_FSM_FFd5 AND DQ(6).PIN)
OR (A(14) AND NOT LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd8 AND
LAN_SM_FSM_FFd3 AND LAN_SM_FSM_FFd6 AND NOT LAN_SM_FSM_FFd1 AND
LAN_SM_FSM_FFd7 AND LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5 AND NOT DQ(6).PIN)
OR (A(14) AND LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
LAN_SM_FSM_FFd3 AND DQ_SWAP AND NOT LAN_SM_FSM_FFd6 AND LAN_SM_FSM_FFd1 AND
NOT LAN_SM_FSM_FFd7 AND LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5 AND NOT DQ(14).PIN)
OR (A(14) AND LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
LAN_SM_FSM_FFd3 AND NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd6 AND LAN_SM_FSM_FFd1 AND
NOT LAN_SM_FSM_FFd7 AND LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5 AND NOT DQ(6).PIN)
OR (NOT A(14) AND NOT LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd3 AND
DQ(6).PIN)
OR (NOT A(14) AND DQ_SWAP AND NOT LAN_SM_FSM_FFd6 AND
LAN_SM_FSM_FFd5 AND DQ(14).PIN));
A(14) <= A_I(14) when A_OE(14) = '1' else 'Z';
A_OE(14) <= (RW AND NOT FCS AND LAN_ACCESS);
FTCPE_A15: FTCPE port map (A_I(15),A_T(15),CLK_EXT,'0',NOT RESET);
A_T(15) <= ((A(15) AND NOT LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd8 AND
LAN_SM_FSM_FFd3 AND LAN_SM_FSM_FFd6 AND NOT LAN_SM_FSM_FFd1 AND
LAN_SM_FSM_FFd7 AND LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5 AND NOT DQ(7).PIN)
OR (A(15) AND LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
LAN_SM_FSM_FFd3 AND DQ_SWAP AND NOT LAN_SM_FSM_FFd6 AND LAN_SM_FSM_FFd1 AND
NOT LAN_SM_FSM_FFd7 AND LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5 AND NOT DQ(15).PIN)
OR (A(15) AND LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
LAN_SM_FSM_FFd3 AND NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd6 AND LAN_SM_FSM_FFd1 AND
NOT LAN_SM_FSM_FFd7 AND LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5 AND NOT DQ(7).PIN)
OR (NOT A(15) AND NOT LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd3 AND
DQ(7).PIN)
OR (NOT A(15) AND DQ_SWAP AND NOT LAN_SM_FSM_FFd6 AND
LAN_SM_FSM_FFd5 AND DQ(15).PIN)
OR (NOT A(15) AND NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd6 AND
LAN_SM_FSM_FFd5 AND DQ(7).PIN));
A(15) <= A_I(15) when A_OE(15) = '1' else 'Z';
A_OE(15) <= (RW AND NOT FCS AND LAN_ACCESS);
FTCPE_A16: FTCPE port map (A_I(16),A_T(16),CLK_EXT,'0',NOT RESET);
A_T(16) <= ((NOT A(16) AND NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd6 AND
LAN_SM_FSM_FFd5 AND DQ(8).PIN)
OR (A(16) AND NOT LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd8 AND
LAN_SM_FSM_FFd3 AND LAN_SM_FSM_FFd6 AND NOT LAN_SM_FSM_FFd1 AND
LAN_SM_FSM_FFd7 AND LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5 AND NOT DQ(8).PIN)
OR (A(16) AND LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
LAN_SM_FSM_FFd3 AND DQ_SWAP AND NOT LAN_SM_FSM_FFd6 AND LAN_SM_FSM_FFd1 AND
NOT LAN_SM_FSM_FFd7 AND LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5 AND NOT DQ(0).PIN)
OR (A(16) AND LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
LAN_SM_FSM_FFd3 AND NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd6 AND LAN_SM_FSM_FFd1 AND
NOT LAN_SM_FSM_FFd7 AND LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5 AND NOT DQ(8).PIN)
OR (NOT A(16) AND NOT LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd3 AND
DQ(8).PIN)
OR (NOT A(16) AND DQ_SWAP AND NOT LAN_SM_FSM_FFd6 AND
LAN_SM_FSM_FFd5 AND DQ(0).PIN));
A(16) <= A_I(16) when A_OE(16) = '1' else 'Z';
A_OE(16) <= (RW AND NOT FCS AND LAN_ACCESS);
FTCPE_A17: FTCPE port map (A_I(17),A_T(17),CLK_EXT,'0',NOT RESET);
A_T(17) <= ((Z3_DATA(10).EXP)
OR (NOT A(17) AND NOT LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd3 AND
DQ(9).PIN)
OR (NOT A(17) AND DQ_SWAP AND NOT LAN_SM_FSM_FFd6 AND
LAN_SM_FSM_FFd5 AND DQ(1).PIN)
OR (NOT A(17) AND NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd6 AND
LAN_SM_FSM_FFd5 AND DQ(9).PIN)
OR (A(17) AND NOT LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd8 AND
LAN_SM_FSM_FFd3 AND LAN_SM_FSM_FFd6 AND NOT LAN_SM_FSM_FFd1 AND
LAN_SM_FSM_FFd7 AND LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5 AND NOT DQ(9).PIN)
OR (A(17) AND LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
LAN_SM_FSM_FFd3 AND DQ_SWAP AND NOT LAN_SM_FSM_FFd6 AND LAN_SM_FSM_FFd1 AND
NOT LAN_SM_FSM_FFd7 AND LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5 AND NOT DQ(1).PIN));
A(17) <= A_I(17) when A_OE(17) = '1' else 'Z';
A_OE(17) <= (RW AND NOT FCS AND LAN_ACCESS);
FTCPE_A18: FTCPE port map (A_I(18),A_T(18),CLK_EXT,'0',NOT RESET);
A_T(18) <= ((NOT A(18) AND DQ_SWAP AND NOT LAN_SM_FSM_FFd6 AND
LAN_SM_FSM_FFd5 AND DQ(2).PIN)
OR (A(18) AND NOT LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd8 AND
LAN_SM_FSM_FFd3 AND LAN_SM_FSM_FFd6 AND NOT LAN_SM_FSM_FFd1 AND
LAN_SM_FSM_FFd7 AND LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5 AND NOT DQ(10).PIN)
OR (A(18) AND LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
LAN_SM_FSM_FFd3 AND DQ_SWAP AND NOT LAN_SM_FSM_FFd6 AND LAN_SM_FSM_FFd1 AND
NOT LAN_SM_FSM_FFd7 AND LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5 AND NOT DQ(2).PIN)
OR (A(18) AND LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
LAN_SM_FSM_FFd3 AND NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd6 AND LAN_SM_FSM_FFd1 AND
NOT LAN_SM_FSM_FFd7 AND LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5 AND NOT DQ(10).PIN)
OR (NOT A(18) AND NOT LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd3 AND
DQ(10).PIN)
OR (NOT A(18) AND NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd6 AND
LAN_SM_FSM_FFd5 AND DQ(10).PIN));
A(18) <= A_I(18) when A_OE(18) = '1' else 'Z';
A_OE(18) <= (RW AND NOT FCS AND LAN_ACCESS);
FTCPE_A19: FTCPE port map (A_I(19),A_T(19),CLK_EXT,'0',NOT RESET);
A_T(19) <= ((NOT A(19) AND DQ_SWAP AND NOT LAN_SM_FSM_FFd6 AND
LAN_SM_FSM_FFd5 AND DQ(3).PIN)
OR (NOT A(19) AND NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd6 AND
LAN_SM_FSM_FFd5 AND DQ(11).PIN)
OR (A(19) AND NOT LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd8 AND
LAN_SM_FSM_FFd3 AND LAN_SM_FSM_FFd6 AND NOT LAN_SM_FSM_FFd1 AND
LAN_SM_FSM_FFd7 AND LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5 AND NOT DQ(11).PIN)
OR (A(19) AND LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
LAN_SM_FSM_FFd3 AND DQ_SWAP AND NOT LAN_SM_FSM_FFd6 AND LAN_SM_FSM_FFd1 AND
NOT LAN_SM_FSM_FFd7 AND LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5 AND NOT DQ(3).PIN)
OR (A(19) AND LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
LAN_SM_FSM_FFd3 AND NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd6 AND LAN_SM_FSM_FFd1 AND
NOT LAN_SM_FSM_FFd7 AND LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5 AND NOT DQ(11).PIN)
OR (NOT A(19) AND NOT LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd3 AND
DQ(11).PIN));
A(19) <= A_I(19) when A_OE(19) = '1' else 'Z';
A_OE(19) <= (RW AND NOT FCS AND LAN_ACCESS);
FTCPE_A20: FTCPE port map (A_I(20),A_T(20),CLK_EXT,'0',NOT RESET);
A_T(20) <= ((A(20) AND NOT LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd8 AND
LAN_SM_FSM_FFd3 AND LAN_SM_FSM_FFd6 AND NOT LAN_SM_FSM_FFd1 AND
LAN_SM_FSM_FFd7 AND LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5 AND NOT DQ(12).PIN)
OR (A(20) AND LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
LAN_SM_FSM_FFd3 AND DQ_SWAP AND NOT LAN_SM_FSM_FFd6 AND LAN_SM_FSM_FFd1 AND
NOT LAN_SM_FSM_FFd7 AND LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5 AND NOT DQ(4).PIN)
OR (A(20) AND LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
LAN_SM_FSM_FFd3 AND NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd6 AND LAN_SM_FSM_FFd1 AND
NOT LAN_SM_FSM_FFd7 AND LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5 AND NOT DQ(12).PIN)
OR (NOT A(20) AND NOT LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd3 AND
DQ(12).PIN)
OR (NOT A(20) AND DQ_SWAP AND NOT LAN_SM_FSM_FFd6 AND
LAN_SM_FSM_FFd5 AND DQ(4).PIN)
OR (NOT A(20) AND NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd6 AND
LAN_SM_FSM_FFd5 AND DQ(12).PIN));
A(20) <= A_I(20) when A_OE(20) = '1' else 'Z';
A_OE(20) <= (RW AND NOT FCS AND LAN_ACCESS);
FTCPE_A21: FTCPE port map (A_I(21),A_T(21),CLK_EXT,'0',NOT RESET);
A_T(21) <= ((NOT A(21) AND DQ_SWAP AND NOT LAN_SM_FSM_FFd6 AND
LAN_SM_FSM_FFd5 AND DQ(5).PIN)
OR (NOT A(21) AND NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd6 AND
LAN_SM_FSM_FFd5 AND DQ(13).PIN)
OR (A(21) AND NOT LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd8 AND
LAN_SM_FSM_FFd3 AND LAN_SM_FSM_FFd6 AND NOT LAN_SM_FSM_FFd1 AND
LAN_SM_FSM_FFd7 AND LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5 AND NOT DQ(13).PIN)
OR (A(21) AND LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
LAN_SM_FSM_FFd3 AND DQ_SWAP AND NOT LAN_SM_FSM_FFd6 AND LAN_SM_FSM_FFd1 AND
NOT LAN_SM_FSM_FFd7 AND LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5 AND NOT DQ(5).PIN)
OR (A(21) AND LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
LAN_SM_FSM_FFd3 AND NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd6 AND LAN_SM_FSM_FFd1 AND
NOT LAN_SM_FSM_FFd7 AND LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5 AND NOT DQ(13).PIN)
OR (NOT A(21) AND NOT LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd3 AND
DQ(13).PIN));
A(21) <= A_I(21) when A_OE(21) = '1' else 'Z';
A_OE(21) <= (RW AND NOT FCS AND LAN_ACCESS);
FTCPE_A22: FTCPE port map (A_I(22),A_T(22),CLK_EXT,'0',NOT RESET);
A_T(22) <= ((A(22) AND NOT LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd8 AND
LAN_SM_FSM_FFd3 AND LAN_SM_FSM_FFd6 AND NOT LAN_SM_FSM_FFd1 AND
LAN_SM_FSM_FFd7 AND LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5 AND NOT DQ(14).PIN)
OR (A(22) AND LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
LAN_SM_FSM_FFd3 AND DQ_SWAP AND NOT LAN_SM_FSM_FFd6 AND LAN_SM_FSM_FFd1 AND
NOT LAN_SM_FSM_FFd7 AND LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5 AND NOT DQ(6).PIN)
OR (A(22) AND LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
LAN_SM_FSM_FFd3 AND NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd6 AND LAN_SM_FSM_FFd1 AND
NOT LAN_SM_FSM_FFd7 AND LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5 AND NOT DQ(14).PIN)
OR (NOT A(22) AND NOT LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd3 AND
DQ(14).PIN)
OR (NOT A(22) AND DQ_SWAP AND NOT LAN_SM_FSM_FFd6 AND
LAN_SM_FSM_FFd5 AND DQ(6).PIN)
OR (NOT A(22) AND NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd6 AND
LAN_SM_FSM_FFd5 AND DQ(14).PIN));
A(22) <= A_I(22) when A_OE(22) = '1' else 'Z';
A_OE(22) <= (RW AND NOT FCS AND LAN_ACCESS);
FTCPE_A23: FTCPE port map (A_I(23),A_T(23),CLK_EXT,'0',NOT RESET);
A_T(23) <= ((ROM_B_0_OBUF$BUF10.EXP)
OR (NOT A(23) AND NOT LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd3 AND
DQ(15).PIN)
OR (NOT A(23) AND DQ_SWAP AND NOT LAN_SM_FSM_FFd6 AND
LAN_SM_FSM_FFd5 AND DQ(7).PIN)
OR (NOT A(23) AND NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd6 AND
LAN_SM_FSM_FFd5 AND DQ(15).PIN)
OR (A(23) AND NOT LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd8 AND
LAN_SM_FSM_FFd3 AND LAN_SM_FSM_FFd6 AND NOT LAN_SM_FSM_FFd1 AND
LAN_SM_FSM_FFd7 AND LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5 AND NOT DQ(15).PIN)
OR (A(23) AND LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
LAN_SM_FSM_FFd3 AND NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd6 AND LAN_SM_FSM_FFd1 AND
NOT LAN_SM_FSM_FFd7 AND LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5 AND NOT DQ(15).PIN));
A(23) <= A_I(23) when A_OE(23) = '1' else 'Z';
A_OE(23) <= (RW AND NOT FCS AND LAN_ACCESS);
FDCPE_AUTOCONFIG_Z2_ACCESS: FDCPE port map (AUTOCONFIG_Z2_ACCESS,AUTOCONFIG_Z2_ACCESS_D,NOT AS,NOT RESET,'0');
AUTOCONFIG_Z2_ACCESS_D <= ((NOT AUTO_CONFIG_Z2_DONE(0) AND A(23).PIN AND A(22).PIN AND
A(21).PIN AND A(19).PIN AND NOT CFIN AND NOT A(17).PIN AND NOT A(16).PIN AND
NOT A(20).PIN AND NOT A(18).PIN)
OR (NOT AUTO_CONFIG_Z2_DONE(1) AND A(23).PIN AND A(22).PIN AND
A(21).PIN AND A(19).PIN AND NOT CFIN AND NOT A(17).PIN AND NOT A(16).PIN AND
NOT A(20).PIN AND NOT A(18).PIN)
OR (NOT AUTO_CONFIG_Z2_DONE(2) AND A(23).PIN AND A(22).PIN AND
A(21).PIN AND A(19).PIN AND NOT CFIN AND NOT A(17).PIN AND NOT A(16).PIN AND
NOT A(20).PIN AND NOT A(18).PIN));
FDCPE_AUTO_CONFIG_Z2_DONE0: FDCPE port map (AUTO_CONFIG_Z2_DONE(0),AUTO_CONFIG_Z2_DONE_D(0),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,NOT RESET,'0',AS);
AUTO_CONFIG_Z2_DONE_D(0) <= (NOT AUTO_CONFIG_Z2_DONE(0) AND
NOT AUTO_CONFIG_Z2_DONE_CYCLE(0));
FDCPE_AUTO_CONFIG_Z2_DONE1: FDCPE port map (AUTO_CONFIG_Z2_DONE(1),AUTO_CONFIG_Z2_DONE_D(1),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,NOT RESET,'0',AS);
AUTO_CONFIG_Z2_DONE_D(1) <= (NOT AUTO_CONFIG_Z2_DONE(1) AND
NOT AUTO_CONFIG_Z2_DONE_CYCLE(1));
FDCPE_AUTO_CONFIG_Z2_DONE2: FDCPE port map (AUTO_CONFIG_Z2_DONE(2),AUTO_CONFIG_Z2_DONE_D(2),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,NOT RESET,'0',AS);
AUTO_CONFIG_Z2_DONE_D(2) <= (NOT AUTO_CONFIG_Z2_DONE(2) AND
NOT AUTO_CONFIG_Z2_DONE_CYCLE(2));
FTCPE_AUTO_CONFIG_Z2_DONE_CYCLE0: FTCPE port map (AUTO_CONFIG_Z2_DONE_CYCLE(0),AUTO_CONFIG_Z2_DONE_CYCLE_T(0),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,NOT RESET,'0');
AUTO_CONFIG_Z2_DONE_CYCLE_T(0) <= ((NOT RW AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(0) AND NOT UDS AND
NOT AUTO_CONFIG_Z2_DONE_CYCLE(0) AND NOT A(5) AND NOT A(4) AND AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND
A(6) AND A(3))
OR (NOT RW AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(0) AND NOT LDS AND
NOT AUTO_CONFIG_Z2_DONE_CYCLE(0) AND NOT A(5) AND NOT A(4) AND AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND
A(6) AND A(3)));
FTCPE_AUTO_CONFIG_Z2_DONE_CYCLE1: FTCPE port map (AUTO_CONFIG_Z2_DONE_CYCLE(1),AUTO_CONFIG_Z2_DONE_CYCLE_T(1),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,NOT RESET,'0');
AUTO_CONFIG_Z2_DONE_CYCLE_T(1) <= ((NOT RW AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND
NOT AUTO_CONFIG_Z2_DONE(1) AND NOT UDS AND NOT AUTO_CONFIG_Z2_DONE_CYCLE(1) AND NOT A(5) AND
NOT A(4) AND AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND A(3))
OR (NOT RW AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND
NOT AUTO_CONFIG_Z2_DONE(1) AND NOT LDS AND NOT AUTO_CONFIG_Z2_DONE_CYCLE(1) AND NOT A(5) AND
NOT A(4) AND AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND A(3)));
FTCPE_AUTO_CONFIG_Z2_DONE_CYCLE2: FTCPE port map (AUTO_CONFIG_Z2_DONE_CYCLE(2),AUTO_CONFIG_Z2_DONE_CYCLE_T(2),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,NOT RESET,'0');
AUTO_CONFIG_Z2_DONE_CYCLE_T(2) <= ((NOT RW AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND
AUTO_CONFIG_Z2_DONE(1) AND NOT UDS AND NOT AUTO_CONFIG_Z2_DONE(2) AND
NOT AUTO_CONFIG_Z2_DONE_CYCLE(2) AND NOT A(5) AND NOT A(4) AND AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND
A(6) AND A(3))
OR (NOT RW AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND
AUTO_CONFIG_Z2_DONE(1) AND NOT LDS AND NOT AUTO_CONFIG_Z2_DONE(2) AND
NOT AUTO_CONFIG_Z2_DONE_CYCLE(2) AND NOT A(5) AND NOT A(4) AND AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND
A(6) AND A(3)));
A_LAN(0) <= NOT ((RESET AND NOT Z3_A_LOW));
A_LAN(1) <= NOT ((RESET AND NOT Z3_ADR_0));
A_LAN(2) <= NOT (((RESET AND NOT A(2) AND NOT CP_CS_BUFR)
OR (RESET AND NOT Z3_ADR_1 AND CP_CS_BUFR)));
A_LAN(3) <= ((NOT RESET AND LAN_A_INIT(3))
OR (RESET AND Z3_ADR(2) AND CP_CS_BUFR)
OR (RESET AND A(3) AND NOT CP_CS_BUFR));
A_LAN(4) <= NOT (((RESET AND NOT A(4) AND NOT CP_CS_BUFR)
OR (RESET AND NOT Z3_ADR(3) AND CP_CS_BUFR)));
A_LAN(5) <= NOT (((RESET AND NOT A(5) AND NOT CP_CS_BUFR)
OR (RESET AND NOT Z3_ADR(4) AND CP_CS_BUFR)));
A_LAN(6) <= ((RESET AND Z3_ADR(5))
OR (NOT RESET AND LAN_A_INIT(6)));
A_LAN(7) <= NOT ((RESET AND NOT Z3_ADR(6)));
A_LAN(8) <= NOT ((RESET AND NOT Z3_ADR(7)));
A_LAN(9) <= NOT ((RESET AND NOT Z3_ADR(8)));
A_LAN(10) <= NOT ((RESET AND NOT Z3_ADR(9)));
A_LAN(11) <= NOT ((RESET AND NOT Z3_ADR(10)));
A_LAN(12) <= NOT ((RESET AND NOT Z3_ADR(11)));
A_LAN(13) <= NOT ((RESET AND NOT Z3_ADR(12)));
CFOUT <= NOT ((AUTO_CONFIG_Z2_DONE(0) AND AUTO_CONFIG_Z2_DONE(1) AND
AUTO_CONFIG_Z2_DONE(2)));
FTCPE_CP_BASEADR0: FTCPE port map (CP_BASEADR(0),CP_BASEADR_T(0),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET);
CP_BASEADR_T(0) <= ((NOT RW AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND
NOT AUTO_CONFIG_Z2_DONE(1) AND NOT LDS AND D(8).PIN AND NOT CP_BASEADR(0) AND NOT A(2) AND NOT A(5) AND
NOT A(4) AND AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND A(3))
OR (NOT RW AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND
NOT AUTO_CONFIG_Z2_DONE(1) AND NOT UDS AND D(8).PIN AND NOT CP_BASEADR(0) AND NOT A(2) AND NOT A(5) AND
NOT A(4) AND AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND A(3))
OR (NOT RW AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND
NOT AUTO_CONFIG_Z2_DONE(1) AND NOT UDS AND NOT D(8).PIN AND CP_BASEADR(0) AND NOT A(2) AND NOT A(5) AND
NOT A(4) AND AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND A(3))
OR (NOT RW AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND
NOT AUTO_CONFIG_Z2_DONE(1) AND NOT LDS AND NOT D(8).PIN AND CP_BASEADR(0) AND NOT A(2) AND NOT A(5) AND
NOT A(4) AND AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND A(3)));
FTCPE_CP_BASEADR1: FTCPE port map (CP_BASEADR(1),CP_BASEADR_T(1),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET);
CP_BASEADR_T(1) <= ((NOT RW AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND
NOT AUTO_CONFIG_Z2_DONE(1) AND NOT LDS AND D(9).PIN AND NOT CP_BASEADR(1) AND NOT A(2) AND NOT A(5) AND
NOT A(4) AND AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND A(3))
OR (NOT RW AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND
NOT AUTO_CONFIG_Z2_DONE(1) AND NOT UDS AND D(9).PIN AND NOT CP_BASEADR(1) AND NOT A(2) AND NOT A(5) AND
NOT A(4) AND AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND A(3))
OR (NOT RW AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND
NOT AUTO_CONFIG_Z2_DONE(1) AND NOT UDS AND NOT D(9).PIN AND CP_BASEADR(1) AND NOT A(2) AND NOT A(5) AND
NOT A(4) AND AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND A(3))
OR (NOT RW AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND
NOT AUTO_CONFIG_Z2_DONE(1) AND NOT LDS AND NOT D(9).PIN AND CP_BASEADR(1) AND NOT A(2) AND NOT A(5) AND
NOT A(4) AND AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND A(3)));
FTCPE_CP_BASEADR2: FTCPE port map (CP_BASEADR(2),CP_BASEADR_T(2),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET);
CP_BASEADR_T(2) <= ((NOT RW AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND
NOT AUTO_CONFIG_Z2_DONE(1) AND NOT LDS AND D(10).PIN AND NOT CP_BASEADR(2) AND NOT A(2) AND NOT A(5) AND
NOT A(4) AND AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND A(3))
OR (NOT RW AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND
NOT AUTO_CONFIG_Z2_DONE(1) AND NOT UDS AND D(10).PIN AND NOT CP_BASEADR(2) AND NOT A(2) AND NOT A(5) AND
NOT A(4) AND AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND A(3))
OR (NOT RW AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND
NOT AUTO_CONFIG_Z2_DONE(1) AND NOT UDS AND NOT D(10).PIN AND CP_BASEADR(2) AND NOT A(2) AND NOT A(5) AND
NOT A(4) AND AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND A(3))
OR (NOT RW AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND
NOT AUTO_CONFIG_Z2_DONE(1) AND NOT LDS AND NOT D(10).PIN AND CP_BASEADR(2) AND NOT A(2) AND NOT A(5) AND
NOT A(4) AND AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND A(3)));
FTCPE_CP_BASEADR3: FTCPE port map (CP_BASEADR(3),CP_BASEADR_T(3),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET);
CP_BASEADR_T(3) <= ((NOT RW AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND
NOT AUTO_CONFIG_Z2_DONE(1) AND NOT LDS AND D(11).PIN AND NOT CP_BASEADR(3) AND NOT A(2) AND NOT A(5) AND
NOT A(4) AND AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND A(3))
OR (NOT RW AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND
NOT AUTO_CONFIG_Z2_DONE(1) AND NOT UDS AND D(11).PIN AND NOT CP_BASEADR(3) AND NOT A(2) AND NOT A(5) AND
NOT A(4) AND AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND A(3))
OR (NOT RW AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND
NOT AUTO_CONFIG_Z2_DONE(1) AND NOT UDS AND NOT D(11).PIN AND CP_BASEADR(3) AND NOT A(2) AND NOT A(5) AND
NOT A(4) AND AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND A(3))
OR (NOT RW AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND
NOT AUTO_CONFIG_Z2_DONE(1) AND NOT LDS AND NOT D(11).PIN AND CP_BASEADR(3) AND NOT A(2) AND NOT A(5) AND
NOT A(4) AND AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND A(3)));
FTCPE_CP_BASEADR4: FTCPE port map (CP_BASEADR(4),CP_BASEADR_T(4),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET);
CP_BASEADR_T(4) <= ((NOT RW AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND
NOT AUTO_CONFIG_Z2_DONE(1) AND NOT LDS AND D(12).PIN AND NOT CP_BASEADR(4) AND NOT A(2) AND NOT A(5) AND
NOT A(4) AND AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND A(3))
OR (NOT RW AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND
NOT AUTO_CONFIG_Z2_DONE(1) AND NOT UDS AND D(12).PIN AND NOT CP_BASEADR(4) AND NOT A(2) AND NOT A(5) AND
NOT A(4) AND AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND A(3))
OR (NOT RW AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND
NOT AUTO_CONFIG_Z2_DONE(1) AND NOT UDS AND NOT D(12).PIN AND CP_BASEADR(4) AND NOT A(2) AND NOT A(5) AND
NOT A(4) AND AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND A(3))
OR (NOT RW AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND
NOT AUTO_CONFIG_Z2_DONE(1) AND NOT LDS AND NOT D(12).PIN AND CP_BASEADR(4) AND NOT A(2) AND NOT A(5) AND
NOT A(4) AND AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND A(3)));
FTCPE_CP_BASEADR5: FTCPE port map (CP_BASEADR(5),CP_BASEADR_T(5),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET);
CP_BASEADR_T(5) <= ((NOT RW AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND
NOT AUTO_CONFIG_Z2_DONE(1) AND NOT LDS AND D(13).PIN AND NOT CP_BASEADR(5) AND NOT A(2) AND NOT A(5) AND
NOT A(4) AND AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND A(3))
OR (NOT RW AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND
NOT AUTO_CONFIG_Z2_DONE(1) AND NOT UDS AND D(13).PIN AND NOT CP_BASEADR(5) AND NOT A(2) AND NOT A(5) AND
NOT A(4) AND AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND A(3))
OR (NOT RW AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND
NOT AUTO_CONFIG_Z2_DONE(1) AND NOT UDS AND NOT D(13).PIN AND CP_BASEADR(5) AND NOT A(2) AND NOT A(5) AND
NOT A(4) AND AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND A(3))
OR (NOT RW AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND
NOT AUTO_CONFIG_Z2_DONE(1) AND NOT LDS AND NOT D(13).PIN AND CP_BASEADR(5) AND NOT A(2) AND NOT A(5) AND
NOT A(4) AND AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND A(3)));
FTCPE_CP_BASEADR6: FTCPE port map (CP_BASEADR(6),CP_BASEADR_T(6),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET);
CP_BASEADR_T(6) <= ((NOT RW AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND
NOT AUTO_CONFIG_Z2_DONE(1) AND NOT LDS AND D(14).PIN AND NOT CP_BASEADR(6) AND NOT A(2) AND NOT A(5) AND
NOT A(4) AND AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND A(3))
OR (NOT RW AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND
NOT AUTO_CONFIG_Z2_DONE(1) AND NOT UDS AND D(14).PIN AND NOT CP_BASEADR(6) AND NOT A(2) AND NOT A(5) AND
NOT A(4) AND AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND A(3))
OR (NOT RW AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND
NOT AUTO_CONFIG_Z2_DONE(1) AND NOT UDS AND NOT D(14).PIN AND CP_BASEADR(6) AND NOT A(2) AND NOT A(5) AND
NOT A(4) AND AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND A(3))
OR (NOT RW AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND
NOT AUTO_CONFIG_Z2_DONE(1) AND NOT LDS AND NOT D(14).PIN AND CP_BASEADR(6) AND NOT A(2) AND NOT A(5) AND
NOT A(4) AND AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND A(3)));
FTCPE_CP_BASEADR7: FTCPE port map (CP_BASEADR(7),CP_BASEADR_T(7),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET);
CP_BASEADR_T(7) <= ((NOT RW AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND
NOT AUTO_CONFIG_Z2_DONE(1) AND NOT LDS AND D(15).PIN AND NOT CP_BASEADR(7) AND NOT A(2) AND NOT A(5) AND
NOT A(4) AND AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND A(3))
OR (NOT RW AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND
NOT AUTO_CONFIG_Z2_DONE(1) AND NOT UDS AND D(15).PIN AND NOT CP_BASEADR(7) AND NOT A(2) AND NOT A(5) AND
NOT A(4) AND AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND A(3))
OR (NOT RW AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND
NOT AUTO_CONFIG_Z2_DONE(1) AND NOT UDS AND NOT D(15).PIN AND CP_BASEADR(7) AND NOT A(2) AND NOT A(5) AND
NOT A(4) AND AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND A(3))
OR (NOT RW AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND
NOT AUTO_CONFIG_Z2_DONE(1) AND NOT LDS AND NOT D(15).PIN AND CP_BASEADR(7) AND NOT A(2) AND NOT A(5) AND
NOT A(4) AND AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND A(3)));
FTCPE_CP_BASEADR8: FTCPE port map (CP_BASEADR(8),CP_BASEADR_T(8),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET);
CP_BASEADR_T(8) <= ((NOT RW AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND
NOT AUTO_CONFIG_Z2_DONE(1) AND NOT UDS AND D(8).PIN AND NOT CP_BASEADR(8) AND A(2) AND NOT A(5) AND
NOT A(4) AND AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND NOT A(3))
OR (NOT RW AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND
NOT AUTO_CONFIG_Z2_DONE(1) AND NOT LDS AND D(8).PIN AND NOT CP_BASEADR(8) AND A(2) AND NOT A(5) AND
NOT A(4) AND AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND NOT A(3))
OR (NOT RW AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND
NOT AUTO_CONFIG_Z2_DONE(1) AND NOT UDS AND NOT D(8).PIN AND CP_BASEADR(8) AND A(2) AND NOT A(5) AND
NOT A(4) AND AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND NOT A(3))
OR (NOT RW AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND
NOT AUTO_CONFIG_Z2_DONE(1) AND NOT LDS AND NOT D(8).PIN AND CP_BASEADR(8) AND A(2) AND NOT A(5) AND
NOT A(4) AND AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND NOT A(3)));
FTCPE_CP_BASEADR9: FTCPE port map (CP_BASEADR(9),CP_BASEADR_T(9),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET);
CP_BASEADR_T(9) <= ((NOT RW AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND
NOT AUTO_CONFIG_Z2_DONE(1) AND NOT UDS AND D(9).PIN AND NOT CP_BASEADR(9) AND A(2) AND NOT A(5) AND
NOT A(4) AND AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND NOT A(3))
OR (NOT RW AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND
NOT AUTO_CONFIG_Z2_DONE(1) AND NOT LDS AND D(9).PIN AND NOT CP_BASEADR(9) AND A(2) AND NOT A(5) AND
NOT A(4) AND AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND NOT A(3))
OR (NOT RW AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND
NOT AUTO_CONFIG_Z2_DONE(1) AND NOT LDS AND NOT D(9).PIN AND CP_BASEADR(9) AND A(2) AND NOT A(5) AND
NOT A(4) AND AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND NOT A(3))
OR (NOT RW AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND
NOT AUTO_CONFIG_Z2_DONE(1) AND NOT UDS AND NOT D(9).PIN AND CP_BASEADR(9) AND A(2) AND NOT A(5) AND
NOT A(4) AND AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND NOT A(3)));
FTCPE_CP_BASEADR10: FTCPE port map (CP_BASEADR(10),CP_BASEADR_T(10),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET);
CP_BASEADR_T(10) <= ((NOT RW AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND
NOT AUTO_CONFIG_Z2_DONE(1) AND NOT UDS AND D(10).PIN AND NOT CP_BASEADR(10) AND A(2) AND NOT A(5) AND
NOT A(4) AND AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND NOT A(3))
OR (NOT RW AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND
NOT AUTO_CONFIG_Z2_DONE(1) AND NOT LDS AND D(10).PIN AND NOT CP_BASEADR(10) AND A(2) AND NOT A(5) AND
NOT A(4) AND AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND NOT A(3))
OR (NOT RW AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND
NOT AUTO_CONFIG_Z2_DONE(1) AND NOT UDS AND NOT D(10).PIN AND CP_BASEADR(10) AND A(2) AND NOT A(5) AND
NOT A(4) AND AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND NOT A(3))
OR (NOT RW AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND
NOT AUTO_CONFIG_Z2_DONE(1) AND NOT LDS AND NOT D(10).PIN AND CP_BASEADR(10) AND A(2) AND NOT A(5) AND
NOT A(4) AND AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND NOT A(3)));
FTCPE_CP_BASEADR11: FTCPE port map (CP_BASEADR(11),CP_BASEADR_T(11),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET);
CP_BASEADR_T(11) <= ((NOT RW AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND
NOT AUTO_CONFIG_Z2_DONE(1) AND NOT LDS AND D(11).PIN AND NOT CP_BASEADR(11) AND A(2) AND NOT A(5) AND
NOT A(4) AND AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND NOT A(3))
OR (NOT RW AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND
NOT AUTO_CONFIG_Z2_DONE(1) AND NOT UDS AND D(11).PIN AND NOT CP_BASEADR(11) AND A(2) AND NOT A(5) AND
NOT A(4) AND AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND NOT A(3))
OR (NOT RW AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND
NOT AUTO_CONFIG_Z2_DONE(1) AND NOT UDS AND NOT D(11).PIN AND CP_BASEADR(11) AND A(2) AND NOT A(5) AND
NOT A(4) AND AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND NOT A(3))
OR (NOT RW AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND
NOT AUTO_CONFIG_Z2_DONE(1) AND NOT LDS AND NOT D(11).PIN AND CP_BASEADR(11) AND A(2) AND NOT A(5) AND
NOT A(4) AND AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND NOT A(3)));
FTCPE_CP_BASEADR12: FTCPE port map (CP_BASEADR(12),CP_BASEADR_T(12),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET);
CP_BASEADR_T(12) <= ((NOT RW AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND
NOT AUTO_CONFIG_Z2_DONE(1) AND NOT LDS AND D(12).PIN AND NOT CP_BASEADR(12) AND A(2) AND NOT A(5) AND
NOT A(4) AND AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND NOT A(3))
OR (NOT RW AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND
NOT AUTO_CONFIG_Z2_DONE(1) AND NOT UDS AND D(12).PIN AND NOT CP_BASEADR(12) AND A(2) AND NOT A(5) AND
NOT A(4) AND AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND NOT A(3))
OR (NOT RW AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND
NOT AUTO_CONFIG_Z2_DONE(1) AND NOT UDS AND NOT D(12).PIN AND CP_BASEADR(12) AND A(2) AND NOT A(5) AND
NOT A(4) AND AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND NOT A(3))
OR (NOT RW AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND
NOT AUTO_CONFIG_Z2_DONE(1) AND NOT LDS AND NOT D(12).PIN AND CP_BASEADR(12) AND A(2) AND NOT A(5) AND
NOT A(4) AND AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND NOT A(3)));
FTCPE_CP_BASEADR13: FTCPE port map (CP_BASEADR(13),CP_BASEADR_T(13),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET);
CP_BASEADR_T(13) <= ((NOT RW AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND
NOT AUTO_CONFIG_Z2_DONE(1) AND NOT UDS AND D(13).PIN AND NOT CP_BASEADR(13) AND A(2) AND NOT A(5) AND
NOT A(4) AND AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND NOT A(3))
OR (NOT RW AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND
NOT AUTO_CONFIG_Z2_DONE(1) AND NOT LDS AND D(13).PIN AND NOT CP_BASEADR(13) AND A(2) AND NOT A(5) AND
NOT A(4) AND AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND NOT A(3))
OR (NOT RW AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND
NOT AUTO_CONFIG_Z2_DONE(1) AND NOT UDS AND NOT D(13).PIN AND CP_BASEADR(13) AND A(2) AND NOT A(5) AND
NOT A(4) AND AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND NOT A(3))
OR (NOT RW AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND
NOT AUTO_CONFIG_Z2_DONE(1) AND NOT LDS AND NOT D(13).PIN AND CP_BASEADR(13) AND A(2) AND NOT A(5) AND
NOT A(4) AND AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND NOT A(3)));
FTCPE_CP_BASEADR14: FTCPE port map (CP_BASEADR(14),CP_BASEADR_T(14),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET);
CP_BASEADR_T(14) <= ((NOT RW AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND
NOT AUTO_CONFIG_Z2_DONE(1) AND NOT LDS AND D(14).PIN AND NOT CP_BASEADR(14) AND A(2) AND NOT A(5) AND
NOT A(4) AND AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND NOT A(3))
OR (NOT RW AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND
NOT AUTO_CONFIG_Z2_DONE(1) AND NOT UDS AND D(14).PIN AND NOT CP_BASEADR(14) AND A(2) AND NOT A(5) AND
NOT A(4) AND AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND NOT A(3))
OR (NOT RW AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND
NOT AUTO_CONFIG_Z2_DONE(1) AND NOT UDS AND NOT D(14).PIN AND CP_BASEADR(14) AND A(2) AND NOT A(5) AND
NOT A(4) AND AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND NOT A(3))
OR (NOT RW AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND
NOT AUTO_CONFIG_Z2_DONE(1) AND NOT LDS AND NOT D(14).PIN AND CP_BASEADR(14) AND A(2) AND NOT A(5) AND
NOT A(4) AND AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND NOT A(3)));
FTCPE_CP_BASEADR15: FTCPE port map (CP_BASEADR(15),CP_BASEADR_T(15),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET);
CP_BASEADR_T(15) <= ((NOT RW AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND
NOT AUTO_CONFIG_Z2_DONE(1) AND NOT LDS AND D(15).PIN AND NOT CP_BASEADR(15) AND A(2) AND NOT A(5) AND
NOT A(4) AND AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND NOT A(3))
OR (NOT RW AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND
NOT AUTO_CONFIG_Z2_DONE(1) AND NOT UDS AND D(15).PIN AND NOT CP_BASEADR(15) AND A(2) AND NOT A(5) AND
NOT A(4) AND AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND NOT A(3))
OR (NOT RW AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND
NOT AUTO_CONFIG_Z2_DONE(1) AND NOT UDS AND NOT D(15).PIN AND CP_BASEADR(15) AND A(2) AND NOT A(5) AND
NOT A(4) AND AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND NOT A(3))
OR (NOT RW AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND
NOT AUTO_CONFIG_Z2_DONE(1) AND NOT LDS AND NOT D(15).PIN AND CP_BASEADR(15) AND A(2) AND NOT A(5) AND
NOT A(4) AND AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND NOT A(3)));
CP_CS <= CP_CS_BUFR;
FDCPE_CP_CS_BUFR: FDCPE port map (CP_CS_BUFR,CP_CS_BUFR_D,NOT FCS,'0',NOT RESET);
CP_CS_BUFR_D <= ((NOT Z3)
OR (SHUT_UP_Z2(1))
OR (EXP46_.EXP)
OR (D(8).PIN AND NOT CP_BASEADR(8))
OR (NOT D(8).PIN AND CP_BASEADR(8))
OR (NOT D(10).PIN AND CP_BASEADR(10))
OR (D(14).PIN AND NOT CP_BASEADR(14))
OR (NOT D(14).PIN AND CP_BASEADR(14))
OR (EXP44_.EXP)
OR (CP_BASEADR(0) AND NOT A(16).PIN)
OR (NOT CP_BASEADR(0) AND A(16).PIN)
OR (D(12).PIN AND NOT CP_BASEADR(12))
OR (CP_BASEADR(3) AND NOT A(19).PIN)
OR (NOT CP_BASEADR(3) AND A(19).PIN)
OR (D(10).PIN AND NOT CP_BASEADR(10)));
CP_RD <= NOT ((NOT FCS AND NOT CP_RD_S));
FDCPE_CP_RD_S: FDCPE port map (CP_RD_S,CP_RD_S_D,CLK_EXT,'0',NOT RESET);
CP_RD_S_D <= ((RW AND NOT FCS AND NOT UDS AND NOT LAN_SM_FSM_FFd2 AND
NOT LAN_SM_FSM_FFd8 AND NOT LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd6 AND
NOT LAN_SM_FSM_FFd7 AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd5 AND NOT LAN_ACCESS AND
NOT CP_CS_BUFR)
OR (RW AND NOT FCS AND NOT LDS AND NOT LAN_SM_FSM_FFd2 AND
NOT LAN_SM_FSM_FFd8 AND NOT LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd6 AND
NOT LAN_SM_FSM_FFd7 AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd5 AND NOT LAN_ACCESS AND
NOT CP_CS_BUFR)
OR (RW AND NOT FCS AND NOT DS1 AND NOT LAN_SM_FSM_FFd2 AND
NOT LAN_SM_FSM_FFd8 AND NOT LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd6 AND
NOT LAN_SM_FSM_FFd7 AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd5 AND NOT LAN_ACCESS AND
NOT CP_CS_BUFR)
OR (RW AND NOT FCS AND NOT DS0 AND NOT LAN_SM_FSM_FFd2 AND
NOT LAN_SM_FSM_FFd8 AND NOT LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd6 AND
NOT LAN_SM_FSM_FFd7 AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd5 AND NOT LAN_ACCESS AND
NOT CP_CS_BUFR)
OR (NOT LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd8 AND
LAN_SM_FSM_FFd3 AND LAN_SM_FSM_FFd6 AND NOT LAN_SM_FSM_FFd1 AND
LAN_SM_FSM_FFd7 AND LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5));
FDCPE_CP_WAIT0: FDCPE port map (CP_WAIT(0),CP_WAIT_D(0),CLK_EXT,NOT RESET,'0');
CP_WAIT_D(0) <= (NOT CP_WAIT(0) AND NOT CP_CS_BUFR);
FDCPE_CP_WAIT1: FDCPE port map (CP_WAIT(1),CP_WAIT_D(1),CLK_EXT,NOT RESET,'0');
CP_WAIT_D(1) <= ((CP_WAIT(0) AND NOT CP_WAIT(1) AND NOT CP_CS_BUFR)
OR (NOT CP_WAIT(0) AND CP_WAIT(1) AND NOT CP_CS_BUFR));
FTCPE_CP_WAIT2: FTCPE port map (CP_WAIT(2),CP_WAIT_T(2),CLK_EXT,NOT RESET,'0');
CP_WAIT_T(2) <= ((CP_WAIT(2) AND CP_CS_BUFR)
OR (CP_WAIT(0) AND CP_WAIT(1) AND NOT CP_CS_BUFR));
FTCPE_CP_WAIT3: FTCPE port map (CP_WAIT(3),CP_WAIT_T(3),CLK_EXT,NOT RESET,'0');
CP_WAIT_T(3) <= ((CP_WAIT(3) AND CP_CS_BUFR)
OR (CP_WAIT(0) AND CP_WAIT(1) AND CP_WAIT(2) AND
NOT CP_CS_BUFR));
CP_WE <= NOT ((NOT FCS AND NOT CP_WE_S));
FDCPE_CP_WE_S: FDCPE port map (CP_WE_S,CP_WE_S_D,CLK_EXT,'0',NOT RESET);
CP_WE_S_D <= ((NOT RW AND NOT FCS AND NOT LDS AND NOT LAN_SM_FSM_FFd2 AND
NOT LAN_SM_FSM_FFd8 AND NOT LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd6 AND
NOT LAN_SM_FSM_FFd7 AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd5 AND NOT LAN_ACCESS AND
NOT CP_CS_BUFR)
OR (LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd8 AND
LAN_SM_FSM_FFd3 AND LAN_SM_FSM_FFd6 AND NOT LAN_SM_FSM_FFd1 AND
LAN_SM_FSM_FFd7 AND LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5)
OR (NOT RW AND NOT FCS AND NOT UDS AND NOT LAN_SM_FSM_FFd2 AND
NOT LAN_SM_FSM_FFd8 AND NOT LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd6 AND
NOT LAN_SM_FSM_FFd7 AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd5 AND NOT LAN_ACCESS AND
NOT CP_CS_BUFR)
OR (NOT RW AND NOT FCS AND NOT DS1 AND NOT LAN_SM_FSM_FFd2 AND
NOT LAN_SM_FSM_FFd8 AND NOT LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd6 AND
NOT LAN_SM_FSM_FFd7 AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd5 AND NOT LAN_ACCESS AND
NOT CP_CS_BUFR)
OR (NOT RW AND NOT FCS AND NOT DS0 AND NOT LAN_SM_FSM_FFd2 AND
NOT LAN_SM_FSM_FFd8 AND NOT LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd6 AND
NOT LAN_SM_FSM_FFd7 AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd5 AND NOT LAN_ACCESS AND
NOT CP_CS_BUFR));
D_I(0) <= NOT (((RW AND NOT FCS AND LAN_ACCESS AND NOT Z3_DATA(16))
OR (RW AND NOT FCS AND NOT Z3_DATA(16) AND NOT CP_CS_BUFR)));
D(0) <= D_I(0) when D_OE(0) = '1' else 'Z';
D_OE(0) <= D_8_IOBUFE/D_8_IOBUFE_TRST;
D_I(1) <= NOT (((RW AND NOT FCS AND LAN_ACCESS AND NOT Z3_DATA(17))
OR (RW AND NOT FCS AND NOT Z3_DATA(17) AND NOT CP_CS_BUFR)));
D(1) <= D_I(1) when D_OE(1) = '1' else 'Z';
D_OE(1) <= D_8_IOBUFE/D_8_IOBUFE_TRST;
D_I(2) <= NOT (((RW AND NOT FCS AND LAN_ACCESS AND NOT Z3_DATA(18))
OR (RW AND NOT FCS AND NOT Z3_DATA(18) AND NOT CP_CS_BUFR)));
D(2) <= D_I(2) when D_OE(2) = '1' else 'Z';
D_OE(2) <= D_8_IOBUFE/D_8_IOBUFE_TRST;
D_I(3) <= NOT (((RW AND NOT FCS AND LAN_ACCESS AND NOT Z3_DATA(19))
OR (RW AND NOT FCS AND NOT Z3_DATA(19) AND NOT CP_CS_BUFR)));
D(3) <= D_I(3) when D_OE(3) = '1' else 'Z';
D_OE(3) <= D_8_IOBUFE/D_8_IOBUFE_TRST;
D_I(4) <= NOT (((RW AND NOT FCS AND LAN_ACCESS AND NOT Z3_DATA(20))
OR (RW AND NOT FCS AND NOT Z3_DATA(20) AND NOT CP_CS_BUFR)));
D(4) <= D_I(4) when D_OE(4) = '1' else 'Z';
D_OE(4) <= D_8_IOBUFE/D_8_IOBUFE_TRST;
D_I(5) <= NOT (((RW AND NOT FCS AND LAN_ACCESS AND NOT Z3_DATA(21))
OR (RW AND NOT FCS AND NOT Z3_DATA(21) AND NOT CP_CS_BUFR)));
D(5) <= D_I(5) when D_OE(5) = '1' else 'Z';
D_OE(5) <= D_8_IOBUFE/D_8_IOBUFE_TRST;
D_I(6) <= NOT (((RW AND NOT FCS AND LAN_ACCESS AND NOT Z3_DATA(22))
OR (RW AND NOT FCS AND NOT Z3_DATA(22) AND NOT CP_CS_BUFR)));
D(6) <= D_I(6) when D_OE(6) = '1' else 'Z';
D_OE(6) <= D_8_IOBUFE/D_8_IOBUFE_TRST;
D_I(7) <= NOT (((RW AND NOT FCS AND LAN_ACCESS AND NOT Z3_DATA(23))
OR (RW AND NOT FCS AND NOT Z3_DATA(23) AND NOT CP_CS_BUFR)));
D(7) <= D_I(7) when D_OE(7) = '1' else 'Z';
D_OE(7) <= D_8_IOBUFE/D_8_IOBUFE_TRST;
D_I(8) <= NOT (((RW AND NOT FCS AND LAN_ACCESS AND NOT Z3_DATA(24))
OR (RW AND NOT FCS AND NOT Z3_DATA(24) AND NOT CP_CS_BUFR)));
D(8) <= D_I(8) when D_OE(8) = '1' else 'Z';
D_OE(8) <= D_8_IOBUFE/D_8_IOBUFE_TRST;
D_I(9) <= NOT (((RW AND NOT FCS AND NOT Z3_DATA(25) AND NOT CP_CS_BUFR)
OR (RW AND NOT FCS AND LAN_ACCESS AND NOT Z3_DATA(25))));
D(9) <= D_I(9) when D_OE(9) = '1' else 'Z';
D_OE(9) <= D_8_IOBUFE/D_8_IOBUFE_TRST;
D_I(10) <= NOT (((RW AND NOT FCS AND LAN_ACCESS AND NOT Z3_DATA(26))
OR (RW AND NOT FCS AND NOT Z3_DATA(26) AND NOT CP_CS_BUFR)));
D(10) <= D_I(10) when D_OE(10) = '1' else 'Z';
D_OE(10) <= D_8_IOBUFE/D_8_IOBUFE_TRST;
D_I(11) <= NOT (((RW AND NOT FCS AND LAN_ACCESS AND NOT Z3_DATA(27))
OR (RW AND NOT FCS AND NOT Z3_DATA(27) AND NOT CP_CS_BUFR)));
D(11) <= D_I(11) when D_OE(11) = '1' else 'Z';
D_OE(11) <= D_8_IOBUFE/D_8_IOBUFE_TRST;
D_I(12) <= ((NOT RW AND D_Z2_OUT(0))
OR (FCS AND D_Z2_OUT(0))
OR (NOT LAN_ACCESS AND D_Z2_OUT(0) AND CP_CS_BUFR)
OR (RW AND NOT FCS AND LAN_ACCESS AND Z3_DATA(28))
OR (RW AND NOT FCS AND Z3_DATA(28) AND NOT CP_CS_BUFR));
D(12) <= D_I(12) when D_OE(12) = '1' else 'Z';
D_OE(12) <= D_8_IOBUFE/D_8_IOBUFE_TRST;
D_I(13) <= ((NOT RW AND D_Z2_OUT(1))
OR (FCS AND D_Z2_OUT(1))
OR (NOT LAN_ACCESS AND D_Z2_OUT(1) AND CP_CS_BUFR)
OR (RW AND NOT FCS AND LAN_ACCESS AND Z3_DATA(29))
OR (RW AND NOT FCS AND Z3_DATA(29) AND NOT CP_CS_BUFR));
D(13) <= D_I(13) when D_OE(13) = '1' else 'Z';
D_OE(13) <= D_8_IOBUFE/D_8_IOBUFE_TRST;
D_I(14) <= ((RW AND NOT FCS AND Z3_DATA(30) AND NOT CP_CS_BUFR)
OR (NOT RW AND D_Z2_OUT(2))
OR (FCS AND D_Z2_OUT(2))
OR (NOT LAN_ACCESS AND D_Z2_OUT(2) AND CP_CS_BUFR)
OR (RW AND NOT FCS AND LAN_ACCESS AND Z3_DATA(30)));
D(14) <= D_I(14) when D_OE(14) = '1' else 'Z';
D_OE(14) <= D_8_IOBUFE/D_8_IOBUFE_TRST;
D_I(15) <= ((RW AND NOT FCS AND LAN_ACCESS AND Z3_DATA(31))
OR (RW AND NOT FCS AND Z3_DATA(31) AND NOT CP_CS_BUFR)
OR (NOT RW AND D_Z2_OUT(3))
OR (FCS AND D_Z2_OUT(3))
OR (NOT LAN_ACCESS AND D_Z2_OUT(3) AND CP_CS_BUFR));
D(15) <= D_I(15) when D_OE(15) = '1' else 'Z';
D_OE(15) <= D_8_IOBUFE/D_8_IOBUFE_TRST;
DQ_I(0) <= (RESET AND DQ_DATA(0));
DQ(0) <= DQ_I(0) when DQ_OE(0) = '1' else 'Z';
DQ_OE(0) <= NOT DQ_11_IOBUFE/DQ_11_IOBUFE_TRST__$INT;
DQ_I(1) <= ((RESET AND DQ_DATA(1))
OR (NOT RESET AND LAN_D_INIT(1)));
DQ(1) <= DQ_I(1) when DQ_OE(1) = '1' else 'Z';
DQ_OE(1) <= NOT DQ_11_IOBUFE/DQ_11_IOBUFE_TRST__$INT;
DQ_I(2) <= (RESET AND DQ_DATA(2));
DQ(2) <= DQ_I(2) when DQ_OE(2) = '1' else 'Z';
DQ_OE(2) <= NOT DQ_11_IOBUFE/DQ_11_IOBUFE_TRST__$INT;
DQ_I(3) <= (RESET AND DQ_DATA(3));
DQ(3) <= DQ_I(3) when DQ_OE(3) = '1' else 'Z';
DQ_OE(3) <= NOT DQ_11_IOBUFE/DQ_11_IOBUFE_TRST__$INT;
DQ_I(4) <= ((RESET AND DQ_DATA(4))
OR (NOT RESET AND LAN_D_INIT(1)));
DQ(4) <= DQ_I(4) when DQ_OE(4) = '1' else 'Z';
DQ_OE(4) <= NOT DQ_11_IOBUFE/DQ_11_IOBUFE_TRST__$INT;
DQ_I(5) <= (RESET AND DQ_DATA(5));
DQ(5) <= DQ_I(5) when DQ_OE(5) = '1' else 'Z';
DQ_OE(5) <= NOT DQ_11_IOBUFE/DQ_11_IOBUFE_TRST__$INT;
DQ_I(6) <= (RESET AND DQ_DATA(6));
DQ(6) <= DQ_I(6) when DQ_OE(6) = '1' else 'Z';
DQ_OE(6) <= NOT DQ_11_IOBUFE/DQ_11_IOBUFE_TRST__$INT;
DQ_I(7) <= (RESET AND DQ_DATA(7));
DQ(7) <= DQ_I(7) when DQ_OE(7) = '1' else 'Z';
DQ_OE(7) <= NOT DQ_11_IOBUFE/DQ_11_IOBUFE_TRST__$INT;
DQ_I(8) <= ((RESET AND DQ_DATA(8))
OR (NOT RESET AND LAN_D_INIT(8)));
DQ(8) <= DQ_I(8) when DQ_OE(8) = '1' else 'Z';
DQ_OE(8) <= NOT DQ_11_IOBUFE/DQ_11_IOBUFE_TRST__$INT;
DQ_I(9) <= ((RESET AND DQ_DATA(9))
OR (NOT RESET AND LAN_D_INIT(1)));
DQ(9) <= DQ_I(9) when DQ_OE(9) = '1' else 'Z';
DQ_OE(9) <= NOT DQ_11_IOBUFE/DQ_11_IOBUFE_TRST__$INT;
DQ_I(10) <= ((RESET AND DQ_DATA(10))
OR (NOT RESET AND LAN_D_INIT(8)));
DQ(10) <= DQ_I(10) when DQ_OE(10) = '1' else 'Z';
DQ_OE(10) <= NOT DQ_11_IOBUFE/DQ_11_IOBUFE_TRST__$INT;
DQ_I(11) <= ((RESET AND DQ_DATA(11))
OR (NOT RESET AND LAN_D_INIT(8)));
DQ(11) <= DQ_I(11) when DQ_OE(11) = '1' else 'Z';
DQ_OE(11) <= NOT DQ_11_IOBUFE/DQ_11_IOBUFE_TRST__$INT;
DQ_I(12) <= (RESET AND DQ_DATA(12));
DQ(12) <= DQ_I(12) when DQ_OE(12) = '1' else 'Z';
DQ_OE(12) <= NOT DQ_11_IOBUFE/DQ_11_IOBUFE_TRST__$INT;
DQ_I(13) <= (RESET AND DQ_DATA(13));
DQ(13) <= DQ_I(13) when DQ_OE(13) = '1' else 'Z';
DQ_OE(13) <= NOT DQ_11_IOBUFE/DQ_11_IOBUFE_TRST__$INT;
DQ_I(14) <= (RESET AND DQ_DATA(14));
DQ(14) <= DQ_I(14) when DQ_OE(14) = '1' else 'Z';
DQ_OE(14) <= NOT DQ_11_IOBUFE/DQ_11_IOBUFE_TRST__$INT;
DQ_I(15) <= (RESET AND DQ_DATA(15));
DQ(15) <= DQ_I(15) when DQ_OE(15) = '1' else 'Z';
DQ_OE(15) <= NOT DQ_11_IOBUFE/DQ_11_IOBUFE_TRST__$INT;
DQ_11_IOBUFE/DQ_11_IOBUFE_TRST__$INT <= ((RESET AND RW)
OR (RESET AND FCS)
OR (RESET AND NOT LAN_ACCESS AND CP_CS_BUFR)
OR (RESET AND UDS AND LDS AND DS1 AND DS0));
FDCPE_DQ_DATA0: FDCPE port map (DQ_DATA(0),DQ_DATA_D(0),CLK_EXT,'0',NOT RESET);
DQ_DATA_D(0) <= ((NOT UDS AND D(8).PIN AND NOT LAN_SM_FSM_FFd2 AND
NOT LAN_SM_FSM_FFd8 AND DQ_SWAP)
OR (NOT LDS AND D(8).PIN AND NOT LAN_SM_FSM_FFd2 AND
NOT LAN_SM_FSM_FFd8 AND DQ_SWAP)
OR (NOT LDS AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
NOT DQ_SWAP AND D(0).PIN)
OR (UDS AND LDS AND A(16).PIN AND NOT LAN_SM_FSM_FFd2 AND
NOT LAN_SM_FSM_FFd8 AND DQ_SWAP)
OR (UDS AND LDS AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
NOT DQ_SWAP AND A(8).PIN)
OR (DQ_DATA(0) AND NOT $OpTx$$OpTx$FX_DC$168_INV$2057)
OR (A(16).PIN AND LAN_SM_FSM_FFd3 AND DQ_SWAP AND
NOT LAN_SM_FSM_FFd4)
OR (LAN_SM_FSM_FFd3 AND NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd4 AND
A(8).PIN)
OR (NOT UDS AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
NOT DQ_SWAP AND D(0).PIN));
FDCPE_DQ_DATA1: FDCPE port map (DQ_DATA(1),DQ_DATA_D(1),CLK_EXT,'0',NOT RESET);
DQ_DATA_D(1) <= ((NOT UDS AND D(9).PIN AND NOT LAN_SM_FSM_FFd2 AND
NOT LAN_SM_FSM_FFd8 AND DQ_SWAP)
OR (NOT LDS AND D(9).PIN AND NOT LAN_SM_FSM_FFd2 AND
NOT LAN_SM_FSM_FFd8 AND DQ_SWAP)
OR (NOT LDS AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
NOT DQ_SWAP AND D(1).PIN)
OR (UDS AND LDS AND A(17).PIN AND NOT LAN_SM_FSM_FFd2 AND
NOT LAN_SM_FSM_FFd8 AND DQ_SWAP)
OR (UDS AND LDS AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
NOT DQ_SWAP AND A(9).PIN)
OR (DQ_DATA(1) AND NOT $OpTx$$OpTx$FX_DC$168_INV$2057)
OR (A(17).PIN AND LAN_SM_FSM_FFd3 AND DQ_SWAP AND
NOT LAN_SM_FSM_FFd4)
OR (LAN_SM_FSM_FFd3 AND NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd4 AND
A(9).PIN)
OR (NOT UDS AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
NOT DQ_SWAP AND D(1).PIN));
FDCPE_DQ_DATA2: FDCPE port map (DQ_DATA(2),DQ_DATA_D(2),CLK_EXT,'0',NOT RESET);
DQ_DATA_D(2) <= ((NOT UDS AND D(10).PIN AND NOT LAN_SM_FSM_FFd2 AND
NOT LAN_SM_FSM_FFd8 AND DQ_SWAP)
OR (NOT LDS AND D(10).PIN AND NOT LAN_SM_FSM_FFd2 AND
NOT LAN_SM_FSM_FFd8 AND DQ_SWAP)
OR (NOT LDS AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
NOT DQ_SWAP AND D(2).PIN)
OR (UDS AND LDS AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
NOT DQ_SWAP AND A(10).PIN)
OR (UDS AND LDS AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
DQ_SWAP AND A(18).PIN)
OR (DQ_DATA(2) AND NOT $OpTx$$OpTx$FX_DC$168_INV$2057)
OR (LAN_SM_FSM_FFd3 AND DQ_SWAP AND NOT LAN_SM_FSM_FFd4 AND
A(18).PIN)
OR (LAN_SM_FSM_FFd3 AND NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd4 AND
A(10).PIN)
OR (NOT UDS AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
NOT DQ_SWAP AND D(2).PIN));
FDCPE_DQ_DATA3: FDCPE port map (DQ_DATA(3),DQ_DATA_D(3),CLK_EXT,'0',NOT RESET);
DQ_DATA_D(3) <= ((NOT LDS AND D(11).PIN AND NOT LAN_SM_FSM_FFd2 AND
NOT LAN_SM_FSM_FFd8 AND DQ_SWAP)
OR (UDS AND LDS AND A(19).PIN AND NOT LAN_SM_FSM_FFd2 AND
NOT LAN_SM_FSM_FFd8 AND DQ_SWAP)
OR (UDS AND LDS AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
NOT DQ_SWAP AND A(11).PIN)
OR (NOT UDS AND D(11).PIN AND NOT LAN_SM_FSM_FFd2 AND
NOT LAN_SM_FSM_FFd8 AND DQ_SWAP)
OR (NOT LDS AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
NOT DQ_SWAP AND D(3).PIN)
OR (DQ_DATA(3) AND NOT $OpTx$$OpTx$FX_DC$168_INV$2057)
OR (A(19).PIN AND LAN_SM_FSM_FFd3 AND DQ_SWAP AND
NOT LAN_SM_FSM_FFd4)
OR (LAN_SM_FSM_FFd3 AND NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd4 AND
A(11).PIN)
OR (NOT UDS AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
NOT DQ_SWAP AND D(3).PIN));
FDCPE_DQ_DATA4: FDCPE port map (DQ_DATA(4),DQ_DATA_D(4),CLK_EXT,'0',NOT RESET);
DQ_DATA_D(4) <= ((NOT UDS AND D(12).PIN AND NOT LAN_SM_FSM_FFd2 AND
NOT LAN_SM_FSM_FFd8 AND DQ_SWAP)
OR (NOT LDS AND D(12).PIN AND NOT LAN_SM_FSM_FFd2 AND
NOT LAN_SM_FSM_FFd8 AND DQ_SWAP)
OR (NOT LDS AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
NOT DQ_SWAP AND D(4).PIN)
OR (UDS AND LDS AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
DQ_SWAP AND A(20).PIN)
OR (UDS AND LDS AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
NOT DQ_SWAP AND A(12).PIN)
OR (DQ_DATA(4) AND NOT $OpTx$$OpTx$FX_DC$168_INV$2057)
OR (LAN_SM_FSM_FFd3 AND DQ_SWAP AND NOT LAN_SM_FSM_FFd4 AND
A(20).PIN)
OR (LAN_SM_FSM_FFd3 AND NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd4 AND
A(12).PIN)
OR (NOT UDS AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
NOT DQ_SWAP AND D(4).PIN));
FDCPE_DQ_DATA5: FDCPE port map (DQ_DATA(5),DQ_DATA_D(5),CLK_EXT,'0',NOT RESET);
DQ_DATA_D(5) <= ((NOT UDS AND D(13).PIN AND NOT LAN_SM_FSM_FFd2 AND
NOT LAN_SM_FSM_FFd8 AND DQ_SWAP)
OR (NOT LDS AND D(13).PIN AND NOT LAN_SM_FSM_FFd2 AND
NOT LAN_SM_FSM_FFd8 AND DQ_SWAP)
OR (NOT LDS AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
NOT DQ_SWAP AND D(5).PIN)
OR (UDS AND LDS AND A(21).PIN AND NOT LAN_SM_FSM_FFd2 AND
NOT LAN_SM_FSM_FFd8 AND DQ_SWAP)
OR (UDS AND LDS AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
NOT DQ_SWAP AND A(13).PIN)
OR (DQ_DATA(5) AND NOT $OpTx$$OpTx$FX_DC$168_INV$2057)
OR (A(21).PIN AND LAN_SM_FSM_FFd3 AND DQ_SWAP AND
NOT LAN_SM_FSM_FFd4)
OR (LAN_SM_FSM_FFd3 AND NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd4 AND
A(13).PIN)
OR (NOT UDS AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
NOT DQ_SWAP AND D(5).PIN));
FDCPE_DQ_DATA6: FDCPE port map (DQ_DATA(6),DQ_DATA_D(6),CLK_EXT,'0',NOT RESET);
DQ_DATA_D(6) <= ((NOT UDS AND D(14).PIN AND NOT LAN_SM_FSM_FFd2 AND
NOT LAN_SM_FSM_FFd8 AND DQ_SWAP)
OR (NOT LDS AND D(14).PIN AND NOT LAN_SM_FSM_FFd2 AND
NOT LAN_SM_FSM_FFd8 AND DQ_SWAP)
OR (NOT LDS AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
NOT DQ_SWAP AND D(6).PIN)
OR (UDS AND LDS AND A(22).PIN AND NOT LAN_SM_FSM_FFd2 AND
NOT LAN_SM_FSM_FFd8 AND DQ_SWAP)
OR (UDS AND LDS AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
NOT DQ_SWAP AND A(14).PIN)
OR (DQ_DATA(6) AND NOT $OpTx$$OpTx$FX_DC$168_INV$2057)
OR (A(22).PIN AND LAN_SM_FSM_FFd3 AND DQ_SWAP AND
NOT LAN_SM_FSM_FFd4)
OR (LAN_SM_FSM_FFd3 AND NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd4 AND
A(14).PIN)
OR (NOT UDS AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
NOT DQ_SWAP AND D(6).PIN));
FDCPE_DQ_DATA7: FDCPE port map (DQ_DATA(7),DQ_DATA_D(7),CLK_EXT,'0',NOT RESET);
DQ_DATA_D(7) <= ((NOT UDS AND D(15).PIN AND NOT LAN_SM_FSM_FFd2 AND
NOT LAN_SM_FSM_FFd8 AND DQ_SWAP)
OR (NOT LDS AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
NOT DQ_SWAP AND D(7).PIN)
OR (NOT LDS AND D(15).PIN AND NOT LAN_SM_FSM_FFd2 AND
NOT LAN_SM_FSM_FFd8 AND DQ_SWAP)
OR (UDS AND LDS AND A(23).PIN AND NOT LAN_SM_FSM_FFd2 AND
NOT LAN_SM_FSM_FFd8 AND DQ_SWAP)
OR (UDS AND LDS AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
NOT DQ_SWAP AND A(15).PIN)
OR (DQ_DATA(7) AND NOT $OpTx$$OpTx$FX_DC$168_INV$2057)
OR (A(23).PIN AND LAN_SM_FSM_FFd3 AND DQ_SWAP AND
NOT LAN_SM_FSM_FFd4)
OR (LAN_SM_FSM_FFd3 AND NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd4 AND
A(15).PIN)
OR (NOT UDS AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
NOT DQ_SWAP AND D(7).PIN));
FDCPE_DQ_DATA8: FDCPE port map (DQ_DATA(8),DQ_DATA_D(8),CLK_EXT,'0',NOT RESET);
DQ_DATA_D(8) <= ((NOT UDS AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
DQ_SWAP AND D(0).PIN)
OR (NOT LDS AND D(8).PIN AND NOT LAN_SM_FSM_FFd2 AND
NOT LAN_SM_FSM_FFd8 AND NOT DQ_SWAP)
OR (NOT LDS AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
DQ_SWAP AND D(0).PIN)
OR (UDS AND LDS AND A(16).PIN AND NOT LAN_SM_FSM_FFd2 AND
NOT LAN_SM_FSM_FFd8 AND NOT DQ_SWAP)
OR (UDS AND LDS AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
DQ_SWAP AND A(8).PIN)
OR (DQ_DATA(8) AND NOT $OpTx$$OpTx$FX_DC$168_INV$2057)
OR (A(16).PIN AND LAN_SM_FSM_FFd3 AND NOT DQ_SWAP AND
NOT LAN_SM_FSM_FFd4)
OR (LAN_SM_FSM_FFd3 AND DQ_SWAP AND NOT LAN_SM_FSM_FFd4 AND
A(8).PIN)
OR (NOT UDS AND D(8).PIN AND NOT LAN_SM_FSM_FFd2 AND
NOT LAN_SM_FSM_FFd8 AND NOT DQ_SWAP));
FDCPE_DQ_DATA9: FDCPE port map (DQ_DATA(9),DQ_DATA_D(9),CLK_EXT,'0',NOT RESET);
DQ_DATA_D(9) <= ((NOT UDS AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
DQ_SWAP AND D(1).PIN)
OR (NOT LDS AND D(9).PIN AND NOT LAN_SM_FSM_FFd2 AND
NOT LAN_SM_FSM_FFd8 AND NOT DQ_SWAP)
OR (NOT LDS AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
DQ_SWAP AND D(1).PIN)
OR (UDS AND LDS AND A(17).PIN AND NOT LAN_SM_FSM_FFd2 AND
NOT LAN_SM_FSM_FFd8 AND NOT DQ_SWAP)
OR (UDS AND LDS AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
DQ_SWAP AND A(9).PIN)
OR (DQ_DATA(9) AND NOT $OpTx$$OpTx$FX_DC$168_INV$2057)
OR (A(17).PIN AND LAN_SM_FSM_FFd3 AND NOT DQ_SWAP AND
NOT LAN_SM_FSM_FFd4)
OR (LAN_SM_FSM_FFd3 AND DQ_SWAP AND NOT LAN_SM_FSM_FFd4 AND
A(9).PIN)
OR (NOT UDS AND D(9).PIN AND NOT LAN_SM_FSM_FFd2 AND
NOT LAN_SM_FSM_FFd8 AND NOT DQ_SWAP));
FDCPE_DQ_DATA10: FDCPE port map (DQ_DATA(10),DQ_DATA_D(10),CLK_EXT,'0',NOT RESET);
DQ_DATA_D(10) <= ((NOT UDS AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
DQ_SWAP AND D(2).PIN)
OR (NOT LDS AND D(10).PIN AND NOT LAN_SM_FSM_FFd2 AND
NOT LAN_SM_FSM_FFd8 AND NOT DQ_SWAP)
OR (NOT LDS AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
DQ_SWAP AND D(2).PIN)
OR (UDS AND LDS AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
DQ_SWAP AND A(10).PIN)
OR (UDS AND LDS AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
NOT DQ_SWAP AND A(18).PIN)
OR (DQ_DATA(10) AND NOT $OpTx$$OpTx$FX_DC$168_INV$2057)
OR (LAN_SM_FSM_FFd3 AND DQ_SWAP AND NOT LAN_SM_FSM_FFd4 AND
A(10).PIN)
OR (LAN_SM_FSM_FFd3 AND NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd4 AND
A(18).PIN)
OR (NOT UDS AND D(10).PIN AND NOT LAN_SM_FSM_FFd2 AND
NOT LAN_SM_FSM_FFd8 AND NOT DQ_SWAP));
FDCPE_DQ_DATA11: FDCPE port map (DQ_DATA(11),DQ_DATA_D(11),CLK_EXT,'0',NOT RESET);
DQ_DATA_D(11) <= ((Z3_DATA(8).EXP)
OR (NOT UDS AND D(11).PIN AND NOT LAN_SM_FSM_FFd2 AND
NOT LAN_SM_FSM_FFd8 AND NOT DQ_SWAP)
OR (NOT UDS AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
DQ_SWAP AND D(3).PIN)
OR (NOT LDS AND D(11).PIN AND NOT LAN_SM_FSM_FFd2 AND
NOT LAN_SM_FSM_FFd8 AND NOT DQ_SWAP)
OR (NOT LDS AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
DQ_SWAP AND D(3).PIN)
OR (UDS AND LDS AND A(19).PIN AND NOT LAN_SM_FSM_FFd2 AND
NOT LAN_SM_FSM_FFd8 AND NOT DQ_SWAP)
OR (DQ_DATA(11) AND NOT $OpTx$$OpTx$FX_DC$168_INV$2057)
OR (A(19).PIN AND LAN_SM_FSM_FFd3 AND NOT DQ_SWAP AND
NOT LAN_SM_FSM_FFd4)
OR (LAN_SM_FSM_FFd3 AND DQ_SWAP AND NOT LAN_SM_FSM_FFd4 AND
A(11).PIN));
FDCPE_DQ_DATA12: FDCPE port map (DQ_DATA(12),DQ_DATA_D(12),CLK_EXT,'0',NOT RESET);
DQ_DATA_D(12) <= ((NOT UDS AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
DQ_SWAP AND D(4).PIN)
OR (NOT LDS AND D(12).PIN AND NOT LAN_SM_FSM_FFd2 AND
NOT LAN_SM_FSM_FFd8 AND NOT DQ_SWAP)
OR (NOT LDS AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
DQ_SWAP AND D(4).PIN)
OR (UDS AND LDS AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
DQ_SWAP AND A(12).PIN)
OR (UDS AND LDS AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
NOT DQ_SWAP AND A(20).PIN)
OR (DQ_DATA(12) AND NOT $OpTx$$OpTx$FX_DC$168_INV$2057)
OR (LAN_SM_FSM_FFd3 AND DQ_SWAP AND NOT LAN_SM_FSM_FFd4 AND
A(12).PIN)
OR (LAN_SM_FSM_FFd3 AND NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd4 AND
A(20).PIN)
OR (NOT UDS AND D(12).PIN AND NOT LAN_SM_FSM_FFd2 AND
NOT LAN_SM_FSM_FFd8 AND NOT DQ_SWAP));
FDCPE_DQ_DATA13: FDCPE port map (DQ_DATA(13),DQ_DATA_D(13),CLK_EXT,'0',NOT RESET);
DQ_DATA_D(13) <= ((NOT UDS AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
DQ_SWAP AND D(5).PIN)
OR (NOT LDS AND D(13).PIN AND NOT LAN_SM_FSM_FFd2 AND
NOT LAN_SM_FSM_FFd8 AND NOT DQ_SWAP)
OR (NOT LDS AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
DQ_SWAP AND D(5).PIN)
OR (UDS AND LDS AND A(21).PIN AND NOT LAN_SM_FSM_FFd2 AND
NOT LAN_SM_FSM_FFd8 AND NOT DQ_SWAP)
OR (UDS AND LDS AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
DQ_SWAP AND A(13).PIN)
OR (DQ_DATA(13) AND NOT $OpTx$$OpTx$FX_DC$168_INV$2057)
OR (A(21).PIN AND LAN_SM_FSM_FFd3 AND NOT DQ_SWAP AND
NOT LAN_SM_FSM_FFd4)
OR (LAN_SM_FSM_FFd3 AND DQ_SWAP AND NOT LAN_SM_FSM_FFd4 AND
A(13).PIN)
OR (NOT UDS AND D(13).PIN AND NOT LAN_SM_FSM_FFd2 AND
NOT LAN_SM_FSM_FFd8 AND NOT DQ_SWAP));
FDCPE_DQ_DATA14: FDCPE port map (DQ_DATA(14),DQ_DATA_D(14),CLK_EXT,'0',NOT RESET);
DQ_DATA_D(14) <= ((NOT UDS AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
DQ_SWAP AND D(6).PIN)
OR (NOT LDS AND D(14).PIN AND NOT LAN_SM_FSM_FFd2 AND
NOT LAN_SM_FSM_FFd8 AND NOT DQ_SWAP)
OR (NOT LDS AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
DQ_SWAP AND D(6).PIN)
OR (UDS AND LDS AND A(22).PIN AND NOT LAN_SM_FSM_FFd2 AND
NOT LAN_SM_FSM_FFd8 AND NOT DQ_SWAP)
OR (UDS AND LDS AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
DQ_SWAP AND A(14).PIN)
OR (DQ_DATA(14) AND NOT $OpTx$$OpTx$FX_DC$168_INV$2057)
OR (A(22).PIN AND LAN_SM_FSM_FFd3 AND NOT DQ_SWAP AND
NOT LAN_SM_FSM_FFd4)
OR (LAN_SM_FSM_FFd3 AND DQ_SWAP AND NOT LAN_SM_FSM_FFd4 AND
A(14).PIN)
OR (NOT UDS AND D(14).PIN AND NOT LAN_SM_FSM_FFd2 AND
NOT LAN_SM_FSM_FFd8 AND NOT DQ_SWAP));
FDCPE_DQ_DATA15: FDCPE port map (DQ_DATA(15),DQ_DATA_D(15),CLK_EXT,'0',NOT RESET);
DQ_DATA_D(15) <= ((NOT UDS AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
DQ_SWAP AND D(7).PIN)
OR (NOT LDS AND D(15).PIN AND NOT LAN_SM_FSM_FFd2 AND
NOT LAN_SM_FSM_FFd8 AND NOT DQ_SWAP)
OR (NOT LDS AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
DQ_SWAP AND D(7).PIN)
OR (UDS AND LDS AND A(23).PIN AND NOT LAN_SM_FSM_FFd2 AND
NOT LAN_SM_FSM_FFd8 AND NOT DQ_SWAP)
OR (UDS AND LDS AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
DQ_SWAP AND A(15).PIN)
OR (DQ_DATA(15) AND NOT $OpTx$$OpTx$FX_DC$168_INV$2057)
OR (A(23).PIN AND LAN_SM_FSM_FFd3 AND NOT DQ_SWAP AND
NOT LAN_SM_FSM_FFd4)
OR (LAN_SM_FSM_FFd3 AND DQ_SWAP AND NOT LAN_SM_FSM_FFd4 AND
A(15).PIN)
OR (NOT UDS AND D(15).PIN AND NOT LAN_SM_FSM_FFd2 AND
NOT LAN_SM_FSM_FFd8 AND NOT DQ_SWAP));
FDCPE_DQ_SWAP: FDCPE port map (DQ_SWAP,DQ_SWAP_D,NOT FCS,NOT RESET,'0');
DQ_SWAP_D <= (($OpTx$INV$123)
OR ($OpTx$INV$124)
OR (D(13).PIN AND NOT LAN_BASEADR(13))
OR (NOT D(13).PIN AND LAN_BASEADR(13))
OR (LAN_BASEADR(6) AND NOT A(22).PIN)
OR (NOT LAN_BASEADR(6) AND A(22).PIN)
OR (A(13).PIN AND A(14).PIN));
DTACK_I <= '0';
DTACK <= DTACK_I when DTACK_OE = '1' else 'Z';
DTACK_OE <= (NOT FCS AND LAN_READY);
D_8_IOBUFE/D_8_IOBUFE_TRST <= ((RW AND NOT FCS AND LAN_ACCESS)
OR (RW AND NOT FCS AND NOT CP_CS_BUFR)
OR (RW AND NOT AS AND AUTOCONFIG_Z2_ACCESS));
FDCPE_D_Z2_OUT0: FDCPE port map (D_Z2_OUT(0),D_Z2_OUT_D(0),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET);
D_Z2_OUT_D(0) <= ((AS)
OR (NOT AUTOCONFIG_Z2_ACCESS)
OR (A(6))
OR (NOT A(2) AND A(4) AND NOT A(3))
OR (A(4) AND A(1) AND NOT A(3))
OR (AUTO_CONFIG_Z2_DONE(0) AND AUTO_CONFIG_Z2_DONE(1) AND
NOT A(5) AND NOT A(3))
OR (AUTO_CONFIG_Z2_DONE(0) AND NOT A(5) AND NOT A(4) AND A(1))
OR (A(2) AND NOT A(5) AND NOT A(4) AND A(3))
OR (UDS AND LDS)
OR (NOT A(2) AND A(5))
OR (A(5) AND A(4))
OR (A(2) AND NOT A(1) AND A(3))
OR (NOT A(2) AND NOT A(4) AND A(1)));
FDCPE_D_Z2_OUT1: FDCPE port map (D_Z2_OUT(1),D_Z2_OUT_D(1),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET);
D_Z2_OUT_D(1) <= ((NOT AS AND NOT A(2) AND NOT A(5) AND NOT A(4) AND AUTOCONFIG_Z2_ACCESS AND
A(1) AND NOT A(6) AND NOT $OpTx$$OpTx$FX_DC$128_INV$2055)
OR (NOT AS AND NOT A(5) AND A(4) AND AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND
NOT A(6) AND A(3) AND NOT $OpTx$$OpTx$FX_DC$128_INV$2055)
OR (NOT AS AND NOT AUTO_CONFIG_Z2_DONE(0) AND NOT A(5) AND NOT A(4) AND
AUTOCONFIG_Z2_ACCESS AND A(1) AND NOT A(6) AND NOT A(3) AND
NOT $OpTx$$OpTx$FX_DC$128_INV$2055)
OR (NOT AS AND AUTO_CONFIG_Z2_DONE(1) AND NOT A(5) AND NOT A(4) AND
AUTOCONFIG_Z2_ACCESS AND A(1) AND NOT A(6) AND NOT A(3) AND
NOT $OpTx$$OpTx$FX_DC$128_INV$2055)
OR (NOT AS AND A(2) AND A(5) AND NOT A(4) AND AUTOCONFIG_Z2_ACCESS AND
NOT A(1) AND NOT A(6) AND NOT A(3) AND NOT $OpTx$$OpTx$FX_DC$128_INV$2055)
OR (NOT AS AND A(2) AND NOT A(5) AND A(4) AND AUTOCONFIG_Z2_ACCESS AND
NOT A(6) AND A(3) AND NOT $OpTx$$OpTx$FX_DC$128_INV$2055)
OR (NOT AS AND NOT AUTO_CONFIG_Z2_DONE(0) AND NOT A(2) AND NOT A(5) AND
AUTOCONFIG_Z2_ACCESS AND A(1) AND NOT A(6) AND NOT A(3) AND
NOT $OpTx$$OpTx$FX_DC$128_INV$2055)
OR (NOT AS AND NOT AUTO_CONFIG_Z2_DONE(1) AND NOT A(2) AND NOT A(5) AND
AUTOCONFIG_Z2_ACCESS AND A(1) AND NOT A(6) AND NOT A(3) AND
NOT $OpTx$$OpTx$FX_DC$128_INV$2055)
OR (NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND
AUTO_CONFIG_Z2_DONE(1) AND A(2) AND NOT A(5) AND A(4) AND AUTOCONFIG_Z2_ACCESS AND
NOT A(1) AND NOT A(6) AND NOT $OpTx$$OpTx$FX_DC$128_INV$2055)
OR (NOT AS AND NOT A(2) AND NOT A(5) AND NOT A(4) AND AUTOCONFIG_Z2_ACCESS AND
NOT A(6) AND NOT A(3) AND NOT $OpTx$$OpTx$FX_DC$128_INV$2055)
OR (NOT AS AND NOT AUTO_CONFIG_Z2_DONE(0) AND A(2) AND NOT A(4) AND
AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND NOT A(6) AND NOT A(3) AND
NOT $OpTx$$OpTx$FX_DC$128_INV$2055)
OR (NOT AS AND NOT AUTO_CONFIG_Z2_DONE(1) AND A(2) AND NOT A(4) AND
AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND NOT A(6) AND NOT A(3) AND
NOT $OpTx$$OpTx$FX_DC$128_INV$2055));
FDCPE_D_Z2_OUT2: FDCPE port map (D_Z2_OUT(2),D_Z2_OUT_D(2),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET);
D_Z2_OUT_D(2) <= ((NOT AUTOCONFIG_Z2_ACCESS)
OR (A(6))
OR (AS)
OR (EXP69_.EXP)
OR (A(5) AND A(4))
OR (A(5) AND NOT A(1))
OR (NOT A(4) AND A(3))
OR (A(1) AND A(3)));
FDCPE_D_Z2_OUT3: FDCPE port map (D_Z2_OUT(3),D_Z2_OUT_D(3),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET);
D_Z2_OUT_D(3) <= ((NOT AS AND NOT AUTO_CONFIG_Z2_DONE(0) AND NOT UDS AND NOT A(5) AND
AUTOCONFIG_Z2_ACCESS AND A(1) AND NOT A(6) AND NOT A(3))
OR (NOT AS AND NOT AUTO_CONFIG_Z2_DONE(0) AND NOT LDS AND NOT A(5) AND
AUTOCONFIG_Z2_ACCESS AND A(1) AND NOT A(6) AND NOT A(3))
OR (NOT AS AND NOT AUTO_CONFIG_Z2_DONE(1) AND NOT UDS AND NOT A(5) AND
AUTOCONFIG_Z2_ACCESS AND A(1) AND NOT A(6) AND NOT A(3))
OR (NOT AS AND NOT AUTO_CONFIG_Z2_DONE(1) AND NOT LDS AND NOT A(5) AND
AUTOCONFIG_Z2_ACCESS AND A(1) AND NOT A(6) AND NOT A(3))
OR (NOT AS AND NOT LDS AND NOT A(2) AND NOT A(5) AND AUTOCONFIG_Z2_ACCESS AND
A(1) AND NOT A(6) AND NOT A(3))
OR (NOT AS AND NOT UDS AND A(2) AND A(5) AND NOT A(4) AND
AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND NOT A(6) AND NOT A(3))
OR (NOT AS AND NOT UDS AND NOT A(2) AND NOT A(5) AND A(4) AND
AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND NOT A(6) AND A(3))
OR (NOT AS AND NOT LDS AND A(2) AND A(5) AND NOT A(4) AND
AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND NOT A(6) AND NOT A(3))
OR (NOT AS AND NOT LDS AND NOT A(2) AND NOT A(5) AND A(4) AND
AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND NOT A(6) AND A(3))
OR (NOT AS AND NOT UDS AND A(2) AND NOT A(5) AND A(4) AND
AUTOCONFIG_Z2_ACCESS AND A(1) AND NOT A(6))
OR (NOT AS AND NOT UDS AND NOT A(2) AND NOT A(5) AND AUTOCONFIG_Z2_ACCESS AND
A(1) AND NOT A(6) AND NOT A(3))
OR (NOT AS AND NOT LDS AND A(2) AND NOT A(5) AND A(4) AND
AUTOCONFIG_Z2_ACCESS AND A(1) AND NOT A(6)));
IDE_A(0) <= A(9).PIN;
IDE_A(1) <= A(10).PIN;
IDE_A(2) <= A(11).PIN;
FDCPE_IDE_ACCESS: FDCPE port map (IDE_ACCESS,IDE_ACCESS_D,NOT AS,NOT RESET,'0');
IDE_ACCESS_D <= ((IDE_BASEADR(4) AND A(20).PIN AND NOT $OpTx$INV$125)
OR (NOT IDE_BASEADR(4) AND NOT A(20).PIN AND NOT $OpTx$INV$125));
FTCPE_IDE_BASEADR0: FTCPE port map (IDE_BASEADR(0),IDE_BASEADR_T(0),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET);
IDE_BASEADR_T(0) <= ((NOT RW AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND
AUTO_CONFIG_Z2_DONE(1) AND NOT UDS AND NOT AUTO_CONFIG_Z2_DONE(2) AND D(8).PIN AND
NOT IDE_BASEADR(0) AND NOT A(2) AND NOT A(5) AND NOT A(4) AND AUTOCONFIG_Z2_ACCESS AND
NOT A(1) AND A(6) AND A(3))
OR (NOT RW AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND
AUTO_CONFIG_Z2_DONE(1) AND NOT UDS AND NOT AUTO_CONFIG_Z2_DONE(2) AND NOT D(8).PIN AND
IDE_BASEADR(0) AND NOT A(2) AND NOT A(5) AND NOT A(4) AND AUTOCONFIG_Z2_ACCESS AND
NOT A(1) AND A(6) AND A(3))
OR (NOT RW AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND
AUTO_CONFIG_Z2_DONE(1) AND NOT LDS AND NOT AUTO_CONFIG_Z2_DONE(2) AND D(8).PIN AND
NOT IDE_BASEADR(0) AND NOT A(2) AND NOT A(5) AND NOT A(4) AND AUTOCONFIG_Z2_ACCESS AND
NOT A(1) AND A(6) AND A(3))
OR (NOT RW AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND
AUTO_CONFIG_Z2_DONE(1) AND NOT LDS AND NOT AUTO_CONFIG_Z2_DONE(2) AND NOT D(8).PIN AND
IDE_BASEADR(0) AND NOT A(2) AND NOT A(5) AND NOT A(4) AND AUTOCONFIG_Z2_ACCESS AND
NOT A(1) AND A(6) AND A(3)));
FTCPE_IDE_BASEADR1: FTCPE port map (IDE_BASEADR(1),IDE_BASEADR_T(1),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET);
IDE_BASEADR_T(1) <= ((NOT RW AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND
AUTO_CONFIG_Z2_DONE(1) AND NOT LDS AND NOT AUTO_CONFIG_Z2_DONE(2) AND D(9).PIN AND
NOT IDE_BASEADR(1) AND NOT A(2) AND NOT A(5) AND NOT A(4) AND AUTOCONFIG_Z2_ACCESS AND
NOT A(1) AND A(6) AND A(3))
OR (NOT RW AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND
AUTO_CONFIG_Z2_DONE(1) AND NOT UDS AND NOT AUTO_CONFIG_Z2_DONE(2) AND D(9).PIN AND
NOT IDE_BASEADR(1) AND NOT A(2) AND NOT A(5) AND NOT A(4) AND AUTOCONFIG_Z2_ACCESS AND
NOT A(1) AND A(6) AND A(3))
OR (NOT RW AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND
AUTO_CONFIG_Z2_DONE(1) AND NOT UDS AND NOT AUTO_CONFIG_Z2_DONE(2) AND NOT D(9).PIN AND
IDE_BASEADR(1) AND NOT A(2) AND NOT A(5) AND NOT A(4) AND AUTOCONFIG_Z2_ACCESS AND
NOT A(1) AND A(6) AND A(3))
OR (NOT RW AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND
AUTO_CONFIG_Z2_DONE(1) AND NOT LDS AND NOT AUTO_CONFIG_Z2_DONE(2) AND NOT D(9).PIN AND
IDE_BASEADR(1) AND NOT A(2) AND NOT A(5) AND NOT A(4) AND AUTOCONFIG_Z2_ACCESS AND
NOT A(1) AND A(6) AND A(3)));
FTCPE_IDE_BASEADR2: FTCPE port map (IDE_BASEADR(2),IDE_BASEADR_T(2),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET);
IDE_BASEADR_T(2) <= ((NOT RW AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND
AUTO_CONFIG_Z2_DONE(1) AND NOT LDS AND NOT AUTO_CONFIG_Z2_DONE(2) AND D(10).PIN AND
NOT IDE_BASEADR(2) AND NOT A(2) AND NOT A(5) AND NOT A(4) AND AUTOCONFIG_Z2_ACCESS AND
NOT A(1) AND A(6) AND A(3))
OR (NOT RW AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND
AUTO_CONFIG_Z2_DONE(1) AND NOT UDS AND NOT AUTO_CONFIG_Z2_DONE(2) AND D(10).PIN AND
NOT IDE_BASEADR(2) AND NOT A(2) AND NOT A(5) AND NOT A(4) AND AUTOCONFIG_Z2_ACCESS AND
NOT A(1) AND A(6) AND A(3))
OR (NOT RW AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND
AUTO_CONFIG_Z2_DONE(1) AND NOT UDS AND NOT AUTO_CONFIG_Z2_DONE(2) AND NOT D(10).PIN AND
IDE_BASEADR(2) AND NOT A(2) AND NOT A(5) AND NOT A(4) AND AUTOCONFIG_Z2_ACCESS AND
NOT A(1) AND A(6) AND A(3))
OR (NOT RW AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND
AUTO_CONFIG_Z2_DONE(1) AND NOT LDS AND NOT AUTO_CONFIG_Z2_DONE(2) AND NOT D(10).PIN AND
IDE_BASEADR(2) AND NOT A(2) AND NOT A(5) AND NOT A(4) AND AUTOCONFIG_Z2_ACCESS AND
NOT A(1) AND A(6) AND A(3)));
FTCPE_IDE_BASEADR3: FTCPE port map (IDE_BASEADR(3),IDE_BASEADR_T(3),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET);
IDE_BASEADR_T(3) <= ((NOT RW AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND
AUTO_CONFIG_Z2_DONE(1) AND NOT LDS AND NOT AUTO_CONFIG_Z2_DONE(2) AND D(11).PIN AND
NOT IDE_BASEADR(3) AND NOT A(2) AND NOT A(5) AND NOT A(4) AND AUTOCONFIG_Z2_ACCESS AND
NOT A(1) AND A(6) AND A(3))
OR (NOT RW AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND
AUTO_CONFIG_Z2_DONE(1) AND NOT UDS AND NOT AUTO_CONFIG_Z2_DONE(2) AND D(11).PIN AND
NOT IDE_BASEADR(3) AND NOT A(2) AND NOT A(5) AND NOT A(4) AND AUTOCONFIG_Z2_ACCESS AND
NOT A(1) AND A(6) AND A(3))
OR (NOT RW AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND
AUTO_CONFIG_Z2_DONE(1) AND NOT UDS AND NOT AUTO_CONFIG_Z2_DONE(2) AND NOT D(11).PIN AND
IDE_BASEADR(3) AND NOT A(2) AND NOT A(5) AND NOT A(4) AND AUTOCONFIG_Z2_ACCESS AND
NOT A(1) AND A(6) AND A(3))
OR (NOT RW AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND
AUTO_CONFIG_Z2_DONE(1) AND NOT LDS AND NOT AUTO_CONFIG_Z2_DONE(2) AND NOT D(11).PIN AND
IDE_BASEADR(3) AND NOT A(2) AND NOT A(5) AND NOT A(4) AND AUTOCONFIG_Z2_ACCESS AND
NOT A(1) AND A(6) AND A(3)));
FTCPE_IDE_BASEADR4: FTCPE port map (IDE_BASEADR(4),IDE_BASEADR_T(4),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET);
IDE_BASEADR_T(4) <= ((NOT RW AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND
AUTO_CONFIG_Z2_DONE(1) AND NOT LDS AND NOT AUTO_CONFIG_Z2_DONE(2) AND D(12).PIN AND
NOT IDE_BASEADR(4) AND NOT A(2) AND NOT A(5) AND NOT A(4) AND AUTOCONFIG_Z2_ACCESS AND
NOT A(1) AND A(6) AND A(3))
OR (NOT RW AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND
AUTO_CONFIG_Z2_DONE(1) AND NOT UDS AND NOT AUTO_CONFIG_Z2_DONE(2) AND D(12).PIN AND
NOT IDE_BASEADR(4) AND NOT A(2) AND NOT A(5) AND NOT A(4) AND AUTOCONFIG_Z2_ACCESS AND
NOT A(1) AND A(6) AND A(3))
OR (NOT RW AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND
AUTO_CONFIG_Z2_DONE(1) AND NOT UDS AND NOT AUTO_CONFIG_Z2_DONE(2) AND NOT D(12).PIN AND
IDE_BASEADR(4) AND NOT A(2) AND NOT A(5) AND NOT A(4) AND AUTOCONFIG_Z2_ACCESS AND
NOT A(1) AND A(6) AND A(3))
OR (NOT RW AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND
AUTO_CONFIG_Z2_DONE(1) AND NOT LDS AND NOT AUTO_CONFIG_Z2_DONE(2) AND NOT D(12).PIN AND
IDE_BASEADR(4) AND NOT A(2) AND NOT A(5) AND NOT A(4) AND AUTOCONFIG_Z2_ACCESS AND
NOT A(1) AND A(6) AND A(3)));
FTCPE_IDE_BASEADR5: FTCPE port map (IDE_BASEADR(5),IDE_BASEADR_T(5),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET);
IDE_BASEADR_T(5) <= ((NOT RW AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND
AUTO_CONFIG_Z2_DONE(1) AND NOT LDS AND NOT AUTO_CONFIG_Z2_DONE(2) AND D(13).PIN AND
NOT IDE_BASEADR(5) AND NOT A(2) AND NOT A(5) AND NOT A(4) AND AUTOCONFIG_Z2_ACCESS AND
NOT A(1) AND A(6) AND A(3))
OR (NOT RW AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND
AUTO_CONFIG_Z2_DONE(1) AND NOT UDS AND NOT AUTO_CONFIG_Z2_DONE(2) AND D(13).PIN AND
NOT IDE_BASEADR(5) AND NOT A(2) AND NOT A(5) AND NOT A(4) AND AUTOCONFIG_Z2_ACCESS AND
NOT A(1) AND A(6) AND A(3))
OR (NOT RW AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND
AUTO_CONFIG_Z2_DONE(1) AND NOT UDS AND NOT AUTO_CONFIG_Z2_DONE(2) AND NOT D(13).PIN AND
IDE_BASEADR(5) AND NOT A(2) AND NOT A(5) AND NOT A(4) AND AUTOCONFIG_Z2_ACCESS AND
NOT A(1) AND A(6) AND A(3))
OR (NOT RW AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND
AUTO_CONFIG_Z2_DONE(1) AND NOT LDS AND NOT AUTO_CONFIG_Z2_DONE(2) AND NOT D(13).PIN AND
IDE_BASEADR(5) AND NOT A(2) AND NOT A(5) AND NOT A(4) AND AUTOCONFIG_Z2_ACCESS AND
NOT A(1) AND A(6) AND A(3)));
FTCPE_IDE_BASEADR6: FTCPE port map (IDE_BASEADR(6),IDE_BASEADR_T(6),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET);
IDE_BASEADR_T(6) <= ((NOT RW AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND
AUTO_CONFIG_Z2_DONE(1) AND NOT LDS AND NOT AUTO_CONFIG_Z2_DONE(2) AND D(14).PIN AND
NOT IDE_BASEADR(6) AND NOT A(2) AND NOT A(5) AND NOT A(4) AND AUTOCONFIG_Z2_ACCESS AND
NOT A(1) AND A(6) AND A(3))
OR (NOT RW AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND
AUTO_CONFIG_Z2_DONE(1) AND NOT UDS AND NOT AUTO_CONFIG_Z2_DONE(2) AND D(14).PIN AND
NOT IDE_BASEADR(6) AND NOT A(2) AND NOT A(5) AND NOT A(4) AND AUTOCONFIG_Z2_ACCESS AND
NOT A(1) AND A(6) AND A(3))
OR (NOT RW AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND
AUTO_CONFIG_Z2_DONE(1) AND NOT UDS AND NOT AUTO_CONFIG_Z2_DONE(2) AND NOT D(14).PIN AND
IDE_BASEADR(6) AND NOT A(2) AND NOT A(5) AND NOT A(4) AND AUTOCONFIG_Z2_ACCESS AND
NOT A(1) AND A(6) AND A(3))
OR (NOT RW AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND
AUTO_CONFIG_Z2_DONE(1) AND NOT LDS AND NOT AUTO_CONFIG_Z2_DONE(2) AND NOT D(14).PIN AND
IDE_BASEADR(6) AND NOT A(2) AND NOT A(5) AND NOT A(4) AND AUTOCONFIG_Z2_ACCESS AND
NOT A(1) AND A(6) AND A(3)));
FTCPE_IDE_BASEADR7: FTCPE port map (IDE_BASEADR(7),IDE_BASEADR_T(7),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET);
IDE_BASEADR_T(7) <= ((NOT RW AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND
AUTO_CONFIG_Z2_DONE(1) AND NOT LDS AND NOT AUTO_CONFIG_Z2_DONE(2) AND D(15).PIN AND
NOT IDE_BASEADR(7) AND NOT A(2) AND NOT A(5) AND NOT A(4) AND AUTOCONFIG_Z2_ACCESS AND
NOT A(1) AND A(6) AND A(3))
OR (NOT RW AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND
AUTO_CONFIG_Z2_DONE(1) AND NOT UDS AND NOT AUTO_CONFIG_Z2_DONE(2) AND D(15).PIN AND
NOT IDE_BASEADR(7) AND NOT A(2) AND NOT A(5) AND NOT A(4) AND AUTOCONFIG_Z2_ACCESS AND
NOT A(1) AND A(6) AND A(3))
OR (NOT RW AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND
AUTO_CONFIG_Z2_DONE(1) AND NOT UDS AND NOT AUTO_CONFIG_Z2_DONE(2) AND NOT D(15).PIN AND
IDE_BASEADR(7) AND NOT A(2) AND NOT A(5) AND NOT A(4) AND AUTOCONFIG_Z2_ACCESS AND
NOT A(1) AND A(6) AND A(3))
OR (NOT RW AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND
AUTO_CONFIG_Z2_DONE(1) AND NOT LDS AND NOT AUTO_CONFIG_Z2_DONE(2) AND NOT D(15).PIN AND
IDE_BASEADR(7) AND NOT A(2) AND NOT A(5) AND NOT A(4) AND AUTOCONFIG_Z2_ACCESS AND
NOT A(1) AND A(6) AND A(3)));
IDE_CS(0) <= NOT A(12).PIN;
IDE_CS(1) <= NOT A(13).PIN;
FDCPE_IDE_ENABLE: FDCPE port map (IDE_ENABLE,'0',SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET,IDE_ENABLE_CE);
IDE_ENABLE_CE <= (NOT RW AND NOT AS AND IDE_ACCESS);
IDE_R <= NOT ((NOT AS AND NOT IDE_R_S));
FDCPE_IDE_R_S: FDCPE port map (IDE_R_S,IDE_R_S_D,SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET);
IDE_R_S_D <= (RW AND NOT AS AND IDE_ACCESS AND NOT IDE_ENABLE);
IDE_W <= NOT ((NOT AS AND NOT IDE_W_S));
FDCPE_IDE_W_S: FDCPE port map (IDE_W_S,IDE_W_S_D,SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET);
IDE_W_S_D <= (NOT RW AND NOT AS AND IDE_ACCESS);
INT2_OUT_I <= '0';
INT2_OUT <= INT2_OUT_I when INT2_OUT_OE = '1' else 'Z';
INT2_OUT_OE <= (LAN_INT_ENABLE AND NOT LAN_INT);
INT6_OUT_I <= '0';
INT6_OUT <= INT6_OUT_I when INT6_OUT_OE = '1' else 'Z';
INT6_OUT_OE <= NOT CP_IRQ;
FDCPE_LAN_ACCESS: FDCPE port map (LAN_ACCESS,LAN_ACCESS_D,NOT FCS,NOT RESET,'0');
LAN_ACCESS_D <= ((D(13).PIN AND LAN_BASEADR(13) AND NOT LAN_BASEADR(6) AND
NOT A(22).PIN AND NOT $OpTx$INV$123 AND NOT $OpTx$INV$124)
OR (NOT D(13).PIN AND NOT LAN_BASEADR(13) AND NOT LAN_BASEADR(6) AND
NOT A(22).PIN AND NOT $OpTx$INV$123 AND NOT $OpTx$INV$124)
OR (D(13).PIN AND LAN_BASEADR(13) AND LAN_BASEADR(6) AND
A(22).PIN AND NOT $OpTx$INV$123 AND NOT $OpTx$INV$124)
OR (NOT D(13).PIN AND NOT LAN_BASEADR(13) AND LAN_BASEADR(6) AND
A(22).PIN AND NOT $OpTx$INV$123 AND NOT $OpTx$INV$124));
FDCPE_LAN_A_INIT3: FDCPE port map (LAN_A_INIT(3),'0',CLK_EXT,'0',RESET);
FDCPE_LAN_A_INIT6: FDCPE port map (LAN_A_INIT(6),NOT LAN_RST_SM_FSM_FFd1,CLK_EXT,'0',RESET);
FTCPE_LAN_BASEADR0: FTCPE port map (LAN_BASEADR(0),LAN_BASEADR_T(0),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET);
LAN_BASEADR_T(0) <= ((NOT RW AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(0) AND NOT UDS AND
D(8).PIN AND NOT LAN_BASEADR(0) AND NOT A(2) AND NOT A(5) AND NOT A(4) AND
AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND A(3))
OR (NOT RW AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(0) AND NOT LDS AND
D(8).PIN AND NOT LAN_BASEADR(0) AND NOT A(2) AND NOT A(5) AND NOT A(4) AND
AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND A(3))
OR (NOT RW AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(0) AND NOT UDS AND
NOT D(8).PIN AND LAN_BASEADR(0) AND NOT A(2) AND NOT A(5) AND NOT A(4) AND
AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND A(3))
OR (NOT RW AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(0) AND NOT LDS AND
NOT D(8).PIN AND LAN_BASEADR(0) AND NOT A(2) AND NOT A(5) AND NOT A(4) AND
AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND A(3)));
FTCPE_LAN_BASEADR1: FTCPE port map (LAN_BASEADR(1),LAN_BASEADR_T(1),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET);
LAN_BASEADR_T(1) <= ((NOT RW AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(0) AND NOT LDS AND
D(9).PIN AND NOT LAN_BASEADR(1) AND NOT A(2) AND NOT A(5) AND NOT A(4) AND
AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND A(3))
OR (NOT RW AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(0) AND NOT UDS AND
D(9).PIN AND NOT LAN_BASEADR(1) AND NOT A(2) AND NOT A(5) AND NOT A(4) AND
AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND A(3))
OR (NOT RW AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(0) AND NOT UDS AND
NOT D(9).PIN AND LAN_BASEADR(1) AND NOT A(2) AND NOT A(5) AND NOT A(4) AND
AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND A(3))
OR (NOT RW AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(0) AND NOT LDS AND
NOT D(9).PIN AND LAN_BASEADR(1) AND NOT A(2) AND NOT A(5) AND NOT A(4) AND
AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND A(3)));
FTCPE_LAN_BASEADR2: FTCPE port map (LAN_BASEADR(2),LAN_BASEADR_T(2),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET);
LAN_BASEADR_T(2) <= ((NOT RW AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(0) AND NOT LDS AND
D(10).PIN AND NOT LAN_BASEADR(2) AND NOT A(2) AND NOT A(5) AND NOT A(4) AND
AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND A(3))
OR (NOT RW AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(0) AND NOT UDS AND
D(10).PIN AND NOT LAN_BASEADR(2) AND NOT A(2) AND NOT A(5) AND NOT A(4) AND
AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND A(3))
OR (NOT RW AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(0) AND NOT UDS AND
NOT D(10).PIN AND LAN_BASEADR(2) AND NOT A(2) AND NOT A(5) AND NOT A(4) AND
AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND A(3))
OR (NOT RW AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(0) AND NOT LDS AND
NOT D(10).PIN AND LAN_BASEADR(2) AND NOT A(2) AND NOT A(5) AND NOT A(4) AND
AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND A(3)));
FTCPE_LAN_BASEADR3: FTCPE port map (LAN_BASEADR(3),LAN_BASEADR_T(3),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET);
LAN_BASEADR_T(3) <= ((NOT RW AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(0) AND NOT UDS AND
D(11).PIN AND NOT LAN_BASEADR(3) AND NOT A(2) AND NOT A(5) AND NOT A(4) AND
AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND A(3))
OR (NOT RW AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(0) AND NOT LDS AND
D(11).PIN AND NOT LAN_BASEADR(3) AND NOT A(2) AND NOT A(5) AND NOT A(4) AND
AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND A(3))
OR (NOT RW AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(0) AND NOT UDS AND
NOT D(11).PIN AND LAN_BASEADR(3) AND NOT A(2) AND NOT A(5) AND NOT A(4) AND
AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND A(3))
OR (NOT RW AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(0) AND NOT LDS AND
NOT D(11).PIN AND LAN_BASEADR(3) AND NOT A(2) AND NOT A(5) AND NOT A(4) AND
AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND A(3)));
FTCPE_LAN_BASEADR4: FTCPE port map (LAN_BASEADR(4),LAN_BASEADR_T(4),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET);
LAN_BASEADR_T(4) <= ((NOT RW AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(0) AND NOT LDS AND
D(12).PIN AND NOT LAN_BASEADR(4) AND NOT A(2) AND NOT A(5) AND NOT A(4) AND
AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND A(3))
OR (NOT RW AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(0) AND NOT UDS AND
D(12).PIN AND NOT LAN_BASEADR(4) AND NOT A(2) AND NOT A(5) AND NOT A(4) AND
AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND A(3))
OR (NOT RW AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(0) AND NOT UDS AND
NOT D(12).PIN AND LAN_BASEADR(4) AND NOT A(2) AND NOT A(5) AND NOT A(4) AND
AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND A(3))
OR (NOT RW AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(0) AND NOT LDS AND
NOT D(12).PIN AND LAN_BASEADR(4) AND NOT A(2) AND NOT A(5) AND NOT A(4) AND
AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND A(3)));
FTCPE_LAN_BASEADR5: FTCPE port map (LAN_BASEADR(5),LAN_BASEADR_T(5),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET);
LAN_BASEADR_T(5) <= ((NOT RW AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(0) AND NOT LDS AND
D(13).PIN AND NOT LAN_BASEADR(5) AND NOT A(2) AND NOT A(5) AND NOT A(4) AND
AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND A(3))
OR (NOT RW AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(0) AND NOT UDS AND
D(13).PIN AND NOT LAN_BASEADR(5) AND NOT A(2) AND NOT A(5) AND NOT A(4) AND
AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND A(3))
OR (NOT RW AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(0) AND NOT UDS AND
NOT D(13).PIN AND LAN_BASEADR(5) AND NOT A(2) AND NOT A(5) AND NOT A(4) AND
AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND A(3))
OR (NOT RW AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(0) AND NOT LDS AND
NOT D(13).PIN AND LAN_BASEADR(5) AND NOT A(2) AND NOT A(5) AND NOT A(4) AND
AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND A(3)));
FTCPE_LAN_BASEADR6: FTCPE port map (LAN_BASEADR(6),LAN_BASEADR_T(6),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET);
LAN_BASEADR_T(6) <= ((NOT RW AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(0) AND NOT UDS AND
D(14).PIN AND NOT LAN_BASEADR(6) AND NOT A(2) AND NOT A(5) AND NOT A(4) AND
AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND A(3))
OR (NOT RW AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(0) AND NOT LDS AND
D(14).PIN AND NOT LAN_BASEADR(6) AND NOT A(2) AND NOT A(5) AND NOT A(4) AND
AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND A(3))
OR (NOT RW AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(0) AND NOT LDS AND
NOT D(14).PIN AND LAN_BASEADR(6) AND NOT A(2) AND NOT A(5) AND NOT A(4) AND
AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND A(3))
OR (NOT RW AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(0) AND NOT UDS AND
NOT D(14).PIN AND LAN_BASEADR(6) AND NOT A(2) AND NOT A(5) AND NOT A(4) AND
AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND A(3)));
FTCPE_LAN_BASEADR7: FTCPE port map (LAN_BASEADR(7),LAN_BASEADR_T(7),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET);
LAN_BASEADR_T(7) <= ((NOT RW AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(0) AND NOT UDS AND
D(15).PIN AND NOT LAN_BASEADR(7) AND NOT A(2) AND NOT A(5) AND NOT A(4) AND
AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND A(3))
OR (NOT RW AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(0) AND NOT UDS AND
NOT D(15).PIN AND LAN_BASEADR(7) AND NOT A(2) AND NOT A(5) AND NOT A(4) AND
AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND A(3))
OR (NOT RW AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(0) AND NOT LDS AND
D(15).PIN AND NOT LAN_BASEADR(7) AND NOT A(2) AND NOT A(5) AND NOT A(4) AND
AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND A(3))
OR (NOT RW AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(0) AND NOT LDS AND
NOT D(15).PIN AND LAN_BASEADR(7) AND NOT A(2) AND NOT A(5) AND NOT A(4) AND
AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND A(3)));
FTCPE_LAN_BASEADR8: FTCPE port map (LAN_BASEADR(8),LAN_BASEADR_T(8),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET);
LAN_BASEADR_T(8) <= ((NOT RW AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(0) AND NOT UDS AND
D(8).PIN AND NOT LAN_BASEADR(8) AND A(2) AND NOT A(5) AND NOT A(4) AND
AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND NOT A(3))
OR (NOT RW AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(0) AND NOT LDS AND
D(8).PIN AND NOT LAN_BASEADR(8) AND A(2) AND NOT A(5) AND NOT A(4) AND
AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND NOT A(3))
OR (NOT RW AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(0) AND NOT UDS AND
NOT D(8).PIN AND LAN_BASEADR(8) AND A(2) AND NOT A(5) AND NOT A(4) AND
AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND NOT A(3))
OR (NOT RW AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(0) AND NOT LDS AND
NOT D(8).PIN AND LAN_BASEADR(8) AND A(2) AND NOT A(5) AND NOT A(4) AND
AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND NOT A(3)));
FTCPE_LAN_BASEADR9: FTCPE port map (LAN_BASEADR(9),LAN_BASEADR_T(9),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET);
LAN_BASEADR_T(9) <= ((NOT RW AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(0) AND NOT LDS AND
D(9).PIN AND NOT LAN_BASEADR(9) AND A(2) AND NOT A(5) AND NOT A(4) AND
AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND NOT A(3))
OR (NOT RW AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(0) AND NOT UDS AND
D(9).PIN AND NOT LAN_BASEADR(9) AND A(2) AND NOT A(5) AND NOT A(4) AND
AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND NOT A(3))
OR (NOT RW AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(0) AND NOT UDS AND
NOT D(9).PIN AND LAN_BASEADR(9) AND A(2) AND NOT A(5) AND NOT A(4) AND
AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND NOT A(3))
OR (NOT RW AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(0) AND NOT LDS AND
NOT D(9).PIN AND LAN_BASEADR(9) AND A(2) AND NOT A(5) AND NOT A(4) AND
AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND NOT A(3)));
FTCPE_LAN_BASEADR10: FTCPE port map (LAN_BASEADR(10),LAN_BASEADR_T(10),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET);
LAN_BASEADR_T(10) <= ((NOT RW AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(0) AND NOT UDS AND
D(10).PIN AND NOT LAN_BASEADR(10) AND A(2) AND NOT A(5) AND NOT A(4) AND
AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND NOT A(3))
OR (NOT RW AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(0) AND NOT LDS AND
D(10).PIN AND NOT LAN_BASEADR(10) AND A(2) AND NOT A(5) AND NOT A(4) AND
AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND NOT A(3))
OR (NOT RW AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(0) AND NOT LDS AND
NOT D(10).PIN AND LAN_BASEADR(10) AND A(2) AND NOT A(5) AND NOT A(4) AND
AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND NOT A(3))
OR (NOT RW AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(0) AND NOT UDS AND
NOT D(10).PIN AND LAN_BASEADR(10) AND A(2) AND NOT A(5) AND NOT A(4) AND
AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND NOT A(3)));
FTCPE_LAN_BASEADR11: FTCPE port map (LAN_BASEADR(11),LAN_BASEADR_T(11),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET);
LAN_BASEADR_T(11) <= ((NOT RW AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(0) AND NOT UDS AND
D(11).PIN AND NOT LAN_BASEADR(11) AND A(2) AND NOT A(5) AND NOT A(4) AND
AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND NOT A(3))
OR (NOT RW AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(0) AND NOT UDS AND
NOT D(11).PIN AND LAN_BASEADR(11) AND A(2) AND NOT A(5) AND NOT A(4) AND
AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND NOT A(3))
OR (NOT RW AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(0) AND NOT LDS AND
D(11).PIN AND NOT LAN_BASEADR(11) AND A(2) AND NOT A(5) AND NOT A(4) AND
AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND NOT A(3))
OR (NOT RW AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(0) AND NOT LDS AND
NOT D(11).PIN AND LAN_BASEADR(11) AND A(2) AND NOT A(5) AND NOT A(4) AND
AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND NOT A(3)));
FTCPE_LAN_BASEADR12: FTCPE port map (LAN_BASEADR(12),LAN_BASEADR_T(12),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET);
LAN_BASEADR_T(12) <= ((NOT RW AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(0) AND NOT LDS AND
D(12).PIN AND NOT LAN_BASEADR(12) AND A(2) AND NOT A(5) AND NOT A(4) AND
AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND NOT A(3))
OR (NOT RW AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(0) AND NOT UDS AND
D(12).PIN AND NOT LAN_BASEADR(12) AND A(2) AND NOT A(5) AND NOT A(4) AND
AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND NOT A(3))
OR (NOT RW AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(0) AND NOT UDS AND
NOT D(12).PIN AND LAN_BASEADR(12) AND A(2) AND NOT A(5) AND NOT A(4) AND
AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND NOT A(3))
OR (NOT RW AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(0) AND NOT LDS AND
NOT D(12).PIN AND LAN_BASEADR(12) AND A(2) AND NOT A(5) AND NOT A(4) AND
AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND NOT A(3)));
FTCPE_LAN_BASEADR13: FTCPE port map (LAN_BASEADR(13),LAN_BASEADR_T(13),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET);
LAN_BASEADR_T(13) <= ((NOT RW AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(0) AND NOT UDS AND
D(13).PIN AND NOT LAN_BASEADR(13) AND A(2) AND NOT A(5) AND NOT A(4) AND
AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND NOT A(3))
OR (NOT RW AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(0) AND NOT LDS AND
D(13).PIN AND NOT LAN_BASEADR(13) AND A(2) AND NOT A(5) AND NOT A(4) AND
AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND NOT A(3))
OR (NOT RW AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(0) AND NOT UDS AND
NOT D(13).PIN AND LAN_BASEADR(13) AND A(2) AND NOT A(5) AND NOT A(4) AND
AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND NOT A(3))
OR (NOT RW AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(0) AND NOT LDS AND
NOT D(13).PIN AND LAN_BASEADR(13) AND A(2) AND NOT A(5) AND NOT A(4) AND
AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND NOT A(3)));
FTCPE_LAN_BASEADR14: FTCPE port map (LAN_BASEADR(14),LAN_BASEADR_T(14),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET);
LAN_BASEADR_T(14) <= ((NOT RW AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(0) AND NOT LDS AND
D(14).PIN AND NOT LAN_BASEADR(14) AND A(2) AND NOT A(5) AND NOT A(4) AND
AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND NOT A(3))
OR (NOT RW AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(0) AND NOT UDS AND
D(14).PIN AND NOT LAN_BASEADR(14) AND A(2) AND NOT A(5) AND NOT A(4) AND
AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND NOT A(3))
OR (NOT RW AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(0) AND NOT UDS AND
NOT D(14).PIN AND LAN_BASEADR(14) AND A(2) AND NOT A(5) AND NOT A(4) AND
AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND NOT A(3))
OR (NOT RW AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(0) AND NOT LDS AND
NOT D(14).PIN AND LAN_BASEADR(14) AND A(2) AND NOT A(5) AND NOT A(4) AND
AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND NOT A(3)));
FTCPE_LAN_BASEADR15: FTCPE port map (LAN_BASEADR(15),LAN_BASEADR_T(15),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET);
LAN_BASEADR_T(15) <= ((NOT RW AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(0) AND NOT LDS AND
D(15).PIN AND NOT LAN_BASEADR(15) AND A(2) AND NOT A(5) AND NOT A(4) AND
AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND NOT A(3))
OR (NOT RW AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(0) AND NOT UDS AND
D(15).PIN AND NOT LAN_BASEADR(15) AND A(2) AND NOT A(5) AND NOT A(4) AND
AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND NOT A(3))
OR (NOT RW AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(0) AND NOT UDS AND
NOT D(15).PIN AND LAN_BASEADR(15) AND A(2) AND NOT A(5) AND NOT A(4) AND
AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND NOT A(3))
OR (NOT RW AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(0) AND NOT LDS AND
NOT D(15).PIN AND LAN_BASEADR(15) AND A(2) AND NOT A(5) AND NOT A(4) AND
AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND A(6) AND NOT A(3)));
LAN_CFG_I(1) <= '0';
LAN_CFG(1) <= LAN_CFG_I(1) when LAN_CFG_OE(1) = '1' else 'Z';
LAN_CFG_OE(1) <= '0';
LAN_CFG_I(2) <= '0';
LAN_CFG(2) <= LAN_CFG_I(2) when LAN_CFG_OE(2) = '1' else 'Z';
LAN_CFG_OE(2) <= '0';
LAN_CFG_I(3) <= '0';
LAN_CFG(3) <= LAN_CFG_I(3) when LAN_CFG_OE(3) = '1' else 'Z';
LAN_CFG_OE(3) <= '0';
LAN_CFG_I(4) <= '0';
LAN_CFG(4) <= LAN_CFG_I(4) when LAN_CFG_OE(4) = '1' else 'Z';
LAN_CFG_OE(4) <= '0';
LAN_CS <= ((NOT RESET AND LAN_CS_RST)
OR (Z3_ADR(13) AND LAN_CS_RST)
OR (RESET AND LAN_ACCESS AND NOT Z3_ADR(13)));
FDCPE_LAN_CS_RST: FDCPE port map (LAN_CS_RST,LAN_CS_RST_D,CLK_EXT,RESET,'0');
LAN_CS_RST_D <= (NOT LAN_D_INIT(8) AND NOT LAN_RST_SM_FSM_FFd3 AND
NOT LAN_RST_SM_FSM_FFd2);
FDCPE_LAN_D_INIT1: FDCPE port map (LAN_D_INIT(1),LAN_RST_SM_FSM_FFd1,CLK_EXT,RESET,'0');
FDCPE_LAN_D_INIT8: FDCPE port map (LAN_D_INIT(8),NOT LAN_RST_SM_FSM_FFd1,CLK_EXT,RESET,'0');
FTCPE_LAN_INT_ENABLE: FTCPE port map (LAN_INT_ENABLE,LAN_INT_ENABLE_T,CLK_EXT,'0','0');
LAN_INT_ENABLE_T <= ((RESET AND NOT RW AND NOT UDS AND D(15).PIN AND NOT LAN_SM_FSM_FFd2 AND
LAN_SM_FSM_FFd8 AND NOT LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd6 AND
NOT LAN_SM_FSM_FFd1 AND NOT LAN_SM_FSM_FFd7 AND NOT LAN_SM_FSM_FFd4 AND
NOT LAN_SM_FSM_FFd5 AND NOT LAN_INT_ENABLE)
OR (RESET AND NOT RW AND NOT UDS AND NOT D(15).PIN AND NOT LAN_SM_FSM_FFd2 AND
LAN_SM_FSM_FFd8 AND NOT LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd6 AND
NOT LAN_SM_FSM_FFd1 AND NOT LAN_SM_FSM_FFd7 AND NOT LAN_SM_FSM_FFd4 AND
NOT LAN_SM_FSM_FFd5 AND LAN_INT_ENABLE)
OR (RESET AND NOT RW AND UDS AND NOT DS1 AND A(23).PIN AND
NOT LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd8 AND NOT LAN_SM_FSM_FFd3 AND
NOT LAN_SM_FSM_FFd6 AND NOT LAN_SM_FSM_FFd1 AND NOT LAN_SM_FSM_FFd7 AND
NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd5 AND NOT LAN_INT_ENABLE)
OR (RESET AND NOT RW AND UDS AND NOT DS1 AND NOT A(23).PIN AND
NOT LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd8 AND NOT LAN_SM_FSM_FFd3 AND
NOT LAN_SM_FSM_FFd6 AND NOT LAN_SM_FSM_FFd1 AND NOT LAN_SM_FSM_FFd7 AND
NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd5 AND LAN_INT_ENABLE));
LAN_RD <= (RESET AND NOT FCS AND LAN_RD_S);
FDCPE_LAN_RD_S: FDCPE port map (LAN_RD_S,LAN_RD_S_D,CLK_EXT,NOT RESET,'0');
LAN_RD_S_D <= ((RW AND NOT FCS AND NOT UDS AND NOT LAN_SM_FSM_FFd2 AND
NOT LAN_SM_FSM_FFd8 AND LAN_ACCESS AND NOT Z3_ADR(13))
OR (RW AND NOT FCS AND NOT LDS AND NOT LAN_SM_FSM_FFd2 AND
NOT LAN_SM_FSM_FFd8 AND LAN_ACCESS AND NOT Z3_ADR(13))
OR (RW AND NOT FCS AND NOT DS1 AND NOT LAN_SM_FSM_FFd2 AND
NOT LAN_SM_FSM_FFd8 AND LAN_ACCESS AND NOT Z3_ADR(13))
OR (RW AND NOT FCS AND NOT DS0 AND NOT LAN_SM_FSM_FFd2 AND
NOT LAN_SM_FSM_FFd8 AND LAN_ACCESS AND NOT Z3_ADR(13))
OR (LAN_SM_FSM_FFd6 AND NOT LAN_SM_FSM_FFd7)
OR (LAN_SM_FSM_FFd6 AND NOT LAN_SM_FSM_FFd5)
OR (NOT LAN_SM_FSM_FFd6 AND LAN_SM_FSM_FFd7));
FDCPE_LAN_READY: FDCPE port map (LAN_READY,LAN_READY_D,CLK_EXT,NOT RESET,'0');
LAN_READY_D <= ((LAN_SM_FSM_FFd8 AND NOT LAN_SM_FSM_FFd7)
OR (LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1 AND CP_WAIT(3))
OR (NOT LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd3 AND CP_WAIT(3))
OR (DS1 AND DS0 AND LAN_SM_FSM_FFd8 AND LAN_SM_FSM_FFd1)
OR (DS1 AND DS0 AND LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd4)
OR (LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3)
OR (NOT LAN_SM_FSM_FFd8 AND LAN_SM_FSM_FFd7)
OR (LAN_SM_FSM_FFd6 AND NOT LAN_SM_FSM_FFd5)
OR (NOT LAN_SM_FSM_FFd6 AND LAN_SM_FSM_FFd5));
FDCPE_LAN_RST_SM_FSM_FFd1: FDCPE port map (LAN_RST_SM_FSM_FFd1,LAN_RST_SM_FSM_FFd1_D,CLK_EXT,RESET,'0');
LAN_RST_SM_FSM_FFd1_D <= ((LAN_D_INIT(8) AND NOT LAN_RST_SM_FSM_FFd1 AND
NOT LAN_RST_SM_FSM_FFd2)
OR (NOT LAN_RST_SM_FSM_FFd1 AND NOT LAN_RST_SM_FSM_FFd3 AND
NOT LAN_RST_SM_FSM_FFd2));
FDCPE_LAN_RST_SM_FSM_FFd2: FDCPE port map (LAN_RST_SM_FSM_FFd2,LAN_RST_SM_FSM_FFd3,CLK_EXT,RESET,'0');
FDCPE_LAN_RST_SM_FSM_FFd3: FDCPE port map (LAN_RST_SM_FSM_FFd3,LAN_D_INIT(8),CLK_EXT,RESET,'0');
FDCPE_LAN_SM_FSM_FFd1: FDCPE port map (LAN_SM_FSM_FFd1,LAN_SM_FSM_FFd1_D,CLK_EXT,NOT RESET,'0');
LAN_SM_FSM_FFd1_D <= ((FCS AND LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
LAN_SM_FSM_FFd3 AND LAN_SM_FSM_FFd6 AND LAN_SM_FSM_FFd1 AND
LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5)
OR (NOT DS1 AND NOT LAN_SM_FSM_FFd8 AND LAN_SM_FSM_FFd3 AND
NOT LAN_SM_FSM_FFd6 AND NOT LAN_SM_FSM_FFd7 AND NOT LAN_SM_FSM_FFd4 AND
NOT LAN_SM_FSM_FFd5 AND NOT CP_WAIT(3))
OR (NOT DS0 AND NOT LAN_SM_FSM_FFd8 AND LAN_SM_FSM_FFd3 AND
NOT LAN_SM_FSM_FFd6 AND NOT LAN_SM_FSM_FFd7 AND NOT LAN_SM_FSM_FFd4 AND
NOT LAN_SM_FSM_FFd5 AND NOT CP_WAIT(3))
OR (LAN_SM_FSM_FFd8 AND LAN_SM_FSM_FFd3 AND
LAN_SM_FSM_FFd6 AND NOT LAN_SM_FSM_FFd1 AND LAN_SM_FSM_FFd7 AND
LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5 AND NOT CP_WAIT(3))
OR (NOT DS1 AND LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd6 AND LAN_SM_FSM_FFd1 AND
NOT LAN_SM_FSM_FFd7 AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd5)
OR (NOT DS0 AND LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd6 AND LAN_SM_FSM_FFd1 AND
NOT LAN_SM_FSM_FFd7 AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd5)
OR (FCS AND NOT LAN_SM_FSM_FFd8 AND LAN_SM_FSM_FFd3 AND
LAN_SM_FSM_FFd6 AND LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5 AND NOT CP_WAIT(3))
OR (NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
NOT LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd6 AND NOT LAN_SM_FSM_FFd7 AND
NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd5)
OR (NOT LAN_SM_FSM_FFd8 AND LAN_SM_FSM_FFd3 AND
LAN_SM_FSM_FFd6 AND NOT LAN_SM_FSM_FFd7 AND LAN_SM_FSM_FFd4 AND
LAN_SM_FSM_FFd5 AND NOT CP_WAIT(3))
OR (LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
LAN_SM_FSM_FFd3 AND LAN_SM_FSM_FFd6 AND LAN_SM_FSM_FFd1 AND
NOT LAN_SM_FSM_FFd7 AND LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5));
FDCPE_LAN_SM_FSM_FFd2: FDCPE port map (LAN_SM_FSM_FFd2,LAN_SM_FSM_FFd2_D,CLK_EXT,NOT RESET,'0');
LAN_SM_FSM_FFd2_D <= ((Z3_DATA(0).EXP)
OR (LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1)
OR (LAN_SM_FSM_FFd8 AND LAN_SM_FSM_FFd1)
OR (LAN_SM_FSM_FFd8 AND NOT LAN_SM_FSM_FFd7)
OR (LAN_SM_FSM_FFd6 AND NOT LAN_SM_FSM_FFd5)
OR (NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5)
OR (NOT FCS AND NOT LAN_SM_FSM_FFd8 AND LAN_SM_FSM_FFd7)
OR (NOT LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd3 AND CP_WAIT(3))
OR (LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd6 AND
$OpTx$$OpTx$FX_DC$134_INV$2056)
OR (LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3)
OR (NOT LAN_SM_FSM_FFd3 AND LAN_SM_FSM_FFd6)
OR (NOT LAN_SM_FSM_FFd6 AND LAN_SM_FSM_FFd7)
OR (NOT LAN_SM_FSM_FFd6 AND LAN_SM_FSM_FFd4));
FDCPE_LAN_SM_FSM_FFd3: FDCPE port map (LAN_SM_FSM_FFd3,LAN_SM_FSM_FFd3_D,CLK_EXT,NOT RESET,'0');
LAN_SM_FSM_FFd3_D <= ((NOT LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd8 AND
NOT LAN_SM_FSM_FFd3 AND LAN_SM_FSM_FFd6 AND NOT LAN_SM_FSM_FFd1 AND
LAN_SM_FSM_FFd7 AND LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5)
OR (NOT DS1 AND LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd6 AND LAN_SM_FSM_FFd1 AND
NOT LAN_SM_FSM_FFd7 AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd5)
OR (NOT DS0 AND LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd6 AND LAN_SM_FSM_FFd1 AND
NOT LAN_SM_FSM_FFd7 AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd5)
OR (UDS AND LDS AND DS1 AND DS0 AND NOT LAN_SM_FSM_FFd2 AND
NOT LAN_SM_FSM_FFd8 AND NOT LAN_SM_FSM_FFd3 AND LAN_SM_FSM_FFd6 AND
NOT LAN_SM_FSM_FFd7 AND LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5)
OR (UDS AND LDS AND DS1 AND DS0 AND NOT LAN_SM_FSM_FFd2 AND
NOT LAN_SM_FSM_FFd8 AND NOT LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd6 AND
NOT LAN_SM_FSM_FFd7 AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd5)
OR (FCS AND LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
LAN_SM_FSM_FFd3 AND LAN_SM_FSM_FFd6 AND LAN_SM_FSM_FFd1 AND
LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5)
OR (FCS AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
NOT LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd6 AND NOT LAN_SM_FSM_FFd7 AND
NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd5)
OR (LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
LAN_SM_FSM_FFd3 AND LAN_SM_FSM_FFd6 AND LAN_SM_FSM_FFd1 AND
NOT LAN_SM_FSM_FFd7 AND LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5)
OR (NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
NOT LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd6 AND NOT LAN_SM_FSM_FFd7 AND
NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd5 AND CP_CS_BUFR)
OR (FCS AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
NOT LAN_SM_FSM_FFd3 AND LAN_SM_FSM_FFd6 AND LAN_SM_FSM_FFd4 AND
LAN_SM_FSM_FFd5)
OR (NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
NOT LAN_SM_FSM_FFd3 AND LAN_SM_FSM_FFd6 AND NOT LAN_SM_FSM_FFd7 AND
LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5 AND LAN_ACCESS)
OR (NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
NOT LAN_SM_FSM_FFd3 AND LAN_SM_FSM_FFd6 AND NOT LAN_SM_FSM_FFd7 AND
LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5 AND CP_CS_BUFR)
OR (NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
NOT LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd6 AND NOT LAN_SM_FSM_FFd7 AND
NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd5 AND LAN_ACCESS));
FDCPE_LAN_SM_FSM_FFd4: FDCPE port map (LAN_SM_FSM_FFd4,LAN_SM_FSM_FFd4_D,CLK_EXT,NOT RESET,'0');
LAN_SM_FSM_FFd4_D <= ((NOT LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd8 AND
NOT LAN_SM_FSM_FFd3 AND LAN_SM_FSM_FFd6 AND NOT LAN_SM_FSM_FFd1 AND
LAN_SM_FSM_FFd7 AND LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5)
OR (FCS AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
NOT LAN_SM_FSM_FFd3 AND LAN_SM_FSM_FFd6 AND LAN_SM_FSM_FFd4 AND
LAN_SM_FSM_FFd5 AND NOT $OpTx$FX_DC$172)
OR (NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
NOT LAN_SM_FSM_FFd3 AND LAN_SM_FSM_FFd6 AND NOT LAN_SM_FSM_FFd7 AND
LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5 AND NOT $OpTx$FX_DC$172)
OR (NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
NOT LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd6 AND NOT LAN_SM_FSM_FFd7 AND
NOT LAN_SM_FSM_FFd5 AND NOT $OpTx$FX_DC$172)
OR (FCS AND LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
LAN_SM_FSM_FFd3 AND LAN_SM_FSM_FFd6 AND LAN_SM_FSM_FFd1 AND
LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5)
OR (LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
LAN_SM_FSM_FFd3 AND LAN_SM_FSM_FFd6 AND LAN_SM_FSM_FFd1 AND
NOT LAN_SM_FSM_FFd7 AND LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5)
OR (LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd6 AND LAN_SM_FSM_FFd1 AND
NOT LAN_SM_FSM_FFd7 AND LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd5));
FDCPE_LAN_SM_FSM_FFd5: FDCPE port map (LAN_SM_FSM_FFd5,LAN_SM_FSM_FFd5_D,CLK_EXT,NOT RESET,'0');
LAN_SM_FSM_FFd5_D <= ((EXP67_.EXP)
OR (RW AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
NOT LAN_SM_FSM_FFd3 AND LAN_SM_FSM_FFd6 AND NOT LAN_SM_FSM_FFd7 AND
LAN_SM_FSM_FFd5 AND LAN_ACCESS)
OR (RW AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
NOT LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd6 AND NOT LAN_SM_FSM_FFd7 AND
NOT LAN_SM_FSM_FFd5 AND LAN_ACCESS)
OR (NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
NOT LAN_SM_FSM_FFd3 AND LAN_SM_FSM_FFd6 AND NOT LAN_SM_FSM_FFd7 AND
LAN_SM_FSM_FFd5 AND LAN_ACCESS AND Z3_ADR(13))
OR (NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
NOT LAN_SM_FSM_FFd3 AND LAN_SM_FSM_FFd6 AND NOT LAN_SM_FSM_FFd7 AND
LAN_SM_FSM_FFd5 AND NOT LAN_ACCESS AND CP_CS_BUFR)
OR (NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
NOT LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd6 AND NOT LAN_SM_FSM_FFd7 AND
NOT LAN_SM_FSM_FFd5 AND LAN_ACCESS AND Z3_ADR(13))
OR (FCS AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
NOT LAN_SM_FSM_FFd3 AND LAN_SM_FSM_FFd6 AND LAN_SM_FSM_FFd5)
OR (FCS AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
NOT LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd6 AND NOT LAN_SM_FSM_FFd7 AND
NOT LAN_SM_FSM_FFd5)
OR (NOT LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd8 AND
NOT LAN_SM_FSM_FFd3 AND LAN_SM_FSM_FFd6 AND NOT LAN_SM_FSM_FFd1 AND
LAN_SM_FSM_FFd7 AND LAN_SM_FSM_FFd5));
FDCPE_LAN_SM_FSM_FFd6: FDCPE port map (LAN_SM_FSM_FFd6,LAN_SM_FSM_FFd6_D,CLK_EXT,NOT RESET,'0');
LAN_SM_FSM_FFd6_D <= ((LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd6 AND LAN_SM_FSM_FFd1 AND
NOT LAN_SM_FSM_FFd7 AND LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd5)
OR (RW AND NOT UDS AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
NOT LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd6 AND NOT LAN_SM_FSM_FFd7 AND
NOT LAN_SM_FSM_FFd5 AND LAN_ACCESS)
OR (RW AND NOT LDS AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
NOT LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd6 AND NOT LAN_SM_FSM_FFd7 AND
NOT LAN_SM_FSM_FFd5 AND LAN_ACCESS)
OR (UDS AND LDS AND DS1 AND DS0 AND NOT LAN_SM_FSM_FFd2 AND
NOT LAN_SM_FSM_FFd8 AND NOT LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd6 AND
NOT LAN_SM_FSM_FFd7 AND NOT LAN_SM_FSM_FFd5)
OR (FCS AND LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
LAN_SM_FSM_FFd3 AND LAN_SM_FSM_FFd6 AND LAN_SM_FSM_FFd1 AND
LAN_SM_FSM_FFd7 AND LAN_SM_FSM_FFd4)
OR (NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
NOT LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd6 AND NOT LAN_SM_FSM_FFd7 AND
NOT LAN_SM_FSM_FFd5 AND NOT LAN_ACCESS AND CP_CS_BUFR)
OR (FCS AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
NOT LAN_SM_FSM_FFd3 AND LAN_SM_FSM_FFd6 AND LAN_SM_FSM_FFd7)
OR (NOT LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd8 AND
NOT LAN_SM_FSM_FFd3 AND LAN_SM_FSM_FFd6 AND NOT LAN_SM_FSM_FFd1 AND
LAN_SM_FSM_FFd7)
OR (FCS AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
NOT LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd6 AND NOT LAN_SM_FSM_FFd7 AND
NOT LAN_SM_FSM_FFd5)
OR (NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
NOT LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd6 AND NOT LAN_SM_FSM_FFd7 AND
NOT LAN_SM_FSM_FFd5 AND LAN_ACCESS AND Z3_ADR(13)));
FDCPE_LAN_SM_FSM_FFd7: FDCPE port map (LAN_SM_FSM_FFd7,LAN_SM_FSM_FFd7_D,CLK_EXT,NOT RESET,'0');
LAN_SM_FSM_FFd7_D <= ((EXP42_.EXP)
OR (FCS AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
NOT LAN_SM_FSM_FFd3 AND LAN_SM_FSM_FFd6 AND LAN_SM_FSM_FFd7)
OR (NOT LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd8 AND
NOT LAN_SM_FSM_FFd3 AND LAN_SM_FSM_FFd6 AND NOT LAN_SM_FSM_FFd1 AND
LAN_SM_FSM_FFd7)
OR (FCS AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
NOT LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd6 AND NOT LAN_SM_FSM_FFd7 AND
NOT LAN_SM_FSM_FFd5)
OR (NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
NOT LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd6 AND NOT LAN_SM_FSM_FFd7 AND
NOT LAN_SM_FSM_FFd5 AND LAN_ACCESS AND Z3_ADR(13))
OR (NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
NOT LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd6 AND NOT LAN_SM_FSM_FFd7 AND
NOT LAN_SM_FSM_FFd5 AND NOT LAN_ACCESS AND CP_CS_BUFR)
OR (NOT DS1 AND NOT LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd8 AND
NOT LAN_SM_FSM_FFd3 AND LAN_SM_FSM_FFd6 AND LAN_SM_FSM_FFd7)
OR (NOT DS0 AND NOT LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd8 AND
NOT LAN_SM_FSM_FFd3 AND LAN_SM_FSM_FFd6 AND LAN_SM_FSM_FFd7));
FDCPE_LAN_SM_FSM_FFd8: FDCPE port map (LAN_SM_FSM_FFd8,LAN_SM_FSM_FFd8_D,CLK_EXT,NOT RESET,'0');
LAN_SM_FSM_FFd8_D <= ((NOT FCS AND NOT UDS AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
NOT CP_CS_BUFR)
OR (NOT FCS AND NOT LDS AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
LAN_ACCESS)
OR (NOT FCS AND NOT LDS AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
NOT CP_CS_BUFR)
OR (NOT FCS AND NOT DS1 AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
NOT CP_CS_BUFR)
OR (NOT FCS AND NOT DS0 AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
NOT CP_CS_BUFR)
OR (LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1 AND NOT CP_WAIT(3))
OR (NOT LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd3 AND NOT CP_WAIT(3))
OR (NOT FCS AND NOT UDS AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
LAN_ACCESS)
OR (NOT FCS AND NOT DS1 AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
LAN_ACCESS)
OR (NOT FCS AND NOT DS0 AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8 AND
LAN_ACCESS)
OR (LAN_SM_FSM_FFd6 AND NOT LAN_SM_FSM_FFd7)
OR (NOT LAN_SM_FSM_FFd6 AND LAN_SM_FSM_FFd7)
OR (NOT DS1 AND LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd4)
OR (NOT DS0 AND LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd4));
LAN_WRH <= ((NOT RESET AND LAN_WR_RST)
OR (FCS AND LAN_WR_RST)
OR (RESET AND NOT FCS AND LAN_WRH_S));
FDCPE_LAN_WRH_S: FDCPE port map (LAN_WRH_S,LAN_WRH_S_D,CLK_EXT,NOT RESET,'0');
LAN_WRH_S_D <= ((NOT LDS AND NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5)
OR (NOT DS0 AND NOT LAN_SM_FSM_FFd3 AND LAN_SM_FSM_FFd4));
LAN_WRL <= ((NOT RESET AND LAN_WR_RST)
OR (FCS AND LAN_WR_RST)
OR (RESET AND NOT FCS AND LAN_WRL_S));
FDCPE_LAN_WRL_S: FDCPE port map (LAN_WRL_S,LAN_WRL_S_D,CLK_EXT,NOT RESET,'0');
LAN_WRL_S_D <= ((NOT UDS AND NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5)
OR (NOT DS1 AND NOT LAN_SM_FSM_FFd3 AND LAN_SM_FSM_FFd4));
FDCPE_LAN_WR_RST: FDCPE port map (LAN_WR_RST,LAN_WR_RST_D,CLK_EXT,RESET,'0');
LAN_WR_RST_D <= ((NOT LAN_D_INIT(8) AND LAN_RST_SM_FSM_FFd3)
OR (LAN_RST_SM_FSM_FFd3 AND NOT LAN_RST_SM_FSM_FFd2));
MTACK_I <= '0';
MTACK <= MTACK_I when MTACK_OE = '1' else 'Z';
MTACK_OE <= '0';
OVR_I <= '0';
OVR <= OVR_I when OVR_OE = '1' else 'Z';
OVR_OE <= (NOT FCS AND LAN_ACCESS);
OWN_I <= '0';
OWN <= OWN_I when OWN_OE = '1' else 'Z';
OWN_OE <= '0';
ROM_B(0) <= '0';
ROM_B(1) <= '0';
ROM_OE <= NOT ((NOT AS AND NOT ROM_OE_S AND NOT AUTOBOOT_OFF));
FDCPE_ROM_OE_S: FDCPE port map (ROM_OE_S,ROM_OE_S_D,SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET);
ROM_OE_S_D <= (RW AND NOT AS AND IDE_ACCESS AND IDE_ENABLE);
FTCPE_SHUT_UP_Z20: FTCPE port map (SHUT_UP_Z2(0),SHUT_UP_Z2_T(0),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET);
SHUT_UP_Z2_T(0) <= ((NOT RW AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(0) AND NOT UDS AND NOT A(2) AND
NOT A(5) AND NOT A(4) AND AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND
SHUT_UP_Z2(0) AND A(6) AND A(3))
OR (NOT RW AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(0) AND NOT LDS AND NOT A(2) AND
NOT A(5) AND NOT A(4) AND AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND
SHUT_UP_Z2(0) AND A(6) AND A(3)));
FTCPE_SHUT_UP_Z21: FTCPE port map (SHUT_UP_Z2(1),SHUT_UP_Z2_T(1),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET);
SHUT_UP_Z2_T(1) <= ((NOT RW AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND
NOT AUTO_CONFIG_Z2_DONE(1) AND NOT LDS AND NOT A(2) AND NOT A(5) AND NOT A(4) AND
AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND SHUT_UP_Z2(1) AND A(6) AND A(3))
OR (NOT RW AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND
NOT AUTO_CONFIG_Z2_DONE(1) AND NOT UDS AND NOT A(2) AND NOT A(5) AND NOT A(4) AND
AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND SHUT_UP_Z2(1) AND A(6) AND A(3)));
FTCPE_SHUT_UP_Z22: FTCPE port map (SHUT_UP_Z2(2),SHUT_UP_Z2_T(2),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET);
SHUT_UP_Z2_T(2) <= ((NOT RW AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND
AUTO_CONFIG_Z2_DONE(1) AND NOT UDS AND NOT AUTO_CONFIG_Z2_DONE(2) AND NOT A(2) AND NOT A(5) AND
NOT A(4) AND AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND SHUT_UP_Z2(2) AND
A(6) AND A(3))
OR (NOT RW AND NOT AS AND AUTO_CONFIG_Z2_DONE(0) AND
AUTO_CONFIG_Z2_DONE(1) AND NOT LDS AND NOT AUTO_CONFIG_Z2_DONE(2) AND NOT A(2) AND NOT A(5) AND
NOT A(4) AND AUTOCONFIG_Z2_ACCESS AND NOT A(1) AND SHUT_UP_Z2(2) AND
A(6) AND A(3)));
SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF <= C3
XOR
SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF <= C1;
SLAVE <= ((FCS AND AS)
OR (AS AND NOT LAN_ACCESS)
OR (FCS AND NOT AUTOCONFIG_Z2_ACCESS AND NOT IDE_ACCESS AND
CP_CS_BUFR)
OR (NOT LAN_ACCESS AND NOT AUTOCONFIG_Z2_ACCESS AND NOT IDE_ACCESS AND
CP_CS_BUFR));
FDCPE_Z3_ADR2: FDCPE port map (Z3_ADR(2),A(4),NOT FCS,'0',NOT RESET);
FDCPE_Z3_ADR3: FDCPE port map (Z3_ADR(3),A(5),NOT FCS,'0',NOT RESET);
FDCPE_Z3_ADR4: FDCPE port map (Z3_ADR(4),A(6),NOT FCS,'0',NOT RESET);
FDCPE_Z3_ADR5: FDCPE port map (Z3_ADR(5),A(7),NOT FCS,'0',NOT RESET);
FDCPE_Z3_ADR6: FDCPE port map (Z3_ADR(6),A(8).PIN,NOT FCS,'0',NOT RESET);
FDCPE_Z3_ADR7: FDCPE port map (Z3_ADR(7),A(9).PIN,NOT FCS,'0',NOT RESET);
FDCPE_Z3_ADR8: FDCPE port map (Z3_ADR(8),A(10).PIN,NOT FCS,'0',NOT RESET);
FDCPE_Z3_ADR9: FDCPE port map (Z3_ADR(9),A(11).PIN,NOT FCS,'0',NOT RESET);
FDCPE_Z3_ADR10: FDCPE port map (Z3_ADR(10),A(12).PIN,NOT FCS,'0',NOT RESET);
FDCPE_Z3_ADR11: FDCPE port map (Z3_ADR(11),A(13).PIN,NOT FCS,'0',NOT RESET);
FDCPE_Z3_ADR12: FDCPE port map (Z3_ADR(12),A(14).PIN,NOT FCS,'0',NOT RESET);
FDCPE_Z3_ADR13: FDCPE port map (Z3_ADR(13),A(15).PIN,NOT FCS,'0',NOT RESET);
FDCPE_Z3_ADR_0: FDCPE port map (Z3_ADR_0,A(2),NOT FCS,'0',NOT RESET);
FDCPE_Z3_ADR_1: FDCPE port map (Z3_ADR_1,A(3),NOT FCS,'0',NOT RESET);
FDCPE_Z3_A_LOW: FDCPE port map (Z3_A_LOW,Z3_A_LOW_D,CLK_EXT,NOT RESET,'0');
Z3_A_LOW_D <= ((NOT DS1 AND LAN_SM_FSM_FFd8 AND LAN_SM_FSM_FFd1)
OR (NOT DS1 AND LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd4)
OR (NOT DS0 AND LAN_SM_FSM_FFd8 AND LAN_SM_FSM_FFd1)
OR (NOT DS0 AND LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd4)
OR (UDS AND LDS AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd8)
OR (LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3)
OR (NOT LAN_SM_FSM_FFd3 AND LAN_SM_FSM_FFd4)
OR (LAN_SM_FSM_FFd6 AND NOT LAN_SM_FSM_FFd7)
OR (LAN_SM_FSM_FFd6 AND NOT LAN_SM_FSM_FFd5));
FTCPE_Z3_DATA16: FTCPE port map (Z3_DATA(16),Z3_DATA_T(16),CLK_EXT,'0',NOT RESET);
Z3_DATA_T(16) <= ((LAN_SM_FSM_FFd8 AND LAN_SM_FSM_FFd3 AND NOT DQ_SWAP AND
LAN_SM_FSM_FFd6 AND LAN_SM_FSM_FFd1 AND LAN_SM_FSM_FFd7 AND
LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5 AND Z3_DATA(16) AND NOT DQ(0).PIN)
OR (LAN_SM_FSM_FFd8 AND LAN_SM_FSM_FFd3 AND
LAN_SM_FSM_FFd6 AND LAN_SM_FSM_FFd1 AND LAN_SM_FSM_FFd7 AND
LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5 AND Z3_DATA(16) AND NOT DQ(0).PIN AND
NOT DQ(8).PIN)
OR (LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd8 AND
LAN_SM_FSM_FFd3 AND DQ_SWAP AND LAN_SM_FSM_FFd6 AND LAN_SM_FSM_FFd1 AND
LAN_SM_FSM_FFd7 AND LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5 AND Z3_DATA(16) AND
NOT DQ(8).PIN)
OR (NOT LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd3 AND NOT Z3_DATA(16) AND
DQ(0).PIN)
OR (LAN_SM_FSM_FFd8 AND DQ_SWAP AND LAN_SM_FSM_FFd1 AND
NOT Z3_DATA(16) AND DQ(8).PIN)
OR (LAN_SM_FSM_FFd8 AND NOT DQ_SWAP AND LAN_SM_FSM_FFd1 AND
NOT Z3_DATA(16) AND DQ(0).PIN)
OR (NOT LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd8 AND
LAN_SM_FSM_FFd3 AND LAN_SM_FSM_FFd6 AND NOT LAN_SM_FSM_FFd1 AND
LAN_SM_FSM_FFd7 AND LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5 AND Z3_DATA(16) AND
NOT DQ(0).PIN));
FTCPE_Z3_DATA17: FTCPE port map (Z3_DATA(17),Z3_DATA_T(17),CLK_EXT,'0',NOT RESET);
Z3_DATA_T(17) <= ((NOT LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd8 AND
LAN_SM_FSM_FFd3 AND LAN_SM_FSM_FFd6 AND NOT LAN_SM_FSM_FFd1 AND
LAN_SM_FSM_FFd7 AND LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5 AND Z3_DATA(17) AND
NOT DQ(1).PIN)
OR (LAN_SM_FSM_FFd8 AND LAN_SM_FSM_FFd3 AND NOT DQ_SWAP AND
LAN_SM_FSM_FFd6 AND LAN_SM_FSM_FFd1 AND LAN_SM_FSM_FFd7 AND
LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5 AND Z3_DATA(17) AND NOT DQ(1).PIN)
OR (LAN_SM_FSM_FFd8 AND LAN_SM_FSM_FFd3 AND
LAN_SM_FSM_FFd6 AND LAN_SM_FSM_FFd1 AND LAN_SM_FSM_FFd7 AND
LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5 AND Z3_DATA(17) AND NOT DQ(1).PIN AND
NOT DQ(9).PIN)
OR (LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd8 AND
LAN_SM_FSM_FFd3 AND DQ_SWAP AND LAN_SM_FSM_FFd6 AND LAN_SM_FSM_FFd1 AND
LAN_SM_FSM_FFd7 AND LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5 AND Z3_DATA(17) AND
NOT DQ(9).PIN)
OR (NOT LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd3 AND NOT Z3_DATA(17) AND
DQ(1).PIN)
OR (LAN_SM_FSM_FFd8 AND DQ_SWAP AND LAN_SM_FSM_FFd1 AND
NOT Z3_DATA(17) AND DQ(9).PIN)
OR (LAN_SM_FSM_FFd8 AND NOT DQ_SWAP AND LAN_SM_FSM_FFd1 AND
NOT Z3_DATA(17) AND DQ(1).PIN));
FTCPE_Z3_DATA18: FTCPE port map (Z3_DATA(18),Z3_DATA_T(18),CLK_EXT,'0',NOT RESET);
Z3_DATA_T(18) <= ((LAN_SM_FSM_FFd8 AND NOT DQ_SWAP AND LAN_SM_FSM_FFd1 AND
NOT Z3_DATA(18) AND DQ(2).PIN)
OR (NOT LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd8 AND
LAN_SM_FSM_FFd3 AND LAN_SM_FSM_FFd6 AND NOT LAN_SM_FSM_FFd1 AND
LAN_SM_FSM_FFd7 AND LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5 AND Z3_DATA(18) AND
NOT DQ(2).PIN)
OR (LAN_SM_FSM_FFd8 AND LAN_SM_FSM_FFd3 AND NOT DQ_SWAP AND
LAN_SM_FSM_FFd6 AND LAN_SM_FSM_FFd1 AND LAN_SM_FSM_FFd7 AND
LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5 AND Z3_DATA(18) AND NOT DQ(2).PIN)
OR (LAN_SM_FSM_FFd8 AND LAN_SM_FSM_FFd3 AND
LAN_SM_FSM_FFd6 AND LAN_SM_FSM_FFd1 AND LAN_SM_FSM_FFd7 AND
LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5 AND Z3_DATA(18) AND NOT DQ(10).PIN AND
NOT DQ(2).PIN)
OR (LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd8 AND
LAN_SM_FSM_FFd3 AND DQ_SWAP AND LAN_SM_FSM_FFd6 AND LAN_SM_FSM_FFd1 AND
LAN_SM_FSM_FFd7 AND LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5 AND Z3_DATA(18) AND
NOT DQ(10).PIN)
OR (NOT LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd3 AND NOT Z3_DATA(18) AND
DQ(2).PIN)
OR (LAN_SM_FSM_FFd8 AND DQ_SWAP AND LAN_SM_FSM_FFd1 AND
NOT Z3_DATA(18) AND DQ(10).PIN));
FTCPE_Z3_DATA19: FTCPE port map (Z3_DATA(19),Z3_DATA_T(19),CLK_EXT,'0',NOT RESET);
Z3_DATA_T(19) <= ((LAN_SM_FSM_FFd8 AND LAN_SM_FSM_FFd3 AND NOT DQ_SWAP AND
LAN_SM_FSM_FFd6 AND LAN_SM_FSM_FFd1 AND LAN_SM_FSM_FFd7 AND
LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5 AND Z3_DATA(19) AND NOT DQ(3).PIN)
OR (LAN_SM_FSM_FFd8 AND LAN_SM_FSM_FFd3 AND
LAN_SM_FSM_FFd6 AND LAN_SM_FSM_FFd1 AND LAN_SM_FSM_FFd7 AND
LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5 AND Z3_DATA(19) AND NOT DQ(11).PIN AND
NOT DQ(3).PIN)
OR (LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd8 AND
LAN_SM_FSM_FFd3 AND DQ_SWAP AND LAN_SM_FSM_FFd6 AND LAN_SM_FSM_FFd1 AND
LAN_SM_FSM_FFd7 AND LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5 AND Z3_DATA(19) AND
NOT DQ(11).PIN)
OR (NOT LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd3 AND NOT Z3_DATA(19) AND
DQ(3).PIN)
OR (LAN_SM_FSM_FFd8 AND DQ_SWAP AND LAN_SM_FSM_FFd1 AND
NOT Z3_DATA(19) AND DQ(11).PIN)
OR (LAN_SM_FSM_FFd8 AND NOT DQ_SWAP AND LAN_SM_FSM_FFd1 AND
NOT Z3_DATA(19) AND DQ(3).PIN)
OR (NOT LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd8 AND
LAN_SM_FSM_FFd3 AND LAN_SM_FSM_FFd6 AND NOT LAN_SM_FSM_FFd1 AND
LAN_SM_FSM_FFd7 AND LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5 AND Z3_DATA(19) AND
NOT DQ(3).PIN));
FTCPE_Z3_DATA20: FTCPE port map (Z3_DATA(20),Z3_DATA_T(20),CLK_EXT,'0',NOT RESET);
Z3_DATA_T(20) <= ((NOT LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd8 AND
LAN_SM_FSM_FFd3 AND LAN_SM_FSM_FFd6 AND NOT LAN_SM_FSM_FFd1 AND
LAN_SM_FSM_FFd7 AND LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5 AND Z3_DATA(20) AND
NOT DQ(4).PIN)
OR (LAN_SM_FSM_FFd8 AND LAN_SM_FSM_FFd3 AND NOT DQ_SWAP AND
LAN_SM_FSM_FFd6 AND LAN_SM_FSM_FFd1 AND LAN_SM_FSM_FFd7 AND
LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5 AND Z3_DATA(20) AND NOT DQ(4).PIN)
OR (LAN_SM_FSM_FFd8 AND LAN_SM_FSM_FFd3 AND
LAN_SM_FSM_FFd6 AND LAN_SM_FSM_FFd1 AND LAN_SM_FSM_FFd7 AND
LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5 AND Z3_DATA(20) AND NOT DQ(12).PIN AND
NOT DQ(4).PIN)
OR (LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd8 AND
LAN_SM_FSM_FFd3 AND DQ_SWAP AND LAN_SM_FSM_FFd6 AND LAN_SM_FSM_FFd1 AND
LAN_SM_FSM_FFd7 AND LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5 AND Z3_DATA(20) AND
NOT DQ(12).PIN)
OR (NOT LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd3 AND NOT Z3_DATA(20) AND
DQ(4).PIN)
OR (LAN_SM_FSM_FFd8 AND DQ_SWAP AND LAN_SM_FSM_FFd1 AND
NOT Z3_DATA(20) AND DQ(12).PIN)
OR (LAN_SM_FSM_FFd8 AND NOT DQ_SWAP AND LAN_SM_FSM_FFd1 AND
NOT Z3_DATA(20) AND DQ(4).PIN));
FTCPE_Z3_DATA21: FTCPE port map (Z3_DATA(21),Z3_DATA_T(21),CLK_EXT,'0',NOT RESET);
Z3_DATA_T(21) <= ((LAN_SM_FSM_FFd8 AND LAN_SM_FSM_FFd3 AND NOT DQ_SWAP AND
LAN_SM_FSM_FFd6 AND LAN_SM_FSM_FFd1 AND LAN_SM_FSM_FFd7 AND
LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5 AND Z3_DATA(21) AND NOT DQ(5).PIN)
OR (LAN_SM_FSM_FFd8 AND LAN_SM_FSM_FFd3 AND
LAN_SM_FSM_FFd6 AND LAN_SM_FSM_FFd1 AND LAN_SM_FSM_FFd7 AND
LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5 AND Z3_DATA(21) AND NOT DQ(13).PIN AND
NOT DQ(5).PIN)
OR (LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd8 AND
LAN_SM_FSM_FFd3 AND DQ_SWAP AND LAN_SM_FSM_FFd6 AND LAN_SM_FSM_FFd1 AND
LAN_SM_FSM_FFd7 AND LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5 AND Z3_DATA(21) AND
NOT DQ(13).PIN)
OR (NOT LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd3 AND NOT Z3_DATA(21) AND
DQ(5).PIN)
OR (LAN_SM_FSM_FFd8 AND DQ_SWAP AND LAN_SM_FSM_FFd1 AND
NOT Z3_DATA(21) AND DQ(13).PIN)
OR (LAN_SM_FSM_FFd8 AND NOT DQ_SWAP AND LAN_SM_FSM_FFd1 AND
NOT Z3_DATA(21) AND DQ(5).PIN)
OR (NOT LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd8 AND
LAN_SM_FSM_FFd3 AND LAN_SM_FSM_FFd6 AND NOT LAN_SM_FSM_FFd1 AND
LAN_SM_FSM_FFd7 AND LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5 AND Z3_DATA(21) AND
NOT DQ(5).PIN));
FTCPE_Z3_DATA22: FTCPE port map (Z3_DATA(22),Z3_DATA_T(22),CLK_EXT,'0',NOT RESET);
Z3_DATA_T(22) <= ((NOT LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd8 AND
LAN_SM_FSM_FFd3 AND LAN_SM_FSM_FFd6 AND NOT LAN_SM_FSM_FFd1 AND
LAN_SM_FSM_FFd7 AND LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5 AND Z3_DATA(22) AND
NOT DQ(6).PIN)
OR (LAN_SM_FSM_FFd8 AND LAN_SM_FSM_FFd3 AND NOT DQ_SWAP AND
LAN_SM_FSM_FFd6 AND LAN_SM_FSM_FFd1 AND LAN_SM_FSM_FFd7 AND
LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5 AND Z3_DATA(22) AND NOT DQ(6).PIN)
OR (LAN_SM_FSM_FFd8 AND LAN_SM_FSM_FFd3 AND
LAN_SM_FSM_FFd6 AND LAN_SM_FSM_FFd1 AND LAN_SM_FSM_FFd7 AND
LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5 AND Z3_DATA(22) AND NOT DQ(14).PIN AND
NOT DQ(6).PIN)
OR (LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd8 AND
LAN_SM_FSM_FFd3 AND DQ_SWAP AND LAN_SM_FSM_FFd6 AND LAN_SM_FSM_FFd1 AND
LAN_SM_FSM_FFd7 AND LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5 AND Z3_DATA(22) AND
NOT DQ(14).PIN)
OR (NOT LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd3 AND NOT Z3_DATA(22) AND
DQ(6).PIN)
OR (LAN_SM_FSM_FFd8 AND DQ_SWAP AND LAN_SM_FSM_FFd1 AND
NOT Z3_DATA(22) AND DQ(14).PIN)
OR (LAN_SM_FSM_FFd8 AND NOT DQ_SWAP AND LAN_SM_FSM_FFd1 AND
NOT Z3_DATA(22) AND DQ(6).PIN));
FTCPE_Z3_DATA23: FTCPE port map (Z3_DATA(23),Z3_DATA_T(23),CLK_EXT,'0',NOT RESET);
Z3_DATA_T(23) <= ((Z3_DATA(24).EXP)
OR (NOT LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd3 AND NOT Z3_DATA(23) AND
DQ(7).PIN)
OR (LAN_SM_FSM_FFd8 AND DQ_SWAP AND LAN_SM_FSM_FFd1 AND
NOT Z3_DATA(23) AND DQ(15).PIN)
OR (LAN_SM_FSM_FFd8 AND NOT DQ_SWAP AND LAN_SM_FSM_FFd1 AND
NOT Z3_DATA(23) AND DQ(7).PIN)
OR (NOT LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd8 AND
LAN_SM_FSM_FFd3 AND LAN_SM_FSM_FFd6 AND NOT LAN_SM_FSM_FFd1 AND
LAN_SM_FSM_FFd7 AND LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5 AND Z3_DATA(23) AND
NOT DQ(7).PIN)
OR (LAN_SM_FSM_FFd8 AND LAN_SM_FSM_FFd3 AND NOT DQ_SWAP AND
LAN_SM_FSM_FFd6 AND LAN_SM_FSM_FFd1 AND LAN_SM_FSM_FFd7 AND
LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5 AND Z3_DATA(23) AND NOT DQ(7).PIN));
FTCPE_Z3_DATA24: FTCPE port map (Z3_DATA(24),Z3_DATA_T(24),CLK_EXT,'0',NOT RESET);
Z3_DATA_T(24) <= ((LAN_SM_FSM_FFd8 AND NOT DQ_SWAP AND LAN_SM_FSM_FFd1 AND
NOT Z3_DATA(24) AND DQ(8).PIN)
OR (NOT LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd8 AND
LAN_SM_FSM_FFd3 AND LAN_SM_FSM_FFd6 AND NOT LAN_SM_FSM_FFd1 AND
LAN_SM_FSM_FFd7 AND LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5 AND Z3_DATA(24) AND
NOT DQ(8).PIN)
OR (LAN_SM_FSM_FFd8 AND LAN_SM_FSM_FFd3 AND NOT DQ_SWAP AND
LAN_SM_FSM_FFd6 AND LAN_SM_FSM_FFd1 AND LAN_SM_FSM_FFd7 AND
LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5 AND Z3_DATA(24) AND NOT DQ(8).PIN)
OR (LAN_SM_FSM_FFd8 AND LAN_SM_FSM_FFd3 AND
LAN_SM_FSM_FFd6 AND LAN_SM_FSM_FFd1 AND LAN_SM_FSM_FFd7 AND
LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5 AND Z3_DATA(24) AND NOT DQ(0).PIN AND
NOT DQ(8).PIN)
OR (LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd8 AND
LAN_SM_FSM_FFd3 AND DQ_SWAP AND LAN_SM_FSM_FFd6 AND LAN_SM_FSM_FFd1 AND
LAN_SM_FSM_FFd7 AND LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5 AND Z3_DATA(24) AND
NOT DQ(0).PIN)
OR (NOT LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd3 AND NOT Z3_DATA(24) AND
DQ(8).PIN)
OR (LAN_SM_FSM_FFd8 AND DQ_SWAP AND LAN_SM_FSM_FFd1 AND
NOT Z3_DATA(24) AND DQ(0).PIN));
FTCPE_Z3_DATA25: FTCPE port map (Z3_DATA(25),Z3_DATA_T(25),CLK_EXT,'0',NOT RESET);
Z3_DATA_T(25) <= ((LAN_SM_FSM_FFd8 AND LAN_SM_FSM_FFd3 AND NOT DQ_SWAP AND
LAN_SM_FSM_FFd6 AND LAN_SM_FSM_FFd1 AND LAN_SM_FSM_FFd7 AND
LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5 AND Z3_DATA(25) AND NOT DQ(9).PIN)
OR (LAN_SM_FSM_FFd8 AND LAN_SM_FSM_FFd3 AND
LAN_SM_FSM_FFd6 AND LAN_SM_FSM_FFd1 AND LAN_SM_FSM_FFd7 AND
LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5 AND Z3_DATA(25) AND NOT DQ(1).PIN AND
NOT DQ(9).PIN)
OR (LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd8 AND
LAN_SM_FSM_FFd3 AND DQ_SWAP AND LAN_SM_FSM_FFd6 AND LAN_SM_FSM_FFd1 AND
LAN_SM_FSM_FFd7 AND LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5 AND Z3_DATA(25) AND
NOT DQ(1).PIN)
OR (NOT LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd3 AND NOT Z3_DATA(25) AND
DQ(9).PIN)
OR (LAN_SM_FSM_FFd8 AND DQ_SWAP AND LAN_SM_FSM_FFd1 AND
NOT Z3_DATA(25) AND DQ(1).PIN)
OR (LAN_SM_FSM_FFd8 AND NOT DQ_SWAP AND LAN_SM_FSM_FFd1 AND
NOT Z3_DATA(25) AND DQ(9).PIN)
OR (NOT LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd8 AND
LAN_SM_FSM_FFd3 AND LAN_SM_FSM_FFd6 AND NOT LAN_SM_FSM_FFd1 AND
LAN_SM_FSM_FFd7 AND LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5 AND Z3_DATA(25) AND
NOT DQ(9).PIN));
FTCPE_Z3_DATA26: FTCPE port map (Z3_DATA(26),Z3_DATA_T(26),CLK_EXT,'0',NOT RESET);
Z3_DATA_T(26) <= ((NOT LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd8 AND
LAN_SM_FSM_FFd3 AND LAN_SM_FSM_FFd6 AND NOT LAN_SM_FSM_FFd1 AND
LAN_SM_FSM_FFd7 AND LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5 AND Z3_DATA(26) AND
NOT DQ(10).PIN)
OR (LAN_SM_FSM_FFd8 AND LAN_SM_FSM_FFd3 AND NOT DQ_SWAP AND
LAN_SM_FSM_FFd6 AND LAN_SM_FSM_FFd1 AND LAN_SM_FSM_FFd7 AND
LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5 AND Z3_DATA(26) AND NOT DQ(10).PIN)
OR (LAN_SM_FSM_FFd8 AND LAN_SM_FSM_FFd3 AND
LAN_SM_FSM_FFd6 AND LAN_SM_FSM_FFd1 AND LAN_SM_FSM_FFd7 AND
LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5 AND Z3_DATA(26) AND NOT DQ(10).PIN AND
NOT DQ(2).PIN)
OR (LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd8 AND
LAN_SM_FSM_FFd3 AND DQ_SWAP AND LAN_SM_FSM_FFd6 AND LAN_SM_FSM_FFd1 AND
LAN_SM_FSM_FFd7 AND LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5 AND Z3_DATA(26) AND
NOT DQ(2).PIN)
OR (NOT LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd3 AND NOT Z3_DATA(26) AND
DQ(10).PIN)
OR (LAN_SM_FSM_FFd8 AND DQ_SWAP AND LAN_SM_FSM_FFd1 AND
NOT Z3_DATA(26) AND DQ(2).PIN)
OR (LAN_SM_FSM_FFd8 AND NOT DQ_SWAP AND LAN_SM_FSM_FFd1 AND
NOT Z3_DATA(26) AND DQ(10).PIN));
FTCPE_Z3_DATA27: FTCPE port map (Z3_DATA(27),Z3_DATA_T(27),CLK_EXT,'0',NOT RESET);
Z3_DATA_T(27) <= ((LAN_SM_FSM_FFd8 AND LAN_SM_FSM_FFd3 AND NOT DQ_SWAP AND
LAN_SM_FSM_FFd6 AND LAN_SM_FSM_FFd1 AND LAN_SM_FSM_FFd7 AND
LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5 AND Z3_DATA(27) AND NOT DQ(11).PIN)
OR (LAN_SM_FSM_FFd8 AND LAN_SM_FSM_FFd3 AND
LAN_SM_FSM_FFd6 AND LAN_SM_FSM_FFd1 AND LAN_SM_FSM_FFd7 AND
LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5 AND Z3_DATA(27) AND NOT DQ(11).PIN AND
NOT DQ(3).PIN)
OR (LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd8 AND
LAN_SM_FSM_FFd3 AND DQ_SWAP AND LAN_SM_FSM_FFd6 AND LAN_SM_FSM_FFd1 AND
LAN_SM_FSM_FFd7 AND LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5 AND Z3_DATA(27) AND
NOT DQ(3).PIN)
OR (NOT LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd3 AND NOT Z3_DATA(27) AND
DQ(11).PIN)
OR (LAN_SM_FSM_FFd8 AND DQ_SWAP AND LAN_SM_FSM_FFd1 AND
NOT Z3_DATA(27) AND DQ(3).PIN)
OR (LAN_SM_FSM_FFd8 AND NOT DQ_SWAP AND LAN_SM_FSM_FFd1 AND
NOT Z3_DATA(27) AND DQ(11).PIN)
OR (NOT LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd8 AND
LAN_SM_FSM_FFd3 AND LAN_SM_FSM_FFd6 AND NOT LAN_SM_FSM_FFd1 AND
LAN_SM_FSM_FFd7 AND LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5 AND Z3_DATA(27) AND
NOT DQ(11).PIN));
FTCPE_Z3_DATA28: FTCPE port map (Z3_DATA(28),Z3_DATA_T(28),CLK_EXT,'0',NOT RESET);
Z3_DATA_T(28) <= ((LAN_SM_FSM_FFd8 AND LAN_SM_FSM_FFd3 AND NOT DQ_SWAP AND
LAN_SM_FSM_FFd6 AND LAN_SM_FSM_FFd1 AND LAN_SM_FSM_FFd7 AND
LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5 AND Z3_DATA(28) AND NOT DQ(12).PIN)
OR (LAN_SM_FSM_FFd8 AND LAN_SM_FSM_FFd3 AND
LAN_SM_FSM_FFd6 AND LAN_SM_FSM_FFd1 AND LAN_SM_FSM_FFd7 AND
LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5 AND Z3_DATA(28) AND NOT DQ(12).PIN AND
NOT DQ(4).PIN)
OR (LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd8 AND
LAN_SM_FSM_FFd3 AND DQ_SWAP AND LAN_SM_FSM_FFd6 AND LAN_SM_FSM_FFd1 AND
LAN_SM_FSM_FFd7 AND LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5 AND Z3_DATA(28) AND
NOT DQ(4).PIN)
OR (NOT LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd3 AND NOT Z3_DATA(28) AND
DQ(12).PIN)
OR (LAN_SM_FSM_FFd8 AND DQ_SWAP AND LAN_SM_FSM_FFd1 AND
NOT Z3_DATA(28) AND DQ(4).PIN)
OR (LAN_SM_FSM_FFd8 AND NOT DQ_SWAP AND LAN_SM_FSM_FFd1 AND
NOT Z3_DATA(28) AND DQ(12).PIN)
OR (NOT LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd8 AND
LAN_SM_FSM_FFd3 AND LAN_SM_FSM_FFd6 AND NOT LAN_SM_FSM_FFd1 AND
LAN_SM_FSM_FFd7 AND LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5 AND Z3_DATA(28) AND
NOT DQ(12).PIN));
FTCPE_Z3_DATA29: FTCPE port map (Z3_DATA(29),Z3_DATA_T(29),CLK_EXT,'0',NOT RESET);
Z3_DATA_T(29) <= ((LAN_SM_FSM_FFd8 AND LAN_SM_FSM_FFd3 AND NOT DQ_SWAP AND
LAN_SM_FSM_FFd6 AND LAN_SM_FSM_FFd1 AND LAN_SM_FSM_FFd7 AND
LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5 AND Z3_DATA(29) AND NOT DQ(13).PIN)
OR (LAN_SM_FSM_FFd8 AND LAN_SM_FSM_FFd3 AND
LAN_SM_FSM_FFd6 AND LAN_SM_FSM_FFd1 AND LAN_SM_FSM_FFd7 AND
LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5 AND Z3_DATA(29) AND NOT DQ(13).PIN AND
NOT DQ(5).PIN)
OR (LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd8 AND
LAN_SM_FSM_FFd3 AND DQ_SWAP AND LAN_SM_FSM_FFd6 AND LAN_SM_FSM_FFd1 AND
LAN_SM_FSM_FFd7 AND LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5 AND Z3_DATA(29) AND
NOT DQ(5).PIN)
OR (NOT LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd3 AND NOT Z3_DATA(29) AND
DQ(13).PIN)
OR (LAN_SM_FSM_FFd8 AND DQ_SWAP AND LAN_SM_FSM_FFd1 AND
NOT Z3_DATA(29) AND DQ(5).PIN)
OR (LAN_SM_FSM_FFd8 AND NOT DQ_SWAP AND LAN_SM_FSM_FFd1 AND
NOT Z3_DATA(29) AND DQ(13).PIN)
OR (NOT LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd8 AND
LAN_SM_FSM_FFd3 AND LAN_SM_FSM_FFd6 AND NOT LAN_SM_FSM_FFd1 AND
LAN_SM_FSM_FFd7 AND LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5 AND Z3_DATA(29) AND
NOT DQ(13).PIN));
FTCPE_Z3_DATA30: FTCPE port map (Z3_DATA(30),Z3_DATA_T(30),CLK_EXT,'0',NOT RESET);
Z3_DATA_T(30) <= ((NOT LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd8 AND
LAN_SM_FSM_FFd3 AND LAN_SM_FSM_FFd6 AND NOT LAN_SM_FSM_FFd1 AND
LAN_SM_FSM_FFd7 AND LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5 AND Z3_DATA(30) AND
NOT DQ(14).PIN)
OR (LAN_SM_FSM_FFd8 AND LAN_SM_FSM_FFd3 AND NOT DQ_SWAP AND
LAN_SM_FSM_FFd6 AND LAN_SM_FSM_FFd1 AND LAN_SM_FSM_FFd7 AND
LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5 AND Z3_DATA(30) AND NOT DQ(14).PIN)
OR (LAN_SM_FSM_FFd8 AND LAN_SM_FSM_FFd3 AND
LAN_SM_FSM_FFd6 AND LAN_SM_FSM_FFd1 AND LAN_SM_FSM_FFd7 AND
LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5 AND Z3_DATA(30) AND NOT DQ(14).PIN AND
NOT DQ(6).PIN)
OR (LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd8 AND
LAN_SM_FSM_FFd3 AND DQ_SWAP AND LAN_SM_FSM_FFd6 AND LAN_SM_FSM_FFd1 AND
LAN_SM_FSM_FFd7 AND LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5 AND Z3_DATA(30) AND
NOT DQ(6).PIN)
OR (NOT LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd3 AND NOT Z3_DATA(30) AND
DQ(14).PIN)
OR (LAN_SM_FSM_FFd8 AND DQ_SWAP AND LAN_SM_FSM_FFd1 AND
NOT Z3_DATA(30) AND DQ(6).PIN)
OR (LAN_SM_FSM_FFd8 AND NOT DQ_SWAP AND LAN_SM_FSM_FFd1 AND
NOT Z3_DATA(30) AND DQ(14).PIN));
FTCPE_Z3_DATA31: FTCPE port map (Z3_DATA(31),Z3_DATA_T(31),CLK_EXT,'0',NOT RESET);
Z3_DATA_T(31) <= ((LAN_SM_FSM_FFd8 AND DQ_SWAP AND LAN_SM_FSM_FFd1 AND
NOT Z3_DATA(31) AND DQ(7).PIN)
OR (NOT LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd8 AND
LAN_SM_FSM_FFd3 AND LAN_SM_FSM_FFd6 AND NOT LAN_SM_FSM_FFd1 AND
LAN_SM_FSM_FFd7 AND LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5 AND Z3_DATA(31) AND
NOT DQ(15).PIN)
OR (LAN_SM_FSM_FFd8 AND LAN_SM_FSM_FFd3 AND NOT DQ_SWAP AND
LAN_SM_FSM_FFd6 AND LAN_SM_FSM_FFd1 AND LAN_SM_FSM_FFd7 AND
LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5 AND Z3_DATA(31) AND NOT DQ(15).PIN)
OR (LAN_SM_FSM_FFd8 AND LAN_SM_FSM_FFd3 AND
LAN_SM_FSM_FFd6 AND LAN_SM_FSM_FFd1 AND LAN_SM_FSM_FFd7 AND
LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5 AND Z3_DATA(31) AND NOT DQ(15).PIN AND
NOT DQ(7).PIN)
OR (LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd8 AND
LAN_SM_FSM_FFd3 AND DQ_SWAP AND LAN_SM_FSM_FFd6 AND LAN_SM_FSM_FFd1 AND
LAN_SM_FSM_FFd7 AND LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd5 AND Z3_DATA(31) AND
NOT DQ(7).PIN)
OR (NOT LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd3 AND NOT Z3_DATA(31) AND
DQ(15).PIN)
OR (LAN_SM_FSM_FFd8 AND NOT DQ_SWAP AND LAN_SM_FSM_FFd1 AND
NOT Z3_DATA(31) AND DQ(15).PIN));
Register Legend:
FDCPE (Q,D,C,CLR,PRE,CE);
FTCPE (Q,D,C,CLR,PRE,CE);
LDCP (Q,D,G,CLR,PRE);
**************************** Compiler Options ****************************
Following is a list of all global compiler options used by the fitter run.
Device(s) Specified : xc95288xl-10-TQ144
Optimization Method : SPEED
Multi-Level Logic Optimization : ON
Ignore Timing Specifications : OFF
Default Register Power Up Value : LOW
Keep User Location Constraints : ON
What-You-See-Is-What-You-Get : OFF
Exhaustive Fitting : OFF
Keep Unused Inputs : OFF
Slew Rate : FAST
Power Mode : STD
Ground on Unused IOs : OFF
Set I/O Pin Termination : FLOAT
Global Clock Optimization : ON
Global Set/Reset Optimization : ON
Global Ouput Enable Optimization : ON
Input Limit : 40
Pterm Limit : 15
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