2499 lines
143 KiB
Plaintext
2499 lines
143 KiB
Plaintext
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cpldfit: version P.20131013 Xilinx Inc.
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Fitter Report
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Design Name: LAN_IDE_CP Date: 12-14-2018, 1:22AM
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Device Used: XC95288XL-10-TQ144
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Fitting Status: Successful
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************************* Mapped Resource Summary **************************
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Macrocells Product Terms Function Block Registers Pins
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Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot
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193/288 ( 67%) 589 /1440 ( 41%) 511/864 ( 59%) 98 /288 ( 34%) 109/117 ( 93%)
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** Function Block Resources **
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Function Mcells FB Inps Pterms IO
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Block Used/Tot Used/Tot Used/Tot Used/Tot
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FB1 14/18 34/54 17/90 8/ 8*
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FB2 18/18* 23/54 39/90 10/10*
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FB3 3/18 34/54 33/90 3/ 5
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FB4 18/18* 29/54 43/90 6/ 6*
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FB5 16/18 35/54 38/90 7/ 8
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FB6 15/18 34/54 29/90 8/ 8*
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FB7 18/18* 33/54 50/90 4/ 4*
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FB8 9/18 35/54 35/90 5/ 5*
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FB9 6/18 35/54 39/90 8/ 9
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FB10 18/18* 36/54 47/90 10/10*
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FB11 18/18* 35/54 66/90 7/ 7*
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FB12 10/18 35/54 31/90 6/ 6*
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FB13 11/18 35/54 41/90 6/ 6*
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FB14 4/18 6/54 5/90 5/ 8
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FB15 9/18 35/54 41/90 8/ 9
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FB16 6/18 37/54 35/90 8/ 8*
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----- ----- ----- -----
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193/288 511/864 589/1440 109/117
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* - Resource is exhausted
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** Global Control Resources **
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Signal 'CLK_EXT' mapped onto global clock net GCK1.
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Global output enable net(s) unused.
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Global set/reset net(s) unused.
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** Pin Resources **
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Signal Type Required Mapped | Pin Type Used Total
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------------------------------------|------------------------------------
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Input : 18 18 | I/O : 102 109
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Output : 42 42 | GCK/IO : 2 3
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Bidirectional : 48 48 | GTS/IO : 4 4
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GCK : 1 1 | GSR/IO : 1 1
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GTS : 0 0 |
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GSR : 0 0 |
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---- ----
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Total 109 109
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** Power Data **
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There are 193 macrocells in high performance mode (MCHP).
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There are 0 macrocells in low power mode (MCLP).
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End of Mapped Resource Summary
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************************** Errors and Warnings ***************************
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WARNING:Cpld - Unable to retrieve the path to the iSE Project Repository. Will
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use the default filename of 'LAN_IDE_CP.ise'.
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INFO:Cpld - Inferring BUFG constraint for signal 'CLK_EXT' based upon the LOC
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constraint 'P30'. It is recommended that you declare this BUFG explicitedly
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in your design. Note that for certain device families the output of a BUFG
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constraint can not drive a gated clock, and the BUFG constraint will be
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ignored.
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WARNING:Cpld:1007 - Removing unused input(s) 'A<1>'. The input(s) are unused
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after optimization. Please verify functionality via simulation.
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WARNING:Cpld:1007 - Removing unused input(s) 'AS'. The input(s) are unused
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after optimization. Please verify functionality via simulation.
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WARNING:Cpld:1007 - Removing unused input(s) 'C1'. The input(s) are unused
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after optimization. Please verify functionality via simulation.
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WARNING:Cpld:1007 - Removing unused input(s) 'C3'. The input(s) are unused
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after optimization. Please verify functionality via simulation.
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WARNING:Cpld:1007 - Removing unused input(s) 'CP_IRQ'. The input(s) are unused
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after optimization. Please verify functionality via simulation.
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WARNING:Cpld:1007 - Removing unused input(s) 'IDE_WAIT'. The input(s) are
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unused after optimization. Please verify functionality via simulation.
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WARNING:Cpld:1007 - Removing unused input(s) 'MTCR'. The input(s) are unused
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after optimization. Please verify functionality via simulation.
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************************* Summary of Mapped Logic ************************
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** 90 Outputs **
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Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init
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Name Pts Inps No. Type Use Mode Rate State
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D<5> 2 5 FB1_5 20 I/O I/O STD FAST
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D<4> 2 5 FB1_6 21 I/O I/O STD FAST
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IDE_CS<0> 0 0 FB1_8 22 I/O O STD FAST
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IDE_CS<1> 0 0 FB1_10 23 I/O O STD FAST
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IDE_A<0> 0 0 FB1_12 24 I/O O STD FAST
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IDE_A<2> 0 0 FB1_14 25 I/O O STD FAST
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IDE_A<1> 0 0 FB1_15 26 I/O O STD FAST
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IDE_R 0 0 FB1_17 27 I/O O STD FAST
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A_LAN<4> 1 2 FB2_2 9 I/O O STD FAST
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A_LAN<7> 1 2 FB2_3 10 I/O O STD FAST
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A_LAN<6> 2 3 FB2_5 11 I/O O STD FAST
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LAN_CFG<1> 0 0 FB2_6 12 I/O O STD FAST
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LAN_CFG<3> 0 0 FB2_8 13 I/O O STD FAST
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D<6> 2 5 FB2_10 14 I/O I/O STD FAST
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D<3> 2 5 FB2_12 15 I/O I/O STD FAST
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D<7> 2 5 FB2_14 16 I/O I/O STD FAST
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D<1> 2 5 FB2_15 17 I/O I/O STD FAST
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D<8> 3 6 FB2_17 19 I/O I/O STD FAST
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IDE_W 0 0 FB3_2 28 I/O O STD FAST
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INT_OUT 1 2 FB3_14 32 GCK/I/O O STD FAST
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D<0> 2 5 FB4_2 2 GTS/I/O I/O STD FAST
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A_LAN<1> 1 2 FB4_5 3 GTS/I/O O STD FAST
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A_LAN<0> 1 2 FB4_6 4 I/O O STD FAST
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A_LAN<3> 2 3 FB4_8 5 GTS/I/O O STD FAST
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A_LAN<2> 1 2 FB4_12 6 GTS/I/O O STD FAST
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A_LAN<5> 1 2 FB4_14 7 I/O O STD FAST
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CP_CS 0 0 FB5_2 34 I/O O STD FAST
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ROM_OE 0 0 FB5_5 35 I/O O STD FAST
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D<2> 2 5 FB5_10 39 I/O I/O STD FAST
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D<9> 3 6 FB5_12 40 I/O I/O STD FAST
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D<10> 3 6 FB5_14 41 I/O I/O STD FAST
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D<11> 3 6 FB5_15 43 I/O I/O STD FAST
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D<12> 3 6 FB5_17 44 I/O I/O STD FAST
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LAN_CFG<2> 0 0 FB6_2 135 I/O O STD FAST
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A_LAN<12> 1 2 FB6_3 136 I/O O STD FAST
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A_LAN<13> 1 2 FB6_5 137 I/O O STD FAST
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A_LAN<10> 1 2 FB6_6 138 I/O O STD FAST
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A_LAN<11> 1 2 FB6_8 139 I/O O STD FAST
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A_LAN<8> 1 2 FB6_10 140 I/O O STD FAST
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A_LAN<9> 1 2 FB6_14 142 I/O O STD FAST
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Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init
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Name Pts Inps No. Type Use Mode Rate State
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D<13> 3 6 FB7_3 45 I/O I/O STD FAST
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D<14> 3 6 FB7_5 46 I/O I/O STD FAST
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D<15> 3 6 FB7_12 48 I/O I/O STD FAST
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DQ<12> 3 10 FB8_2 130 I/O I/O STD FAST
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DQ<14> 3 10 FB8_3 131 I/O I/O STD FAST
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LAN_WRH 2 3 FB8_5 132 I/O O STD FAST
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LAN_CS 2 3 FB8_8 133 I/O O STD FAST
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LAN_RD 1 2 FB8_10 134 I/O O STD FAST
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A<8> 7 17 FB9_11 56 I/O I/O STD FAST RESET
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A<9> 7 17 FB9_14 58 I/O I/O STD FAST RESET
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A<10> 7 17 FB9_17 59 I/O I/O STD FAST RESET
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DQ<1> 4 11 FB10_2 117 I/O I/O STD FAST
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DQ<0> 3 10 FB10_3 118 I/O I/O STD FAST
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DQ<3> 3 10 FB10_5 119 I/O I/O STD FAST
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DQ<2> 3 10 FB10_6 120 I/O I/O STD FAST
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DQ<5> 3 10 FB10_8 121 I/O I/O STD FAST
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DQ<4> 4 11 FB10_10 124 I/O I/O STD FAST
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DQ<7> 3 10 FB10_11 125 I/O I/O STD FAST
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DQ<6> 3 10 FB10_12 126 I/O I/O STD FAST
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DQ<8> 3 10 FB10_14 128 I/O I/O STD FAST
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DQ<10> 4 11 FB10_17 129 I/O I/O STD FAST
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A<11> 7 17 FB11_3 60 I/O I/O STD FAST RESET
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A<12> 7 17 FB11_5 61 I/O I/O STD FAST RESET
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A<13> 7 17 FB11_10 64 I/O I/O STD FAST RESET
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A<14> 7 17 FB11_11 66 I/O I/O STD FAST RESET
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ROM_B<0> 0 0 FB11_12 68 I/O O STD FAST
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ROM_B<1> 0 0 FB11_14 69 I/O O STD FAST
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CP_WE 0 0 FB11_17 70 I/O O STD FAST
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LAN_CFG<4> 0 0 FB12_2 110 I/O O STD FAST
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DQ<15> 3 10 FB12_5 112 I/O I/O STD FAST
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DQ<13> 3 10 FB12_8 113 I/O I/O STD FAST
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DQ<11> 4 11 FB12_10 115 I/O I/O STD FAST
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DQ<9> 4 11 FB12_12 116 I/O I/O STD FAST
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CP_RD 0 0 FB13_2 71 I/O O STD FAST
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A<15> 7 17 FB13_8 74 I/O I/O STD FAST RESET
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LAN_WRL 2 3 FB13_14 76 I/O O STD FAST
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OVR 0 0 FB14_3 100 I/O O STD FAST
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CFOUT 3 4 FB14_11 105 I/O O STD FAST SET
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SLAVE 2 3 FB14_14 106 I/O O STD FAST
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OWN 0 0 FB14_15 107 I/O O STD FAST
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Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init
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Name Pts Inps No. Type Use Mode Rate State
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DTACK 1 1 FB15_12 85 I/O O STD FAST
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A<23> 7 17 FB15_14 86 I/O I/O STD FAST RESET
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A<22> 7 17 FB15_15 87 I/O I/O STD FAST RESET
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A<21> 7 17 FB15_17 88 I/O I/O STD FAST RESET
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A<20> 7 17 FB16_2 91 I/O I/O STD FAST RESET
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A<19> 7 17 FB16_3 92 I/O I/O STD FAST RESET
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A<18> 7 17 FB16_6 94 I/O I/O STD FAST RESET
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A<17> 7 17 FB16_8 95 I/O I/O STD FAST RESET
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MTACK 0 0 FB16_10 96 I/O O STD FAST
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A<16> 7 17 FB16_11 97 I/O I/O STD FAST RESET
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** 103 Buried Nodes **
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Signal Total Total Loc Pwr Reg Init
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Name Pts Inps Mode State
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BUF_autoconfig 1 19 FB1_7 STD
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$OpTx$FX_DC$25 1 2 FB1_9 STD
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N0$BUF7/N0$BUF7_TRST 2 3 FB1_11 STD
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Z3_ADR_1 3 3 FB1_13 STD RESET
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Z3_ADR_0 3 3 FB1_16 STD RESET
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Z3_ADR<8> 3 3 FB1_18 STD RESET
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$OpTx$FX_DC$42 1 11 FB2_1 STD
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SHUT_UP 2 13 FB2_4 STD RESET
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AUTO_CONFIG_DONE_CYCLE 2 12 FB2_7 STD RESET
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Dout1<2> 3 10 FB2_9 STD SET
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Dout1<6> 4 11 FB2_11 STD SET
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Dout1<5> 4 11 FB2_13 STD SET
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Dout1<4> 4 11 FB2_16 STD SET
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Dout1<1> 4 10 FB2_18 STD SET
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Mcompar_lan_adr_sw_cmp_eq0001_AEB_or0000/Mcompar_lan_adr_sw_cmp_eq0001_AEB_or0000_D2 32 32 FB3_17 STD
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BUF_LAN_D_INIT<1>__$INT 2 3 FB4_1 STD
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LAN_WR_RST 3 4 FB4_3 STD RESET
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LAN_RST_SM_FSM_FFd3 3 4 FB4_4 STD RESET
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LAN_RST_SM_FSM_FFd2 3 4 FB4_7 STD RESET
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LAN_RST_SM_FSM_FFd1 3 4 FB4_9 STD RESET
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LAN_CS_RST 3 3 FB4_10 STD RESET
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LAN_BASEADR<4> 3 4 FB4_11 STD RESET
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LAN_BASEADR<3> 3 4 FB4_13 STD RESET
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LAN_BASEADR<2> 3 4 FB4_15 STD RESET
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LAN_BASEADR<13> 3 4 FB4_16 STD RESET
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LAN_BASEADR<12> 3 4 FB4_17 STD RESET
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LAN_BASEADR<11> 3 4 FB4_18 STD RESET
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LAN_IRQ_D0 2 2 FB5_4 STD RESET
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Dout1<7> 2 9 FB5_6 STD SET
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Dout1<3> 2 8 FB5_7 STD SET
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Dout1<0> 2 10 FB5_8 STD SET
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LAN_INT_ENABLE 3 4 FB5_9 STD RESET
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LAN_BASEADR<15> 3 4 FB5_11 STD RESET
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LAN_BASEADR<14> 3 4 FB5_13 STD RESET
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LAN_BASEADR<10> 3 4 FB5_16 STD RESET
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LAN_IRQ_OUT 4 7 FB5_18 STD RESET
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$OpTx$FX_DC$24 1 2 FB6_9 STD
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$OpTx$FX_DC$23 1 2 FB6_11 STD
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LAN_WRL_S 3 6 FB6_12 STD RESET
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LAN_BASEADR<9> 3 4 FB6_13 STD RESET
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Signal Total Total Loc Pwr Reg Init
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Name Pts Inps Mode State
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LAN_BASEADR<5> 3 4 FB6_15 STD RESET
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LAN_BASEADR<1> 3 4 FB6_16 STD RESET
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LAN_BASEADR<0> 3 4 FB6_17 STD RESET
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Z3_DATA<25> 6 15 FB6_18 STD RESET
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lan_adr_sw/lan_adr_sw_RSTF 1 2 FB7_1 STD
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LAN_D_INIT<1> 2 2 FB7_2 STD RESET
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LAN_D_INIT<10> 2 2 FB7_4 STD RESET
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LAN_A_INIT<6> 2 2 FB7_6 STD SET
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lan_adr 3 6 FB7_7 STD RESET
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autoconfig 3 3 FB7_8 STD RESET
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Z3_ADR<7> 3 3 FB7_9 STD RESET
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Z3_ADR<6> 3 3 FB7_10 STD RESET
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Z3_ADR<5> 3 3 FB7_11 STD RESET
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Z3_ADR<4> 3 3 FB7_13 STD RESET
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Z3_ADR<3> 3 3 FB7_14 STD RESET
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LAN_BASEADR<8> 3 4 FB7_15 STD RESET
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LAN_BASEADR<7> 3 4 FB7_16 STD RESET
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LAN_BASEADR<6> 3 4 FB7_17 STD RESET
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lan_adr_sw 4 8 FB7_18 STD RESET
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Z3_DATA<27> 6 15 FB8_1 STD RESET
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Z3_DATA<26> 6 15 FB8_16 STD RESET
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Z3_DATA<19> 6 15 FB8_17 STD RESET
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Z3_DATA<18> 6 15 FB8_18 STD RESET
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Z3_DATA<24> 6 15 FB9_15 STD RESET
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Z3_DATA<17> 6 15 FB9_16 STD RESET
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Z3_DATA<16> 6 15 FB9_18 STD RESET
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lan_rdy/lan_rdy_RSTF 1 2 FB10_1 STD
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Z3_DATA<7>/Z3_DATA<7>_TRST 1 4 FB10_4 STD
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$OpTx$FX_DC$66 1 4 FB10_7 STD
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DQ_14_IOBUFE/DQ_14_IOBUFE_TRST 2 5 FB10_9 STD
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DQ_11_IOBUFE/DQ_11_IOBUFE_TRST 2 5 FB10_13 STD
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$OpTx$FX_DC$61 2 6 FB10_15 STD
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$OpTx$FX_DC$49 2 6 FB10_16 STD
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Z3_ADR<10> 3 3 FB10_18 STD RESET
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LAN_SM_FSM_FFd1 2 8 FB11_1 STD RESET
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BUF_LAN_RD_S 2 4 FB11_2 STD
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Z3_ADR<9> 3 3 FB11_4 STD RESET
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Z3_ADR<12> 3 3 FB11_6 STD RESET
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Z3_ADR<11> 3 3 FB11_7 STD RESET
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LAN_SM_FSM_FFd3 3 6 FB11_8 STD RESET
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Signal Total Total Loc Pwr Reg Init
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Name Pts Inps Mode State
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$OpTx$FX_DC$326 3 8 FB11_9 STD
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lan_rdy 4 6 FB11_13 STD RESET
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BUF_LAN_SM_FSM_FFd2 4 7 FB11_15 STD
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Z3_A_LOW 5 9 FB11_16 STD RESET
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BUF_LAN_SM_FSM_FFd4__$INT 6 8 FB11_18 STD
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LAN_D_INIT<9> 1 1 FB12_14 STD RESET
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LAN_A_INIT<3> 1 1 FB12_15 STD SET
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LAN_WRH_S 3 6 FB12_16 STD RESET
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Z3_DATA<31> 6 15 FB12_17 STD RESET
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Z3_DATA<23> 6 15 FB12_18 STD RESET
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LAN_SM_FSM_FFd4 2 2 FB13_1 STD RESET
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LAN_SM_FSM_FFd2 2 2 FB13_11 STD RESET
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LAN_RD_S 2 2 FB13_12 STD RESET
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$OpTx$FX_DC$325 2 4 FB13_13 STD
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Z3_DATA<30> 6 15 FB13_15 STD RESET
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Z3_DATA<28> 6 15 FB13_16 STD RESET
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Z3_DATA<22> 6 15 FB13_17 STD RESET
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Z3_DATA<20> 6 15 FB13_18 STD RESET
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Z3_DATA<29> 6 15 FB15_2 STD RESET
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Z3_ADR<13> 3 3 FB15_3 STD RESET
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Z3_ADR<2> 3 3 FB15_4 STD RESET
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$OpTx$FX_DC$268 1 2 FB15_5 STD
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Z3_DATA<21> 6 15 FB15_18 STD RESET
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** 19 Inputs **
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Signal Loc Pin Pin Pin
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Name No. Type Use
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CLK_EXT FB3_10 30 GCK/I/O GCK
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RESET FB6_15 143 GSR/I/O I
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A<5> FB7_15 49 I/O I
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A<4> FB9_2 50 I/O I
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A<6> FB9_3 51 I/O I
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A<3> FB9_5 52 I/O I
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A<7> FB9_6 53 I/O I
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A<2> FB9_8 54 I/O I
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LAN_INT FB12_3 111 I/O I
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AUTOBOOT_OFF FB13_11 75 I/O I
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FCS FB13_15 77 I/O I
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DS1 FB13_17 78 I/O I
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CFIN FB14_10 104 I/O I
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Z3 FB15_2 79 I/O I
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UDS FB15_8 81 I/O I
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LDS FB15_10 82 I/O I
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RW FB15_11 83 I/O I
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DS0 FB16_5 93 I/O I
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BERR FB16_12 98 I/O I
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Legend:
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Pin No. - ~ - User Assigned
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************************** Function Block Details ************************
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Legend:
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Total Pt - Total product terms used by the macrocell signal
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Imp Pt - Product terms imported from other macrocells
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Exp Pt - Product terms exported to other macrocells
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in direction shown
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Unused Pt - Unused local product terms remaining in macrocell
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Loc - Location where logic was mapped in device
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Pin Type/Use - I - Input GCK - Global Clock
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O - Output GTS - Global Output Enable
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(b) - Buried macrocell GSR - Global Set/Reset
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X - Signal used as input to the macrocell logic.
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Pin No. - ~ - User Assigned
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*********************************** FB1 ***********************************
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Number of function block inputs used/remaining: 34/20
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Number of signals used by logic mapping into function block: 34
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Signal Total Imp Exp Unused Loc Pin Pin Pin
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Name Pt Pt Pt Pt # Type Use
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(unused) 0 0 0 5 FB1_1 (b)
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(unused) 0 0 0 5 FB1_2 (b)
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(unused) 0 0 0 5 FB1_3 (b)
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(unused) 0 0 0 5 FB1_4 (b)
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D<5> 2 0 0 3 FB1_5 20 I/O I/O
|
|
D<4> 2 0 0 3 FB1_6 21 I/O I/O
|
|
BUF_autoconfig 1 0 0 4 FB1_7 (b) (b)
|
|
IDE_CS<0> 0 0 0 5 FB1_8 22 I/O O
|
|
$OpTx$FX_DC$25 1 0 0 4 FB1_9 (b) (b)
|
|
IDE_CS<1> 0 0 0 5 FB1_10 23 I/O O
|
|
N0$BUF7/N0$BUF7_TRST
|
|
2 0 0 3 FB1_11 (b) (b)
|
|
IDE_A<0> 0 0 0 5 FB1_12 24 I/O O
|
|
Z3_ADR_1 3 0 0 2 FB1_13 (b) (b)
|
|
IDE_A<2> 0 0 0 5 FB1_14 25 I/O O
|
|
IDE_A<1> 0 0 0 5 FB1_15 26 I/O O
|
|
Z3_ADR_0 3 0 0 2 FB1_16 (b) (b)
|
|
IDE_R 0 0 0 5 FB1_17 27 I/O O
|
|
Z3_ADR<8> 3 0 0 2 FB1_18 (b) (b)
|
|
|
|
Signals Used by Logic in Function Block
|
|
1: $OpTx$FX_DC$23 13: A<22>.PIN 24: D<9>.PIN
|
|
2: $OpTx$FX_DC$24 14: A<17>.PIN 25: D<8>.PIN
|
|
3: $OpTx$FX_DC$25 15: A<23>.PIN 26: RW
|
|
4: A<2> 16: A<18>.PIN 27: SLAVE
|
|
5: A<3> 17: A<19>.PIN 28: Z3_DATA<20>
|
|
6: CFIN 18: D<15>.PIN 29: Z3_DATA<21>
|
|
7: CFOUT 19: D<14>.PIN 30: Z3_DATA<7>/Z3_DATA<7>_TRST
|
|
8: FCS 20: D<13>.PIN 31: Z3
|
|
9: A<10>.PIN 21: D<12>.PIN 32: autoconfig
|
|
10: A<20>.PIN 22: D<11>.PIN 33: lan_adr_sw/lan_adr_sw_RSTF
|
|
11: A<21>.PIN 23: D<10>.PIN 34: lan_rdy
|
|
12: A<16>.PIN
|
|
|
|
Signal 1 2 3 4 FB
|
|
Name 0----+----0----+----0----+----0----+----0 Inputs
|
|
D<5> ..X......................XX.XX.......... 5
|
|
D<4> ..X......................XXX.X.......... 5
|
|
BUF_autoconfig .....XX..XXXXXXXXXXXXXXXX.....X......... 19
|
|
IDE_CS<0> ........................................ 0
|
|
$OpTx$FX_DC$25 XX...................................... 2
|
|
IDE_CS<1> ........................................ 0
|
|
N0$BUF7/N0$BUF7_TRST
|
|
.......X.......................X.X...... 3
|
|
IDE_A<0> ........................................ 0
|
|
Z3_ADR_1 ....X..X........................X....... 3
|
|
IDE_A<2> ........................................ 0
|
|
IDE_A<1> ........................................ 0
|
|
Z3_ADR_0 ...X...X........................X....... 3
|
|
IDE_R ........................................ 0
|
|
Z3_ADR<8> .......XX.......................X....... 3
|
|
0----+----1----+----2----+----3----+----4
|
|
0 0 0 0
|
|
*********************************** FB2 ***********************************
|
|
Number of function block inputs used/remaining: 23/31
|
|
Number of signals used by logic mapping into function block: 23
|
|
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
|
Name Pt Pt Pt Pt # Type Use
|
|
$OpTx$FX_DC$42 1 0 0 4 FB2_1 (b) (b)
|
|
A_LAN<4> 1 0 0 4 FB2_2 9 I/O O
|
|
A_LAN<7> 1 0 0 4 FB2_3 10 I/O O
|
|
SHUT_UP 2 0 0 3 FB2_4 (b) (b)
|
|
A_LAN<6> 2 0 0 3 FB2_5 11 I/O O
|
|
LAN_CFG<1> 0 0 0 5 FB2_6 12 I/O O
|
|
AUTO_CONFIG_DONE_CYCLE
|
|
2 0 0 3 FB2_7 (b) (b)
|
|
LAN_CFG<3> 0 0 0 5 FB2_8 13 I/O O
|
|
Dout1<2> 3 0 0 2 FB2_9 (b) (b)
|
|
D<6> 2 0 0 3 FB2_10 14 I/O I/O
|
|
Dout1<6> 4 0 0 1 FB2_11 (b) (b)
|
|
D<3> 2 0 0 3 FB2_12 15 I/O I/O
|
|
Dout1<5> 4 0 0 1 FB2_13 (b) (b)
|
|
D<7> 2 0 0 3 FB2_14 16 I/O I/O
|
|
D<1> 2 0 0 3 FB2_15 17 I/O I/O
|
|
Dout1<4> 4 0 0 1 FB2_16 (b) (b)
|
|
D<8> 3 0 0 2 FB2_17 19 I/O I/O
|
|
Dout1<1> 4 0 0 1 FB2_18 (b) (b)
|
|
|
|
Signals Used by Logic in Function Block
|
|
1: $OpTx$FX_DC$25 9: SLAVE 17: Z3_DATA<17>
|
|
2: AUTO_CONFIG_DONE_CYCLE 10: Z3_ADR<2> 18: Z3_DATA<19>
|
|
3: Dout1<0> 11: Z3_ADR<3> 19: Z3_DATA<22>
|
|
4: FCS 12: Z3_ADR<4> 20: Z3_DATA<23>
|
|
5: LAN_A_INIT<6> 13: Z3_ADR<5> 21: Z3_DATA<24>
|
|
6: RESET 14: Z3_ADR<6> 22: Z3_DATA<7>/Z3_DATA<7>_TRST
|
|
7: RW 15: Z3_ADR_0 23: autoconfig
|
|
8: SHUT_UP 16: Z3_ADR_1
|
|
|
|
Signal 1 2 3 4 FB
|
|
Name 0----+----0----+----0----+----0----+----0 Inputs
|
|
$OpTx$FX_DC$42 X..X..X..XXXXXXX......X................. 11
|
|
A_LAN<4> .....X....X............................. 2
|
|
A_LAN<7> .....X.......X.......................... 2
|
|
SHUT_UP X..X.XXX.XXXXXXX......X................. 13
|
|
A_LAN<6> ....XX......X........................... 3
|
|
LAN_CFG<1> ........................................ 0
|
|
AUTO_CONFIG_DONE_CYCLE
|
|
XX.X.XX..XXXXX.X......X................. 12
|
|
LAN_CFG<3> ........................................ 0
|
|
Dout1<2> X..X.X...XXXX.XX......X................. 10
|
|
D<6> X.....X.X.........X..X.................. 5
|
|
Dout1<6> X..X.X...XXXXXXX......X................. 11
|
|
D<3> X.....X.X........X...X.................. 5
|
|
Dout1<5> X..X.X...XXXXXXX......X................. 11
|
|
D<7> X.....X.X..........X.X.................. 5
|
|
D<1> X.....X.X.......X....X.................. 5
|
|
Dout1<4> X..X.X...XXXXXXX......X................. 11
|
|
D<8> X.X...X.X...........XX.................. 6
|
|
Dout1<1> X..X.X...XXXX.XX......X................. 10
|
|
0----+----1----+----2----+----3----+----4
|
|
0 0 0 0
|
|
*********************************** FB3 ***********************************
|
|
Number of function block inputs used/remaining: 34/20
|
|
Number of signals used by logic mapping into function block: 34
|
|
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
|
Name Pt Pt Pt Pt # Type Use
|
|
(unused) 0 0 /\5 0 FB3_1 (b) (b)
|
|
IDE_W 0 0 /\3 2 FB3_2 28 I/O O
|
|
(unused) 0 0 0 5 FB3_3 (b)
|
|
(unused) 0 0 0 5 FB3_4 (b)
|
|
(unused) 0 0 0 5 FB3_5 (b)
|
|
(unused) 0 0 0 5 FB3_6 (b)
|
|
(unused) 0 0 0 5 FB3_7 (b)
|
|
(unused) 0 0 0 5 FB3_8 (b)
|
|
(unused) 0 0 0 5 FB3_9 (b)
|
|
(unused) 0 0 0 5 FB3_10 30 GCK/I/O GCK
|
|
(unused) 0 0 0 5 FB3_11 (b)
|
|
(unused) 0 0 0 5 FB3_12 31 I/O
|
|
(unused) 0 0 0 5 FB3_13 (b)
|
|
INT_OUT 1 0 \/4 0 FB3_14 32 GCK/I/O O
|
|
(unused) 0 0 \/5 0 FB3_15 33 I/O (b)
|
|
(unused) 0 0 \/5 0 FB3_16 (b) (b)
|
|
Mcompar_lan_adr_sw_cmp_eq0001_AEB_or0000/Mcompar_lan_adr_sw_cmp_eq0001_AEB_or0000_D2
|
|
32 27<- 0 0 FB3_17 (b) (b)
|
|
(unused) 0 0 /\5 0 FB3_18 (b) (b)
|
|
|
|
Signals Used by Logic in Function Block
|
|
1: LAN_BASEADR<0> 13: LAN_BASEADR<6> 24: A<23>.PIN
|
|
2: LAN_BASEADR<10> 14: LAN_BASEADR<7> 25: A<18>.PIN
|
|
3: LAN_BASEADR<11> 15: LAN_BASEADR<8> 26: A<19>.PIN
|
|
4: LAN_BASEADR<12> 16: LAN_BASEADR<9> 27: D<15>.PIN
|
|
5: LAN_BASEADR<13> 17: LAN_INT_ENABLE 28: D<14>.PIN
|
|
6: LAN_BASEADR<14> 18: LAN_IRQ_OUT 29: D<13>.PIN
|
|
7: LAN_BASEADR<15> 19: A<20>.PIN 30: D<12>.PIN
|
|
8: LAN_BASEADR<1> 20: A<21>.PIN 31: D<11>.PIN
|
|
9: LAN_BASEADR<2> 21: A<16>.PIN 32: D<10>.PIN
|
|
10: LAN_BASEADR<3> 22: A<22>.PIN 33: D<9>.PIN
|
|
11: LAN_BASEADR<4> 23: A<17>.PIN 34: D<8>.PIN
|
|
12: LAN_BASEADR<5>
|
|
|
|
Signal 1 2 3 4 FB
|
|
Name 0----+----0----+----0----+----0----+----0 Inputs
|
|
IDE_W ........................................ 0
|
|
INT_OUT ................XX...................... 2
|
|
Mcompar_lan_adr_sw_cmp_eq0001_AEB_or0000/Mcompar_lan_adr_sw_cmp_eq0001_AEB_or0000_D2
|
|
XXXXXXXXXXXXXXXX..XXXXXXXXXXXXXXXX...... 32
|
|
0----+----1----+----2----+----3----+----4
|
|
0 0 0 0
|
|
*********************************** FB4 ***********************************
|
|
Number of function block inputs used/remaining: 29/25
|
|
Number of signals used by logic mapping into function block: 29
|
|
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
|
Name Pt Pt Pt Pt # Type Use
|
|
BUF_LAN_D_INIT<1>__$INT
|
|
2 0 0 3 FB4_1 (b) (b)
|
|
D<0> 2 0 0 3 FB4_2 2 GTS/I/O I/O
|
|
LAN_WR_RST 3 0 0 2 FB4_3 (b) (b)
|
|
LAN_RST_SM_FSM_FFd3 3 0 0 2 FB4_4 (b) (b)
|
|
A_LAN<1> 1 0 0 4 FB4_5 3 GTS/I/O O
|
|
A_LAN<0> 1 0 0 4 FB4_6 4 I/O O
|
|
LAN_RST_SM_FSM_FFd2 3 0 0 2 FB4_7 (b) (b)
|
|
A_LAN<3> 2 0 0 3 FB4_8 5 GTS/I/O O
|
|
LAN_RST_SM_FSM_FFd1 3 0 0 2 FB4_9 (b) (b)
|
|
LAN_CS_RST 3 0 0 2 FB4_10 (b) (b)
|
|
LAN_BASEADR<4> 3 0 0 2 FB4_11 (b) (b)
|
|
A_LAN<2> 1 0 0 4 FB4_12 6 GTS/I/O O
|
|
LAN_BASEADR<3> 3 0 0 2 FB4_13 (b) (b)
|
|
A_LAN<5> 1 0 0 4 FB4_14 7 I/O O
|
|
LAN_BASEADR<2> 3 0 0 2 FB4_15 (b) (b)
|
|
LAN_BASEADR<13> 3 0 0 2 FB4_16 (b) (b)
|
|
LAN_BASEADR<12> 3 0 0 2 FB4_17 (b) (b)
|
|
LAN_BASEADR<11> 3 0 0 2 FB4_18 (b) (b)
|
|
|
|
Signals Used by Logic in Function Block
|
|
1: $OpTx$FX_DC$25 11: LAN_RST_SM_FSM_FFd1 21: RW
|
|
2: $OpTx$FX_DC$42 12: LAN_RST_SM_FSM_FFd2 22: SLAVE
|
|
3: BUF_LAN_D_INIT<1>__$INT 13: LAN_RST_SM_FSM_FFd3 23: Z3_ADR<2>
|
|
4: LAN_A_INIT<3> 14: D<13>.PIN 24: Z3_ADR<4>
|
|
5: LAN_BASEADR<11> 15: D<12>.PIN 25: Z3_ADR_0
|
|
6: LAN_BASEADR<12> 16: D<11>.PIN 26: Z3_ADR_1
|
|
7: LAN_BASEADR<13> 17: D<4>.PIN 27: Z3_A_LOW
|
|
8: LAN_BASEADR<2> 18: D<3>.PIN 28: Z3_DATA<16>
|
|
9: LAN_BASEADR<3> 19: D<2>.PIN 29: Z3_DATA<7>/Z3_DATA<7>_TRST
|
|
10: LAN_BASEADR<4> 20: RESET
|
|
|
|
Signal 1 2 3 4 FB
|
|
Name 0----+----0----+----0----+----0----+----0 Inputs
|
|
BUF_LAN_D_INIT<1>__$INT
|
|
..........XXX........................... 3
|
|
D<0> X...................XX.....XX........... 5
|
|
LAN_WR_RST ..........XXX......X.................... 4
|
|
LAN_RST_SM_FSM_FFd3 ..X.......XX.......X.................... 4
|
|
A_LAN<1> ...................X....X............... 2
|
|
A_LAN<0> ...................X......X............. 2
|
|
LAN_RST_SM_FSM_FFd2 ..X........XX......X.................... 4
|
|
A_LAN<3> ...X...............X..X................. 3
|
|
LAN_RST_SM_FSM_FFd1 ..........XXX......X.................... 4
|
|
LAN_CS_RST ..X.......X........X.................... 3
|
|
LAN_BASEADR<4> .X.......X......X..X.................... 4
|
|
A_LAN<2> ...................X.....X.............. 2
|
|
LAN_BASEADR<3> .X......X........X.X.................... 4
|
|
A_LAN<5> ...................X...X................ 2
|
|
LAN_BASEADR<2> .X.....X..........XX.................... 4
|
|
LAN_BASEADR<13> .X....X......X.....X.................... 4
|
|
LAN_BASEADR<12> .X...X........X....X.................... 4
|
|
LAN_BASEADR<11> .X..X..........X...X.................... 4
|
|
0----+----1----+----2----+----3----+----4
|
|
0 0 0 0
|
|
*********************************** FB5 ***********************************
|
|
Number of function block inputs used/remaining: 35/19
|
|
Number of signals used by logic mapping into function block: 35
|
|
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
|
Name Pt Pt Pt Pt # Type Use
|
|
(unused) 0 0 0 5 FB5_1 (b)
|
|
CP_CS 0 0 0 5 FB5_2 34 I/O O
|
|
(unused) 0 0 0 5 FB5_3 (b)
|
|
LAN_IRQ_D0 2 0 0 3 FB5_4 (b) (b)
|
|
ROM_OE 0 0 0 5 FB5_5 35 I/O O
|
|
Dout1<7> 2 0 0 3 FB5_6 (b) (b)
|
|
Dout1<3> 2 0 0 3 FB5_7 (b) (b)
|
|
Dout1<0> 2 0 0 3 FB5_8 38 GCK/I/O (b)
|
|
LAN_INT_ENABLE 3 0 0 2 FB5_9 (b) (b)
|
|
D<2> 2 0 0 3 FB5_10 39 I/O I/O
|
|
LAN_BASEADR<15> 3 0 0 2 FB5_11 (b) (b)
|
|
D<9> 3 0 0 2 FB5_12 40 I/O I/O
|
|
LAN_BASEADR<14> 3 0 0 2 FB5_13 (b) (b)
|
|
D<10> 3 0 0 2 FB5_14 41 I/O I/O
|
|
D<11> 3 0 0 2 FB5_15 43 I/O I/O
|
|
LAN_BASEADR<10> 3 0 0 2 FB5_16 (b) (b)
|
|
D<12> 3 0 0 2 FB5_17 44 I/O I/O
|
|
LAN_IRQ_OUT 4 0 0 1 FB5_18 (b) (b)
|
|
|
|
Signals Used by Logic in Function Block
|
|
1: $OpTx$FX_DC$25 13: LAN_INT 25: Z3_ADR<5>
|
|
2: $OpTx$FX_DC$42 14: LAN_IRQ_D0 26: Z3_ADR<6>
|
|
3: $OpTx$FX_DC$66 15: LAN_IRQ_OUT 27: Z3_ADR_0
|
|
4: Dout1<1> 16: D<15>.PIN 28: Z3_ADR_1
|
|
5: Dout1<2> 17: D<14>.PIN 29: Z3_DATA<18>
|
|
6: Dout1<3> 18: D<10>.PIN 30: Z3_DATA<25>
|
|
7: Dout1<4> 19: RESET 31: Z3_DATA<26>
|
|
8: FCS 20: RW 32: Z3_DATA<27>
|
|
9: LAN_BASEADR<10> 21: SLAVE 33: Z3_DATA<28>
|
|
10: LAN_BASEADR<14> 22: Z3_ADR<2> 34: Z3_DATA<7>/Z3_DATA<7>_TRST
|
|
11: LAN_BASEADR<15> 23: Z3_ADR<3> 35: autoconfig
|
|
12: LAN_INT_ENABLE 24: Z3_ADR<4>
|
|
|
|
Signal 1 2 3 4 FB
|
|
Name 0----+----0----+----0----+----0----+----0 Inputs
|
|
CP_CS ........................................ 0
|
|
LAN_IRQ_D0 ............X.....X..................... 2
|
|
ROM_OE ........................................ 0
|
|
Dout1<7> X......X..........X...XXXX.X......X..... 9
|
|
Dout1<3> X......X..........X...XXX..X......X..... 8
|
|
Dout1<0> X......X..........X..XXXX.XX......X..... 10
|
|
LAN_INT_ENABLE ..X........X...X..X..................... 4
|
|
D<2> X..................XX.......X....X...... 5
|
|
LAN_BASEADR<15> .X........X....X..X..................... 4
|
|
D<9> X..X...............XX........X...X...... 6
|
|
LAN_BASEADR<14> .X.......X......X.X..................... 4
|
|
D<10> X...X..............XX.........X..X...... 6
|
|
D<11> X....X.............XX..........X.X...... 6
|
|
LAN_BASEADR<10> .X......X........XX..................... 4
|
|
D<12> X.....X............XX...........XX...... 6
|
|
LAN_IRQ_OUT ..X........XXXX.X.X..................... 7
|
|
0----+----1----+----2----+----3----+----4
|
|
0 0 0 0
|
|
*********************************** FB6 ***********************************
|
|
Number of function block inputs used/remaining: 34/20
|
|
Number of signals used by logic mapping into function block: 34
|
|
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
|
Name Pt Pt Pt Pt # Type Use
|
|
(unused) 0 0 0 5 FB6_1 (b)
|
|
LAN_CFG<2> 0 0 0 5 FB6_2 135 I/O O
|
|
A_LAN<12> 1 0 0 4 FB6_3 136 I/O O
|
|
(unused) 0 0 0 5 FB6_4 (b)
|
|
A_LAN<13> 1 0 0 4 FB6_5 137 I/O O
|
|
A_LAN<10> 1 0 0 4 FB6_6 138 I/O O
|
|
(unused) 0 0 0 5 FB6_7 (b)
|
|
A_LAN<11> 1 0 0 4 FB6_8 139 I/O O
|
|
$OpTx$FX_DC$24 1 0 0 4 FB6_9 (b) (b)
|
|
A_LAN<8> 1 0 0 4 FB6_10 140 I/O O
|
|
$OpTx$FX_DC$23 1 0 0 4 FB6_11 (b) (b)
|
|
LAN_WRL_S 3 0 0 2 FB6_12 (b) (b)
|
|
LAN_BASEADR<9> 3 0 0 2 FB6_13 (b) (b)
|
|
A_LAN<9> 1 0 0 4 FB6_14 142 I/O O
|
|
LAN_BASEADR<5> 3 0 0 2 FB6_15 143 GSR/I/O I
|
|
LAN_BASEADR<1> 3 0 0 2 FB6_16 (b) (b)
|
|
LAN_BASEADR<0> 3 0 \/1 1 FB6_17 (b) (b)
|
|
Z3_DATA<25> 6 1<- 0 0 FB6_18 (b) (b)
|
|
|
|
Signals Used by Logic in Function Block
|
|
1: $OpTx$FX_DC$25 13: LAN_SM_FSM_FFd3 24: Z3_ADR<10>
|
|
2: $OpTx$FX_DC$268 14: LAN_SM_FSM_FFd4 25: Z3_ADR<11>
|
|
3: $OpTx$FX_DC$325 15: LDS 26: Z3_ADR<12>
|
|
4: $OpTx$FX_DC$42 16: DQ<9>.PIN 27: Z3_ADR<13>
|
|
5: DS0 17: DQ<1>.PIN 28: Z3_ADR<7>
|
|
6: DS1 18: D<9>.PIN 29: Z3_ADR<8>
|
|
7: LAN_BASEADR<0> 19: D<5>.PIN 30: Z3_ADR<9>
|
|
8: LAN_BASEADR<1> 20: D<1>.PIN 31: Z3_DATA<25>
|
|
9: LAN_BASEADR<5> 21: D<0>.PIN 32: lan_adr
|
|
10: LAN_BASEADR<9> 22: RESET 33: lan_adr_sw
|
|
11: LAN_SM_FSM_FFd1 23: UDS 34: lan_rdy/lan_rdy_RSTF
|
|
12: LAN_SM_FSM_FFd2
|
|
|
|
Signal 1 2 3 4 FB
|
|
Name 0----+----0----+----0----+----0----+----0 Inputs
|
|
LAN_CFG<2> ........................................ 0
|
|
A_LAN<12> .....................X..X............... 2
|
|
A_LAN<13> .....................X...X.............. 2
|
|
A_LAN<10> .....................X.......X.......... 2
|
|
A_LAN<11> .....................X.X................ 2
|
|
$OpTx$FX_DC$24 ..............X.......X................. 2
|
|
A_LAN<8> .....................X.....X............ 2
|
|
$OpTx$FX_DC$23 ....XX.................................. 2
|
|
LAN_WRL_S .X...X....XX..........X..........X...... 6
|
|
LAN_BASEADR<9> ...X.....X.......X...X.................. 4
|
|
A_LAN<9> .....................X......X........... 2
|
|
LAN_BASEADR<5> ...X....X.........X..X.................. 4
|
|
LAN_BASEADR<1> ...X...X...........X.X.................. 4
|
|
LAN_BASEADR<0> ...X..X.............XX.................. 4
|
|
Z3_DATA<25> X.X.......XXXX.XXX.X......X...XXXX...... 15
|
|
0----+----1----+----2----+----3----+----4
|
|
0 0 0 0
|
|
*********************************** FB7 ***********************************
|
|
Number of function block inputs used/remaining: 33/21
|
|
Number of signals used by logic mapping into function block: 33
|
|
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
|
Name Pt Pt Pt Pt # Type Use
|
|
lan_adr_sw/lan_adr_sw_RSTF
|
|
1 0 0 4 FB7_1 (b) (b)
|
|
LAN_D_INIT<1> 2 0 0 3 FB7_2 (b) (b)
|
|
D<13> 3 0 0 2 FB7_3 45 I/O I/O
|
|
LAN_D_INIT<10> 2 0 0 3 FB7_4 (b) (b)
|
|
D<14> 3 0 0 2 FB7_5 46 I/O I/O
|
|
LAN_A_INIT<6> 2 0 0 3 FB7_6 (b) (b)
|
|
lan_adr 3 0 0 2 FB7_7 (b) (b)
|
|
autoconfig 3 0 0 2 FB7_8 (b) (b)
|
|
Z3_ADR<7> 3 0 0 2 FB7_9 (b) (b)
|
|
Z3_ADR<6> 3 0 0 2 FB7_10 (b) (b)
|
|
Z3_ADR<5> 3 0 0 2 FB7_11 (b) (b)
|
|
D<15> 3 0 0 2 FB7_12 48 I/O I/O
|
|
Z3_ADR<4> 3 0 0 2 FB7_13 (b) (b)
|
|
Z3_ADR<3> 3 0 0 2 FB7_14 (b) (b)
|
|
LAN_BASEADR<8> 3 0 0 2 FB7_15 49 I/O I
|
|
LAN_BASEADR<7> 3 0 0 2 FB7_16 (b) (b)
|
|
LAN_BASEADR<6> 3 0 0 2 FB7_17 (b) (b)
|
|
lan_adr_sw 4 0 0 1 FB7_18 (b) (b)
|
|
|
|
Signals Used by Logic in Function Block
|
|
1: $OpTx$FX_DC$25 12: FCS 23: D<6>.PIN
|
|
2: $OpTx$FX_DC$42 13: LAN_BASEADR<6> 24: RESET
|
|
3: A<5> 14: LAN_BASEADR<7> 25: RW
|
|
4: A<6> 15: LAN_BASEADR<8> 26: SHUT_UP
|
|
5: A<7> 16: Mcompar_lan_adr_sw_cmp_eq0001_AEB_or0000/Mcompar_lan_adr_sw_cmp_eq0001_AEB_or0000_D2 27: SLAVE
|
|
6: BERR 17: A<13>.PIN 28: Z3_DATA<29>
|
|
7: BUF_LAN_D_INIT<1>__$INT 18: A<14>.PIN 29: Z3_DATA<30>
|
|
8: BUF_autoconfig 19: A<8>.PIN 30: Z3_DATA<31>
|
|
9: Dout1<5> 20: A<9>.PIN 31: Z3_DATA<7>/Z3_DATA<7>_TRST
|
|
10: Dout1<6> 21: D<8>.PIN 32: Z3
|
|
11: Dout1<7> 22: D<7>.PIN 33: lan_adr_sw/lan_adr_sw_RSTF
|
|
|
|
Signal 1 2 3 4 FB
|
|
Name 0----+----0----+----0----+----0----+----0 Inputs
|
|
lan_adr_sw/lan_adr_sw_RSTF
|
|
.....X.................X................ 2
|
|
LAN_D_INIT<1> ......X................X................ 2
|
|
D<13> X.......X...............X.XX..X......... 6
|
|
LAN_D_INIT<10> ......X................X................ 2
|
|
D<14> X........X..............X.X.X.X......... 6
|
|
LAN_A_INIT<6> ......X................X................ 2
|
|
lan_adr .......X...X...X.........X.....XX....... 6
|
|
autoconfig .......X...X....................X....... 3
|
|
Z3_ADR<7> ...........X.......X............X....... 3
|
|
Z3_ADR<6> ...........X......X.............X....... 3
|
|
Z3_ADR<5> ....X......X....................X....... 3
|
|
D<15> X.........X.............X.X..XX......... 6
|
|
Z3_ADR<4> ...X.......X....................X....... 3
|
|
Z3_ADR<3> ..X........X....................X....... 3
|
|
LAN_BASEADR<8> .X............X.....X..X................ 4
|
|
LAN_BASEADR<7> .X...........X.......X.X................ 4
|
|
LAN_BASEADR<6> .X..........X.........XX................ 4
|
|
lan_adr_sw .......X...X...XXX.......X.....XX....... 8
|
|
0----+----1----+----2----+----3----+----4
|
|
0 0 0 0
|
|
*********************************** FB8 ***********************************
|
|
Number of function block inputs used/remaining: 35/19
|
|
Number of signals used by logic mapping into function block: 35
|
|
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
|
Name Pt Pt Pt Pt # Type Use
|
|
Z3_DATA<27> 6 2<- /\1 0 FB8_1 (b) (b)
|
|
DQ<12> 3 0 /\2 0 FB8_2 130 I/O I/O
|
|
DQ<14> 3 0 0 2 FB8_3 131 I/O I/O
|
|
(unused) 0 0 0 5 FB8_4 (b)
|
|
LAN_WRH 2 0 0 3 FB8_5 132 I/O O
|
|
(unused) 0 0 0 5 FB8_6 (b)
|
|
(unused) 0 0 0 5 FB8_7 (b)
|
|
LAN_CS 2 0 0 3 FB8_8 133 I/O O
|
|
(unused) 0 0 0 5 FB8_9 (b)
|
|
LAN_RD 1 0 0 4 FB8_10 134 I/O O
|
|
(unused) 0 0 0 5 FB8_11 (b)
|
|
(unused) 0 0 0 5 FB8_12 (b)
|
|
(unused) 0 0 0 5 FB8_13 (b)
|
|
(unused) 0 0 0 5 FB8_14 (b)
|
|
(unused) 0 0 \/2 3 FB8_15 (b) (b)
|
|
Z3_DATA<26> 6 2<- \/1 0 FB8_16 (b) (b)
|
|
Z3_DATA<19> 6 1<- 0 0 FB8_17 (b) (b)
|
|
Z3_DATA<18> 6 1<- 0 0 FB8_18 (b) (b)
|
|
|
|
Signals Used by Logic in Function Block
|
|
1: $OpTx$FX_DC$25 13: LAN_WRH_S 25: Z3_ADR<13>
|
|
2: $OpTx$FX_DC$325 14: LAN_WR_RST 26: Z3_A_LOW
|
|
3: $OpTx$FX_DC$49 15: DQ<11>.PIN 27: Z3_DATA<18>
|
|
4: A<20> 16: DQ<10>.PIN 28: Z3_DATA<19>
|
|
5: A<22> 17: DQ<3>.PIN 29: Z3_DATA<26>
|
|
6: DQ_14_IOBUFE/DQ_14_IOBUFE_TRST 18: DQ<2>.PIN 30: Z3_DATA<27>
|
|
7: LAN_CS_RST 19: D<11>.PIN 31: Z3_DATA<28>
|
|
8: LAN_RD_S 20: D<10>.PIN 32: Z3_DATA<30>
|
|
9: LAN_SM_FSM_FFd1 21: D<3>.PIN 33: lan_adr
|
|
10: LAN_SM_FSM_FFd2 22: D<2>.PIN 34: lan_adr_sw
|
|
11: LAN_SM_FSM_FFd3 23: RESET 35: lan_rdy/lan_rdy_RSTF
|
|
12: LAN_SM_FSM_FFd4 24: RW
|
|
|
|
Signal 1 2 3 4 FB
|
|
Name 0----+----0----+----0----+----0----+----0 Inputs
|
|
Z3_DATA<27> XX......XXXX..X.X.X.X...X....X..XXX..... 15
|
|
DQ<12> X.XX.X................XX.X....X.X.X..... 10
|
|
DQ<14> X.X.XX................XX.X.....XX.X..... 10
|
|
LAN_WRH ............XX....................X..... 3
|
|
LAN_CS ......X...............X.........X....... 3
|
|
LAN_RD .......X..........................X..... 2
|
|
Z3_DATA<26> XX......XXXX...X.X.X.X..X...X...XXX..... 15
|
|
Z3_DATA<19> XX......XXXX..X.X.X.X...X..X....XXX..... 15
|
|
Z3_DATA<18> XX......XXXX...X.X.X.X..X.X.....XXX..... 15
|
|
0----+----1----+----2----+----3----+----4
|
|
0 0 0 0
|
|
*********************************** FB9 ***********************************
|
|
Number of function block inputs used/remaining: 35/19
|
|
Number of signals used by logic mapping into function block: 35
|
|
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
|
Name Pt Pt Pt Pt # Type Use
|
|
(unused) 0 0 /\4 1 FB9_1 (b) (b)
|
|
(unused) 0 0 0 5 FB9_2 50 I/O I
|
|
(unused) 0 0 0 5 FB9_3 51 I/O I
|
|
(unused) 0 0 0 5 FB9_4 (b)
|
|
(unused) 0 0 0 5 FB9_5 52 I/O I
|
|
(unused) 0 0 0 5 FB9_6 53 I/O I
|
|
(unused) 0 0 0 5 FB9_7 (b)
|
|
(unused) 0 0 0 5 FB9_8 54 I/O I
|
|
(unused) 0 0 0 5 FB9_9 (b)
|
|
(unused) 0 0 \/1 4 FB9_10 (b) (b)
|
|
A<8> 7 2<- 0 0 FB9_11 56 I/O I/O
|
|
(unused) 0 0 /\1 4 FB9_12 57 I/O (b)
|
|
(unused) 0 0 \/3 2 FB9_13 (b) (b)
|
|
A<9> 7 3<- \/1 0 FB9_14 58 I/O I/O
|
|
Z3_DATA<24> 6 1<- 0 0 FB9_15 (b) (b)
|
|
Z3_DATA<17> 6 1<- 0 0 FB9_16 (b) (b)
|
|
A<10> 7 3<- /\1 0 FB9_17 59 I/O I/O
|
|
Z3_DATA<16> 6 4<- /\3 0 FB9_18 (b) (b)
|
|
|
|
Signals Used by Logic in Function Block
|
|
1: $OpTx$FX_DC$25 13: A<16>.PIN 25: D<8>.PIN
|
|
2: $OpTx$FX_DC$325 14: A<17>.PIN 26: D<1>.PIN
|
|
3: $OpTx$FX_DC$326 15: A<18>.PIN 27: D<0>.PIN
|
|
4: A<10> 16: A<8>.PIN 28: RW
|
|
5: A<8> 17: A<9>.PIN 29: Z3_ADR<13>
|
|
6: A<9> 18: DQ<10>.PIN 30: Z3_DATA<16>
|
|
7: FCS 19: DQ<9>.PIN 31: Z3_DATA<17>
|
|
8: LAN_SM_FSM_FFd1 20: DQ<8>.PIN 32: Z3_DATA<24>
|
|
9: LAN_SM_FSM_FFd2 21: DQ<2>.PIN 33: lan_adr
|
|
10: LAN_SM_FSM_FFd3 22: DQ<1>.PIN 34: lan_adr_sw
|
|
11: LAN_SM_FSM_FFd4 23: DQ<0>.PIN 35: lan_rdy/lan_rdy_RSTF
|
|
12: A<10>.PIN 24: D<9>.PIN
|
|
|
|
Signal 1 2 3 4 FB
|
|
Name 0----+----0----+----0----+----0----+----0 Inputs
|
|
A<8> X.X.X.XXXXX.X..X...X..X....XX...XXX..... 17
|
|
A<9> X.X..XXXXXX..X..X.X..X.....XX...XXX..... 17
|
|
Z3_DATA<24> XX.....XXXX........X..X.X.X.X..XXXX..... 15
|
|
Z3_DATA<17> XX.....XXXX.......X..X.X.X..X.X.XXX..... 15
|
|
A<10> X.XX..XXXXXX..X..X..X......XX...XXX..... 17
|
|
Z3_DATA<16> XX.....XXXX........X..X.X.X.XX..XXX..... 15
|
|
0----+----1----+----2----+----3----+----4
|
|
0 0 0 0
|
|
*********************************** FB10 ***********************************
|
|
Number of function block inputs used/remaining: 36/18
|
|
Number of signals used by logic mapping into function block: 36
|
|
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
|
Name Pt Pt Pt Pt # Type Use
|
|
lan_rdy/lan_rdy_RSTF
|
|
1 0 0 4 FB10_1 (b) (b)
|
|
DQ<1> 4 0 0 1 FB10_2 117 I/O I/O
|
|
DQ<0> 3 0 0 2 FB10_3 118 I/O I/O
|
|
Z3_DATA<7>/Z3_DATA<7>_TRST
|
|
1 0 0 4 FB10_4 (b) (b)
|
|
DQ<3> 3 0 0 2 FB10_5 119 I/O I/O
|
|
DQ<2> 3 0 0 2 FB10_6 120 I/O I/O
|
|
$OpTx$FX_DC$66 1 0 0 4 FB10_7 (b) (b)
|
|
DQ<5> 3 0 0 2 FB10_8 121 I/O I/O
|
|
DQ_14_IOBUFE/DQ_14_IOBUFE_TRST
|
|
2 0 0 3 FB10_9 (b) (b)
|
|
DQ<4> 4 0 0 1 FB10_10 124 I/O I/O
|
|
DQ<7> 3 0 0 2 FB10_11 125 I/O I/O
|
|
DQ<6> 3 0 0 2 FB10_12 126 I/O I/O
|
|
DQ_11_IOBUFE/DQ_11_IOBUFE_TRST
|
|
2 0 0 3 FB10_13 (b) (b)
|
|
DQ<8> 3 0 0 2 FB10_14 128 I/O I/O
|
|
$OpTx$FX_DC$61 2 0 0 3 FB10_15 (b) (b)
|
|
$OpTx$FX_DC$49 2 0 0 3 FB10_16 (b) (b)
|
|
DQ<10> 4 0 0 1 FB10_17 129 I/O I/O
|
|
Z3_ADR<10> 3 0 0 2 FB10_18 (b) (b)
|
|
|
|
Signals Used by Logic in Function Block
|
|
1: $OpTx$FX_DC$25 13: A<9> 25: Z3_DATA<17>
|
|
2: $OpTx$FX_DC$49 14: DQ_11_IOBUFE/DQ_11_IOBUFE_TRST 26: Z3_DATA<18>
|
|
3: $OpTx$FX_DC$61 15: DQ_14_IOBUFE/DQ_14_IOBUFE_TRST 27: Z3_DATA<19>
|
|
4: A<10> 16: FCS 28: Z3_DATA<20>
|
|
5: A<11> 17: LAN_D_INIT<10> 29: Z3_DATA<21>
|
|
6: A<12> 18: LAN_D_INIT<1> 30: Z3_DATA<22>
|
|
7: A<13> 19: A<12>.PIN 31: Z3_DATA<23>
|
|
8: A<14> 20: RESET 32: Z3_DATA<24>
|
|
9: A<15> 21: RW 33: Z3_DATA<26>
|
|
10: A<16> 22: Z3_ADR<13> 34: lan_adr
|
|
11: A<18> 23: Z3_A_LOW 35: lan_adr_sw/lan_adr_sw_RSTF
|
|
12: A<8> 24: Z3_DATA<16> 36: lan_rdy/lan_rdy_RSTF
|
|
|
|
Signal 1 2 3 4 FB
|
|
Name 0----+----0----+----0----+----0----+----0 Inputs
|
|
lan_rdy/lan_rdy_RSTF
|
|
...............X...X.................... 2
|
|
DQ<1> X.X.........X.X..X.XX.X.X........X.X.... 11
|
|
DQ<0> XX.........X..X....XX.XX.........X.X.... 10
|
|
Z3_DATA<7>/Z3_DATA<7>_TRST
|
|
X..............X....X............X...... 4
|
|
DQ<3> XX..X.........X....XX.X...X......X.X.... 10
|
|
DQ<2> XX.X.........X.....XX.X..X.......X.X.... 10
|
|
$OpTx$FX_DC$66 X...................XX...........X...... 4
|
|
DQ<5> XX....X.......X....XX.X.....X....X.X.... 10
|
|
DQ_14_IOBUFE/DQ_14_IOBUFE_TRST
|
|
X..................XX............X.X.... 5
|
|
DQ<4> X.X..X........X..X.XX.X....X.....X.X.... 11
|
|
DQ<7> XX......X.....X....XX.X.......X..X.X.... 10
|
|
DQ<6> XX.....X......X....XX.X......X...X.X.... 10
|
|
DQ_11_IOBUFE/DQ_11_IOBUFE_TRST
|
|
X..................XX............X.X.... 5
|
|
DQ<8> XX.......X...X.....XX.X........X.X.X.... 10
|
|
$OpTx$FX_DC$61 X..............X...XX.X..........X...... 6
|
|
$OpTx$FX_DC$49 X..............X...XX.X..........X...... 6
|
|
DQ<10> X.X.......X...X.X..XX.X.........XX.X.... 11
|
|
Z3_ADR<10> ...............X..X...............X..... 3
|
|
0----+----1----+----2----+----3----+----4
|
|
0 0 0 0
|
|
*********************************** FB11 ***********************************
|
|
Number of function block inputs used/remaining: 35/19
|
|
Number of signals used by logic mapping into function block: 35
|
|
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
|
Name Pt Pt Pt Pt # Type Use
|
|
LAN_SM_FSM_FFd1 2 0 0 3 FB11_1 (b) (b)
|
|
BUF_LAN_RD_S 2 0 \/1 2 FB11_2 (b) (b)
|
|
A<11> 7 2<- 0 0 FB11_3 60 I/O I/O
|
|
Z3_ADR<9> 3 0 /\1 1 FB11_4 (b) (b)
|
|
A<12> 7 2<- 0 0 FB11_5 61 I/O I/O
|
|
Z3_ADR<12> 3 0 /\2 0 FB11_6 (b) (b)
|
|
Z3_ADR<11> 3 0 0 2 FB11_7 (b) (b)
|
|
LAN_SM_FSM_FFd3 3 0 0 2 FB11_8 (b) (b)
|
|
$OpTx$FX_DC$326 3 0 \/2 0 FB11_9 (b) (b)
|
|
A<13> 7 2<- 0 0 FB11_10 64 I/O I/O
|
|
A<14> 7 2<- 0 0 FB11_11 66 I/O I/O
|
|
ROM_B<0> 0 0 /\2 3 FB11_12 68 I/O O
|
|
lan_rdy 4 0 0 1 FB11_13 (b) (b)
|
|
ROM_B<1> 0 0 0 5 FB11_14 69 I/O O
|
|
BUF_LAN_SM_FSM_FFd2 4 0 0 1 FB11_15 (b) (b)
|
|
Z3_A_LOW 5 0 0 0 FB11_16 (b) (b)
|
|
CP_WE 0 0 \/1 4 FB11_17 70 I/O O
|
|
BUF_LAN_SM_FSM_FFd4__$INT
|
|
6 1<- 0 0 FB11_18 (b) (b)
|
|
|
|
Signals Used by Logic in Function Block
|
|
1: $OpTx$FX_DC$23 13: LAN_SM_FSM_FFd4 25: DQ<11>.PIN
|
|
2: $OpTx$FX_DC$24 14: A<11>.PIN 26: DQ<6>.PIN
|
|
3: $OpTx$FX_DC$25 15: A<12>.PIN 27: DQ<5>.PIN
|
|
4: $OpTx$FX_DC$326 16: A<13>.PIN 28: DQ<4>.PIN
|
|
5: A<11> 17: A<14>.PIN 29: DQ<3>.PIN
|
|
6: A<12> 18: A<20>.PIN 30: RW
|
|
7: A<13> 19: A<21>.PIN 31: Z3_ADR<13>
|
|
8: A<14> 20: A<22>.PIN 32: lan_adr
|
|
9: FCS 21: A<19>.PIN 33: lan_adr_sw
|
|
10: LAN_SM_FSM_FFd1 22: DQ<14>.PIN 34: lan_adr_sw/lan_adr_sw_RSTF
|
|
11: LAN_SM_FSM_FFd2 23: DQ<13>.PIN 35: lan_rdy/lan_rdy_RSTF
|
|
12: LAN_SM_FSM_FFd3 24: DQ<12>.PIN
|
|
|
|
Signal 1 2 3 4 FB
|
|
Name 0----+----0----+----0----+----0----+----0 Inputs
|
|
LAN_SM_FSM_FFd1 ..X......X.XX................XXX..X..... 8
|
|
BUF_LAN_RD_S .........XXXX........................... 4
|
|
A<11> ..XXX...XXXXXX......X...X...XXXXX.X..... 17
|
|
Z3_ADR<9> ........X....X...................X...... 3
|
|
A<12> ..XX.X..XXXXX.X..X.....X...X.XXXX.X..... 17
|
|
Z3_ADR<12> ........X.......X................X...... 3
|
|
Z3_ADR<11> ........X......X.................X...... 3
|
|
LAN_SM_FSM_FFd3 X........XXXX.....................X..... 6
|
|
$OpTx$FX_DC$326 XX.......XXXX.................XX........ 8
|
|
A<13> ..XX..X.XXXXX..X..X...X...X..XXXX.X..... 17
|
|
A<14> ..XX...XXXXXX...X..X.X...X...XXXX.X..... 17
|
|
ROM_B<0> ........................................ 0
|
|
lan_rdy X........XXXX.....................X..... 6
|
|
ROM_B<1> ........................................ 0
|
|
BUF_LAN_SM_FSM_FFd2 XX........XXX.................XX........ 7
|
|
Z3_A_LOW XX.......XXXX.................XX..X..... 9
|
|
CP_WE ........................................ 0
|
|
BUF_LAN_SM_FSM_FFd4__$INT
|
|
XX.......XXXX.................XX........ 8
|
|
0----+----1----+----2----+----3----+----4
|
|
0 0 0 0
|
|
*********************************** FB12 ***********************************
|
|
Number of function block inputs used/remaining: 35/19
|
|
Number of signals used by logic mapping into function block: 35
|
|
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
|
Name Pt Pt Pt Pt # Type Use
|
|
(unused) 0 0 /\1 4 FB12_1 (b) (b)
|
|
LAN_CFG<4> 0 0 0 5 FB12_2 110 I/O O
|
|
(unused) 0 0 0 5 FB12_3 111 I/O I
|
|
(unused) 0 0 0 5 FB12_4 (b)
|
|
DQ<15> 3 0 0 2 FB12_5 112 I/O I/O
|
|
(unused) 0 0 0 5 FB12_6 (b)
|
|
(unused) 0 0 0 5 FB12_7 (b)
|
|
DQ<13> 3 0 0 2 FB12_8 113 I/O I/O
|
|
(unused) 0 0 0 5 FB12_9 (b)
|
|
DQ<11> 4 0 0 1 FB12_10 115 I/O I/O
|
|
(unused) 0 0 0 5 FB12_11 (b)
|
|
DQ<9> 4 0 0 1 FB12_12 116 I/O I/O
|
|
(unused) 0 0 0 5 FB12_13 (b)
|
|
LAN_D_INIT<9> 1 0 0 4 FB12_14 (b) (b)
|
|
LAN_A_INIT<3> 1 0 0 4 FB12_15 (b) (b)
|
|
LAN_WRH_S 3 0 \/1 1 FB12_16 (b) (b)
|
|
Z3_DATA<31> 6 1<- 0 0 FB12_17 (b) (b)
|
|
Z3_DATA<23> 6 1<- 0 0 FB12_18 (b) (b)
|
|
|
|
Signals Used by Logic in Function Block
|
|
1: $OpTx$FX_DC$25 13: LAN_D_INIT<10> 25: RW
|
|
2: $OpTx$FX_DC$268 14: LAN_D_INIT<9> 26: Z3_ADR<13>
|
|
3: $OpTx$FX_DC$325 15: LAN_SM_FSM_FFd1 27: Z3_A_LOW
|
|
4: $OpTx$FX_DC$49 16: LAN_SM_FSM_FFd2 28: Z3_DATA<23>
|
|
5: $OpTx$FX_DC$61 17: LAN_SM_FSM_FFd3 29: Z3_DATA<25>
|
|
6: A<17> 18: LAN_SM_FSM_FFd4 30: Z3_DATA<27>
|
|
7: A<19> 19: LDS 31: Z3_DATA<29>
|
|
8: A<21> 20: DQ<15>.PIN 32: Z3_DATA<31>
|
|
9: A<23> 21: DQ<7>.PIN 33: lan_adr
|
|
10: DQ_11_IOBUFE/DQ_11_IOBUFE_TRST 22: D<15>.PIN 34: lan_adr_sw
|
|
11: DQ_14_IOBUFE/DQ_14_IOBUFE_TRST 23: D<7>.PIN 35: lan_rdy/lan_rdy_RSTF
|
|
12: DS0 24: RESET
|
|
|
|
Signal 1 2 3 4 FB
|
|
Name 0----+----0----+----0----+----0----+----0 Inputs
|
|
LAN_CFG<4> ........................................ 0
|
|
DQ<15> X..X....X.X............XX.X....XX.X..... 10
|
|
DQ<13> X..X...X.X.............XX.X...X.X.X..... 10
|
|
DQ<11> X...X.X..X..X..........XX.X..X..X.X..... 11
|
|
DQ<9> X...XX....X..X.........XX.X.X...X.X..... 11
|
|
LAN_D_INIT<9> .......................X................ 1
|
|
LAN_A_INIT<3> .......................X................ 1
|
|
LAN_WRH_S .X.........X..XX..X...............X..... 6
|
|
Z3_DATA<31> X.X...........XXXX.XXXX..X.....XXXX..... 15
|
|
Z3_DATA<23> X.X...........XXXX.XXXX..X.X....XXX..... 15
|
|
0----+----1----+----2----+----3----+----4
|
|
0 0 0 0
|
|
*********************************** FB13 ***********************************
|
|
Number of function block inputs used/remaining: 35/19
|
|
Number of signals used by logic mapping into function block: 35
|
|
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
|
Name Pt Pt Pt Pt # Type Use
|
|
LAN_SM_FSM_FFd4 2 0 /\2 1 FB13_1 (b) (b)
|
|
CP_RD 0 0 0 5 FB13_2 71 I/O O
|
|
(unused) 0 0 0 5 FB13_3 (b)
|
|
(unused) 0 0 0 5 FB13_4 (b)
|
|
(unused) 0 0 0 5 FB13_5 (b)
|
|
(unused) 0 0 0 5 FB13_6 (b)
|
|
(unused) 0 0 \/1 4 FB13_7 (b) (b)
|
|
A<15> 7 2<- 0 0 FB13_8 74 I/O I/O
|
|
(unused) 0 0 /\1 4 FB13_9 (b) (b)
|
|
(unused) 0 0 0 5 FB13_10 (b)
|
|
LAN_SM_FSM_FFd2 2 0 0 3 FB13_11 75 I/O I
|
|
LAN_RD_S 2 0 0 3 FB13_12 (b) (b)
|
|
$OpTx$FX_DC$325 2 0 0 3 FB13_13 (b) (b)
|
|
LAN_WRL 2 0 \/2 1 FB13_14 76 I/O O
|
|
Z3_DATA<30> 6 2<- \/1 0 FB13_15 77 I/O I
|
|
Z3_DATA<28> 6 1<- 0 0 FB13_16 (b) (b)
|
|
Z3_DATA<22> 6 1<- 0 0 FB13_17 78 I/O I
|
|
Z3_DATA<20> 6 2<- /\1 0 FB13_18 (b) (b)
|
|
|
|
Signals Used by Logic in Function Block
|
|
1: $OpTx$FX_DC$25 13: LAN_WRL_S 25: D<6>.PIN
|
|
2: $OpTx$FX_DC$325 14: LAN_WR_RST 26: D<4>.PIN
|
|
3: $OpTx$FX_DC$326 15: A<15>.PIN 27: RW
|
|
4: A<15> 16: A<23>.PIN 28: Z3_ADR<13>
|
|
5: BUF_LAN_RD_S 17: DQ<15>.PIN 29: Z3_DATA<20>
|
|
6: BUF_LAN_SM_FSM_FFd2 18: DQ<14>.PIN 30: Z3_DATA<22>
|
|
7: BUF_LAN_SM_FSM_FFd4__$INT 19: DQ<12>.PIN 31: Z3_DATA<28>
|
|
8: FCS 20: DQ<7>.PIN 32: Z3_DATA<30>
|
|
9: LAN_SM_FSM_FFd1 21: DQ<6>.PIN 33: lan_adr
|
|
10: LAN_SM_FSM_FFd2 22: DQ<4>.PIN 34: lan_adr_sw
|
|
11: LAN_SM_FSM_FFd3 23: D<14>.PIN 35: lan_rdy/lan_rdy_RSTF
|
|
12: LAN_SM_FSM_FFd4 24: D<12>.PIN
|
|
|
|
Signal 1 2 3 4 FB
|
|
Name 0----+----0----+----0----+----0----+----0 Inputs
|
|
LAN_SM_FSM_FFd4 ......X...........................X..... 2
|
|
CP_RD ........................................ 0
|
|
A<15> X.XX...XXXXX..XXX..X......XX....XXX..... 17
|
|
LAN_SM_FSM_FFd2 .....X............................X..... 2
|
|
LAN_RD_S ....X.............................X..... 2
|
|
$OpTx$FX_DC$325 ....XXX.X............................... 4
|
|
LAN_WRL ............XX....................X..... 3
|
|
Z3_DATA<30> XX......XXXX.....X..X.X.X..X...XXXX..... 15
|
|
Z3_DATA<28> XX......XXXX......X..X.X.X.X..X.XXX..... 15
|
|
Z3_DATA<22> XX......XXXX.....X..X.X.X..X.X..XXX..... 15
|
|
Z3_DATA<20> XX......XXXX......X..X.X.X.XX...XXX..... 15
|
|
0----+----1----+----2----+----3----+----4
|
|
0 0 0 0
|
|
*********************************** FB14 ***********************************
|
|
Number of function block inputs used/remaining: 6/48
|
|
Number of signals used by logic mapping into function block: 6
|
|
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
|
Name Pt Pt Pt Pt # Type Use
|
|
(unused) 0 0 0 5 FB14_1 (b)
|
|
(unused) 0 0 0 5 FB14_2 (b)
|
|
OVR 0 0 0 5 FB14_3 100 I/O O
|
|
(unused) 0 0 0 5 FB14_4 (b)
|
|
(unused) 0 0 0 5 FB14_5 101 I/O
|
|
(unused) 0 0 0 5 FB14_6 102 I/O
|
|
(unused) 0 0 0 5 FB14_7 (b)
|
|
(unused) 0 0 0 5 FB14_8 103 I/O
|
|
(unused) 0 0 0 5 FB14_9 (b)
|
|
(unused) 0 0 0 5 FB14_10 104 I/O I
|
|
CFOUT 3 0 0 2 FB14_11 105 I/O O
|
|
(unused) 0 0 0 5 FB14_12 (b)
|
|
(unused) 0 0 0 5 FB14_13 (b)
|
|
SLAVE 2 0 0 3 FB14_14 106 I/O O
|
|
OWN 0 0 0 5 FB14_15 107 I/O O
|
|
(unused) 0 0 0 5 FB14_16 (b)
|
|
(unused) 0 0 0 5 FB14_17 (b)
|
|
(unused) 0 0 0 5 FB14_18 (b)
|
|
|
|
Signals Used by Logic in Function Block
|
|
1: AUTOBOOT_OFF 3: FCS 5: autoconfig
|
|
2: AUTO_CONFIG_DONE_CYCLE 4: RESET 6: lan_adr
|
|
|
|
Signal 1 2 3 4 FB
|
|
Name 0----+----0----+----0----+----0----+----0 Inputs
|
|
OVR ........................................ 0
|
|
CFOUT XXXX.................................... 4
|
|
SLAVE ..X.XX.................................. 3
|
|
OWN ........................................ 0
|
|
0----+----1----+----2----+----3----+----4
|
|
0 0 0 0
|
|
*********************************** FB15 ***********************************
|
|
Number of function block inputs used/remaining: 35/19
|
|
Number of signals used by logic mapping into function block: 35
|
|
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
|
Name Pt Pt Pt Pt # Type Use
|
|
(unused) 0 0 /\3 2 FB15_1 (b) (b)
|
|
Z3_DATA<29> 6 1<- 0 0 FB15_2 79 I/O I
|
|
Z3_ADR<13> 3 0 /\1 1 FB15_3 80 I/O (b)
|
|
Z3_ADR<2> 3 0 0 2 FB15_4 (b) (b)
|
|
$OpTx$FX_DC$268 1 0 0 4 FB15_5 (b) (b)
|
|
(unused) 0 0 0 5 FB15_6 (b)
|
|
(unused) 0 0 0 5 FB15_7 (b)
|
|
(unused) 0 0 0 5 FB15_8 81 I/O I
|
|
(unused) 0 0 0 5 FB15_9 (b)
|
|
(unused) 0 0 0 5 FB15_10 82 I/O I
|
|
(unused) 0 0 0 5 FB15_11 83 I/O I
|
|
DTACK 1 0 0 4 FB15_12 85 I/O O
|
|
(unused) 0 0 \/2 3 FB15_13 (b) (b)
|
|
A<23> 7 2<- 0 0 FB15_14 86 I/O I/O
|
|
A<22> 7 2<- 0 0 FB15_15 87 I/O I/O
|
|
(unused) 0 0 /\2 3 FB15_16 (b) (b)
|
|
A<21> 7 2<- 0 0 FB15_17 88 I/O I/O
|
|
Z3_DATA<21> 6 3<- /\2 0 FB15_18 (b) (b)
|
|
|
|
Signals Used by Logic in Function Block
|
|
1: $OpTx$FX_DC$25 13: N0$BUF7/N0$BUF7_TRST 25: DQ<5>.PIN
|
|
2: $OpTx$FX_DC$325 14: A<13>.PIN 26: D<13>.PIN
|
|
3: $OpTx$FX_DC$326 15: A<14>.PIN 27: D<5>.PIN
|
|
4: A<21> 16: A<15>.PIN 28: RW
|
|
5: A<22> 17: A<21>.PIN 29: Z3_ADR<13>
|
|
6: A<23> 18: A<22>.PIN 30: Z3_DATA<21>
|
|
7: A<4> 19: A<23>.PIN 31: Z3_DATA<29>
|
|
8: FCS 20: DQ<15>.PIN 32: lan_adr
|
|
9: LAN_SM_FSM_FFd1 21: DQ<14>.PIN 33: lan_adr_sw
|
|
10: LAN_SM_FSM_FFd2 22: DQ<13>.PIN 34: lan_adr_sw/lan_adr_sw_RSTF
|
|
11: LAN_SM_FSM_FFd3 23: DQ<7>.PIN 35: lan_rdy/lan_rdy_RSTF
|
|
12: LAN_SM_FSM_FFd4 24: DQ<6>.PIN
|
|
|
|
Signal 1 2 3 4 FB
|
|
Name 0----+----0----+----0----+----0----+----0 Inputs
|
|
Z3_DATA<29> XX......XXXX.........X..XXX.X.XXX.X..... 15
|
|
Z3_ADR<13> .......X.......X.................X...... 3
|
|
Z3_ADR<2> ......XX.........................X...... 3
|
|
$OpTx$FX_DC$268 ..........XX............................ 2
|
|
DTACK ............X........................... 1
|
|
A<23> X.X..X.XXXXX...X..XX..X....XX..XX.X..... 17
|
|
A<22> X.X.X..XXXXX..X..X..X..X...XX..XX.X..... 17
|
|
A<21> X.XX...XXXXX.X..X....X..X..XX..XX.X..... 17
|
|
Z3_DATA<21> XX......XXXX.........X..XXX.XX.XX.X..... 15
|
|
0----+----1----+----2----+----3----+----4
|
|
0 0 0 0
|
|
*********************************** FB16 ***********************************
|
|
Number of function block inputs used/remaining: 37/17
|
|
Number of signals used by logic mapping into function block: 37
|
|
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
|
Name Pt Pt Pt Pt # Type Use
|
|
(unused) 0 0 \/2 3 FB16_1 (b) (b)
|
|
A<20> 7 2<- 0 0 FB16_2 91 I/O I/O
|
|
A<19> 7 2<- 0 0 FB16_3 92 I/O I/O
|
|
(unused) 0 0 /\2 3 FB16_4 (b) (b)
|
|
(unused) 0 0 \/1 4 FB16_5 93 I/O I
|
|
A<18> 7 2<- 0 0 FB16_6 94 I/O I/O
|
|
(unused) 0 0 /\1 4 FB16_7 (b) (b)
|
|
A<17> 7 2<- 0 0 FB16_8 95 I/O I/O
|
|
(unused) 0 0 /\2 3 FB16_9 (b) (b)
|
|
MTACK 0 0 \/1 4 FB16_10 96 I/O O
|
|
A<16> 7 2<- 0 0 FB16_11 97 I/O I/O
|
|
(unused) 0 0 /\1 4 FB16_12 98 I/O I
|
|
(unused) 0 0 0 5 FB16_13 (b)
|
|
(unused) 0 0 0 5 FB16_14 (b)
|
|
(unused) 0 0 0 5 FB16_15 (b)
|
|
(unused) 0 0 0 5 FB16_16 (b)
|
|
(unused) 0 0 0 5 FB16_17 (b)
|
|
(unused) 0 0 0 5 FB16_18 (b)
|
|
|
|
Signals Used by Logic in Function Block
|
|
1: $OpTx$FX_DC$25 14: A<11>.PIN 26: DQ<9>.PIN
|
|
2: $OpTx$FX_DC$326 15: A<12>.PIN 27: DQ<8>.PIN
|
|
3: A<16> 16: A<20>.PIN 28: DQ<4>.PIN
|
|
4: A<17> 17: A<16>.PIN 29: DQ<3>.PIN
|
|
5: A<18> 18: A<17>.PIN 30: DQ<2>.PIN
|
|
6: A<19> 19: A<18>.PIN 31: DQ<1>.PIN
|
|
7: A<20> 20: A<19>.PIN 32: DQ<0>.PIN
|
|
8: FCS 21: A<8>.PIN 33: RW
|
|
9: LAN_SM_FSM_FFd1 22: A<9>.PIN 34: Z3_ADR<13>
|
|
10: LAN_SM_FSM_FFd2 23: DQ<12>.PIN 35: lan_adr
|
|
11: LAN_SM_FSM_FFd3 24: DQ<11>.PIN 36: lan_adr_sw
|
|
12: LAN_SM_FSM_FFd4 25: DQ<10>.PIN 37: lan_rdy/lan_rdy_RSTF
|
|
13: A<10>.PIN
|
|
|
|
Signal 1 2 3 4 FB
|
|
Name 0----+----0----+----0----+----0----+----0 Inputs
|
|
A<20> XX....XXXXXX..XX......X....X....XXXXX... 17
|
|
A<19> XX...X.XXXXX.X.....X...X....X...XXXXX... 17
|
|
A<18> XX..X..XXXXXX.....X.....X....X..XXXXX... 17
|
|
A<17> XX.X...XXXXX.....X...X...X....X.XXXXX... 17
|
|
MTACK ........................................ 0
|
|
A<16> XXX....XXXXX....X...X.....X....XXXXXX... 17
|
|
0----+----1----+----2----+----3----+----4
|
|
0 0 0 0
|
|
******************************* Equations ********************************
|
|
|
|
********** Mapped Logic **********
|
|
|
|
|
|
$OpTx$FX_DC$23 <= (DS0 AND DS1);
|
|
|
|
|
|
$OpTx$FX_DC$24 <= (UDS AND LDS);
|
|
|
|
|
|
$OpTx$FX_DC$25 <= ($OpTx$FX_DC$23 AND $OpTx$FX_DC$24);
|
|
|
|
|
|
$OpTx$FX_DC$268 <= (NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd3);
|
|
|
|
|
|
$OpTx$FX_DC$325 <= ((NOT LAN_SM_FSM_FFd1 AND NOT BUF_LAN_SM_FSM_FFd4__$INT AND
|
|
NOT BUF_LAN_RD_S)
|
|
OR (NOT LAN_SM_FSM_FFd1 AND BUF_LAN_SM_FSM_FFd2 AND
|
|
NOT BUF_LAN_RD_S));
|
|
|
|
|
|
$OpTx$FX_DC$326 <= ((NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND
|
|
LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd1)
|
|
OR (NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND
|
|
NOT LAN_SM_FSM_FFd1 AND lan_adr AND NOT Z3_ADR(13) AND NOT $OpTx$FX_DC$23)
|
|
OR (NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND
|
|
NOT LAN_SM_FSM_FFd1 AND lan_adr AND NOT Z3_ADR(13) AND NOT $OpTx$FX_DC$24));
|
|
|
|
|
|
$OpTx$FX_DC$42 <= (NOT FCS AND NOT Z3_ADR(2) AND NOT Z3_ADR_0 AND Z3_ADR_1 AND
|
|
NOT Z3_ADR(6) AND autoconfig AND NOT RW AND NOT Z3_ADR(3) AND Z3_ADR(4) AND
|
|
NOT Z3_ADR(5) AND NOT $OpTx$FX_DC$25);
|
|
|
|
|
|
$OpTx$FX_DC$49 <= ((NOT RESET)
|
|
OR (NOT FCS AND lan_adr AND NOT RW AND NOT Z3_A_LOW AND NOT $OpTx$FX_DC$25));
|
|
|
|
|
|
$OpTx$FX_DC$61 <= ((NOT RESET)
|
|
OR (NOT FCS AND lan_adr AND NOT RW AND NOT Z3_A_LOW AND NOT $OpTx$FX_DC$25));
|
|
|
|
|
|
$OpTx$FX_DC$66 <= (lan_adr AND NOT RW AND Z3_ADR(13) AND NOT $OpTx$FX_DC$25);
|
|
|
|
FDCPE_A8: FDCPE port map (A_I(8),A(8),CLK_EXT,'0',NOT lan_rdy/lan_rdy_RSTF);
|
|
A(8) <= ((NOT lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd3 AND
|
|
A(8).PIN AND lan_adr AND NOT Z3_ADR(13) AND NOT $OpTx$FX_DC$25)
|
|
OR (lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd3 AND
|
|
lan_adr AND NOT Z3_ADR(13) AND A(16).PIN AND NOT $OpTx$FX_DC$25)
|
|
OR (A(8) AND NOT $OpTx$FX_DC$326)
|
|
OR (lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND
|
|
LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd1 AND DQ(8).PIN)
|
|
OR (NOT lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND
|
|
LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd1 AND DQ(0).PIN));
|
|
A(8) <= A_I(8) when A_OE(8) = '1' else 'Z';
|
|
A_OE(8) <= (NOT FCS AND lan_adr AND RW AND NOT $OpTx$FX_DC$25);
|
|
|
|
FDCPE_A9: FDCPE port map (A_I(9),A(9),CLK_EXT,'0',NOT lan_rdy/lan_rdy_RSTF);
|
|
A(9) <= ((lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND
|
|
LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd1 AND DQ(9).PIN)
|
|
OR (lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd3 AND
|
|
lan_adr AND NOT Z3_ADR(13) AND A(17).PIN AND NOT $OpTx$FX_DC$25)
|
|
OR (NOT lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd3 AND
|
|
lan_adr AND NOT Z3_ADR(13) AND A(9).PIN AND NOT $OpTx$FX_DC$25)
|
|
OR (A(9) AND NOT $OpTx$FX_DC$326)
|
|
OR (NOT lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND
|
|
LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd1 AND DQ(1).PIN));
|
|
A(9) <= A_I(9) when A_OE(9) = '1' else 'Z';
|
|
A_OE(9) <= (NOT FCS AND lan_adr AND RW AND NOT $OpTx$FX_DC$25);
|
|
|
|
FDCPE_A10: FDCPE port map (A_I(10),A(10),CLK_EXT,'0',NOT lan_rdy/lan_rdy_RSTF);
|
|
A(10) <= ((lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND
|
|
LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd1 AND DQ(10).PIN)
|
|
OR (lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd3 AND
|
|
lan_adr AND NOT Z3_ADR(13) AND A(18).PIN AND NOT $OpTx$FX_DC$25)
|
|
OR (NOT lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd3 AND
|
|
lan_adr AND NOT Z3_ADR(13) AND A(10).PIN AND NOT $OpTx$FX_DC$25)
|
|
OR (A(10) AND NOT $OpTx$FX_DC$326)
|
|
OR (NOT lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND
|
|
LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd1 AND DQ(2).PIN));
|
|
A(10) <= A_I(10) when A_OE(10) = '1' else 'Z';
|
|
A_OE(10) <= (NOT FCS AND lan_adr AND RW AND NOT $OpTx$FX_DC$25);
|
|
|
|
FDCPE_A11: FDCPE port map (A_I(11),A(11),CLK_EXT,'0',NOT lan_rdy/lan_rdy_RSTF);
|
|
A(11) <= ((NOT lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd3 AND
|
|
lan_adr AND NOT Z3_ADR(13) AND A(11).PIN AND NOT $OpTx$FX_DC$25)
|
|
OR (lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd3 AND
|
|
lan_adr AND NOT Z3_ADR(13) AND A(19).PIN AND NOT $OpTx$FX_DC$25)
|
|
OR (A(11) AND NOT $OpTx$FX_DC$326)
|
|
OR (lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND
|
|
LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd1 AND DQ(11).PIN)
|
|
OR (NOT lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND
|
|
LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd1 AND DQ(3).PIN));
|
|
A(11) <= A_I(11) when A_OE(11) = '1' else 'Z';
|
|
A_OE(11) <= (NOT FCS AND lan_adr AND RW AND NOT $OpTx$FX_DC$25);
|
|
|
|
FDCPE_A12: FDCPE port map (A_I(12),A(12),CLK_EXT,'0',NOT lan_rdy/lan_rdy_RSTF);
|
|
A(12) <= ((lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd3 AND
|
|
lan_adr AND NOT Z3_ADR(13) AND A(20).PIN AND NOT $OpTx$FX_DC$25)
|
|
OR (NOT lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd3 AND
|
|
lan_adr AND NOT Z3_ADR(13) AND A(12).PIN AND NOT $OpTx$FX_DC$25)
|
|
OR (A(12) AND NOT $OpTx$FX_DC$326)
|
|
OR (lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND
|
|
LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd1 AND DQ(12).PIN)
|
|
OR (NOT lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND
|
|
LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd1 AND DQ(4).PIN));
|
|
A(12) <= A_I(12) when A_OE(12) = '1' else 'Z';
|
|
A_OE(12) <= (NOT FCS AND lan_adr AND RW AND NOT $OpTx$FX_DC$25);
|
|
|
|
FDCPE_A13: FDCPE port map (A_I(13),A(13),CLK_EXT,'0',NOT lan_rdy/lan_rdy_RSTF);
|
|
A(13) <= ((lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd3 AND
|
|
lan_adr AND NOT Z3_ADR(13) AND A(21).PIN AND NOT $OpTx$FX_DC$25)
|
|
OR (NOT lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd3 AND
|
|
lan_adr AND NOT Z3_ADR(13) AND A(13).PIN AND NOT $OpTx$FX_DC$25)
|
|
OR (A(13) AND NOT $OpTx$FX_DC$326)
|
|
OR (lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND
|
|
LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd1 AND DQ(13).PIN)
|
|
OR (NOT lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND
|
|
LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd1 AND DQ(5).PIN));
|
|
A(13) <= A_I(13) when A_OE(13) = '1' else 'Z';
|
|
A_OE(13) <= (NOT FCS AND lan_adr AND RW AND NOT $OpTx$FX_DC$25);
|
|
|
|
FDCPE_A14: FDCPE port map (A_I(14),A(14),CLK_EXT,'0',NOT lan_rdy/lan_rdy_RSTF);
|
|
A(14) <= ((lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd3 AND
|
|
lan_adr AND NOT Z3_ADR(13) AND A(22).PIN AND NOT $OpTx$FX_DC$25)
|
|
OR (NOT lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd3 AND
|
|
lan_adr AND NOT Z3_ADR(13) AND A(14).PIN AND NOT $OpTx$FX_DC$25)
|
|
OR (A(14) AND NOT $OpTx$FX_DC$326)
|
|
OR (lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND
|
|
LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd1 AND DQ(14).PIN)
|
|
OR (NOT lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND
|
|
LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd1 AND DQ(6).PIN));
|
|
A(14) <= A_I(14) when A_OE(14) = '1' else 'Z';
|
|
A_OE(14) <= (NOT FCS AND lan_adr AND RW AND NOT $OpTx$FX_DC$25);
|
|
|
|
FDCPE_A15: FDCPE port map (A_I(15),A(15),CLK_EXT,'0',NOT lan_rdy/lan_rdy_RSTF);
|
|
A(15) <= ((NOT lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd3 AND
|
|
lan_adr AND A(15).PIN AND NOT Z3_ADR(13) AND NOT $OpTx$FX_DC$25)
|
|
OR (lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd3 AND
|
|
lan_adr AND NOT Z3_ADR(13) AND A(23).PIN AND NOT $OpTx$FX_DC$25)
|
|
OR (A(15) AND NOT $OpTx$FX_DC$326)
|
|
OR (lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND
|
|
LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd1 AND DQ(15).PIN)
|
|
OR (NOT lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND
|
|
LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd1 AND DQ(7).PIN));
|
|
A(15) <= A_I(15) when A_OE(15) = '1' else 'Z';
|
|
A_OE(15) <= (NOT FCS AND lan_adr AND RW AND NOT $OpTx$FX_DC$25);
|
|
|
|
FDCPE_A16: FDCPE port map (A_I(16),A(16),CLK_EXT,'0',NOT lan_rdy/lan_rdy_RSTF);
|
|
A(16) <= ((NOT lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd3 AND
|
|
lan_adr AND NOT Z3_ADR(13) AND A(16).PIN AND NOT $OpTx$FX_DC$25)
|
|
OR (lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd3 AND
|
|
A(8).PIN AND lan_adr AND NOT Z3_ADR(13) AND NOT $OpTx$FX_DC$25)
|
|
OR (A(16) AND NOT $OpTx$FX_DC$326)
|
|
OR (lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND
|
|
LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd1 AND DQ(0).PIN)
|
|
OR (NOT lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND
|
|
LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd1 AND DQ(8).PIN));
|
|
A(16) <= A_I(16) when A_OE(16) = '1' else 'Z';
|
|
A_OE(16) <= (NOT FCS AND lan_adr AND RW AND NOT $OpTx$FX_DC$25);
|
|
|
|
FDCPE_A17: FDCPE port map (A_I(17),A(17),CLK_EXT,'0',NOT lan_rdy/lan_rdy_RSTF);
|
|
A(17) <= ((lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd3 AND
|
|
lan_adr AND NOT Z3_ADR(13) AND A(9).PIN AND NOT $OpTx$FX_DC$25)
|
|
OR (NOT lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd3 AND
|
|
lan_adr AND NOT Z3_ADR(13) AND A(17).PIN AND NOT $OpTx$FX_DC$25)
|
|
OR (A(17) AND NOT $OpTx$FX_DC$326)
|
|
OR (lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND
|
|
LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd1 AND DQ(1).PIN)
|
|
OR (NOT lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND
|
|
LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd1 AND DQ(9).PIN));
|
|
A(17) <= A_I(17) when A_OE(17) = '1' else 'Z';
|
|
A_OE(17) <= (NOT FCS AND lan_adr AND RW AND NOT $OpTx$FX_DC$25);
|
|
|
|
FDCPE_A18: FDCPE port map (A_I(18),A(18),CLK_EXT,'0',NOT lan_rdy/lan_rdy_RSTF);
|
|
A(18) <= ((NOT lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd3 AND
|
|
lan_adr AND NOT Z3_ADR(13) AND A(18).PIN AND NOT $OpTx$FX_DC$25)
|
|
OR (lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd3 AND
|
|
lan_adr AND NOT Z3_ADR(13) AND A(10).PIN AND NOT $OpTx$FX_DC$25)
|
|
OR (A(18) AND NOT $OpTx$FX_DC$326)
|
|
OR (lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND
|
|
LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd1 AND DQ(2).PIN)
|
|
OR (NOT lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND
|
|
LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd1 AND DQ(10).PIN));
|
|
A(18) <= A_I(18) when A_OE(18) = '1' else 'Z';
|
|
A_OE(18) <= (NOT FCS AND lan_adr AND RW AND NOT $OpTx$FX_DC$25);
|
|
|
|
FDCPE_A19: FDCPE port map (A_I(19),A(19),CLK_EXT,'0',NOT lan_rdy/lan_rdy_RSTF);
|
|
A(19) <= ((lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd3 AND
|
|
lan_adr AND NOT Z3_ADR(13) AND A(11).PIN AND NOT $OpTx$FX_DC$25)
|
|
OR (NOT lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd3 AND
|
|
lan_adr AND NOT Z3_ADR(13) AND A(19).PIN AND NOT $OpTx$FX_DC$25)
|
|
OR (A(19) AND NOT $OpTx$FX_DC$326)
|
|
OR (lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND
|
|
LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd1 AND DQ(3).PIN)
|
|
OR (NOT lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND
|
|
LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd1 AND DQ(11).PIN));
|
|
A(19) <= A_I(19) when A_OE(19) = '1' else 'Z';
|
|
A_OE(19) <= (NOT FCS AND lan_adr AND RW AND NOT $OpTx$FX_DC$25);
|
|
|
|
FDCPE_A20: FDCPE port map (A_I(20),A(20),CLK_EXT,'0',NOT lan_rdy/lan_rdy_RSTF);
|
|
A(20) <= ((lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd3 AND
|
|
lan_adr AND NOT Z3_ADR(13) AND A(12).PIN AND NOT $OpTx$FX_DC$25)
|
|
OR (NOT lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd3 AND
|
|
lan_adr AND NOT Z3_ADR(13) AND A(20).PIN AND NOT $OpTx$FX_DC$25)
|
|
OR (A(20) AND NOT $OpTx$FX_DC$326)
|
|
OR (lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND
|
|
LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd1 AND DQ(4).PIN)
|
|
OR (NOT lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND
|
|
LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd1 AND DQ(12).PIN));
|
|
A(20) <= A_I(20) when A_OE(20) = '1' else 'Z';
|
|
A_OE(20) <= (NOT FCS AND lan_adr AND RW AND NOT $OpTx$FX_DC$25);
|
|
|
|
FDCPE_A21: FDCPE port map (A_I(21),A(21),CLK_EXT,'0',NOT lan_rdy/lan_rdy_RSTF);
|
|
A(21) <= ((lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd3 AND
|
|
lan_adr AND NOT Z3_ADR(13) AND A(13).PIN AND NOT $OpTx$FX_DC$25)
|
|
OR (NOT lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd3 AND
|
|
lan_adr AND NOT Z3_ADR(13) AND A(21).PIN AND NOT $OpTx$FX_DC$25)
|
|
OR (A(21) AND NOT $OpTx$FX_DC$326)
|
|
OR (lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND
|
|
LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd1 AND DQ(5).PIN)
|
|
OR (NOT lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND
|
|
LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd1 AND DQ(13).PIN));
|
|
A(21) <= A_I(21) when A_OE(21) = '1' else 'Z';
|
|
A_OE(21) <= (NOT FCS AND lan_adr AND RW AND NOT $OpTx$FX_DC$25);
|
|
|
|
FDCPE_A22: FDCPE port map (A_I(22),A(22),CLK_EXT,'0',NOT lan_rdy/lan_rdy_RSTF);
|
|
A(22) <= ((lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd3 AND
|
|
lan_adr AND NOT Z3_ADR(13) AND A(14).PIN AND NOT $OpTx$FX_DC$25)
|
|
OR (NOT lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd3 AND
|
|
lan_adr AND NOT Z3_ADR(13) AND A(22).PIN AND NOT $OpTx$FX_DC$25)
|
|
OR (A(22) AND NOT $OpTx$FX_DC$326)
|
|
OR (lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND
|
|
LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd1 AND DQ(6).PIN)
|
|
OR (NOT lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND
|
|
LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd1 AND DQ(14).PIN));
|
|
A(22) <= A_I(22) when A_OE(22) = '1' else 'Z';
|
|
A_OE(22) <= (NOT FCS AND lan_adr AND RW AND NOT $OpTx$FX_DC$25);
|
|
|
|
FDCPE_A23: FDCPE port map (A_I(23),A(23),CLK_EXT,'0',NOT lan_rdy/lan_rdy_RSTF);
|
|
A(23) <= ((lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd3 AND
|
|
lan_adr AND A(15).PIN AND NOT Z3_ADR(13) AND NOT $OpTx$FX_DC$25)
|
|
OR (NOT lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd3 AND
|
|
lan_adr AND NOT Z3_ADR(13) AND A(23).PIN AND NOT $OpTx$FX_DC$25)
|
|
OR (A(23) AND NOT $OpTx$FX_DC$326)
|
|
OR (lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND
|
|
LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd1 AND DQ(7).PIN)
|
|
OR (NOT lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND
|
|
LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd1 AND DQ(15).PIN));
|
|
A(23) <= A_I(23) when A_OE(23) = '1' else 'Z';
|
|
A_OE(23) <= (NOT FCS AND lan_adr AND RW AND NOT $OpTx$FX_DC$25);
|
|
|
|
FTCPE_AUTO_CONFIG_DONE_CYCLE: FTCPE port map (AUTO_CONFIG_DONE_CYCLE,AUTO_CONFIG_DONE_CYCLE_T,CLK_EXT,NOT RESET,'0');
|
|
AUTO_CONFIG_DONE_CYCLE_T <= (NOT AUTO_CONFIG_DONE_CYCLE AND NOT FCS AND NOT Z3_ADR(2) AND
|
|
Z3_ADR_1 AND NOT Z3_ADR(6) AND autoconfig AND NOT RW AND NOT Z3_ADR(3) AND
|
|
Z3_ADR(4) AND NOT Z3_ADR(5) AND NOT $OpTx$FX_DC$25);
|
|
|
|
|
|
A_LAN(0) <= NOT ((RESET AND NOT Z3_A_LOW));
|
|
|
|
|
|
A_LAN(1) <= NOT ((RESET AND NOT Z3_ADR_0));
|
|
|
|
|
|
A_LAN(2) <= NOT ((RESET AND NOT Z3_ADR_1));
|
|
|
|
|
|
A_LAN(3) <= ((RESET AND Z3_ADR(2))
|
|
OR (NOT RESET AND LAN_A_INIT(3)));
|
|
|
|
|
|
A_LAN(4) <= NOT ((RESET AND NOT Z3_ADR(3)));
|
|
|
|
|
|
A_LAN(5) <= NOT ((RESET AND NOT Z3_ADR(4)));
|
|
|
|
|
|
A_LAN(6) <= ((RESET AND Z3_ADR(5))
|
|
OR (NOT RESET AND LAN_A_INIT(6)));
|
|
|
|
|
|
A_LAN(7) <= NOT ((RESET AND NOT Z3_ADR(6)));
|
|
|
|
|
|
A_LAN(8) <= NOT ((RESET AND NOT Z3_ADR(7)));
|
|
|
|
|
|
A_LAN(9) <= NOT ((RESET AND NOT Z3_ADR(8)));
|
|
|
|
|
|
A_LAN(10) <= NOT ((RESET AND NOT Z3_ADR(9)));
|
|
|
|
|
|
A_LAN(11) <= NOT ((RESET AND NOT Z3_ADR(10)));
|
|
|
|
|
|
A_LAN(12) <= NOT ((RESET AND NOT Z3_ADR(11)));
|
|
|
|
|
|
A_LAN(13) <= NOT ((RESET AND NOT Z3_ADR(12)));
|
|
|
|
|
|
BUF_LAN_D_INIT(1)__$INT <= ((LAN_RST_SM_FSM_FFd3 AND NOT LAN_RST_SM_FSM_FFd1)
|
|
OR (NOT LAN_RST_SM_FSM_FFd3 AND LAN_RST_SM_FSM_FFd2));
|
|
|
|
|
|
BUF_LAN_RD_S <= ((LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd1)
|
|
OR (LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3 AND
|
|
NOT LAN_SM_FSM_FFd1));
|
|
|
|
|
|
BUF_LAN_SM_FSM_FFd2 <= ((LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2)
|
|
OR (LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3)
|
|
OR (LAN_SM_FSM_FFd2 AND $OpTx$FX_DC$23)
|
|
OR (NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd3 AND lan_adr AND
|
|
NOT Z3_ADR(13) AND NOT $OpTx$FX_DC$24));
|
|
|
|
|
|
BUF_LAN_SM_FSM_FFd4__$INT <= ((NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND
|
|
NOT LAN_SM_FSM_FFd1 AND $OpTx$FX_DC$23 AND $OpTx$FX_DC$24)
|
|
OR (LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd3)
|
|
OR (NOT LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd3)
|
|
OR (LAN_SM_FSM_FFd3 AND $OpTx$FX_DC$23)
|
|
OR (NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND
|
|
NOT LAN_SM_FSM_FFd1 AND NOT lan_adr)
|
|
OR (NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND
|
|
NOT LAN_SM_FSM_FFd1 AND Z3_ADR(13)));
|
|
|
|
|
|
BUF_autoconfig <= (D(15).PIN AND D(10).PIN AND D(11).PIN AND D(12).PIN AND
|
|
D(13).PIN AND D(14).PIN AND D(8).PIN AND D(9).PIN AND Z3 AND
|
|
NOT A(18).PIN AND NOT A(17).PIN AND NOT A(16).PIN AND NOT A(22).PIN AND NOT A(21).PIN AND
|
|
NOT A(19).PIN AND NOT A(20).PIN AND NOT A(23).PIN AND NOT CFIN AND CFOUT);
|
|
|
|
FDCPE_CFOUT: FDCPE port map (CFOUT,CFOUT_D,CLK_EXT,'0',NOT RESET,FCS);
|
|
CFOUT_D <= (NOT AUTO_CONFIG_DONE_CYCLE AND AUTOBOOT_OFF);
|
|
|
|
|
|
CP_CS <= '1';
|
|
|
|
|
|
CP_RD <= '1';
|
|
|
|
|
|
CP_WE <= '1';
|
|
|
|
|
|
D_I(0) <= NOT ((NOT Z3_DATA(16) AND Z3_DATA(7)/Z3_DATA(7)_TRST));
|
|
D(0) <= D_I(0) when D_OE(0) = '1' else 'Z';
|
|
D_OE(0) <= (RW AND NOT SLAVE AND NOT $OpTx$FX_DC$25);
|
|
|
|
|
|
D_I(1) <= NOT ((NOT Z3_DATA(17) AND Z3_DATA(7)/Z3_DATA(7)_TRST));
|
|
D(1) <= D_I(1) when D_OE(1) = '1' else 'Z';
|
|
D_OE(1) <= (RW AND NOT SLAVE AND NOT $OpTx$FX_DC$25);
|
|
|
|
|
|
D_I(2) <= NOT ((NOT Z3_DATA(18) AND Z3_DATA(7)/Z3_DATA(7)_TRST));
|
|
D(2) <= D_I(2) when D_OE(2) = '1' else 'Z';
|
|
D_OE(2) <= (RW AND NOT SLAVE AND NOT $OpTx$FX_DC$25);
|
|
|
|
|
|
D_I(3) <= NOT ((NOT Z3_DATA(19) AND Z3_DATA(7)/Z3_DATA(7)_TRST));
|
|
D(3) <= D_I(3) when D_OE(3) = '1' else 'Z';
|
|
D_OE(3) <= (RW AND NOT SLAVE AND NOT $OpTx$FX_DC$25);
|
|
|
|
|
|
D_I(4) <= NOT ((NOT Z3_DATA(20) AND Z3_DATA(7)/Z3_DATA(7)_TRST));
|
|
D(4) <= D_I(4) when D_OE(4) = '1' else 'Z';
|
|
D_OE(4) <= (RW AND NOT SLAVE AND NOT $OpTx$FX_DC$25);
|
|
|
|
|
|
D_I(5) <= NOT ((NOT Z3_DATA(21) AND Z3_DATA(7)/Z3_DATA(7)_TRST));
|
|
D(5) <= D_I(5) when D_OE(5) = '1' else 'Z';
|
|
D_OE(5) <= (RW AND NOT SLAVE AND NOT $OpTx$FX_DC$25);
|
|
|
|
|
|
D_I(6) <= NOT ((NOT Z3_DATA(22) AND Z3_DATA(7)/Z3_DATA(7)_TRST));
|
|
D(6) <= D_I(6) when D_OE(6) = '1' else 'Z';
|
|
D_OE(6) <= (RW AND NOT SLAVE AND NOT $OpTx$FX_DC$25);
|
|
|
|
|
|
D_I(7) <= NOT ((NOT Z3_DATA(23) AND Z3_DATA(7)/Z3_DATA(7)_TRST));
|
|
D(7) <= D_I(7) when D_OE(7) = '1' else 'Z';
|
|
D_OE(7) <= (RW AND NOT SLAVE AND NOT $OpTx$FX_DC$25);
|
|
|
|
|
|
D_I(8) <= ((Z3_DATA(24) AND Z3_DATA(7)/Z3_DATA(7)_TRST)
|
|
OR (Dout1(0) AND NOT Z3_DATA(7)/Z3_DATA(7)_TRST));
|
|
D(8) <= D_I(8) when D_OE(8) = '1' else 'Z';
|
|
D_OE(8) <= (RW AND NOT SLAVE AND NOT $OpTx$FX_DC$25);
|
|
|
|
|
|
D_I(9) <= ((Z3_DATA(25) AND Z3_DATA(7)/Z3_DATA(7)_TRST)
|
|
OR (Dout1(1) AND NOT Z3_DATA(7)/Z3_DATA(7)_TRST));
|
|
D(9) <= D_I(9) when D_OE(9) = '1' else 'Z';
|
|
D_OE(9) <= (RW AND NOT SLAVE AND NOT $OpTx$FX_DC$25);
|
|
|
|
|
|
D_I(10) <= ((Z3_DATA(26) AND Z3_DATA(7)/Z3_DATA(7)_TRST)
|
|
OR (Dout1(2) AND NOT Z3_DATA(7)/Z3_DATA(7)_TRST));
|
|
D(10) <= D_I(10) when D_OE(10) = '1' else 'Z';
|
|
D_OE(10) <= (RW AND NOT SLAVE AND NOT $OpTx$FX_DC$25);
|
|
|
|
|
|
D_I(11) <= ((Z3_DATA(27) AND Z3_DATA(7)/Z3_DATA(7)_TRST)
|
|
OR (Dout1(3) AND NOT Z3_DATA(7)/Z3_DATA(7)_TRST));
|
|
D(11) <= D_I(11) when D_OE(11) = '1' else 'Z';
|
|
D_OE(11) <= (RW AND NOT SLAVE AND NOT $OpTx$FX_DC$25);
|
|
|
|
|
|
D_I(12) <= ((Z3_DATA(28) AND Z3_DATA(7)/Z3_DATA(7)_TRST)
|
|
OR (Dout1(4) AND NOT Z3_DATA(7)/Z3_DATA(7)_TRST));
|
|
D(12) <= D_I(12) when D_OE(12) = '1' else 'Z';
|
|
D_OE(12) <= (RW AND NOT SLAVE AND NOT $OpTx$FX_DC$25);
|
|
|
|
|
|
D_I(13) <= ((Z3_DATA(29) AND Z3_DATA(7)/Z3_DATA(7)_TRST)
|
|
OR (Dout1(5) AND NOT Z3_DATA(7)/Z3_DATA(7)_TRST));
|
|
D(13) <= D_I(13) when D_OE(13) = '1' else 'Z';
|
|
D_OE(13) <= (RW AND NOT SLAVE AND NOT $OpTx$FX_DC$25);
|
|
|
|
|
|
D_I(14) <= ((Z3_DATA(30) AND Z3_DATA(7)/Z3_DATA(7)_TRST)
|
|
OR (Dout1(6) AND NOT Z3_DATA(7)/Z3_DATA(7)_TRST));
|
|
D(14) <= D_I(14) when D_OE(14) = '1' else 'Z';
|
|
D_OE(14) <= (RW AND NOT SLAVE AND NOT $OpTx$FX_DC$25);
|
|
|
|
|
|
D_I(15) <= ((Z3_DATA(31) AND Z3_DATA(7)/Z3_DATA(7)_TRST)
|
|
OR (Dout1(7) AND NOT Z3_DATA(7)/Z3_DATA(7)_TRST));
|
|
D(15) <= D_I(15) when D_OE(15) = '1' else 'Z';
|
|
D_OE(15) <= (RW AND NOT SLAVE AND NOT $OpTx$FX_DC$25);
|
|
|
|
|
|
DQ_I(0) <= ((A(8) AND NOT $OpTx$FX_DC$49)
|
|
OR (RESET AND lan_adr AND NOT RW AND NOT Z3_A_LOW AND Z3_DATA(16) AND
|
|
lan_rdy/lan_rdy_RSTF AND NOT $OpTx$FX_DC$25));
|
|
DQ(0) <= DQ_I(0) when DQ_OE(0) = '1' else 'Z';
|
|
DQ_OE(0) <= DQ_14_IOBUFE/DQ_14_IOBUFE_TRST;
|
|
|
|
|
|
DQ_I(1) <= ((A(9) AND NOT $OpTx$FX_DC$61)
|
|
OR (NOT RESET AND LAN_D_INIT(1))
|
|
OR (RESET AND lan_adr AND NOT RW AND NOT Z3_A_LOW AND Z3_DATA(17) AND
|
|
lan_rdy/lan_rdy_RSTF AND NOT $OpTx$FX_DC$25));
|
|
DQ(1) <= DQ_I(1) when DQ_OE(1) = '1' else 'Z';
|
|
DQ_OE(1) <= DQ_14_IOBUFE/DQ_14_IOBUFE_TRST;
|
|
|
|
|
|
DQ_I(2) <= ((A(10) AND NOT $OpTx$FX_DC$49)
|
|
OR (RESET AND lan_adr AND NOT RW AND NOT Z3_A_LOW AND Z3_DATA(18) AND
|
|
lan_rdy/lan_rdy_RSTF AND NOT $OpTx$FX_DC$25));
|
|
DQ(2) <= DQ_I(2) when DQ_OE(2) = '1' else 'Z';
|
|
DQ_OE(2) <= DQ_11_IOBUFE/DQ_11_IOBUFE_TRST;
|
|
|
|
|
|
DQ_I(3) <= ((A(11) AND NOT $OpTx$FX_DC$49)
|
|
OR (RESET AND lan_adr AND NOT RW AND NOT Z3_A_LOW AND Z3_DATA(19) AND
|
|
lan_rdy/lan_rdy_RSTF AND NOT $OpTx$FX_DC$25));
|
|
DQ(3) <= DQ_I(3) when DQ_OE(3) = '1' else 'Z';
|
|
DQ_OE(3) <= DQ_14_IOBUFE/DQ_14_IOBUFE_TRST;
|
|
|
|
|
|
DQ_I(4) <= ((A(12) AND NOT $OpTx$FX_DC$61)
|
|
OR (NOT RESET AND LAN_D_INIT(1))
|
|
OR (RESET AND lan_adr AND NOT RW AND NOT Z3_A_LOW AND Z3_DATA(20) AND
|
|
lan_rdy/lan_rdy_RSTF AND NOT $OpTx$FX_DC$25));
|
|
DQ(4) <= DQ_I(4) when DQ_OE(4) = '1' else 'Z';
|
|
DQ_OE(4) <= DQ_14_IOBUFE/DQ_14_IOBUFE_TRST;
|
|
|
|
|
|
DQ_I(5) <= ((A(13) AND NOT $OpTx$FX_DC$49)
|
|
OR (RESET AND lan_adr AND NOT RW AND NOT Z3_A_LOW AND Z3_DATA(21) AND
|
|
lan_rdy/lan_rdy_RSTF AND NOT $OpTx$FX_DC$25));
|
|
DQ(5) <= DQ_I(5) when DQ_OE(5) = '1' else 'Z';
|
|
DQ_OE(5) <= DQ_14_IOBUFE/DQ_14_IOBUFE_TRST;
|
|
|
|
|
|
DQ_I(6) <= ((A(14) AND NOT $OpTx$FX_DC$49)
|
|
OR (RESET AND lan_adr AND NOT RW AND NOT Z3_A_LOW AND Z3_DATA(22) AND
|
|
lan_rdy/lan_rdy_RSTF AND NOT $OpTx$FX_DC$25));
|
|
DQ(6) <= DQ_I(6) when DQ_OE(6) = '1' else 'Z';
|
|
DQ_OE(6) <= DQ_14_IOBUFE/DQ_14_IOBUFE_TRST;
|
|
|
|
|
|
DQ_I(7) <= ((A(15) AND NOT $OpTx$FX_DC$49)
|
|
OR (RESET AND lan_adr AND NOT RW AND NOT Z3_A_LOW AND Z3_DATA(23) AND
|
|
lan_rdy/lan_rdy_RSTF AND NOT $OpTx$FX_DC$25));
|
|
DQ(7) <= DQ_I(7) when DQ_OE(7) = '1' else 'Z';
|
|
DQ_OE(7) <= DQ_14_IOBUFE/DQ_14_IOBUFE_TRST;
|
|
|
|
|
|
DQ_I(8) <= ((A(16) AND NOT $OpTx$FX_DC$49)
|
|
OR (RESET AND lan_adr AND NOT RW AND NOT Z3_A_LOW AND Z3_DATA(24) AND
|
|
lan_rdy/lan_rdy_RSTF AND NOT $OpTx$FX_DC$25));
|
|
DQ(8) <= DQ_I(8) when DQ_OE(8) = '1' else 'Z';
|
|
DQ_OE(8) <= DQ_11_IOBUFE/DQ_11_IOBUFE_TRST;
|
|
|
|
|
|
DQ_I(9) <= ((A(17) AND NOT $OpTx$FX_DC$61)
|
|
OR (NOT RESET AND LAN_D_INIT(9))
|
|
OR (RESET AND lan_adr AND NOT RW AND NOT Z3_A_LOW AND Z3_DATA(25) AND
|
|
lan_rdy/lan_rdy_RSTF AND NOT $OpTx$FX_DC$25));
|
|
DQ(9) <= DQ_I(9) when DQ_OE(9) = '1' else 'Z';
|
|
DQ_OE(9) <= DQ_14_IOBUFE/DQ_14_IOBUFE_TRST;
|
|
|
|
|
|
DQ_I(10) <= ((A(18) AND NOT $OpTx$FX_DC$61)
|
|
OR (NOT RESET AND LAN_D_INIT(10))
|
|
OR (RESET AND lan_adr AND NOT RW AND NOT Z3_A_LOW AND Z3_DATA(26) AND
|
|
lan_rdy/lan_rdy_RSTF AND NOT $OpTx$FX_DC$25));
|
|
DQ(10) <= DQ_I(10) when DQ_OE(10) = '1' else 'Z';
|
|
DQ_OE(10) <= DQ_14_IOBUFE/DQ_14_IOBUFE_TRST;
|
|
|
|
|
|
DQ_I(11) <= ((A(19) AND NOT $OpTx$FX_DC$61)
|
|
OR (NOT RESET AND LAN_D_INIT(10))
|
|
OR (RESET AND lan_adr AND NOT RW AND NOT Z3_A_LOW AND Z3_DATA(27) AND
|
|
lan_rdy/lan_rdy_RSTF AND NOT $OpTx$FX_DC$25));
|
|
DQ(11) <= DQ_I(11) when DQ_OE(11) = '1' else 'Z';
|
|
DQ_OE(11) <= DQ_11_IOBUFE/DQ_11_IOBUFE_TRST;
|
|
|
|
|
|
DQ_I(12) <= ((A(20) AND NOT $OpTx$FX_DC$49)
|
|
OR (RESET AND lan_adr AND NOT RW AND NOT Z3_A_LOW AND Z3_DATA(28) AND
|
|
lan_rdy/lan_rdy_RSTF AND NOT $OpTx$FX_DC$25));
|
|
DQ(12) <= DQ_I(12) when DQ_OE(12) = '1' else 'Z';
|
|
DQ_OE(12) <= DQ_14_IOBUFE/DQ_14_IOBUFE_TRST;
|
|
|
|
|
|
DQ_I(13) <= ((A(21) AND NOT $OpTx$FX_DC$49)
|
|
OR (RESET AND lan_adr AND NOT RW AND NOT Z3_A_LOW AND Z3_DATA(29) AND
|
|
lan_rdy/lan_rdy_RSTF AND NOT $OpTx$FX_DC$25));
|
|
DQ(13) <= DQ_I(13) when DQ_OE(13) = '1' else 'Z';
|
|
DQ_OE(13) <= DQ_11_IOBUFE/DQ_11_IOBUFE_TRST;
|
|
|
|
|
|
DQ_I(14) <= ((A(22) AND NOT $OpTx$FX_DC$49)
|
|
OR (RESET AND lan_adr AND NOT RW AND NOT Z3_A_LOW AND Z3_DATA(30) AND
|
|
lan_rdy/lan_rdy_RSTF AND NOT $OpTx$FX_DC$25));
|
|
DQ(14) <= DQ_I(14) when DQ_OE(14) = '1' else 'Z';
|
|
DQ_OE(14) <= DQ_14_IOBUFE/DQ_14_IOBUFE_TRST;
|
|
|
|
|
|
DQ_I(15) <= ((A(23) AND NOT $OpTx$FX_DC$49)
|
|
OR (RESET AND lan_adr AND NOT RW AND NOT Z3_A_LOW AND Z3_DATA(31) AND
|
|
lan_rdy/lan_rdy_RSTF AND NOT $OpTx$FX_DC$25));
|
|
DQ(15) <= DQ_I(15) when DQ_OE(15) = '1' else 'Z';
|
|
DQ_OE(15) <= DQ_14_IOBUFE/DQ_14_IOBUFE_TRST;
|
|
|
|
|
|
DQ_11_IOBUFE/DQ_11_IOBUFE_TRST <= ((NOT RESET)
|
|
OR (lan_adr AND NOT RW AND lan_rdy/lan_rdy_RSTF AND
|
|
NOT $OpTx$FX_DC$25));
|
|
|
|
|
|
DQ_14_IOBUFE/DQ_14_IOBUFE_TRST <= ((NOT RESET)
|
|
OR (lan_adr AND NOT RW AND lan_rdy/lan_rdy_RSTF AND
|
|
NOT $OpTx$FX_DC$25));
|
|
|
|
|
|
DTACK_I <= '0';
|
|
DTACK <= DTACK_I when DTACK_OE = '1' else 'Z';
|
|
DTACK_OE <= N0$BUF7/N0$BUF7_TRST;
|
|
|
|
FDCPE_Dout10: FDCPE port map (Dout1(0),Dout1_D(0),CLK_EXT,'0',NOT RESET);
|
|
Dout1_D(0) <= (NOT FCS AND NOT Z3_ADR(2) AND Z3_ADR_0 AND NOT Z3_ADR_1 AND
|
|
autoconfig AND NOT Z3_ADR(3) AND NOT Z3_ADR(4) AND NOT Z3_ADR(5) AND
|
|
NOT $OpTx$FX_DC$25);
|
|
|
|
FDCPE_Dout11: FDCPE port map (Dout1(1),Dout1_D(1),CLK_EXT,'0',NOT RESET);
|
|
Dout1_D(1) <= ((NOT FCS AND NOT Z3_ADR(2) AND NOT Z3_ADR_0 AND autoconfig AND
|
|
NOT Z3_ADR(3) AND NOT Z3_ADR(4) AND NOT Z3_ADR(5) AND NOT $OpTx$FX_DC$25)
|
|
OR (NOT FCS AND NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND autoconfig AND
|
|
NOT Z3_ADR(3) AND NOT Z3_ADR(4) AND NOT Z3_ADR(5) AND NOT $OpTx$FX_DC$25)
|
|
OR (NOT FCS AND NOT Z3_ADR_0 AND NOT Z3_ADR_1 AND autoconfig AND
|
|
NOT Z3_ADR(3) AND NOT Z3_ADR(4) AND NOT Z3_ADR(5) AND NOT $OpTx$FX_DC$25));
|
|
|
|
FDCPE_Dout12: FDCPE port map (Dout1(2),Dout1_D(2),CLK_EXT,'0',NOT RESET);
|
|
Dout1_D(2) <= ((NOT FCS AND Z3_ADR(2) AND Z3_ADR_0 AND NOT Z3_ADR_1 AND
|
|
autoconfig AND NOT Z3_ADR(3) AND NOT Z3_ADR(4) AND NOT Z3_ADR(5) AND
|
|
NOT $OpTx$FX_DC$25)
|
|
OR (NOT FCS AND NOT Z3_ADR(2) AND NOT Z3_ADR_0 AND NOT Z3_ADR_1 AND
|
|
autoconfig AND NOT Z3_ADR(3) AND NOT Z3_ADR(4) AND NOT Z3_ADR(5) AND
|
|
NOT $OpTx$FX_DC$25));
|
|
|
|
FDCPE_Dout13: FDCPE port map (Dout1(3),Dout1_D(3),CLK_EXT,'0',NOT RESET);
|
|
Dout1_D(3) <= (NOT FCS AND NOT Z3_ADR_1 AND autoconfig AND NOT Z3_ADR(3) AND
|
|
NOT Z3_ADR(4) AND NOT Z3_ADR(5) AND NOT $OpTx$FX_DC$25);
|
|
|
|
FDCPE_Dout14: FDCPE port map (Dout1(4),Dout1_D(4),CLK_EXT,'0',NOT RESET);
|
|
Dout1_D(4) <= ((NOT FCS AND NOT Z3_ADR(2) AND Z3_ADR_0 AND NOT Z3_ADR_1 AND
|
|
autoconfig AND NOT Z3_ADR(3) AND NOT Z3_ADR(4) AND NOT Z3_ADR(5) AND
|
|
NOT $OpTx$FX_DC$25)
|
|
OR (NOT FCS AND NOT Z3_ADR(2) AND NOT Z3_ADR_0 AND NOT Z3_ADR(6) AND
|
|
autoconfig AND NOT Z3_ADR(3) AND NOT Z3_ADR(4) AND NOT Z3_ADR(5) AND
|
|
NOT $OpTx$FX_DC$25)
|
|
OR (NOT FCS AND Z3_ADR_0 AND NOT Z3_ADR_1 AND NOT Z3_ADR(6) AND
|
|
autoconfig AND NOT Z3_ADR(3) AND NOT Z3_ADR(4) AND NOT Z3_ADR(5) AND
|
|
NOT $OpTx$FX_DC$25));
|
|
|
|
FDCPE_Dout15: FDCPE port map (Dout1(5),Dout1_D(5),CLK_EXT,'0',NOT RESET);
|
|
Dout1_D(5) <= ((NOT FCS AND NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND autoconfig AND
|
|
NOT Z3_ADR(3) AND NOT Z3_ADR(4) AND NOT Z3_ADR(5) AND NOT $OpTx$FX_DC$25)
|
|
OR (NOT FCS AND NOT Z3_ADR(2) AND NOT Z3_ADR_0 AND Z3_ADR(6) AND
|
|
autoconfig AND NOT Z3_ADR(3) AND NOT Z3_ADR(4) AND NOT Z3_ADR(5) AND
|
|
NOT $OpTx$FX_DC$25)
|
|
OR (NOT FCS AND NOT Z3_ADR_0 AND NOT Z3_ADR_1 AND Z3_ADR(6) AND
|
|
autoconfig AND NOT Z3_ADR(3) AND NOT Z3_ADR(4) AND NOT Z3_ADR(5) AND
|
|
NOT $OpTx$FX_DC$25));
|
|
|
|
FDCPE_Dout16: FDCPE port map (Dout1(6),Dout1_D(6),CLK_EXT,'0',NOT RESET);
|
|
Dout1_D(6) <= ((NOT FCS AND NOT Z3_ADR(2) AND NOT Z3_ADR_0 AND NOT Z3_ADR_1 AND
|
|
autoconfig AND NOT Z3_ADR(3) AND NOT Z3_ADR(4) AND NOT Z3_ADR(5) AND
|
|
NOT $OpTx$FX_DC$25)
|
|
OR (NOT FCS AND NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND NOT Z3_ADR(6) AND
|
|
autoconfig AND NOT Z3_ADR(3) AND NOT Z3_ADR(4) AND NOT Z3_ADR(5) AND
|
|
NOT $OpTx$FX_DC$25)
|
|
OR (NOT FCS AND Z3_ADR(2) AND Z3_ADR_0 AND NOT Z3_ADR_1 AND
|
|
Z3_ADR(6) AND autoconfig AND NOT Z3_ADR(3) AND NOT Z3_ADR(4) AND NOT Z3_ADR(5) AND
|
|
NOT $OpTx$FX_DC$25));
|
|
|
|
FDCPE_Dout17: FDCPE port map (Dout1(7),Dout1_D(7),CLK_EXT,'0',NOT RESET);
|
|
Dout1_D(7) <= (NOT FCS AND NOT Z3_ADR_1 AND Z3_ADR(6) AND autoconfig AND
|
|
NOT Z3_ADR(3) AND NOT Z3_ADR(4) AND NOT Z3_ADR(5) AND NOT $OpTx$FX_DC$25);
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
IDE_A(0) <= '1';
|
|
|
|
|
|
IDE_A(1) <= '1';
|
|
|
|
|
|
IDE_A(2) <= '1';
|
|
|
|
|
|
IDE_CS(0) <= '1';
|
|
|
|
|
|
IDE_CS(1) <= '1';
|
|
|
|
|
|
IDE_R <= '1';
|
|
|
|
|
|
IDE_W <= '1';
|
|
|
|
|
|
INT_OUT_I <= '0';
|
|
INT_OUT <= INT_OUT_I when INT_OUT_OE = '1' else 'Z';
|
|
INT_OUT_OE <= (LAN_INT_ENABLE AND NOT LAN_IRQ_OUT);
|
|
|
|
FDCPE_LAN_A_INIT3: FDCPE port map (LAN_A_INIT(3),'0',CLK_EXT,'0',RESET);
|
|
|
|
FDCPE_LAN_A_INIT6: FDCPE port map (LAN_A_INIT(6),BUF_LAN_D_INIT(1)__$INT,CLK_EXT,'0',RESET);
|
|
|
|
FDCPE_LAN_BASEADR0: FDCPE port map (LAN_BASEADR(0),LAN_BASEADR_D(0),CLK_EXT,'0',NOT RESET);
|
|
LAN_BASEADR_D(0) <= ((D(0).PIN AND $OpTx$FX_DC$42)
|
|
OR (LAN_BASEADR(0) AND NOT $OpTx$FX_DC$42));
|
|
|
|
FDCPE_LAN_BASEADR1: FDCPE port map (LAN_BASEADR(1),LAN_BASEADR_D(1),CLK_EXT,'0',NOT RESET);
|
|
LAN_BASEADR_D(1) <= ((D(1).PIN AND $OpTx$FX_DC$42)
|
|
OR (LAN_BASEADR(1) AND NOT $OpTx$FX_DC$42));
|
|
|
|
FDCPE_LAN_BASEADR2: FDCPE port map (LAN_BASEADR(2),LAN_BASEADR_D(2),CLK_EXT,'0',NOT RESET);
|
|
LAN_BASEADR_D(2) <= ((D(2).PIN AND $OpTx$FX_DC$42)
|
|
OR (LAN_BASEADR(2) AND NOT $OpTx$FX_DC$42));
|
|
|
|
FDCPE_LAN_BASEADR3: FDCPE port map (LAN_BASEADR(3),LAN_BASEADR_D(3),CLK_EXT,'0',NOT RESET);
|
|
LAN_BASEADR_D(3) <= ((D(3).PIN AND $OpTx$FX_DC$42)
|
|
OR (LAN_BASEADR(3) AND NOT $OpTx$FX_DC$42));
|
|
|
|
FDCPE_LAN_BASEADR4: FDCPE port map (LAN_BASEADR(4),LAN_BASEADR_D(4),CLK_EXT,'0',NOT RESET);
|
|
LAN_BASEADR_D(4) <= ((D(4).PIN AND $OpTx$FX_DC$42)
|
|
OR (LAN_BASEADR(4) AND NOT $OpTx$FX_DC$42));
|
|
|
|
FDCPE_LAN_BASEADR5: FDCPE port map (LAN_BASEADR(5),LAN_BASEADR_D(5),CLK_EXT,'0',NOT RESET);
|
|
LAN_BASEADR_D(5) <= ((D(5).PIN AND $OpTx$FX_DC$42)
|
|
OR (LAN_BASEADR(5) AND NOT $OpTx$FX_DC$42));
|
|
|
|
FDCPE_LAN_BASEADR6: FDCPE port map (LAN_BASEADR(6),LAN_BASEADR_D(6),CLK_EXT,'0',NOT RESET);
|
|
LAN_BASEADR_D(6) <= ((D(6).PIN AND $OpTx$FX_DC$42)
|
|
OR (LAN_BASEADR(6) AND NOT $OpTx$FX_DC$42));
|
|
|
|
FDCPE_LAN_BASEADR7: FDCPE port map (LAN_BASEADR(7),LAN_BASEADR_D(7),CLK_EXT,'0',NOT RESET);
|
|
LAN_BASEADR_D(7) <= ((D(7).PIN AND $OpTx$FX_DC$42)
|
|
OR (LAN_BASEADR(7) AND NOT $OpTx$FX_DC$42));
|
|
|
|
FDCPE_LAN_BASEADR8: FDCPE port map (LAN_BASEADR(8),LAN_BASEADR_D(8),CLK_EXT,'0',NOT RESET);
|
|
LAN_BASEADR_D(8) <= ((D(8).PIN AND $OpTx$FX_DC$42)
|
|
OR (LAN_BASEADR(8) AND NOT $OpTx$FX_DC$42));
|
|
|
|
FDCPE_LAN_BASEADR9: FDCPE port map (LAN_BASEADR(9),LAN_BASEADR_D(9),CLK_EXT,'0',NOT RESET);
|
|
LAN_BASEADR_D(9) <= ((D(9).PIN AND $OpTx$FX_DC$42)
|
|
OR (LAN_BASEADR(9) AND NOT $OpTx$FX_DC$42));
|
|
|
|
FDCPE_LAN_BASEADR10: FDCPE port map (LAN_BASEADR(10),LAN_BASEADR_D(10),CLK_EXT,'0',NOT RESET);
|
|
LAN_BASEADR_D(10) <= ((D(10).PIN AND $OpTx$FX_DC$42)
|
|
OR (LAN_BASEADR(10) AND NOT $OpTx$FX_DC$42));
|
|
|
|
FDCPE_LAN_BASEADR11: FDCPE port map (LAN_BASEADR(11),LAN_BASEADR_D(11),CLK_EXT,'0',NOT RESET);
|
|
LAN_BASEADR_D(11) <= ((D(11).PIN AND $OpTx$FX_DC$42)
|
|
OR (LAN_BASEADR(11) AND NOT $OpTx$FX_DC$42));
|
|
|
|
FDCPE_LAN_BASEADR12: FDCPE port map (LAN_BASEADR(12),LAN_BASEADR_D(12),CLK_EXT,'0',NOT RESET);
|
|
LAN_BASEADR_D(12) <= ((D(12).PIN AND $OpTx$FX_DC$42)
|
|
OR (LAN_BASEADR(12) AND NOT $OpTx$FX_DC$42));
|
|
|
|
FDCPE_LAN_BASEADR13: FDCPE port map (LAN_BASEADR(13),LAN_BASEADR_D(13),CLK_EXT,'0',NOT RESET);
|
|
LAN_BASEADR_D(13) <= ((D(13).PIN AND $OpTx$FX_DC$42)
|
|
OR (LAN_BASEADR(13) AND NOT $OpTx$FX_DC$42));
|
|
|
|
FDCPE_LAN_BASEADR14: FDCPE port map (LAN_BASEADR(14),LAN_BASEADR_D(14),CLK_EXT,'0',NOT RESET);
|
|
LAN_BASEADR_D(14) <= ((D(14).PIN AND $OpTx$FX_DC$42)
|
|
OR (LAN_BASEADR(14) AND NOT $OpTx$FX_DC$42));
|
|
|
|
FDCPE_LAN_BASEADR15: FDCPE port map (LAN_BASEADR(15),LAN_BASEADR_D(15),CLK_EXT,'0',NOT RESET);
|
|
LAN_BASEADR_D(15) <= ((D(15).PIN AND $OpTx$FX_DC$42)
|
|
OR (LAN_BASEADR(15) AND NOT $OpTx$FX_DC$42));
|
|
|
|
|
|
LAN_CFG_I(1) <= '0';
|
|
LAN_CFG(1) <= LAN_CFG_I(1) when LAN_CFG_OE(1) = '1' else 'Z';
|
|
LAN_CFG_OE(1) <= '0';
|
|
|
|
|
|
LAN_CFG_I(2) <= '0';
|
|
LAN_CFG(2) <= LAN_CFG_I(2) when LAN_CFG_OE(2) = '1' else 'Z';
|
|
LAN_CFG_OE(2) <= '0';
|
|
|
|
|
|
LAN_CFG_I(3) <= '0';
|
|
LAN_CFG(3) <= LAN_CFG_I(3) when LAN_CFG_OE(3) = '1' else 'Z';
|
|
LAN_CFG_OE(3) <= '0';
|
|
|
|
|
|
LAN_CFG_I(4) <= '0';
|
|
LAN_CFG(4) <= LAN_CFG_I(4) when LAN_CFG_OE(4) = '1' else 'Z';
|
|
LAN_CFG_OE(4) <= '0';
|
|
|
|
|
|
LAN_CS <= ((RESET AND lan_adr)
|
|
OR (NOT RESET AND LAN_CS_RST));
|
|
|
|
FDCPE_LAN_CS_RST: FDCPE port map (LAN_CS_RST,LAN_CS_RST_D,CLK_EXT,RESET,'0');
|
|
LAN_CS_RST_D <= LAN_RST_SM_FSM_FFd1
|
|
XOR
|
|
LAN_CS_RST_D <= BUF_LAN_D_INIT(1)__$INT;
|
|
|
|
FDCPE_LAN_D_INIT1: FDCPE port map (LAN_D_INIT(1),BUF_LAN_D_INIT(1)__$INT,CLK_EXT,RESET,'0');
|
|
|
|
FDCPE_LAN_D_INIT9: FDCPE port map (LAN_D_INIT(9),'1',CLK_EXT,RESET,'0');
|
|
|
|
FDCPE_LAN_D_INIT10: FDCPE port map (LAN_D_INIT(10),BUF_LAN_D_INIT(1)__$INT,CLK_EXT,RESET,'0');
|
|
|
|
FDCPE_LAN_INT_ENABLE: FDCPE port map (LAN_INT_ENABLE,LAN_INT_ENABLE_D,CLK_EXT,NOT RESET,'0');
|
|
LAN_INT_ENABLE_D <= ((D(15).PIN AND $OpTx$FX_DC$66)
|
|
OR (LAN_INT_ENABLE AND NOT $OpTx$FX_DC$66));
|
|
|
|
FDCPE_LAN_IRQ_D0: FDCPE port map (LAN_IRQ_D0,LAN_INT,CLK_EXT,'0',NOT RESET);
|
|
|
|
FDCPE_LAN_IRQ_OUT: FDCPE port map (LAN_IRQ_OUT,LAN_IRQ_OUT_D,CLK_EXT,'0',NOT RESET);
|
|
LAN_IRQ_OUT_D <= ((NOT LAN_INT AND LAN_IRQ_D0)
|
|
OR (LAN_INT_ENABLE AND NOT D(14).PIN AND NOT LAN_INT AND
|
|
$OpTx$FX_DC$66)
|
|
OR (LAN_INT_ENABLE AND NOT LAN_IRQ_OUT AND NOT LAN_INT AND
|
|
NOT $OpTx$FX_DC$66));
|
|
|
|
|
|
LAN_RD <= (LAN_RD_S AND lan_rdy/lan_rdy_RSTF);
|
|
|
|
FDCPE_LAN_RD_S: FDCPE port map (LAN_RD_S,BUF_LAN_RD_S,CLK_EXT,NOT lan_rdy/lan_rdy_RSTF,'0');
|
|
|
|
FDCPE_LAN_RST_SM_FSM_FFd1: FDCPE port map (LAN_RST_SM_FSM_FFd1,LAN_RST_SM_FSM_FFd1_D,CLK_EXT,RESET,'0');
|
|
LAN_RST_SM_FSM_FFd1_D <= ((NOT LAN_RST_SM_FSM_FFd3)
|
|
OR (NOT LAN_RST_SM_FSM_FFd2 AND LAN_RST_SM_FSM_FFd1));
|
|
|
|
FDCPE_LAN_RST_SM_FSM_FFd2: FDCPE port map (LAN_RST_SM_FSM_FFd2,LAN_RST_SM_FSM_FFd2_D,CLK_EXT,RESET,'0');
|
|
LAN_RST_SM_FSM_FFd2_D <= ((BUF_LAN_D_INIT(1)__$INT)
|
|
OR (LAN_RST_SM_FSM_FFd3 AND NOT LAN_RST_SM_FSM_FFd2));
|
|
|
|
FDCPE_LAN_RST_SM_FSM_FFd3: FDCPE port map (LAN_RST_SM_FSM_FFd3,LAN_RST_SM_FSM_FFd3_D,CLK_EXT,RESET,'0');
|
|
LAN_RST_SM_FSM_FFd3_D <= ((LAN_RST_SM_FSM_FFd1 AND NOT BUF_LAN_D_INIT(1)__$INT)
|
|
OR (NOT LAN_RST_SM_FSM_FFd2 AND NOT LAN_RST_SM_FSM_FFd1 AND
|
|
BUF_LAN_D_INIT(1)__$INT));
|
|
|
|
FTCPE_LAN_SM_FSM_FFd1: FTCPE port map (LAN_SM_FSM_FFd1,LAN_SM_FSM_FFd1_T,CLK_EXT,NOT lan_rdy/lan_rdy_RSTF,'0');
|
|
LAN_SM_FSM_FFd1_T <= (NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd3 AND
|
|
NOT LAN_SM_FSM_FFd1 AND lan_adr AND NOT RW AND NOT Z3_ADR(13) AND NOT $OpTx$FX_DC$25);
|
|
|
|
FDCPE_LAN_SM_FSM_FFd2: FDCPE port map (LAN_SM_FSM_FFd2,BUF_LAN_SM_FSM_FFd2,CLK_EXT,NOT lan_rdy/lan_rdy_RSTF,'0');
|
|
|
|
FDCPE_LAN_SM_FSM_FFd3: FDCPE port map (LAN_SM_FSM_FFd3,LAN_SM_FSM_FFd3_D,CLK_EXT,NOT lan_rdy/lan_rdy_RSTF,'0');
|
|
LAN_SM_FSM_FFd3_D <= ((NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
|
|
LAN_SM_FSM_FFd3 AND NOT $OpTx$FX_DC$23)
|
|
OR (NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND
|
|
NOT LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd1));
|
|
|
|
FDCPE_LAN_SM_FSM_FFd4: FDCPE port map (LAN_SM_FSM_FFd4,BUF_LAN_SM_FSM_FFd4__$INT,CLK_EXT,NOT lan_rdy/lan_rdy_RSTF,'0');
|
|
|
|
|
|
LAN_WRH <= ((LAN_WR_RST AND NOT lan_rdy/lan_rdy_RSTF)
|
|
OR (LAN_WRH_S AND lan_rdy/lan_rdy_RSTF));
|
|
|
|
FDCPE_LAN_WRH_S: FDCPE port map (LAN_WRH_S,LAN_WRH_S_D,CLK_EXT,NOT lan_rdy/lan_rdy_RSTF,'0');
|
|
LAN_WRH_S_D <= ((LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd1 AND NOT LDS AND
|
|
NOT $OpTx$FX_DC$268)
|
|
OR (NOT LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd1 AND NOT DS0 AND
|
|
NOT $OpTx$FX_DC$268));
|
|
|
|
|
|
LAN_WRL <= ((LAN_WR_RST AND NOT lan_rdy/lan_rdy_RSTF)
|
|
OR (LAN_WRL_S AND lan_rdy/lan_rdy_RSTF));
|
|
|
|
FDCPE_LAN_WRL_S: FDCPE port map (LAN_WRL_S,LAN_WRL_S_D,CLK_EXT,NOT lan_rdy/lan_rdy_RSTF,'0');
|
|
LAN_WRL_S_D <= ((LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd1 AND NOT UDS AND
|
|
NOT $OpTx$FX_DC$268)
|
|
OR (NOT LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd1 AND NOT DS1 AND
|
|
NOT $OpTx$FX_DC$268));
|
|
|
|
FDCPE_LAN_WR_RST: FDCPE port map (LAN_WR_RST,LAN_WR_RST_D,CLK_EXT,RESET,'0');
|
|
LAN_WR_RST_D <= ((LAN_RST_SM_FSM_FFd3 AND LAN_RST_SM_FSM_FFd2 AND
|
|
NOT LAN_RST_SM_FSM_FFd1)
|
|
OR (LAN_RST_SM_FSM_FFd3 AND NOT LAN_RST_SM_FSM_FFd2 AND
|
|
LAN_RST_SM_FSM_FFd1));
|
|
|
|
|
|
MTACK_I <= '0';
|
|
MTACK <= MTACK_I when MTACK_OE = '1' else 'Z';
|
|
MTACK_OE <= '0';
|
|
|
|
|
|
Mcompar_lan_adr_sw_cmp_eq0001_AEB_or0000/Mcompar_lan_adr_sw_cmp_eq0001_AEB_or0000_D2 <= ((EXP23_.EXP)
|
|
OR (D(15).PIN AND NOT LAN_BASEADR(15))
|
|
OR (NOT D(15).PIN AND LAN_BASEADR(15))
|
|
OR (D(10).PIN AND NOT LAN_BASEADR(10))
|
|
OR (NOT D(10).PIN AND LAN_BASEADR(10))
|
|
OR (D(11).PIN AND NOT LAN_BASEADR(11))
|
|
OR (EXP22_.EXP)
|
|
OR (NOT D(12).PIN AND LAN_BASEADR(12))
|
|
OR (D(13).PIN AND NOT LAN_BASEADR(13))
|
|
OR (NOT D(13).PIN AND LAN_BASEADR(13))
|
|
OR (D(14).PIN AND NOT LAN_BASEADR(14))
|
|
OR (NOT D(14).PIN AND LAN_BASEADR(14))
|
|
OR (NOT D(11).PIN AND LAN_BASEADR(11))
|
|
OR (D(8).PIN AND NOT LAN_BASEADR(8))
|
|
OR (NOT D(8).PIN AND LAN_BASEADR(8))
|
|
OR (D(9).PIN AND NOT LAN_BASEADR(9))
|
|
OR (NOT D(9).PIN AND LAN_BASEADR(9)));
|
|
|
|
|
|
N0$BUF7/N0$BUF7_TRST <= ((NOT FCS AND autoconfig)
|
|
OR (NOT FCS AND lan_rdy));
|
|
|
|
|
|
OVR_I <= '0';
|
|
OVR <= OVR_I when OVR_OE = '1' else 'Z';
|
|
OVR_OE <= '0';
|
|
|
|
|
|
OWN_I <= '0';
|
|
OWN <= OWN_I when OWN_OE = '1' else 'Z';
|
|
OWN_OE <= '0';
|
|
|
|
|
|
ROM_B(0) <= '1';
|
|
|
|
|
|
ROM_B(1) <= '1';
|
|
|
|
|
|
ROM_OE <= '1';
|
|
|
|
FTCPE_SHUT_UP: FTCPE port map (SHUT_UP,SHUT_UP_T,CLK_EXT,'0',NOT RESET);
|
|
SHUT_UP_T <= (NOT FCS AND NOT Z3_ADR(2) AND NOT Z3_ADR_0 AND Z3_ADR_1 AND
|
|
NOT Z3_ADR(6) AND autoconfig AND NOT RW AND NOT Z3_ADR(3) AND Z3_ADR(4) AND
|
|
NOT Z3_ADR(5) AND SHUT_UP AND NOT $OpTx$FX_DC$25);
|
|
|
|
|
|
SLAVE <= ((FCS)
|
|
OR (NOT autoconfig AND NOT lan_adr));
|
|
|
|
FDCPE_Z3_ADR2: FDCPE port map (Z3_ADR(2),A(4),NOT FCS,'0',NOT lan_adr_sw/lan_adr_sw_RSTF);
|
|
|
|
FDCPE_Z3_ADR3: FDCPE port map (Z3_ADR(3),A(5),NOT FCS,'0',NOT lan_adr_sw/lan_adr_sw_RSTF);
|
|
|
|
FDCPE_Z3_ADR4: FDCPE port map (Z3_ADR(4),A(6),NOT FCS,'0',NOT lan_adr_sw/lan_adr_sw_RSTF);
|
|
|
|
FDCPE_Z3_ADR5: FDCPE port map (Z3_ADR(5),A(7),NOT FCS,'0',NOT lan_adr_sw/lan_adr_sw_RSTF);
|
|
|
|
FDCPE_Z3_ADR6: FDCPE port map (Z3_ADR(6),A(8).PIN,NOT FCS,'0',NOT lan_adr_sw/lan_adr_sw_RSTF);
|
|
|
|
FDCPE_Z3_ADR7: FDCPE port map (Z3_ADR(7),A(9).PIN,NOT FCS,'0',NOT lan_adr_sw/lan_adr_sw_RSTF);
|
|
|
|
FDCPE_Z3_ADR8: FDCPE port map (Z3_ADR(8),A(10).PIN,NOT FCS,'0',NOT lan_adr_sw/lan_adr_sw_RSTF);
|
|
|
|
FDCPE_Z3_ADR9: FDCPE port map (Z3_ADR(9),A(11).PIN,NOT FCS,'0',NOT lan_adr_sw/lan_adr_sw_RSTF);
|
|
|
|
FDCPE_Z3_ADR10: FDCPE port map (Z3_ADR(10),A(12).PIN,NOT FCS,'0',NOT lan_adr_sw/lan_adr_sw_RSTF);
|
|
|
|
FDCPE_Z3_ADR11: FDCPE port map (Z3_ADR(11),A(13).PIN,NOT FCS,'0',NOT lan_adr_sw/lan_adr_sw_RSTF);
|
|
|
|
FDCPE_Z3_ADR12: FDCPE port map (Z3_ADR(12),A(14).PIN,NOT FCS,'0',NOT lan_adr_sw/lan_adr_sw_RSTF);
|
|
|
|
FDCPE_Z3_ADR13: FDCPE port map (Z3_ADR(13),A(15).PIN,NOT FCS,'0',NOT lan_adr_sw/lan_adr_sw_RSTF);
|
|
|
|
FDCPE_Z3_ADR_0: FDCPE port map (Z3_ADR_0,A(2),NOT FCS,'0',NOT lan_adr_sw/lan_adr_sw_RSTF);
|
|
|
|
FDCPE_Z3_ADR_1: FDCPE port map (Z3_ADR_1,A(3),NOT FCS,'0',NOT lan_adr_sw/lan_adr_sw_RSTF);
|
|
|
|
FDCPE_Z3_A_LOW: FDCPE port map (Z3_A_LOW,Z3_A_LOW_D,CLK_EXT,NOT lan_rdy/lan_rdy_RSTF,'0');
|
|
Z3_A_LOW_D <= ((LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2)
|
|
OR (NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
|
|
NOT $OpTx$FX_DC$23)
|
|
OR (NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3 AND
|
|
LAN_SM_FSM_FFd1)
|
|
OR (NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3 AND lan_adr AND
|
|
NOT Z3_ADR(13) AND NOT $OpTx$FX_DC$23 AND $OpTx$FX_DC$24));
|
|
|
|
|
|
Z3_DATA(7)/Z3_DATA(7)_TRST <= (NOT FCS AND lan_adr AND RW AND NOT $OpTx$FX_DC$25);
|
|
|
|
FDCPE_Z3_DATA16: FDCPE port map (Z3_DATA(16),Z3_DATA_D(16),CLK_EXT,'0',NOT lan_rdy/lan_rdy_RSTF);
|
|
Z3_DATA_D(16) <= ((lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
|
|
NOT LAN_SM_FSM_FFd1 AND DQ(8).PIN)
|
|
OR (NOT lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
|
|
NOT LAN_SM_FSM_FFd1 AND DQ(0).PIN)
|
|
OR (D(0).PIN AND NOT lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND
|
|
NOT LAN_SM_FSM_FFd3 AND lan_adr AND NOT Z3_ADR(13) AND NOT $OpTx$FX_DC$25)
|
|
OR (D(8).PIN AND lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND
|
|
NOT LAN_SM_FSM_FFd3 AND lan_adr AND NOT Z3_ADR(13) AND NOT $OpTx$FX_DC$25)
|
|
OR (Z3_DATA(16) AND NOT $OpTx$FX_DC$325));
|
|
|
|
FDCPE_Z3_DATA17: FDCPE port map (Z3_DATA(17),Z3_DATA_D(17),CLK_EXT,'0',NOT lan_rdy/lan_rdy_RSTF);
|
|
Z3_DATA_D(17) <= ((D(9).PIN AND lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND
|
|
NOT LAN_SM_FSM_FFd3 AND lan_adr AND NOT Z3_ADR(13) AND NOT $OpTx$FX_DC$25)
|
|
OR (Z3_DATA(17) AND NOT $OpTx$FX_DC$325)
|
|
OR (lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
|
|
NOT LAN_SM_FSM_FFd1 AND DQ(9).PIN)
|
|
OR (NOT lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
|
|
NOT LAN_SM_FSM_FFd1 AND DQ(1).PIN)
|
|
OR (D(1).PIN AND NOT lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND
|
|
NOT LAN_SM_FSM_FFd3 AND lan_adr AND NOT Z3_ADR(13) AND NOT $OpTx$FX_DC$25));
|
|
|
|
FDCPE_Z3_DATA18: FDCPE port map (Z3_DATA(18),Z3_DATA_D(18),CLK_EXT,'0',NOT lan_rdy/lan_rdy_RSTF);
|
|
Z3_DATA_D(18) <= ((D(10).PIN AND lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND
|
|
NOT LAN_SM_FSM_FFd3 AND lan_adr AND NOT Z3_ADR(13) AND NOT $OpTx$FX_DC$25)
|
|
OR (Z3_DATA(18) AND NOT $OpTx$FX_DC$325)
|
|
OR (lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
|
|
NOT LAN_SM_FSM_FFd1 AND DQ(10).PIN)
|
|
OR (NOT lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
|
|
NOT LAN_SM_FSM_FFd1 AND DQ(2).PIN)
|
|
OR (D(2).PIN AND NOT lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND
|
|
NOT LAN_SM_FSM_FFd3 AND lan_adr AND NOT Z3_ADR(13) AND NOT $OpTx$FX_DC$25));
|
|
|
|
FDCPE_Z3_DATA19: FDCPE port map (Z3_DATA(19),Z3_DATA_D(19),CLK_EXT,'0',NOT lan_rdy/lan_rdy_RSTF);
|
|
Z3_DATA_D(19) <= ((D(11).PIN AND lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND
|
|
NOT LAN_SM_FSM_FFd3 AND lan_adr AND NOT Z3_ADR(13) AND NOT $OpTx$FX_DC$25)
|
|
OR (Z3_DATA(19) AND NOT $OpTx$FX_DC$325)
|
|
OR (lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
|
|
NOT LAN_SM_FSM_FFd1 AND DQ(11).PIN)
|
|
OR (NOT lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
|
|
NOT LAN_SM_FSM_FFd1 AND DQ(3).PIN)
|
|
OR (D(3).PIN AND NOT lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND
|
|
NOT LAN_SM_FSM_FFd3 AND lan_adr AND NOT Z3_ADR(13) AND NOT $OpTx$FX_DC$25));
|
|
|
|
FDCPE_Z3_DATA20: FDCPE port map (Z3_DATA(20),Z3_DATA_D(20),CLK_EXT,'0',NOT lan_rdy/lan_rdy_RSTF);
|
|
Z3_DATA_D(20) <= ((D(12).PIN AND lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND
|
|
NOT LAN_SM_FSM_FFd3 AND lan_adr AND NOT Z3_ADR(13) AND NOT $OpTx$FX_DC$25)
|
|
OR (D(4).PIN AND NOT lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND
|
|
NOT LAN_SM_FSM_FFd3 AND lan_adr AND NOT Z3_ADR(13) AND NOT $OpTx$FX_DC$25)
|
|
OR (Z3_DATA(20) AND NOT $OpTx$FX_DC$325)
|
|
OR (lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
|
|
NOT LAN_SM_FSM_FFd1 AND DQ(12).PIN)
|
|
OR (NOT lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
|
|
NOT LAN_SM_FSM_FFd1 AND DQ(4).PIN));
|
|
|
|
FDCPE_Z3_DATA21: FDCPE port map (Z3_DATA(21),Z3_DATA_D(21),CLK_EXT,'0',NOT lan_rdy/lan_rdy_RSTF);
|
|
Z3_DATA_D(21) <= ((lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
|
|
NOT LAN_SM_FSM_FFd1 AND DQ(13).PIN)
|
|
OR (D(13).PIN AND lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND
|
|
NOT LAN_SM_FSM_FFd3 AND lan_adr AND NOT Z3_ADR(13) AND NOT $OpTx$FX_DC$25)
|
|
OR (D(5).PIN AND NOT lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND
|
|
NOT LAN_SM_FSM_FFd3 AND lan_adr AND NOT Z3_ADR(13) AND NOT $OpTx$FX_DC$25)
|
|
OR (Z3_DATA(21) AND NOT $OpTx$FX_DC$325)
|
|
OR (NOT lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
|
|
NOT LAN_SM_FSM_FFd1 AND DQ(5).PIN));
|
|
|
|
FDCPE_Z3_DATA22: FDCPE port map (Z3_DATA(22),Z3_DATA_D(22),CLK_EXT,'0',NOT lan_rdy/lan_rdy_RSTF);
|
|
Z3_DATA_D(22) <= ((D(14).PIN AND lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND
|
|
NOT LAN_SM_FSM_FFd3 AND lan_adr AND NOT Z3_ADR(13) AND NOT $OpTx$FX_DC$25)
|
|
OR (Z3_DATA(22) AND NOT $OpTx$FX_DC$325)
|
|
OR (lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
|
|
NOT LAN_SM_FSM_FFd1 AND DQ(14).PIN)
|
|
OR (NOT lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
|
|
NOT LAN_SM_FSM_FFd1 AND DQ(6).PIN)
|
|
OR (D(6).PIN AND NOT lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND
|
|
NOT LAN_SM_FSM_FFd3 AND lan_adr AND NOT Z3_ADR(13) AND NOT $OpTx$FX_DC$25));
|
|
|
|
FDCPE_Z3_DATA23: FDCPE port map (Z3_DATA(23),Z3_DATA_D(23),CLK_EXT,'0',NOT lan_rdy/lan_rdy_RSTF);
|
|
Z3_DATA_D(23) <= ((D(15).PIN AND lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND
|
|
NOT LAN_SM_FSM_FFd3 AND lan_adr AND NOT Z3_ADR(13) AND NOT $OpTx$FX_DC$25)
|
|
OR (Z3_DATA(23) AND NOT $OpTx$FX_DC$325)
|
|
OR (lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
|
|
NOT LAN_SM_FSM_FFd1 AND DQ(15).PIN)
|
|
OR (NOT lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
|
|
NOT LAN_SM_FSM_FFd1 AND DQ(7).PIN)
|
|
OR (D(7).PIN AND NOT lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND
|
|
NOT LAN_SM_FSM_FFd3 AND lan_adr AND NOT Z3_ADR(13) AND NOT $OpTx$FX_DC$25));
|
|
|
|
FDCPE_Z3_DATA24: FDCPE port map (Z3_DATA(24),Z3_DATA_D(24),CLK_EXT,'0',NOT lan_rdy/lan_rdy_RSTF);
|
|
Z3_DATA_D(24) <= ((D(0).PIN AND lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND
|
|
NOT LAN_SM_FSM_FFd3 AND lan_adr AND NOT Z3_ADR(13) AND NOT $OpTx$FX_DC$25)
|
|
OR (Z3_DATA(24) AND NOT $OpTx$FX_DC$325)
|
|
OR (lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
|
|
NOT LAN_SM_FSM_FFd1 AND DQ(0).PIN)
|
|
OR (NOT lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
|
|
NOT LAN_SM_FSM_FFd1 AND DQ(8).PIN)
|
|
OR (D(8).PIN AND NOT lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND
|
|
NOT LAN_SM_FSM_FFd3 AND lan_adr AND NOT Z3_ADR(13) AND NOT $OpTx$FX_DC$25));
|
|
|
|
FDCPE_Z3_DATA25: FDCPE port map (Z3_DATA(25),Z3_DATA_D(25),CLK_EXT,'0',NOT lan_rdy/lan_rdy_RSTF);
|
|
Z3_DATA_D(25) <= ((D(1).PIN AND lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND
|
|
NOT LAN_SM_FSM_FFd3 AND lan_adr AND NOT Z3_ADR(13) AND NOT $OpTx$FX_DC$25)
|
|
OR (Z3_DATA(25) AND NOT $OpTx$FX_DC$325)
|
|
OR (lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
|
|
NOT LAN_SM_FSM_FFd1 AND DQ(1).PIN)
|
|
OR (NOT lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
|
|
NOT LAN_SM_FSM_FFd1 AND DQ(9).PIN)
|
|
OR (D(9).PIN AND NOT lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND
|
|
NOT LAN_SM_FSM_FFd3 AND lan_adr AND NOT Z3_ADR(13) AND NOT $OpTx$FX_DC$25));
|
|
|
|
FDCPE_Z3_DATA26: FDCPE port map (Z3_DATA(26),Z3_DATA_D(26),CLK_EXT,'0',NOT lan_rdy/lan_rdy_RSTF);
|
|
Z3_DATA_D(26) <= ((D(10).PIN AND NOT lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND
|
|
NOT LAN_SM_FSM_FFd3 AND lan_adr AND NOT Z3_ADR(13) AND NOT $OpTx$FX_DC$25)
|
|
OR (D(2).PIN AND lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND
|
|
NOT LAN_SM_FSM_FFd3 AND lan_adr AND NOT Z3_ADR(13) AND NOT $OpTx$FX_DC$25)
|
|
OR (Z3_DATA(26) AND NOT $OpTx$FX_DC$325)
|
|
OR (lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
|
|
NOT LAN_SM_FSM_FFd1 AND DQ(2).PIN)
|
|
OR (NOT lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
|
|
NOT LAN_SM_FSM_FFd1 AND DQ(10).PIN));
|
|
|
|
FDCPE_Z3_DATA27: FDCPE port map (Z3_DATA(27),Z3_DATA_D(27),CLK_EXT,'0',NOT lan_rdy/lan_rdy_RSTF);
|
|
Z3_DATA_D(27) <= ((D(11).PIN AND NOT lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND
|
|
NOT LAN_SM_FSM_FFd3 AND lan_adr AND NOT Z3_ADR(13) AND NOT $OpTx$FX_DC$25)
|
|
OR (D(3).PIN AND lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND
|
|
NOT LAN_SM_FSM_FFd3 AND lan_adr AND NOT Z3_ADR(13) AND NOT $OpTx$FX_DC$25)
|
|
OR (Z3_DATA(27) AND NOT $OpTx$FX_DC$325)
|
|
OR (lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
|
|
NOT LAN_SM_FSM_FFd1 AND DQ(3).PIN)
|
|
OR (NOT lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
|
|
NOT LAN_SM_FSM_FFd1 AND DQ(11).PIN));
|
|
|
|
FDCPE_Z3_DATA28: FDCPE port map (Z3_DATA(28),Z3_DATA_D(28),CLK_EXT,'0',NOT lan_rdy/lan_rdy_RSTF);
|
|
Z3_DATA_D(28) <= ((D(4).PIN AND lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND
|
|
NOT LAN_SM_FSM_FFd3 AND lan_adr AND NOT Z3_ADR(13) AND NOT $OpTx$FX_DC$25)
|
|
OR (Z3_DATA(28) AND NOT $OpTx$FX_DC$325)
|
|
OR (lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
|
|
NOT LAN_SM_FSM_FFd1 AND DQ(4).PIN)
|
|
OR (NOT lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
|
|
NOT LAN_SM_FSM_FFd1 AND DQ(12).PIN)
|
|
OR (D(12).PIN AND NOT lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND
|
|
NOT LAN_SM_FSM_FFd3 AND lan_adr AND NOT Z3_ADR(13) AND NOT $OpTx$FX_DC$25));
|
|
|
|
FDCPE_Z3_DATA29: FDCPE port map (Z3_DATA(29),Z3_DATA_D(29),CLK_EXT,'0',NOT lan_rdy/lan_rdy_RSTF);
|
|
Z3_DATA_D(29) <= ((D(5).PIN AND lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND
|
|
NOT LAN_SM_FSM_FFd3 AND lan_adr AND NOT Z3_ADR(13) AND NOT $OpTx$FX_DC$25)
|
|
OR (Z3_DATA(29) AND NOT $OpTx$FX_DC$325)
|
|
OR (lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
|
|
NOT LAN_SM_FSM_FFd1 AND DQ(5).PIN)
|
|
OR (NOT lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
|
|
NOT LAN_SM_FSM_FFd1 AND DQ(13).PIN)
|
|
OR (D(13).PIN AND NOT lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND
|
|
NOT LAN_SM_FSM_FFd3 AND lan_adr AND NOT Z3_ADR(13) AND NOT $OpTx$FX_DC$25));
|
|
|
|
FDCPE_Z3_DATA30: FDCPE port map (Z3_DATA(30),Z3_DATA_D(30),CLK_EXT,'0',NOT lan_rdy/lan_rdy_RSTF);
|
|
Z3_DATA_D(30) <= ((D(14).PIN AND NOT lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND
|
|
NOT LAN_SM_FSM_FFd3 AND lan_adr AND NOT Z3_ADR(13) AND NOT $OpTx$FX_DC$25)
|
|
OR (D(6).PIN AND lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND
|
|
NOT LAN_SM_FSM_FFd3 AND lan_adr AND NOT Z3_ADR(13) AND NOT $OpTx$FX_DC$25)
|
|
OR (Z3_DATA(30) AND NOT $OpTx$FX_DC$325)
|
|
OR (lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
|
|
NOT LAN_SM_FSM_FFd1 AND DQ(6).PIN)
|
|
OR (NOT lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
|
|
NOT LAN_SM_FSM_FFd1 AND DQ(14).PIN));
|
|
|
|
FDCPE_Z3_DATA31: FDCPE port map (Z3_DATA(31),Z3_DATA_D(31),CLK_EXT,'0',NOT lan_rdy/lan_rdy_RSTF);
|
|
Z3_DATA_D(31) <= ((D(7).PIN AND lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND
|
|
NOT LAN_SM_FSM_FFd3 AND lan_adr AND NOT Z3_ADR(13) AND NOT $OpTx$FX_DC$25)
|
|
OR (Z3_DATA(31) AND NOT $OpTx$FX_DC$325)
|
|
OR (lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
|
|
NOT LAN_SM_FSM_FFd1 AND DQ(7).PIN)
|
|
OR (NOT lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
|
|
NOT LAN_SM_FSM_FFd1 AND DQ(15).PIN)
|
|
OR (D(15).PIN AND NOT lan_adr_sw AND NOT LAN_SM_FSM_FFd4 AND
|
|
NOT LAN_SM_FSM_FFd3 AND lan_adr AND NOT Z3_ADR(13) AND NOT $OpTx$FX_DC$25));
|
|
|
|
FDCPE_autoconfig: FDCPE port map (autoconfig,BUF_autoconfig,NOT FCS,NOT lan_adr_sw/lan_adr_sw_RSTF,'0');
|
|
|
|
FDCPE_lan_adr: FDCPE port map (lan_adr,lan_adr_D,NOT FCS,NOT lan_adr_sw/lan_adr_sw_RSTF,'0');
|
|
lan_adr_D <= (Z3 AND NOT SHUT_UP AND
|
|
NOT Mcompar_lan_adr_sw_cmp_eq0001_AEB_or0000/Mcompar_lan_adr_sw_cmp_eq0001_AEB_or0000_D2 AND NOT BUF_autoconfig);
|
|
|
|
FDCPE_lan_adr_sw: FDCPE port map (lan_adr_sw,lan_adr_sw_D,NOT FCS,NOT lan_adr_sw/lan_adr_sw_RSTF,'0');
|
|
lan_adr_sw_D <= ((Z3 AND NOT SHUT_UP AND NOT A(13).PIN AND
|
|
NOT Mcompar_lan_adr_sw_cmp_eq0001_AEB_or0000/Mcompar_lan_adr_sw_cmp_eq0001_AEB_or0000_D2 AND NOT BUF_autoconfig)
|
|
OR (Z3 AND NOT SHUT_UP AND NOT A(14).PIN AND
|
|
NOT Mcompar_lan_adr_sw_cmp_eq0001_AEB_or0000/Mcompar_lan_adr_sw_cmp_eq0001_AEB_or0000_D2 AND NOT BUF_autoconfig));
|
|
|
|
|
|
lan_adr_sw/lan_adr_sw_RSTF <= (RESET AND BERR);
|
|
|
|
FDCPE_lan_rdy: FDCPE port map (lan_rdy,lan_rdy_D,CLK_EXT,NOT lan_rdy/lan_rdy_RSTF,'0');
|
|
lan_rdy_D <= ((NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND
|
|
$OpTx$FX_DC$23)
|
|
OR (NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND
|
|
LAN_SM_FSM_FFd3)
|
|
OR (NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND
|
|
LAN_SM_FSM_FFd1));
|
|
|
|
|
|
lan_rdy/lan_rdy_RSTF <= (RESET AND NOT FCS);
|
|
|
|
Register Legend:
|
|
FDCPE (Q,D,C,CLR,PRE,CE);
|
|
FTCPE (Q,D,C,CLR,PRE,CE);
|
|
LDCP (Q,D,G,CLR,PRE);
|
|
|
|
****************************** Device Pin Out *****************************
|
|
|
|
Device : XC95288XL-10-TQ144
|
|
|
|
|
|
Pin Signal Pin Signal
|
|
No. Name No. Name
|
|
1 VCC 73 VCC
|
|
2 D<0> 74 A<15>
|
|
3 A_LAN<1> 75 AUTOBOOT_OFF
|
|
4 A_LAN<0> 76 LAN_WRL
|
|
5 A_LAN<3> 77 FCS
|
|
6 A_LAN<2> 78 DS1
|
|
7 A_LAN<5> 79 Z3
|
|
8 VCC 80 TIE
|
|
9 A_LAN<4> 81 UDS
|
|
10 A_LAN<7> 82 LDS
|
|
11 A_LAN<6> 83 RW
|
|
12 LAN_CFG<1> 84 VCC
|
|
13 LAN_CFG<3> 85 DTACK
|
|
14 D<6> 86 A<23>
|
|
15 D<3> 87 A<22>
|
|
16 D<7> 88 A<21>
|
|
17 D<1> 89 GND
|
|
18 GND 90 GND
|
|
19 D<8> 91 A<20>
|
|
20 D<5> 92 A<19>
|
|
21 D<4> 93 DS0
|
|
22 IDE_CS<0> 94 A<18>
|
|
23 IDE_CS<1> 95 A<17>
|
|
24 IDE_A<0> 96 MTACK
|
|
25 IDE_A<2> 97 A<16>
|
|
26 IDE_A<1> 98 BERR
|
|
27 IDE_R 99 GND
|
|
28 IDE_W 100 OVR
|
|
29 GND 101 TIE
|
|
30 CLK_EXT 102 TIE
|
|
31 TIE 103 TIE
|
|
32 INT_OUT 104 CFIN
|
|
33 TIE 105 CFOUT
|
|
34 CP_CS 106 SLAVE
|
|
35 ROM_OE 107 OWN
|
|
36 GND 108 GND
|
|
37 VCC 109 VCC
|
|
38 TIE 110 LAN_CFG<4>
|
|
39 D<2> 111 LAN_INT
|
|
40 D<9> 112 DQ<15>
|
|
41 D<10> 113 DQ<13>
|
|
42 VCC 114 GND
|
|
43 D<11> 115 DQ<11>
|
|
44 D<12> 116 DQ<9>
|
|
45 D<13> 117 DQ<1>
|
|
46 D<14> 118 DQ<0>
|
|
47 GND 119 DQ<3>
|
|
48 D<15> 120 DQ<2>
|
|
49 A<5> 121 DQ<5>
|
|
50 A<4> 122 TDO
|
|
51 A<6> 123 GND
|
|
52 A<3> 124 DQ<4>
|
|
53 A<7> 125 DQ<7>
|
|
54 A<2> 126 DQ<6>
|
|
55 VCC 127 VCC
|
|
56 A<8> 128 DQ<8>
|
|
57 TIE 129 DQ<10>
|
|
58 A<9> 130 DQ<12>
|
|
59 A<10> 131 DQ<14>
|
|
60 A<11> 132 LAN_WRH
|
|
61 A<12> 133 LAN_CS
|
|
62 GND 134 LAN_RD
|
|
63 TDI 135 LAN_CFG<2>
|
|
64 A<13> 136 A_LAN<12>
|
|
65 TMS 137 A_LAN<13>
|
|
66 A<14> 138 A_LAN<10>
|
|
67 TCK 139 A_LAN<11>
|
|
68 ROM_B<0> 140 A_LAN<8>
|
|
69 ROM_B<1> 141 VCC
|
|
70 CP_WE 142 A_LAN<9>
|
|
71 CP_RD 143 RESET
|
|
72 GND 144 GND
|
|
|
|
|
|
Legend : NC = Not Connected, unbonded pin
|
|
PGND = Unused I/O configured as additional Ground pin
|
|
TIE = Unused I/O floating -- must tie to VCC, GND or other signal
|
|
KPR = Unused I/O with weak keeper (leave unconnected)
|
|
VCC = Dedicated Power Pin
|
|
GND = Dedicated Ground Pin
|
|
TDI = Test Data In, JTAG pin
|
|
TDO = Test Data Out, JTAG pin
|
|
TCK = Test Clock, JTAG pin
|
|
TMS = Test Mode Select, JTAG pin
|
|
PROHIBITED = User reserved pin
|
|
**************************** Compiler Options ****************************
|
|
|
|
Following is a list of all global compiler options used by the fitter run.
|
|
|
|
Device(s) Specified : xc95288xl-10-TQ144
|
|
Optimization Method : DENSITY
|
|
Multi-Level Logic Optimization : ON
|
|
Ignore Timing Specifications : OFF
|
|
Default Register Power Up Value : LOW
|
|
Keep User Location Constraints : ON
|
|
What-You-See-Is-What-You-Get : OFF
|
|
Exhaustive Fitting : OFF
|
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Keep Unused Inputs : OFF
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Slew Rate : FAST
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Power Mode : STD
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Ground on Unused IOs : OFF
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Set I/O Pin Termination : FLOAT
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Global Clock Optimization : ON
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Global Set/Reset Optimization : ON
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Global Ouput Enable Optimization : ON
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Input Limit : 54
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Pterm Limit : 35
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