3473 lines
183 KiB
Plaintext
3473 lines
183 KiB
Plaintext
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cpldfit: version P.20131013 Xilinx Inc.
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Fitter Report
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Design Name: LAN_IDE_CP Date: 2-21-2019, 11:44PM
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Device Used: XC95288XL-10-TQ144
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Fitting Status: Successful
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************************* Mapped Resource Summary **************************
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Macrocells Product Terms Function Block Registers Pins
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Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot
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241/288 ( 84%) 1176/1440 ( 82%) 603/864 ( 70%) 153/288 ( 53%) 115/117 ( 98%)
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** Function Block Resources **
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Function Mcells FB Inps Pterms IO
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Block Used/Tot Used/Tot Used/Tot Used/Tot
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FB1 18/18* 42/54 75/90 8/ 8*
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FB2 16/18 46/54 79/90 10/10*
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FB3 18/18* 41/54 52/90 5/ 5*
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FB4 18/18* 47/54 86/90 6/ 6*
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FB5 9/18 49/54 78/90 7/ 8
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FB6 18/18* 30/54 41/90 8/ 8*
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FB7 13/18 43/54 85/90 4/ 4*
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FB8 12/18 37/54 89/90 5/ 5*
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FB9 17/18 45/54 72/90 9/ 9*
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FB10 11/18 31/54 87/90 10/10*
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FB11 18/18* 34/54 66/90 7/ 7*
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FB12 12/18 37/54 89/90 6/ 6*
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FB13 10/18 29/54 82/90 6/ 6*
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FB14 18/18* 21/54 36/90 7/ 8
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FB15 17/18 41/54 82/90 9/ 9*
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FB16 16/18 30/54 77/90 8/ 8*
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----- ----- ----- -----
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241/288 603/864 1176/1440 115/117
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* - Resource is exhausted
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** Global Control Resources **
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Signal 'CLK_EXT' mapped onto global clock net GCK1.
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Global output enable net(s) unused.
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Global set/reset net(s) unused.
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** Pin Resources **
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Signal Type Required Mapped | Pin Type Used Total
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------------------------------------|------------------------------------
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Input : 23 23 | I/O : 108 109
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Output : 43 43 | GCK/IO : 2 3
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Bidirectional : 48 48 | GTS/IO : 4 4
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GCK : 1 1 | GSR/IO : 1 1
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GTS : 0 0 |
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GSR : 0 0 |
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---- ----
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Total 115 115
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** Power Data **
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There are 241 macrocells in high performance mode (MCHP).
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There are 0 macrocells in low power mode (MCLP).
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End of Mapped Resource Summary
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************************** Errors and Warnings ***************************
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WARNING:Cpld - Unable to retrieve the path to the iSE Project Repository. Will
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use the default filename of 'LAN_IDE_CP.ise'.
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INFO:Cpld - Inferring BUFG constraint for signal 'CLK_EXT' based upon the LOC
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constraint 'P30'. It is recommended that you declare this BUFG explicitedly
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in your design. Note that for certain device families the output of a BUFG
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constraint can not drive a gated clock, and the BUFG constraint will be
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ignored.
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WARNING:Cpld:1007 - Removing unused input(s) 'IDE_WAIT'. The input(s) are
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unused after optimization. Please verify functionality via simulation.
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WARNING:Cpld:1007 - Removing unused input(s) 'MTCR'. The input(s) are unused
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after optimization. Please verify functionality via simulation.
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WARNING:Cpld:896 - Unable to map all desired signals into function block, FB10,
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because too many function block product terms are required. Buffering output
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signal DQ<8> to allow all signals assigned to this function block to be
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placed.
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WARNING:Cpld:896 - Unable to map all desired signals into function block, FB10,
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because too many function block product terms are required. Buffering output
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signal DQ<4> to allow all signals assigned to this function block to be
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placed.
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************************* Summary of Mapped Logic ************************
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** 91 Outputs **
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Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init
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Name Pts Inps No. Type Use Mode Rate State
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D<5> 7 8 FB1_5 20 I/O I/O STD FAST
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D<4> 7 8 FB1_6 21 I/O I/O STD FAST
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IDE_CS<0> 1 1 FB1_8 22 I/O O STD FAST
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IDE_CS<1> 1 1 FB1_10 23 I/O O STD FAST
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IDE_A<0> 1 1 FB1_12 24 I/O O STD FAST
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IDE_A<2> 1 1 FB1_14 25 I/O O STD FAST
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IDE_A<1> 1 1 FB1_15 26 I/O O STD FAST
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IDE_R 1 2 FB1_17 27 I/O O STD FAST
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A_LAN<4> 2 4 FB2_2 9 I/O O STD FAST
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A_LAN<7> 1 2 FB2_3 10 I/O O STD FAST
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A_LAN<6> 2 3 FB2_5 11 I/O O STD FAST
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LAN_CFG<1> 0 0 FB2_6 12 I/O O STD FAST
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LAN_CFG<3> 0 0 FB2_8 13 I/O O STD FAST
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D<6> 7 8 FB2_10 14 I/O I/O STD FAST
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D<3> 7 8 FB2_12 15 I/O I/O STD FAST
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D<7> 7 8 FB2_14 16 I/O I/O STD FAST
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D<1> 7 8 FB2_15 17 I/O I/O STD FAST
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D<8> 7 8 FB2_17 19 I/O I/O STD FAST
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IDE_W 1 2 FB3_2 28 I/O O STD FAST
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INT2_OUT 1 2 FB3_14 32 GCK/I/O O STD FAST
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ROM_B<0> 0 0 FB3_15 33 I/O O STD FAST
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D<0> 7 8 FB4_2 2 GTS/I/O I/O STD FAST
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A_LAN<1> 1 2 FB4_5 3 GTS/I/O O STD FAST
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A_LAN<0> 1 2 FB4_6 4 I/O O STD FAST
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A_LAN<3> 3 5 FB4_8 5 GTS/I/O O STD FAST
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A_LAN<2> 2 4 FB4_12 6 GTS/I/O O STD FAST
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A_LAN<5> 2 4 FB4_14 7 I/O O STD FAST
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CP_CS 19 19 FB5_2 34 I/O O STD FAST SET
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ROM_OE 1 3 FB5_5 35 I/O O STD FAST
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D<2> 7 8 FB5_10 39 I/O I/O STD FAST
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D<9> 7 8 FB5_12 40 I/O I/O STD FAST
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D<10> 7 8 FB5_14 41 I/O I/O STD FAST
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D<11> 7 8 FB5_15 43 I/O I/O STD FAST
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D<12> 9 9 FB5_17 44 I/O I/O STD FAST
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LAN_CFG<2> 0 0 FB6_2 135 I/O O STD FAST
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A_LAN<12> 1 2 FB6_3 136 I/O O STD FAST
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A_LAN<13> 1 2 FB6_5 137 I/O O STD FAST
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A_LAN<10> 1 2 FB6_6 138 I/O O STD FAST
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A_LAN<11> 1 2 FB6_8 139 I/O O STD FAST
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A_LAN<8> 1 2 FB6_10 140 I/O O STD FAST
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Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init
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Name Pts Inps No. Type Use Mode Rate State
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A_LAN<9> 1 2 FB6_14 142 I/O O STD FAST
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D<13> 9 9 FB7_3 45 I/O I/O STD FAST
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D<14> 9 9 FB7_5 46 I/O I/O STD FAST
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D<15> 9 9 FB7_12 48 I/O I/O STD FAST
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DQ<12> 9 11 FB8_2 130 I/O I/O STD FAST
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DQ<14> 9 11 FB8_3 131 I/O I/O STD FAST
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LAN_WRH 3 4 FB8_5 132 I/O O STD FAST
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LAN_CS 3 4 FB8_8 133 I/O O STD FAST
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LAN_RD 1 3 FB8_10 134 I/O O STD FAST
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A<8> 5 8 FB9_11 56 I/O I/O STD FAST RESET
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A<9> 5 8 FB9_14 58 I/O I/O STD FAST RESET
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A<10> 5 8 FB9_17 59 I/O I/O STD FAST RESET
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DQ<1> 10 12 FB10_2 117 I/O I/O STD FAST
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DQ<0> 9 11 FB10_3 118 I/O I/O STD FAST
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DQ<3> 9 11 FB10_5 119 I/O I/O STD FAST
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DQ<2> 9 11 FB10_6 120 I/O I/O STD FAST
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DQ<5> 9 11 FB10_8 121 I/O I/O STD FAST
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DQ<4> 2 2 FB10_10 124 I/O I/O STD FAST
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DQ<7> 9 11 FB10_11 125 I/O I/O STD FAST
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DQ<6> 9 11 FB10_12 126 I/O I/O STD FAST
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DQ<8> 2 2 FB10_14 128 I/O I/O STD FAST
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DQ<10> 10 12 FB10_17 129 I/O I/O STD FAST
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A<11> 5 8 FB11_3 60 I/O I/O STD FAST RESET
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A<12> 5 8 FB11_5 61 I/O I/O STD FAST RESET
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A<13> 5 8 FB11_10 64 I/O I/O STD FAST RESET
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A<14> 5 8 FB11_11 66 I/O I/O STD FAST RESET
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INT6_OUT 1 1 FB11_12 68 I/O O STD FAST
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ROM_B<1> 0 0 FB11_14 69 I/O O STD FAST
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CP_WE 1 3 FB11_17 70 I/O O STD FAST
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LAN_CFG<4> 0 0 FB12_2 110 I/O O STD FAST
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DQ<15> 9 11 FB12_5 112 I/O I/O STD FAST
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DQ<13> 9 11 FB12_8 113 I/O I/O STD FAST
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DQ<11> 10 12 FB12_10 115 I/O I/O STD FAST
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DQ<9> 10 12 FB12_12 116 I/O I/O STD FAST
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CP_RD 1 2 FB13_2 71 I/O O STD FAST
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A<15> 5 8 FB13_8 74 I/O I/O STD FAST RESET
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LAN_WRL 3 4 FB13_14 76 I/O O STD FAST
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OVR 1 2 FB14_3 100 I/O O STD FAST
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CFOUT 1 3 FB14_11 105 I/O O STD FAST
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SLAVE 4 6 FB14_14 106 I/O O STD FAST
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Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init
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Name Pts Inps No. Type Use Mode Rate State
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OWN 0 0 FB14_15 107 I/O O STD FAST
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DTACK 1 2 FB15_12 85 I/O O STD FAST
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A<23> 5 8 FB15_14 86 I/O I/O STD FAST RESET
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A<22> 5 8 FB15_15 87 I/O I/O STD FAST RESET
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A<21> 5 8 FB15_17 88 I/O I/O STD FAST RESET
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A<20> 5 8 FB16_2 91 I/O I/O STD FAST RESET
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A<19> 5 8 FB16_3 92 I/O I/O STD FAST RESET
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A<18> 5 8 FB16_6 94 I/O I/O STD FAST RESET
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A<17> 5 8 FB16_8 95 I/O I/O STD FAST RESET
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MTACK 0 0 FB16_10 96 I/O O STD FAST
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A<16> 5 8 FB16_11 97 I/O I/O STD FAST RESET
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** 150 Buried Nodes **
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Signal Total Total Loc Pwr Reg Init
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Name Pts Inps Mode State
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SHUT_UP_Z2<1> 4 16 FB1_1 STD SET
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LAN_BASEADR<8> 6 16 FB1_2 STD RESET
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D_9_IOBUFE/D_9_IOBUFE_TRST 3 6 FB1_3 STD
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LAN_BASEADR<3> 6 16 FB1_4 STD RESET
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LAN_BASEADR<2> 6 16 FB1_7 STD RESET
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LAN_BASEADR<12> 6 16 FB1_9 STD RESET
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LAN_BASEADR<11> 6 16 FB1_11 STD RESET
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LAN_BASEADR<10> 6 16 FB1_13 STD RESET
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LAN_BASEADR<0> 6 16 FB1_16 STD RESET
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CP_BASEADR<3> 6 17 FB1_18 STD RESET
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DQ<8>_BUFR 9 11 FB2_1 STD
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IDE_BASEADR<3> 6 18 FB2_4 STD RESET
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IDE_BASEADR<2> 6 18 FB2_7 STD RESET
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IDE_BASEADR<1> 6 18 FB2_9 STD RESET
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IDE_BASEADR<0> 6 18 FB2_13 STD RESET
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DQ_9_IOBUFE/DQ_9_IOBUFE_TRST 6 10 FB2_16 STD
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$OpTx$INV$438 15 15 FB3_1 STD
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SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF 2 2 FB3_3 STD
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CP_WE_QUIRK 2 2 FB3_4 STD RESET
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$OpTx$FX_DC$463 2 2 FB3_5 STD
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$OpTx$FX_DC$462 2 2 FB3_6 STD
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$OpTx$FX_DC$461 2 2 FB3_7 STD
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Z3_ADR<8> 3 3 FB3_8 STD RESET
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Z3_ADR<7> 3 3 FB3_9 STD RESET
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Z3_ADR<6> 3 3 FB3_10 STD RESET
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Z3_ADR<5> 3 3 FB3_11 STD RESET
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Z3_ADR<4> 3 3 FB3_12 STD RESET
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Z3_ADR<3> 3 3 FB3_13 STD RESET
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Z3_ADR<2> 3 3 FB3_16 STD RESET
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Z3_ADR<13> 3 3 FB3_17 STD RESET
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$OpTx$$OpTx$FX_DC$476_INV$1624 1 3 FB3_18 STD
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SHUT_UP_Z2<2> 4 17 FB4_1 STD SET
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IDE_BASEADR<7> 6 18 FB4_3 STD RESET
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IDE_BASEADR<6> 6 18 FB4_4 STD RESET
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IDE_BASEADR<5> 6 18 FB4_7 STD RESET
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IDE_BASEADR<4> 6 18 FB4_9 STD RESET
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CP_BASEADR<7> 6 17 FB4_10 STD RESET
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CP_BASEADR<6> 6 17 FB4_11 STD RESET
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CP_BASEADR<5> 6 17 FB4_13 STD RESET
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CP_BASEADR<4> 6 17 FB4_15 STD RESET
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Signal Total Total Loc Pwr Reg Init
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Name Pts Inps Mode State
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CP_BASEADR<2> 6 17 FB4_16 STD RESET
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CP_BASEADR<1> 6 17 FB4_17 STD RESET
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CP_BASEADR<0> 6 17 FB4_18 STD RESET
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$OpTx$INV$436 16 16 FB5_6 STD
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AUTOCONFIG_Z2_ACCESS 5 14 FB5_18 STD RESET
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LAN_RST_SM_FSM_FFd3 2 2 FB6_1 STD RESET
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LAN_RST_SM_FSM_FFd2 2 2 FB6_4 STD RESET
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LAN_IRQ_D0 2 2 FB6_7 STD RESET
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Z3_ADR<10> 3 3 FB6_9 STD RESET
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LAN_IRQ_OUT 3 4 FB6_11 STD RESET
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IDE_W_S 3 5 FB6_12 STD RESET
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IDE_ACCESS 4 5 FB6_13 STD RESET
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AUTO_CONFIG_Z2_DONE<2> 4 5 FB6_15 STD RESET
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AUTO_CONFIG_Z2_DONE<1> 4 5 FB6_16 STD RESET
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AUTO_CONFIG_Z2_DONE<0> 4 5 FB6_17 STD RESET
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$OpTx$INV$437 4 4 FB6_18 STD
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LAN_BASEADR<9> 6 16 FB7_1 STD RESET
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LAN_BASEADR<7> 6 16 FB7_4 STD RESET
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LAN_BASEADR<5> 6 16 FB7_8 STD RESET
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LAN_BASEADR<4> 6 16 FB7_9 STD RESET
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LAN_BASEADR<1> 6 16 FB7_10 STD RESET
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LAN_BASEADR<6> 6 16 FB7_14 STD RESET
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LAN_BASEADR<15> 6 16 FB7_15 STD RESET
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LAN_BASEADR<14> 6 16 FB7_16 STD RESET
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LAN_BASEADR<13> 6 16 FB7_17 STD RESET
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AUTO_CONFIG_Z2_DONE_CYCLE<2> 4 16 FB7_18 STD RESET
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DQ_DATA<0> 10 12 FB8_1 STD RESET
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DQ_DATA<12> 10 12 FB8_7 STD RESET
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DQ_DATA<14> 10 12 FB8_9 STD RESET
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DQ_DATA<4> 10 12 FB8_12 STD RESET
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DQ_DATA<6> 10 12 FB8_14 STD RESET
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DQ_DATA<8> 10 12 FB8_16 STD RESET
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LAN_SM_FSM_FFd8 4 9 FB8_17 STD RESET
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LAN_ACCESS 16 16 FB9_2 STD RESET
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LAN_SM_FSM_FFd13 1 1 FB9_3 STD SET
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LAN_SM_FSM_FFd2 2 2 FB9_4 STD RESET
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Z3_ADR<12> 3 3 FB9_5 STD RESET
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Z3_ADR<11> 3 3 FB9_6 STD RESET
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LAN_WRL_S 3 5 FB9_7 STD RESET
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LAN_WRH_S 3 5 FB9_8 STD RESET
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Signal Total Total Loc Pwr Reg Init
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Name Pts Inps Mode State
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LAN_SM_FSM_FFd7 3 5 FB9_9 STD RESET
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LAN_SM_FSM_FFd6 3 4 FB9_10 STD RESET
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LAN_SM_FSM_FFd3 3 5 FB9_12 STD RESET
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IDE_ENABLE 3 5 FB9_13 STD RESET
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DQ_SWAP 10 17 FB9_15 STD RESET
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LAN_SM_FSM_FFd4 2 2 FB9_16 STD RESET
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LAN_SM_FSM_FFd1 2 3 FB9_18 STD RESET
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DQ<4>_BUFR 9 11 FB10_1 STD
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$OpTx$FX_DC$1323 1 11 FB11_1 STD
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Z3_DATA<30> 4 5 FB11_2 STD RESET
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Z3_DATA<29> 4 5 FB11_4 STD RESET
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Z3_DATA<28> 4 5 FB11_6 STD RESET
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Z3_DATA<27> 4 5 FB11_7 STD RESET
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Z3_DATA<22> 4 5 FB11_8 STD RESET
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Z3_DATA<21> 4 5 FB11_9 STD RESET
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Z3_DATA<20> 4 5 FB11_13 STD RESET
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Z3_DATA<19> 4 5 FB11_15 STD RESET
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LAN_READY 4 10 FB11_16 STD RESET
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Z3_A_LOW 7 12 FB11_18 STD RESET
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DQ_DATA<11> 10 12 FB12_1 STD RESET
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Z3_DATA<9>/Z3_DATA<9>_SETF__$INT 4 8 FB12_3 STD
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LAN_SM_FSM_FFd10 3 7 FB12_4 STD RESET
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LAN_INT_ENABLE 4 11 FB12_6 STD RESET
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DQ_DATA<7> 10 12 FB12_14 STD RESET
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DQ_DATA<3> 10 12 FB12_16 STD RESET
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DQ_DATA<15> 10 12 FB12_18 STD RESET
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SHUT_UP_Z2<0> 4 15 FB13_1 STD SET
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AUTO_CONFIG_Z2_DONE_CYCLE<1> 4 15 FB13_3 STD RESET
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AUTO_CONFIG_Z2_DONE_CYCLE<0> 4 14 FB13_4 STD RESET
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D_Z2_OUT<3> 14 14 FB13_7 STD SET
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D_Z2_OUT<2> 16 14 FB13_10 STD SET
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D_Z2_OUT<0> 15 14 FB13_13 STD SET
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D_Z2_OUT<1> 16 15 FB13_17 STD SET
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LAN_A_INIT<3> 1 1 FB14_1 STD SET
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LAN_WR_RST 2 3 FB14_2 STD RESET
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LAN_RST_SM_FSM_FFd7 2 2 FB14_4 STD RESET
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LAN_RST_SM_FSM_FFd6 2 2 FB14_5 STD RESET
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LAN_RST_SM_FSM_FFd5 2 2 FB14_6 STD RESET
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LAN_RST_SM_FSM_FFd4 2 2 FB14_7 STD RESET
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LAN_RST_SM_FSM_FFd1 2 3 FB14_8 STD RESET
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Signal Total Total Loc Pwr Reg Init
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Name Pts Inps Mode State
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LAN_D_INIT<8> 2 5 FB14_9 STD RESET
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LAN_D_INIT<1> 2 5 FB14_10 STD RESET
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LAN_CS_RST 2 3 FB14_12 STD RESET
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LAN_A_INIT<6> 2 5 FB14_13 STD SET
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Z3_ADR_1 3 3 FB14_16 STD RESET
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Z3_ADR_0 3 3 FB14_17 STD RESET
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Z3_ADR<9> 3 3 FB14_18 STD RESET
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DQ_DATA<1> 10 12 FB15_1 STD RESET
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LAN_SM_FSM_FFd5 2 3 FB15_2 STD RESET
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DQ_DATA<13> 10 12 FB15_3 STD RESET
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ROM_OE_S 3 6 FB15_4 STD RESET
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LAN_SM_FSM_FFd11 3 6 FB15_5 STD RESET
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IDE_R_S 3 6 FB15_6 STD RESET
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CP_WE_S 3 6 FB15_7 STD RESET
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CP_RD_S 3 6 FB15_8 STD RESET
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LAN_RD_S 4 7 FB15_9 STD RESET
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DQ_DATA<9> 10 12 FB15_10 STD RESET
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|
LAN_SM_FSM_FFd9 3 6 FB15_11 STD RESET
|
|
DQ_DATA<5> 10 12 FB15_13 STD RESET
|
|
LAN_SM_FSM_FFd12 2 4 FB15_16 STD RESET
|
|
DQ_DATA<10> 10 12 FB16_1 STD RESET
|
|
DQ_DATA<2> 10 12 FB16_5 STD RESET
|
|
Z3_DATA<17> 4 5 FB16_7 STD RESET
|
|
Z3_DATA<18> 4 5 FB16_9 STD RESET
|
|
Z3_DATA<23> 4 5 FB16_12 STD RESET
|
|
Z3_DATA<24> 4 5 FB16_13 STD RESET
|
|
Z3_DATA<25> 4 5 FB16_14 STD RESET
|
|
Z3_DATA<26> 4 5 FB16_15 STD RESET
|
|
Z3_DATA<31> 4 5 FB16_16 STD RESET
|
|
Z3_DATA<16> 4 5 FB16_17 STD RESET
|
|
|
|
** 24 Inputs **
|
|
|
|
Signal Loc Pin Pin Pin
|
|
Name No. Type Use
|
|
CLK_EXT FB3_10 30 GCK/I/O GCK
|
|
CP_IRQ FB3_12 31 I/O I
|
|
RESET FB6_15 143 GSR/I/O I
|
|
A<5> FB7_15 49 I/O I
|
|
A<4> FB9_2 50 I/O I
|
|
A<6> FB9_3 51 I/O I
|
|
A<3> FB9_5 52 I/O I
|
|
A<7> FB9_6 53 I/O I
|
|
A<2> FB9_8 54 I/O I
|
|
A<1> FB9_12 57 I/O I
|
|
LAN_INT FB12_3 111 I/O I
|
|
AUTOBOOT_OFF FB13_11 75 I/O I
|
|
FCS FB13_15 77 I/O I
|
|
DS1 FB13_17 78 I/O I
|
|
C3 FB14_6 102 I/O I
|
|
C1 FB14_8 103 I/O I
|
|
CFIN FB14_10 104 I/O I
|
|
Z3 FB15_2 79 I/O I
|
|
AS FB15_3 80 I/O I
|
|
UDS FB15_8 81 I/O I
|
|
LDS FB15_10 82 I/O I
|
|
RW FB15_11 83 I/O I
|
|
DS0 FB16_5 93 I/O I
|
|
BERR FB16_12 98 I/O I
|
|
|
|
Legend:
|
|
Pin No. - ~ - User Assigned
|
|
************************** Function Block Details ************************
|
|
Legend:
|
|
Total Pt - Total product terms used by the macrocell signal
|
|
Imp Pt - Product terms imported from other macrocells
|
|
Exp Pt - Product terms exported to other macrocells
|
|
in direction shown
|
|
Unused Pt - Unused local product terms remaining in macrocell
|
|
Loc - Location where logic was mapped in device
|
|
Pin Type/Use - I - Input GCK - Global Clock
|
|
O - Output GTS - Global Output Enable
|
|
(b) - Buried macrocell GSR - Global Set/Reset
|
|
X - Signal used as input to the macrocell logic.
|
|
Pin No. - ~ - User Assigned
|
|
*********************************** FB1 ***********************************
|
|
Number of function block inputs used/remaining: 42/12
|
|
Number of signals used by logic mapping into function block: 42
|
|
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
|
Name Pt Pt Pt Pt # Type Use
|
|
SHUT_UP_Z2<1> 4 0 \/1 0 FB1_1 (b) (b)
|
|
LAN_BASEADR<8> 6 1<- 0 0 FB1_2 (b) (b)
|
|
D_9_IOBUFE/D_9_IOBUFE_TRST
|
|
3 0 \/2 0 FB1_3 (b) (b)
|
|
LAN_BASEADR<3> 6 2<- \/1 0 FB1_4 (b) (b)
|
|
D<5> 7 2<- 0 0 FB1_5 20 I/O I/O
|
|
D<4> 7 3<- /\1 0 FB1_6 21 I/O I/O
|
|
LAN_BASEADR<2> 6 4<- /\3 0 FB1_7 (b) (b)
|
|
IDE_CS<0> 1 0 /\4 0 FB1_8 22 I/O O
|
|
LAN_BASEADR<12> 6 1<- 0 0 FB1_9 (b) (b)
|
|
IDE_CS<1> 1 0 /\1 3 FB1_10 23 I/O O
|
|
LAN_BASEADR<11> 6 1<- 0 0 FB1_11 (b) (b)
|
|
IDE_A<0> 1 0 /\1 3 FB1_12 24 I/O O
|
|
LAN_BASEADR<10> 6 1<- 0 0 FB1_13 (b) (b)
|
|
IDE_A<2> 1 0 /\1 3 FB1_14 25 I/O O
|
|
IDE_A<1> 1 0 \/1 3 FB1_15 26 I/O O
|
|
LAN_BASEADR<0> 6 1<- 0 0 FB1_16 (b) (b)
|
|
IDE_R 1 0 \/1 3 FB1_17 27 I/O O
|
|
CP_BASEADR<3> 6 1<- 0 0 FB1_18 (b) (b)
|
|
|
|
Signals Used by Logic in Function Block
|
|
1: AS 15: A<9>.PIN 29: DQ<5>.PIN
|
|
2: AUTOCONFIG_Z2_ACCESS 16: A<10>.PIN 30: DQ<4>.PIN
|
|
3: AUTO_CONFIG_Z2_DONE<0> 17: A<11>.PIN 31: A<13>.PIN
|
|
4: AUTO_CONFIG_Z2_DONE<1> 18: IDE_R_S 32: D<12>.PIN
|
|
5: A<1> 19: LAN_ACCESS 33: D<11>.PIN
|
|
6: A<2> 20: LAN_BASEADR<0> 34: D<10>.PIN
|
|
7: A<3> 21: LAN_BASEADR<10> 35: D<8>.PIN
|
|
8: A<4> 22: LAN_BASEADR<11> 36: RESET
|
|
9: A<5> 23: LAN_BASEADR<12> 37: RW
|
|
10: A<6> 24: LAN_BASEADR<2> 38: SHUT_UP_Z2<1>
|
|
11: CP_BASEADR<3> 25: LAN_BASEADR<3> 39: SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF
|
|
12: CP_CS 26: LAN_BASEADR<8> 40: UDS
|
|
13: D_9_IOBUFE/D_9_IOBUFE_TRST 27: LDS 41: Z3_DATA<20>
|
|
14: FCS 28: A<12>.PIN 42: Z3_DATA<21>
|
|
|
|
Signal 1 2 3 4 5 FB
|
|
Name 0----+----0----+----0----+----0----+----0----+----0 Inputs
|
|
SHUT_UP_Z2<1> XXXXXXXXXX................X........XXXXX.......... 16
|
|
LAN_BASEADR<8> XX.XXXXXXX...............XX.......XXX.XX.......... 16
|
|
D_9_IOBUFE/D_9_IOBUFE_TRST
|
|
XX.........X.X....X.................X............. 6
|
|
LAN_BASEADR<3> XXX.XXXXXX..............X.X.....X..XX.XX.......... 16
|
|
D<5> XX..........XX....X.........X.......X....X........ 8
|
|
D<4> XX..........XX....X..........X......X...X......... 8
|
|
LAN_BASEADR<2> XXX.XXXXXX.............X..X......X.XX.XX.......... 16
|
|
IDE_CS<0> ...........................X...................... 1
|
|
LAN_BASEADR<12> XX.XXXXXXX............X...X....X...XX.XX.......... 16
|
|
IDE_CS<1> ..............................X................... 1
|
|
LAN_BASEADR<11> XX.XXXXXXX...........X....X.....X..XX.XX.......... 16
|
|
IDE_A<0> ..............X................................... 1
|
|
LAN_BASEADR<10> XX.XXXXXXX..........X.....X......X.XX.XX.......... 16
|
|
IDE_A<2> ................X................................. 1
|
|
IDE_A<1> ...............X.................................. 1
|
|
LAN_BASEADR<0> XXX.XXXXXX.........X......X.......XXX.XX.......... 16
|
|
IDE_R X................X................................ 2
|
|
CP_BASEADR<3> XXXXXXXXXXX...............X.....X..XX.XX.......... 17
|
|
0----+----1----+----2----+----3----+----4----+----5
|
|
0 0 0 0 0
|
|
*********************************** FB2 ***********************************
|
|
Number of function block inputs used/remaining: 46/8
|
|
Number of signals used by logic mapping into function block: 46
|
|
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
|
Name Pt Pt Pt Pt # Type Use
|
|
DQ<8>_BUFR 9 4<- 0 0 FB2_1 (b) (b)
|
|
A_LAN<4> 2 1<- /\4 0 FB2_2 9 I/O O
|
|
A_LAN<7> 1 0 /\1 3 FB2_3 10 I/O O
|
|
IDE_BASEADR<3> 6 1<- 0 0 FB2_4 (b) (b)
|
|
A_LAN<6> 2 0 /\1 2 FB2_5 11 I/O O
|
|
LAN_CFG<1> 0 0 \/1 4 FB2_6 12 I/O O
|
|
IDE_BASEADR<2> 6 1<- 0 0 FB2_7 (b) (b)
|
|
LAN_CFG<3> 0 0 \/3 2 FB2_8 13 I/O O
|
|
IDE_BASEADR<1> 6 3<- \/2 0 FB2_9 (b) (b)
|
|
D<6> 7 2<- 0 0 FB2_10 14 I/O I/O
|
|
(unused) 0 0 \/5 0 FB2_11 (b) (b)
|
|
D<3> 7 5<- \/3 0 FB2_12 15 I/O I/O
|
|
IDE_BASEADR<0> 6 3<- \/2 0 FB2_13 (b) (b)
|
|
D<7> 7 2<- 0 0 FB2_14 16 I/O I/O
|
|
D<1> 7 2<- 0 0 FB2_15 17 I/O I/O
|
|
DQ_9_IOBUFE/DQ_9_IOBUFE_TRST
|
|
6 3<- /\2 0 FB2_16 (b) (b)
|
|
D<8> 7 5<- /\3 0 FB2_17 19 I/O I/O
|
|
(unused) 0 0 /\5 0 FB2_18 (b) (b)
|
|
|
|
Signals Used by Logic in Function Block
|
|
1: AS 17: FCS 32: D<10>.PIN
|
|
2: AUTOCONFIG_Z2_ACCESS 18: IDE_BASEADR<0> 33: D<9>.PIN
|
|
3: AUTO_CONFIG_Z2_DONE<0> 19: IDE_BASEADR<1> 34: D<8>.PIN
|
|
4: AUTO_CONFIG_Z2_DONE<1> 20: IDE_BASEADR<2> 35: RESET
|
|
5: AUTO_CONFIG_Z2_DONE<2> 21: IDE_BASEADR<3> 36: RW
|
|
6: A<1> 22: LAN_ACCESS 37: SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF
|
|
7: A<2> 23: LAN_A_INIT<6> 38: UDS
|
|
8: A<3> 24: LAN_D_INIT<8> 39: Z3_ADR<3>
|
|
9: A<4> 25: LDS 40: Z3_ADR<5>
|
|
10: A<5> 26: DQ<7>.PIN 41: Z3_ADR<6>
|
|
11: A<6> 27: DQ<6>.PIN 42: Z3_DATA<17>
|
|
12: CP_CS 28: DQ<3>.PIN 43: Z3_DATA<19>
|
|
13: DQ_DATA<8> 29: DQ<1>.PIN 44: Z3_DATA<22>
|
|
14: DS0 30: DQ<0>.PIN 45: Z3_DATA<23>
|
|
15: DS1 31: D<11>.PIN 46: Z3_DATA<24>
|
|
16: D_9_IOBUFE/D_9_IOBUFE_TRST
|
|
|
|
Signal 1 2 3 4 5 FB
|
|
Name 0----+----0----+----0----+----0----+----0----+----0 Inputs
|
|
DQ<8>_BUFR ............XXX.X....X.XX........XXX.X............ 11
|
|
A_LAN<4> ........X..X......................X...X........... 4
|
|
A_LAN<7> ..................................X.....X......... 2
|
|
IDE_BASEADR<3> XXXXXXXXXXX.........X...X.....X...XXXX............ 18
|
|
A_LAN<6> ......................X...........X....X.......... 3
|
|
LAN_CFG<1> .................................................. 0
|
|
IDE_BASEADR<2> XXXXXXXXXXX........X....X......X..XXXX............ 18
|
|
LAN_CFG<3> .................................................. 0
|
|
IDE_BASEADR<1> XXXXXXXXXXX.......X.....X.......X.XXXX............ 18
|
|
D<6> XX.............XX....X....X........X.......X...... 8
|
|
D<3> XX.............XX....X.....X.......X......X....... 8
|
|
IDE_BASEADR<0> XXXXXXXXXXX......X......X........XXXXX............ 18
|
|
D<7> XX.............XX....X...X.........X........X..... 8
|
|
D<1> XX.............XX....X......X......X.....X........ 8
|
|
DQ_9_IOBUFE/DQ_9_IOBUFE_TRST
|
|
X..........X.XX.X....X..X.........XX.X............ 10
|
|
D<8> XX.............XX....X.......X.....X.........X.... 8
|
|
0----+----1----+----2----+----3----+----4----+----5
|
|
0 0 0 0 0
|
|
*********************************** FB3 ***********************************
|
|
Number of function block inputs used/remaining: 41/13
|
|
Number of signals used by logic mapping into function block: 41
|
|
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
|
Name Pt Pt Pt Pt # Type Use
|
|
$OpTx$INV$438 15 10<- 0 0 FB3_1 (b) (b)
|
|
IDE_W 1 1<- /\5 0 FB3_2 28 I/O O
|
|
SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF
|
|
2 0 /\1 2 FB3_3 (b) (b)
|
|
CP_WE_QUIRK 2 0 0 3 FB3_4 (b) (b)
|
|
$OpTx$FX_DC$463 2 0 0 3 FB3_5 (b) (b)
|
|
$OpTx$FX_DC$462 2 0 0 3 FB3_6 (b) (b)
|
|
$OpTx$FX_DC$461 2 0 0 3 FB3_7 (b) (b)
|
|
Z3_ADR<8> 3 0 0 2 FB3_8 (b) (b)
|
|
Z3_ADR<7> 3 0 0 2 FB3_9 (b) (b)
|
|
Z3_ADR<6> 3 0 0 2 FB3_10 30 GCK/I/O GCK
|
|
Z3_ADR<5> 3 0 0 2 FB3_11 (b) (b)
|
|
Z3_ADR<4> 3 0 0 2 FB3_12 31 I/O I
|
|
Z3_ADR<3> 3 0 0 2 FB3_13 (b) (b)
|
|
INT2_OUT 1 0 0 4 FB3_14 32 GCK/I/O O
|
|
ROM_B<0> 0 0 0 5 FB3_15 33 I/O O
|
|
Z3_ADR<2> 3 0 0 2 FB3_16 (b) (b)
|
|
Z3_ADR<13> 3 0 \/1 1 FB3_17 (b) (b)
|
|
$OpTx$$OpTx$FX_DC$476_INV$1624
|
|
1 1<- \/5 0 FB3_18 (b) (b)
|
|
|
|
Signals Used by Logic in Function Block
|
|
1: AS 15: IDE_BASEADR<1> 29: A<18>.PIN
|
|
2: A<1> 16: IDE_BASEADR<2> 30: A<19>.PIN
|
|
3: A<2> 17: IDE_BASEADR<3> 31: A<8>.PIN
|
|
4: A<4> 18: IDE_BASEADR<4> 32: D<15>.PIN
|
|
5: A<5> 19: IDE_BASEADR<5> 33: D<12>.PIN
|
|
6: A<6> 20: IDE_BASEADR<7> 34: D<11>.PIN
|
|
7: A<7> 21: IDE_W_S 35: A<20>.PIN
|
|
8: C1 22: LAN_BASEADR<11> 36: A<15>.PIN
|
|
9: C3 23: LAN_BASEADR<12> 37: A<21>.PIN
|
|
10: CP_WE_S 24: LAN_BASEADR<15> 38: A<16>.PIN
|
|
11: FCS 25: LAN_INT_ENABLE 39: RESET
|
|
12: A<9>.PIN 26: LAN_IRQ_OUT 40: SHUT_UP_Z2<2>
|
|
13: A<10>.PIN 27: A<17>.PIN 41: SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF
|
|
14: IDE_BASEADR<0> 28: A<23>.PIN
|
|
|
|
Signal 1 2 3 4 5 FB
|
|
Name 0----+----0----+----0----+----0----+----0----+----0 Inputs
|
|
$OpTx$INV$438 .............XXXXXXX......XXXX....X.XX.X.......... 15
|
|
IDE_W X...................X............................. 2
|
|
SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF
|
|
.......XX......................................... 2
|
|
CP_WE_QUIRK .........X..............................X......... 2
|
|
$OpTx$FX_DC$463 .......................X.......X.................. 2
|
|
$OpTx$FX_DC$462 ......................X.........X................. 2
|
|
$OpTx$FX_DC$461 .....................X...........X................ 2
|
|
Z3_ADR<8> ..........X.X.........................X........... 3
|
|
Z3_ADR<7> ..........XX..........................X........... 3
|
|
Z3_ADR<6> ..........X...................X.......X........... 3
|
|
Z3_ADR<5> ......X...X...........................X........... 3
|
|
Z3_ADR<4> .....X....X...........................X........... 3
|
|
Z3_ADR<3> ....X.....X...........................X........... 3
|
|
INT2_OUT ........................XX........................ 2
|
|
ROM_B<0> .................................................. 0
|
|
Z3_ADR<2> ...X......X...........................X........... 3
|
|
Z3_ADR<13> ..........X........................X..X........... 3
|
|
$OpTx$$OpTx$FX_DC$476_INV$1624
|
|
.XXX.............................................. 3
|
|
0----+----1----+----2----+----3----+----4----+----5
|
|
0 0 0 0 0
|
|
*********************************** FB4 ***********************************
|
|
Number of function block inputs used/remaining: 47/7
|
|
Number of signals used by logic mapping into function block: 47
|
|
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
|
Name Pt Pt Pt Pt # Type Use
|
|
SHUT_UP_Z2<2> 4 0 /\1 0 FB4_1 (b) (b)
|
|
D<0> 7 2<- 0 0 FB4_2 2 GTS/I/O I/O
|
|
IDE_BASEADR<7> 6 3<- /\2 0 FB4_3 (b) (b)
|
|
IDE_BASEADR<6> 6 4<- /\3 0 FB4_4 (b) (b)
|
|
A_LAN<1> 1 0 /\4 0 FB4_5 3 GTS/I/O O
|
|
A_LAN<0> 1 0 \/2 2 FB4_6 4 I/O O
|
|
IDE_BASEADR<5> 6 2<- \/1 0 FB4_7 (b) (b)
|
|
A_LAN<3> 3 1<- \/3 0 FB4_8 5 GTS/I/O O
|
|
IDE_BASEADR<4> 6 3<- \/2 0 FB4_9 (b) (b)
|
|
CP_BASEADR<7> 6 2<- \/1 0 FB4_10 (b) (b)
|
|
CP_BASEADR<6> 6 1<- 0 0 FB4_11 (b) (b)
|
|
A_LAN<2> 2 0 \/1 2 FB4_12 6 GTS/I/O O
|
|
CP_BASEADR<5> 6 1<- 0 0 FB4_13 (b) (b)
|
|
A_LAN<5> 2 0 \/3 0 FB4_14 7 I/O O
|
|
CP_BASEADR<4> 6 3<- \/2 0 FB4_15 (b) (b)
|
|
CP_BASEADR<2> 6 2<- \/1 0 FB4_16 (b) (b)
|
|
CP_BASEADR<1> 6 1<- 0 0 FB4_17 (b) (b)
|
|
CP_BASEADR<0> 6 1<- 0 0 FB4_18 (b) (b)
|
|
|
|
Signals Used by Logic in Function Block
|
|
1: AS 17: CP_BASEADR<6> 33: D<12>.PIN
|
|
2: AUTOCONFIG_Z2_ACCESS 18: CP_BASEADR<7> 34: D<10>.PIN
|
|
3: AUTO_CONFIG_Z2_DONE<0> 19: CP_CS 35: D<9>.PIN
|
|
4: AUTO_CONFIG_Z2_DONE<1> 20: D_9_IOBUFE/D_9_IOBUFE_TRST 36: D<8>.PIN
|
|
5: AUTO_CONFIG_Z2_DONE<2> 21: FCS 37: RESET
|
|
6: A<1> 22: IDE_BASEADR<4> 38: RW
|
|
7: A<2> 23: IDE_BASEADR<5> 39: SHUT_UP_Z2<2>
|
|
8: A<3> 24: IDE_BASEADR<6> 40: SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF
|
|
9: A<4> 25: IDE_BASEADR<7> 41: UDS
|
|
10: A<5> 26: LAN_ACCESS 42: Z3_ADR<2>
|
|
11: A<6> 27: LAN_A_INIT<3> 43: Z3_ADR<4>
|
|
12: CP_BASEADR<0> 28: LDS 44: Z3_ADR_0
|
|
13: CP_BASEADR<1> 29: DQ<0>.PIN 45: Z3_ADR_1
|
|
14: CP_BASEADR<2> 30: D<15>.PIN 46: Z3_A_LOW
|
|
15: CP_BASEADR<4> 31: D<14>.PIN 47: Z3_DATA<16>
|
|
16: CP_BASEADR<5> 32: D<13>.PIN
|
|
|
|
Signal 1 2 3 4 5 FB
|
|
Name 0----+----0----+----0----+----0----+----0----+----0 Inputs
|
|
SHUT_UP_Z2<2> XXXXXXXXXXX................X........XXXXX......... 17
|
|
D<0> XX.................XX....X..X........X........X... 8
|
|
IDE_BASEADR<7> XXXXXXXXXXX.............X..X.X......XX.XX......... 18
|
|
IDE_BASEADR<6> XXXXXXXXXXX............X...X..X.....XX.XX......... 18
|
|
A_LAN<1> ....................................X......X...... 2
|
|
A_LAN<0> ....................................X........X.... 2
|
|
IDE_BASEADR<5> XXXXXXXXXXX...........X....X...X....XX.XX......... 18
|
|
A_LAN<3> .......X..........X.......X.........X....X........ 5
|
|
IDE_BASEADR<4> XXXXXXXXXXX..........X.....X....X...XX.XX......... 18
|
|
CP_BASEADR<7> XXXX.XXXXXX......X.........X.X......XX.XX......... 17
|
|
CP_BASEADR<6> XXXX.XXXXXX.....X..........X..X.....XX.XX......... 17
|
|
A_LAN<2> ......X...........X.................X.......X..... 4
|
|
CP_BASEADR<5> XXXX.XXXXXX....X...........X...X....XX.XX......... 17
|
|
A_LAN<5> .........X........X.................X.....X....... 4
|
|
CP_BASEADR<4> XXXX.XXXXXX...X............X....X...XX.XX......... 17
|
|
CP_BASEADR<2> XXXX.XXXXXX..X.............X.....X..XX.XX......... 17
|
|
CP_BASEADR<1> XXXX.XXXXXX.X..............X......X.XX.XX......... 17
|
|
CP_BASEADR<0> XXXX.XXXXXXX...............X.......XXX.XX......... 17
|
|
0----+----1----+----2----+----3----+----4----+----5
|
|
0 0 0 0 0
|
|
*********************************** FB5 ***********************************
|
|
Number of function block inputs used/remaining: 49/5
|
|
Number of signals used by logic mapping into function block: 49
|
|
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
|
Name Pt Pt Pt Pt # Type Use
|
|
(unused) 0 0 \/5 0 FB5_1 (b) (b)
|
|
CP_CS 19 14<- 0 0 FB5_2 34 I/O O
|
|
(unused) 0 0 /\5 0 FB5_3 (b) (b)
|
|
(unused) 0 0 /\4 1 FB5_4 (b) (b)
|
|
ROM_OE 1 0 \/4 0 FB5_5 35 I/O O
|
|
$OpTx$INV$436 16 11<- 0 0 FB5_6 (b) (b)
|
|
(unused) 0 0 /\5 0 FB5_7 (b) (b)
|
|
(unused) 0 0 /\2 3 FB5_8 38 GCK/I/O (b)
|
|
(unused) 0 0 \/2 3 FB5_9 (b) (b)
|
|
D<2> 7 2<- 0 0 FB5_10 39 I/O I/O
|
|
(unused) 0 0 \/2 3 FB5_11 (b) (b)
|
|
D<9> 7 2<- 0 0 FB5_12 40 I/O I/O
|
|
(unused) 0 0 \/4 1 FB5_13 (b) (b)
|
|
D<10> 7 4<- \/2 0 FB5_14 41 I/O I/O
|
|
D<11> 7 2<- 0 0 FB5_15 43 I/O I/O
|
|
(unused) 0 0 \/4 1 FB5_16 (b) (b)
|
|
D<12> 9 4<- 0 0 FB5_17 44 I/O I/O
|
|
AUTOCONFIG_Z2_ACCESS
|
|
5 0 0 0 FB5_18 (b) (b)
|
|
|
|
Signals Used by Logic in Function Block
|
|
1: AS 18: FCS 34: DQ<2>.PIN
|
|
2: AUTOBOOT_OFF 19: LAN_ACCESS 35: DQ<1>.PIN
|
|
3: AUTOCONFIG_Z2_ACCESS 20: LAN_BASEADR<0> 36: D<14>.PIN
|
|
4: AUTO_CONFIG_Z2_DONE<0> 21: LAN_BASEADR<14> 37: A<20>.PIN
|
|
5: AUTO_CONFIG_Z2_DONE<1> 22: LAN_BASEADR<1> 38: A<21>.PIN
|
|
6: AUTO_CONFIG_Z2_DONE<2> 23: LAN_BASEADR<2> 39: A<16>.PIN
|
|
7: CFIN 24: LAN_BASEADR<3> 40: A<22>.PIN
|
|
8: CP_BASEADR<0> 25: LAN_BASEADR<4> 41: RESET
|
|
9: CP_BASEADR<1> 26: LAN_BASEADR<5> 42: ROM_OE_S
|
|
10: CP_BASEADR<2> 27: LAN_BASEADR<7> 43: RW
|
|
11: CP_BASEADR<3> 28: A<17>.PIN 44: SHUT_UP_Z2<1>
|
|
12: CP_BASEADR<4> 29: A<23>.PIN 45: Z3_DATA<18>
|
|
13: CP_BASEADR<5> 30: A<18>.PIN 46: Z3_DATA<25>
|
|
14: CP_BASEADR<6> 31: A<19>.PIN 47: Z3_DATA<26>
|
|
15: CP_BASEADR<7> 32: DQ<4>.PIN 48: Z3_DATA<27>
|
|
16: D_9_IOBUFE/D_9_IOBUFE_TRST 33: DQ<3>.PIN 49: Z3_DATA<28>
|
|
17: D_Z2_OUT<0>
|
|
|
|
Signal 1 2 3 4 5 FB
|
|
Name 0----+----0----+----0----+----0----+----0----+----0 Inputs
|
|
CP_CS X......XXXXXXXX............XXXX.....XXXXX..X...... 19
|
|
ROM_OE XX.......................................X........ 3
|
|
$OpTx$INV$436 ...................XXXXXXXXXXXX....XXXX........... 16
|
|
D<2> X.X............X.XX..............X........X.X..... 8
|
|
D<9> X.X............X.XX...............X.......X..X.... 8
|
|
D<10> X.X............X.XX..............X........X...X... 8
|
|
D<11> X.X............X.XX.............X.........X....X.. 8
|
|
D<12> X.X............XXXX............X..........X.....X. 9
|
|
AUTOCONFIG_Z2_ACCESS
|
|
X..XXXX....................XXXX.....XXXXX......... 14
|
|
0----+----1----+----2----+----3----+----4----+----5
|
|
0 0 0 0 0
|
|
*********************************** FB6 ***********************************
|
|
Number of function block inputs used/remaining: 30/24
|
|
Number of signals used by logic mapping into function block: 30
|
|
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
|
Name Pt Pt Pt Pt # Type Use
|
|
LAN_RST_SM_FSM_FFd3 2 0 0 3 FB6_1 (b) (b)
|
|
LAN_CFG<2> 0 0 0 5 FB6_2 135 I/O O
|
|
A_LAN<12> 1 0 0 4 FB6_3 136 I/O O
|
|
LAN_RST_SM_FSM_FFd2 2 0 0 3 FB6_4 (b) (b)
|
|
A_LAN<13> 1 0 0 4 FB6_5 137 I/O O
|
|
A_LAN<10> 1 0 0 4 FB6_6 138 I/O O
|
|
LAN_IRQ_D0 2 0 0 3 FB6_7 (b) (b)
|
|
A_LAN<11> 1 0 0 4 FB6_8 139 I/O O
|
|
Z3_ADR<10> 3 0 0 2 FB6_9 (b) (b)
|
|
A_LAN<8> 1 0 0 4 FB6_10 140 I/O O
|
|
LAN_IRQ_OUT 3 0 0 2 FB6_11 (b) (b)
|
|
IDE_W_S 3 0 0 2 FB6_12 (b) (b)
|
|
IDE_ACCESS 4 0 0 1 FB6_13 (b) (b)
|
|
A_LAN<9> 1 0 0 4 FB6_14 142 I/O O
|
|
AUTO_CONFIG_Z2_DONE<2>
|
|
4 0 0 1 FB6_15 143 GSR/I/O I
|
|
AUTO_CONFIG_Z2_DONE<1>
|
|
4 0 0 1 FB6_16 (b) (b)
|
|
AUTO_CONFIG_Z2_DONE<0>
|
|
4 0 0 1 FB6_17 (b) (b)
|
|
$OpTx$INV$437 4 0 0 1 FB6_18 (b) (b)
|
|
|
|
Signals Used by Logic in Function Block
|
|
1: $OpTx$INV$438 11: IDE_BASEADR<6> 21: A<22>.PIN
|
|
2: AS 12: LAN_BASEADR<13> 22: RESET
|
|
3: AUTO_CONFIG_Z2_DONE<0> 13: LAN_BASEADR<6> 23: RW
|
|
4: AUTO_CONFIG_Z2_DONE<1> 14: LAN_INT 24: SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF
|
|
5: AUTO_CONFIG_Z2_DONE<2> 15: LAN_IRQ_D0 25: Z3_ADR<10>
|
|
6: AUTO_CONFIG_Z2_DONE_CYCLE<0> 16: LAN_IRQ_OUT 26: Z3_ADR<11>
|
|
7: AUTO_CONFIG_Z2_DONE_CYCLE<1> 17: LAN_RST_SM_FSM_FFd3 27: Z3_ADR<12>
|
|
8: AUTO_CONFIG_Z2_DONE_CYCLE<2> 18: LAN_RST_SM_FSM_FFd4 28: Z3_ADR<7>
|
|
9: FCS 19: A<12>.PIN 29: Z3_ADR<8>
|
|
10: IDE_ACCESS 20: D<13>.PIN 30: Z3_ADR<9>
|
|
|
|
Signal 1 2 3 4 FB
|
|
Name 0----+----0----+----0----+----0----+----0 Inputs
|
|
LAN_RST_SM_FSM_FFd3 .................X...X.................. 2
|
|
LAN_CFG<2> ........................................ 0
|
|
A_LAN<12> .....................X...X.............. 2
|
|
LAN_RST_SM_FSM_FFd2 ................X....X.................. 2
|
|
A_LAN<13> .....................X....X............. 2
|
|
A_LAN<10> .....................X.......X.......... 2
|
|
LAN_IRQ_D0 .............X.......X.................. 2
|
|
A_LAN<11> .....................X..X............... 2
|
|
Z3_ADR<10> ........X.........X..X.................. 3
|
|
A_LAN<8> .....................X.....X............ 2
|
|
LAN_IRQ_OUT .............XXX.....X.................. 4
|
|
IDE_W_S .X.......X...........XXX................ 5
|
|
IDE_ACCESS XX........X.........XX.................. 5
|
|
A_LAN<9> .....................X......X........... 2
|
|
AUTO_CONFIG_Z2_DONE<2>
|
|
.X..X..X.............X.X................ 5
|
|
AUTO_CONFIG_Z2_DONE<1>
|
|
.X.X..X..............X.X................ 5
|
|
AUTO_CONFIG_Z2_DONE<0>
|
|
.XX..X...............X.X................ 5
|
|
$OpTx$INV$437 ...........XX......XX................... 4
|
|
0----+----1----+----2----+----3----+----4
|
|
0 0 0 0
|
|
*********************************** FB7 ***********************************
|
|
Number of function block inputs used/remaining: 43/11
|
|
Number of signals used by logic mapping into function block: 43
|
|
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
|
Name Pt Pt Pt Pt # Type Use
|
|
LAN_BASEADR<9> 6 1<- 0 0 FB7_1 (b) (b)
|
|
(unused) 0 0 \/5 0 FB7_2 (b) (b)
|
|
D<13> 9 5<- \/1 0 FB7_3 45 I/O I/O
|
|
LAN_BASEADR<7> 6 1<- 0 0 FB7_4 (b) (b)
|
|
D<14> 9 4<- 0 0 FB7_5 46 I/O I/O
|
|
(unused) 0 0 /\4 1 FB7_6 (b) (b)
|
|
(unused) 0 0 \/3 2 FB7_7 (b) (b)
|
|
LAN_BASEADR<5> 6 3<- \/2 0 FB7_8 (b) (b)
|
|
LAN_BASEADR<4> 6 2<- \/1 0 FB7_9 (b) (b)
|
|
LAN_BASEADR<1> 6 1<- 0 0 FB7_10 (b) (b)
|
|
(unused) 0 0 \/4 1 FB7_11 (b) (b)
|
|
D<15> 9 4<- 0 0 FB7_12 48 I/O I/O
|
|
(unused) 0 0 \/4 1 FB7_13 (b) (b)
|
|
LAN_BASEADR<6> 6 4<- \/3 0 FB7_14 (b) (b)
|
|
LAN_BASEADR<15> 6 3<- \/2 0 FB7_15 49 I/O I
|
|
LAN_BASEADR<14> 6 2<- \/1 0 FB7_16 (b) (b)
|
|
LAN_BASEADR<13> 6 1<- 0 0 FB7_17 (b) (b)
|
|
AUTO_CONFIG_Z2_DONE_CYCLE<2>
|
|
4 0 \/1 0 FB7_18 (b) (b)
|
|
|
|
Signals Used by Logic in Function Block
|
|
1: AS 16: D_Z2_OUT<3> 30: DQ<6>.PIN
|
|
2: AUTOCONFIG_Z2_ACCESS 17: FCS 31: DQ<5>.PIN
|
|
3: AUTO_CONFIG_Z2_DONE<0> 18: LAN_ACCESS 32: D<15>.PIN
|
|
4: AUTO_CONFIG_Z2_DONE<1> 19: LAN_BASEADR<13> 33: D<14>.PIN
|
|
5: AUTO_CONFIG_Z2_DONE<2> 20: LAN_BASEADR<14> 34: D<13>.PIN
|
|
6: AUTO_CONFIG_Z2_DONE_CYCLE<2> 21: LAN_BASEADR<15> 35: D<12>.PIN
|
|
7: A<1> 22: LAN_BASEADR<1> 36: D<9>.PIN
|
|
8: A<2> 23: LAN_BASEADR<4> 37: RESET
|
|
9: A<3> 24: LAN_BASEADR<5> 38: RW
|
|
10: A<4> 25: LAN_BASEADR<6> 39: SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF
|
|
11: A<5> 26: LAN_BASEADR<7> 40: UDS
|
|
12: A<6> 27: LAN_BASEADR<9> 41: Z3_DATA<29>
|
|
13: D_9_IOBUFE/D_9_IOBUFE_TRST 28: LDS 42: Z3_DATA<30>
|
|
14: D_Z2_OUT<1> 29: DQ<7>.PIN 43: Z3_DATA<31>
|
|
15: D_Z2_OUT<2>
|
|
|
|
Signal 1 2 3 4 5 FB
|
|
Name 0----+----0----+----0----+----0----+----0----+----0 Inputs
|
|
LAN_BASEADR<9> XX.X..XXXXXX..............XX.......XXXXX.......... 16
|
|
D<13> XX..........XX..XX............X......X..X......... 9
|
|
LAN_BASEADR<7> XXX...XXXXXX.............X.X...X....XXXX.......... 16
|
|
D<14> XX..........X.X.XX...........X.......X...X........ 9
|
|
LAN_BASEADR<5> XXX...XXXXXX...........X...X.....X..XXXX.......... 16
|
|
LAN_BASEADR<4> XXX...XXXXXX..........X....X......X.XXXX.......... 16
|
|
LAN_BASEADR<1> XXX...XXXXXX.........X.....X.......XXXXX.......... 16
|
|
D<15> XX..........X..XXX..........X........X....X....... 9
|
|
LAN_BASEADR<6> XXX...XXXXXX............X..X....X...XXXX.......... 16
|
|
LAN_BASEADR<15> XX.X..XXXXXX........X......X...X....XXXX.......... 16
|
|
LAN_BASEADR<14> XX.X..XXXXXX.......X.......X....X...XXXX.......... 16
|
|
LAN_BASEADR<13> XX.X..XXXXXX......X........X.....X..XXXX.......... 16
|
|
AUTO_CONFIG_Z2_DONE_CYCLE<2>
|
|
XXXXXXX.XXXX...............X........XXXX.......... 16
|
|
0----+----1----+----2----+----3----+----4----+----5
|
|
0 0 0 0 0
|
|
*********************************** FB8 ***********************************
|
|
Number of function block inputs used/remaining: 37/17
|
|
Number of signals used by logic mapping into function block: 37
|
|
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
|
Name Pt Pt Pt Pt # Type Use
|
|
DQ_DATA<0> 10 6<- \/1 0 FB8_1 (b) (b)
|
|
DQ<12> 9 4<- 0 0 FB8_2 130 I/O I/O
|
|
DQ<14> 9 7<- /\3 0 FB8_3 131 I/O I/O
|
|
(unused) 0 0 /\5 0 FB8_4 (b) (b)
|
|
LAN_WRH 3 0 /\2 0 FB8_5 132 I/O O
|
|
(unused) 0 0 \/5 0 FB8_6 (b) (b)
|
|
DQ_DATA<12> 10 5<- 0 0 FB8_7 (b) (b)
|
|
LAN_CS 3 0 \/2 0 FB8_8 133 I/O O
|
|
DQ_DATA<14> 10 5<- 0 0 FB8_9 (b) (b)
|
|
LAN_RD 1 0 /\3 1 FB8_10 134 I/O O
|
|
(unused) 0 0 \/5 0 FB8_11 (b) (b)
|
|
DQ_DATA<4> 10 5<- 0 0 FB8_12 (b) (b)
|
|
(unused) 0 0 \/5 0 FB8_13 (b) (b)
|
|
DQ_DATA<6> 10 5<- 0 0 FB8_14 (b) (b)
|
|
(unused) 0 0 \/5 0 FB8_15 (b) (b)
|
|
DQ_DATA<8> 10 5<- 0 0 FB8_16 (b) (b)
|
|
LAN_SM_FSM_FFd8 4 0 \/1 0 FB8_17 (b) (b)
|
|
(unused) 0 0 \/5 0 FB8_18 (b) (b)
|
|
|
|
Signals Used by Logic in Function Block
|
|
1: $OpTx$FX_DC$1323 14: LAN_CS_RST 26: A<14>.PIN
|
|
2: DQ_9_IOBUFE/DQ_9_IOBUFE_TRST 15: LAN_RD_S 27: D<6>.PIN
|
|
3: DQ_DATA<0> 16: LAN_SM_FSM_FFd13 28: D<4>.PIN
|
|
4: DQ_DATA<12> 17: LAN_SM_FSM_FFd3 29: D<0>.PIN
|
|
5: DQ_DATA<14> 18: LAN_WRH_S 30: A<20>.PIN
|
|
6: DQ_DATA<4> 19: LAN_WR_RST 31: A<16>.PIN
|
|
7: DQ_DATA<6> 20: LDS 32: A<22>.PIN
|
|
8: DQ_DATA<8> 21: A<8>.PIN 33: RESET
|
|
9: DQ_SWAP 22: A<12>.PIN 34: RW
|
|
10: DS0 23: D<14>.PIN 35: UDS
|
|
11: DS1 24: D<12>.PIN 36: Z3_ADR<13>
|
|
12: FCS 25: D<8>.PIN 37: Z3_DATA<9>/Z3_DATA<9>_SETF__$INT
|
|
13: LAN_ACCESS
|
|
|
|
Signal 1 2 3 4 FB
|
|
Name 0----+----0----+----0----+----0----+----0 Inputs
|
|
DQ_DATA<0> X.X.....X......XX..XX...X...X.X...X.X... 12
|
|
DQ<12> .X.X.....XXXX......X...X........XXX..... 11
|
|
DQ<14> .X..X....XXXX......X..X.........XXX..... 11
|
|
LAN_WRH ...........X.....XX.............X....... 4
|
|
DQ_DATA<12> X..X....X......XX..X.X.X...X.X....X.X... 12
|
|
LAN_CS ............XX..................X..X.... 4
|
|
DQ_DATA<14> X...X...X......XX..X..X..XX....X..X.X... 12
|
|
LAN_RD ...........X..X.................X....... 3
|
|
DQ_DATA<4> X....X..X......XX..X.X.X...X.X....X.X... 12
|
|
DQ_DATA<6> X.....X.X......XX..X..X..XX....X..X.X... 12
|
|
DQ_DATA<8> X......XX......XX..XX...X...X.X...X.X... 12
|
|
LAN_SM_FSM_FFd8 .........XX....XX..X.............XXXX... 9
|
|
0----+----1----+----2----+----3----+----4
|
|
0 0 0 0
|
|
*********************************** FB9 ***********************************
|
|
Number of function block inputs used/remaining: 45/9
|
|
Number of signals used by logic mapping into function block: 45
|
|
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
|
Name Pt Pt Pt Pt # Type Use
|
|
(unused) 0 0 \/5 0 FB9_1 (b) (b)
|
|
LAN_ACCESS 16 11<- 0 0 FB9_2 50 I/O I
|
|
LAN_SM_FSM_FFd13 1 0 /\4 0 FB9_3 51 I/O I
|
|
LAN_SM_FSM_FFd2 2 0 0 3 FB9_4 (b) (b)
|
|
Z3_ADR<12> 3 0 0 2 FB9_5 52 I/O I
|
|
Z3_ADR<11> 3 0 0 2 FB9_6 53 I/O I
|
|
LAN_WRL_S 3 0 0 2 FB9_7 (b) (b)
|
|
LAN_WRH_S 3 0 0 2 FB9_8 54 I/O I
|
|
LAN_SM_FSM_FFd7 3 0 0 2 FB9_9 (b) (b)
|
|
LAN_SM_FSM_FFd6 3 0 0 2 FB9_10 (b) (b)
|
|
A<8> 5 0 0 0 FB9_11 56 I/O I/O
|
|
LAN_SM_FSM_FFd3 3 0 0 2 FB9_12 57 I/O I
|
|
IDE_ENABLE 3 0 \/2 0 FB9_13 (b) (b)
|
|
A<9> 5 2<- \/2 0 FB9_14 58 I/O I/O
|
|
DQ_SWAP 10 5<- 0 0 FB9_15 (b) (b)
|
|
LAN_SM_FSM_FFd4 2 0 /\3 0 FB9_16 (b) (b)
|
|
A<10> 5 0 0 0 FB9_17 59 I/O I/O
|
|
LAN_SM_FSM_FFd1 2 0 \/2 1 FB9_18 (b) (b)
|
|
|
|
Signals Used by Logic in Function Block
|
|
1: $OpTx$FX_DC$461 16: LAN_BASEADR<9> 31: A<13>.PIN
|
|
2: $OpTx$FX_DC$462 17: LAN_SM_FSM_FFd1 32: DQ<1>.PIN
|
|
3: $OpTx$FX_DC$463 18: LAN_SM_FSM_FFd11 33: DQ<0>.PIN
|
|
4: $OpTx$INV$436 19: LAN_SM_FSM_FFd2 34: D<11>.PIN
|
|
5: $OpTx$INV$437 20: LAN_SM_FSM_FFd3 35: D<10>.PIN
|
|
6: AS 21: LAN_SM_FSM_FFd4 36: D<9>.PIN
|
|
7: DQ_SWAP 22: LAN_SM_FSM_FFd5 37: D<8>.PIN
|
|
8: DS0 23: LAN_SM_FSM_FFd7 38: A<14>.PIN
|
|
9: DS1 24: LAN_SM_FSM_FFd8 39: RESET
|
|
10: FCS 25: LAN_SM_FSM_FFd9 40: RW
|
|
11: IDE_ACCESS 26: LDS 41: SHUT_UP_Z2<0>
|
|
12: LAN_ACCESS 27: DQ<10>.PIN 42: SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF
|
|
13: LAN_BASEADR<10> 28: DQ<9>.PIN 43: UDS
|
|
14: LAN_BASEADR<11> 29: DQ<8>.PIN 44: Z3_DATA<9>/Z3_DATA<9>_SETF__$INT
|
|
15: LAN_BASEADR<8> 30: DQ<2>.PIN 45: Z3
|
|
|
|
Signal 1 2 3 4 5 FB
|
|
Name 0----+----0----+----0----+----0----+----0----+----0 Inputs
|
|
LAN_ACCESS .XXXX....X..XXXX.................XXXX.X.X...X..... 16
|
|
LAN_SM_FSM_FFd13 ...........................................X...... 1
|
|
LAN_SM_FSM_FFd2 .......................X...................X...... 2
|
|
Z3_ADR<12> .........X...........................XX........... 3
|
|
Z3_ADR<11> .........X....................X.......X........... 3
|
|
LAN_WRL_S ........X..............XX.................XX...... 5
|
|
LAN_WRH_S .......X...............XXX.................X...... 5
|
|
LAN_SM_FSM_FFd7 .......XX........X....X....................X...... 5
|
|
LAN_SM_FSM_FFd6 .......XX.............X....................X...... 4
|
|
A<8> ......X..X.X.........X......X...X......X...X...... 8
|
|
LAN_SM_FSM_FFd3 .......XX..........XX......................X...... 5
|
|
IDE_ENABLE .....X....X...........................XX.X........ 5
|
|
A<9> ......X..X.X.........X.....X...X.......X...X...... 8
|
|
DQ_SWAP XXXXX....X..X.XX..............X...XXXXX.X...X..... 17
|
|
LAN_SM_FSM_FFd4 ........................X..................X...... 2
|
|
A<10> ......X..X.X.........X....X..X.........X...X...... 8
|
|
LAN_SM_FSM_FFd1 ................X.X........................X...... 3
|
|
0----+----1----+----2----+----3----+----4----+----5
|
|
0 0 0 0 0
|
|
*********************************** FB10 ***********************************
|
|
Number of function block inputs used/remaining: 31/23
|
|
Number of signals used by logic mapping into function block: 31
|
|
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
|
Name Pt Pt Pt Pt # Type Use
|
|
DQ<4>_BUFR 9 8<- \/4 0 FB10_1 (b) (b)
|
|
DQ<1> 10 5<- 0 0 FB10_2 117 I/O I/O
|
|
DQ<0> 9 5<- /\1 0 FB10_3 118 I/O I/O
|
|
(unused) 0 0 /\5 0 FB10_4 (b) (b)
|
|
DQ<3> 9 4<- 0 0 FB10_5 119 I/O I/O
|
|
DQ<2> 9 8<- /\4 0 FB10_6 120 I/O I/O
|
|
(unused) 0 0 /\5 0 FB10_7 (b) (b)
|
|
DQ<5> 9 7<- /\3 0 FB10_8 121 I/O I/O
|
|
(unused) 0 0 /\5 0 FB10_9 (b) (b)
|
|
DQ<4> 2 0 /\2 1 FB10_10 124 I/O I/O
|
|
DQ<7> 9 4<- 0 0 FB10_11 125 I/O I/O
|
|
DQ<6> 9 8<- /\4 0 FB10_12 126 I/O I/O
|
|
(unused) 0 0 /\5 0 FB10_13 (b) (b)
|
|
DQ<8> 2 0 /\3 0 FB10_14 128 I/O I/O
|
|
(unused) 0 0 \/3 2 FB10_15 (b) (b)
|
|
(unused) 0 0 \/5 0 FB10_16 (b) (b)
|
|
DQ<10> 10 8<- \/3 0 FB10_17 129 I/O I/O
|
|
(unused) 0 0 \/5 0 FB10_18 (b) (b)
|
|
|
|
Signals Used by Logic in Function Block
|
|
1: DQ<4>_BUFR 12: DQ_DATA<7> 22: D<6>.PIN
|
|
2: DQ<8>_BUFR 13: DS0 23: D<5>.PIN
|
|
3: DQ_9_IOBUFE/DQ_9_IOBUFE_TRST 14: DS1 24: D<4>.PIN
|
|
4: DQ_DATA<0> 15: FCS 25: D<3>.PIN
|
|
5: DQ_DATA<10> 16: LAN_ACCESS 26: D<2>.PIN
|
|
6: DQ_DATA<1> 17: LAN_D_INIT<1> 27: D<1>.PIN
|
|
7: DQ_DATA<2> 18: LAN_D_INIT<8> 28: D<0>.PIN
|
|
8: DQ_DATA<3> 19: LDS 29: RESET
|
|
9: DQ_DATA<4> 20: D<10>.PIN 30: RW
|
|
10: DQ_DATA<5> 21: D<7>.PIN 31: UDS
|
|
11: DQ_DATA<6>
|
|
|
|
Signal 1 2 3 4 FB
|
|
Name 0----+----0----+----0----+----0----+----0 Inputs
|
|
DQ<4>_BUFR ........X...XXXXX.X....X....XXX......... 11
|
|
DQ<1> ..X..X......XXXXX.X.......X.XXX......... 12
|
|
DQ<0> ..XX........XXXX..X........XXXX......... 11
|
|
DQ<3> ..X....X....XXXX..X.....X...XXX......... 11
|
|
DQ<2> ..X...X.....XXXX..X......X..XXX......... 11
|
|
DQ<5> ..X......X..XXXX..X...X.....XXX......... 11
|
|
DQ<4> X.X..................................... 2
|
|
DQ<7> ..X........XXXXX..X.X.......XXX......... 11
|
|
DQ<6> ..X.......X.XXXX..X..X......XXX......... 11
|
|
DQ<8> .XX..................................... 2
|
|
DQ<10> ..X.X.......XXXX.XXX........XXX......... 12
|
|
0----+----1----+----2----+----3----+----4
|
|
0 0 0 0
|
|
*********************************** FB11 ***********************************
|
|
Number of function block inputs used/remaining: 34/20
|
|
Number of signals used by logic mapping into function block: 34
|
|
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
|
Name Pt Pt Pt Pt # Type Use
|
|
$OpTx$FX_DC$1323 1 0 0 4 FB11_1 (b) (b)
|
|
Z3_DATA<30> 4 0 0 1 FB11_2 (b) (b)
|
|
A<11> 5 0 0 0 FB11_3 60 I/O I/O
|
|
Z3_DATA<29> 4 0 0 1 FB11_4 (b) (b)
|
|
A<12> 5 0 0 0 FB11_5 61 I/O I/O
|
|
Z3_DATA<28> 4 0 0 1 FB11_6 (b) (b)
|
|
Z3_DATA<27> 4 0 0 1 FB11_7 (b) (b)
|
|
Z3_DATA<22> 4 0 0 1 FB11_8 (b) (b)
|
|
Z3_DATA<21> 4 0 0 1 FB11_9 (b) (b)
|
|
A<13> 5 0 0 0 FB11_10 64 I/O I/O
|
|
A<14> 5 0 0 0 FB11_11 66 I/O I/O
|
|
INT6_OUT 1 0 0 4 FB11_12 68 I/O O
|
|
Z3_DATA<20> 4 0 0 1 FB11_13 (b) (b)
|
|
ROM_B<1> 0 0 0 5 FB11_14 69 I/O O
|
|
Z3_DATA<19> 4 0 0 1 FB11_15 (b) (b)
|
|
LAN_READY 4 0 0 1 FB11_16 (b) (b)
|
|
CP_WE 1 0 \/2 2 FB11_17 70 I/O O
|
|
Z3_A_LOW 7 2<- 0 0 FB11_18 (b) (b)
|
|
|
|
Signals Used by Logic in Function Block
|
|
1: AS 13: LAN_SM_FSM_FFd12 24: DQ<14>.PIN
|
|
2: CP_IRQ 14: LAN_SM_FSM_FFd13 25: DQ<13>.PIN
|
|
3: CP_WE_QUIRK 15: LAN_SM_FSM_FFd2 26: DQ<12>.PIN
|
|
4: CP_WE_S 16: LAN_SM_FSM_FFd3 27: DQ<11>.PIN
|
|
5: DQ_SWAP 17: LAN_SM_FSM_FFd4 28: DQ<6>.PIN
|
|
6: DS0 18: LAN_SM_FSM_FFd5 29: DQ<5>.PIN
|
|
7: DS1 19: LAN_SM_FSM_FFd6 30: DQ<4>.PIN
|
|
8: FCS 20: LAN_SM_FSM_FFd7 31: DQ<3>.PIN
|
|
9: LAN_ACCESS 21: LAN_SM_FSM_FFd8 32: RW
|
|
10: LAN_SM_FSM_FFd1 22: LAN_SM_FSM_FFd9 33: UDS
|
|
11: LAN_SM_FSM_FFd10 23: LDS 34: Z3_DATA<9>/Z3_DATA<9>_SETF__$INT
|
|
12: LAN_SM_FSM_FFd11
|
|
|
|
Signal 1 2 3 4 FB
|
|
Name 0----+----0----+----0----+----0----+----0 Inputs
|
|
$OpTx$FX_DC$1323 .........XXXX.X.XXXXXX.................. 11
|
|
Z3_DATA<30> ....X..............X...X...X.....X...... 5
|
|
A<11> ....X..XX........X........X...XX.X...... 8
|
|
Z3_DATA<29> ....X..............X....X...X....X...... 5
|
|
A<12> ....X..XX........X.......X...X.X.X...... 8
|
|
Z3_DATA<28> ....X..............X.....X...X...X...... 5
|
|
Z3_DATA<27> ....X..............X......X...X..X...... 5
|
|
Z3_DATA<22> ....X..............X...X...X.....X...... 5
|
|
Z3_DATA<21> ....X..............X....X...X....X...... 5
|
|
A<13> ....X..XX........X......X...X..X.X...... 8
|
|
A<14> ....X..XX........X.....X...X...X.X...... 8
|
|
INT6_OUT .X...................................... 1
|
|
Z3_DATA<20> ....X..............X.....X...X...X...... 5
|
|
ROM_B<1> ........................................ 0
|
|
Z3_DATA<19> ....X..............X......X...X..X...... 5
|
|
LAN_READY .....XX..XX.X.XX.X.X.............X...... 10
|
|
CP_WE X.XX.................................... 3
|
|
Z3_A_LOW .....XX...X..XXX..XXX.X.........XX...... 12
|
|
0----+----1----+----2----+----3----+----4
|
|
0 0 0 0
|
|
*********************************** FB12 ***********************************
|
|
Number of function block inputs used/remaining: 37/17
|
|
Number of signals used by logic mapping into function block: 37
|
|
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
|
Name Pt Pt Pt Pt # Type Use
|
|
DQ_DATA<11> 10 5<- 0 0 FB12_1 (b) (b)
|
|
LAN_CFG<4> 0 0 /\4 1 FB12_2 110 I/O O
|
|
Z3_DATA<9>/Z3_DATA<9>_SETF__$INT
|
|
4 0 \/1 0 FB12_3 111 I/O I
|
|
LAN_SM_FSM_FFd10 3 1<- \/3 0 FB12_4 (b) (b)
|
|
DQ<15> 9 4<- 0 0 FB12_5 112 I/O I/O
|
|
LAN_INT_ENABLE 4 0 /\1 0 FB12_6 (b) (b)
|
|
(unused) 0 0 \/5 0 FB12_7 (b) (b)
|
|
DQ<13> 9 5<- \/1 0 FB12_8 113 I/O I/O
|
|
(unused) 0 0 \/5 0 FB12_9 (b) (b)
|
|
DQ<11> 10 6<- \/1 0 FB12_10 115 I/O I/O
|
|
(unused) 0 0 \/5 0 FB12_11 (b) (b)
|
|
DQ<9> 10 6<- \/1 0 FB12_12 116 I/O I/O
|
|
(unused) 0 0 \/5 0 FB12_13 (b) (b)
|
|
DQ_DATA<7> 10 6<- \/1 0 FB12_14 (b) (b)
|
|
(unused) 0 0 \/5 0 FB12_15 (b) (b)
|
|
DQ_DATA<3> 10 6<- \/1 0 FB12_16 (b) (b)
|
|
(unused) 0 0 \/5 0 FB12_17 (b) (b)
|
|
DQ_DATA<15> 10 6<- \/1 0 FB12_18 (b) (b)
|
|
|
|
Signals Used by Logic in Function Block
|
|
1: $OpTx$FX_DC$1323 14: A<11>.PIN 26: D<15>.PIN
|
|
2: BERR 15: LAN_ACCESS 27: D<13>.PIN
|
|
3: DQ_9_IOBUFE/DQ_9_IOBUFE_TRST 16: LAN_D_INIT<1> 28: D<11>.PIN
|
|
4: DQ_DATA<11> 17: LAN_D_INIT<8> 29: D<9>.PIN
|
|
5: DQ_DATA<13> 18: LAN_INT_ENABLE 30: D<7>.PIN
|
|
6: DQ_DATA<15> 19: LAN_SM_FSM_FFd12 31: D<3>.PIN
|
|
7: DQ_DATA<3> 20: LAN_SM_FSM_FFd13 32: A<15>.PIN
|
|
8: DQ_DATA<7> 21: LAN_SM_FSM_FFd3 33: RESET
|
|
9: DQ_DATA<9> 22: LAN_SM_FSM_FFd6 34: RW
|
|
10: DQ_SWAP 23: LDS 35: UDS
|
|
11: DS0 24: A<23>.PIN 36: Z3_ADR<13>
|
|
12: DS1 25: A<19>.PIN 37: Z3_DATA<9>/Z3_DATA<9>_SETF__$INT
|
|
13: FCS
|
|
|
|
Signal 1 2 3 4 FB
|
|
Name 0----+----0----+----0----+----0----+----0 Inputs
|
|
DQ_DATA<11> X..X.....X...X.....XX.X.X..X..X...X.X... 12
|
|
LAN_CFG<4> ........................................ 0
|
|
Z3_DATA<9>/Z3_DATA<9>_SETF__$INT
|
|
.X........XXX.X.......X.........X.X..... 8
|
|
LAN_SM_FSM_FFd10 ...................X.XX..........XXXX... 7
|
|
DQ<15> ..X..X....XXX.X.......X..X......XXX..... 11
|
|
LAN_INT_ENABLE .X.........XX.X..XX....X.X......XXX..... 11
|
|
DQ<13> ..X.X.....XXX.X.......X...X.....XXX..... 11
|
|
DQ<11> ..XX......XXX.X.X.....X....X....XXX..... 12
|
|
DQ<9> ..X.....X.XXX.XX......X.....X...XXX..... 12
|
|
DQ_DATA<7> X......X.X.........XX.XX.X...X.X..X.X... 12
|
|
DQ_DATA<3> X.....X..X...X.....XX.X.X..X..X...X.X... 12
|
|
DQ_DATA<15> X....X...X.........XX.XX.X...X.X..X.X... 12
|
|
0----+----1----+----2----+----3----+----4
|
|
0 0 0 0
|
|
*********************************** FB13 ***********************************
|
|
Number of function block inputs used/remaining: 29/25
|
|
Number of signals used by logic mapping into function block: 29
|
|
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
|
Name Pt Pt Pt Pt # Type Use
|
|
SHUT_UP_Z2<0> 4 0 /\1 0 FB13_1 (b) (b)
|
|
CP_RD 1 0 0 4 FB13_2 71 I/O O
|
|
AUTO_CONFIG_Z2_DONE_CYCLE<1>
|
|
4 0 0 1 FB13_3 (b) (b)
|
|
AUTO_CONFIG_Z2_DONE_CYCLE<0>
|
|
4 0 0 1 FB13_4 (b) (b)
|
|
(unused) 0 0 \/5 0 FB13_5 (b) (b)
|
|
(unused) 0 0 \/5 0 FB13_6 (b) (b)
|
|
D_Z2_OUT<3> 14 10<- \/1 0 FB13_7 (b) (b)
|
|
A<15> 5 1<- \/1 0 FB13_8 74 I/O I/O
|
|
(unused) 0 0 \/5 0 FB13_9 (b) (b)
|
|
D_Z2_OUT<2> 16 11<- 0 0 FB13_10 (b) (b)
|
|
(unused) 0 0 /\5 0 FB13_11 75 I/O I
|
|
(unused) 0 0 \/5 0 FB13_12 (b) (b)
|
|
D_Z2_OUT<0> 15 10<- 0 0 FB13_13 (b) (b)
|
|
LAN_WRL 3 3<- /\5 0 FB13_14 76 I/O O
|
|
(unused) 0 0 /\3 2 FB13_15 77 I/O I
|
|
(unused) 0 0 \/5 0 FB13_16 (b) (b)
|
|
D_Z2_OUT<1> 16 11<- 0 0 FB13_17 78 I/O I
|
|
(unused) 0 0 /\5 0 FB13_18 (b) (b)
|
|
|
|
Signals Used by Logic in Function Block
|
|
1: $OpTx$$OpTx$FX_DC$476_INV$1624 11: A<4> 21: LDS
|
|
2: AS 12: A<5> 22: DQ<15>.PIN
|
|
3: AUTOCONFIG_Z2_ACCESS 13: A<6> 23: DQ<7>.PIN
|
|
4: AUTO_CONFIG_Z2_DONE<0> 14: CP_RD_S 24: RESET
|
|
5: AUTO_CONFIG_Z2_DONE<1> 15: DQ_SWAP 25: RW
|
|
6: AUTO_CONFIG_Z2_DONE_CYCLE<0> 16: FCS 26: SHUT_UP_Z2<0>
|
|
7: AUTO_CONFIG_Z2_DONE_CYCLE<1> 17: LAN_ACCESS 27: SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF
|
|
8: A<1> 18: LAN_SM_FSM_FFd5 28: UDS
|
|
9: A<2> 19: LAN_WRL_S 29: Z3_DATA<9>/Z3_DATA<9>_SETF__$INT
|
|
10: A<3> 20: LAN_WR_RST
|
|
|
|
Signal 1 2 3 4 FB
|
|
Name 0----+----0----+----0----+----0----+----0 Inputs
|
|
SHUT_UP_Z2<0> .XXX...XXXXXX.......X..XXXXX............ 15
|
|
CP_RD .X...........X.......................... 2
|
|
AUTO_CONFIG_Z2_DONE_CYCLE<1>
|
|
.XXXX.XX.XXXX.......X..XX.XX............ 15
|
|
AUTO_CONFIG_Z2_DONE_CYCLE<0>
|
|
.XXX.X.X.XXXX.......X..XX.XX............ 14
|
|
D_Z2_OUT<3> .XXXX..XXXXXX.......X..X..XX............ 14
|
|
A<15> ..............XXXX...XX.X...X........... 8
|
|
D_Z2_OUT<2> .XXXX..XXXXXX.......X..X..XX............ 14
|
|
D_Z2_OUT<0> .XXXX..XXXXXX.......X..X..XX............ 14
|
|
LAN_WRL ...............X..XX...X................ 4
|
|
D_Z2_OUT<1> XXXXX..XXXXXX.......X..X..XX............ 15
|
|
0----+----1----+----2----+----3----+----4
|
|
0 0 0 0
|
|
*********************************** FB14 ***********************************
|
|
Number of function block inputs used/remaining: 21/33
|
|
Number of signals used by logic mapping into function block: 21
|
|
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
|
Name Pt Pt Pt Pt # Type Use
|
|
LAN_A_INIT<3> 1 0 0 4 FB14_1 (b) (b)
|
|
LAN_WR_RST 2 0 0 3 FB14_2 (b) (b)
|
|
OVR 1 0 0 4 FB14_3 100 I/O O
|
|
LAN_RST_SM_FSM_FFd7 2 0 0 3 FB14_4 (b) (b)
|
|
LAN_RST_SM_FSM_FFd6 2 0 0 3 FB14_5 101 I/O (b)
|
|
LAN_RST_SM_FSM_FFd5 2 0 0 3 FB14_6 102 I/O I
|
|
LAN_RST_SM_FSM_FFd4 2 0 0 3 FB14_7 (b) (b)
|
|
LAN_RST_SM_FSM_FFd1 2 0 0 3 FB14_8 103 I/O I
|
|
LAN_D_INIT<8> 2 0 0 3 FB14_9 (b) (b)
|
|
LAN_D_INIT<1> 2 0 0 3 FB14_10 104 I/O I
|
|
CFOUT 1 0 0 4 FB14_11 105 I/O O
|
|
LAN_CS_RST 2 0 0 3 FB14_12 (b) (b)
|
|
LAN_A_INIT<6> 2 0 0 3 FB14_13 (b) (b)
|
|
SLAVE 4 0 0 1 FB14_14 106 I/O O
|
|
OWN 0 0 0 5 FB14_15 107 I/O O
|
|
Z3_ADR_1 3 0 0 2 FB14_16 (b) (b)
|
|
Z3_ADR_0 3 0 0 2 FB14_17 (b) (b)
|
|
Z3_ADR<9> 3 0 0 2 FB14_18 (b) (b)
|
|
|
|
Signals Used by Logic in Function Block
|
|
1: AS 8: CP_CS 15: LAN_RST_SM_FSM_FFd2
|
|
2: AUTOCONFIG_Z2_ACCESS 9: FCS 16: LAN_RST_SM_FSM_FFd3
|
|
3: AUTO_CONFIG_Z2_DONE<0> 10: IDE_ACCESS 17: LAN_RST_SM_FSM_FFd4
|
|
4: AUTO_CONFIG_Z2_DONE<1> 11: A<11>.PIN 18: LAN_RST_SM_FSM_FFd5
|
|
5: AUTO_CONFIG_Z2_DONE<2> 12: LAN_ACCESS 19: LAN_RST_SM_FSM_FFd6
|
|
6: A<2> 13: LAN_A_INIT<3> 20: LAN_RST_SM_FSM_FFd7
|
|
7: A<3> 14: LAN_RST_SM_FSM_FFd1 21: RESET
|
|
|
|
Signal 1 2 3 4 FB
|
|
Name 0----+----0----+----0----+----0----+----0 Inputs
|
|
LAN_A_INIT<3> ....................X................... 1
|
|
LAN_WR_RST ...............X..X.X................... 3
|
|
OVR ........X..X............................ 2
|
|
LAN_RST_SM_FSM_FFd7 ............X.......X................... 2
|
|
LAN_RST_SM_FSM_FFd6 ...................XX................... 2
|
|
LAN_RST_SM_FSM_FFd5 ..................X.X................... 2
|
|
LAN_RST_SM_FSM_FFd4 .................X..X................... 2
|
|
LAN_RST_SM_FSM_FFd1 .............XX.....X................... 3
|
|
LAN_D_INIT<8> ............X....XXXX................... 5
|
|
LAN_D_INIT<1> .............XXXX...X................... 5
|
|
CFOUT ..XXX................................... 3
|
|
LAN_CS_RST ............XX......X................... 3
|
|
LAN_A_INIT<6> ............X....XXXX................... 5
|
|
SLAVE XX.....XXX.X............................ 6
|
|
OWN ........................................ 0
|
|
Z3_ADR_1 ......X.X...........X................... 3
|
|
Z3_ADR_0 .....X..X...........X................... 3
|
|
Z3_ADR<9> ........X.X.........X................... 3
|
|
0----+----1----+----2----+----3----+----4
|
|
0 0 0 0
|
|
*********************************** FB15 ***********************************
|
|
Number of function block inputs used/remaining: 41/13
|
|
Number of signals used by logic mapping into function block: 41
|
|
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
|
Name Pt Pt Pt Pt # Type Use
|
|
DQ_DATA<1> 10 5<- 0 0 FB15_1 (b) (b)
|
|
LAN_SM_FSM_FFd5 2 0 \/3 0 FB15_2 79 I/O I
|
|
DQ_DATA<13> 10 5<- 0 0 FB15_3 80 I/O I
|
|
ROM_OE_S 3 0 /\2 0 FB15_4 (b) (b)
|
|
LAN_SM_FSM_FFd11 3 0 0 2 FB15_5 (b) (b)
|
|
IDE_R_S 3 0 0 2 FB15_6 (b) (b)
|
|
CP_WE_S 3 0 0 2 FB15_7 (b) (b)
|
|
CP_RD_S 3 0 \/2 0 FB15_8 81 I/O I
|
|
LAN_RD_S 4 2<- \/3 0 FB15_9 (b) (b)
|
|
DQ_DATA<9> 10 5<- 0 0 FB15_10 82 I/O I
|
|
LAN_SM_FSM_FFd9 3 0 /\2 0 FB15_11 83 I/O I
|
|
DTACK 1 0 \/4 0 FB15_12 85 I/O O
|
|
DQ_DATA<5> 10 5<- 0 0 FB15_13 (b) (b)
|
|
A<23> 5 1<- /\1 0 FB15_14 86 I/O I/O
|
|
A<22> 5 1<- /\1 0 FB15_15 87 I/O I/O
|
|
LAN_SM_FSM_FFd12 2 0 /\1 2 FB15_16 (b) (b)
|
|
A<21> 5 0 0 0 FB15_17 88 I/O I/O
|
|
(unused) 0 0 \/5 0 FB15_18 (b) (b)
|
|
|
|
Signals Used by Logic in Function Block
|
|
1: $OpTx$FX_DC$1323 15: LAN_SM_FSM_FFd10 29: DQ<5>.PIN
|
|
2: AS 16: LAN_SM_FSM_FFd11 30: A<13>.PIN
|
|
3: CP_CS 17: LAN_SM_FSM_FFd12 31: D<13>.PIN
|
|
4: DQ_DATA<13> 18: LAN_SM_FSM_FFd13 32: D<9>.PIN
|
|
5: DQ_DATA<1> 19: LAN_SM_FSM_FFd3 33: D<5>.PIN
|
|
6: DQ_DATA<5> 20: LAN_SM_FSM_FFd5 34: D<1>.PIN
|
|
7: DQ_DATA<9> 21: LAN_SM_FSM_FFd6 35: A<21>.PIN
|
|
8: DQ_SWAP 22: LDS 36: RESET
|
|
9: FCS 23: A<17>.PIN 37: RW
|
|
10: IDE_ACCESS 24: DQ<15>.PIN 38: SHUT_UP_Z2<2>/SHUT_UP_Z2<2>_CLKF
|
|
11: A<9>.PIN 25: DQ<14>.PIN 39: UDS
|
|
12: IDE_ENABLE 26: DQ<13>.PIN 40: Z3_ADR<13>
|
|
13: LAN_ACCESS 27: DQ<7>.PIN 41: Z3_DATA<9>/Z3_DATA<9>_SETF__$INT
|
|
14: LAN_READY 28: DQ<6>.PIN
|
|
|
|
Signal 1 2 3 4 5 FB
|
|
Name 0----+----0----+----0----+----0----+----0----+----0 Inputs
|
|
DQ_DATA<1> X...X..X..X......XX..XX........X.X....X.X......... 12
|
|
LAN_SM_FSM_FFd5 ..............X....X....................X......... 3
|
|
DQ_DATA<13> X..X...X.........XX..X.......XX.X.X...X.X......... 12
|
|
ROM_OE_S .X.......X.X.......................XXX............ 6
|
|
LAN_SM_FSM_FFd11 .................X...X..............X.XXX......... 6
|
|
IDE_R_S .X.......X.X.......................XXX............ 6
|
|
CP_WE_S .XX..................X..............XXX........... 6
|
|
CP_RD_S .XX..................X..............XXX........... 6
|
|
LAN_RD_S ..............XX.X..X...............X..XX......... 7
|
|
DQ_DATA<9> X.....XX..X......XX..XX........X.X....X.X......... 12
|
|
LAN_SM_FSM_FFd9 .................X...X..............X.XXX......... 6
|
|
DTACK ........X....X.................................... 2
|
|
DQ_DATA<5> X....X.X.........XX..X.......XX.X.X...X.X......... 12
|
|
A<23> .......XX...X......X...X..X.........X...X......... 8
|
|
A<22> .......XX...X......X....X..X........X...X......... 8
|
|
LAN_SM_FSM_FFd12 ................XX.....................XX......... 4
|
|
A<21> .......XX...X......X.....X..X.......X...X......... 8
|
|
0----+----1----+----2----+----3----+----4----+----5
|
|
0 0 0 0 0
|
|
*********************************** FB16 ***********************************
|
|
Number of function block inputs used/remaining: 30/24
|
|
Number of signals used by logic mapping into function block: 30
|
|
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
|
Name Pt Pt Pt Pt # Type Use
|
|
DQ_DATA<10> 10 5<- 0 0 FB16_1 (b) (b)
|
|
A<20> 5 0 0 0 FB16_2 91 I/O I/O
|
|
A<19> 5 0 0 0 FB16_3 92 I/O I/O
|
|
(unused) 0 0 \/5 0 FB16_4 (b) (b)
|
|
DQ_DATA<2> 10 5<- 0 0 FB16_5 93 I/O I
|
|
A<18> 5 0 0 0 FB16_6 94 I/O I/O
|
|
Z3_DATA<17> 4 0 0 1 FB16_7 (b) (b)
|
|
A<17> 5 0 0 0 FB16_8 95 I/O I/O
|
|
Z3_DATA<18> 4 0 0 1 FB16_9 (b) (b)
|
|
MTACK 0 0 0 5 FB16_10 96 I/O O
|
|
A<16> 5 0 0 0 FB16_11 97 I/O I/O
|
|
Z3_DATA<23> 4 0 0 1 FB16_12 98 I/O I
|
|
Z3_DATA<24> 4 0 0 1 FB16_13 (b) (b)
|
|
Z3_DATA<25> 4 0 0 1 FB16_14 (b) (b)
|
|
Z3_DATA<26> 4 0 0 1 FB16_15 (b) (b)
|
|
Z3_DATA<31> 4 0 0 1 FB16_16 (b) (b)
|
|
Z3_DATA<16> 4 0 0 1 FB16_17 (b) (b)
|
|
(unused) 0 0 \/5 0 FB16_18 (b) (b)
|
|
|
|
Signals Used by Logic in Function Block
|
|
1: $OpTx$FX_DC$1323 11: LAN_SM_FSM_FFd7 21: DQ<4>.PIN
|
|
2: DQ_DATA<10> 12: LDS 22: DQ<3>.PIN
|
|
3: DQ_DATA<2> 13: A<18>.PIN 23: DQ<2>.PIN
|
|
4: DQ_SWAP 14: DQ<15>.PIN 24: DQ<1>.PIN
|
|
5: FCS 15: DQ<12>.PIN 25: DQ<0>.PIN
|
|
6: A<10>.PIN 16: DQ<11>.PIN 26: D<10>.PIN
|
|
7: LAN_ACCESS 17: DQ<10>.PIN 27: D<2>.PIN
|
|
8: LAN_SM_FSM_FFd13 18: DQ<9>.PIN 28: RW
|
|
9: LAN_SM_FSM_FFd3 19: DQ<8>.PIN 29: UDS
|
|
10: LAN_SM_FSM_FFd5 20: DQ<7>.PIN 30: Z3_DATA<9>/Z3_DATA<9>_SETF__$INT
|
|
|
|
Signal 1 2 3 4 FB
|
|
Name 0----+----0----+----0----+----0----+----0 Inputs
|
|
DQ_DATA<10> XX.X.X.XX..XX............XX.XX.......... 12
|
|
A<20> ...XX.X..X....X.....X......X.X.......... 8
|
|
A<19> ...XX.X..X.....X.....X.....X.X.......... 8
|
|
DQ_DATA<2> X.XX.X.XX..XX............XX.XX.......... 12
|
|
A<18> ...XX.X..X......X.....X....X.X.......... 8
|
|
Z3_DATA<17> ...X......X......X.....X.....X.......... 5
|
|
A<17> ...XX.X..X.......X.....X...X.X.......... 8
|
|
Z3_DATA<18> ...X......X.....X.....X......X.......... 5
|
|
MTACK ........................................ 0
|
|
A<16> ...XX.X..X........X.....X..X.X.......... 8
|
|
Z3_DATA<23> ...X......X..X.....X.........X.......... 5
|
|
Z3_DATA<24> ...X......X.......X.....X....X.......... 5
|
|
Z3_DATA<25> ...X......X......X.....X.....X.......... 5
|
|
Z3_DATA<26> ...X......X.....X.....X......X.......... 5
|
|
Z3_DATA<31> ...X......X..X.....X.........X.......... 5
|
|
Z3_DATA<16> ...X......X.......X.....X....X.......... 5
|
|
0----+----1----+----2----+----3----+----4
|
|
0 0 0 0
|
|
******************************* Equations ********************************
|
|
|
|
********** Mapped Logic **********
|
|
|
|
|
|
$OpTx$$OpTx$FX_DC$476_INV$1624 <= (NOT A(4) AND A(2) AND NOT A(1));
|
|
|
|
|
|
$OpTx$FX_DC$1323 <= (NOT LAN_SM_FSM_FFd7 AND NOT LAN_SM_FSM_FFd5 AND
|
|
NOT LAN_SM_FSM_FFd10 AND NOT LAN_SM_FSM_FFd8 AND NOT LAN_SM_FSM_FFd12 AND
|
|
NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd6 AND NOT LAN_SM_FSM_FFd9 AND
|
|
NOT LAN_SM_FSM_FFd1 AND NOT LAN_SM_FSM_FFd11 AND NOT LAN_SM_FSM_FFd4);
|
|
|
|
|
|
$OpTx$FX_DC$461 <= D(11).PIN
|
|
XOR
|
|
$OpTx$FX_DC$461 <= LAN_BASEADR(11);
|
|
|
|
|
|
$OpTx$FX_DC$462 <= D(12).PIN
|
|
XOR
|
|
$OpTx$FX_DC$462 <= LAN_BASEADR(12);
|
|
|
|
|
|
$OpTx$FX_DC$463 <= D(15).PIN
|
|
XOR
|
|
$OpTx$FX_DC$463 <= LAN_BASEADR(15);
|
|
|
|
|
|
$OpTx$INV$436 <= ((LAN_BASEADR(2) AND NOT A(18).PIN)
|
|
OR (LAN_BASEADR(3) AND NOT A(19).PIN)
|
|
OR (NOT LAN_BASEADR(3) AND A(19).PIN)
|
|
OR (NOT LAN_BASEADR(4) AND A(20).PIN)
|
|
OR (EXP30_.EXP)
|
|
OR (LAN_BASEADR(4) AND NOT A(20).PIN)
|
|
OR (LAN_BASEADR(5) AND NOT A(21).PIN)
|
|
OR (NOT LAN_BASEADR(5) AND A(21).PIN)
|
|
OR (LAN_BASEADR(7) AND NOT A(23).PIN)
|
|
OR (NOT LAN_BASEADR(7) AND A(23).PIN)
|
|
OR (LAN_BASEADR(0) AND NOT A(16).PIN)
|
|
OR (NOT LAN_BASEADR(0) AND A(16).PIN)
|
|
OR (LAN_BASEADR(1) AND NOT A(17).PIN)
|
|
OR (NOT LAN_BASEADR(1) AND A(17).PIN)
|
|
OR (NOT LAN_BASEADR(2) AND A(18).PIN));
|
|
|
|
|
|
$OpTx$INV$437 <= ((D(13).PIN AND NOT LAN_BASEADR(13))
|
|
OR (NOT D(13).PIN AND LAN_BASEADR(13))
|
|
OR (LAN_BASEADR(6) AND NOT A(22).PIN)
|
|
OR (NOT LAN_BASEADR(6) AND A(22).PIN));
|
|
|
|
|
|
$OpTx$INV$438 <= ((SHUT_UP_Z2(2))
|
|
OR (IDE_BASEADR(4) AND NOT A(20).PIN)
|
|
OR (IDE_BASEADR(5) AND NOT A(21).PIN)
|
|
OR (NOT IDE_BASEADR(5) AND A(21).PIN)
|
|
OR (IDE_BASEADR(7) AND NOT A(23).PIN)
|
|
OR (NOT IDE_BASEADR(7) AND A(23).PIN)
|
|
OR (IDE_BASEADR(2) AND NOT A(18).PIN)
|
|
OR (NOT IDE_BASEADR(2) AND A(18).PIN)
|
|
OR (IDE_BASEADR(3) AND NOT A(19).PIN)
|
|
OR (NOT IDE_BASEADR(3) AND A(19).PIN)
|
|
OR (NOT IDE_BASEADR(4) AND A(20).PIN)
|
|
OR (IDE_BASEADR(0) AND NOT A(16).PIN)
|
|
OR (NOT IDE_BASEADR(0) AND A(16).PIN)
|
|
OR (IDE_BASEADR(1) AND NOT A(17).PIN)
|
|
OR (NOT IDE_BASEADR(1) AND A(17).PIN));
|
|
|
|
FDCPE_A8: FDCPE port map (A_I(8),A(8),CLK_EXT,'0',NOT Z3_DATA(9)/Z3_DATA(9)_SETF__$INT,LAN_SM_FSM_FFd5);
|
|
A(8) <= ((DQ_SWAP AND DQ(8).PIN)
|
|
OR (NOT DQ_SWAP AND DQ(0).PIN));
|
|
A(8) <= A_I(8) when A_OE(8) = '1' else 'Z';
|
|
A_OE(8) <= (NOT FCS AND RW AND LAN_ACCESS);
|
|
|
|
FDCPE_A9: FDCPE port map (A_I(9),A(9),CLK_EXT,'0',NOT Z3_DATA(9)/Z3_DATA(9)_SETF__$INT,LAN_SM_FSM_FFd5);
|
|
A(9) <= ((DQ_SWAP AND DQ(9).PIN)
|
|
OR (NOT DQ_SWAP AND DQ(1).PIN));
|
|
A(9) <= A_I(9) when A_OE(9) = '1' else 'Z';
|
|
A_OE(9) <= (NOT FCS AND RW AND LAN_ACCESS);
|
|
|
|
FDCPE_A10: FDCPE port map (A_I(10),A(10),CLK_EXT,'0',NOT Z3_DATA(9)/Z3_DATA(9)_SETF__$INT,LAN_SM_FSM_FFd5);
|
|
A(10) <= ((DQ_SWAP AND DQ(10).PIN)
|
|
OR (NOT DQ_SWAP AND DQ(2).PIN));
|
|
A(10) <= A_I(10) when A_OE(10) = '1' else 'Z';
|
|
A_OE(10) <= (NOT FCS AND RW AND LAN_ACCESS);
|
|
|
|
FDCPE_A11: FDCPE port map (A_I(11),A(11),CLK_EXT,'0',NOT Z3_DATA(9)/Z3_DATA(9)_SETF__$INT,LAN_SM_FSM_FFd5);
|
|
A(11) <= ((DQ_SWAP AND DQ(11).PIN)
|
|
OR (NOT DQ_SWAP AND DQ(3).PIN));
|
|
A(11) <= A_I(11) when A_OE(11) = '1' else 'Z';
|
|
A_OE(11) <= (NOT FCS AND RW AND LAN_ACCESS);
|
|
|
|
FDCPE_A12: FDCPE port map (A_I(12),A(12),CLK_EXT,'0',NOT Z3_DATA(9)/Z3_DATA(9)_SETF__$INT,LAN_SM_FSM_FFd5);
|
|
A(12) <= ((DQ_SWAP AND DQ(12).PIN)
|
|
OR (NOT DQ_SWAP AND DQ(4).PIN));
|
|
A(12) <= A_I(12) when A_OE(12) = '1' else 'Z';
|
|
A_OE(12) <= (NOT FCS AND RW AND LAN_ACCESS);
|
|
|
|
FDCPE_A13: FDCPE port map (A_I(13),A(13),CLK_EXT,'0',NOT Z3_DATA(9)/Z3_DATA(9)_SETF__$INT,LAN_SM_FSM_FFd5);
|
|
A(13) <= ((DQ_SWAP AND DQ(13).PIN)
|
|
OR (NOT DQ_SWAP AND DQ(5).PIN));
|
|
A(13) <= A_I(13) when A_OE(13) = '1' else 'Z';
|
|
A_OE(13) <= (NOT FCS AND RW AND LAN_ACCESS);
|
|
|
|
FDCPE_A14: FDCPE port map (A_I(14),A(14),CLK_EXT,'0',NOT Z3_DATA(9)/Z3_DATA(9)_SETF__$INT,LAN_SM_FSM_FFd5);
|
|
A(14) <= ((DQ_SWAP AND DQ(14).PIN)
|
|
OR (NOT DQ_SWAP AND DQ(6).PIN));
|
|
A(14) <= A_I(14) when A_OE(14) = '1' else 'Z';
|
|
A_OE(14) <= (NOT FCS AND RW AND LAN_ACCESS);
|
|
|
|
FDCPE_A15: FDCPE port map (A_I(15),A(15),CLK_EXT,'0',NOT Z3_DATA(9)/Z3_DATA(9)_SETF__$INT,LAN_SM_FSM_FFd5);
|
|
A(15) <= ((NOT DQ_SWAP AND DQ(7).PIN)
|
|
OR (DQ_SWAP AND DQ(15).PIN));
|
|
A(15) <= A_I(15) when A_OE(15) = '1' else 'Z';
|
|
A_OE(15) <= (NOT FCS AND RW AND LAN_ACCESS);
|
|
|
|
FDCPE_A16: FDCPE port map (A_I(16),A(16),CLK_EXT,'0',NOT Z3_DATA(9)/Z3_DATA(9)_SETF__$INT,LAN_SM_FSM_FFd5);
|
|
A(16) <= ((DQ_SWAP AND DQ(0).PIN)
|
|
OR (NOT DQ_SWAP AND DQ(8).PIN));
|
|
A(16) <= A_I(16) when A_OE(16) = '1' else 'Z';
|
|
A_OE(16) <= (NOT FCS AND RW AND LAN_ACCESS);
|
|
|
|
FDCPE_A17: FDCPE port map (A_I(17),A(17),CLK_EXT,'0',NOT Z3_DATA(9)/Z3_DATA(9)_SETF__$INT,LAN_SM_FSM_FFd5);
|
|
A(17) <= ((DQ_SWAP AND DQ(1).PIN)
|
|
OR (NOT DQ_SWAP AND DQ(9).PIN));
|
|
A(17) <= A_I(17) when A_OE(17) = '1' else 'Z';
|
|
A_OE(17) <= (NOT FCS AND RW AND LAN_ACCESS);
|
|
|
|
FDCPE_A18: FDCPE port map (A_I(18),A(18),CLK_EXT,'0',NOT Z3_DATA(9)/Z3_DATA(9)_SETF__$INT,LAN_SM_FSM_FFd5);
|
|
A(18) <= ((DQ_SWAP AND DQ(2).PIN)
|
|
OR (NOT DQ_SWAP AND DQ(10).PIN));
|
|
A(18) <= A_I(18) when A_OE(18) = '1' else 'Z';
|
|
A_OE(18) <= (NOT FCS AND RW AND LAN_ACCESS);
|
|
|
|
FDCPE_A19: FDCPE port map (A_I(19),A(19),CLK_EXT,'0',NOT Z3_DATA(9)/Z3_DATA(9)_SETF__$INT,LAN_SM_FSM_FFd5);
|
|
A(19) <= ((DQ_SWAP AND DQ(3).PIN)
|
|
OR (NOT DQ_SWAP AND DQ(11).PIN));
|
|
A(19) <= A_I(19) when A_OE(19) = '1' else 'Z';
|
|
A_OE(19) <= (NOT FCS AND RW AND LAN_ACCESS);
|
|
|
|
FDCPE_A20: FDCPE port map (A_I(20),A(20),CLK_EXT,'0',NOT Z3_DATA(9)/Z3_DATA(9)_SETF__$INT,LAN_SM_FSM_FFd5);
|
|
A(20) <= ((DQ_SWAP AND DQ(4).PIN)
|
|
OR (NOT DQ_SWAP AND DQ(12).PIN));
|
|
A(20) <= A_I(20) when A_OE(20) = '1' else 'Z';
|
|
A_OE(20) <= (NOT FCS AND RW AND LAN_ACCESS);
|
|
|
|
FDCPE_A21: FDCPE port map (A_I(21),A(21),CLK_EXT,'0',NOT Z3_DATA(9)/Z3_DATA(9)_SETF__$INT,LAN_SM_FSM_FFd5);
|
|
A(21) <= ((DQ_SWAP AND DQ(5).PIN)
|
|
OR (NOT DQ_SWAP AND DQ(13).PIN));
|
|
A(21) <= A_I(21) when A_OE(21) = '1' else 'Z';
|
|
A_OE(21) <= (NOT FCS AND RW AND LAN_ACCESS);
|
|
|
|
FDCPE_A22: FDCPE port map (A_I(22),A(22),CLK_EXT,'0',NOT Z3_DATA(9)/Z3_DATA(9)_SETF__$INT,LAN_SM_FSM_FFd5);
|
|
A(22) <= ((DQ_SWAP AND DQ(6).PIN)
|
|
OR (NOT DQ_SWAP AND DQ(14).PIN));
|
|
A(22) <= A_I(22) when A_OE(22) = '1' else 'Z';
|
|
A_OE(22) <= (NOT FCS AND RW AND LAN_ACCESS);
|
|
|
|
FDCPE_A23: FDCPE port map (A_I(23),A(23),CLK_EXT,'0',NOT Z3_DATA(9)/Z3_DATA(9)_SETF__$INT,LAN_SM_FSM_FFd5);
|
|
A(23) <= ((DQ_SWAP AND DQ(7).PIN)
|
|
OR (NOT DQ_SWAP AND DQ(15).PIN));
|
|
A(23) <= A_I(23) when A_OE(23) = '1' else 'Z';
|
|
A_OE(23) <= (NOT FCS AND RW AND LAN_ACCESS);
|
|
|
|
FDCPE_AUTOCONFIG_Z2_ACCESS: FDCPE port map (AUTOCONFIG_Z2_ACCESS,AUTOCONFIG_Z2_ACCESS_D,NOT AS,NOT RESET,'0');
|
|
AUTOCONFIG_Z2_ACCESS_D <= ((NOT AUTO_CONFIG_Z2_DONE(0) AND A(23).PIN AND A(22).PIN AND
|
|
A(21).PIN AND A(19).PIN AND NOT CFIN AND NOT A(17).PIN AND NOT A(16).PIN AND
|
|
NOT A(20).PIN AND NOT A(18).PIN)
|
|
OR (NOT AUTO_CONFIG_Z2_DONE(1) AND A(23).PIN AND A(22).PIN AND
|
|
A(21).PIN AND A(19).PIN AND NOT CFIN AND NOT A(17).PIN AND NOT A(16).PIN AND
|
|
NOT A(20).PIN AND NOT A(18).PIN)
|
|
OR (NOT AUTO_CONFIG_Z2_DONE(2) AND A(23).PIN AND A(22).PIN AND
|
|
A(21).PIN AND A(19).PIN AND NOT CFIN AND NOT A(17).PIN AND NOT A(16).PIN AND
|
|
NOT A(20).PIN AND NOT A(18).PIN));
|
|
|
|
FDCPE_AUTO_CONFIG_Z2_DONE0: FDCPE port map (AUTO_CONFIG_Z2_DONE(0),AUTO_CONFIG_Z2_DONE_D(0),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,NOT RESET,'0',AS);
|
|
AUTO_CONFIG_Z2_DONE_D(0) <= (NOT AUTO_CONFIG_Z2_DONE(0) AND
|
|
NOT AUTO_CONFIG_Z2_DONE_CYCLE(0));
|
|
|
|
FDCPE_AUTO_CONFIG_Z2_DONE1: FDCPE port map (AUTO_CONFIG_Z2_DONE(1),AUTO_CONFIG_Z2_DONE_D(1),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,NOT RESET,'0',AS);
|
|
AUTO_CONFIG_Z2_DONE_D(1) <= (NOT AUTO_CONFIG_Z2_DONE(1) AND
|
|
NOT AUTO_CONFIG_Z2_DONE_CYCLE(1));
|
|
|
|
FDCPE_AUTO_CONFIG_Z2_DONE2: FDCPE port map (AUTO_CONFIG_Z2_DONE(2),AUTO_CONFIG_Z2_DONE_D(2),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,NOT RESET,'0',AS);
|
|
AUTO_CONFIG_Z2_DONE_D(2) <= (NOT AUTO_CONFIG_Z2_DONE(2) AND
|
|
NOT AUTO_CONFIG_Z2_DONE_CYCLE(2));
|
|
|
|
FTCPE_AUTO_CONFIG_Z2_DONE_CYCLE0: FTCPE port map (AUTO_CONFIG_Z2_DONE_CYCLE(0),AUTO_CONFIG_Z2_DONE_CYCLE_T(0),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,NOT RESET,'0');
|
|
AUTO_CONFIG_Z2_DONE_CYCLE_T(0) <= ((NOT A(5) AND NOT A(4) AND NOT A(1) AND NOT AS AND
|
|
NOT AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE_CYCLE(0) AND NOT UDS AND A(6) AND
|
|
A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT A(5) AND NOT A(4) AND NOT A(1) AND NOT AS AND
|
|
NOT AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE_CYCLE(0) AND NOT LDS AND A(6) AND
|
|
A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS));
|
|
|
|
FTCPE_AUTO_CONFIG_Z2_DONE_CYCLE1: FTCPE port map (AUTO_CONFIG_Z2_DONE_CYCLE(1),AUTO_CONFIG_Z2_DONE_CYCLE_T(1),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,NOT RESET,'0');
|
|
AUTO_CONFIG_Z2_DONE_CYCLE_T(1) <= ((NOT A(5) AND NOT A(4) AND NOT A(1) AND NOT AS AND
|
|
AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE(1) AND
|
|
NOT AUTO_CONFIG_Z2_DONE_CYCLE(1) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT A(5) AND NOT A(4) AND NOT A(1) AND NOT AS AND
|
|
AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE(1) AND
|
|
NOT AUTO_CONFIG_Z2_DONE_CYCLE(1) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS));
|
|
|
|
FTCPE_AUTO_CONFIG_Z2_DONE_CYCLE2: FTCPE port map (AUTO_CONFIG_Z2_DONE_CYCLE(2),AUTO_CONFIG_Z2_DONE_CYCLE_T(2),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,NOT RESET,'0');
|
|
AUTO_CONFIG_Z2_DONE_CYCLE_T(2) <= ((NOT A(5) AND NOT A(4) AND NOT A(1) AND NOT AS AND
|
|
AUTO_CONFIG_Z2_DONE(0) AND AUTO_CONFIG_Z2_DONE(1) AND NOT AUTO_CONFIG_Z2_DONE(2) AND
|
|
NOT AUTO_CONFIG_Z2_DONE_CYCLE(2) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT A(5) AND NOT A(4) AND NOT A(1) AND NOT AS AND
|
|
AUTO_CONFIG_Z2_DONE(0) AND AUTO_CONFIG_Z2_DONE(1) AND NOT AUTO_CONFIG_Z2_DONE(2) AND
|
|
NOT AUTO_CONFIG_Z2_DONE_CYCLE(2) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS));
|
|
|
|
|
|
A_LAN(0) <= NOT ((RESET AND NOT Z3_A_LOW));
|
|
|
|
|
|
A_LAN(1) <= NOT ((RESET AND NOT Z3_ADR_0));
|
|
|
|
|
|
A_LAN(2) <= NOT (((RESET AND NOT A(2) AND NOT CP_CS)
|
|
OR (RESET AND NOT Z3_ADR_1 AND CP_CS)));
|
|
|
|
|
|
A_LAN(3) <= ((RESET AND A(3) AND NOT CP_CS)
|
|
OR (NOT RESET AND LAN_A_INIT(3))
|
|
OR (RESET AND Z3_ADR(2) AND CP_CS));
|
|
|
|
|
|
A_LAN(4) <= NOT (((RESET AND NOT Z3_ADR(3) AND CP_CS)
|
|
OR (RESET AND NOT A(4) AND NOT CP_CS)));
|
|
|
|
|
|
A_LAN(5) <= NOT (((RESET AND NOT A(5) AND NOT CP_CS)
|
|
OR (RESET AND NOT Z3_ADR(4) AND CP_CS)));
|
|
|
|
|
|
A_LAN(6) <= ((RESET AND Z3_ADR(5))
|
|
OR (NOT RESET AND LAN_A_INIT(6)));
|
|
|
|
|
|
A_LAN(7) <= NOT ((RESET AND NOT Z3_ADR(6)));
|
|
|
|
|
|
A_LAN(8) <= NOT ((RESET AND NOT Z3_ADR(7)));
|
|
|
|
|
|
A_LAN(9) <= NOT ((RESET AND NOT Z3_ADR(8)));
|
|
|
|
|
|
A_LAN(10) <= NOT ((RESET AND NOT Z3_ADR(9)));
|
|
|
|
|
|
A_LAN(11) <= NOT ((RESET AND NOT Z3_ADR(10)));
|
|
|
|
|
|
A_LAN(12) <= NOT ((RESET AND NOT Z3_ADR(11)));
|
|
|
|
|
|
A_LAN(13) <= NOT ((RESET AND NOT Z3_ADR(12)));
|
|
|
|
|
|
CFOUT <= NOT ((AUTO_CONFIG_Z2_DONE(0) AND AUTO_CONFIG_Z2_DONE(1) AND
|
|
AUTO_CONFIG_Z2_DONE(2)));
|
|
|
|
FTCPE_CP_BASEADR0: FTCPE port map (CP_BASEADR(0),CP_BASEADR_T(0),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET);
|
|
CP_BASEADR_T(0) <= ((NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
|
|
AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE(1) AND D(8).PIN AND
|
|
NOT CP_BASEADR(0) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
|
|
AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE(1) AND D(8).PIN AND
|
|
NOT CP_BASEADR(0) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
|
|
AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE(1) AND NOT D(8).PIN AND
|
|
CP_BASEADR(0) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
|
|
AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE(1) AND NOT D(8).PIN AND
|
|
CP_BASEADR(0) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS));
|
|
|
|
FTCPE_CP_BASEADR1: FTCPE port map (CP_BASEADR(1),CP_BASEADR_T(1),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET);
|
|
CP_BASEADR_T(1) <= ((NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
|
|
AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE(1) AND D(9).PIN AND
|
|
NOT CP_BASEADR(1) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
|
|
AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE(1) AND D(9).PIN AND
|
|
NOT CP_BASEADR(1) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
|
|
AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE(1) AND NOT D(9).PIN AND
|
|
CP_BASEADR(1) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
|
|
AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE(1) AND NOT D(9).PIN AND
|
|
CP_BASEADR(1) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS));
|
|
|
|
FTCPE_CP_BASEADR2: FTCPE port map (CP_BASEADR(2),CP_BASEADR_T(2),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET);
|
|
CP_BASEADR_T(2) <= ((NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
|
|
AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE(1) AND D(10).PIN AND
|
|
NOT CP_BASEADR(2) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
|
|
AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE(1) AND D(10).PIN AND
|
|
NOT CP_BASEADR(2) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
|
|
AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE(1) AND NOT D(10).PIN AND
|
|
CP_BASEADR(2) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
|
|
AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE(1) AND NOT D(10).PIN AND
|
|
CP_BASEADR(2) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS));
|
|
|
|
FTCPE_CP_BASEADR3: FTCPE port map (CP_BASEADR(3),CP_BASEADR_T(3),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET);
|
|
CP_BASEADR_T(3) <= ((NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
|
|
AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE(1) AND D(11).PIN AND
|
|
NOT CP_BASEADR(3) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
|
|
AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE(1) AND D(11).PIN AND
|
|
NOT CP_BASEADR(3) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
|
|
AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE(1) AND NOT D(11).PIN AND
|
|
CP_BASEADR(3) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
|
|
AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE(1) AND NOT D(11).PIN AND
|
|
CP_BASEADR(3) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS));
|
|
|
|
FTCPE_CP_BASEADR4: FTCPE port map (CP_BASEADR(4),CP_BASEADR_T(4),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET);
|
|
CP_BASEADR_T(4) <= ((NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
|
|
AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE(1) AND D(12).PIN AND
|
|
NOT CP_BASEADR(4) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
|
|
AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE(1) AND D(12).PIN AND
|
|
NOT CP_BASEADR(4) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
|
|
AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE(1) AND NOT D(12).PIN AND
|
|
CP_BASEADR(4) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
|
|
AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE(1) AND NOT D(12).PIN AND
|
|
CP_BASEADR(4) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS));
|
|
|
|
FTCPE_CP_BASEADR5: FTCPE port map (CP_BASEADR(5),CP_BASEADR_T(5),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET);
|
|
CP_BASEADR_T(5) <= ((NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
|
|
AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE(1) AND D(13).PIN AND
|
|
NOT CP_BASEADR(5) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
|
|
AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE(1) AND D(13).PIN AND
|
|
NOT CP_BASEADR(5) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
|
|
AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE(1) AND NOT D(13).PIN AND
|
|
CP_BASEADR(5) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
|
|
AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE(1) AND NOT D(13).PIN AND
|
|
CP_BASEADR(5) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS));
|
|
|
|
FTCPE_CP_BASEADR6: FTCPE port map (CP_BASEADR(6),CP_BASEADR_T(6),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET);
|
|
CP_BASEADR_T(6) <= ((NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
|
|
AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE(1) AND D(14).PIN AND
|
|
NOT CP_BASEADR(6) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
|
|
AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE(1) AND D(14).PIN AND
|
|
NOT CP_BASEADR(6) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
|
|
AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE(1) AND NOT D(14).PIN AND
|
|
CP_BASEADR(6) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
|
|
AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE(1) AND NOT D(14).PIN AND
|
|
CP_BASEADR(6) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS));
|
|
|
|
FTCPE_CP_BASEADR7: FTCPE port map (CP_BASEADR(7),CP_BASEADR_T(7),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET);
|
|
CP_BASEADR_T(7) <= ((NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
|
|
AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE(1) AND D(15).PIN AND
|
|
NOT CP_BASEADR(7) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
|
|
AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE(1) AND D(15).PIN AND
|
|
NOT CP_BASEADR(7) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
|
|
AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE(1) AND NOT D(15).PIN AND
|
|
CP_BASEADR(7) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
|
|
AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE(1) AND NOT D(15).PIN AND
|
|
CP_BASEADR(7) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS));
|
|
|
|
FDCPE_CP_CS: FDCPE port map (CP_CS,CP_CS_D,NOT AS,'0',NOT RESET);
|
|
CP_CS_D <= ((SHUT_UP_Z2(1))
|
|
OR (CP_BASEADR(0) AND NOT A(16).PIN)
|
|
OR (NOT CP_BASEADR(0) AND A(16).PIN)
|
|
OR (NOT CP_BASEADR(2) AND A(18).PIN)
|
|
OR (CP_BASEADR(7) AND NOT A(23).PIN)
|
|
OR (NOT CP_BASEADR(7) AND A(23).PIN)
|
|
OR (EXP28_.EXP)
|
|
OR (CP_BASEADR(1) AND NOT A(17).PIN)
|
|
OR (NOT CP_BASEADR(1) AND A(17).PIN)
|
|
OR (CP_BASEADR(2) AND NOT A(18).PIN)
|
|
OR (CP_BASEADR(4) AND NOT A(20).PIN)
|
|
OR (NOT CP_BASEADR(4) AND A(20).PIN)
|
|
OR (CP_BASEADR(6) AND NOT A(22).PIN)
|
|
OR (NOT CP_BASEADR(6) AND A(22).PIN));
|
|
|
|
|
|
CP_RD <= NOT ((NOT AS AND NOT CP_RD_S));
|
|
|
|
FDCPE_CP_RD_S: FDCPE port map (CP_RD_S,CP_RD_S_D,SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0','0');
|
|
CP_RD_S_D <= ((NOT AS AND NOT UDS AND RW AND NOT CP_CS)
|
|
OR (NOT AS AND NOT LDS AND RW AND NOT CP_CS));
|
|
|
|
|
|
CP_WE <= NOT ((NOT AS AND NOT CP_WE_S AND CP_WE_QUIRK));
|
|
|
|
FDCPE_CP_WE_QUIRK: FDCPE port map (CP_WE_QUIRK,CP_WE_S,SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0','0');
|
|
|
|
FDCPE_CP_WE_S: FDCPE port map (CP_WE_S,CP_WE_S_D,SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0','0');
|
|
CP_WE_S_D <= ((NOT AS AND NOT UDS AND NOT RW AND NOT CP_CS)
|
|
OR (NOT AS AND NOT LDS AND NOT RW AND NOT CP_CS));
|
|
|
|
|
|
D_I(0) <= ((FCS AND NOT AS AND RW AND AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT FCS AND Z3_DATA(16) AND RW AND LAN_ACCESS)
|
|
OR (FCS AND DQ(0).PIN)
|
|
OR (NOT RW AND DQ(0).PIN)
|
|
OR (NOT LAN_ACCESS AND DQ(0).PIN)
|
|
OR (NOT AS AND RW AND AUTOCONFIG_Z2_ACCESS AND NOT LAN_ACCESS));
|
|
D(0) <= D_I(0) when D_OE(0) = '1' else 'Z';
|
|
D_OE(0) <= D_9_IOBUFE/D_9_IOBUFE_TRST;
|
|
|
|
|
|
D_I(1) <= ((FCS AND NOT AS AND RW AND AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT FCS AND Z3_DATA(17) AND RW AND LAN_ACCESS)
|
|
OR (FCS AND DQ(1).PIN)
|
|
OR (NOT RW AND DQ(1).PIN)
|
|
OR (NOT LAN_ACCESS AND DQ(1).PIN)
|
|
OR (NOT AS AND RW AND AUTOCONFIG_Z2_ACCESS AND NOT LAN_ACCESS));
|
|
D(1) <= D_I(1) when D_OE(1) = '1' else 'Z';
|
|
D_OE(1) <= D_9_IOBUFE/D_9_IOBUFE_TRST;
|
|
|
|
|
|
D_I(2) <= ((FCS AND NOT AS AND RW AND AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT FCS AND Z3_DATA(18) AND RW AND LAN_ACCESS)
|
|
OR (FCS AND DQ(2).PIN)
|
|
OR (NOT RW AND DQ(2).PIN)
|
|
OR (NOT LAN_ACCESS AND DQ(2).PIN)
|
|
OR (NOT AS AND RW AND AUTOCONFIG_Z2_ACCESS AND NOT LAN_ACCESS));
|
|
D(2) <= D_I(2) when D_OE(2) = '1' else 'Z';
|
|
D_OE(2) <= D_9_IOBUFE/D_9_IOBUFE_TRST;
|
|
|
|
|
|
D_I(3) <= ((FCS AND DQ(3).PIN)
|
|
OR (NOT LAN_ACCESS AND DQ(3).PIN)
|
|
OR (FCS AND NOT AS AND RW AND AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT FCS AND Z3_DATA(19) AND RW AND LAN_ACCESS)
|
|
OR (NOT AS AND RW AND AUTOCONFIG_Z2_ACCESS AND NOT LAN_ACCESS)
|
|
OR (NOT RW AND DQ(3).PIN));
|
|
D(3) <= D_I(3) when D_OE(3) = '1' else 'Z';
|
|
D_OE(3) <= D_9_IOBUFE/D_9_IOBUFE_TRST;
|
|
|
|
|
|
D_I(4) <= ((FCS AND NOT AS AND RW AND AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT FCS AND Z3_DATA(20) AND RW AND LAN_ACCESS)
|
|
OR (NOT AS AND RW AND AUTOCONFIG_Z2_ACCESS AND NOT LAN_ACCESS)
|
|
OR (FCS AND DQ(4).PIN)
|
|
OR (NOT RW AND DQ(4).PIN)
|
|
OR (NOT LAN_ACCESS AND DQ(4).PIN));
|
|
D(4) <= D_I(4) when D_OE(4) = '1' else 'Z';
|
|
D_OE(4) <= D_9_IOBUFE/D_9_IOBUFE_TRST;
|
|
|
|
|
|
D_I(5) <= ((FCS AND NOT AS AND RW AND AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT FCS AND Z3_DATA(21) AND RW AND LAN_ACCESS)
|
|
OR (FCS AND DQ(5).PIN)
|
|
OR (NOT RW AND DQ(5).PIN)
|
|
OR (NOT LAN_ACCESS AND DQ(5).PIN)
|
|
OR (NOT AS AND RW AND AUTOCONFIG_Z2_ACCESS AND NOT LAN_ACCESS));
|
|
D(5) <= D_I(5) when D_OE(5) = '1' else 'Z';
|
|
D_OE(5) <= D_9_IOBUFE/D_9_IOBUFE_TRST;
|
|
|
|
|
|
D_I(6) <= ((FCS AND NOT AS AND RW AND AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT FCS AND Z3_DATA(22) AND RW AND LAN_ACCESS)
|
|
OR (FCS AND DQ(6).PIN)
|
|
OR (NOT RW AND DQ(6).PIN)
|
|
OR (NOT LAN_ACCESS AND DQ(6).PIN)
|
|
OR (NOT AS AND RW AND AUTOCONFIG_Z2_ACCESS AND NOT LAN_ACCESS));
|
|
D(6) <= D_I(6) when D_OE(6) = '1' else 'Z';
|
|
D_OE(6) <= D_9_IOBUFE/D_9_IOBUFE_TRST;
|
|
|
|
|
|
D_I(7) <= ((FCS AND NOT AS AND RW AND AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT FCS AND Z3_DATA(23) AND RW AND LAN_ACCESS)
|
|
OR (FCS AND DQ(7).PIN)
|
|
OR (NOT RW AND DQ(7).PIN)
|
|
OR (NOT LAN_ACCESS AND DQ(7).PIN)
|
|
OR (NOT AS AND RW AND AUTOCONFIG_Z2_ACCESS AND NOT LAN_ACCESS));
|
|
D(7) <= D_I(7) when D_OE(7) = '1' else 'Z';
|
|
D_OE(7) <= D_9_IOBUFE/D_9_IOBUFE_TRST;
|
|
|
|
|
|
D_I(8) <= ((FCS AND DQ(0).PIN)
|
|
OR (NOT LAN_ACCESS AND DQ(0).PIN)
|
|
OR (FCS AND NOT AS AND RW AND AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT FCS AND Z3_DATA(24) AND RW AND LAN_ACCESS)
|
|
OR (NOT AS AND RW AND AUTOCONFIG_Z2_ACCESS AND NOT LAN_ACCESS)
|
|
OR (NOT RW AND DQ(0).PIN));
|
|
D(8) <= D_I(8) when D_OE(8) = '1' else 'Z';
|
|
D_OE(8) <= D_9_IOBUFE/D_9_IOBUFE_TRST;
|
|
|
|
|
|
D_I(9) <= ((FCS AND NOT AS AND RW AND AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT FCS AND Z3_DATA(25) AND RW AND LAN_ACCESS)
|
|
OR (FCS AND DQ(1).PIN)
|
|
OR (NOT RW AND DQ(1).PIN)
|
|
OR (NOT LAN_ACCESS AND DQ(1).PIN)
|
|
OR (NOT AS AND RW AND AUTOCONFIG_Z2_ACCESS AND NOT LAN_ACCESS));
|
|
D(9) <= D_I(9) when D_OE(9) = '1' else 'Z';
|
|
D_OE(9) <= D_9_IOBUFE/D_9_IOBUFE_TRST;
|
|
|
|
|
|
D_I(10) <= ((FCS AND DQ(2).PIN)
|
|
OR (FCS AND NOT AS AND RW AND AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT FCS AND Z3_DATA(26) AND RW AND LAN_ACCESS)
|
|
OR (NOT AS AND RW AND AUTOCONFIG_Z2_ACCESS AND NOT LAN_ACCESS)
|
|
OR (NOT RW AND DQ(2).PIN)
|
|
OR (NOT LAN_ACCESS AND DQ(2).PIN));
|
|
D(10) <= D_I(10) when D_OE(10) = '1' else 'Z';
|
|
D_OE(10) <= D_9_IOBUFE/D_9_IOBUFE_TRST;
|
|
|
|
|
|
D_I(11) <= ((FCS AND NOT AS AND RW AND AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT FCS AND Z3_DATA(27) AND RW AND LAN_ACCESS)
|
|
OR (FCS AND DQ(3).PIN)
|
|
OR (NOT RW AND DQ(3).PIN)
|
|
OR (NOT LAN_ACCESS AND DQ(3).PIN)
|
|
OR (NOT AS AND RW AND AUTOCONFIG_Z2_ACCESS AND NOT LAN_ACCESS));
|
|
D(11) <= D_I(11) when D_OE(11) = '1' else 'Z';
|
|
D_OE(11) <= D_9_IOBUFE/D_9_IOBUFE_TRST;
|
|
|
|
|
|
D_I(12) <= ((FCS AND AS AND DQ(4).PIN)
|
|
OR (NOT FCS AND Z3_DATA(28) AND RW AND LAN_ACCESS)
|
|
OR (FCS AND NOT AS AND RW AND AUTOCONFIG_Z2_ACCESS AND
|
|
D_Z2_OUT(0))
|
|
OR (NOT AS AND RW AND AUTOCONFIG_Z2_ACCESS AND NOT LAN_ACCESS AND
|
|
D_Z2_OUT(0))
|
|
OR (NOT RW AND DQ(4).PIN)
|
|
OR (FCS AND NOT AUTOCONFIG_Z2_ACCESS AND DQ(4).PIN)
|
|
OR (AS AND NOT LAN_ACCESS AND DQ(4).PIN)
|
|
OR (NOT AUTOCONFIG_Z2_ACCESS AND NOT LAN_ACCESS AND DQ(4).PIN));
|
|
D(12) <= D_I(12) when D_OE(12) = '1' else 'Z';
|
|
D_OE(12) <= D_9_IOBUFE/D_9_IOBUFE_TRST;
|
|
|
|
|
|
D_I(13) <= ((FCS AND AS AND DQ(5).PIN)
|
|
OR (FCS AND NOT AUTOCONFIG_Z2_ACCESS AND DQ(5).PIN)
|
|
OR (NOT FCS AND Z3_DATA(29) AND RW AND LAN_ACCESS)
|
|
OR (FCS AND NOT AS AND RW AND AUTOCONFIG_Z2_ACCESS AND
|
|
D_Z2_OUT(1))
|
|
OR (NOT AS AND RW AND AUTOCONFIG_Z2_ACCESS AND NOT LAN_ACCESS AND
|
|
D_Z2_OUT(1))
|
|
OR (NOT RW AND DQ(5).PIN)
|
|
OR (AS AND NOT LAN_ACCESS AND DQ(5).PIN)
|
|
OR (NOT AUTOCONFIG_Z2_ACCESS AND NOT LAN_ACCESS AND DQ(5).PIN));
|
|
D(13) <= D_I(13) when D_OE(13) = '1' else 'Z';
|
|
D_OE(13) <= D_9_IOBUFE/D_9_IOBUFE_TRST;
|
|
|
|
|
|
D_I(14) <= ((FCS AND AS AND DQ(6).PIN)
|
|
OR (NOT FCS AND Z3_DATA(30) AND RW AND LAN_ACCESS)
|
|
OR (FCS AND NOT AS AND RW AND AUTOCONFIG_Z2_ACCESS AND
|
|
D_Z2_OUT(2))
|
|
OR (NOT AS AND RW AND AUTOCONFIG_Z2_ACCESS AND NOT LAN_ACCESS AND
|
|
D_Z2_OUT(2))
|
|
OR (NOT RW AND DQ(6).PIN)
|
|
OR (FCS AND NOT AUTOCONFIG_Z2_ACCESS AND DQ(6).PIN)
|
|
OR (AS AND NOT LAN_ACCESS AND DQ(6).PIN)
|
|
OR (NOT AUTOCONFIG_Z2_ACCESS AND NOT LAN_ACCESS AND DQ(6).PIN));
|
|
D(14) <= D_I(14) when D_OE(14) = '1' else 'Z';
|
|
D_OE(14) <= D_9_IOBUFE/D_9_IOBUFE_TRST;
|
|
|
|
|
|
D_I(15) <= ((FCS AND AS AND DQ(7).PIN)
|
|
OR (NOT FCS AND Z3_DATA(31) AND RW AND LAN_ACCESS)
|
|
OR (FCS AND NOT AS AND RW AND AUTOCONFIG_Z2_ACCESS AND
|
|
D_Z2_OUT(3))
|
|
OR (NOT AS AND RW AND AUTOCONFIG_Z2_ACCESS AND NOT LAN_ACCESS AND
|
|
D_Z2_OUT(3))
|
|
OR (NOT RW AND DQ(7).PIN)
|
|
OR (FCS AND NOT AUTOCONFIG_Z2_ACCESS AND DQ(7).PIN)
|
|
OR (AS AND NOT LAN_ACCESS AND DQ(7).PIN)
|
|
OR (NOT AUTOCONFIG_Z2_ACCESS AND NOT LAN_ACCESS AND DQ(7).PIN));
|
|
D(15) <= D_I(15) when D_OE(15) = '1' else 'Z';
|
|
D_OE(15) <= D_9_IOBUFE/D_9_IOBUFE_TRST;
|
|
|
|
|
|
DQ_I(0) <= ((NOT FCS AND RESET AND NOT UDS AND NOT RW AND LAN_ACCESS AND
|
|
DQ_DATA(0))
|
|
OR (NOT FCS AND RESET AND NOT LDS AND NOT RW AND LAN_ACCESS AND
|
|
DQ_DATA(0))
|
|
OR (NOT FCS AND RESET AND NOT DS1 AND NOT RW AND LAN_ACCESS AND
|
|
DQ_DATA(0))
|
|
OR (NOT FCS AND RESET AND NOT DS0 AND NOT RW AND LAN_ACCESS AND
|
|
DQ_DATA(0))
|
|
OR (RESET AND UDS AND LDS AND DS1 AND DS0 AND D(0).PIN)
|
|
OR (FCS AND RESET AND D(0).PIN)
|
|
OR (RESET AND RW AND D(0).PIN)
|
|
OR (RESET AND NOT LAN_ACCESS AND D(0).PIN));
|
|
DQ(0) <= DQ_I(0) when DQ_OE(0) = '1' else 'Z';
|
|
DQ_OE(0) <= DQ_9_IOBUFE/DQ_9_IOBUFE_TRST;
|
|
|
|
|
|
DQ_I(1) <= ((NOT FCS AND RESET AND NOT UDS AND NOT RW AND LAN_ACCESS AND
|
|
DQ_DATA(1))
|
|
OR (NOT FCS AND RESET AND NOT LDS AND NOT RW AND LAN_ACCESS AND
|
|
DQ_DATA(1))
|
|
OR (NOT FCS AND RESET AND NOT DS1 AND NOT RW AND LAN_ACCESS AND
|
|
DQ_DATA(1))
|
|
OR (RESET AND UDS AND LDS AND DS1 AND DS0 AND D(1).PIN)
|
|
OR (NOT FCS AND RESET AND NOT DS0 AND NOT RW AND LAN_ACCESS AND
|
|
DQ_DATA(1))
|
|
OR (NOT RESET AND LAN_D_INIT(1))
|
|
OR (FCS AND RESET AND D(1).PIN)
|
|
OR (RESET AND RW AND D(1).PIN)
|
|
OR (RESET AND NOT LAN_ACCESS AND D(1).PIN));
|
|
DQ(1) <= DQ_I(1) when DQ_OE(1) = '1' else 'Z';
|
|
DQ_OE(1) <= DQ_9_IOBUFE/DQ_9_IOBUFE_TRST;
|
|
|
|
|
|
DQ_I(2) <= ((DQ_5_IOBUFE.EXP)
|
|
OR (FCS AND RESET AND D(2).PIN)
|
|
OR (RESET AND RW AND D(2).PIN)
|
|
OR (RESET AND NOT LAN_ACCESS AND D(2).PIN)
|
|
OR (NOT FCS AND RESET AND NOT UDS AND NOT RW AND LAN_ACCESS AND
|
|
DQ_DATA(2))
|
|
OR (RESET AND UDS AND LDS AND DS1 AND DS0 AND D(2).PIN));
|
|
DQ(2) <= DQ_I(2) when DQ_OE(2) = '1' else 'Z';
|
|
DQ_OE(2) <= DQ_9_IOBUFE/DQ_9_IOBUFE_TRST;
|
|
|
|
|
|
DQ_I(3) <= ((NOT FCS AND RESET AND NOT UDS AND NOT RW AND LAN_ACCESS AND
|
|
DQ_DATA(3))
|
|
OR (NOT FCS AND RESET AND NOT LDS AND NOT RW AND LAN_ACCESS AND
|
|
DQ_DATA(3))
|
|
OR (NOT FCS AND RESET AND NOT DS1 AND NOT RW AND LAN_ACCESS AND
|
|
DQ_DATA(3))
|
|
OR (NOT FCS AND RESET AND NOT DS0 AND NOT RW AND LAN_ACCESS AND
|
|
DQ_DATA(3))
|
|
OR (FCS AND RESET AND D(3).PIN)
|
|
OR (RESET AND RW AND D(3).PIN)
|
|
OR (RESET AND NOT LAN_ACCESS AND D(3).PIN)
|
|
OR (RESET AND UDS AND LDS AND DS1 AND DS0 AND D(3).PIN));
|
|
DQ(3) <= DQ_I(3) when DQ_OE(3) = '1' else 'Z';
|
|
DQ_OE(3) <= DQ_9_IOBUFE/DQ_9_IOBUFE_TRST;
|
|
|
|
|
|
DQ_I(4) <= DQ(4)_BUFR;
|
|
DQ(4) <= DQ_I(4) when DQ_OE(4) = '1' else 'Z';
|
|
DQ_OE(4) <= DQ_9_IOBUFE/DQ_9_IOBUFE_TRST;
|
|
|
|
|
|
DQ(4)_BUFR <= ((DQ_10_IOBUFE.EXP)
|
|
OR (FCS AND RESET AND D(4).PIN)
|
|
OR (RESET AND RW AND D(4).PIN)
|
|
OR (RESET AND NOT LAN_ACCESS AND D(4).PIN)
|
|
OR (NOT FCS AND RESET AND NOT UDS AND NOT RW AND LAN_ACCESS AND
|
|
DQ_DATA(4))
|
|
OR (RESET AND UDS AND LDS AND DS1 AND DS0 AND D(4).PIN)
|
|
OR (NOT RESET AND LAN_D_INIT(1)));
|
|
|
|
|
|
DQ_I(5) <= ((_19_.EXP)
|
|
OR (FCS AND RESET AND D(5).PIN)
|
|
OR (RESET AND RW AND D(5).PIN)
|
|
OR (NOT FCS AND RESET AND NOT UDS AND NOT RW AND LAN_ACCESS AND
|
|
DQ_DATA(5))
|
|
OR (NOT FCS AND RESET AND NOT LDS AND NOT RW AND LAN_ACCESS AND
|
|
DQ_DATA(5))
|
|
OR (RESET AND UDS AND LDS AND DS1 AND DS0 AND D(5).PIN)
|
|
OR (RESET AND NOT LAN_ACCESS AND D(5).PIN));
|
|
DQ(5) <= DQ_I(5) when DQ_OE(5) = '1' else 'Z';
|
|
DQ_OE(5) <= DQ_9_IOBUFE/DQ_9_IOBUFE_TRST;
|
|
|
|
|
|
DQ_I(6) <= ((_18_.EXP)
|
|
OR (FCS AND RESET AND D(6).PIN)
|
|
OR (RESET AND RW AND D(6).PIN)
|
|
OR (RESET AND NOT LAN_ACCESS AND D(6).PIN)
|
|
OR (NOT FCS AND RESET AND NOT UDS AND NOT RW AND LAN_ACCESS AND
|
|
DQ_DATA(6))
|
|
OR (RESET AND UDS AND LDS AND DS1 AND DS0 AND D(6).PIN));
|
|
DQ(6) <= DQ_I(6) when DQ_OE(6) = '1' else 'Z';
|
|
DQ_OE(6) <= DQ_9_IOBUFE/DQ_9_IOBUFE_TRST;
|
|
|
|
|
|
DQ_I(7) <= ((NOT FCS AND RESET AND NOT UDS AND NOT RW AND LAN_ACCESS AND
|
|
DQ_DATA(7))
|
|
OR (NOT FCS AND RESET AND NOT LDS AND NOT RW AND LAN_ACCESS AND
|
|
DQ_DATA(7))
|
|
OR (NOT FCS AND RESET AND NOT DS1 AND NOT RW AND LAN_ACCESS AND
|
|
DQ_DATA(7))
|
|
OR (NOT FCS AND RESET AND NOT DS0 AND NOT RW AND LAN_ACCESS AND
|
|
DQ_DATA(7))
|
|
OR (FCS AND RESET AND D(7).PIN)
|
|
OR (RESET AND RW AND D(7).PIN)
|
|
OR (RESET AND NOT LAN_ACCESS AND D(7).PIN)
|
|
OR (RESET AND UDS AND LDS AND DS1 AND DS0 AND D(7).PIN));
|
|
DQ(7) <= DQ_I(7) when DQ_OE(7) = '1' else 'Z';
|
|
DQ_OE(7) <= DQ_9_IOBUFE/DQ_9_IOBUFE_TRST;
|
|
|
|
|
|
DQ(8)_BUFR <= ((NOT FCS AND RESET AND NOT UDS AND NOT RW AND LAN_ACCESS AND
|
|
DQ_DATA(8))
|
|
OR (NOT FCS AND RESET AND NOT LDS AND NOT RW AND LAN_ACCESS AND
|
|
DQ_DATA(8))
|
|
OR (NOT FCS AND RESET AND NOT DS1 AND NOT RW AND LAN_ACCESS AND
|
|
DQ_DATA(8))
|
|
OR (NOT FCS AND RESET AND NOT DS0 AND NOT RW AND LAN_ACCESS AND
|
|
DQ_DATA(8))
|
|
OR (NOT RESET AND LAN_D_INIT(8))
|
|
OR (FCS AND RESET AND D(8).PIN)
|
|
OR (RESET AND D(8).PIN AND RW)
|
|
OR (RESET AND D(8).PIN AND NOT LAN_ACCESS)
|
|
OR (RESET AND D(8).PIN AND UDS AND LDS AND DS1 AND DS0));
|
|
|
|
|
|
DQ_I(8) <= DQ(8)_BUFR;
|
|
DQ(8) <= DQ_I(8) when DQ_OE(8) = '1' else 'Z';
|
|
DQ_OE(8) <= DQ_9_IOBUFE/DQ_9_IOBUFE_TRST;
|
|
|
|
|
|
DQ_I(9) <= ((DQ_11_IOBUFE.EXP)
|
|
OR (FCS AND RESET AND D(9).PIN)
|
|
OR (NOT FCS AND RESET AND NOT UDS AND NOT RW AND LAN_ACCESS AND
|
|
DQ_DATA(9))
|
|
OR (NOT FCS AND RESET AND NOT LDS AND NOT RW AND LAN_ACCESS AND
|
|
DQ_DATA(9))
|
|
OR (NOT FCS AND RESET AND NOT DS1 AND NOT RW AND LAN_ACCESS AND
|
|
DQ_DATA(9))
|
|
OR (RESET AND D(9).PIN AND UDS AND LDS AND DS1 AND DS0)
|
|
OR (NOT RESET AND LAN_D_INIT(1))
|
|
OR (RESET AND D(9).PIN AND RW)
|
|
OR (RESET AND D(9).PIN AND NOT LAN_ACCESS));
|
|
DQ(9) <= DQ_I(9) when DQ_OE(9) = '1' else 'Z';
|
|
DQ_OE(9) <= DQ_9_IOBUFE/DQ_9_IOBUFE_TRST;
|
|
|
|
|
|
DQ_I(10) <= ((EXP51_.EXP)
|
|
OR (FCS AND RESET AND D(10).PIN)
|
|
OR (RESET AND D(10).PIN AND RW)
|
|
OR (RESET AND D(10).PIN AND NOT LAN_ACCESS)
|
|
OR (NOT FCS AND RESET AND NOT UDS AND NOT RW AND LAN_ACCESS AND
|
|
DQ_DATA(10))
|
|
OR (RESET AND D(10).PIN AND UDS AND LDS AND DS1 AND DS0)
|
|
OR (NOT RESET AND LAN_D_INIT(8)));
|
|
DQ(10) <= DQ_I(10) when DQ_OE(10) = '1' else 'Z';
|
|
DQ_OE(10) <= DQ_9_IOBUFE/DQ_9_IOBUFE_TRST;
|
|
|
|
|
|
DQ_I(11) <= ((DQ_13_IOBUFE.EXP)
|
|
OR (FCS AND RESET AND D(11).PIN)
|
|
OR (NOT FCS AND RESET AND NOT UDS AND NOT RW AND LAN_ACCESS AND
|
|
DQ_DATA(11))
|
|
OR (NOT FCS AND RESET AND NOT LDS AND NOT RW AND LAN_ACCESS AND
|
|
DQ_DATA(11))
|
|
OR (NOT FCS AND RESET AND NOT DS1 AND NOT RW AND LAN_ACCESS AND
|
|
DQ_DATA(11))
|
|
OR (RESET AND D(11).PIN AND UDS AND LDS AND DS1 AND DS0)
|
|
OR (NOT RESET AND LAN_D_INIT(8))
|
|
OR (RESET AND D(11).PIN AND RW)
|
|
OR (RESET AND D(11).PIN AND NOT LAN_ACCESS));
|
|
DQ(11) <= DQ_I(11) when DQ_OE(11) = '1' else 'Z';
|
|
DQ_OE(11) <= DQ_9_IOBUFE/DQ_9_IOBUFE_TRST;
|
|
|
|
|
|
DQ_I(12) <= ((NOT FCS AND RESET AND NOT UDS AND NOT RW AND LAN_ACCESS AND
|
|
DQ_DATA(12))
|
|
OR (NOT FCS AND RESET AND NOT LDS AND NOT RW AND LAN_ACCESS AND
|
|
DQ_DATA(12))
|
|
OR (NOT FCS AND RESET AND NOT DS1 AND NOT RW AND LAN_ACCESS AND
|
|
DQ_DATA(12))
|
|
OR (NOT FCS AND RESET AND NOT DS0 AND NOT RW AND LAN_ACCESS AND
|
|
DQ_DATA(12))
|
|
OR (FCS AND RESET AND D(12).PIN)
|
|
OR (RESET AND D(12).PIN AND RW)
|
|
OR (RESET AND D(12).PIN AND NOT LAN_ACCESS)
|
|
OR (RESET AND D(12).PIN AND UDS AND LDS AND DS1 AND DS0));
|
|
DQ(12) <= DQ_I(12) when DQ_OE(12) = '1' else 'Z';
|
|
DQ_OE(12) <= DQ_9_IOBUFE/DQ_9_IOBUFE_TRST;
|
|
|
|
|
|
DQ_I(13) <= ((NOT FCS AND RESET AND NOT UDS AND NOT RW AND LAN_ACCESS AND
|
|
DQ_DATA(13))
|
|
OR (NOT FCS AND RESET AND NOT LDS AND NOT RW AND LAN_ACCESS AND
|
|
DQ_DATA(13))
|
|
OR (NOT FCS AND RESET AND NOT DS1 AND NOT RW AND LAN_ACCESS AND
|
|
DQ_DATA(13))
|
|
OR (NOT FCS AND RESET AND NOT DS0 AND NOT RW AND LAN_ACCESS AND
|
|
DQ_DATA(13))
|
|
OR (RESET AND D(13).PIN AND UDS AND LDS AND DS1 AND DS0)
|
|
OR (FCS AND RESET AND D(13).PIN)
|
|
OR (RESET AND D(13).PIN AND RW)
|
|
OR (RESET AND D(13).PIN AND NOT LAN_ACCESS));
|
|
DQ(13) <= DQ_I(13) when DQ_OE(13) = '1' else 'Z';
|
|
DQ_OE(13) <= DQ_9_IOBUFE/DQ_9_IOBUFE_TRST;
|
|
|
|
|
|
DQ_I(14) <= ((LAN_WRH_OBUF.EXP)
|
|
OR (FCS AND RESET AND D(14).PIN)
|
|
OR (RESET AND D(14).PIN AND RW)
|
|
OR (NOT FCS AND RESET AND NOT UDS AND NOT RW AND LAN_ACCESS AND
|
|
DQ_DATA(14))
|
|
OR (NOT FCS AND RESET AND NOT LDS AND NOT RW AND LAN_ACCESS AND
|
|
DQ_DATA(14))
|
|
OR (RESET AND D(14).PIN AND UDS AND LDS AND DS1 AND DS0)
|
|
OR (RESET AND D(14).PIN AND NOT LAN_ACCESS));
|
|
DQ(14) <= DQ_I(14) when DQ_OE(14) = '1' else 'Z';
|
|
DQ_OE(14) <= DQ_9_IOBUFE/DQ_9_IOBUFE_TRST;
|
|
|
|
|
|
DQ_I(15) <= ((NOT FCS AND RESET AND NOT UDS AND NOT RW AND LAN_ACCESS AND
|
|
DQ_DATA(15))
|
|
OR (NOT FCS AND RESET AND NOT LDS AND NOT RW AND LAN_ACCESS AND
|
|
DQ_DATA(15))
|
|
OR (NOT FCS AND RESET AND NOT DS1 AND NOT RW AND LAN_ACCESS AND
|
|
DQ_DATA(15))
|
|
OR (NOT FCS AND RESET AND NOT DS0 AND NOT RW AND LAN_ACCESS AND
|
|
DQ_DATA(15))
|
|
OR (FCS AND RESET AND D(15).PIN)
|
|
OR (RESET AND D(15).PIN AND RW)
|
|
OR (RESET AND D(15).PIN AND NOT LAN_ACCESS)
|
|
OR (RESET AND D(15).PIN AND UDS AND LDS AND DS1 AND DS0));
|
|
DQ(15) <= DQ_I(15) when DQ_OE(15) = '1' else 'Z';
|
|
DQ_OE(15) <= DQ_9_IOBUFE/DQ_9_IOBUFE_TRST;
|
|
|
|
|
|
DQ_9_IOBUFE/DQ_9_IOBUFE_TRST <= ((NOT RESET)
|
|
OR (NOT FCS AND NOT LDS AND NOT RW AND LAN_ACCESS)
|
|
OR (NOT FCS AND NOT DS1 AND NOT RW AND LAN_ACCESS)
|
|
OR (NOT FCS AND NOT DS0 AND NOT RW AND LAN_ACCESS)
|
|
OR (NOT AS AND NOT RW AND NOT CP_CS)
|
|
OR (NOT FCS AND NOT UDS AND NOT RW AND LAN_ACCESS));
|
|
|
|
FDCPE_DQ_DATA0: FDCPE port map (DQ_DATA(0),DQ_DATA_D(0),CLK_EXT,'0',NOT Z3_DATA(9)/Z3_DATA(9)_SETF__$INT);
|
|
DQ_DATA_D(0) <= ((LAN_SM_FSM_FFd8.EXP)
|
|
OR (D(8).PIN AND NOT UDS AND DQ_SWAP AND LAN_SM_FSM_FFd13)
|
|
OR (D(8).PIN AND NOT LDS AND DQ_SWAP AND LAN_SM_FSM_FFd13)
|
|
OR (NOT UDS AND NOT DQ_SWAP AND LAN_SM_FSM_FFd13 AND D(0).PIN)
|
|
OR (NOT LDS AND NOT DQ_SWAP AND LAN_SM_FSM_FFd13 AND D(0).PIN)
|
|
OR (UDS AND LDS AND A(16).PIN AND DQ_SWAP AND
|
|
LAN_SM_FSM_FFd13)
|
|
OR (DQ_DATA(0) AND NOT $OpTx$FX_DC$1323)
|
|
OR (A(16).PIN AND DQ_SWAP AND LAN_SM_FSM_FFd3)
|
|
OR (NOT DQ_SWAP AND LAN_SM_FSM_FFd3 AND A(8).PIN));
|
|
|
|
FDCPE_DQ_DATA1: FDCPE port map (DQ_DATA(1),DQ_DATA_D(1),CLK_EXT,'0',NOT Z3_DATA(9)/Z3_DATA(9)_SETF__$INT);
|
|
DQ_DATA_D(1) <= ((D(9).PIN AND NOT UDS AND DQ_SWAP AND LAN_SM_FSM_FFd13)
|
|
OR (D(9).PIN AND NOT LDS AND DQ_SWAP AND LAN_SM_FSM_FFd13)
|
|
OR (NOT LDS AND NOT DQ_SWAP AND LAN_SM_FSM_FFd13 AND D(1).PIN)
|
|
OR (UDS AND LDS AND A(17).PIN AND DQ_SWAP AND
|
|
LAN_SM_FSM_FFd13)
|
|
OR (UDS AND LDS AND NOT DQ_SWAP AND A(9).PIN AND
|
|
LAN_SM_FSM_FFd13)
|
|
OR (DQ_DATA(1) AND NOT $OpTx$FX_DC$1323)
|
|
OR (A(17).PIN AND DQ_SWAP AND LAN_SM_FSM_FFd3)
|
|
OR (NOT DQ_SWAP AND LAN_SM_FSM_FFd3 AND A(9).PIN)
|
|
OR (NOT UDS AND NOT DQ_SWAP AND LAN_SM_FSM_FFd13 AND D(1).PIN));
|
|
|
|
FDCPE_DQ_DATA2: FDCPE port map (DQ_DATA(2),DQ_DATA_D(2),CLK_EXT,'0',NOT Z3_DATA(9)/Z3_DATA(9)_SETF__$INT);
|
|
DQ_DATA_D(2) <= ((D(10).PIN AND NOT UDS AND DQ_SWAP AND LAN_SM_FSM_FFd13)
|
|
OR (D(10).PIN AND NOT LDS AND DQ_SWAP AND LAN_SM_FSM_FFd13)
|
|
OR (NOT LDS AND NOT DQ_SWAP AND LAN_SM_FSM_FFd13 AND D(2).PIN)
|
|
OR (UDS AND LDS AND DQ_SWAP AND LAN_SM_FSM_FFd13 AND
|
|
A(18).PIN)
|
|
OR (UDS AND LDS AND NOT DQ_SWAP AND A(10).PIN AND
|
|
LAN_SM_FSM_FFd13)
|
|
OR (DQ_DATA(2) AND NOT $OpTx$FX_DC$1323)
|
|
OR (DQ_SWAP AND LAN_SM_FSM_FFd3 AND A(18).PIN)
|
|
OR (NOT DQ_SWAP AND LAN_SM_FSM_FFd3 AND A(10).PIN)
|
|
OR (NOT UDS AND NOT DQ_SWAP AND LAN_SM_FSM_FFd13 AND D(2).PIN));
|
|
|
|
FDCPE_DQ_DATA3: FDCPE port map (DQ_DATA(3),DQ_DATA_D(3),CLK_EXT,'0',NOT Z3_DATA(9)/Z3_DATA(9)_SETF__$INT);
|
|
DQ_DATA_D(3) <= ((DQ_DATA(7).EXP)
|
|
OR (D(11).PIN AND NOT UDS AND DQ_SWAP AND LAN_SM_FSM_FFd13)
|
|
OR (D(11).PIN AND NOT LDS AND DQ_SWAP AND LAN_SM_FSM_FFd13)
|
|
OR (NOT UDS AND NOT DQ_SWAP AND LAN_SM_FSM_FFd13 AND D(3).PIN)
|
|
OR (NOT LDS AND NOT DQ_SWAP AND LAN_SM_FSM_FFd13 AND D(3).PIN)
|
|
OR (UDS AND LDS AND A(19).PIN AND DQ_SWAP AND
|
|
LAN_SM_FSM_FFd13)
|
|
OR (DQ_DATA(3) AND NOT $OpTx$FX_DC$1323)
|
|
OR (A(19).PIN AND DQ_SWAP AND LAN_SM_FSM_FFd3)
|
|
OR (NOT DQ_SWAP AND LAN_SM_FSM_FFd3 AND A(11).PIN));
|
|
|
|
FDCPE_DQ_DATA4: FDCPE port map (DQ_DATA(4),DQ_DATA_D(4),CLK_EXT,'0',NOT Z3_DATA(9)/Z3_DATA(9)_SETF__$INT);
|
|
DQ_DATA_D(4) <= ((D(12).PIN AND NOT UDS AND DQ_SWAP AND LAN_SM_FSM_FFd13)
|
|
OR (D(12).PIN AND NOT LDS AND DQ_SWAP AND LAN_SM_FSM_FFd13)
|
|
OR (NOT LDS AND NOT DQ_SWAP AND LAN_SM_FSM_FFd13 AND D(4).PIN)
|
|
OR (UDS AND LDS AND DQ_SWAP AND LAN_SM_FSM_FFd13 AND
|
|
A(20).PIN)
|
|
OR (UDS AND LDS AND NOT DQ_SWAP AND A(12).PIN AND
|
|
LAN_SM_FSM_FFd13)
|
|
OR (DQ_DATA(4) AND NOT $OpTx$FX_DC$1323)
|
|
OR (DQ_SWAP AND LAN_SM_FSM_FFd3 AND A(20).PIN)
|
|
OR (NOT DQ_SWAP AND LAN_SM_FSM_FFd3 AND A(12).PIN)
|
|
OR (NOT UDS AND NOT DQ_SWAP AND LAN_SM_FSM_FFd13 AND D(4).PIN));
|
|
|
|
FDCPE_DQ_DATA5: FDCPE port map (DQ_DATA(5),DQ_DATA_D(5),CLK_EXT,'0',NOT Z3_DATA(9)/Z3_DATA(9)_SETF__$INT);
|
|
DQ_DATA_D(5) <= ((D(13).PIN AND NOT UDS AND DQ_SWAP AND LAN_SM_FSM_FFd13)
|
|
OR (D(13).PIN AND NOT LDS AND DQ_SWAP AND LAN_SM_FSM_FFd13)
|
|
OR (NOT LDS AND NOT DQ_SWAP AND LAN_SM_FSM_FFd13 AND D(5).PIN)
|
|
OR (UDS AND LDS AND A(21).PIN AND DQ_SWAP AND
|
|
LAN_SM_FSM_FFd13)
|
|
OR (UDS AND LDS AND NOT DQ_SWAP AND A(13).PIN AND
|
|
LAN_SM_FSM_FFd13)
|
|
OR (DQ_DATA(5) AND NOT $OpTx$FX_DC$1323)
|
|
OR (A(21).PIN AND DQ_SWAP AND LAN_SM_FSM_FFd3)
|
|
OR (NOT DQ_SWAP AND LAN_SM_FSM_FFd3 AND A(13).PIN)
|
|
OR (NOT UDS AND NOT DQ_SWAP AND LAN_SM_FSM_FFd13 AND D(5).PIN));
|
|
|
|
FDCPE_DQ_DATA6: FDCPE port map (DQ_DATA(6),DQ_DATA_D(6),CLK_EXT,'0',NOT Z3_DATA(9)/Z3_DATA(9)_SETF__$INT);
|
|
DQ_DATA_D(6) <= ((D(14).PIN AND NOT UDS AND DQ_SWAP AND LAN_SM_FSM_FFd13)
|
|
OR (D(14).PIN AND NOT LDS AND DQ_SWAP AND LAN_SM_FSM_FFd13)
|
|
OR (NOT LDS AND NOT DQ_SWAP AND LAN_SM_FSM_FFd13 AND D(6).PIN)
|
|
OR (UDS AND LDS AND A(22).PIN AND DQ_SWAP AND
|
|
LAN_SM_FSM_FFd13)
|
|
OR (UDS AND LDS AND NOT DQ_SWAP AND A(14).PIN AND
|
|
LAN_SM_FSM_FFd13)
|
|
OR (DQ_DATA(6) AND NOT $OpTx$FX_DC$1323)
|
|
OR (A(22).PIN AND DQ_SWAP AND LAN_SM_FSM_FFd3)
|
|
OR (NOT DQ_SWAP AND LAN_SM_FSM_FFd3 AND A(14).PIN)
|
|
OR (NOT UDS AND NOT DQ_SWAP AND LAN_SM_FSM_FFd13 AND D(6).PIN));
|
|
|
|
FDCPE_DQ_DATA7: FDCPE port map (DQ_DATA(7),DQ_DATA_D(7),CLK_EXT,'0',NOT Z3_DATA(9)/Z3_DATA(9)_SETF__$INT);
|
|
DQ_DATA_D(7) <= ((DQ_9_IOBUFE.EXP)
|
|
OR (D(15).PIN AND NOT UDS AND DQ_SWAP AND LAN_SM_FSM_FFd13)
|
|
OR (D(15).PIN AND NOT LDS AND DQ_SWAP AND LAN_SM_FSM_FFd13)
|
|
OR (NOT UDS AND NOT DQ_SWAP AND LAN_SM_FSM_FFd13 AND D(7).PIN)
|
|
OR (NOT LDS AND NOT DQ_SWAP AND LAN_SM_FSM_FFd13 AND D(7).PIN)
|
|
OR (UDS AND LDS AND A(23).PIN AND DQ_SWAP AND
|
|
LAN_SM_FSM_FFd13)
|
|
OR (DQ_DATA(7) AND NOT $OpTx$FX_DC$1323)
|
|
OR (A(23).PIN AND DQ_SWAP AND LAN_SM_FSM_FFd3)
|
|
OR (NOT DQ_SWAP AND LAN_SM_FSM_FFd3 AND A(15).PIN));
|
|
|
|
FDCPE_DQ_DATA8: FDCPE port map (DQ_DATA(8),DQ_DATA_D(8),CLK_EXT,'0',NOT Z3_DATA(9)/Z3_DATA(9)_SETF__$INT);
|
|
DQ_DATA_D(8) <= ((D(8).PIN AND NOT LDS AND NOT DQ_SWAP AND LAN_SM_FSM_FFd13)
|
|
OR (NOT UDS AND DQ_SWAP AND LAN_SM_FSM_FFd13 AND D(0).PIN)
|
|
OR (NOT LDS AND DQ_SWAP AND LAN_SM_FSM_FFd13 AND D(0).PIN)
|
|
OR (UDS AND LDS AND A(16).PIN AND NOT DQ_SWAP AND
|
|
LAN_SM_FSM_FFd13)
|
|
OR (UDS AND LDS AND DQ_SWAP AND A(8).PIN AND
|
|
LAN_SM_FSM_FFd13)
|
|
OR (DQ_DATA(8) AND NOT $OpTx$FX_DC$1323)
|
|
OR (A(16).PIN AND NOT DQ_SWAP AND LAN_SM_FSM_FFd3)
|
|
OR (DQ_SWAP AND LAN_SM_FSM_FFd3 AND A(8).PIN)
|
|
OR (D(8).PIN AND NOT UDS AND NOT DQ_SWAP AND LAN_SM_FSM_FFd13));
|
|
|
|
FDCPE_DQ_DATA9: FDCPE port map (DQ_DATA(9),DQ_DATA_D(9),CLK_EXT,'0',NOT Z3_DATA(9)/Z3_DATA(9)_SETF__$INT);
|
|
DQ_DATA_D(9) <= ((D(9).PIN AND NOT LDS AND NOT DQ_SWAP AND LAN_SM_FSM_FFd13)
|
|
OR (NOT UDS AND DQ_SWAP AND LAN_SM_FSM_FFd13 AND D(1).PIN)
|
|
OR (NOT LDS AND DQ_SWAP AND LAN_SM_FSM_FFd13 AND D(1).PIN)
|
|
OR (UDS AND LDS AND A(17).PIN AND NOT DQ_SWAP AND
|
|
LAN_SM_FSM_FFd13)
|
|
OR (UDS AND LDS AND DQ_SWAP AND A(9).PIN AND
|
|
LAN_SM_FSM_FFd13)
|
|
OR (DQ_DATA(9) AND NOT $OpTx$FX_DC$1323)
|
|
OR (A(17).PIN AND NOT DQ_SWAP AND LAN_SM_FSM_FFd3)
|
|
OR (DQ_SWAP AND LAN_SM_FSM_FFd3 AND A(9).PIN)
|
|
OR (D(9).PIN AND NOT UDS AND NOT DQ_SWAP AND LAN_SM_FSM_FFd13));
|
|
|
|
FDCPE_DQ_DATA10: FDCPE port map (DQ_DATA(10),DQ_DATA_D(10),CLK_EXT,'0',NOT Z3_DATA(9)/Z3_DATA(9)_SETF__$INT);
|
|
DQ_DATA_D(10) <= ((D(10).PIN AND NOT LDS AND NOT DQ_SWAP AND LAN_SM_FSM_FFd13)
|
|
OR (NOT UDS AND DQ_SWAP AND LAN_SM_FSM_FFd13 AND D(2).PIN)
|
|
OR (NOT LDS AND DQ_SWAP AND LAN_SM_FSM_FFd13 AND D(2).PIN)
|
|
OR (UDS AND LDS AND DQ_SWAP AND A(10).PIN AND
|
|
LAN_SM_FSM_FFd13)
|
|
OR (UDS AND LDS AND NOT DQ_SWAP AND LAN_SM_FSM_FFd13 AND
|
|
A(18).PIN)
|
|
OR (DQ_DATA(10) AND NOT $OpTx$FX_DC$1323)
|
|
OR (DQ_SWAP AND LAN_SM_FSM_FFd3 AND A(10).PIN)
|
|
OR (NOT DQ_SWAP AND LAN_SM_FSM_FFd3 AND A(18).PIN)
|
|
OR (D(10).PIN AND NOT UDS AND NOT DQ_SWAP AND LAN_SM_FSM_FFd13));
|
|
|
|
FDCPE_DQ_DATA11: FDCPE port map (DQ_DATA(11),DQ_DATA_D(11),CLK_EXT,'0',NOT Z3_DATA(9)/Z3_DATA(9)_SETF__$INT);
|
|
DQ_DATA_D(11) <= ((NOT UDS AND DQ_SWAP AND LAN_SM_FSM_FFd13 AND D(3).PIN)
|
|
OR (NOT LDS AND DQ_SWAP AND LAN_SM_FSM_FFd13 AND D(3).PIN)
|
|
OR (UDS AND LDS AND A(19).PIN AND NOT DQ_SWAP AND
|
|
LAN_SM_FSM_FFd13)
|
|
OR (UDS AND LDS AND DQ_SWAP AND A(11).PIN AND
|
|
LAN_SM_FSM_FFd13)
|
|
OR (D(11).PIN AND NOT LDS AND NOT DQ_SWAP AND LAN_SM_FSM_FFd13)
|
|
OR (DQ_DATA(11) AND NOT $OpTx$FX_DC$1323)
|
|
OR (A(19).PIN AND NOT DQ_SWAP AND LAN_SM_FSM_FFd3)
|
|
OR (DQ_SWAP AND LAN_SM_FSM_FFd3 AND A(11).PIN)
|
|
OR (D(11).PIN AND NOT UDS AND NOT DQ_SWAP AND LAN_SM_FSM_FFd13));
|
|
|
|
FDCPE_DQ_DATA12: FDCPE port map (DQ_DATA(12),DQ_DATA_D(12),CLK_EXT,'0',NOT Z3_DATA(9)/Z3_DATA(9)_SETF__$INT);
|
|
DQ_DATA_D(12) <= ((D(12).PIN AND NOT LDS AND NOT DQ_SWAP AND LAN_SM_FSM_FFd13)
|
|
OR (NOT UDS AND DQ_SWAP AND LAN_SM_FSM_FFd13 AND D(4).PIN)
|
|
OR (NOT LDS AND DQ_SWAP AND LAN_SM_FSM_FFd13 AND D(4).PIN)
|
|
OR (UDS AND LDS AND DQ_SWAP AND A(12).PIN AND
|
|
LAN_SM_FSM_FFd13)
|
|
OR (UDS AND LDS AND NOT DQ_SWAP AND LAN_SM_FSM_FFd13 AND
|
|
A(20).PIN)
|
|
OR (DQ_DATA(12) AND NOT $OpTx$FX_DC$1323)
|
|
OR (DQ_SWAP AND LAN_SM_FSM_FFd3 AND A(12).PIN)
|
|
OR (NOT DQ_SWAP AND LAN_SM_FSM_FFd3 AND A(20).PIN)
|
|
OR (D(12).PIN AND NOT UDS AND NOT DQ_SWAP AND LAN_SM_FSM_FFd13));
|
|
|
|
FDCPE_DQ_DATA13: FDCPE port map (DQ_DATA(13),DQ_DATA_D(13),CLK_EXT,'0',NOT Z3_DATA(9)/Z3_DATA(9)_SETF__$INT);
|
|
DQ_DATA_D(13) <= ((D(13).PIN AND NOT LDS AND NOT DQ_SWAP AND LAN_SM_FSM_FFd13)
|
|
OR (NOT UDS AND DQ_SWAP AND LAN_SM_FSM_FFd13 AND D(5).PIN)
|
|
OR (NOT LDS AND DQ_SWAP AND LAN_SM_FSM_FFd13 AND D(5).PIN)
|
|
OR (UDS AND LDS AND A(21).PIN AND NOT DQ_SWAP AND
|
|
LAN_SM_FSM_FFd13)
|
|
OR (UDS AND LDS AND DQ_SWAP AND A(13).PIN AND
|
|
LAN_SM_FSM_FFd13)
|
|
OR (DQ_DATA(13) AND NOT $OpTx$FX_DC$1323)
|
|
OR (A(21).PIN AND NOT DQ_SWAP AND LAN_SM_FSM_FFd3)
|
|
OR (DQ_SWAP AND LAN_SM_FSM_FFd3 AND A(13).PIN)
|
|
OR (D(13).PIN AND NOT UDS AND NOT DQ_SWAP AND LAN_SM_FSM_FFd13));
|
|
|
|
FDCPE_DQ_DATA14: FDCPE port map (DQ_DATA(14),DQ_DATA_D(14),CLK_EXT,'0',NOT Z3_DATA(9)/Z3_DATA(9)_SETF__$INT);
|
|
DQ_DATA_D(14) <= ((D(14).PIN AND NOT LDS AND NOT DQ_SWAP AND LAN_SM_FSM_FFd13)
|
|
OR (NOT UDS AND DQ_SWAP AND LAN_SM_FSM_FFd13 AND D(6).PIN)
|
|
OR (NOT LDS AND DQ_SWAP AND LAN_SM_FSM_FFd13 AND D(6).PIN)
|
|
OR (UDS AND LDS AND A(22).PIN AND NOT DQ_SWAP AND
|
|
LAN_SM_FSM_FFd13)
|
|
OR (UDS AND LDS AND DQ_SWAP AND A(14).PIN AND
|
|
LAN_SM_FSM_FFd13)
|
|
OR (DQ_DATA(14) AND NOT $OpTx$FX_DC$1323)
|
|
OR (A(22).PIN AND NOT DQ_SWAP AND LAN_SM_FSM_FFd3)
|
|
OR (DQ_SWAP AND LAN_SM_FSM_FFd3 AND A(14).PIN)
|
|
OR (D(14).PIN AND NOT UDS AND NOT DQ_SWAP AND LAN_SM_FSM_FFd13));
|
|
|
|
FDCPE_DQ_DATA15: FDCPE port map (DQ_DATA(15),DQ_DATA_D(15),CLK_EXT,'0',NOT Z3_DATA(9)/Z3_DATA(9)_SETF__$INT);
|
|
DQ_DATA_D(15) <= ((DQ_DATA(3).EXP)
|
|
OR (D(15).PIN AND NOT UDS AND NOT DQ_SWAP AND LAN_SM_FSM_FFd13)
|
|
OR (D(15).PIN AND NOT LDS AND NOT DQ_SWAP AND LAN_SM_FSM_FFd13)
|
|
OR (NOT UDS AND DQ_SWAP AND LAN_SM_FSM_FFd13 AND D(7).PIN)
|
|
OR (NOT LDS AND DQ_SWAP AND LAN_SM_FSM_FFd13 AND D(7).PIN)
|
|
OR (UDS AND LDS AND DQ_SWAP AND A(15).PIN AND
|
|
LAN_SM_FSM_FFd13)
|
|
OR (DQ_DATA(15) AND NOT $OpTx$FX_DC$1323)
|
|
OR (A(23).PIN AND NOT DQ_SWAP AND LAN_SM_FSM_FFd3)
|
|
OR (DQ_SWAP AND LAN_SM_FSM_FFd3 AND A(15).PIN));
|
|
|
|
FDCPE_DQ_SWAP: FDCPE port map (DQ_SWAP,DQ_SWAP_D,NOT FCS,'0',NOT RESET);
|
|
DQ_SWAP_D <= ((Z3 AND D(8).PIN AND D(9).PIN AND NOT D(10).PIN AND
|
|
NOT LAN_BASEADR(10) AND LAN_BASEADR(8) AND LAN_BASEADR(9) AND NOT SHUT_UP_Z2(0) AND
|
|
A(13).PIN AND A(14).PIN AND NOT $OpTx$FX_DC$461 AND NOT $OpTx$FX_DC$462 AND
|
|
NOT $OpTx$FX_DC$463 AND NOT $OpTx$INV$437 AND NOT $OpTx$INV$436)
|
|
OR (Z3 AND NOT D(8).PIN AND NOT D(9).PIN AND D(10).PIN AND
|
|
LAN_BASEADR(10) AND NOT LAN_BASEADR(8) AND NOT LAN_BASEADR(9) AND NOT SHUT_UP_Z2(0) AND
|
|
A(13).PIN AND A(14).PIN AND NOT $OpTx$FX_DC$461 AND NOT $OpTx$FX_DC$462 AND
|
|
NOT $OpTx$FX_DC$463 AND NOT $OpTx$INV$437 AND NOT $OpTx$INV$436)
|
|
OR (Z3 AND D(8).PIN AND NOT D(9).PIN AND NOT D(10).PIN AND
|
|
NOT LAN_BASEADR(10) AND LAN_BASEADR(8) AND NOT LAN_BASEADR(9) AND NOT SHUT_UP_Z2(0) AND
|
|
A(13).PIN AND A(14).PIN AND NOT $OpTx$FX_DC$461 AND NOT $OpTx$FX_DC$462 AND
|
|
NOT $OpTx$FX_DC$463 AND NOT $OpTx$INV$437 AND NOT $OpTx$INV$436)
|
|
OR (Z3 AND NOT D(8).PIN AND D(9).PIN AND NOT D(10).PIN AND
|
|
NOT LAN_BASEADR(10) AND NOT LAN_BASEADR(8) AND LAN_BASEADR(9) AND NOT SHUT_UP_Z2(0) AND
|
|
A(13).PIN AND A(14).PIN AND NOT $OpTx$FX_DC$461 AND NOT $OpTx$FX_DC$462 AND
|
|
NOT $OpTx$FX_DC$463 AND NOT $OpTx$INV$437 AND NOT $OpTx$INV$436)
|
|
OR (Z3 AND NOT D(8).PIN AND NOT D(9).PIN AND NOT D(10).PIN AND
|
|
NOT LAN_BASEADR(10) AND NOT LAN_BASEADR(8) AND NOT LAN_BASEADR(9) AND NOT SHUT_UP_Z2(0) AND
|
|
A(13).PIN AND A(14).PIN AND NOT $OpTx$FX_DC$461 AND NOT $OpTx$FX_DC$462 AND
|
|
NOT $OpTx$FX_DC$463 AND NOT $OpTx$INV$437 AND NOT $OpTx$INV$436)
|
|
OR (Z3 AND D(8).PIN AND D(9).PIN AND D(10).PIN AND
|
|
LAN_BASEADR(10) AND LAN_BASEADR(8) AND LAN_BASEADR(9) AND NOT SHUT_UP_Z2(0) AND
|
|
A(13).PIN AND A(14).PIN AND NOT $OpTx$FX_DC$461 AND NOT $OpTx$FX_DC$462 AND
|
|
NOT $OpTx$FX_DC$463 AND NOT $OpTx$INV$437 AND NOT $OpTx$INV$436)
|
|
OR (Z3 AND D(8).PIN AND NOT D(9).PIN AND D(10).PIN AND
|
|
LAN_BASEADR(10) AND LAN_BASEADR(8) AND NOT LAN_BASEADR(9) AND NOT SHUT_UP_Z2(0) AND
|
|
A(13).PIN AND A(14).PIN AND NOT $OpTx$FX_DC$461 AND NOT $OpTx$FX_DC$462 AND
|
|
NOT $OpTx$FX_DC$463 AND NOT $OpTx$INV$437 AND NOT $OpTx$INV$436)
|
|
OR (Z3 AND NOT D(8).PIN AND D(9).PIN AND D(10).PIN AND
|
|
LAN_BASEADR(10) AND NOT LAN_BASEADR(8) AND LAN_BASEADR(9) AND NOT SHUT_UP_Z2(0) AND
|
|
A(13).PIN AND A(14).PIN AND NOT $OpTx$FX_DC$461 AND NOT $OpTx$FX_DC$462 AND
|
|
NOT $OpTx$FX_DC$463 AND NOT $OpTx$INV$437 AND NOT $OpTx$INV$436));
|
|
|
|
|
|
DTACK_I <= '0';
|
|
DTACK <= DTACK_I when DTACK_OE = '1' else 'Z';
|
|
DTACK_OE <= (NOT FCS AND LAN_READY);
|
|
|
|
|
|
D_9_IOBUFE/D_9_IOBUFE_TRST <= ((NOT FCS AND RW AND LAN_ACCESS)
|
|
OR (NOT AS AND RW AND AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT AS AND RW AND NOT CP_CS));
|
|
|
|
FDCPE_D_Z2_OUT0: FDCPE port map (D_Z2_OUT(0),D_Z2_OUT_D(0),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET);
|
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D_Z2_OUT_D(0) <= ((AS)
|
|
OR (A(6))
|
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OR (NOT AUTOCONFIG_Z2_ACCESS)
|
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OR (A(5) AND A(4))
|
|
OR (A(5) AND NOT A(2))
|
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OR (UDS AND LDS)
|
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OR (A(4) AND NOT A(2) AND NOT A(3))
|
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OR (A(4) AND A(1) AND NOT A(3))
|
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OR (NOT A(4) AND NOT A(2) AND A(1))
|
|
OR (A(2) AND NOT A(1) AND A(3))
|
|
OR (NOT A(5) AND NOT A(4) AND A(1) AND AUTO_CONFIG_Z2_DONE(0))
|
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OR (NOT A(5) AND NOT A(4) AND A(1) AND A(3))
|
|
OR (NOT A(5) AND AUTO_CONFIG_Z2_DONE(0) AND
|
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AUTO_CONFIG_Z2_DONE(1) AND NOT A(3)));
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FDCPE_D_Z2_OUT1: FDCPE port map (D_Z2_OUT(1),D_Z2_OUT_D(1),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET);
|
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D_Z2_OUT_D(1) <= ((AS)
|
|
OR (A(6))
|
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OR (NOT AUTOCONFIG_Z2_ACCESS)
|
|
OR (A(5) AND NOT $OpTx$$OpTx$FX_DC$476_INV$1624)
|
|
OR (UDS AND LDS)
|
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OR (NOT A(4) AND A(2) AND A(3))
|
|
OR (NOT A(4) AND NOT A(1) AND A(3))
|
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OR (A(4) AND A(2) AND NOT AUTO_CONFIG_Z2_DONE(0) AND NOT A(3))
|
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OR (SHUT_UP_Z2(0).EXP)
|
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OR (NOT A(5) AND AUTO_CONFIG_Z2_DONE(0) AND
|
|
AUTO_CONFIG_Z2_DONE(1) AND $OpTx$$OpTx$FX_DC$476_INV$1624)
|
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OR (A(4) AND A(2) AND NOT AUTO_CONFIG_Z2_DONE(1) AND NOT A(3))
|
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OR (A(4) AND NOT A(2) AND A(1) AND A(3))
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OR (A(4) AND NOT A(2) AND NOT A(1) AND NOT A(3))
|
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OR (A(4) AND A(1) AND AUTO_CONFIG_Z2_DONE(0) AND
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AUTO_CONFIG_Z2_DONE(1) AND NOT A(3)));
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FDCPE_D_Z2_OUT2: FDCPE port map (D_Z2_OUT(2),D_Z2_OUT_D(2),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET);
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D_Z2_OUT_D(2) <= ((AS)
|
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OR (A(6))
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OR (NOT AUTOCONFIG_Z2_ACCESS)
|
|
OR (Z3_DATA(7).EXP)
|
|
OR (A(5) AND A(4))
|
|
OR (A(5) AND NOT A(2))
|
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OR (A(4) AND NOT A(2))
|
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OR (NOT A(4) AND A(3))
|
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OR (A(1) AND A(3))
|
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OR (A(5) AND NOT A(1))
|
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OR (UDS AND LDS)
|
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OR (A(4) AND NOT A(1) AND NOT A(3))
|
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OR (NOT A(2) AND NOT A(1) AND AUTO_CONFIG_Z2_DONE(0))
|
|
OR (NOT A(4) AND NOT A(1) AND AUTO_CONFIG_Z2_DONE(0) AND
|
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AUTO_CONFIG_Z2_DONE(1)));
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FDCPE_D_Z2_OUT3: FDCPE port map (D_Z2_OUT(3),D_Z2_OUT_D(3),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET);
|
|
D_Z2_OUT_D(3) <= ((EXP60_.EXP)
|
|
OR (NOT A(5) AND NOT A(2) AND A(1) AND NOT AS AND NOT UDS AND NOT A(6) AND NOT A(3) AND
|
|
AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT A(5) AND NOT A(2) AND A(1) AND NOT AS AND NOT LDS AND NOT A(6) AND NOT A(3) AND
|
|
AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT A(5) AND A(1) AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(0) AND
|
|
NOT UDS AND NOT A(6) AND NOT A(3) AND AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT A(5) AND A(1) AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(1) AND
|
|
NOT UDS AND NOT A(6) AND NOT A(3) AND AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT A(5) AND A(1) AND NOT AS AND NOT AUTO_CONFIG_Z2_DONE(1) AND
|
|
NOT LDS AND NOT A(6) AND NOT A(3) AND AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT A(5) AND A(4) AND A(2) AND A(1) AND NOT AS AND NOT UDS AND NOT A(6) AND
|
|
AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT A(5) AND A(4) AND A(2) AND A(1) AND NOT AS AND NOT LDS AND NOT A(6) AND
|
|
AUTOCONFIG_Z2_ACCESS));
|
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IDE_A(0) <= A(9).PIN;
|
|
|
|
|
|
IDE_A(1) <= A(10).PIN;
|
|
|
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|
|
IDE_A(2) <= A(11).PIN;
|
|
|
|
FDCPE_IDE_ACCESS: FDCPE port map (IDE_ACCESS,IDE_ACCESS_D,NOT AS,NOT RESET,'0');
|
|
IDE_ACCESS_D <= ((IDE_BASEADR(6) AND A(22).PIN AND NOT $OpTx$INV$438)
|
|
OR (NOT IDE_BASEADR(6) AND NOT A(22).PIN AND NOT $OpTx$INV$438));
|
|
|
|
FTCPE_IDE_BASEADR0: FTCPE port map (IDE_BASEADR(0),IDE_BASEADR_T(0),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET);
|
|
IDE_BASEADR_T(0) <= ((NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
|
|
AUTO_CONFIG_Z2_DONE(0) AND AUTO_CONFIG_Z2_DONE(1) AND NOT AUTO_CONFIG_Z2_DONE(2) AND
|
|
D(8).PIN AND NOT IDE_BASEADR(0) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND
|
|
AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
|
|
AUTO_CONFIG_Z2_DONE(0) AND AUTO_CONFIG_Z2_DONE(1) AND NOT AUTO_CONFIG_Z2_DONE(2) AND
|
|
D(8).PIN AND NOT IDE_BASEADR(0) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND
|
|
AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
|
|
AUTO_CONFIG_Z2_DONE(0) AND AUTO_CONFIG_Z2_DONE(1) AND NOT AUTO_CONFIG_Z2_DONE(2) AND
|
|
NOT D(8).PIN AND IDE_BASEADR(0) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND
|
|
AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
|
|
AUTO_CONFIG_Z2_DONE(0) AND AUTO_CONFIG_Z2_DONE(1) AND NOT AUTO_CONFIG_Z2_DONE(2) AND
|
|
NOT D(8).PIN AND IDE_BASEADR(0) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND
|
|
AUTOCONFIG_Z2_ACCESS));
|
|
|
|
FTCPE_IDE_BASEADR1: FTCPE port map (IDE_BASEADR(1),IDE_BASEADR_T(1),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET);
|
|
IDE_BASEADR_T(1) <= ((NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
|
|
AUTO_CONFIG_Z2_DONE(0) AND AUTO_CONFIG_Z2_DONE(1) AND NOT AUTO_CONFIG_Z2_DONE(2) AND
|
|
D(9).PIN AND NOT IDE_BASEADR(1) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND
|
|
AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
|
|
AUTO_CONFIG_Z2_DONE(0) AND AUTO_CONFIG_Z2_DONE(1) AND NOT AUTO_CONFIG_Z2_DONE(2) AND
|
|
D(9).PIN AND NOT IDE_BASEADR(1) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND
|
|
AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
|
|
AUTO_CONFIG_Z2_DONE(0) AND AUTO_CONFIG_Z2_DONE(1) AND NOT AUTO_CONFIG_Z2_DONE(2) AND
|
|
NOT D(9).PIN AND IDE_BASEADR(1) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND
|
|
AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
|
|
AUTO_CONFIG_Z2_DONE(0) AND AUTO_CONFIG_Z2_DONE(1) AND NOT AUTO_CONFIG_Z2_DONE(2) AND
|
|
NOT D(9).PIN AND IDE_BASEADR(1) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND
|
|
AUTOCONFIG_Z2_ACCESS));
|
|
|
|
FTCPE_IDE_BASEADR2: FTCPE port map (IDE_BASEADR(2),IDE_BASEADR_T(2),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET);
|
|
IDE_BASEADR_T(2) <= ((NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
|
|
AUTO_CONFIG_Z2_DONE(0) AND AUTO_CONFIG_Z2_DONE(1) AND NOT AUTO_CONFIG_Z2_DONE(2) AND
|
|
D(10).PIN AND NOT IDE_BASEADR(2) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND
|
|
AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
|
|
AUTO_CONFIG_Z2_DONE(0) AND AUTO_CONFIG_Z2_DONE(1) AND NOT AUTO_CONFIG_Z2_DONE(2) AND
|
|
D(10).PIN AND NOT IDE_BASEADR(2) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND
|
|
AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
|
|
AUTO_CONFIG_Z2_DONE(0) AND AUTO_CONFIG_Z2_DONE(1) AND NOT AUTO_CONFIG_Z2_DONE(2) AND
|
|
NOT D(10).PIN AND IDE_BASEADR(2) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND
|
|
AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
|
|
AUTO_CONFIG_Z2_DONE(0) AND AUTO_CONFIG_Z2_DONE(1) AND NOT AUTO_CONFIG_Z2_DONE(2) AND
|
|
NOT D(10).PIN AND IDE_BASEADR(2) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND
|
|
AUTOCONFIG_Z2_ACCESS));
|
|
|
|
FTCPE_IDE_BASEADR3: FTCPE port map (IDE_BASEADR(3),IDE_BASEADR_T(3),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET);
|
|
IDE_BASEADR_T(3) <= ((NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
|
|
AUTO_CONFIG_Z2_DONE(0) AND AUTO_CONFIG_Z2_DONE(1) AND NOT AUTO_CONFIG_Z2_DONE(2) AND
|
|
D(11).PIN AND NOT IDE_BASEADR(3) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND
|
|
AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
|
|
AUTO_CONFIG_Z2_DONE(0) AND AUTO_CONFIG_Z2_DONE(1) AND NOT AUTO_CONFIG_Z2_DONE(2) AND
|
|
D(11).PIN AND NOT IDE_BASEADR(3) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND
|
|
AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
|
|
AUTO_CONFIG_Z2_DONE(0) AND AUTO_CONFIG_Z2_DONE(1) AND NOT AUTO_CONFIG_Z2_DONE(2) AND
|
|
NOT D(11).PIN AND IDE_BASEADR(3) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND
|
|
AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
|
|
AUTO_CONFIG_Z2_DONE(0) AND AUTO_CONFIG_Z2_DONE(1) AND NOT AUTO_CONFIG_Z2_DONE(2) AND
|
|
NOT D(11).PIN AND IDE_BASEADR(3) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND
|
|
AUTOCONFIG_Z2_ACCESS));
|
|
|
|
FTCPE_IDE_BASEADR4: FTCPE port map (IDE_BASEADR(4),IDE_BASEADR_T(4),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET);
|
|
IDE_BASEADR_T(4) <= ((NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
|
|
AUTO_CONFIG_Z2_DONE(0) AND AUTO_CONFIG_Z2_DONE(1) AND NOT AUTO_CONFIG_Z2_DONE(2) AND
|
|
D(12).PIN AND NOT IDE_BASEADR(4) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND
|
|
AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
|
|
AUTO_CONFIG_Z2_DONE(0) AND AUTO_CONFIG_Z2_DONE(1) AND NOT AUTO_CONFIG_Z2_DONE(2) AND
|
|
D(12).PIN AND NOT IDE_BASEADR(4) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND
|
|
AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
|
|
AUTO_CONFIG_Z2_DONE(0) AND AUTO_CONFIG_Z2_DONE(1) AND NOT AUTO_CONFIG_Z2_DONE(2) AND
|
|
NOT D(12).PIN AND IDE_BASEADR(4) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND
|
|
AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
|
|
AUTO_CONFIG_Z2_DONE(0) AND AUTO_CONFIG_Z2_DONE(1) AND NOT AUTO_CONFIG_Z2_DONE(2) AND
|
|
NOT D(12).PIN AND IDE_BASEADR(4) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND
|
|
AUTOCONFIG_Z2_ACCESS));
|
|
|
|
FTCPE_IDE_BASEADR5: FTCPE port map (IDE_BASEADR(5),IDE_BASEADR_T(5),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET);
|
|
IDE_BASEADR_T(5) <= ((NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
|
|
AUTO_CONFIG_Z2_DONE(0) AND AUTO_CONFIG_Z2_DONE(1) AND NOT AUTO_CONFIG_Z2_DONE(2) AND
|
|
D(13).PIN AND NOT IDE_BASEADR(5) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND
|
|
AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
|
|
AUTO_CONFIG_Z2_DONE(0) AND AUTO_CONFIG_Z2_DONE(1) AND NOT AUTO_CONFIG_Z2_DONE(2) AND
|
|
D(13).PIN AND NOT IDE_BASEADR(5) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND
|
|
AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
|
|
AUTO_CONFIG_Z2_DONE(0) AND AUTO_CONFIG_Z2_DONE(1) AND NOT AUTO_CONFIG_Z2_DONE(2) AND
|
|
NOT D(13).PIN AND IDE_BASEADR(5) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND
|
|
AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
|
|
AUTO_CONFIG_Z2_DONE(0) AND AUTO_CONFIG_Z2_DONE(1) AND NOT AUTO_CONFIG_Z2_DONE(2) AND
|
|
NOT D(13).PIN AND IDE_BASEADR(5) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND
|
|
AUTOCONFIG_Z2_ACCESS));
|
|
|
|
FTCPE_IDE_BASEADR6: FTCPE port map (IDE_BASEADR(6),IDE_BASEADR_T(6),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET);
|
|
IDE_BASEADR_T(6) <= ((NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
|
|
AUTO_CONFIG_Z2_DONE(0) AND AUTO_CONFIG_Z2_DONE(1) AND NOT AUTO_CONFIG_Z2_DONE(2) AND
|
|
D(14).PIN AND NOT IDE_BASEADR(6) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND
|
|
AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
|
|
AUTO_CONFIG_Z2_DONE(0) AND AUTO_CONFIG_Z2_DONE(1) AND NOT AUTO_CONFIG_Z2_DONE(2) AND
|
|
D(14).PIN AND NOT IDE_BASEADR(6) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND
|
|
AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
|
|
AUTO_CONFIG_Z2_DONE(0) AND AUTO_CONFIG_Z2_DONE(1) AND NOT AUTO_CONFIG_Z2_DONE(2) AND
|
|
NOT D(14).PIN AND IDE_BASEADR(6) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND
|
|
AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
|
|
AUTO_CONFIG_Z2_DONE(0) AND AUTO_CONFIG_Z2_DONE(1) AND NOT AUTO_CONFIG_Z2_DONE(2) AND
|
|
NOT D(14).PIN AND IDE_BASEADR(6) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND
|
|
AUTOCONFIG_Z2_ACCESS));
|
|
|
|
FTCPE_IDE_BASEADR7: FTCPE port map (IDE_BASEADR(7),IDE_BASEADR_T(7),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET);
|
|
IDE_BASEADR_T(7) <= ((NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
|
|
AUTO_CONFIG_Z2_DONE(0) AND AUTO_CONFIG_Z2_DONE(1) AND NOT AUTO_CONFIG_Z2_DONE(2) AND
|
|
D(15).PIN AND NOT IDE_BASEADR(7) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND
|
|
AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
|
|
AUTO_CONFIG_Z2_DONE(0) AND AUTO_CONFIG_Z2_DONE(1) AND NOT AUTO_CONFIG_Z2_DONE(2) AND
|
|
D(15).PIN AND NOT IDE_BASEADR(7) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND
|
|
AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
|
|
AUTO_CONFIG_Z2_DONE(0) AND AUTO_CONFIG_Z2_DONE(1) AND NOT AUTO_CONFIG_Z2_DONE(2) AND
|
|
NOT D(15).PIN AND IDE_BASEADR(7) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND
|
|
AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
|
|
AUTO_CONFIG_Z2_DONE(0) AND AUTO_CONFIG_Z2_DONE(1) AND NOT AUTO_CONFIG_Z2_DONE(2) AND
|
|
NOT D(15).PIN AND IDE_BASEADR(7) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND
|
|
AUTOCONFIG_Z2_ACCESS));
|
|
|
|
|
|
IDE_CS(0) <= NOT A(12).PIN;
|
|
|
|
|
|
IDE_CS(1) <= NOT A(13).PIN;
|
|
|
|
FDCPE_IDE_ENABLE: FDCPE port map (IDE_ENABLE,'0',SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET,IDE_ENABLE_CE);
|
|
IDE_ENABLE_CE <= (NOT AS AND NOT RW AND IDE_ACCESS);
|
|
|
|
|
|
IDE_R <= NOT ((NOT AS AND NOT IDE_R_S));
|
|
|
|
FDCPE_IDE_R_S: FDCPE port map (IDE_R_S,IDE_R_S_D,SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET);
|
|
IDE_R_S_D <= (NOT AS AND RW AND IDE_ACCESS AND NOT IDE_ENABLE);
|
|
|
|
|
|
IDE_W <= NOT ((NOT AS AND NOT IDE_W_S));
|
|
|
|
FDCPE_IDE_W_S: FDCPE port map (IDE_W_S,IDE_W_S_D,SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET);
|
|
IDE_W_S_D <= (NOT AS AND NOT RW AND IDE_ACCESS);
|
|
|
|
|
|
INT2_OUT_I <= '0';
|
|
INT2_OUT <= INT2_OUT_I when INT2_OUT_OE = '1' else 'Z';
|
|
INT2_OUT_OE <= (NOT LAN_IRQ_OUT AND LAN_INT_ENABLE);
|
|
|
|
|
|
INT6_OUT_I <= '0';
|
|
INT6_OUT <= INT6_OUT_I when INT6_OUT_OE = '1' else 'Z';
|
|
INT6_OUT_OE <= NOT CP_IRQ;
|
|
|
|
FDCPE_LAN_ACCESS: FDCPE port map (LAN_ACCESS,LAN_ACCESS_D,NOT FCS,NOT RESET,'0');
|
|
LAN_ACCESS_D <= ((NOT Z3)
|
|
OR (SHUT_UP_Z2(0))
|
|
OR ($OpTx$FX_DC$462)
|
|
OR ($OpTx$FX_DC$463)
|
|
OR ($OpTx$INV$437)
|
|
OR ($OpTx$INV$436)
|
|
OR (LAN_SM_FSM_FFd1.EXP)
|
|
OR (D(8).PIN AND NOT LAN_BASEADR(8))
|
|
OR (NOT D(8).PIN AND LAN_BASEADR(8))
|
|
OR (D(9).PIN AND NOT LAN_BASEADR(9))
|
|
OR (NOT D(9).PIN AND LAN_BASEADR(9))
|
|
OR (D(10).PIN AND NOT LAN_BASEADR(10))
|
|
OR (NOT D(10).PIN AND LAN_BASEADR(10)));
|
|
|
|
FDCPE_LAN_A_INIT3: FDCPE port map (LAN_A_INIT(3),'0',CLK_EXT,'0',RESET);
|
|
|
|
FDCPE_LAN_A_INIT6: FDCPE port map (LAN_A_INIT(6),LAN_A_INIT_D(6),CLK_EXT,'0',RESET);
|
|
LAN_A_INIT_D(6) <= (NOT LAN_RST_SM_FSM_FFd6 AND NOT LAN_RST_SM_FSM_FFd5 AND
|
|
NOT LAN_RST_SM_FSM_FFd7 AND NOT LAN_A_INIT(3));
|
|
|
|
FTCPE_LAN_BASEADR0: FTCPE port map (LAN_BASEADR(0),LAN_BASEADR_T(0),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET);
|
|
LAN_BASEADR_T(0) <= ((NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
|
|
NOT AUTO_CONFIG_Z2_DONE(0) AND D(8).PIN AND NOT LAN_BASEADR(0) AND NOT LDS AND A(6) AND A(3) AND
|
|
NOT RW AND AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
|
|
NOT AUTO_CONFIG_Z2_DONE(0) AND D(8).PIN AND NOT LAN_BASEADR(0) AND NOT UDS AND A(6) AND A(3) AND
|
|
NOT RW AND AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
|
|
NOT AUTO_CONFIG_Z2_DONE(0) AND NOT D(8).PIN AND LAN_BASEADR(0) AND NOT UDS AND A(6) AND A(3) AND
|
|
NOT RW AND AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
|
|
NOT AUTO_CONFIG_Z2_DONE(0) AND NOT D(8).PIN AND LAN_BASEADR(0) AND NOT LDS AND A(6) AND A(3) AND
|
|
NOT RW AND AUTOCONFIG_Z2_ACCESS));
|
|
|
|
FTCPE_LAN_BASEADR1: FTCPE port map (LAN_BASEADR(1),LAN_BASEADR_T(1),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET);
|
|
LAN_BASEADR_T(1) <= ((NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
|
|
NOT AUTO_CONFIG_Z2_DONE(0) AND D(9).PIN AND NOT LAN_BASEADR(1) AND NOT LDS AND A(6) AND A(3) AND
|
|
NOT RW AND AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
|
|
NOT AUTO_CONFIG_Z2_DONE(0) AND D(9).PIN AND NOT LAN_BASEADR(1) AND NOT UDS AND A(6) AND A(3) AND
|
|
NOT RW AND AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
|
|
NOT AUTO_CONFIG_Z2_DONE(0) AND NOT D(9).PIN AND LAN_BASEADR(1) AND NOT UDS AND A(6) AND A(3) AND
|
|
NOT RW AND AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
|
|
NOT AUTO_CONFIG_Z2_DONE(0) AND NOT D(9).PIN AND LAN_BASEADR(1) AND NOT LDS AND A(6) AND A(3) AND
|
|
NOT RW AND AUTOCONFIG_Z2_ACCESS));
|
|
|
|
FTCPE_LAN_BASEADR2: FTCPE port map (LAN_BASEADR(2),LAN_BASEADR_T(2),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET);
|
|
LAN_BASEADR_T(2) <= ((NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
|
|
NOT AUTO_CONFIG_Z2_DONE(0) AND D(10).PIN AND NOT LAN_BASEADR(2) AND NOT UDS AND A(6) AND A(3) AND
|
|
NOT RW AND AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
|
|
NOT AUTO_CONFIG_Z2_DONE(0) AND D(10).PIN AND NOT LAN_BASEADR(2) AND NOT LDS AND A(6) AND A(3) AND
|
|
NOT RW AND AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
|
|
NOT AUTO_CONFIG_Z2_DONE(0) AND NOT D(10).PIN AND LAN_BASEADR(2) AND NOT UDS AND A(6) AND A(3) AND
|
|
NOT RW AND AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
|
|
NOT AUTO_CONFIG_Z2_DONE(0) AND NOT D(10).PIN AND LAN_BASEADR(2) AND NOT LDS AND A(6) AND A(3) AND
|
|
NOT RW AND AUTOCONFIG_Z2_ACCESS));
|
|
|
|
FTCPE_LAN_BASEADR3: FTCPE port map (LAN_BASEADR(3),LAN_BASEADR_T(3),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET);
|
|
LAN_BASEADR_T(3) <= ((NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
|
|
NOT AUTO_CONFIG_Z2_DONE(0) AND D(11).PIN AND NOT LAN_BASEADR(3) AND NOT UDS AND A(6) AND A(3) AND
|
|
NOT RW AND AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
|
|
NOT AUTO_CONFIG_Z2_DONE(0) AND D(11).PIN AND NOT LAN_BASEADR(3) AND NOT LDS AND A(6) AND A(3) AND
|
|
NOT RW AND AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
|
|
NOT AUTO_CONFIG_Z2_DONE(0) AND NOT D(11).PIN AND LAN_BASEADR(3) AND NOT UDS AND A(6) AND A(3) AND
|
|
NOT RW AND AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
|
|
NOT AUTO_CONFIG_Z2_DONE(0) AND NOT D(11).PIN AND LAN_BASEADR(3) AND NOT LDS AND A(6) AND A(3) AND
|
|
NOT RW AND AUTOCONFIG_Z2_ACCESS));
|
|
|
|
FTCPE_LAN_BASEADR4: FTCPE port map (LAN_BASEADR(4),LAN_BASEADR_T(4),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET);
|
|
LAN_BASEADR_T(4) <= ((NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
|
|
NOT AUTO_CONFIG_Z2_DONE(0) AND D(12).PIN AND NOT LAN_BASEADR(4) AND NOT UDS AND A(6) AND A(3) AND
|
|
NOT RW AND AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
|
|
NOT AUTO_CONFIG_Z2_DONE(0) AND D(12).PIN AND NOT LAN_BASEADR(4) AND NOT LDS AND A(6) AND A(3) AND
|
|
NOT RW AND AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
|
|
NOT AUTO_CONFIG_Z2_DONE(0) AND NOT D(12).PIN AND LAN_BASEADR(4) AND NOT UDS AND A(6) AND A(3) AND
|
|
NOT RW AND AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
|
|
NOT AUTO_CONFIG_Z2_DONE(0) AND NOT D(12).PIN AND LAN_BASEADR(4) AND NOT LDS AND A(6) AND A(3) AND
|
|
NOT RW AND AUTOCONFIG_Z2_ACCESS));
|
|
|
|
FTCPE_LAN_BASEADR5: FTCPE port map (LAN_BASEADR(5),LAN_BASEADR_T(5),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET);
|
|
LAN_BASEADR_T(5) <= ((NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
|
|
NOT AUTO_CONFIG_Z2_DONE(0) AND D(13).PIN AND NOT LAN_BASEADR(5) AND NOT UDS AND A(6) AND A(3) AND
|
|
NOT RW AND AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
|
|
NOT AUTO_CONFIG_Z2_DONE(0) AND D(13).PIN AND NOT LAN_BASEADR(5) AND NOT LDS AND A(6) AND A(3) AND
|
|
NOT RW AND AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
|
|
NOT AUTO_CONFIG_Z2_DONE(0) AND NOT D(13).PIN AND LAN_BASEADR(5) AND NOT LDS AND A(6) AND A(3) AND
|
|
NOT RW AND AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
|
|
NOT AUTO_CONFIG_Z2_DONE(0) AND NOT D(13).PIN AND LAN_BASEADR(5) AND NOT UDS AND A(6) AND A(3) AND
|
|
NOT RW AND AUTOCONFIG_Z2_ACCESS));
|
|
|
|
FTCPE_LAN_BASEADR6: FTCPE port map (LAN_BASEADR(6),LAN_BASEADR_T(6),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET);
|
|
LAN_BASEADR_T(6) <= ((NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
|
|
NOT AUTO_CONFIG_Z2_DONE(0) AND D(14).PIN AND NOT LAN_BASEADR(6) AND NOT UDS AND A(6) AND A(3) AND
|
|
NOT RW AND AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
|
|
NOT AUTO_CONFIG_Z2_DONE(0) AND D(14).PIN AND NOT LAN_BASEADR(6) AND NOT LDS AND A(6) AND A(3) AND
|
|
NOT RW AND AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
|
|
NOT AUTO_CONFIG_Z2_DONE(0) AND NOT D(14).PIN AND LAN_BASEADR(6) AND NOT UDS AND A(6) AND A(3) AND
|
|
NOT RW AND AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
|
|
NOT AUTO_CONFIG_Z2_DONE(0) AND NOT D(14).PIN AND LAN_BASEADR(6) AND NOT LDS AND A(6) AND A(3) AND
|
|
NOT RW AND AUTOCONFIG_Z2_ACCESS));
|
|
|
|
FTCPE_LAN_BASEADR7: FTCPE port map (LAN_BASEADR(7),LAN_BASEADR_T(7),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET);
|
|
LAN_BASEADR_T(7) <= ((NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
|
|
NOT AUTO_CONFIG_Z2_DONE(0) AND D(15).PIN AND NOT LAN_BASEADR(7) AND NOT LDS AND A(6) AND A(3) AND
|
|
NOT RW AND AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
|
|
NOT AUTO_CONFIG_Z2_DONE(0) AND D(15).PIN AND NOT LAN_BASEADR(7) AND NOT UDS AND A(6) AND A(3) AND
|
|
NOT RW AND AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
|
|
NOT AUTO_CONFIG_Z2_DONE(0) AND NOT D(15).PIN AND LAN_BASEADR(7) AND NOT UDS AND A(6) AND A(3) AND
|
|
NOT RW AND AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
|
|
NOT AUTO_CONFIG_Z2_DONE(0) AND NOT D(15).PIN AND LAN_BASEADR(7) AND NOT LDS AND A(6) AND A(3) AND
|
|
NOT RW AND AUTOCONFIG_Z2_ACCESS));
|
|
|
|
FTCPE_LAN_BASEADR8: FTCPE port map (LAN_BASEADR(8),LAN_BASEADR_T(8),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET);
|
|
LAN_BASEADR_T(8) <= ((NOT A(5) AND NOT A(4) AND A(2) AND NOT A(1) AND NOT AS AND
|
|
NOT AUTO_CONFIG_Z2_DONE(1) AND D(8).PIN AND NOT LAN_BASEADR(8) AND NOT LDS AND A(6) AND NOT A(3) AND
|
|
NOT RW AND AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT A(5) AND NOT A(4) AND A(2) AND NOT A(1) AND NOT AS AND
|
|
NOT AUTO_CONFIG_Z2_DONE(1) AND D(8).PIN AND NOT LAN_BASEADR(8) AND NOT UDS AND A(6) AND NOT A(3) AND
|
|
NOT RW AND AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT A(5) AND NOT A(4) AND A(2) AND NOT A(1) AND NOT AS AND
|
|
NOT AUTO_CONFIG_Z2_DONE(1) AND NOT D(8).PIN AND LAN_BASEADR(8) AND NOT UDS AND A(6) AND NOT A(3) AND
|
|
NOT RW AND AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT A(5) AND NOT A(4) AND A(2) AND NOT A(1) AND NOT AS AND
|
|
NOT AUTO_CONFIG_Z2_DONE(1) AND NOT D(8).PIN AND LAN_BASEADR(8) AND NOT LDS AND A(6) AND NOT A(3) AND
|
|
NOT RW AND AUTOCONFIG_Z2_ACCESS));
|
|
|
|
FTCPE_LAN_BASEADR9: FTCPE port map (LAN_BASEADR(9),LAN_BASEADR_T(9),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET);
|
|
LAN_BASEADR_T(9) <= ((NOT A(5) AND NOT A(4) AND A(2) AND NOT A(1) AND NOT AS AND
|
|
NOT AUTO_CONFIG_Z2_DONE(1) AND D(9).PIN AND NOT LAN_BASEADR(9) AND NOT LDS AND A(6) AND NOT A(3) AND
|
|
NOT RW AND AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT A(5) AND NOT A(4) AND A(2) AND NOT A(1) AND NOT AS AND
|
|
NOT AUTO_CONFIG_Z2_DONE(1) AND D(9).PIN AND NOT LAN_BASEADR(9) AND NOT UDS AND A(6) AND NOT A(3) AND
|
|
NOT RW AND AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT A(5) AND NOT A(4) AND A(2) AND NOT A(1) AND NOT AS AND
|
|
NOT AUTO_CONFIG_Z2_DONE(1) AND NOT D(9).PIN AND LAN_BASEADR(9) AND NOT UDS AND A(6) AND NOT A(3) AND
|
|
NOT RW AND AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT A(5) AND NOT A(4) AND A(2) AND NOT A(1) AND NOT AS AND
|
|
NOT AUTO_CONFIG_Z2_DONE(1) AND NOT D(9).PIN AND LAN_BASEADR(9) AND NOT LDS AND A(6) AND NOT A(3) AND
|
|
NOT RW AND AUTOCONFIG_Z2_ACCESS));
|
|
|
|
FTCPE_LAN_BASEADR10: FTCPE port map (LAN_BASEADR(10),LAN_BASEADR_T(10),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET);
|
|
LAN_BASEADR_T(10) <= ((NOT A(5) AND NOT A(4) AND A(2) AND NOT A(1) AND NOT AS AND
|
|
NOT AUTO_CONFIG_Z2_DONE(1) AND D(10).PIN AND NOT LAN_BASEADR(10) AND NOT LDS AND A(6) AND
|
|
NOT A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT A(5) AND NOT A(4) AND A(2) AND NOT A(1) AND NOT AS AND
|
|
NOT AUTO_CONFIG_Z2_DONE(1) AND D(10).PIN AND NOT LAN_BASEADR(10) AND NOT UDS AND A(6) AND
|
|
NOT A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT A(5) AND NOT A(4) AND A(2) AND NOT A(1) AND NOT AS AND
|
|
NOT AUTO_CONFIG_Z2_DONE(1) AND NOT D(10).PIN AND LAN_BASEADR(10) AND NOT UDS AND A(6) AND
|
|
NOT A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT A(5) AND NOT A(4) AND A(2) AND NOT A(1) AND NOT AS AND
|
|
NOT AUTO_CONFIG_Z2_DONE(1) AND NOT D(10).PIN AND LAN_BASEADR(10) AND NOT LDS AND A(6) AND
|
|
NOT A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS));
|
|
|
|
FTCPE_LAN_BASEADR11: FTCPE port map (LAN_BASEADR(11),LAN_BASEADR_T(11),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET);
|
|
LAN_BASEADR_T(11) <= ((NOT A(5) AND NOT A(4) AND A(2) AND NOT A(1) AND NOT AS AND
|
|
NOT AUTO_CONFIG_Z2_DONE(1) AND D(11).PIN AND NOT LAN_BASEADR(11) AND NOT LDS AND A(6) AND
|
|
NOT A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT A(5) AND NOT A(4) AND A(2) AND NOT A(1) AND NOT AS AND
|
|
NOT AUTO_CONFIG_Z2_DONE(1) AND D(11).PIN AND NOT LAN_BASEADR(11) AND NOT UDS AND A(6) AND
|
|
NOT A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT A(5) AND NOT A(4) AND A(2) AND NOT A(1) AND NOT AS AND
|
|
NOT AUTO_CONFIG_Z2_DONE(1) AND NOT D(11).PIN AND LAN_BASEADR(11) AND NOT UDS AND A(6) AND
|
|
NOT A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT A(5) AND NOT A(4) AND A(2) AND NOT A(1) AND NOT AS AND
|
|
NOT AUTO_CONFIG_Z2_DONE(1) AND NOT D(11).PIN AND LAN_BASEADR(11) AND NOT LDS AND A(6) AND
|
|
NOT A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS));
|
|
|
|
FTCPE_LAN_BASEADR12: FTCPE port map (LAN_BASEADR(12),LAN_BASEADR_T(12),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET);
|
|
LAN_BASEADR_T(12) <= ((NOT A(5) AND NOT A(4) AND A(2) AND NOT A(1) AND NOT AS AND
|
|
NOT AUTO_CONFIG_Z2_DONE(1) AND D(12).PIN AND NOT LAN_BASEADR(12) AND NOT LDS AND A(6) AND
|
|
NOT A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT A(5) AND NOT A(4) AND A(2) AND NOT A(1) AND NOT AS AND
|
|
NOT AUTO_CONFIG_Z2_DONE(1) AND D(12).PIN AND NOT LAN_BASEADR(12) AND NOT UDS AND A(6) AND
|
|
NOT A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT A(5) AND NOT A(4) AND A(2) AND NOT A(1) AND NOT AS AND
|
|
NOT AUTO_CONFIG_Z2_DONE(1) AND NOT D(12).PIN AND LAN_BASEADR(12) AND NOT UDS AND A(6) AND
|
|
NOT A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT A(5) AND NOT A(4) AND A(2) AND NOT A(1) AND NOT AS AND
|
|
NOT AUTO_CONFIG_Z2_DONE(1) AND NOT D(12).PIN AND LAN_BASEADR(12) AND NOT LDS AND A(6) AND
|
|
NOT A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS));
|
|
|
|
FTCPE_LAN_BASEADR13: FTCPE port map (LAN_BASEADR(13),LAN_BASEADR_T(13),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET);
|
|
LAN_BASEADR_T(13) <= ((NOT A(5) AND NOT A(4) AND A(2) AND NOT A(1) AND NOT AS AND
|
|
NOT AUTO_CONFIG_Z2_DONE(1) AND D(13).PIN AND NOT LAN_BASEADR(13) AND NOT LDS AND A(6) AND
|
|
NOT A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT A(5) AND NOT A(4) AND A(2) AND NOT A(1) AND NOT AS AND
|
|
NOT AUTO_CONFIG_Z2_DONE(1) AND D(13).PIN AND NOT LAN_BASEADR(13) AND NOT UDS AND A(6) AND
|
|
NOT A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT A(5) AND NOT A(4) AND A(2) AND NOT A(1) AND NOT AS AND
|
|
NOT AUTO_CONFIG_Z2_DONE(1) AND NOT D(13).PIN AND LAN_BASEADR(13) AND NOT UDS AND A(6) AND
|
|
NOT A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT A(5) AND NOT A(4) AND A(2) AND NOT A(1) AND NOT AS AND
|
|
NOT AUTO_CONFIG_Z2_DONE(1) AND NOT D(13).PIN AND LAN_BASEADR(13) AND NOT LDS AND A(6) AND
|
|
NOT A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS));
|
|
|
|
FTCPE_LAN_BASEADR14: FTCPE port map (LAN_BASEADR(14),LAN_BASEADR_T(14),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET);
|
|
LAN_BASEADR_T(14) <= ((NOT A(5) AND NOT A(4) AND A(2) AND NOT A(1) AND NOT AS AND
|
|
NOT AUTO_CONFIG_Z2_DONE(1) AND D(14).PIN AND NOT LAN_BASEADR(14) AND NOT UDS AND A(6) AND
|
|
NOT A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT A(5) AND NOT A(4) AND A(2) AND NOT A(1) AND NOT AS AND
|
|
NOT AUTO_CONFIG_Z2_DONE(1) AND D(14).PIN AND NOT LAN_BASEADR(14) AND NOT LDS AND A(6) AND
|
|
NOT A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT A(5) AND NOT A(4) AND A(2) AND NOT A(1) AND NOT AS AND
|
|
NOT AUTO_CONFIG_Z2_DONE(1) AND NOT D(14).PIN AND LAN_BASEADR(14) AND NOT UDS AND A(6) AND
|
|
NOT A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT A(5) AND NOT A(4) AND A(2) AND NOT A(1) AND NOT AS AND
|
|
NOT AUTO_CONFIG_Z2_DONE(1) AND NOT D(14).PIN AND LAN_BASEADR(14) AND NOT LDS AND A(6) AND
|
|
NOT A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS));
|
|
|
|
FTCPE_LAN_BASEADR15: FTCPE port map (LAN_BASEADR(15),LAN_BASEADR_T(15),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET);
|
|
LAN_BASEADR_T(15) <= ((NOT A(5) AND NOT A(4) AND A(2) AND NOT A(1) AND NOT AS AND
|
|
NOT AUTO_CONFIG_Z2_DONE(1) AND D(15).PIN AND NOT LAN_BASEADR(15) AND NOT UDS AND A(6) AND
|
|
NOT A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT A(5) AND NOT A(4) AND A(2) AND NOT A(1) AND NOT AS AND
|
|
NOT AUTO_CONFIG_Z2_DONE(1) AND D(15).PIN AND NOT LAN_BASEADR(15) AND NOT LDS AND A(6) AND
|
|
NOT A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT A(5) AND NOT A(4) AND A(2) AND NOT A(1) AND NOT AS AND
|
|
NOT AUTO_CONFIG_Z2_DONE(1) AND NOT D(15).PIN AND LAN_BASEADR(15) AND NOT LDS AND A(6) AND
|
|
NOT A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS)
|
|
OR (NOT A(5) AND NOT A(4) AND A(2) AND NOT A(1) AND NOT AS AND
|
|
NOT AUTO_CONFIG_Z2_DONE(1) AND NOT D(15).PIN AND LAN_BASEADR(15) AND NOT UDS AND A(6) AND
|
|
NOT A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS));
|
|
|
|
|
|
LAN_CFG_I(1) <= '0';
|
|
LAN_CFG(1) <= LAN_CFG_I(1) when LAN_CFG_OE(1) = '1' else 'Z';
|
|
LAN_CFG_OE(1) <= '0';
|
|
|
|
|
|
LAN_CFG_I(2) <= '0';
|
|
LAN_CFG(2) <= LAN_CFG_I(2) when LAN_CFG_OE(2) = '1' else 'Z';
|
|
LAN_CFG_OE(2) <= '0';
|
|
|
|
|
|
LAN_CFG_I(3) <= '0';
|
|
LAN_CFG(3) <= LAN_CFG_I(3) when LAN_CFG_OE(3) = '1' else 'Z';
|
|
LAN_CFG_OE(3) <= '0';
|
|
|
|
|
|
LAN_CFG_I(4) <= '0';
|
|
LAN_CFG(4) <= LAN_CFG_I(4) when LAN_CFG_OE(4) = '1' else 'Z';
|
|
LAN_CFG_OE(4) <= '0';
|
|
|
|
|
|
LAN_CS <= ((NOT RESET AND LAN_CS_RST)
|
|
OR (Z3_ADR(13) AND LAN_CS_RST)
|
|
OR (RESET AND NOT Z3_ADR(13) AND LAN_ACCESS));
|
|
|
|
FDCPE_LAN_CS_RST: FDCPE port map (LAN_CS_RST,LAN_CS_RST_D,CLK_EXT,RESET,'0');
|
|
LAN_CS_RST_D <= (NOT LAN_RST_SM_FSM_FFd1 AND NOT LAN_A_INIT(3));
|
|
|
|
FDCPE_LAN_D_INIT1: FDCPE port map (LAN_D_INIT(1),LAN_D_INIT_D(1),CLK_EXT,RESET,'0');
|
|
LAN_D_INIT_D(1) <= (NOT LAN_RST_SM_FSM_FFd1 AND NOT LAN_RST_SM_FSM_FFd3 AND
|
|
NOT LAN_RST_SM_FSM_FFd2 AND NOT LAN_RST_SM_FSM_FFd4);
|
|
|
|
FDCPE_LAN_D_INIT8: FDCPE port map (LAN_D_INIT(8),LAN_D_INIT_D(8),CLK_EXT,RESET,'0');
|
|
LAN_D_INIT_D(8) <= (NOT LAN_RST_SM_FSM_FFd6 AND NOT LAN_RST_SM_FSM_FFd5 AND
|
|
NOT LAN_RST_SM_FSM_FFd7 AND NOT LAN_A_INIT(3));
|
|
|
|
FTCPE_LAN_INT_ENABLE: FTCPE port map (LAN_INT_ENABLE,LAN_INT_ENABLE_T,CLK_EXT,'0','0');
|
|
LAN_INT_ENABLE_T <= ((NOT FCS AND RESET AND BERR AND D(15).PIN AND NOT UDS AND NOT RW AND
|
|
LAN_SM_FSM_FFd12 AND LAN_ACCESS AND NOT LAN_INT_ENABLE)
|
|
OR (NOT FCS AND RESET AND BERR AND NOT D(15).PIN AND NOT UDS AND NOT RW AND
|
|
LAN_SM_FSM_FFd12 AND LAN_ACCESS AND LAN_INT_ENABLE)
|
|
OR (NOT FCS AND RESET AND BERR AND UDS AND NOT DS1 AND A(23).PIN AND
|
|
NOT RW AND LAN_SM_FSM_FFd12 AND LAN_ACCESS AND NOT LAN_INT_ENABLE)
|
|
OR (NOT FCS AND RESET AND BERR AND UDS AND NOT DS1 AND NOT A(23).PIN AND
|
|
NOT RW AND LAN_SM_FSM_FFd12 AND LAN_ACCESS AND LAN_INT_ENABLE));
|
|
|
|
FDCPE_LAN_IRQ_D0: FDCPE port map (LAN_IRQ_D0,LAN_INT,CLK_EXT,'0',NOT RESET);
|
|
|
|
FDCPE_LAN_IRQ_OUT: FDCPE port map (LAN_IRQ_OUT,LAN_IRQ_OUT_D,CLK_EXT,'0',NOT RESET);
|
|
LAN_IRQ_OUT_D <= ((LAN_INT)
|
|
OR (LAN_IRQ_OUT AND NOT LAN_IRQ_D0));
|
|
|
|
|
|
LAN_RD <= (NOT FCS AND RESET AND LAN_RD_S);
|
|
|
|
FDCPE_LAN_RD_S: FDCPE port map (LAN_RD_S,LAN_RD_S_D,CLK_EXT,NOT Z3_DATA(9)/Z3_DATA(9)_SETF__$INT,'0');
|
|
LAN_RD_S_D <= ((NOT RW AND NOT LAN_SM_FSM_FFd10 AND NOT LAN_SM_FSM_FFd6 AND
|
|
NOT LAN_SM_FSM_FFd11)
|
|
OR (NOT LAN_SM_FSM_FFd10 AND NOT LAN_SM_FSM_FFd6 AND
|
|
NOT LAN_SM_FSM_FFd11 AND Z3_ADR(13))
|
|
OR (NOT LAN_SM_FSM_FFd10 AND NOT LAN_SM_FSM_FFd6 AND
|
|
NOT LAN_SM_FSM_FFd11 AND NOT LAN_SM_FSM_FFd13));
|
|
|
|
FDCPE_LAN_READY: FDCPE port map (LAN_READY,LAN_READY_D,CLK_EXT,NOT Z3_DATA(9)/Z3_DATA(9)_SETF__$INT,'0');
|
|
LAN_READY_D <= ((NOT DS1 AND NOT LAN_SM_FSM_FFd5 AND NOT LAN_SM_FSM_FFd10 AND
|
|
NOT LAN_SM_FSM_FFd12 AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1)
|
|
OR (NOT DS0 AND NOT LAN_SM_FSM_FFd5 AND NOT LAN_SM_FSM_FFd10 AND
|
|
NOT LAN_SM_FSM_FFd12 AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1)
|
|
OR (NOT LAN_SM_FSM_FFd7 AND NOT LAN_SM_FSM_FFd5 AND
|
|
NOT LAN_SM_FSM_FFd10 AND NOT LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd12 AND
|
|
NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1));
|
|
|
|
FDCPE_LAN_RST_SM_FSM_FFd1: FDCPE port map (LAN_RST_SM_FSM_FFd1,LAN_RST_SM_FSM_FFd1_D,CLK_EXT,RESET,'0');
|
|
LAN_RST_SM_FSM_FFd1_D <= (NOT LAN_RST_SM_FSM_FFd1 AND NOT LAN_RST_SM_FSM_FFd2);
|
|
|
|
FDCPE_LAN_RST_SM_FSM_FFd2: FDCPE port map (LAN_RST_SM_FSM_FFd2,LAN_RST_SM_FSM_FFd3,CLK_EXT,RESET,'0');
|
|
|
|
FDCPE_LAN_RST_SM_FSM_FFd3: FDCPE port map (LAN_RST_SM_FSM_FFd3,LAN_RST_SM_FSM_FFd4,CLK_EXT,RESET,'0');
|
|
|
|
FDCPE_LAN_RST_SM_FSM_FFd4: FDCPE port map (LAN_RST_SM_FSM_FFd4,LAN_RST_SM_FSM_FFd5,CLK_EXT,RESET,'0');
|
|
|
|
FDCPE_LAN_RST_SM_FSM_FFd5: FDCPE port map (LAN_RST_SM_FSM_FFd5,LAN_RST_SM_FSM_FFd6,CLK_EXT,RESET,'0');
|
|
|
|
FDCPE_LAN_RST_SM_FSM_FFd6: FDCPE port map (LAN_RST_SM_FSM_FFd6,LAN_RST_SM_FSM_FFd7,CLK_EXT,RESET,'0');
|
|
|
|
FDCPE_LAN_RST_SM_FSM_FFd7: FDCPE port map (LAN_RST_SM_FSM_FFd7,LAN_A_INIT(3),CLK_EXT,RESET,'0');
|
|
|
|
FDCPE_LAN_SM_FSM_FFd1: FDCPE port map (LAN_SM_FSM_FFd1,LAN_SM_FSM_FFd1_D,CLK_EXT,NOT Z3_DATA(9)/Z3_DATA(9)_SETF__$INT,'0');
|
|
LAN_SM_FSM_FFd1_D <= (NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1);
|
|
|
|
FDCPE_LAN_SM_FSM_FFd10: FDCPE port map (LAN_SM_FSM_FFd10,LAN_SM_FSM_FFd10_D,CLK_EXT,NOT Z3_DATA(9)/Z3_DATA(9)_SETF__$INT,'0');
|
|
LAN_SM_FSM_FFd10_D <= ((LAN_SM_FSM_FFd6)
|
|
OR (UDS AND LDS AND RW AND NOT Z3_ADR(13) AND LAN_SM_FSM_FFd13));
|
|
|
|
FDCPE_LAN_SM_FSM_FFd11: FDCPE port map (LAN_SM_FSM_FFd11,LAN_SM_FSM_FFd11_D,CLK_EXT,NOT Z3_DATA(9)/Z3_DATA(9)_SETF__$INT,'0');
|
|
LAN_SM_FSM_FFd11_D <= ((NOT UDS AND RW AND NOT Z3_ADR(13) AND LAN_SM_FSM_FFd13)
|
|
OR (NOT LDS AND RW AND NOT Z3_ADR(13) AND LAN_SM_FSM_FFd13));
|
|
|
|
FTCPE_LAN_SM_FSM_FFd12: FTCPE port map (LAN_SM_FSM_FFd12,LAN_SM_FSM_FFd12_T,CLK_EXT,NOT Z3_DATA(9)/Z3_DATA(9)_SETF__$INT,'0');
|
|
LAN_SM_FSM_FFd12_T <= (NOT LAN_SM_FSM_FFd12 AND Z3_ADR(13) AND LAN_SM_FSM_FFd13);
|
|
|
|
FDCPE_LAN_SM_FSM_FFd13: FDCPE port map (LAN_SM_FSM_FFd13,'0',CLK_EXT,'0',NOT Z3_DATA(9)/Z3_DATA(9)_SETF__$INT);
|
|
|
|
FDCPE_LAN_SM_FSM_FFd2: FDCPE port map (LAN_SM_FSM_FFd2,LAN_SM_FSM_FFd8,CLK_EXT,NOT Z3_DATA(9)/Z3_DATA(9)_SETF__$INT,'0');
|
|
|
|
FDCPE_LAN_SM_FSM_FFd3: FDCPE port map (LAN_SM_FSM_FFd3,LAN_SM_FSM_FFd3_D,CLK_EXT,NOT Z3_DATA(9)/Z3_DATA(9)_SETF__$INT,'0');
|
|
LAN_SM_FSM_FFd3_D <= ((LAN_SM_FSM_FFd4)
|
|
OR (DS1 AND DS0 AND LAN_SM_FSM_FFd3));
|
|
|
|
FDCPE_LAN_SM_FSM_FFd4: FDCPE port map (LAN_SM_FSM_FFd4,LAN_SM_FSM_FFd9,CLK_EXT,NOT Z3_DATA(9)/Z3_DATA(9)_SETF__$INT,'0');
|
|
|
|
FDCPE_LAN_SM_FSM_FFd5: FDCPE port map (LAN_SM_FSM_FFd5,LAN_SM_FSM_FFd5_D,CLK_EXT,NOT Z3_DATA(9)/Z3_DATA(9)_SETF__$INT,'0');
|
|
LAN_SM_FSM_FFd5_D <= (NOT LAN_SM_FSM_FFd5 AND NOT LAN_SM_FSM_FFd10);
|
|
|
|
FDCPE_LAN_SM_FSM_FFd6: FDCPE port map (LAN_SM_FSM_FFd6,LAN_SM_FSM_FFd6_D,CLK_EXT,NOT Z3_DATA(9)/Z3_DATA(9)_SETF__$INT,'0');
|
|
LAN_SM_FSM_FFd6_D <= ((NOT DS1 AND LAN_SM_FSM_FFd7)
|
|
OR (NOT DS0 AND LAN_SM_FSM_FFd7));
|
|
|
|
FDCPE_LAN_SM_FSM_FFd7: FDCPE port map (LAN_SM_FSM_FFd7,LAN_SM_FSM_FFd7_D,CLK_EXT,NOT Z3_DATA(9)/Z3_DATA(9)_SETF__$INT,'0');
|
|
LAN_SM_FSM_FFd7_D <= ((LAN_SM_FSM_FFd11)
|
|
OR (DS1 AND DS0 AND LAN_SM_FSM_FFd7));
|
|
|
|
FDCPE_LAN_SM_FSM_FFd8: FDCPE port map (LAN_SM_FSM_FFd8,LAN_SM_FSM_FFd8_D,CLK_EXT,NOT Z3_DATA(9)/Z3_DATA(9)_SETF__$INT,'0');
|
|
LAN_SM_FSM_FFd8_D <= ((NOT DS1 AND LAN_SM_FSM_FFd3)
|
|
OR (NOT DS0 AND LAN_SM_FSM_FFd3)
|
|
OR (UDS AND LDS AND NOT RW AND NOT Z3_ADR(13) AND LAN_SM_FSM_FFd13));
|
|
|
|
FDCPE_LAN_SM_FSM_FFd9: FDCPE port map (LAN_SM_FSM_FFd9,LAN_SM_FSM_FFd9_D,CLK_EXT,NOT Z3_DATA(9)/Z3_DATA(9)_SETF__$INT,'0');
|
|
LAN_SM_FSM_FFd9_D <= ((NOT UDS AND NOT RW AND NOT Z3_ADR(13) AND LAN_SM_FSM_FFd13)
|
|
OR (NOT LDS AND NOT RW AND NOT Z3_ADR(13) AND LAN_SM_FSM_FFd13));
|
|
|
|
|
|
LAN_WRH <= ((FCS AND LAN_WR_RST)
|
|
OR (NOT RESET AND LAN_WR_RST)
|
|
OR (NOT FCS AND RESET AND LAN_WRH_S));
|
|
|
|
FDCPE_LAN_WRH_S: FDCPE port map (LAN_WRH_S,LAN_WRH_S_D,CLK_EXT,NOT Z3_DATA(9)/Z3_DATA(9)_SETF__$INT,'0');
|
|
LAN_WRH_S_D <= ((NOT LDS AND LAN_SM_FSM_FFd9)
|
|
OR (NOT DS0 AND LAN_SM_FSM_FFd8));
|
|
|
|
|
|
LAN_WRL <= ((FCS AND LAN_WR_RST)
|
|
OR (NOT RESET AND LAN_WR_RST)
|
|
OR (NOT FCS AND RESET AND LAN_WRL_S));
|
|
|
|
FDCPE_LAN_WRL_S: FDCPE port map (LAN_WRL_S,LAN_WRL_S_D,CLK_EXT,NOT Z3_DATA(9)/Z3_DATA(9)_SETF__$INT,'0');
|
|
LAN_WRL_S_D <= ((NOT UDS AND LAN_SM_FSM_FFd9)
|
|
OR (NOT DS1 AND LAN_SM_FSM_FFd8));
|
|
|
|
FDCPE_LAN_WR_RST: FDCPE port map (LAN_WR_RST,LAN_WR_RST_D,CLK_EXT,RESET,'0');
|
|
LAN_WR_RST_D <= (NOT LAN_RST_SM_FSM_FFd3 AND NOT LAN_RST_SM_FSM_FFd6);
|
|
|
|
|
|
MTACK_I <= '0';
|
|
MTACK <= MTACK_I when MTACK_OE = '1' else 'Z';
|
|
MTACK_OE <= '0';
|
|
|
|
|
|
OVR_I <= '0';
|
|
OVR <= OVR_I when OVR_OE = '1' else 'Z';
|
|
OVR_OE <= (NOT FCS AND LAN_ACCESS);
|
|
|
|
|
|
OWN_I <= '0';
|
|
OWN <= OWN_I when OWN_OE = '1' else 'Z';
|
|
OWN_OE <= '0';
|
|
|
|
|
|
ROM_B(0) <= '0';
|
|
|
|
|
|
ROM_B(1) <= '0';
|
|
|
|
|
|
ROM_OE <= NOT ((NOT AS AND NOT ROM_OE_S AND NOT AUTOBOOT_OFF));
|
|
|
|
FDCPE_ROM_OE_S: FDCPE port map (ROM_OE_S,ROM_OE_S_D,SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET);
|
|
ROM_OE_S_D <= (NOT AS AND RW AND IDE_ACCESS AND IDE_ENABLE);
|
|
|
|
FTCPE_SHUT_UP_Z20: FTCPE port map (SHUT_UP_Z2(0),SHUT_UP_Z2_T(0),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET);
|
|
SHUT_UP_Z2_T(0) <= ((NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
|
|
NOT AUTO_CONFIG_Z2_DONE(0) AND NOT UDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS AND
|
|
SHUT_UP_Z2(0))
|
|
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
|
|
NOT AUTO_CONFIG_Z2_DONE(0) AND NOT LDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS AND
|
|
SHUT_UP_Z2(0)));
|
|
|
|
FTCPE_SHUT_UP_Z21: FTCPE port map (SHUT_UP_Z2(1),SHUT_UP_Z2_T(1),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET);
|
|
SHUT_UP_Z2_T(1) <= ((NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
|
|
AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE(1) AND NOT UDS AND A(6) AND A(3) AND
|
|
NOT RW AND AUTOCONFIG_Z2_ACCESS AND SHUT_UP_Z2(1))
|
|
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
|
|
AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE(1) AND NOT LDS AND A(6) AND A(3) AND
|
|
NOT RW AND AUTOCONFIG_Z2_ACCESS AND SHUT_UP_Z2(1)));
|
|
|
|
FTCPE_SHUT_UP_Z22: FTCPE port map (SHUT_UP_Z2(2),SHUT_UP_Z2_T(2),SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF,'0',NOT RESET);
|
|
SHUT_UP_Z2_T(2) <= ((NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
|
|
AUTO_CONFIG_Z2_DONE(0) AND AUTO_CONFIG_Z2_DONE(1) AND NOT AUTO_CONFIG_Z2_DONE(2) AND
|
|
NOT UDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS AND
|
|
SHUT_UP_Z2(2))
|
|
OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND NOT A(1) AND NOT AS AND
|
|
AUTO_CONFIG_Z2_DONE(0) AND AUTO_CONFIG_Z2_DONE(1) AND NOT AUTO_CONFIG_Z2_DONE(2) AND
|
|
NOT LDS AND A(6) AND A(3) AND NOT RW AND AUTOCONFIG_Z2_ACCESS AND
|
|
SHUT_UP_Z2(2)));
|
|
|
|
|
|
SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF <= C1
|
|
XOR
|
|
SHUT_UP_Z2(2)/SHUT_UP_Z2(2)_CLKF <= C3;
|
|
|
|
|
|
SLAVE <= ((FCS AND AS)
|
|
OR (AS AND NOT LAN_ACCESS)
|
|
OR (FCS AND NOT AUTOCONFIG_Z2_ACCESS AND NOT IDE_ACCESS AND CP_CS)
|
|
OR (NOT AUTOCONFIG_Z2_ACCESS AND NOT LAN_ACCESS AND NOT IDE_ACCESS AND
|
|
CP_CS));
|
|
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|
FDCPE_Z3_ADR2: FDCPE port map (Z3_ADR(2),A(4),NOT FCS,'0',NOT RESET);
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FDCPE_Z3_ADR3: FDCPE port map (Z3_ADR(3),A(5),NOT FCS,'0',NOT RESET);
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|
FDCPE_Z3_ADR4: FDCPE port map (Z3_ADR(4),A(6),NOT FCS,'0',NOT RESET);
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|
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|
FDCPE_Z3_ADR5: FDCPE port map (Z3_ADR(5),A(7),NOT FCS,'0',NOT RESET);
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|
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FDCPE_Z3_ADR6: FDCPE port map (Z3_ADR(6),A(8).PIN,NOT FCS,'0',NOT RESET);
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FDCPE_Z3_ADR7: FDCPE port map (Z3_ADR(7),A(9).PIN,NOT FCS,'0',NOT RESET);
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FDCPE_Z3_ADR8: FDCPE port map (Z3_ADR(8),A(10).PIN,NOT FCS,'0',NOT RESET);
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FDCPE_Z3_ADR9: FDCPE port map (Z3_ADR(9),A(11).PIN,NOT FCS,'0',NOT RESET);
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FDCPE_Z3_ADR10: FDCPE port map (Z3_ADR(10),A(12).PIN,NOT FCS,'0',NOT RESET);
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FDCPE_Z3_ADR11: FDCPE port map (Z3_ADR(11),A(13).PIN,NOT FCS,'0',NOT RESET);
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FDCPE_Z3_ADR12: FDCPE port map (Z3_ADR(12),A(14).PIN,NOT FCS,'0',NOT RESET);
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|
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FDCPE_Z3_ADR13: FDCPE port map (Z3_ADR(13),A(15).PIN,NOT FCS,'0',NOT RESET);
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FDCPE_Z3_ADR_0: FDCPE port map (Z3_ADR_0,A(2),NOT FCS,'0',NOT RESET);
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FDCPE_Z3_ADR_1: FDCPE port map (Z3_ADR_1,A(3),NOT FCS,'0',NOT RESET);
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FDCPE_Z3_A_LOW: FDCPE port map (Z3_A_LOW,Z3_A_LOW_D,CLK_EXT,NOT Z3_DATA(9)/Z3_DATA(9)_SETF__$INT,'0');
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Z3_A_LOW_D <= ((DS1 AND DS0 AND NOT LAN_SM_FSM_FFd10 AND NOT LAN_SM_FSM_FFd8 AND
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NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd6 AND NOT LAN_SM_FSM_FFd13)
|
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OR (NOT LAN_SM_FSM_FFd7 AND NOT LAN_SM_FSM_FFd10 AND
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|
NOT LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd8 AND NOT LAN_SM_FSM_FFd2 AND
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|
NOT LAN_SM_FSM_FFd6 AND NOT LAN_SM_FSM_FFd13)
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|
OR (NOT UDS AND DS1 AND DS0 AND NOT LAN_SM_FSM_FFd10 AND
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NOT LAN_SM_FSM_FFd8 AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd6)
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|
OR (NOT UDS AND NOT LAN_SM_FSM_FFd7 AND NOT LAN_SM_FSM_FFd10 AND
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NOT LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd8 AND NOT LAN_SM_FSM_FFd2 AND
|
|
NOT LAN_SM_FSM_FFd6)
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OR (NOT LDS AND DS1 AND DS0 AND NOT LAN_SM_FSM_FFd10 AND
|
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NOT LAN_SM_FSM_FFd8 AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd6)
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|
OR (NOT LDS AND NOT LAN_SM_FSM_FFd7 AND NOT LAN_SM_FSM_FFd10 AND
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|
NOT LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd8 AND NOT LAN_SM_FSM_FFd2 AND
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|
NOT LAN_SM_FSM_FFd6));
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Z3_DATA(9)/Z3_DATA(9)_SETF__$INT <= ((NOT FCS AND RESET AND BERR AND NOT UDS AND LAN_ACCESS)
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OR (NOT FCS AND RESET AND BERR AND NOT LDS AND LAN_ACCESS)
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|
OR (NOT FCS AND RESET AND BERR AND NOT DS1 AND LAN_ACCESS)
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|
OR (NOT FCS AND RESET AND BERR AND NOT DS0 AND LAN_ACCESS));
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FDCPE_Z3_DATA16: FDCPE port map (Z3_DATA(16),Z3_DATA_D(16),CLK_EXT,'0',NOT Z3_DATA(9)/Z3_DATA(9)_SETF__$INT,LAN_SM_FSM_FFd7);
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Z3_DATA_D(16) <= ((DQ_SWAP AND DQ(8).PIN)
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OR (NOT DQ_SWAP AND DQ(0).PIN));
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FDCPE_Z3_DATA17: FDCPE port map (Z3_DATA(17),Z3_DATA_D(17),CLK_EXT,'0',NOT Z3_DATA(9)/Z3_DATA(9)_SETF__$INT,LAN_SM_FSM_FFd7);
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Z3_DATA_D(17) <= ((DQ_SWAP AND DQ(9).PIN)
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OR (NOT DQ_SWAP AND DQ(1).PIN));
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|
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FDCPE_Z3_DATA18: FDCPE port map (Z3_DATA(18),Z3_DATA_D(18),CLK_EXT,'0',NOT Z3_DATA(9)/Z3_DATA(9)_SETF__$INT,LAN_SM_FSM_FFd7);
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Z3_DATA_D(18) <= ((DQ_SWAP AND DQ(10).PIN)
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|
OR (NOT DQ_SWAP AND DQ(2).PIN));
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|
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FDCPE_Z3_DATA19: FDCPE port map (Z3_DATA(19),Z3_DATA_D(19),CLK_EXT,'0',NOT Z3_DATA(9)/Z3_DATA(9)_SETF__$INT,LAN_SM_FSM_FFd7);
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Z3_DATA_D(19) <= ((DQ_SWAP AND DQ(11).PIN)
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|
OR (NOT DQ_SWAP AND DQ(3).PIN));
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|
|
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FDCPE_Z3_DATA20: FDCPE port map (Z3_DATA(20),Z3_DATA_D(20),CLK_EXT,'0',NOT Z3_DATA(9)/Z3_DATA(9)_SETF__$INT,LAN_SM_FSM_FFd7);
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Z3_DATA_D(20) <= ((DQ_SWAP AND DQ(12).PIN)
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|
OR (NOT DQ_SWAP AND DQ(4).PIN));
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|
|
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FDCPE_Z3_DATA21: FDCPE port map (Z3_DATA(21),Z3_DATA_D(21),CLK_EXT,'0',NOT Z3_DATA(9)/Z3_DATA(9)_SETF__$INT,LAN_SM_FSM_FFd7);
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Z3_DATA_D(21) <= ((DQ_SWAP AND DQ(13).PIN)
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|
OR (NOT DQ_SWAP AND DQ(5).PIN));
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|
|
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FDCPE_Z3_DATA22: FDCPE port map (Z3_DATA(22),Z3_DATA_D(22),CLK_EXT,'0',NOT Z3_DATA(9)/Z3_DATA(9)_SETF__$INT,LAN_SM_FSM_FFd7);
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|
Z3_DATA_D(22) <= ((DQ_SWAP AND DQ(14).PIN)
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|
OR (NOT DQ_SWAP AND DQ(6).PIN));
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|
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FDCPE_Z3_DATA23: FDCPE port map (Z3_DATA(23),Z3_DATA_D(23),CLK_EXT,'0',NOT Z3_DATA(9)/Z3_DATA(9)_SETF__$INT,LAN_SM_FSM_FFd7);
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|
Z3_DATA_D(23) <= ((DQ_SWAP AND DQ(15).PIN)
|
|
OR (NOT DQ_SWAP AND DQ(7).PIN));
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|
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FDCPE_Z3_DATA24: FDCPE port map (Z3_DATA(24),Z3_DATA_D(24),CLK_EXT,'0',NOT Z3_DATA(9)/Z3_DATA(9)_SETF__$INT,LAN_SM_FSM_FFd7);
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|
Z3_DATA_D(24) <= ((DQ_SWAP AND DQ(0).PIN)
|
|
OR (NOT DQ_SWAP AND DQ(8).PIN));
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|
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FDCPE_Z3_DATA25: FDCPE port map (Z3_DATA(25),Z3_DATA_D(25),CLK_EXT,'0',NOT Z3_DATA(9)/Z3_DATA(9)_SETF__$INT,LAN_SM_FSM_FFd7);
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|
Z3_DATA_D(25) <= ((DQ_SWAP AND DQ(1).PIN)
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|
OR (NOT DQ_SWAP AND DQ(9).PIN));
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|
|
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FDCPE_Z3_DATA26: FDCPE port map (Z3_DATA(26),Z3_DATA_D(26),CLK_EXT,'0',NOT Z3_DATA(9)/Z3_DATA(9)_SETF__$INT,LAN_SM_FSM_FFd7);
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|
Z3_DATA_D(26) <= ((DQ_SWAP AND DQ(2).PIN)
|
|
OR (NOT DQ_SWAP AND DQ(10).PIN));
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|
|
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FDCPE_Z3_DATA27: FDCPE port map (Z3_DATA(27),Z3_DATA_D(27),CLK_EXT,'0',NOT Z3_DATA(9)/Z3_DATA(9)_SETF__$INT,LAN_SM_FSM_FFd7);
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|
Z3_DATA_D(27) <= ((DQ_SWAP AND DQ(3).PIN)
|
|
OR (NOT DQ_SWAP AND DQ(11).PIN));
|
|
|
|
FDCPE_Z3_DATA28: FDCPE port map (Z3_DATA(28),Z3_DATA_D(28),CLK_EXT,'0',NOT Z3_DATA(9)/Z3_DATA(9)_SETF__$INT,LAN_SM_FSM_FFd7);
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|
Z3_DATA_D(28) <= ((DQ_SWAP AND DQ(4).PIN)
|
|
OR (NOT DQ_SWAP AND DQ(12).PIN));
|
|
|
|
FDCPE_Z3_DATA29: FDCPE port map (Z3_DATA(29),Z3_DATA_D(29),CLK_EXT,'0',NOT Z3_DATA(9)/Z3_DATA(9)_SETF__$INT,LAN_SM_FSM_FFd7);
|
|
Z3_DATA_D(29) <= ((DQ_SWAP AND DQ(5).PIN)
|
|
OR (NOT DQ_SWAP AND DQ(13).PIN));
|
|
|
|
FDCPE_Z3_DATA30: FDCPE port map (Z3_DATA(30),Z3_DATA_D(30),CLK_EXT,'0',NOT Z3_DATA(9)/Z3_DATA(9)_SETF__$INT,LAN_SM_FSM_FFd7);
|
|
Z3_DATA_D(30) <= ((DQ_SWAP AND DQ(6).PIN)
|
|
OR (NOT DQ_SWAP AND DQ(14).PIN));
|
|
|
|
FDCPE_Z3_DATA31: FDCPE port map (Z3_DATA(31),Z3_DATA_D(31),CLK_EXT,'0',NOT Z3_DATA(9)/Z3_DATA(9)_SETF__$INT,LAN_SM_FSM_FFd7);
|
|
Z3_DATA_D(31) <= ((DQ_SWAP AND DQ(7).PIN)
|
|
OR (NOT DQ_SWAP AND DQ(15).PIN));
|
|
|
|
Register Legend:
|
|
FDCPE (Q,D,C,CLR,PRE,CE);
|
|
FTCPE (Q,D,C,CLR,PRE,CE);
|
|
LDCP (Q,D,G,CLR,PRE);
|
|
|
|
****************************** Device Pin Out *****************************
|
|
|
|
Device : XC95288XL-10-TQ144
|
|
|
|
|
|
Pin Signal Pin Signal
|
|
No. Name No. Name
|
|
1 VCC 73 VCC
|
|
2 D<0> 74 A<15>
|
|
3 A_LAN<1> 75 AUTOBOOT_OFF
|
|
4 A_LAN<0> 76 LAN_WRL
|
|
5 A_LAN<3> 77 FCS
|
|
6 A_LAN<2> 78 DS1
|
|
7 A_LAN<5> 79 Z3
|
|
8 VCC 80 AS
|
|
9 A_LAN<4> 81 UDS
|
|
10 A_LAN<7> 82 LDS
|
|
11 A_LAN<6> 83 RW
|
|
12 LAN_CFG<1> 84 VCC
|
|
13 LAN_CFG<3> 85 DTACK
|
|
14 D<6> 86 A<23>
|
|
15 D<3> 87 A<22>
|
|
16 D<7> 88 A<21>
|
|
17 D<1> 89 GND
|
|
18 GND 90 GND
|
|
19 D<8> 91 A<20>
|
|
20 D<5> 92 A<19>
|
|
21 D<4> 93 DS0
|
|
22 IDE_CS<0> 94 A<18>
|
|
23 IDE_CS<1> 95 A<17>
|
|
24 IDE_A<0> 96 MTACK
|
|
25 IDE_A<2> 97 A<16>
|
|
26 IDE_A<1> 98 BERR
|
|
27 IDE_R 99 GND
|
|
28 IDE_W 100 OVR
|
|
29 GND 101 TIE
|
|
30 CLK_EXT 102 C3
|
|
31 CP_IRQ 103 C1
|
|
32 INT2_OUT 104 CFIN
|
|
33 ROM_B<0> 105 CFOUT
|
|
34 CP_CS 106 SLAVE
|
|
35 ROM_OE 107 OWN
|
|
36 GND 108 GND
|
|
37 VCC 109 VCC
|
|
38 TIE 110 LAN_CFG<4>
|
|
39 D<2> 111 LAN_INT
|
|
40 D<9> 112 DQ<15>
|
|
41 D<10> 113 DQ<13>
|
|
42 VCC 114 GND
|
|
43 D<11> 115 DQ<11>
|
|
44 D<12> 116 DQ<9>
|
|
45 D<13> 117 DQ<1>
|
|
46 D<14> 118 DQ<0>
|
|
47 GND 119 DQ<3>
|
|
48 D<15> 120 DQ<2>
|
|
49 A<5> 121 DQ<5>
|
|
50 A<4> 122 TDO
|
|
51 A<6> 123 GND
|
|
52 A<3> 124 DQ<4>
|
|
53 A<7> 125 DQ<7>
|
|
54 A<2> 126 DQ<6>
|
|
55 VCC 127 VCC
|
|
56 A<8> 128 DQ<8>
|
|
57 A<1> 129 DQ<10>
|
|
58 A<9> 130 DQ<12>
|
|
59 A<10> 131 DQ<14>
|
|
60 A<11> 132 LAN_WRH
|
|
61 A<12> 133 LAN_CS
|
|
62 GND 134 LAN_RD
|
|
63 TDI 135 LAN_CFG<2>
|
|
64 A<13> 136 A_LAN<12>
|
|
65 TMS 137 A_LAN<13>
|
|
66 A<14> 138 A_LAN<10>
|
|
67 TCK 139 A_LAN<11>
|
|
68 INT6_OUT 140 A_LAN<8>
|
|
69 ROM_B<1> 141 VCC
|
|
70 CP_WE 142 A_LAN<9>
|
|
71 CP_RD 143 RESET
|
|
72 GND 144 GND
|
|
|
|
|
|
Legend : NC = Not Connected, unbonded pin
|
|
PGND = Unused I/O configured as additional Ground pin
|
|
TIE = Unused I/O floating -- must tie to VCC, GND or other signal
|
|
KPR = Unused I/O with weak keeper (leave unconnected)
|
|
VCC = Dedicated Power Pin
|
|
GND = Dedicated Ground Pin
|
|
TDI = Test Data In, JTAG pin
|
|
TDO = Test Data Out, JTAG pin
|
|
TCK = Test Clock, JTAG pin
|
|
TMS = Test Mode Select, JTAG pin
|
|
PROHIBITED = User reserved pin
|
|
**************************** Compiler Options ****************************
|
|
|
|
Following is a list of all global compiler options used by the fitter run.
|
|
|
|
Device(s) Specified : xc95288xl-10-TQ144
|
|
Optimization Method : SPEED
|
|
Multi-Level Logic Optimization : ON
|
|
Ignore Timing Specifications : OFF
|
|
Default Register Power Up Value : LOW
|
|
Keep User Location Constraints : ON
|
|
What-You-See-Is-What-You-Get : OFF
|
|
Exhaustive Fitting : OFF
|
|
Keep Unused Inputs : OFF
|
|
Slew Rate : FAST
|
|
Power Mode : STD
|
|
Ground on Unused IOs : OFF
|
|
Set I/O Pin Termination : FLOAT
|
|
Global Clock Optimization : ON
|
|
Global Set/Reset Optimization : ON
|
|
Global Ouput Enable Optimization : ON
|
|
Input Limit : 54
|
|
Pterm Limit : 14
|