316 lines
14 KiB
Plaintext
316 lines
14 KiB
Plaintext
Release 14.7 - xst P.20131013 (nt64)
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Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
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--> Parameter TMPDIR set to xst/projnav.tmp
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Total REAL time to Xst completion: 0.00 secs
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Total CPU time to Xst completion: 0.08 secs
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--> Parameter xsthdpdir set to xst
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Total REAL time to Xst completion: 0.00 secs
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Total CPU time to Xst completion: 0.08 secs
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--> Reading design: LAN_IDE_CP.prj
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TABLE OF CONTENTS
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1) Synthesis Options Summary
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2) HDL Compilation
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3) Design Hierarchy Analysis
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4) HDL Analysis
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5) HDL Synthesis
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5.1) HDL Synthesis Report
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6) Advanced HDL Synthesis
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6.1) Advanced HDL Synthesis Report
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7) Low Level Synthesis
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8) Partition Report
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9) Final Report
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=========================================================================
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* Synthesis Options Summary *
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=========================================================================
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---- Source Parameters
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Input File Name : "LAN_IDE_CP.prj"
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Input Format : mixed
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Ignore Synthesis Constraint File : NO
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---- Target Parameters
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Output File Name : "LAN_IDE_CP"
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Output Format : NGC
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Target Device : XC9500XL CPLDs
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---- Source Options
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Top Module Name : LAN_IDE_CP
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Automatic FSM Extraction : YES
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FSM Encoding Algorithm : Gray
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Safe Implementation : No
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Mux Extraction : Yes
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Resource Sharing : YES
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---- Target Options
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Add IO Buffers : YES
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MACRO Preserve : YES
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XOR Preserve : YES
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Equivalent register Removal : YES
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---- General Options
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Optimization Goal : Speed
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Optimization Effort : 2
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Keep Hierarchy : Yes
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Netlist Hierarchy : As_Optimized
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RTL Output : Yes
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Hierarchy Separator : /
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Bus Delimiter : <>
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Case Specifier : Maintain
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Verilog 2001 : YES
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---- Other Options
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Clock Enable : YES
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wysiwyg : NO
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=========================================================================
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Setting FSM Encoding Algorithm to : Gray
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=========================================================================
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* HDL Compilation *
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=========================================================================
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Compiling vhdl file "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE_V2/LAN_IDE_CP-Z2v2.vhd" in Library work.
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Entity <lan_ide_cp> compiled.
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Entity <lan_ide_cp> (Architecture <behavioral>) compiled.
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=========================================================================
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* Design Hierarchy Analysis *
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=========================================================================
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Analyzing hierarchy for entity <LAN_IDE_CP> in library <work> (architecture <behavioral>).
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=========================================================================
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* HDL Analysis *
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=========================================================================
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Analyzing Entity <LAN_IDE_CP> in library <work> (Architecture <behavioral>).
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Entity <LAN_IDE_CP> analyzed. Unit <LAN_IDE_CP> generated.
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=========================================================================
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* HDL Synthesis *
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=========================================================================
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Performing bidirectional port resolution...
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INFO:Xst:2561 - Always blocking tristate driving signal <A> in unit <LAN_IDE_CP> is removed.
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Synthesizing Unit <LAN_IDE_CP>.
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Related source file is "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE_V2/LAN_IDE_CP-Z2v2.vhd".
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WARNING:Xst:647 - Input <DS0> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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WARNING:Xst:647 - Input <DS1> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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WARNING:Xst:647 - Input <FCS> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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WARNING:Xst:647 - Input <Z3> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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WARNING:Xst:647 - Input <MTCR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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WARNING:Xst:646 - Signal <ROM_OE_D0> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
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WARNING:Xst:1780 - Signal <LAN_INT_D0> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
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WARNING:Xst:1780 - Signal <DTACK_S> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
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WARNING:Xst:646 - Signal <DECODE_RESET> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
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Found finite state machine <FSM_0> for signal <LAN_RST_SM>.
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-----------------------------------------------------------------------
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| States | 8 |
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| Transitions | 8 |
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| Inputs | 0 |
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| Outputs | 8 |
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| Clock | CLK_EXT (rising_edge) |
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| Reset | RESET (negative) |
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| Reset type | synchronous |
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| Reset State | nop |
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| Power Up State | nop |
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| Encoding | gray |
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| Implementation | automatic |
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-----------------------------------------------------------------------
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Found 16-bit tristate buffer for signal <D>.
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Found 16-bit tristate buffer for signal <DQ>.
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Found 1-bit tristate buffer for signal <OWN>.
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Found 1-bit tristate buffer for signal <OVR>.
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Found 1-bit tristate buffer for signal <MTACK>.
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Found 1-bit tristate buffer for signal <DTACK>.
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Found 1-bit tristate buffer for signal <INT2_OUT>.
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Found 1-bit tristate buffer for signal <INT6_OUT>.
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Found 1-bit xor2 for signal <AMIGA_CLK$xor0000> created at line 148.
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Found 2-bit register for signal <AUTO_CONFIG_DONE>.
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Found 2-bit register for signal <AUTO_CONFIG_DONE_CYCLE>.
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Found 2-bit adder for signal <AUTO_CONFIG_DONE_CYCLE$addsub0000> created at line 459.
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Found 1-bit register for signal <autoconfig>.
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Found 2-bit comparator less for signal <autoconfig$cmp_lt0000> created at line 217.
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Found 1-bit register for signal <cp>.
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Found 8-bit comparator equal for signal <cp$cmp_eq0000> created at line 227.
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Found 8-bit register for signal <CP_BASEADR>.
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Found 1-bit register for signal <CP_RD_S>.
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Found 1-bit register for signal <CP_WE_QUIRK>.
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Found 1-bit register for signal <CP_WE_S>.
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Found 4-bit register for signal <Dout1>.
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Found 3-bit comparator less for signal <Dout1$cmp_lt0000> created at line 381.
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Found 1-bit register for signal <DS_D>.
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Found 1-bit register for signal <ide>.
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Found 8-bit comparator equal for signal <ide$cmp_eq0000> created at line 231.
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Found 8-bit register for signal <IDE_BASEADR>.
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Found 1-bit register for signal <IDE_ENABLE>.
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Found 1-bit register for signal <IDE_R_S>.
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Found 1-bit register for signal <IDE_TERM>.
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Found 1-bit register for signal <IDE_W_S>.
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Found 1-bit register for signal <lan_adr>.
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Found 1-bit register for signal <lan_adr_sw>.
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Found 8-bit comparator equal for signal <lan_adr_sw$cmp_eq0000> created at line 220.
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Found 2-bit comparator less for signal <lan_adr_sw$cmp_lt0000> created at line 221.
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Found 8-bit register for signal <LAN_BASEADR>.
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Found 1-bit register for signal <LAN_CS_RST>.
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Found 1-bit register for signal <LAN_INT_ENABLE>.
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Found 1-bit register for signal <LAN_IRQ_D0>.
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Found 1-bit register for signal <LAN_IRQ_OUT>.
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Found 1-bit register for signal <LAN_RD_S>.
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Found 1-bit register for signal <LAN_WR_RST>.
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Found 1-bit register for signal <LAN_WRH_S>.
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Found 1-bit register for signal <LAN_WRL_S>.
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Found 1-bit register for signal <lancp>.
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Found 1-bit register for signal <ROM_OE_S>.
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Found 3-bit register for signal <SHUT_UP>.
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Summary:
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inferred 1 Finite State Machine(s).
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inferred 24 D-type flip-flop(s).
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inferred 1 Adder/Subtractor(s).
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inferred 6 Comparator(s).
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inferred 1 Xor(s).
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inferred 38 Tristate(s).
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Unit <LAN_IDE_CP> synthesized.
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=========================================================================
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HDL Synthesis Report
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Macro Statistics
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# Adders/Subtractors : 1
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2-bit adder : 1
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# Registers : 32
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1-bit register : 26
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2-bit register : 2
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4-bit register : 1
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8-bit register : 3
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# Comparators : 6
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2-bit comparator less : 2
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3-bit comparator less : 1
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8-bit comparator equal : 3
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# Tristates : 8
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1-bit tristate buffer : 6
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16-bit tristate buffer : 2
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# Xors : 1
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1-bit xor2 : 1
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=========================================================================
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=========================================================================
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* Advanced HDL Synthesis *
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=========================================================================
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Optimizing FSM <LAN_RST_SM/FSM> on signal <LAN_RST_SM[1:3]> with gray encoding.
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------------------------
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State | Encoding
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------------------------
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nop | 000
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wait0 | 001
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clr | 011
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clr_commit | 010
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wait1 | 110
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set | 111
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set_commit | 101
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done | 100
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------------------------
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=========================================================================
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Advanced HDL Synthesis Report
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Macro Statistics
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# FSMs : 1
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# Adders/Subtractors : 1
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2-bit adder : 1
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# Registers : 24
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Flip-Flops : 24
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# Comparators : 3
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8-bit comparator equal : 3
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=========================================================================
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=========================================================================
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* Low Level Synthesis *
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=========================================================================
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Optimizing unit <LAN_IDE_CP> ...
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implementation constraint: INIT=r : LAN_RST_SM_FSM_FFd3
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implementation constraint: INIT=r : LAN_RST_SM_FSM_FFd2
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implementation constraint: INIT=r : LAN_RST_SM_FSM_FFd1
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=========================================================================
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* Partition Report *
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=========================================================================
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Partition Implementation Status
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-------------------------------
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No Partitions were found in this design.
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-------------------------------
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=========================================================================
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* Final Report *
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=========================================================================
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Final Results
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RTL Top Level Output File Name : LAN_IDE_CP.ngr
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Top Level Output File Name : LAN_IDE_CP
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Output Format : NGC
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Optimization Goal : Speed
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Keep Hierarchy : Yes
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Target Technology : XC9500XL CPLDs
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Macro Preserve : YES
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XOR Preserve : YES
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Clock Enable : YES
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wysiwyg : NO
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Design Statistics
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# IOs : 113
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Cell Usage :
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# BELS : 864
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# AND2 : 211
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# AND3 : 67
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# AND4 : 8
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# AND5 : 3
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# AND8 : 3
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# GND : 1
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# INV : 345
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# OR2 : 187
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# OR3 : 10
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# OR4 : 2
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# XOR2 : 27
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# FlipFlops/Latches : 61
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# FD : 5
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# FDC : 9
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# FDCE : 6
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# FDP : 8
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# FDPE : 33
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# IO Buffers : 107
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# IBUF : 36
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# IOBUFE : 32
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# OBUF : 33
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# OBUFE : 6
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=========================================================================
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Total REAL time to Xst completion: 3.00 secs
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Total CPU time to Xst completion: 2.73 secs
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-->
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Total memory usage is 4514352 kilobytes
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Number of errors : 0 ( 0 filtered)
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Number of warnings : 9 ( 0 filtered)
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Number of infos : 1 ( 0 filtered)
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