34 lines
2.4 KiB
XML
34 lines
2.4 KiB
XML
<?xml version="1.0" encoding="UTF-8"?>
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<!-- IMPORTANT: This is an internal file that has been generated
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by the Xilinx ISE software. Any direct editing or
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changes made to this file may result in unpredictable
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behavior or data corruption. It is strongly advised that
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users do not edit the contents of this file. -->
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<messages>
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<msg type="warning" file="Cpld" num="0" delta="new" >Unable to retrieve the path to the iSE Project Repository. Will use the default filename of '<arg fmt="%s" index="1">LAN_IDE_CP.ise</arg>'.
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</msg>
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<msg type="info" file="Cpld" num="0" delta="new" >Inferring BUFG constraint for signal '<arg fmt="%s" index="1">CLK_EXT</arg>' based upon the LOC constraint '<arg fmt="%s" index="2">P30</arg>'. It is recommended that you declare this BUFG explicitedly in your design. Note that for certain device families the output of a BUFG constraint can not drive a gated clock, and the BUFG constraint will be ignored.
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</msg>
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<msg type="warning" file="Cpld" num="1007" delta="old" >Removing unused input(s) '<arg fmt="%s" index="1">DS0</arg>'. The input(s) are unused after optimization. Please verify functionality via simulation.
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</msg>
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<msg type="warning" file="Cpld" num="1007" delta="old" >Removing unused input(s) '<arg fmt="%s" index="1">DS1</arg>'. The input(s) are unused after optimization. Please verify functionality via simulation.
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</msg>
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<msg type="warning" file="Cpld" num="1007" delta="old" >Removing unused input(s) '<arg fmt="%s" index="1">FCS</arg>'. The input(s) are unused after optimization. Please verify functionality via simulation.
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</msg>
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<msg type="warning" file="Cpld" num="1007" delta="old" >Removing unused input(s) '<arg fmt="%s" index="1">MTCR</arg>'. The input(s) are unused after optimization. Please verify functionality via simulation.
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</msg>
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<msg type="warning" file="Cpld" num="1007" delta="old" >Removing unused input(s) '<arg fmt="%s" index="1">Z3</arg>'. The input(s) are unused after optimization. Please verify functionality via simulation.
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</msg>
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<msg type="warning" file="Cpld" num="896" delta="new" >Unable to map all desired signals into function block, FB<arg fmt="%d" index="1">10</arg>, because too many function block product terms are required. Buffering output signal <arg fmt="%s" index="2">DQ<8></arg> to allow all signals assigned to this function block to be placed.
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</msg>
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</messages>
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