566 lines
17 KiB
VHDL
566 lines
17 KiB
VHDL
----------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date: 22:08:29 12/13/2016
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-- Design Name:
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-- Module Name: LAN_IDE_CP - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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-- directory cleanup hint:
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-- svn status|grep ^M|sed "s/^M [\t ]*//"|xargs rm
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity LAN_IDE_CP is
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Port ( A : inout STD_LOGIC_VECTOR (23 downto 1);
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D : inout STD_LOGIC_VECTOR (15 downto 0);
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DQ : inout STD_LOGIC_VECTOR (15 downto 0);
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A_LAN : out STD_LOGIC_VECTOR (13 downto 0);
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OWN : out STD_LOGIC;
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SLAVE : out STD_LOGIC;
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CFOUT : out STD_LOGIC;
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CFIN : in STD_LOGIC;
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C1 : in STD_LOGIC;
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C3 : in STD_LOGIC;
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MTCR : in STD_LOGIC;
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OVR : out STD_LOGIC;
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BERR : in STD_LOGIC;
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MTACK : out STD_LOGIC;
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DS0 : in STD_LOGIC;
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DTACK : out STD_LOGIC;
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UDS : in STD_LOGIC;
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LDS : in STD_LOGIC;
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AS : in STD_LOGIC;
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RW : in STD_LOGIC;
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Z3 : in STD_LOGIC;
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DS1 : in STD_LOGIC;
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FCS : in STD_LOGIC;
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RESET : in STD_LOGIC;
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INT_OUT : out STD_LOGIC;
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AUTOBOOT_OFF : in STD_LOGIC;
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ROM_B : out STD_LOGIC_VECTOR (1 downto 0);
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ROM_OE : out STD_LOGIC;
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IDE_WAIT : in STD_LOGIC;
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CLK_EXT : in STD_LOGIC;
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IDE_W : out STD_LOGIC;
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IDE_R : out STD_LOGIC;
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IDE_A : out STD_LOGIC_VECTOR (2 downto 0);
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IDE_CS : out STD_LOGIC_VECTOR (1 downto 0);
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LAN_CFG : out STD_LOGIC_VECTOR (4 downto 1);
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LAN_RD : out STD_LOGIC;
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LAN_CS : out STD_LOGIC;
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LAN_WRH : out STD_LOGIC;
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LAN_WRL : out STD_LOGIC;
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LAN_INT : in STD_LOGIC;
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CP_RD : out STD_LOGIC;
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CP_WE : out STD_LOGIC;
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CP_CS : out STD_LOGIC;
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CP_IRQ : in STD_LOGIC);
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end LAN_IDE_CP;
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architecture Behavioral of LAN_IDE_CP is
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TYPE lan_reset IS (
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nop,
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wait0,
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clr,
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clr_commit,
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wait1,
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set,
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set_commit,
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done
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);
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TYPE lan_bus_sm IS (
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nop,
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start_read_upper,
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wait_read_upper,
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end_read_upper,
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start_read_lower,
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wait_read_lower,
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end_read_lower,
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start_write_upper,
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wait_write_upper,
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end_write_upper,
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start_write_lower,
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wait_write_lower,
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end_write_lower
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);
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SIGNAL LAN_RST_SM: lan_reset :=nop;
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SIGNAL LAN_SM: lan_bus_sm :=nop;
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SIGNAL AUTOCONFIG_ACCESS: STD_LOGIC;
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SIGNAL LAN_ACCESS: STD_LOGIC;
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SIGNAL DQ_SWAP: STD_LOGIC;
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signal D_OUT:STD_LOGIC_VECTOR(7 downto 0):=x"FF";
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signal AUTO_CONFIG_DONE:STD_LOGIC;
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signal AUTO_CONFIG_DONE_CYCLE:STD_LOGIC;
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signal SHUT_UP:STD_LOGIC;
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signal LAN_BASEADR:STD_LOGIC_VECTOR(15 downto 0);
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signal LAN_INT_ENABLE: std_logic;
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signal DECODE_RESET: std_logic;
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signal LAN_RD_S: std_logic;
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signal LAN_WRH_S: std_logic;
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signal LAN_WRL_S: std_logic;
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signal LAN_READY: std_logic;
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signal CONFIG_READY: std_logic;
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signal LAN_IRQ_D0: std_logic;
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signal LAN_IRQ_OUT: std_logic;
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signal Z3_ADR:STD_LOGIC_VECTOR(15 downto 2);
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signal Z3_DATA_IN:STD_LOGIC_VECTOR(31 downto 0);
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signal Z3_DATA:STD_LOGIC_VECTOR(31 downto 0);
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signal DQ_DATA:STD_LOGIC_VECTOR(15 downto 0);
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signal Z3_DS:STD_LOGIC_VECTOR(3 downto 0);
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signal Z3_A_LOW:STD_LOGIC;
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signal LAN_SM_RST:STD_LOGIC;
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signal LAN_CS_RST: std_logic;
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signal LAN_WR_RST: std_logic;
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signal LAN_A_INIT:STD_LOGIC_VECTOR(13 downto 0) :="11"&x"FFF";
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signal LAN_D_INIT:STD_LOGIC_VECTOR(15 downto 0) := x"0000";
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constant LAN_A_CLRREG:STD_LOGIC_VECTOR(13 downto 0) :="11"&x"FF7";
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constant LAN_A_SETREG:STD_LOGIC_VECTOR(13 downto 0) :="11"&x"FB7";
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--constant LAN_D_SET:STD_LOGIC_VECTOR(15 downto 0) := "0000000100010000"; --33MHz
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--constant LAN_D_CLR:STD_LOGIC_VECTOR(15 downto 0) := "0000111000000000"; --33MHz
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constant LAN_D_SET:STD_LOGIC_VECTOR(15 downto 0) := "0000001000010010"; --25MHz
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constant LAN_D_CLR:STD_LOGIC_VECTOR(15 downto 0) := "0000110100000000"; --25MHz
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Function to_std_logic(X: in Boolean) return Std_Logic is
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variable ret : std_logic;
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begin
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if x then ret := '1'; else ret := '0'; end if;
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return ret;
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end to_std_logic;
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begin
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Z3_DATA_IN <= D(15 downto 0) & A(23 downto 8);
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DECODE_RESET <= BERR and reset;
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Z3_DS <= UDS & LDS & DS1 & DS0;
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clock_init: process(reset,CLK_EXT)
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begin
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if(reset='1')then
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--default values
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LAN_CS_RST<='0';
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LAN_WR_RST<='0';
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LAN_RST_SM<=nop;
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LAN_A_INIT<="11"&x"FFF";
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LAN_D_INIT<= x"0000";
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elsif(rising_edge(CLK_EXT))then --reset is low!
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case LAN_RST_SM is
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when nop=>
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LAN_CS_RST<='0';
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LAN_WR_RST<='0';
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LAN_RST_SM<=wait0;
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LAN_A_INIT <= LAN_A_CLRREG;
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LAN_D_INIT <= LAN_D_CLR;
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when wait0=>
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LAN_CS_RST<='1';
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LAN_WR_RST<='0';
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LAN_RST_SM<=clr;
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LAN_A_INIT <= LAN_A_CLRREG;
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LAN_D_INIT <= LAN_D_CLR;
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when clr=>
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LAN_CS_RST<='1';
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LAN_WR_RST<='1';
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LAN_RST_SM<=clr_commit;
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LAN_A_INIT <= LAN_A_CLRREG;
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LAN_D_INIT <= LAN_D_CLR;
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when clr_commit=>
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LAN_CS_RST<='1';
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LAN_WR_RST<='0';
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LAN_RST_SM<=wait1;
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LAN_A_INIT <= LAN_A_CLRREG;
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LAN_D_INIT <= LAN_D_CLR;
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when wait1=>
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LAN_CS_RST<='1';
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LAN_WR_RST<='0';
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LAN_RST_SM<=set;
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LAN_A_INIT <= LAN_A_SETREG;
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LAN_D_INIT <= LAN_D_SET;
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when set=>
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LAN_CS_RST<='1';
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LAN_WR_RST<='1';
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LAN_RST_SM<=set_commit;
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LAN_A_INIT <= LAN_A_SETREG;
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LAN_D_INIT <= LAN_D_SET;
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when set_commit=>
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LAN_CS_RST<='1';
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LAN_WR_RST<='0';
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LAN_RST_SM<=done;
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LAN_A_INIT <= LAN_A_SETREG;
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LAN_D_INIT <= LAN_D_SET;
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when done=>
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LAN_CS_RST<='0';
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LAN_WR_RST<='0';
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LAN_RST_SM<=done;
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LAN_A_INIT <= LAN_A_SETREG;
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LAN_D_INIT <= LAN_D_SET;
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end case;
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end if;
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end process clock_init;
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ADDRESS_DECODE: process(DECODE_RESET,FCS)
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begin
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if(DECODE_RESET ='0')then
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AUTOCONFIG_ACCESS <= '0';
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LAN_ACCESS <= '0';
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DQ_SWAP <= '1';
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Z3_ADR <= (others => '1');
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elsif(falling_edge(FCS))then
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Z3_ADR(15 downto 2) <= A(15 downto 2);-- latch the whole address for the whole cycle
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--use D(15 downto 8)& A(23 downto 16) = A(31 downto 16) for quick response
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--AUTOCONFIG_ACCESS
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if(Z3='1' and (D(15 downto 8)& A(23 downto 16)) = x"FF00" and AUTO_CONFIG_DONE = '0' and CFIN='0')then
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AUTOCONFIG_ACCESS <= '1';
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else
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AUTOCONFIG_ACCESS <= '0';
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end if;
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--lan base
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if(Z3='1' and (D(15 downto 8) & A(23 downto 16)) = LAN_BASEADR and SHUT_UP='0' )then
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if(A(14 downto 13)<"11")then
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DQ_SWAP <= '1';
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else
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DQ_SWAP <= '0';
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end if;
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LAN_ACCESS <= '1';
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else
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LAN_ACCESS <= '0';
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DQ_SWAP <= '1';
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end if;
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end if;
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end process ADDRESS_DECODE;
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--LAN interrupt enable
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lan_int_proc: process (CLK_EXT,reset)
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begin
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if(reset ='0') then
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LAN_INT_ENABLE <='0';
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LAN_IRQ_D0 <='1';
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LAN_IRQ_OUT <='1';
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CONFIG_READY <='0';
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elsif rising_edge(CLK_EXT) then
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LAN_IRQ_D0 <= LAN_INT;
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--set/deassert the LAN-interrupt bit
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if( LAN_INT ='1' --or --no interupt
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--(LAN_ACCESS = '1' and FCS ='0' and Z3_DS(3) ='0' and RW='0' and
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-- Z3_ADR(15)='1' and Z3_DATA_IN(30)='1') --deassert via bus controll
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)then
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LAN_IRQ_OUT <='1';
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elsif(
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(LAN_INT ='0' and LAN_IRQ_D0 = '1' ) --or --falling edge
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--(LAN_ACCESS = '1' and FCS ='0' and Z3_DS(3) ='0' and RW='0' and
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-- Z3_ADR(15)='1' and Z3_DATA_IN(30)='0' and LAN_INT_ENABLE ='1') --set via bus controll
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) then
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LAN_IRQ_OUT <='0';
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end if;
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--set int enable and config ready flogs
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if(LAN_ACCESS = '1' and FCS ='0' and RW='0' and Z3_ADR(15)='1') then --enable if a write to A15 occured
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if(Z3_DS(3) ='0')then
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LAN_INT_ENABLE <= Z3_DATA_IN(31); --this controlls the output bit
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elsif(Z3_DS(2) ='0')then
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LAN_INT_ENABLE <= Z3_DATA_IN(15); --this controlls the output bit
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end if;
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CONFIG_READY <='1';
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end if;
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end if;
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end process lan_int_proc;
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--clock this signal to avoid glitches due to short resets
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lan_rst_gen: process (CLK_EXT)
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begin
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if falling_edge(CLK_EXT) then
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if(FCS ='1' or reset = '0' or Z3_DS = "1111" or LAN_ACCESS = '0' or Z3_ADR(15) = '1' ) then
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LAN_SM_RST <='1';
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else
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LAN_SM_RST <='0';
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end if;
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end if;
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end process lan_rst_gen;
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--lan signal generation: all Signals are HIGH active!
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lan_rw_gen: process (CLK_EXT,LAN_SM_RST)
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begin
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if(LAN_SM_RST ='1' ) then
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LAN_SM <=nop;
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LAN_RD_S <= '0';
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LAN_WRH_S <= '0';
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LAN_WRL_S <= '0';
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Z3_A_LOW <= '1';
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LAN_READY <= '0';
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Z3_DATA(31 downto 0) <= x"FFFFFFFF";
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DQ_DATA(15 downto 0) <= x"FFFF";
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elsif rising_edge(CLK_EXT) then
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--default values
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LAN_RD_S <= '0';
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LAN_WRH_S <= '0';
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LAN_WRL_S <= '0';
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Z3_A_LOW <= '1';
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LAN_READY <= '0';
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case LAN_SM is
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when nop=>
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--cycle start!
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-- prepare the data for write
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-- this is a quite complex thing for a cpld
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-- so I have to move this out of the cycle start condition and prepare it for every loop
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if(Z3_DS(3 downto 2) < "11")then
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if(DQ_SWAP='0') then
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DQ_DATA(15 downto 0) <= Z3_DATA_IN(31 downto 16);
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else
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DQ_DATA(15 downto 0) <= Z3_DATA_IN(23 downto 16) & Z3_DATA_IN(31 downto 24);
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end if;
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--elsif(Z3_DS(3 downto 2) = "10")then
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-- DQ_DATA(15 downto 0) <= Z3_DATA_IN(23 downto 16) & Z3_DATA_IN(23 downto 16);
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--elsif(Z3_DS(3 downto 2) = "01")then
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-- DQ_DATA(15 downto 0) <= Z3_DATA_IN(31 downto 24) & Z3_DATA_IN(31 downto 24);
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else -- lower word!
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Z3_A_LOW <= '0';
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--if(Z3_DS(1 downto 0) < "11")then
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if(DQ_SWAP='0') then
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DQ_DATA(15 downto 0) <= Z3_DATA_IN(15 downto 0);
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else
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DQ_DATA(15 downto 0) <= Z3_DATA_IN( 7 downto 0) & Z3_DATA_IN(15 downto 8);
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end if;
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--elsif(Z3_DS(1 downto 0) = "10")then
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-- DQ_DATA(15 downto 0) <= Z3_DATA_IN( 7 downto 0) & Z3_DATA_IN( 7 downto 0);
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--elsif(Z3_DS(1 downto 0) = "01")then
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-- DQ_DATA(15 downto 0) <= Z3_DATA_IN(15 downto 8) & Z3_DATA_IN(15 downto 8);
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--else --"11"
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-- DQ_DATA(15 downto 0) <= Z3_DATA_IN(15 downto 0);
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--end if;
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end if;
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if(RW='1')then --read from MSB
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-- determine bushalf
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if(Z3_DS(3 downto 2) < "11")then
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LAN_SM <= wait_read_upper;
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LAN_RD_S <= '1';
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else
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LAN_RD_S <= '1';
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LAN_SM <= wait_read_lower;
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end if;
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else
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-- determine bushalf
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if(Z3_DS(3 downto 2) < "11")then
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LAN_SM <= start_write_upper;
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else
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LAN_SM <= start_write_lower;
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end if;
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end if;
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when start_read_upper=>
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LAN_RD_S <= '1';
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LAN_SM <= wait_read_upper;
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when wait_read_upper=>
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LAN_RD_S <= '1';
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LAN_SM<=end_read_upper;
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when end_read_upper=>
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--fetch data
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if(DQ_SWAP='0') then
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Z3_DATA(31 downto 16) <= DQ;
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else
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Z3_DATA(31 downto 16) <= DQ(7 downto 0) & DQ(15 downto 8);
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end if;
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if(Z3_DS(1 downto 0) = "11")then -- no lower half
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LAN_READY <='1';
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LAN_SM <= end_read_upper; -- stay here until cylce end
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else
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Z3_A_LOW <= '0';
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LAN_SM <= start_read_lower;
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end if;
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when start_read_lower=>
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Z3_A_LOW <= '0';
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LAN_RD_S <= '1';
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LAN_SM <= wait_read_lower;
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when wait_read_lower=>
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Z3_A_LOW <= '0';
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LAN_RD_S <= '1';
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LAN_READY <= '1';
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LAN_SM<=end_read_lower;
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when end_read_lower=>
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--fetch data
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if(DQ_SWAP='0') then
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Z3_DATA(15 downto 0) <= DQ;
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else
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Z3_DATA(15 downto 0) <= DQ(7 downto 0) & DQ(15 downto 8);
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end if;
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LAN_READY <='1';
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LAN_SM<=end_read_lower; -- stay here until cylce end
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when start_write_upper=>
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-- swapped DS3/DS2 here: ENC624 is little endian
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LAN_WRH_S <= not Z3_DS(2);
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LAN_WRL_S <= not Z3_DS(3);
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LAN_SM <= wait_write_upper;
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when wait_write_upper=>
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LAN_SM<=end_write_upper;
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when end_write_upper=>
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-- prepare the data for write
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--if(Z3_DS(1 downto 0) = "00")then
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if(DQ_SWAP='0') then
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DQ_DATA(15 downto 0) <= Z3_DATA_IN(15 downto 0);
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else
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DQ_DATA(15 downto 0) <= Z3_DATA_IN( 7 downto 0) & Z3_DATA_IN(15 downto 8);
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end if;
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--elsif(Z3_DS(1 downto 0) = "10")then
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-- DQ_DATA(15 downto 0) <= Z3_DATA_IN( 7 downto 0) & Z3_DATA_IN( 7 downto 0);
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--elsif(Z3_DS(1 downto 0) = "01")then
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-- DQ_DATA(15 downto 0) <= Z3_DATA_IN(15 downto 8) & Z3_DATA_IN(15 downto 8);
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--else --"11"
|
|
-- DQ_DATA(15 downto 0) <= Z3_DATA_IN(15 downto 0);
|
|
--end if;
|
|
|
|
if(Z3_DS(1 downto 0) = "11")then -- no lower half
|
|
LAN_READY <='1';
|
|
LAN_SM <= end_write_upper; -- stay here until cylce end
|
|
else
|
|
Z3_A_LOW <= '0';
|
|
LAN_SM <= start_write_lower;
|
|
end if;
|
|
when start_write_lower=>
|
|
Z3_A_LOW <= '0';
|
|
-- swapped DS0/DS1 here: ENC624 is little endian
|
|
LAN_WRH_S <= not Z3_DS(0);
|
|
LAN_WRL_S <= not Z3_DS(1);
|
|
LAN_SM <= wait_write_lower;
|
|
when wait_write_lower=>
|
|
Z3_A_LOW <= '0';
|
|
LAN_READY <='1';
|
|
LAN_SM<=end_write_lower;
|
|
when end_write_lower=>
|
|
LAN_READY <='1';
|
|
LAN_SM<=end_write_lower; -- stay here until cylce end
|
|
end case;
|
|
end if;
|
|
end process lan_rw_gen;
|
|
|
|
|
|
--AUTOCONFIG_ACCESS
|
|
AUTOCONFIG_ACCESS_proc: process (reset, CLK_EXT)
|
|
begin
|
|
if reset = '0' then
|
|
-- reset active ...
|
|
AUTO_CONFIG_DONE_CYCLE <='0';
|
|
D_OUT<=x"FF";
|
|
SHUT_UP <='1';
|
|
LAN_BASEADR<=x"FFFF";
|
|
AUTO_CONFIG_DONE <='0';
|
|
elsif rising_edge(CLK_EXT) then -- no reset, so wait for rising edge of the clock
|
|
--default value
|
|
D_OUT<=x"FF";
|
|
if(FCS='1')then
|
|
AUTO_CONFIG_DONE <= AUTO_CONFIG_DONE_CYCLE or not AUTOBOOT_OFF ;
|
|
elsif(AUTOCONFIG_ACCESS= '1' and Z3_DS(3)='0' ) then
|
|
case Z3_ADR(8 downto 2) is
|
|
when "0000000" => D_OUT <= "10000001" ; --Z3, No mem, no Rom, single, board, 64kb
|
|
when "1000000" => D_OUT <= "00010001" ; --Z3, No mem, no Rom, single, board, 64kb
|
|
when "0000001" => D_OUT <= "10000100" ; --ProductID: 7B->10000100
|
|
when "1000001" => D_OUT <= "01000100" ; --ProductID: 7B->10000100
|
|
when "0000010" => D_OUT <= "11101101" ; --Flags
|
|
when "1000010" => D_OUT <= "11011101" ; --Flags
|
|
when "0000100" => D_OUT <= "11110101" ; --Ventor ID 0/1
|
|
when "1000100" => D_OUT <= "01010101" ; --Ventor ID 0/1
|
|
when "0000101" => D_OUT <= "11100011" ; --Ventor ID 2/3 : $0A1C: A1K.org
|
|
when "1000101" => D_OUT <= "00110011" ; --Ventor ID 2/3 : $0A1C: A1K.org
|
|
when "0010001" =>
|
|
if(RW='0')then
|
|
LAN_BASEADR(15 downto 0) <= Z3_DATA_IN(31 downto 16); --Base address
|
|
SHUT_UP <='0'; --enable board
|
|
AUTO_CONFIG_DONE_CYCLE <= '1'; --done here
|
|
end if;
|
|
when "0010011" =>
|
|
if(RW='0')then
|
|
AUTO_CONFIG_DONE_CYCLE <= '1'; --done here
|
|
end if;
|
|
when others =>
|
|
--nothing
|
|
end case;
|
|
end if;
|
|
end if;
|
|
end process AUTOCONFIG_ACCESS_proc; --- that's all
|
|
|
|
LAN_CS <= LAN_ACCESS when reset='1' else LAN_CS_RST;
|
|
LAN_WRL <= LAN_WRL_S when FCS='0' and reset = '1' else LAN_WR_RST;
|
|
LAN_WRH <= LAN_WRH_S when FCS='0' and reset = '1' else LAN_WR_RST;
|
|
LAN_RD <= LAN_RD_S when FCS='0' and reset = '1' else '0';
|
|
LAN_CFG <= "ZZZZ";
|
|
|
|
|
|
A_LAN(13 downto 0)<= LAN_A_INIT when reset ='0' else
|
|
Z3_ADR(14 downto 2) & Z3_A_LOW;
|
|
|
|
--signal assignment
|
|
D(15 downto 0) <= Z3_DATA(31 downto 16) when RW='1' and Z3_DS <"1111" and FCS='0' and LAN_ACCESS ='1' else
|
|
D_OUT & x"FF" when RW='1' and Z3_DS <"1111" and FCS='0' and AUTOCONFIG_ACCESS ='1' else
|
|
(others => 'Z');
|
|
|
|
A(23 downto 8) <= Z3_DATA(15 downto 0) when RW='1' and Z3_DS <"1111" and FCS='0' and LAN_ACCESS ='1' else
|
|
(others => 'Z');
|
|
|
|
A(7 downto 1) <= (others => 'Z');
|
|
|
|
--defined lancp signal that matches both LAN and CP addresses
|
|
DQ <= LAN_D_INIT when reset='0' else
|
|
DQ_DATA(15 downto 0) when RW='0' and FCS='0' and Z3_DS <"1111" and LAN_ACCESS ='1' else
|
|
(others => 'Z');
|
|
|
|
INT_OUT <= '0' when LAN_IRQ_OUT = '0' and LAN_INT_ENABLE = '1' else
|
|
'Z';
|
|
|
|
OWN <= 'Z';
|
|
SLAVE <= '0' when FCS='0' and (AUTOCONFIG_ACCESS = '1' or LAN_ACCESS = '1') else '1';
|
|
CFOUT <= '0' when AUTO_CONFIG_DONE='1' else '1';
|
|
|
|
OVR <= '0' when FCS='0' and (AUTOCONFIG_ACCESS = '1' or LAN_ACCESS = '1') else 'Z'; --is Cache inhibit ob Z3!
|
|
|
|
DTACK <= '0' when FCS='0' and (LAN_READY = '1' or AUTOCONFIG_ACCESS ='1' or CONFIG_READY='1') else 'Z';
|
|
|
|
MTACK <= 'Z';
|
|
|
|
|
|
--for the future
|
|
CP_WE <= '1';
|
|
CP_RD <= '1';
|
|
CP_CS <= '1';
|
|
IDE_W <= '1';
|
|
IDE_R <= '1';
|
|
IDE_CS(0)<= '1';
|
|
IDE_CS(1)<= '1';
|
|
IDE_A(2 downto 0) <= "111";
|
|
ROM_B <= "11";
|
|
ROM_OE <= '1';
|
|
|
|
|
|
end Behavioral;
|
|
|