2279 lines
116 KiB
Plaintext
2279 lines
116 KiB
Plaintext
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cpldfit: version P.20131013 Xilinx Inc.
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Fitter Report
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Design Name: LAN_IDE_CP Date: 12-18-2018, 11:58AM
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Device Used: XC95288XL-10-TQ144
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Fitting Status: Successful
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************************* Mapped Resource Summary **************************
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Macrocells Product Terms Function Block Registers Pins
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Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot
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203/288 ( 70%) 540 /1440 ( 37%) 399/864 ( 46%) 114/288 ( 40%) 109/117 ( 93%)
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** Function Block Resources **
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Function Mcells FB Inps Pterms IO
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Block Used/Tot Used/Tot Used/Tot Used/Tot
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FB1 8/18 4/54 4/90 8/ 8*
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FB2 18/18* 32/54 35/90 10/10*
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FB3 3/18 38/54 37/90 3/ 5
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FB4 18/18* 22/54 34/90 6/ 6*
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FB5 16/18 40/54 41/90 7/ 8
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FB6 7/18 7/54 6/90 8/ 8*
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FB7 3/18 8/54 9/90 4/ 4*
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FB8 13/18 24/54 23/90 5/ 5*
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FB9 18/18* 38/54 54/90 8/ 9
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FB10 18/18* 28/54 50/90 10/10*
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FB11 18/18* 39/54 55/90 7/ 7*
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FB12 5/18 8/54 10/90 6/ 6*
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FB13 18/18* 39/54 55/90 6/ 6*
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FB14 4/18 6/54 5/90 5/ 8
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FB15 18/18* 39/54 53/90 8/ 9
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FB16 18/18* 27/54 69/90 8/ 8*
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----- ----- ----- -----
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203/288 399/864 540/1440 109/117
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* - Resource is exhausted
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** Global Control Resources **
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Signal 'CLK_EXT' mapped onto global clock net GCK1.
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Global output enable net(s) unused.
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Global set/reset net(s) unused.
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** Pin Resources **
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Signal Type Required Mapped | Pin Type Used Total
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------------------------------------|------------------------------------
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Input : 18 18 | I/O : 102 109
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Output : 42 42 | GCK/IO : 2 3
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Bidirectional : 48 48 | GTS/IO : 4 4
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GCK : 1 1 | GSR/IO : 1 1
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GTS : 0 0 |
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GSR : 0 0 |
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---- ----
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Total 109 109
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** Power Data **
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There are 203 macrocells in high performance mode (MCHP).
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There are 0 macrocells in low power mode (MCLP).
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End of Mapped Resource Summary
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************************** Errors and Warnings ***************************
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WARNING:Cpld - Unable to retrieve the path to the iSE Project Repository. Will
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use the default filename of 'LAN_IDE_CP.ise'.
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INFO:Cpld - Inferring BUFG constraint for signal 'CLK_EXT' based upon the LOC
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constraint 'P30'. It is recommended that you declare this BUFG explicitedly
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in your design. Note that for certain device families the output of a BUFG
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constraint can not drive a gated clock, and the BUFG constraint will be
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ignored.
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WARNING:Cpld:1007 - Removing unused input(s) 'A<1>'. The input(s) are unused
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after optimization. Please verify functionality via simulation.
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WARNING:Cpld:1007 - Removing unused input(s) 'AS'. The input(s) are unused
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after optimization. Please verify functionality via simulation.
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WARNING:Cpld:1007 - Removing unused input(s) 'C1'. The input(s) are unused
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after optimization. Please verify functionality via simulation.
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WARNING:Cpld:1007 - Removing unused input(s) 'C3'. The input(s) are unused
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after optimization. Please verify functionality via simulation.
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WARNING:Cpld:1007 - Removing unused input(s) 'CP_IRQ'. The input(s) are unused
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after optimization. Please verify functionality via simulation.
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WARNING:Cpld:1007 - Removing unused input(s) 'IDE_WAIT'. The input(s) are
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unused after optimization. Please verify functionality via simulation.
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WARNING:Cpld:1007 - Removing unused input(s) 'MTCR'. The input(s) are unused
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after optimization. Please verify functionality via simulation.
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************************* Summary of Mapped Logic ************************
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** 90 Outputs **
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Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init
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Name Pts Inps No. Type Use Mode Rate State
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D<5> 2 3 FB1_5 20 I/O I/O STD FAST
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D<4> 2 3 FB1_6 21 I/O I/O STD FAST
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IDE_CS<0> 0 0 FB1_8 22 I/O O STD FAST
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IDE_CS<1> 0 0 FB1_10 23 I/O O STD FAST
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IDE_A<0> 0 0 FB1_12 24 I/O O STD FAST
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IDE_A<2> 0 0 FB1_14 25 I/O O STD FAST
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IDE_A<1> 0 0 FB1_15 26 I/O O STD FAST
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IDE_R 0 0 FB1_17 27 I/O O STD FAST
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A_LAN<4> 1 2 FB2_2 9 I/O O STD FAST
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A_LAN<7> 1 2 FB2_3 10 I/O O STD FAST
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A_LAN<6> 2 3 FB2_5 11 I/O O STD FAST
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LAN_CFG<1> 0 0 FB2_6 12 I/O O STD FAST
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LAN_CFG<3> 0 0 FB2_8 13 I/O O STD FAST
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D<6> 2 3 FB2_10 14 I/O I/O STD FAST
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D<3> 2 3 FB2_12 15 I/O I/O STD FAST
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D<7> 2 3 FB2_14 16 I/O I/O STD FAST
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D<1> 2 3 FB2_15 17 I/O I/O STD FAST
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D<8> 3 4 FB2_17 19 I/O I/O STD FAST
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IDE_W 0 0 FB3_2 28 I/O O STD FAST
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INT_OUT 1 2 FB3_14 32 GCK/I/O O STD FAST
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D<0> 2 3 FB4_2 2 GTS/I/O I/O STD FAST
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A_LAN<1> 1 2 FB4_5 3 GTS/I/O O STD FAST
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A_LAN<0> 1 2 FB4_6 4 I/O O STD FAST
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A_LAN<3> 2 3 FB4_8 5 GTS/I/O O STD FAST
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A_LAN<2> 1 2 FB4_12 6 GTS/I/O O STD FAST
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A_LAN<5> 1 2 FB4_14 7 I/O O STD FAST
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CP_CS 0 0 FB5_2 34 I/O O STD FAST
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ROM_OE 0 0 FB5_5 35 I/O O STD FAST
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D<2> 2 3 FB5_10 39 I/O I/O STD FAST
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D<9> 3 4 FB5_12 40 I/O I/O STD FAST
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D<10> 3 4 FB5_14 41 I/O I/O STD FAST
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D<11> 3 4 FB5_15 43 I/O I/O STD FAST
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D<12> 3 4 FB5_17 44 I/O I/O STD FAST
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LAN_CFG<2> 0 0 FB6_2 135 I/O O STD FAST
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A_LAN<12> 1 2 FB6_3 136 I/O O STD FAST
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A_LAN<13> 1 2 FB6_5 137 I/O O STD FAST
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A_LAN<10> 1 2 FB6_6 138 I/O O STD FAST
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A_LAN<11> 1 2 FB6_8 139 I/O O STD FAST
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A_LAN<8> 1 2 FB6_10 140 I/O O STD FAST
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A_LAN<9> 1 2 FB6_14 142 I/O O STD FAST
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Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init
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Name Pts Inps No. Type Use Mode Rate State
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D<13> 3 4 FB7_3 45 I/O I/O STD FAST
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D<14> 3 4 FB7_5 46 I/O I/O STD FAST
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D<15> 3 4 FB7_12 48 I/O I/O STD FAST
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DQ<12> 2 3 FB8_2 130 I/O I/O STD FAST
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DQ<14> 2 3 FB8_3 131 I/O I/O STD FAST
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LAN_WRH 2 3 FB8_5 132 I/O O STD FAST
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LAN_CS 2 3 FB8_8 133 I/O O STD FAST
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LAN_RD 1 2 FB8_10 134 I/O O STD FAST
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A<8> 4 9 FB9_11 56 I/O I/O STD FAST RESET
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A<9> 4 9 FB9_14 58 I/O I/O STD FAST RESET
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A<10> 4 9 FB9_17 59 I/O I/O STD FAST RESET
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DQ<1> 3 4 FB10_2 117 I/O I/O STD FAST
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DQ<0> 2 3 FB10_3 118 I/O I/O STD FAST
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DQ<3> 2 3 FB10_5 119 I/O I/O STD FAST
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DQ<2> 2 3 FB10_6 120 I/O I/O STD FAST
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DQ<5> 2 3 FB10_8 121 I/O I/O STD FAST
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DQ<4> 3 4 FB10_10 124 I/O I/O STD FAST
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DQ<7> 2 3 FB10_11 125 I/O I/O STD FAST
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DQ<6> 2 3 FB10_12 126 I/O I/O STD FAST
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DQ<8> 3 4 FB10_14 128 I/O I/O STD FAST
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DQ<10> 3 4 FB10_17 129 I/O I/O STD FAST
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A<11> 4 9 FB11_3 60 I/O I/O STD FAST RESET
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A<12> 4 9 FB11_5 61 I/O I/O STD FAST RESET
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A<13> 4 9 FB11_10 64 I/O I/O STD FAST RESET
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A<14> 4 9 FB11_11 66 I/O I/O STD FAST RESET
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ROM_B<0> 0 0 FB11_12 68 I/O O STD FAST
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ROM_B<1> 0 0 FB11_14 69 I/O O STD FAST
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CP_WE 0 0 FB11_17 70 I/O O STD FAST
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LAN_CFG<4> 0 0 FB12_2 110 I/O O STD FAST
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DQ<15> 2 3 FB12_5 112 I/O I/O STD FAST
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DQ<13> 2 3 FB12_8 113 I/O I/O STD FAST
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DQ<11> 3 4 FB12_10 115 I/O I/O STD FAST
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DQ<9> 3 4 FB12_12 116 I/O I/O STD FAST
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CP_RD 0 0 FB13_2 71 I/O O STD FAST
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A<15> 4 9 FB13_8 74 I/O I/O STD FAST RESET
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LAN_WRL 2 3 FB13_14 76 I/O O STD FAST
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OVR 0 0 FB14_3 100 I/O O STD FAST
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CFOUT 3 4 FB14_11 105 I/O O STD FAST SET
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SLAVE 2 3 FB14_14 106 I/O O STD FAST
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OWN 0 0 FB14_15 107 I/O O STD FAST
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Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init
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Name Pts Inps No. Type Use Mode Rate State
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DTACK 1 1 FB15_12 85 I/O O STD FAST
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A<23> 4 9 FB15_14 86 I/O I/O STD FAST RESET
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A<22> 4 9 FB15_15 87 I/O I/O STD FAST RESET
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A<21> 4 9 FB15_17 88 I/O I/O STD FAST RESET
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A<20> 4 9 FB16_2 91 I/O I/O STD FAST RESET
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A<19> 4 9 FB16_3 92 I/O I/O STD FAST RESET
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A<18> 4 9 FB16_6 94 I/O I/O STD FAST RESET
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A<17> 4 9 FB16_8 95 I/O I/O STD FAST RESET
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MTACK 0 0 FB16_10 96 I/O O STD FAST
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A<16> 4 9 FB16_11 97 I/O I/O STD FAST RESET
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** 113 Buried Nodes **
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Signal Total Total Loc Pwr Reg Init
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Name Pts Inps Mode State
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LAN_SM_RST 1 2 FB2_1 STD RESET
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$OpTx$FX_DC$32 1 3 FB2_4 STD
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D_OUT<7> 2 8 FB2_7 STD SET
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D_OUT<3> 2 7 FB2_9 STD SET
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D_OUT<0> 2 9 FB2_11 STD SET
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D_9_IOBUFE/D_9_IOBUFE_TRST 2 4 FB2_13 STD
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DQ_9_IOBUFE/DQ_9_IOBUFE_TRST 2 4 FB2_16 STD
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LAN_SM_FSM_FFd3 8 12 FB2_18 STD RESET
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LAN_ACCESS 36 36 FB3_11 STD RESET
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LAN_A_INIT<3> 1 1 FB4_1 STD SET
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$OpTx$FX_DC$35 1 2 FB4_3 STD
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LAN_WR_RST 2 3 FB4_4 STD RESET
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LAN_D_INIT<8> 2 2 FB4_7 STD RESET
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LAN_D_INIT<1> 2 2 FB4_9 STD RESET
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LAN_CS_RST 2 3 FB4_10 STD RESET
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LAN_A_INIT<6> 2 2 FB4_11 STD SET
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DQ_SWAP$BUF7/DQ_SWAP$BUF7_TRST 2 4 FB4_13 STD
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Z3_ADR<9> 3 3 FB4_15 STD RESET
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Z3_ADR<8> 3 3 FB4_16 STD RESET
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Z3_ADR<7> 3 3 FB4_17 STD RESET
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Z3_ADR<6> 3 3 FB4_18 STD RESET
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Z3_ADR<5> 3 3 FB5_4 STD RESET
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Z3_ADR<4> 3 3 FB5_6 STD RESET
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Z3_ADR<3> 3 3 FB5_7 STD RESET
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Z3_ADR<2> 3 3 FB5_8 STD RESET
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Z3_ADR<13> 3 3 FB5_9 STD RESET
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Z3_ADR<12> 3 3 FB5_11 STD RESET
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Z3_ADR<11> 3 3 FB5_13 STD RESET
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Z3_ADR<10> 3 3 FB5_16 STD RESET
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AUTOCONFIG_ACCESS 3 21 FB5_18 STD RESET
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Z3_ADR_1/Z3_ADR_1_SETF 1 2 FB8_11 STD
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$OpTx$FX_DC$8 1 2 FB8_12 STD
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$OpTx$FX_DC$33 1 3 FB8_13 STD
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$OpTx$FX_DC$25 1 2 FB8_14 STD
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$OpTx$FX_DC$9 2 3 FB8_15 STD
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$OpTx$FX_DC$29 2 3 FB8_16 STD
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Z3_ADR_1 3 3 FB8_17 STD RESET
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Z3_ADR_0 3 3 FB8_18 STD RESET
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SHUT_UP 2 3 FB9_1 STD RESET
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LAN_RST_SM_FSM_FFd1 2 4 FB9_2 STD RESET
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Signal Total Total Loc Pwr Reg Init
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Name Pts Inps Mode State
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LAN_IRQ_D0 2 2 FB9_3 STD RESET
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CONFIG_READY 2 3 FB9_4 STD RESET
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LAN_RST_SM_FSM_FFd3 3 3 FB9_5 STD RESET
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LAN_RST_SM_FSM_FFd2 3 4 FB9_6 STD RESET
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LAN_INT_ENABLE 3 4 FB9_7 STD RESET
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LAN_BASEADR<6> 3 4 FB9_8 STD RESET
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LAN_BASEADR<5> 3 4 FB9_9 STD RESET
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LAN_BASEADR<4> 3 4 FB9_10 STD RESET
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LAN_BASEADR<3> 3 4 FB9_12 STD RESET
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LAN_BASEADR<2> 3 4 FB9_13 STD RESET
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LAN_BASEADR<1> 3 4 FB9_15 STD RESET
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LAN_BASEADR<15> 3 4 FB9_16 STD RESET
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LAN_IRQ_OUT 4 7 FB9_18 STD RESET
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$OpTx$FX_DC$19 1 10 FB10_1 STD
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AUTO_CONFIG_DONE_CYCLE 2 11 FB10_4 STD RESET
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D_OUT<2> 3 9 FB10_7 STD SET
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LAN_BASEADR<14> 4 14 FB10_9 STD RESET
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D_OUT<6> 4 10 FB10_13 STD SET
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D_OUT<5> 4 10 FB10_15 STD SET
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D_OUT<4> 4 10 FB10_16 STD SET
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D_OUT<1> 4 9 FB10_18 STD SET
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$OpTx$FX_SC$28 2 5 FB11_1 STD
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Z3_DATA<31> 3 6 FB11_2 STD RESET
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Z3_DATA<30> 3 6 FB11_4 STD RESET
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LAN_SM_FSM_FFd1 3 5 FB11_6 STD RESET
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DQ_DATA<2> 4 10 FB11_7 STD RESET
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DQ_DATA<1> 4 10 FB11_8 STD RESET
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DQ_DATA<15> 4 10 FB11_9 STD RESET
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DQ_DATA<14> 4 10 FB11_13 STD RESET
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DQ_DATA<13> 4 10 FB11_15 STD RESET
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DQ_DATA<12> 4 10 FB11_16 STD RESET
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DQ_DATA<11> 4 10 FB11_18 STD RESET
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Z3_DATA<29> 3 6 FB13_1 STD RESET
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Z3_DATA<23> 3 6 FB13_3 STD RESET
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Z3_DATA<22> 3 6 FB13_4 STD RESET
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Z3_DATA<21> 3 6 FB13_5 STD RESET
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Z3_DATA<20> 3 6 FB13_6 STD RESET
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Z3_DATA<19> 3 6 FB13_7 STD RESET
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Z3_DATA<18> 3 6 FB13_9 STD RESET
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Z3_DATA<17> 3 6 FB13_10 STD RESET
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Signal Total Total Loc Pwr Reg Init
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Name Pts Inps Mode State
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Z3_DATA<16> 3 6 FB13_11 STD RESET
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LAN_WRL_S 3 7 FB13_12 STD RESET
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LAN_WRH_S 3 7 FB13_13 STD RESET
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DQ_DATA<6> 4 10 FB13_15 STD RESET
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DQ_DATA<5> 4 10 FB13_16 STD RESET
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DQ_DATA<4> 4 10 FB13_17 STD RESET
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DQ_DATA<3> 4 10 FB13_18 STD RESET
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Z3_DATA<30>/Z3_DATA<30>_CE 1 4 FB15_1 STD
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Z3_DATA<10>/Z3_DATA<10>_CE 1 4 FB15_2 STD
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$OpTx$FX_DC$22 2 4 FB15_3 STD
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LAN_BASEADR<9> 3 4 FB15_4 STD RESET
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LAN_BASEADR<8> 3 4 FB15_5 STD RESET
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LAN_BASEADR<7> 3 4 FB15_6 STD RESET
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LAN_BASEADR<13> 3 4 FB15_7 STD RESET
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LAN_BASEADR<12> 3 4 FB15_8 STD RESET
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LAN_BASEADR<11> 3 4 FB15_9 STD RESET
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LAN_BASEADR<10> 3 4 FB15_10 STD RESET
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LAN_BASEADR<0> 3 4 FB15_11 STD RESET
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DQ_DATA<9> 4 10 FB15_13 STD RESET
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DQ_DATA<8> 4 10 FB15_16 STD RESET
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DQ_DATA<7> 4 10 FB15_18 STD RESET
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Z3_DATA<28> 3 6 FB16_1 STD RESET
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Z3_DATA<27> 3 6 FB16_4 STD RESET
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Z3_DATA<26> 3 6 FB16_5 STD RESET
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Z3_DATA<25> 3 6 FB16_7 STD RESET
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Z3_DATA<24> 3 6 FB16_9 STD RESET
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LAN_RD_S 4 8 FB16_12 STD RESET
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DQ_DATA<10> 4 10 FB16_13 STD RESET
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DQ_DATA<0> 4 10 FB16_14 STD RESET
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LAN_SM_FSM_FFd2 5 9 FB16_15 STD RESET
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LAN_READY 5 7 FB16_16 STD RESET
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Z3_A_LOW 6 11 FB16_17 STD RESET
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LAN_SM_FSM_FFd4 6 10 FB16_18 STD RESET
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** 19 Inputs **
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Signal Loc Pin Pin Pin
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Name No. Type Use
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CLK_EXT FB3_10 30 GCK/I/O GCK
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RESET FB6_15 143 GSR/I/O I
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A<5> FB7_15 49 I/O I
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A<4> FB9_2 50 I/O I
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A<6> FB9_3 51 I/O I
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A<3> FB9_5 52 I/O I
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A<7> FB9_6 53 I/O I
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A<2> FB9_8 54 I/O I
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LAN_INT FB12_3 111 I/O I
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AUTOBOOT_OFF FB13_11 75 I/O I
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FCS FB13_15 77 I/O I
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DS1 FB13_17 78 I/O I
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CFIN FB14_10 104 I/O I
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Z3 FB15_2 79 I/O I
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UDS FB15_8 81 I/O I
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LDS FB15_10 82 I/O I
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RW FB15_11 83 I/O I
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DS0 FB16_5 93 I/O I
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BERR FB16_12 98 I/O I
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Legend:
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Pin No. - ~ - User Assigned
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************************** Function Block Details ************************
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Legend:
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Total Pt - Total product terms used by the macrocell signal
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Imp Pt - Product terms imported from other macrocells
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Exp Pt - Product terms exported to other macrocells
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in direction shown
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Unused Pt - Unused local product terms remaining in macrocell
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Loc - Location where logic was mapped in device
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Pin Type/Use - I - Input GCK - Global Clock
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O - Output GTS - Global Output Enable
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(b) - Buried macrocell GSR - Global Set/Reset
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X - Signal used as input to the macrocell logic.
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Pin No. - ~ - User Assigned
|
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*********************************** FB1 ***********************************
|
|
Number of function block inputs used/remaining: 4/50
|
|
Number of signals used by logic mapping into function block: 4
|
|
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
|
Name Pt Pt Pt Pt # Type Use
|
|
(unused) 0 0 0 5 FB1_1 (b)
|
|
(unused) 0 0 0 5 FB1_2 (b)
|
|
(unused) 0 0 0 5 FB1_3 (b)
|
|
(unused) 0 0 0 5 FB1_4 (b)
|
|
D<5> 2 0 0 3 FB1_5 20 I/O I/O
|
|
D<4> 2 0 0 3 FB1_6 21 I/O I/O
|
|
(unused) 0 0 0 5 FB1_7 (b)
|
|
IDE_CS<0> 0 0 0 5 FB1_8 22 I/O O
|
|
(unused) 0 0 0 5 FB1_9 (b)
|
|
IDE_CS<1> 0 0 0 5 FB1_10 23 I/O O
|
|
(unused) 0 0 0 5 FB1_11 (b)
|
|
IDE_A<0> 0 0 0 5 FB1_12 24 I/O O
|
|
(unused) 0 0 0 5 FB1_13 (b)
|
|
IDE_A<2> 0 0 0 5 FB1_14 25 I/O O
|
|
IDE_A<1> 0 0 0 5 FB1_15 26 I/O O
|
|
(unused) 0 0 0 5 FB1_16 (b)
|
|
IDE_R 0 0 0 5 FB1_17 27 I/O O
|
|
(unused) 0 0 0 5 FB1_18 (b)
|
|
|
|
Signals Used by Logic in Function Block
|
|
1: $OpTx$FX_DC$32 3: Z3_DATA<20> 4: Z3_DATA<21>
|
|
2: D_9_IOBUFE/D_9_IOBUFE_TRST
|
|
|
|
Signal 1 2 3 4 FB
|
|
Name 0----+----0----+----0----+----0----+----0 Inputs
|
|
D<5> XX.X.................................... 3
|
|
D<4> XXX..................................... 3
|
|
IDE_CS<0> ........................................ 0
|
|
IDE_CS<1> ........................................ 0
|
|
IDE_A<0> ........................................ 0
|
|
IDE_A<2> ........................................ 0
|
|
IDE_A<1> ........................................ 0
|
|
IDE_R ........................................ 0
|
|
0----+----1----+----2----+----3----+----4
|
|
0 0 0 0
|
|
*********************************** FB2 ***********************************
|
|
Number of function block inputs used/remaining: 32/22
|
|
Number of signals used by logic mapping into function block: 32
|
|
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
|
Name Pt Pt Pt Pt # Type Use
|
|
LAN_SM_RST 1 0 /\1 3 FB2_1 (b) (b)
|
|
A_LAN<4> 1 0 0 4 FB2_2 9 I/O O
|
|
A_LAN<7> 1 0 0 4 FB2_3 10 I/O O
|
|
$OpTx$FX_DC$32 1 0 0 4 FB2_4 (b) (b)
|
|
A_LAN<6> 2 0 0 3 FB2_5 11 I/O O
|
|
LAN_CFG<1> 0 0 0 5 FB2_6 12 I/O O
|
|
D_OUT<7> 2 0 0 3 FB2_7 (b) (b)
|
|
LAN_CFG<3> 0 0 0 5 FB2_8 13 I/O O
|
|
D_OUT<3> 2 0 0 3 FB2_9 (b) (b)
|
|
D<6> 2 0 0 3 FB2_10 14 I/O I/O
|
|
D_OUT<0> 2 0 0 3 FB2_11 (b) (b)
|
|
D<3> 2 0 0 3 FB2_12 15 I/O I/O
|
|
D_9_IOBUFE/D_9_IOBUFE_TRST
|
|
2 0 0 3 FB2_13 (b) (b)
|
|
D<7> 2 0 0 3 FB2_14 16 I/O I/O
|
|
D<1> 2 0 0 3 FB2_15 17 I/O I/O
|
|
DQ_9_IOBUFE/DQ_9_IOBUFE_TRST
|
|
2 0 0 3 FB2_16 (b) (b)
|
|
D<8> 3 0 \/2 0 FB2_17 19 I/O I/O
|
|
LAN_SM_FSM_FFd3 8 3<- 0 0 FB2_18 (b) (b)
|
|
|
|
Signals Used by Logic in Function Block
|
|
1: $OpTx$FX_DC$25 12: LAN_SM_FSM_FFd2 23: Z3_ADR<6>
|
|
2: $OpTx$FX_DC$29 13: LAN_SM_FSM_FFd3 24: Z3_ADR_0
|
|
3: $OpTx$FX_DC$32 14: LAN_SM_FSM_FFd4 25: Z3_ADR_1
|
|
4: $OpTx$FX_DC$8 15: LAN_SM_RST 26: Z3_DATA<10>/Z3_DATA<10>_CE
|
|
5: $OpTx$FX_DC$9 16: RESET 27: Z3_DATA<17>
|
|
6: AUTOCONFIG_ACCESS 17: RW 28: Z3_DATA<19>
|
|
7: D_9_IOBUFE/D_9_IOBUFE_TRST 18: Z3_ADR<13> 29: Z3_DATA<22>
|
|
8: D_OUT<0> 19: Z3_ADR<2> 30: Z3_DATA<23>
|
|
9: LAN_ACCESS 20: Z3_ADR<3> 31: Z3_DATA<24>
|
|
10: LAN_A_INIT<6> 21: Z3_ADR<4> 32: Z3_DATA<30>/Z3_DATA<30>_CE
|
|
11: LAN_SM_FSM_FFd1 22: Z3_ADR<5>
|
|
|
|
Signal 1 2 3 4 FB
|
|
Name 0----+----0----+----0----+----0----+----0 Inputs
|
|
LAN_SM_RST ....X..........X........................ 2
|
|
A_LAN<4> ...............X...X.................... 2
|
|
A_LAN<7> ...............X......X................. 2
|
|
$OpTx$FX_DC$32 ....X...X.......X....................... 3
|
|
A_LAN<6> .........X.....X.....X.................. 3
|
|
LAN_CFG<1> ........................................ 0
|
|
D_OUT<7> ....XX.........X...XXXX.X............... 8
|
|
LAN_CFG<3> ........................................ 0
|
|
D_OUT<3> ....XX.........X...XXX..X............... 7
|
|
D<6> ..X...X.....................X........... 3
|
|
D_OUT<0> ....XX.........X..XXXX.XX............... 9
|
|
D<3> ..X...X....................X............ 3
|
|
D_9_IOBUFE/D_9_IOBUFE_TRST
|
|
..X.XX..........X....................... 4
|
|
D<7> ..X...X......................X.......... 3
|
|
D<1> ..X...X...................X............. 3
|
|
DQ_9_IOBUFE/DQ_9_IOBUFE_TRST
|
|
..X.X...X......X........................ 4
|
|
D<8> ..X...XX......................X......... 4
|
|
LAN_SM_FSM_FFd3 XX.X......XXXXX.XX.......X.....X........ 12
|
|
0----+----1----+----2----+----3----+----4
|
|
0 0 0 0
|
|
*********************************** FB3 ***********************************
|
|
Number of function block inputs used/remaining: 38/16
|
|
Number of signals used by logic mapping into function block: 38
|
|
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
|
Name Pt Pt Pt Pt # Type Use
|
|
(unused) 0 0 0 5 FB3_1 (b)
|
|
IDE_W 0 0 0 5 FB3_2 28 I/O O
|
|
(unused) 0 0 0 5 FB3_3 (b)
|
|
(unused) 0 0 0 5 FB3_4 (b)
|
|
(unused) 0 0 0 5 FB3_5 (b)
|
|
(unused) 0 0 0 5 FB3_6 (b)
|
|
(unused) 0 0 \/2 3 FB3_7 (b) (b)
|
|
(unused) 0 0 \/5 0 FB3_8 (b) (b)
|
|
(unused) 0 0 \/5 0 FB3_9 (b) (b)
|
|
(unused) 0 0 \/5 0 FB3_10 30 GCK/I/O GCK
|
|
LAN_ACCESS 36 31<- 0 0 FB3_11 (b) (b)
|
|
(unused) 0 0 /\5 0 FB3_12 31 I/O (b)
|
|
(unused) 0 0 /\5 0 FB3_13 (b) (b)
|
|
INT_OUT 1 0 /\4 0 FB3_14 32 GCK/I/O O
|
|
(unused) 0 0 0 5 FB3_15 33 I/O
|
|
(unused) 0 0 0 5 FB3_16 (b)
|
|
(unused) 0 0 0 5 FB3_17 (b)
|
|
(unused) 0 0 0 5 FB3_18 (b)
|
|
|
|
Signals Used by Logic in Function Block
|
|
1: FCS 14: LAN_BASEADR<6> 27: D<12>.PIN
|
|
2: LAN_BASEADR<0> 15: LAN_BASEADR<7> 28: D<11>.PIN
|
|
3: LAN_BASEADR<10> 16: LAN_BASEADR<8> 29: D<10>.PIN
|
|
4: LAN_BASEADR<11> 17: LAN_BASEADR<9> 30: D<9>.PIN
|
|
5: LAN_BASEADR<12> 18: LAN_INT_ENABLE 31: D<8>.PIN
|
|
6: LAN_BASEADR<13> 19: LAN_IRQ_OUT 32: A<20>.PIN
|
|
7: LAN_BASEADR<14> 20: A<17>.PIN 33: A<21>.PIN
|
|
8: LAN_BASEADR<15> 21: A<23>.PIN 34: A<16>.PIN
|
|
9: LAN_BASEADR<1> 22: A<18>.PIN 35: A<22>.PIN
|
|
10: LAN_BASEADR<2> 23: A<19>.PIN 36: SHUT_UP
|
|
11: LAN_BASEADR<3> 24: D<15>.PIN 37: Z3_ADR_1/Z3_ADR_1_SETF
|
|
12: LAN_BASEADR<4> 25: D<14>.PIN 38: Z3
|
|
13: LAN_BASEADR<5> 26: D<13>.PIN
|
|
|
|
Signal 1 2 3 4 FB
|
|
Name 0----+----0----+----0----+----0----+----0 Inputs
|
|
IDE_W ........................................ 0
|
|
LAN_ACCESS XXXXXXXXXXXXXXXXX..XXXXXXXXXXXXXXXXXXX.. 36
|
|
INT_OUT .................XX..................... 2
|
|
0----+----1----+----2----+----3----+----4
|
|
0 0 0 0
|
|
*********************************** FB4 ***********************************
|
|
Number of function block inputs used/remaining: 22/32
|
|
Number of signals used by logic mapping into function block: 22
|
|
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
|
Name Pt Pt Pt Pt # Type Use
|
|
LAN_A_INIT<3> 1 0 0 4 FB4_1 (b) (b)
|
|
D<0> 2 0 0 3 FB4_2 2 GTS/I/O I/O
|
|
$OpTx$FX_DC$35 1 0 0 4 FB4_3 (b) (b)
|
|
LAN_WR_RST 2 0 0 3 FB4_4 (b) (b)
|
|
A_LAN<1> 1 0 0 4 FB4_5 3 GTS/I/O O
|
|
A_LAN<0> 1 0 0 4 FB4_6 4 I/O O
|
|
LAN_D_INIT<8> 2 0 0 3 FB4_7 (b) (b)
|
|
A_LAN<3> 2 0 0 3 FB4_8 5 GTS/I/O O
|
|
LAN_D_INIT<1> 2 0 0 3 FB4_9 (b) (b)
|
|
LAN_CS_RST 2 0 0 3 FB4_10 (b) (b)
|
|
LAN_A_INIT<6> 2 0 0 3 FB4_11 (b) (b)
|
|
A_LAN<2> 1 0 0 4 FB4_12 6 GTS/I/O O
|
|
DQ_SWAP$BUF7/DQ_SWAP$BUF7_TRST
|
|
2 0 0 3 FB4_13 (b) (b)
|
|
A_LAN<5> 1 0 0 4 FB4_14 7 I/O O
|
|
Z3_ADR<9> 3 0 0 2 FB4_15 (b) (b)
|
|
Z3_ADR<8> 3 0 0 2 FB4_16 (b) (b)
|
|
Z3_ADR<7> 3 0 0 2 FB4_17 (b) (b)
|
|
Z3_ADR<6> 3 0 0 2 FB4_18 (b) (b)
|
|
|
|
Signals Used by Logic in Function Block
|
|
1: $OpTx$FX_DC$32 9: LAN_RST_SM_FSM_FFd2 16: Z3_ADR<2>
|
|
2: AUTOCONFIG_ACCESS 10: LAN_RST_SM_FSM_FFd3 17: Z3_ADR<4>
|
|
3: CONFIG_READY 11: A<10>.PIN 18: Z3_ADR_0
|
|
4: D_9_IOBUFE/D_9_IOBUFE_TRST 12: A<11>.PIN 19: Z3_ADR_1
|
|
5: FCS 13: A<8>.PIN 20: Z3_ADR_1/Z3_ADR_1_SETF
|
|
6: LAN_A_INIT<3> 14: A<9>.PIN 21: Z3_A_LOW
|
|
7: LAN_READY 15: RESET 22: Z3_DATA<16>
|
|
8: LAN_RST_SM_FSM_FFd1
|
|
|
|
Signal 1 2 3 4 FB
|
|
Name 0----+----0----+----0----+----0----+----0 Inputs
|
|
LAN_A_INIT<3> ..............X......................... 1
|
|
D<0> X..X.................X.................. 3
|
|
$OpTx$FX_DC$35 ....X.........X......................... 2
|
|
LAN_WR_RST ........XX....X......................... 3
|
|
A_LAN<1> ..............X..X...................... 2
|
|
A_LAN<0> ..............X.....X................... 2
|
|
LAN_D_INIT<8> .......X......X......................... 2
|
|
A_LAN<3> .....X........XX........................ 3
|
|
LAN_D_INIT<1> .......X......X......................... 2
|
|
LAN_CS_RST ........XX....X......................... 3
|
|
LAN_A_INIT<6> .......X......X......................... 2
|
|
A_LAN<2> ..............X...X..................... 2
|
|
DQ_SWAP$BUF7/DQ_SWAP$BUF7_TRST
|
|
.XX.X.X................................. 4
|
|
A_LAN<5> ..............X.X....................... 2
|
|
Z3_ADR<9> ....X......X.......X.................... 3
|
|
Z3_ADR<8> ....X.....X........X.................... 3
|
|
Z3_ADR<7> ....X........X.....X.................... 3
|
|
Z3_ADR<6> ....X.......X......X.................... 3
|
|
0----+----1----+----2----+----3----+----4
|
|
0 0 0 0
|
|
*********************************** FB5 ***********************************
|
|
Number of function block inputs used/remaining: 40/14
|
|
Number of signals used by logic mapping into function block: 40
|
|
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
|
Name Pt Pt Pt Pt # Type Use
|
|
(unused) 0 0 0 5 FB5_1 (b)
|
|
CP_CS 0 0 0 5 FB5_2 34 I/O O
|
|
(unused) 0 0 0 5 FB5_3 (b)
|
|
Z3_ADR<5> 3 0 0 2 FB5_4 (b) (b)
|
|
ROM_OE 0 0 0 5 FB5_5 35 I/O O
|
|
Z3_ADR<4> 3 0 0 2 FB5_6 (b) (b)
|
|
Z3_ADR<3> 3 0 0 2 FB5_7 (b) (b)
|
|
Z3_ADR<2> 3 0 0 2 FB5_8 38 GCK/I/O (b)
|
|
Z3_ADR<13> 3 0 0 2 FB5_9 (b) (b)
|
|
D<2> 2 0 0 3 FB5_10 39 I/O I/O
|
|
Z3_ADR<12> 3 0 0 2 FB5_11 (b) (b)
|
|
D<9> 3 0 0 2 FB5_12 40 I/O I/O
|
|
Z3_ADR<11> 3 0 0 2 FB5_13 (b) (b)
|
|
D<10> 3 0 0 2 FB5_14 41 I/O I/O
|
|
D<11> 3 0 0 2 FB5_15 43 I/O I/O
|
|
Z3_ADR<10> 3 0 0 2 FB5_16 (b) (b)
|
|
D<12> 3 0 0 2 FB5_17 44 I/O I/O
|
|
AUTOCONFIG_ACCESS 3 0 0 2 FB5_18 (b) (b)
|
|
|
|
Signals Used by Logic in Function Block
|
|
1: $OpTx$FX_DC$32 15: A<23>.PIN 28: A<14>.PIN
|
|
2: A<4> 16: A<18>.PIN 29: A<20>.PIN
|
|
3: A<5> 17: A<19>.PIN 30: A<15>.PIN
|
|
4: A<6> 18: A<12>.PIN 31: A<21>.PIN
|
|
5: A<7> 19: A<13>.PIN 32: A<16>.PIN
|
|
6: CFIN 20: D<15>.PIN 33: A<22>.PIN
|
|
7: CFOUT 21: D<14>.PIN 34: Z3_ADR_1/Z3_ADR_1_SETF
|
|
8: D_9_IOBUFE/D_9_IOBUFE_TRST 22: D<13>.PIN 35: Z3_DATA<18>
|
|
9: D_OUT<1> 23: D<12>.PIN 36: Z3_DATA<25>
|
|
10: D_OUT<2> 24: D<11>.PIN 37: Z3_DATA<26>
|
|
11: D_OUT<3> 25: D<10>.PIN 38: Z3_DATA<27>
|
|
12: D_OUT<4> 26: D<9>.PIN 39: Z3_DATA<28>
|
|
13: FCS 27: D<8>.PIN 40: Z3
|
|
14: A<17>.PIN
|
|
|
|
Signal 1 2 3 4 5 FB
|
|
Name 0----+----0----+----0----+----0----+----0----+----0 Inputs
|
|
CP_CS .................................................. 0
|
|
Z3_ADR<5> ....X.......X....................X................ 3
|
|
ROM_OE .................................................. 0
|
|
Z3_ADR<4> ...X........X....................X................ 3
|
|
Z3_ADR<3> ..X.........X....................X................ 3
|
|
Z3_ADR<2> .X..........X....................X................ 3
|
|
Z3_ADR<13> ............X................X...X................ 3
|
|
D<2> X......X..........................X............... 3
|
|
Z3_ADR<12> ............X..............X.....X................ 3
|
|
D<9> X......XX..........................X.............. 4
|
|
Z3_ADR<11> ............X.....X..............X................ 3
|
|
D<10> X......X.X..........................X............. 4
|
|
D<11> X......X..X..........................X............ 4
|
|
Z3_ADR<10> ............X....X...............X................ 3
|
|
D<12> X......X...X..........................X........... 4
|
|
AUTOCONFIG_ACCESS .....XX.....XXXXX..XXXXXXXX.X.XXXX.....X.......... 21
|
|
0----+----1----+----2----+----3----+----4----+----5
|
|
0 0 0 0 0
|
|
*********************************** FB6 ***********************************
|
|
Number of function block inputs used/remaining: 7/47
|
|
Number of signals used by logic mapping into function block: 7
|
|
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
|
Name Pt Pt Pt Pt # Type Use
|
|
(unused) 0 0 0 5 FB6_1 (b)
|
|
LAN_CFG<2> 0 0 0 5 FB6_2 135 I/O O
|
|
A_LAN<12> 1 0 0 4 FB6_3 136 I/O O
|
|
(unused) 0 0 0 5 FB6_4 (b)
|
|
A_LAN<13> 1 0 0 4 FB6_5 137 I/O O
|
|
A_LAN<10> 1 0 0 4 FB6_6 138 I/O O
|
|
(unused) 0 0 0 5 FB6_7 (b)
|
|
A_LAN<11> 1 0 0 4 FB6_8 139 I/O O
|
|
(unused) 0 0 0 5 FB6_9 (b)
|
|
A_LAN<8> 1 0 0 4 FB6_10 140 I/O O
|
|
(unused) 0 0 0 5 FB6_11 (b)
|
|
(unused) 0 0 0 5 FB6_12 (b)
|
|
(unused) 0 0 0 5 FB6_13 (b)
|
|
A_LAN<9> 1 0 0 4 FB6_14 142 I/O O
|
|
(unused) 0 0 0 5 FB6_15 143 GSR/I/O I
|
|
(unused) 0 0 0 5 FB6_16 (b)
|
|
(unused) 0 0 0 5 FB6_17 (b)
|
|
(unused) 0 0 0 5 FB6_18 (b)
|
|
|
|
Signals Used by Logic in Function Block
|
|
1: RESET 4: Z3_ADR<12> 6: Z3_ADR<8>
|
|
2: Z3_ADR<10> 5: Z3_ADR<7> 7: Z3_ADR<9>
|
|
3: Z3_ADR<11>
|
|
|
|
Signal 1 2 3 4 FB
|
|
Name 0----+----0----+----0----+----0----+----0 Inputs
|
|
LAN_CFG<2> ........................................ 0
|
|
A_LAN<12> X.X..................................... 2
|
|
A_LAN<13> X..X.................................... 2
|
|
A_LAN<10> X.....X................................. 2
|
|
A_LAN<11> XX...................................... 2
|
|
A_LAN<8> X...X................................... 2
|
|
A_LAN<9> X....X.................................. 2
|
|
0----+----1----+----2----+----3----+----4
|
|
0 0 0 0
|
|
*********************************** FB7 ***********************************
|
|
Number of function block inputs used/remaining: 8/46
|
|
Number of signals used by logic mapping into function block: 8
|
|
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
|
Name Pt Pt Pt Pt # Type Use
|
|
(unused) 0 0 0 5 FB7_1 (b)
|
|
(unused) 0 0 0 5 FB7_2 (b)
|
|
D<13> 3 0 0 2 FB7_3 45 I/O I/O
|
|
(unused) 0 0 0 5 FB7_4 (b)
|
|
D<14> 3 0 0 2 FB7_5 46 I/O I/O
|
|
(unused) 0 0 0 5 FB7_6 (b)
|
|
(unused) 0 0 0 5 FB7_7 (b)
|
|
(unused) 0 0 0 5 FB7_8 (b)
|
|
(unused) 0 0 0 5 FB7_9 (b)
|
|
(unused) 0 0 0 5 FB7_10 (b)
|
|
(unused) 0 0 0 5 FB7_11 (b)
|
|
D<15> 3 0 0 2 FB7_12 48 I/O I/O
|
|
(unused) 0 0 0 5 FB7_13 (b)
|
|
(unused) 0 0 0 5 FB7_14 (b)
|
|
(unused) 0 0 0 5 FB7_15 49 I/O I
|
|
(unused) 0 0 0 5 FB7_16 (b)
|
|
(unused) 0 0 0 5 FB7_17 (b)
|
|
(unused) 0 0 0 5 FB7_18 (b)
|
|
|
|
Signals Used by Logic in Function Block
|
|
1: $OpTx$FX_DC$32 4: D_OUT<6> 7: Z3_DATA<30>
|
|
2: D_9_IOBUFE/D_9_IOBUFE_TRST 5: D_OUT<7> 8: Z3_DATA<31>
|
|
3: D_OUT<5> 6: Z3_DATA<29>
|
|
|
|
Signal 1 2 3 4 FB
|
|
Name 0----+----0----+----0----+----0----+----0 Inputs
|
|
D<13> XXX..X.................................. 4
|
|
D<14> XX.X..X................................. 4
|
|
D<15> XX..X..X................................ 4
|
|
0----+----1----+----2----+----3----+----4
|
|
0 0 0 0
|
|
*********************************** FB8 ***********************************
|
|
Number of function block inputs used/remaining: 24/30
|
|
Number of signals used by logic mapping into function block: 24
|
|
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
|
Name Pt Pt Pt Pt # Type Use
|
|
(unused) 0 0 0 5 FB8_1 (b)
|
|
DQ<12> 2 0 0 3 FB8_2 130 I/O I/O
|
|
DQ<14> 2 0 0 3 FB8_3 131 I/O I/O
|
|
(unused) 0 0 0 5 FB8_4 (b)
|
|
LAN_WRH 2 0 0 3 FB8_5 132 I/O O
|
|
(unused) 0 0 0 5 FB8_6 (b)
|
|
(unused) 0 0 0 5 FB8_7 (b)
|
|
LAN_CS 2 0 0 3 FB8_8 133 I/O O
|
|
(unused) 0 0 0 5 FB8_9 (b)
|
|
LAN_RD 1 0 0 4 FB8_10 134 I/O O
|
|
Z3_ADR_1/Z3_ADR_1_SETF
|
|
1 0 0 4 FB8_11 (b) (b)
|
|
$OpTx$FX_DC$8 1 0 0 4 FB8_12 (b) (b)
|
|
$OpTx$FX_DC$33 1 0 0 4 FB8_13 (b) (b)
|
|
$OpTx$FX_DC$25 1 0 0 4 FB8_14 (b) (b)
|
|
$OpTx$FX_DC$9 2 0 0 3 FB8_15 (b) (b)
|
|
$OpTx$FX_DC$29 2 0 0 3 FB8_16 (b) (b)
|
|
Z3_ADR_1 3 0 0 2 FB8_17 (b) (b)
|
|
Z3_ADR_0 3 0 0 2 FB8_18 (b) (b)
|
|
|
|
Signals Used by Logic in Function Block
|
|
1: $OpTx$FX_DC$25 9: DQ_DATA<12> 17: LAN_WRH_S
|
|
2: $OpTx$FX_DC$29 10: DQ_DATA<14> 18: LAN_WR_RST
|
|
3: $OpTx$FX_DC$35 11: DS0 19: LDS
|
|
4: $OpTx$FX_DC$8 12: DS1 20: RESET
|
|
5: A<2> 13: FCS 21: RW
|
|
6: A<3> 14: LAN_ACCESS 22: UDS
|
|
7: BERR 15: LAN_CS_RST 23: Z3_ADR<13>
|
|
8: DQ_9_IOBUFE/DQ_9_IOBUFE_TRST 16: LAN_RD_S 24: Z3_ADR_1/Z3_ADR_1_SETF
|
|
|
|
Signal 1 2 3 4 FB
|
|
Name 0----+----0----+----0----+----0----+----0 Inputs
|
|
DQ<12> .......XX..........X.................... 3
|
|
DQ<14> .......X.X.........X.................... 3
|
|
LAN_WRH ..X.............XX...................... 3
|
|
LAN_CS .............XX....X.................... 3
|
|
LAN_RD ..X............X........................ 2
|
|
Z3_ADR_1/Z3_ADR_1_SETF
|
|
......X............X.................... 2
|
|
$OpTx$FX_DC$8 ..................X..X.................. 2
|
|
$OpTx$FX_DC$33 .X..................X.X................. 3
|
|
$OpTx$FX_DC$25 ..........XX............................ 2
|
|
$OpTx$FX_DC$9 X..X........X........................... 3
|
|
$OpTx$FX_DC$29 X..X.........X.......................... 3
|
|
Z3_ADR_1 .....X......X..........X................ 3
|
|
Z3_ADR_0 ....X.......X..........X................ 3
|
|
0----+----1----+----2----+----3----+----4
|
|
0 0 0 0
|
|
*********************************** FB9 ***********************************
|
|
Number of function block inputs used/remaining: 38/16
|
|
Number of signals used by logic mapping into function block: 38
|
|
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
|
Name Pt Pt Pt Pt # Type Use
|
|
SHUT_UP 2 0 0 3 FB9_1 (b) (b)
|
|
LAN_RST_SM_FSM_FFd1 2 0 0 3 FB9_2 50 I/O I
|
|
LAN_IRQ_D0 2 0 0 3 FB9_3 51 I/O I
|
|
CONFIG_READY 2 0 0 3 FB9_4 (b) (b)
|
|
LAN_RST_SM_FSM_FFd3 3 0 0 2 FB9_5 52 I/O I
|
|
LAN_RST_SM_FSM_FFd2 3 0 0 2 FB9_6 53 I/O I
|
|
LAN_INT_ENABLE 3 0 0 2 FB9_7 (b) (b)
|
|
LAN_BASEADR<6> 3 0 0 2 FB9_8 54 I/O I
|
|
LAN_BASEADR<5> 3 0 0 2 FB9_9 (b) (b)
|
|
LAN_BASEADR<4> 3 0 0 2 FB9_10 (b) (b)
|
|
A<8> 4 0 0 1 FB9_11 56 I/O I/O
|
|
LAN_BASEADR<3> 3 0 0 2 FB9_12 57 I/O (b)
|
|
LAN_BASEADR<2> 3 0 0 2 FB9_13 (b) (b)
|
|
A<9> 4 0 0 1 FB9_14 58 I/O I/O
|
|
LAN_BASEADR<1> 3 0 0 2 FB9_15 (b) (b)
|
|
LAN_BASEADR<15> 3 0 0 2 FB9_16 (b) (b)
|
|
A<10> 4 0 0 1 FB9_17 59 I/O I/O
|
|
LAN_IRQ_OUT 4 0 0 1 FB9_18 (b) (b)
|
|
|
|
Signals Used by Logic in Function Block
|
|
1: $OpTx$FX_DC$19 14: LAN_INT 27: DQ<0>.PIN
|
|
2: $OpTx$FX_DC$33 15: LAN_IRQ_D0 28: D<15>.PIN
|
|
3: $OpTx$FX_DC$9 16: LAN_IRQ_OUT 29: D<14>.PIN
|
|
4: CONFIG_READY 17: LAN_RST_SM_FSM_FFd1 30: D<6>.PIN
|
|
5: LAN_ACCESS 18: LAN_RST_SM_FSM_FFd2 31: D<5>.PIN
|
|
6: LAN_BASEADR<15> 19: LAN_RST_SM_FSM_FFd3 32: D<4>.PIN
|
|
7: LAN_BASEADR<1> 20: LAN_SM_FSM_FFd1 33: D<3>.PIN
|
|
8: LAN_BASEADR<2> 21: LAN_SM_FSM_FFd2 34: D<2>.PIN
|
|
9: LAN_BASEADR<3> 22: LAN_SM_FSM_FFd3 35: D<1>.PIN
|
|
10: LAN_BASEADR<4> 23: LAN_SM_FSM_FFd4 36: RESET
|
|
11: LAN_BASEADR<5> 24: LAN_SM_RST 37: RW
|
|
12: LAN_BASEADR<6> 25: DQ<2>.PIN 38: SHUT_UP
|
|
13: LAN_INT_ENABLE 26: DQ<1>.PIN
|
|
|
|
Signal 1 2 3 4 FB
|
|
Name 0----+----0----+----0----+----0----+----0 Inputs
|
|
SHUT_UP X..................................X.X.. 3
|
|
LAN_RST_SM_FSM_FFd1 ................XXX................X.... 4
|
|
LAN_IRQ_D0 .............X.....................X.... 2
|
|
CONFIG_READY .X.X...............................X.... 3
|
|
LAN_RST_SM_FSM_FFd3 ................XX.................X.... 3
|
|
LAN_RST_SM_FSM_FFd2 ................XXX................X.... 4
|
|
LAN_INT_ENABLE .X..........X..............X.......X.... 4
|
|
LAN_BASEADR<6> X..........X.................X.....X.... 4
|
|
LAN_BASEADR<5> X.........X...................X....X.... 4
|
|
LAN_BASEADR<4> X........X.....................X...X.... 4
|
|
A<8> ..X.X..............XXXXX..X.........X... 9
|
|
LAN_BASEADR<3> X.......X.......................X..X.... 4
|
|
LAN_BASEADR<2> X......X.........................X.X.... 4
|
|
A<9> ..X.X..............XXXXX.X..........X... 9
|
|
LAN_BASEADR<1> X.....X...........................XX.... 4
|
|
LAN_BASEADR<15> X....X.....................X.......X.... 4
|
|
A<10> ..X.X..............XXXXXX...........X... 9
|
|
LAN_IRQ_OUT .X..........XXXX............X......X.... 7
|
|
0----+----1----+----2----+----3----+----4
|
|
0 0 0 0
|
|
*********************************** FB10 ***********************************
|
|
Number of function block inputs used/remaining: 28/26
|
|
Number of signals used by logic mapping into function block: 28
|
|
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
|
Name Pt Pt Pt Pt # Type Use
|
|
$OpTx$FX_DC$19 1 0 0 4 FB10_1 (b) (b)
|
|
DQ<1> 3 0 0 2 FB10_2 117 I/O I/O
|
|
DQ<0> 2 0 0 3 FB10_3 118 I/O I/O
|
|
AUTO_CONFIG_DONE_CYCLE
|
|
2 0 0 3 FB10_4 (b) (b)
|
|
DQ<3> 2 0 0 3 FB10_5 119 I/O I/O
|
|
DQ<2> 2 0 0 3 FB10_6 120 I/O I/O
|
|
D_OUT<2> 3 0 0 2 FB10_7 (b) (b)
|
|
DQ<5> 2 0 0 3 FB10_8 121 I/O I/O
|
|
LAN_BASEADR<14> 4 0 0 1 FB10_9 (b) (b)
|
|
DQ<4> 3 0 0 2 FB10_10 124 I/O I/O
|
|
DQ<7> 2 0 0 3 FB10_11 125 I/O I/O
|
|
DQ<6> 2 0 0 3 FB10_12 126 I/O I/O
|
|
D_OUT<6> 4 0 0 1 FB10_13 (b) (b)
|
|
DQ<8> 3 0 0 2 FB10_14 128 I/O I/O
|
|
D_OUT<5> 4 0 0 1 FB10_15 (b) (b)
|
|
D_OUT<4> 4 0 0 1 FB10_16 (b) (b)
|
|
DQ<10> 3 0 0 2 FB10_17 129 I/O I/O
|
|
D_OUT<1> 4 0 0 1 FB10_18 (b) (b)
|
|
|
|
Signals Used by Logic in Function Block
|
|
1: $OpTx$FX_DC$19 11: DQ_DATA<4> 20: RESET
|
|
2: $OpTx$FX_DC$9 12: DQ_DATA<5> 21: RW
|
|
3: AUTOCONFIG_ACCESS 13: DQ_DATA<6> 22: Z3_ADR<2>
|
|
4: AUTO_CONFIG_DONE_CYCLE 14: DQ_DATA<7> 23: Z3_ADR<3>
|
|
5: DQ_9_IOBUFE/DQ_9_IOBUFE_TRST 15: DQ_DATA<8> 24: Z3_ADR<4>
|
|
6: DQ_DATA<0> 16: LAN_BASEADR<14> 25: Z3_ADR<5>
|
|
7: DQ_DATA<10> 17: LAN_D_INIT<1> 26: Z3_ADR<6>
|
|
8: DQ_DATA<1> 18: LAN_D_INIT<8> 27: Z3_ADR_0
|
|
9: DQ_DATA<2> 19: D<14>.PIN 28: Z3_ADR_1
|
|
10: DQ_DATA<3>
|
|
|
|
Signal 1 2 3 4 FB
|
|
Name 0----+----0----+----0----+----0----+----0 Inputs
|
|
$OpTx$FX_DC$19 .XX.................XXXXXXXX............ 10
|
|
DQ<1> ....X..X........X..X.................... 4
|
|
DQ<0> ....XX.............X.................... 3
|
|
AUTO_CONFIG_DONE_CYCLE
|
|
.XXX...............XXXXXXXX............. 11
|
|
DQ<3> ....X....X.........X.................... 3
|
|
DQ<2> ....X...X..........X.................... 3
|
|
D_OUT<2> .XX................X.XXXX.XX............ 9
|
|
DQ<5> ....X......X.......X.................... 3
|
|
LAN_BASEADR<14> XXX............X..XXXXXXXXXX............ 14
|
|
DQ<4> ....X.....X.....X..X.................... 4
|
|
DQ<7> ....X........X.....X.................... 3
|
|
DQ<6> ....X.......X......X.................... 3
|
|
D_OUT<6> .XX................X.XXXXXXX............ 10
|
|
DQ<8> ....X.........X..X.X.................... 4
|
|
D_OUT<5> .XX................X.XXXXXXX............ 10
|
|
D_OUT<4> .XX................X.XXXXXXX............ 10
|
|
DQ<10> ....X.X..........X.X.................... 4
|
|
D_OUT<1> .XX................X.XXXX.XX............ 9
|
|
0----+----1----+----2----+----3----+----4
|
|
0 0 0 0
|
|
*********************************** FB11 ***********************************
|
|
Number of function block inputs used/remaining: 39/15
|
|
Number of signals used by logic mapping into function block: 39
|
|
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
|
Name Pt Pt Pt Pt # Type Use
|
|
$OpTx$FX_SC$28 2 0 0 3 FB11_1 (b) (b)
|
|
Z3_DATA<31> 3 0 0 2 FB11_2 (b) (b)
|
|
A<11> 4 0 0 1 FB11_3 60 I/O I/O
|
|
Z3_DATA<30> 3 0 0 2 FB11_4 (b) (b)
|
|
A<12> 4 0 0 1 FB11_5 61 I/O I/O
|
|
LAN_SM_FSM_FFd1 3 0 0 2 FB11_6 (b) (b)
|
|
DQ_DATA<2> 4 0 0 1 FB11_7 (b) (b)
|
|
DQ_DATA<1> 4 0 0 1 FB11_8 (b) (b)
|
|
DQ_DATA<15> 4 0 0 1 FB11_9 (b) (b)
|
|
A<13> 4 0 0 1 FB11_10 64 I/O I/O
|
|
A<14> 4 0 0 1 FB11_11 66 I/O I/O
|
|
ROM_B<0> 0 0 0 5 FB11_12 68 I/O O
|
|
DQ_DATA<14> 4 0 0 1 FB11_13 (b) (b)
|
|
ROM_B<1> 0 0 0 5 FB11_14 69 I/O O
|
|
DQ_DATA<13> 4 0 0 1 FB11_15 (b) (b)
|
|
DQ_DATA<12> 4 0 0 1 FB11_16 (b) (b)
|
|
CP_WE 0 0 0 5 FB11_17 70 I/O O
|
|
DQ_DATA<11> 4 0 0 1 FB11_18 (b) (b)
|
|
|
|
Signals Used by Logic in Function Block
|
|
1: $OpTx$FX_DC$22 14: LAN_SM_FSM_FFd1 27: DQ<4>.PIN
|
|
2: $OpTx$FX_DC$25 15: LAN_SM_FSM_FFd2 28: DQ<3>.PIN
|
|
3: $OpTx$FX_DC$8 16: LAN_SM_FSM_FFd3 29: D<15>.PIN
|
|
4: $OpTx$FX_DC$9 17: LAN_SM_FSM_FFd4 30: D<14>.PIN
|
|
5: $OpTx$FX_SC$28 18: LAN_SM_RST 31: D<13>.PIN
|
|
6: DQ_DATA<11> 19: A<10>.PIN 32: D<12>.PIN
|
|
7: DQ_DATA<12> 20: A<23>.PIN 33: D<11>.PIN
|
|
8: DQ_DATA<13> 21: A<19>.PIN 34: D<2>.PIN
|
|
9: DQ_DATA<14> 22: A<9>.PIN 35: D<1>.PIN
|
|
10: DQ_DATA<15> 23: DQ<15>.PIN 36: A<20>.PIN
|
|
11: DQ_DATA<1> 24: DQ<14>.PIN 37: A<21>.PIN
|
|
12: DQ_DATA<2> 25: DQ<6>.PIN 38: A<22>.PIN
|
|
13: LAN_ACCESS 26: DQ<5>.PIN 39: RW
|
|
|
|
Signal 1 2 3 4 FB
|
|
Name 0----+----0----+----0----+----0----+----0 Inputs
|
|
$OpTx$FX_SC$28 ..X..........XXXX....................... 5
|
|
Z3_DATA<31> .............XXXXX....X................. 6
|
|
A<11> ...X........XXXXXX.........X..........X. 9
|
|
Z3_DATA<30> .............XXXXX.....X................ 6
|
|
A<12> ...X........XXXXXX........X...........X. 9
|
|
LAN_SM_FSM_FFd1 .X...........X.XXX...................... 5
|
|
DQ_DATA<2> X.X.X......X..XXXXX..............X...... 10
|
|
DQ_DATA<1> X.X.X.....X...XXXX...X............X..... 10
|
|
DQ_DATA<15> X.X.X....X....XXXX.X........X........... 10
|
|
A<13> ...X........XXXXXX.......X............X. 9
|
|
A<14> ...X........XXXXXX......X.............X. 9
|
|
ROM_B<0> ........................................ 0
|
|
DQ_DATA<14> X.X.X...X.....XXXX...........X.......X.. 10
|
|
ROM_B<1> ........................................ 0
|
|
DQ_DATA<13> X.X.X..X......XXXX............X.....X... 10
|
|
DQ_DATA<12> X.X.X.X.......XXXX.............X...X.... 10
|
|
CP_WE ........................................ 0
|
|
DQ_DATA<11> X.X.XX........XXXX..X...........X....... 10
|
|
0----+----1----+----2----+----3----+----4
|
|
0 0 0 0
|
|
*********************************** FB12 ***********************************
|
|
Number of function block inputs used/remaining: 8/46
|
|
Number of signals used by logic mapping into function block: 8
|
|
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
|
Name Pt Pt Pt Pt # Type Use
|
|
(unused) 0 0 0 5 FB12_1 (b)
|
|
LAN_CFG<4> 0 0 0 5 FB12_2 110 I/O O
|
|
(unused) 0 0 0 5 FB12_3 111 I/O I
|
|
(unused) 0 0 0 5 FB12_4 (b)
|
|
DQ<15> 2 0 0 3 FB12_5 112 I/O I/O
|
|
(unused) 0 0 0 5 FB12_6 (b)
|
|
(unused) 0 0 0 5 FB12_7 (b)
|
|
DQ<13> 2 0 0 3 FB12_8 113 I/O I/O
|
|
(unused) 0 0 0 5 FB12_9 (b)
|
|
DQ<11> 3 0 0 2 FB12_10 115 I/O I/O
|
|
(unused) 0 0 0 5 FB12_11 (b)
|
|
DQ<9> 3 0 0 2 FB12_12 116 I/O I/O
|
|
(unused) 0 0 0 5 FB12_13 (b)
|
|
(unused) 0 0 0 5 FB12_14 (b)
|
|
(unused) 0 0 0 5 FB12_15 (b)
|
|
(unused) 0 0 0 5 FB12_16 (b)
|
|
(unused) 0 0 0 5 FB12_17 (b)
|
|
(unused) 0 0 0 5 FB12_18 (b)
|
|
|
|
Signals Used by Logic in Function Block
|
|
1: DQ_9_IOBUFE/DQ_9_IOBUFE_TRST 4: DQ_DATA<15> 7: LAN_D_INIT<8>
|
|
2: DQ_DATA<11> 5: DQ_DATA<9> 8: RESET
|
|
3: DQ_DATA<13> 6: LAN_D_INIT<1>
|
|
|
|
Signal 1 2 3 4 FB
|
|
Name 0----+----0----+----0----+----0----+----0 Inputs
|
|
LAN_CFG<4> ........................................ 0
|
|
DQ<15> X..X...X................................ 3
|
|
DQ<13> X.X....X................................ 3
|
|
DQ<11> XX....XX................................ 4
|
|
DQ<9> X...XX.X................................ 4
|
|
0----+----1----+----2----+----3----+----4
|
|
0 0 0 0
|
|
*********************************** FB13 ***********************************
|
|
Number of function block inputs used/remaining: 39/15
|
|
Number of signals used by logic mapping into function block: 39
|
|
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
|
Name Pt Pt Pt Pt # Type Use
|
|
Z3_DATA<29> 3 0 0 2 FB13_1 (b) (b)
|
|
CP_RD 0 0 0 5 FB13_2 71 I/O O
|
|
Z3_DATA<23> 3 0 0 2 FB13_3 (b) (b)
|
|
Z3_DATA<22> 3 0 0 2 FB13_4 (b) (b)
|
|
Z3_DATA<21> 3 0 0 2 FB13_5 (b) (b)
|
|
Z3_DATA<20> 3 0 0 2 FB13_6 (b) (b)
|
|
Z3_DATA<19> 3 0 0 2 FB13_7 (b) (b)
|
|
A<15> 4 0 0 1 FB13_8 74 I/O I/O
|
|
Z3_DATA<18> 3 0 0 2 FB13_9 (b) (b)
|
|
Z3_DATA<17> 3 0 0 2 FB13_10 (b) (b)
|
|
Z3_DATA<16> 3 0 0 2 FB13_11 75 I/O I
|
|
LAN_WRL_S 3 0 0 2 FB13_12 (b) (b)
|
|
LAN_WRH_S 3 0 0 2 FB13_13 (b) (b)
|
|
LAN_WRL 2 0 0 3 FB13_14 76 I/O O
|
|
DQ_DATA<6> 4 0 0 1 FB13_15 77 I/O I
|
|
DQ_DATA<5> 4 0 0 1 FB13_16 (b) (b)
|
|
DQ_DATA<4> 4 0 0 1 FB13_17 78 I/O I
|
|
DQ_DATA<3> 4 0 0 1 FB13_18 (b) (b)
|
|
|
|
Signals Used by Logic in Function Block
|
|
1: $OpTx$FX_DC$22 14: LAN_SM_FSM_FFd2 27: DQ<4>.PIN
|
|
2: $OpTx$FX_DC$35 15: LAN_SM_FSM_FFd3 28: DQ<3>.PIN
|
|
3: $OpTx$FX_DC$8 16: LAN_SM_FSM_FFd4 29: DQ<2>.PIN
|
|
4: $OpTx$FX_DC$9 17: LAN_SM_RST 30: A<13>.PIN
|
|
5: $OpTx$FX_SC$28 18: LAN_WRL_S 31: DQ<1>.PIN
|
|
6: DQ_DATA<3> 19: LAN_WR_RST 32: DQ<0>.PIN
|
|
7: DQ_DATA<4> 20: LDS 33: A<14>.PIN
|
|
8: DQ_DATA<5> 21: A<11>.PIN 34: D<6>.PIN
|
|
9: DQ_DATA<6> 22: DQ<13>.PIN 35: D<5>.PIN
|
|
10: DS0 23: A<12>.PIN 36: D<4>.PIN
|
|
11: DS1 24: DQ<7>.PIN 37: D<3>.PIN
|
|
12: LAN_ACCESS 25: DQ<6>.PIN 38: RW
|
|
13: LAN_SM_FSM_FFd1 26: DQ<5>.PIN 39: UDS
|
|
|
|
Signal 1 2 3 4 FB
|
|
Name 0----+----0----+----0----+----0----+----0 Inputs
|
|
Z3_DATA<29> ............XXXXX....X.................. 6
|
|
CP_RD ........................................ 0
|
|
Z3_DATA<23> ............XXXXX......X................ 6
|
|
Z3_DATA<22> ............XXXXX.......X............... 6
|
|
Z3_DATA<21> ............XXXXX........X.............. 6
|
|
Z3_DATA<20> ............XXXXX.........X............. 6
|
|
Z3_DATA<19> ............XXXXX..........X............ 6
|
|
A<15> ...X.......XXXXXX......X.............X.. 9
|
|
Z3_DATA<18> ............XXXXX...........X........... 6
|
|
Z3_DATA<17> ............XXXXX.............X......... 6
|
|
Z3_DATA<16> ............XXXXX..............X........ 6
|
|
LAN_WRL_S ..........X.XXXXX.....................X. 7
|
|
LAN_WRH_S .........X..XXXXX..X.................... 7
|
|
LAN_WRL .X...............XX..................... 3
|
|
DQ_DATA<6> X.X.X...X....XXXX...............XX...... 10
|
|
DQ_DATA<5> X.X.X..X.....XXXX............X....X..... 10
|
|
DQ_DATA<4> X.X.X.X......XXXX.....X............X.... 10
|
|
DQ_DATA<3> X.X.XX.......XXXX...X...............X... 10
|
|
0----+----1----+----2----+----3----+----4
|
|
0 0 0 0
|
|
*********************************** FB14 ***********************************
|
|
Number of function block inputs used/remaining: 6/48
|
|
Number of signals used by logic mapping into function block: 6
|
|
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
|
Name Pt Pt Pt Pt # Type Use
|
|
(unused) 0 0 0 5 FB14_1 (b)
|
|
(unused) 0 0 0 5 FB14_2 (b)
|
|
OVR 0 0 0 5 FB14_3 100 I/O O
|
|
(unused) 0 0 0 5 FB14_4 (b)
|
|
(unused) 0 0 0 5 FB14_5 101 I/O
|
|
(unused) 0 0 0 5 FB14_6 102 I/O
|
|
(unused) 0 0 0 5 FB14_7 (b)
|
|
(unused) 0 0 0 5 FB14_8 103 I/O
|
|
(unused) 0 0 0 5 FB14_9 (b)
|
|
(unused) 0 0 0 5 FB14_10 104 I/O I
|
|
CFOUT 3 0 0 2 FB14_11 105 I/O O
|
|
(unused) 0 0 0 5 FB14_12 (b)
|
|
(unused) 0 0 0 5 FB14_13 (b)
|
|
SLAVE 2 0 0 3 FB14_14 106 I/O O
|
|
OWN 0 0 0 5 FB14_15 107 I/O O
|
|
(unused) 0 0 0 5 FB14_16 (b)
|
|
(unused) 0 0 0 5 FB14_17 (b)
|
|
(unused) 0 0 0 5 FB14_18 (b)
|
|
|
|
Signals Used by Logic in Function Block
|
|
1: AUTOBOOT_OFF 3: AUTO_CONFIG_DONE_CYCLE 5: LAN_ACCESS
|
|
2: AUTOCONFIG_ACCESS 4: FCS 6: RESET
|
|
|
|
Signal 1 2 3 4 FB
|
|
Name 0----+----0----+----0----+----0----+----0 Inputs
|
|
OVR ........................................ 0
|
|
CFOUT X.XX.X.................................. 4
|
|
SLAVE .X.XX................................... 3
|
|
OWN ........................................ 0
|
|
0----+----1----+----2----+----3----+----4
|
|
0 0 0 0
|
|
*********************************** FB15 ***********************************
|
|
Number of function block inputs used/remaining: 39/15
|
|
Number of signals used by logic mapping into function block: 39
|
|
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
|
Name Pt Pt Pt Pt # Type Use
|
|
Z3_DATA<30>/Z3_DATA<30>_CE
|
|
1 0 0 4 FB15_1 (b) (b)
|
|
Z3_DATA<10>/Z3_DATA<10>_CE
|
|
1 0 0 4 FB15_2 79 I/O I
|
|
$OpTx$FX_DC$22 2 0 0 3 FB15_3 80 I/O (b)
|
|
LAN_BASEADR<9> 3 0 0 2 FB15_4 (b) (b)
|
|
LAN_BASEADR<8> 3 0 0 2 FB15_5 (b) (b)
|
|
LAN_BASEADR<7> 3 0 0 2 FB15_6 (b) (b)
|
|
LAN_BASEADR<13> 3 0 0 2 FB15_7 (b) (b)
|
|
LAN_BASEADR<12> 3 0 0 2 FB15_8 81 I/O I
|
|
LAN_BASEADR<11> 3 0 0 2 FB15_9 (b) (b)
|
|
LAN_BASEADR<10> 3 0 0 2 FB15_10 82 I/O I
|
|
LAN_BASEADR<0> 3 0 0 2 FB15_11 83 I/O I
|
|
DTACK 1 0 0 4 FB15_12 85 I/O O
|
|
DQ_DATA<9> 4 0 0 1 FB15_13 (b) (b)
|
|
A<23> 4 0 0 1 FB15_14 86 I/O I/O
|
|
A<22> 4 0 0 1 FB15_15 87 I/O I/O
|
|
DQ_DATA<8> 4 0 0 1 FB15_16 (b) (b)
|
|
A<21> 4 0 0 1 FB15_17 88 I/O I/O
|
|
DQ_DATA<7> 4 0 0 1 FB15_18 (b) (b)
|
|
|
|
Signals Used by Logic in Function Block
|
|
1: $OpTx$FX_DC$19 14: LAN_BASEADR<12> 27: DQ<13>.PIN
|
|
2: $OpTx$FX_DC$22 15: LAN_BASEADR<13> 28: D<13>.PIN
|
|
3: $OpTx$FX_DC$8 16: LAN_BASEADR<7> 29: D<12>.PIN
|
|
4: $OpTx$FX_DC$9 17: LAN_BASEADR<8> 30: D<11>.PIN
|
|
5: $OpTx$FX_SC$28 18: LAN_BASEADR<9> 31: D<10>.PIN
|
|
6: DQ_DATA<7> 19: LAN_SM_FSM_FFd1 32: D<9>.PIN
|
|
7: DQ_DATA<8> 20: LAN_SM_FSM_FFd2 33: D<8>.PIN
|
|
8: DQ_DATA<9> 21: LAN_SM_FSM_FFd3 34: D<7>.PIN
|
|
9: DQ_SWAP$BUF7/DQ_SWAP$BUF7_TRST 22: LAN_SM_FSM_FFd4 35: D<0>.PIN
|
|
10: LAN_ACCESS 23: LAN_SM_RST 36: A<15>.PIN
|
|
11: LAN_BASEADR<0> 24: A<17>.PIN 37: A<16>.PIN
|
|
12: LAN_BASEADR<10> 25: DQ<15>.PIN 38: RESET
|
|
13: LAN_BASEADR<11> 26: DQ<14>.PIN 39: RW
|
|
|
|
Signal 1 2 3 4 FB
|
|
Name 0----+----0----+----0----+----0----+----0 Inputs
|
|
Z3_DATA<30>/Z3_DATA<30>_CE
|
|
..................XXXX.................. 4
|
|
Z3_DATA<10>/Z3_DATA<10>_CE
|
|
..................XXXX.................. 4
|
|
$OpTx$FX_DC$22 ..................XXXX.................. 4
|
|
LAN_BASEADR<9> X................X.............X.....X.. 4
|
|
LAN_BASEADR<8> X...............X...............X....X.. 4
|
|
LAN_BASEADR<7> X..............X.................X...X.. 4
|
|
LAN_BASEADR<13> X.............X............X.........X.. 4
|
|
LAN_BASEADR<12> X............X..............X........X.. 4
|
|
LAN_BASEADR<11> X...........X................X.......X.. 4
|
|
LAN_BASEADR<10> X..........X..................X......X.. 4
|
|
LAN_BASEADR<0> X.........X.......................X..X.. 4
|
|
DTACK ........X............................... 1
|
|
DQ_DATA<9> .XX.X..X...........XXXXX.......X........ 10
|
|
A<23> ...X.....X........XXXXX.X.............X. 9
|
|
A<22> ...X.....X........XXXXX..X............X. 9
|
|
DQ_DATA<8> .XX.X.X............XXXX.........X...X... 10
|
|
A<21> ...X.....X........XXXXX...X...........X. 9
|
|
DQ_DATA<7> .XX.XX.............XXXX..........X.X.... 10
|
|
0----+----1----+----2----+----3----+----4
|
|
0 0 0 0
|
|
*********************************** FB16 ***********************************
|
|
Number of function block inputs used/remaining: 27/27
|
|
Number of signals used by logic mapping into function block: 27
|
|
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
|
Name Pt Pt Pt Pt # Type Use
|
|
Z3_DATA<28> 3 0 /\2 0 FB16_1 (b) (b)
|
|
A<20> 4 0 0 1 FB16_2 91 I/O I/O
|
|
A<19> 4 0 0 1 FB16_3 92 I/O I/O
|
|
Z3_DATA<27> 3 0 0 2 FB16_4 (b) (b)
|
|
Z3_DATA<26> 3 0 0 2 FB16_5 93 I/O I
|
|
A<18> 4 0 0 1 FB16_6 94 I/O I/O
|
|
Z3_DATA<25> 3 0 0 2 FB16_7 (b) (b)
|
|
A<17> 4 0 0 1 FB16_8 95 I/O I/O
|
|
Z3_DATA<24> 3 0 0 2 FB16_9 (b) (b)
|
|
MTACK 0 0 0 5 FB16_10 96 I/O O
|
|
A<16> 4 0 0 1 FB16_11 97 I/O I/O
|
|
LAN_RD_S 4 0 0 1 FB16_12 98 I/O I
|
|
DQ_DATA<10> 4 0 0 1 FB16_13 (b) (b)
|
|
DQ_DATA<0> 4 0 0 1 FB16_14 (b) (b)
|
|
LAN_SM_FSM_FFd2 5 0 0 0 FB16_15 (b) (b)
|
|
LAN_READY 5 0 0 0 FB16_16 (b) (b)
|
|
Z3_A_LOW 6 1<- 0 0 FB16_17 (b) (b)
|
|
LAN_SM_FSM_FFd4 6 2<- /\1 0 FB16_18 (b) (b)
|
|
|
|
Signals Used by Logic in Function Block
|
|
1: $OpTx$FX_DC$22 10: LAN_SM_FSM_FFd1 19: DQ<10>.PIN
|
|
2: $OpTx$FX_DC$25 11: LAN_SM_FSM_FFd2 20: DQ<9>.PIN
|
|
3: $OpTx$FX_DC$29 12: LAN_SM_FSM_FFd3 21: DQ<8>.PIN
|
|
4: $OpTx$FX_DC$8 13: LAN_SM_FSM_FFd4 22: D<10>.PIN
|
|
5: $OpTx$FX_DC$9 14: LAN_SM_RST 23: D<0>.PIN
|
|
6: $OpTx$FX_SC$28 15: A<18>.PIN 24: RW
|
|
7: DQ_DATA<0> 16: A<8>.PIN 25: Z3_ADR<13>
|
|
8: DQ_DATA<10> 17: DQ<12>.PIN 26: Z3_DATA<10>/Z3_DATA<10>_CE
|
|
9: LAN_ACCESS 18: DQ<11>.PIN 27: Z3_DATA<30>/Z3_DATA<30>_CE
|
|
|
|
Signal 1 2 3 4 FB
|
|
Name 0----+----0----+----0----+----0----+----0 Inputs
|
|
Z3_DATA<28> .........XXXXX..X....................... 6
|
|
A<20> ....X...XXXXXX..X......X................ 9
|
|
A<19> ....X...XXXXXX...X.....X................ 9
|
|
Z3_DATA<27> .........XXXXX...X...................... 6
|
|
Z3_DATA<26> .........XXXXX....X..................... 6
|
|
A<18> ....X...XXXXXX....X....X................ 9
|
|
Z3_DATA<25> .........XXXXX.....X.................... 6
|
|
A<17> ....X...XXXXXX.....X...X................ 9
|
|
Z3_DATA<24> .........XXXXX......X................... 6
|
|
MTACK ........................................ 0
|
|
A<16> ....X...XXXXXX......X..X................ 9
|
|
LAN_RD_S ..X......XXXXX.........XX............... 8
|
|
DQ_DATA<10> X..X.X.X..XXXXX......X.................. 10
|
|
DQ_DATA<0> X..X.XX...XXXX.X......X................. 10
|
|
LAN_SM_FSM_FFd2 ..XX.....XXXXX.........XX............... 9
|
|
LAN_READY .X.......X.XXX...........XX............. 7
|
|
Z3_A_LOW .X.X....XXXXXX..........XXX............. 11
|
|
LAN_SM_FSM_FFd4 .XX......XXXXX.........XXX.............. 10
|
|
0----+----1----+----2----+----3----+----4
|
|
0 0 0 0
|
|
******************************* Equations ********************************
|
|
|
|
********** Mapped Logic **********
|
|
|
|
|
|
$OpTx$FX_DC$19 <= (NOT RW AND NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND
|
|
NOT Z3_ADR(6) AND AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND
|
|
NOT Z3_ADR(5) AND NOT $OpTx$FX_DC$9);
|
|
|
|
|
|
$OpTx$FX_DC$22 <= ((LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd1 AND
|
|
LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3)
|
|
OR (NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd1 AND
|
|
NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3));
|
|
|
|
|
|
$OpTx$FX_DC$25 <= (DS1 AND DS0);
|
|
|
|
|
|
$OpTx$FX_DC$29 <= ((NOT LAN_ACCESS)
|
|
OR ($OpTx$FX_DC$8 AND $OpTx$FX_DC$25));
|
|
|
|
|
|
$OpTx$FX_DC$32 <= (RW AND LAN_ACCESS AND NOT $OpTx$FX_DC$9);
|
|
|
|
|
|
$OpTx$FX_DC$33 <= (NOT RW AND Z3_ADR(13) AND NOT $OpTx$FX_DC$29);
|
|
|
|
|
|
$OpTx$FX_DC$35 <= (NOT FCS AND RESET);
|
|
|
|
|
|
$OpTx$FX_DC$8 <= (UDS AND LDS);
|
|
|
|
|
|
$OpTx$FX_DC$9 <= ((FCS)
|
|
OR ($OpTx$FX_DC$8 AND $OpTx$FX_DC$25));
|
|
|
|
|
|
$OpTx$FX_SC$28 <= ((LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd1 AND
|
|
NOT LAN_SM_FSM_FFd3)
|
|
OR (NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND
|
|
NOT LAN_SM_FSM_FFd3 AND $OpTx$FX_DC$8));
|
|
|
|
FDCPE_A8: FDCPE port map (A_I(8),DQ(0).PIN,CLK_EXT,'0',LAN_SM_RST,A_CE(8));
|
|
A_CE(8) <= (NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd1 AND
|
|
LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3);
|
|
A(8) <= A_I(8) when A_OE(8) = '1' else 'Z';
|
|
A_OE(8) <= (RW AND LAN_ACCESS AND NOT $OpTx$FX_DC$9);
|
|
|
|
FDCPE_A9: FDCPE port map (A_I(9),DQ(1).PIN,CLK_EXT,'0',LAN_SM_RST,A_CE(9));
|
|
A_CE(9) <= (NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd1 AND
|
|
LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3);
|
|
A(9) <= A_I(9) when A_OE(9) = '1' else 'Z';
|
|
A_OE(9) <= (RW AND LAN_ACCESS AND NOT $OpTx$FX_DC$9);
|
|
|
|
FDCPE_A10: FDCPE port map (A_I(10),DQ(2).PIN,CLK_EXT,'0',LAN_SM_RST,A_CE(10));
|
|
A_CE(10) <= (NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd1 AND
|
|
LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3);
|
|
A(10) <= A_I(10) when A_OE(10) = '1' else 'Z';
|
|
A_OE(10) <= (RW AND LAN_ACCESS AND NOT $OpTx$FX_DC$9);
|
|
|
|
FDCPE_A11: FDCPE port map (A_I(11),DQ(3).PIN,CLK_EXT,'0',LAN_SM_RST,A_CE(11));
|
|
A_CE(11) <= (NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd1 AND
|
|
LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3);
|
|
A(11) <= A_I(11) when A_OE(11) = '1' else 'Z';
|
|
A_OE(11) <= (RW AND LAN_ACCESS AND NOT $OpTx$FX_DC$9);
|
|
|
|
FDCPE_A12: FDCPE port map (A_I(12),DQ(4).PIN,CLK_EXT,'0',LAN_SM_RST,A_CE(12));
|
|
A_CE(12) <= (NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd1 AND
|
|
LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3);
|
|
A(12) <= A_I(12) when A_OE(12) = '1' else 'Z';
|
|
A_OE(12) <= (RW AND LAN_ACCESS AND NOT $OpTx$FX_DC$9);
|
|
|
|
FDCPE_A13: FDCPE port map (A_I(13),DQ(5).PIN,CLK_EXT,'0',LAN_SM_RST,A_CE(13));
|
|
A_CE(13) <= (NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd1 AND
|
|
LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3);
|
|
A(13) <= A_I(13) when A_OE(13) = '1' else 'Z';
|
|
A_OE(13) <= (RW AND LAN_ACCESS AND NOT $OpTx$FX_DC$9);
|
|
|
|
FDCPE_A14: FDCPE port map (A_I(14),DQ(6).PIN,CLK_EXT,'0',LAN_SM_RST,A_CE(14));
|
|
A_CE(14) <= (NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd1 AND
|
|
LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3);
|
|
A(14) <= A_I(14) when A_OE(14) = '1' else 'Z';
|
|
A_OE(14) <= (RW AND LAN_ACCESS AND NOT $OpTx$FX_DC$9);
|
|
|
|
FDCPE_A15: FDCPE port map (A_I(15),DQ(7).PIN,CLK_EXT,'0',LAN_SM_RST,A_CE(15));
|
|
A_CE(15) <= (NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd1 AND
|
|
LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3);
|
|
A(15) <= A_I(15) when A_OE(15) = '1' else 'Z';
|
|
A_OE(15) <= (RW AND LAN_ACCESS AND NOT $OpTx$FX_DC$9);
|
|
|
|
FDCPE_A16: FDCPE port map (A_I(16),DQ(8).PIN,CLK_EXT,'0',LAN_SM_RST,A_CE(16));
|
|
A_CE(16) <= (NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd1 AND
|
|
LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3);
|
|
A(16) <= A_I(16) when A_OE(16) = '1' else 'Z';
|
|
A_OE(16) <= (RW AND LAN_ACCESS AND NOT $OpTx$FX_DC$9);
|
|
|
|
FDCPE_A17: FDCPE port map (A_I(17),DQ(9).PIN,CLK_EXT,'0',LAN_SM_RST,A_CE(17));
|
|
A_CE(17) <= (NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd1 AND
|
|
LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3);
|
|
A(17) <= A_I(17) when A_OE(17) = '1' else 'Z';
|
|
A_OE(17) <= (RW AND LAN_ACCESS AND NOT $OpTx$FX_DC$9);
|
|
|
|
FDCPE_A18: FDCPE port map (A_I(18),DQ(10).PIN,CLK_EXT,'0',LAN_SM_RST,A_CE(18));
|
|
A_CE(18) <= (NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd1 AND
|
|
LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3);
|
|
A(18) <= A_I(18) when A_OE(18) = '1' else 'Z';
|
|
A_OE(18) <= (RW AND LAN_ACCESS AND NOT $OpTx$FX_DC$9);
|
|
|
|
FDCPE_A19: FDCPE port map (A_I(19),DQ(11).PIN,CLK_EXT,'0',LAN_SM_RST,A_CE(19));
|
|
A_CE(19) <= (NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd1 AND
|
|
LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3);
|
|
A(19) <= A_I(19) when A_OE(19) = '1' else 'Z';
|
|
A_OE(19) <= (RW AND LAN_ACCESS AND NOT $OpTx$FX_DC$9);
|
|
|
|
FDCPE_A20: FDCPE port map (A_I(20),DQ(12).PIN,CLK_EXT,'0',LAN_SM_RST,A_CE(20));
|
|
A_CE(20) <= (NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd1 AND
|
|
LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3);
|
|
A(20) <= A_I(20) when A_OE(20) = '1' else 'Z';
|
|
A_OE(20) <= (RW AND LAN_ACCESS AND NOT $OpTx$FX_DC$9);
|
|
|
|
FDCPE_A21: FDCPE port map (A_I(21),DQ(13).PIN,CLK_EXT,'0',LAN_SM_RST,A_CE(21));
|
|
A_CE(21) <= (NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd1 AND
|
|
LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3);
|
|
A(21) <= A_I(21) when A_OE(21) = '1' else 'Z';
|
|
A_OE(21) <= (RW AND LAN_ACCESS AND NOT $OpTx$FX_DC$9);
|
|
|
|
FDCPE_A22: FDCPE port map (A_I(22),DQ(14).PIN,CLK_EXT,'0',LAN_SM_RST,A_CE(22));
|
|
A_CE(22) <= (NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd1 AND
|
|
LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3);
|
|
A(22) <= A_I(22) when A_OE(22) = '1' else 'Z';
|
|
A_OE(22) <= (RW AND LAN_ACCESS AND NOT $OpTx$FX_DC$9);
|
|
|
|
FDCPE_A23: FDCPE port map (A_I(23),DQ(15).PIN,CLK_EXT,'0',LAN_SM_RST,A_CE(23));
|
|
A_CE(23) <= (NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd1 AND
|
|
LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3);
|
|
A(23) <= A_I(23) when A_OE(23) = '1' else 'Z';
|
|
A_OE(23) <= (RW AND LAN_ACCESS AND NOT $OpTx$FX_DC$9);
|
|
|
|
FDCPE_AUTOCONFIG_ACCESS: FDCPE port map (AUTOCONFIG_ACCESS,AUTOCONFIG_ACCESS_D,NOT FCS,NOT Z3_ADR_1/Z3_ADR_1_SETF,'0');
|
|
AUTOCONFIG_ACCESS_D <= (Z3 AND D(9).PIN AND D(8).PIN AND D(14).PIN AND
|
|
D(13).PIN AND D(12).PIN AND D(11).PIN AND D(10).PIN AND D(15).PIN AND
|
|
NOT CFIN AND NOT A(20).PIN AND NOT A(19).PIN AND NOT A(18).PIN AND NOT A(17).PIN AND
|
|
NOT A(16).PIN AND NOT A(23).PIN AND NOT A(22).PIN AND NOT A(21).PIN AND CFOUT);
|
|
|
|
FTCPE_AUTO_CONFIG_DONE_CYCLE: FTCPE port map (AUTO_CONFIG_DONE_CYCLE,AUTO_CONFIG_DONE_CYCLE_T,CLK_EXT,NOT RESET,'0');
|
|
AUTO_CONFIG_DONE_CYCLE_T <= (NOT RW AND NOT AUTO_CONFIG_DONE_CYCLE AND NOT Z3_ADR(2) AND
|
|
Z3_ADR_0 AND NOT Z3_ADR(6) AND AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND
|
|
Z3_ADR(4) AND NOT Z3_ADR(5) AND NOT $OpTx$FX_DC$9);
|
|
|
|
|
|
A_LAN(0) <= NOT ((RESET AND NOT Z3_A_LOW));
|
|
|
|
|
|
A_LAN(1) <= NOT ((RESET AND NOT Z3_ADR_0));
|
|
|
|
|
|
A_LAN(2) <= NOT ((RESET AND NOT Z3_ADR_1));
|
|
|
|
|
|
A_LAN(3) <= ((RESET AND Z3_ADR(2))
|
|
OR (NOT RESET AND LAN_A_INIT(3)));
|
|
|
|
|
|
A_LAN(4) <= NOT ((RESET AND NOT Z3_ADR(3)));
|
|
|
|
|
|
A_LAN(5) <= NOT ((RESET AND NOT Z3_ADR(4)));
|
|
|
|
|
|
A_LAN(6) <= ((RESET AND Z3_ADR(5))
|
|
OR (NOT RESET AND LAN_A_INIT(6)));
|
|
|
|
|
|
A_LAN(7) <= NOT ((RESET AND NOT Z3_ADR(6)));
|
|
|
|
|
|
A_LAN(8) <= NOT ((RESET AND NOT Z3_ADR(7)));
|
|
|
|
|
|
A_LAN(9) <= NOT ((RESET AND NOT Z3_ADR(8)));
|
|
|
|
|
|
A_LAN(10) <= NOT ((RESET AND NOT Z3_ADR(9)));
|
|
|
|
|
|
A_LAN(11) <= NOT ((RESET AND NOT Z3_ADR(10)));
|
|
|
|
|
|
A_LAN(12) <= NOT ((RESET AND NOT Z3_ADR(11)));
|
|
|
|
|
|
A_LAN(13) <= NOT ((RESET AND NOT Z3_ADR(12)));
|
|
|
|
FDCPE_CFOUT: FDCPE port map (CFOUT,CFOUT_D,CLK_EXT,'0',NOT RESET,FCS);
|
|
CFOUT_D <= (NOT AUTO_CONFIG_DONE_CYCLE AND AUTOBOOT_OFF);
|
|
|
|
FDCPE_CONFIG_READY: FDCPE port map (CONFIG_READY,CONFIG_READY_D,CLK_EXT,NOT RESET,'0');
|
|
CONFIG_READY_D <= (NOT CONFIG_READY AND NOT $OpTx$FX_DC$33);
|
|
|
|
|
|
CP_CS <= '1';
|
|
|
|
|
|
CP_RD <= '1';
|
|
|
|
|
|
CP_WE <= '1';
|
|
|
|
|
|
D_I(0) <= NOT ((NOT Z3_DATA(16) AND $OpTx$FX_DC$32));
|
|
D(0) <= D_I(0) when D_OE(0) = '1' else 'Z';
|
|
D_OE(0) <= D_9_IOBUFE/D_9_IOBUFE_TRST;
|
|
|
|
|
|
D_I(1) <= NOT ((NOT Z3_DATA(17) AND $OpTx$FX_DC$32));
|
|
D(1) <= D_I(1) when D_OE(1) = '1' else 'Z';
|
|
D_OE(1) <= D_9_IOBUFE/D_9_IOBUFE_TRST;
|
|
|
|
|
|
D_I(2) <= NOT ((NOT Z3_DATA(18) AND $OpTx$FX_DC$32));
|
|
D(2) <= D_I(2) when D_OE(2) = '1' else 'Z';
|
|
D_OE(2) <= D_9_IOBUFE/D_9_IOBUFE_TRST;
|
|
|
|
|
|
D_I(3) <= NOT ((NOT Z3_DATA(19) AND $OpTx$FX_DC$32));
|
|
D(3) <= D_I(3) when D_OE(3) = '1' else 'Z';
|
|
D_OE(3) <= D_9_IOBUFE/D_9_IOBUFE_TRST;
|
|
|
|
|
|
D_I(4) <= NOT ((NOT Z3_DATA(20) AND $OpTx$FX_DC$32));
|
|
D(4) <= D_I(4) when D_OE(4) = '1' else 'Z';
|
|
D_OE(4) <= D_9_IOBUFE/D_9_IOBUFE_TRST;
|
|
|
|
|
|
D_I(5) <= NOT ((NOT Z3_DATA(21) AND $OpTx$FX_DC$32));
|
|
D(5) <= D_I(5) when D_OE(5) = '1' else 'Z';
|
|
D_OE(5) <= D_9_IOBUFE/D_9_IOBUFE_TRST;
|
|
|
|
|
|
D_I(6) <= NOT ((NOT Z3_DATA(22) AND $OpTx$FX_DC$32));
|
|
D(6) <= D_I(6) when D_OE(6) = '1' else 'Z';
|
|
D_OE(6) <= D_9_IOBUFE/D_9_IOBUFE_TRST;
|
|
|
|
|
|
D_I(7) <= NOT ((NOT Z3_DATA(23) AND $OpTx$FX_DC$32));
|
|
D(7) <= D_I(7) when D_OE(7) = '1' else 'Z';
|
|
D_OE(7) <= D_9_IOBUFE/D_9_IOBUFE_TRST;
|
|
|
|
|
|
D_I(8) <= ((Z3_DATA(24) AND $OpTx$FX_DC$32)
|
|
OR (D_OUT(0) AND NOT $OpTx$FX_DC$32));
|
|
D(8) <= D_I(8) when D_OE(8) = '1' else 'Z';
|
|
D_OE(8) <= D_9_IOBUFE/D_9_IOBUFE_TRST;
|
|
|
|
|
|
D_I(9) <= ((Z3_DATA(25) AND $OpTx$FX_DC$32)
|
|
OR (D_OUT(1) AND NOT $OpTx$FX_DC$32));
|
|
D(9) <= D_I(9) when D_OE(9) = '1' else 'Z';
|
|
D_OE(9) <= D_9_IOBUFE/D_9_IOBUFE_TRST;
|
|
|
|
|
|
D_I(10) <= ((Z3_DATA(26) AND $OpTx$FX_DC$32)
|
|
OR (D_OUT(2) AND NOT $OpTx$FX_DC$32));
|
|
D(10) <= D_I(10) when D_OE(10) = '1' else 'Z';
|
|
D_OE(10) <= D_9_IOBUFE/D_9_IOBUFE_TRST;
|
|
|
|
|
|
D_I(11) <= ((Z3_DATA(27) AND $OpTx$FX_DC$32)
|
|
OR (D_OUT(3) AND NOT $OpTx$FX_DC$32));
|
|
D(11) <= D_I(11) when D_OE(11) = '1' else 'Z';
|
|
D_OE(11) <= D_9_IOBUFE/D_9_IOBUFE_TRST;
|
|
|
|
|
|
D_I(12) <= ((Z3_DATA(28) AND $OpTx$FX_DC$32)
|
|
OR (D_OUT(4) AND NOT $OpTx$FX_DC$32));
|
|
D(12) <= D_I(12) when D_OE(12) = '1' else 'Z';
|
|
D_OE(12) <= D_9_IOBUFE/D_9_IOBUFE_TRST;
|
|
|
|
|
|
D_I(13) <= ((Z3_DATA(29) AND $OpTx$FX_DC$32)
|
|
OR (D_OUT(5) AND NOT $OpTx$FX_DC$32));
|
|
D(13) <= D_I(13) when D_OE(13) = '1' else 'Z';
|
|
D_OE(13) <= D_9_IOBUFE/D_9_IOBUFE_TRST;
|
|
|
|
|
|
D_I(14) <= ((Z3_DATA(30) AND $OpTx$FX_DC$32)
|
|
OR (D_OUT(6) AND NOT $OpTx$FX_DC$32));
|
|
D(14) <= D_I(14) when D_OE(14) = '1' else 'Z';
|
|
D_OE(14) <= D_9_IOBUFE/D_9_IOBUFE_TRST;
|
|
|
|
|
|
D_I(15) <= ((Z3_DATA(31) AND $OpTx$FX_DC$32)
|
|
OR (D_OUT(7) AND NOT $OpTx$FX_DC$32));
|
|
D(15) <= D_I(15) when D_OE(15) = '1' else 'Z';
|
|
D_OE(15) <= D_9_IOBUFE/D_9_IOBUFE_TRST;
|
|
|
|
|
|
DQ_I(0) <= (RESET AND DQ_DATA(0));
|
|
DQ(0) <= DQ_I(0) when DQ_OE(0) = '1' else 'Z';
|
|
DQ_OE(0) <= DQ_9_IOBUFE/DQ_9_IOBUFE_TRST;
|
|
|
|
|
|
DQ_I(1) <= ((RESET AND DQ_DATA(1))
|
|
OR (NOT RESET AND LAN_D_INIT(1)));
|
|
DQ(1) <= DQ_I(1) when DQ_OE(1) = '1' else 'Z';
|
|
DQ_OE(1) <= DQ_9_IOBUFE/DQ_9_IOBUFE_TRST;
|
|
|
|
|
|
DQ_I(2) <= (RESET AND DQ_DATA(2));
|
|
DQ(2) <= DQ_I(2) when DQ_OE(2) = '1' else 'Z';
|
|
DQ_OE(2) <= DQ_9_IOBUFE/DQ_9_IOBUFE_TRST;
|
|
|
|
|
|
DQ_I(3) <= (RESET AND DQ_DATA(3));
|
|
DQ(3) <= DQ_I(3) when DQ_OE(3) = '1' else 'Z';
|
|
DQ_OE(3) <= DQ_9_IOBUFE/DQ_9_IOBUFE_TRST;
|
|
|
|
|
|
DQ_I(4) <= ((RESET AND DQ_DATA(4))
|
|
OR (NOT RESET AND LAN_D_INIT(1)));
|
|
DQ(4) <= DQ_I(4) when DQ_OE(4) = '1' else 'Z';
|
|
DQ_OE(4) <= DQ_9_IOBUFE/DQ_9_IOBUFE_TRST;
|
|
|
|
|
|
DQ_I(5) <= (RESET AND DQ_DATA(5));
|
|
DQ(5) <= DQ_I(5) when DQ_OE(5) = '1' else 'Z';
|
|
DQ_OE(5) <= DQ_9_IOBUFE/DQ_9_IOBUFE_TRST;
|
|
|
|
|
|
DQ_I(6) <= (RESET AND DQ_DATA(6));
|
|
DQ(6) <= DQ_I(6) when DQ_OE(6) = '1' else 'Z';
|
|
DQ_OE(6) <= DQ_9_IOBUFE/DQ_9_IOBUFE_TRST;
|
|
|
|
|
|
DQ_I(7) <= (RESET AND DQ_DATA(7));
|
|
DQ(7) <= DQ_I(7) when DQ_OE(7) = '1' else 'Z';
|
|
DQ_OE(7) <= DQ_9_IOBUFE/DQ_9_IOBUFE_TRST;
|
|
|
|
|
|
DQ_I(8) <= ((RESET AND DQ_DATA(8))
|
|
OR (NOT RESET AND LAN_D_INIT(8)));
|
|
DQ(8) <= DQ_I(8) when DQ_OE(8) = '1' else 'Z';
|
|
DQ_OE(8) <= DQ_9_IOBUFE/DQ_9_IOBUFE_TRST;
|
|
|
|
|
|
DQ_I(9) <= ((RESET AND DQ_DATA(9))
|
|
OR (NOT RESET AND LAN_D_INIT(1)));
|
|
DQ(9) <= DQ_I(9) when DQ_OE(9) = '1' else 'Z';
|
|
DQ_OE(9) <= DQ_9_IOBUFE/DQ_9_IOBUFE_TRST;
|
|
|
|
|
|
DQ_I(10) <= ((RESET AND DQ_DATA(10))
|
|
OR (NOT RESET AND LAN_D_INIT(8)));
|
|
DQ(10) <= DQ_I(10) when DQ_OE(10) = '1' else 'Z';
|
|
DQ_OE(10) <= DQ_9_IOBUFE/DQ_9_IOBUFE_TRST;
|
|
|
|
|
|
DQ_I(11) <= ((RESET AND DQ_DATA(11))
|
|
OR (NOT RESET AND LAN_D_INIT(8)));
|
|
DQ(11) <= DQ_I(11) when DQ_OE(11) = '1' else 'Z';
|
|
DQ_OE(11) <= DQ_9_IOBUFE/DQ_9_IOBUFE_TRST;
|
|
|
|
|
|
DQ_I(12) <= (RESET AND DQ_DATA(12));
|
|
DQ(12) <= DQ_I(12) when DQ_OE(12) = '1' else 'Z';
|
|
DQ_OE(12) <= DQ_9_IOBUFE/DQ_9_IOBUFE_TRST;
|
|
|
|
|
|
DQ_I(13) <= (RESET AND DQ_DATA(13));
|
|
DQ(13) <= DQ_I(13) when DQ_OE(13) = '1' else 'Z';
|
|
DQ_OE(13) <= DQ_9_IOBUFE/DQ_9_IOBUFE_TRST;
|
|
|
|
|
|
DQ_I(14) <= (RESET AND DQ_DATA(14));
|
|
DQ(14) <= DQ_I(14) when DQ_OE(14) = '1' else 'Z';
|
|
DQ_OE(14) <= DQ_9_IOBUFE/DQ_9_IOBUFE_TRST;
|
|
|
|
|
|
DQ_I(15) <= (RESET AND DQ_DATA(15));
|
|
DQ(15) <= DQ_I(15) when DQ_OE(15) = '1' else 'Z';
|
|
DQ_OE(15) <= DQ_9_IOBUFE/DQ_9_IOBUFE_TRST;
|
|
|
|
|
|
DQ_9_IOBUFE/DQ_9_IOBUFE_TRST <= ((NOT RESET)
|
|
OR (LAN_ACCESS AND NOT $OpTx$FX_DC$9 AND NOT $OpTx$FX_DC$32));
|
|
|
|
FDCPE_DQ_DATA0: FDCPE port map (DQ_DATA(0),DQ_DATA_D(0),CLK_EXT,'0',LAN_SM_RST);
|
|
DQ_DATA_D(0) <= ((A(8).PIN AND $OpTx$FX_SC$28)
|
|
OR (DQ_DATA(0) AND NOT $OpTx$FX_DC$22)
|
|
OR (D(0).PIN AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND
|
|
NOT LAN_SM_FSM_FFd3 AND NOT $OpTx$FX_DC$8));
|
|
|
|
FDCPE_DQ_DATA1: FDCPE port map (DQ_DATA(1),DQ_DATA_D(1),CLK_EXT,'0',LAN_SM_RST);
|
|
DQ_DATA_D(1) <= ((DQ_DATA(1) AND NOT $OpTx$FX_DC$22)
|
|
OR (A(9).PIN AND $OpTx$FX_SC$28)
|
|
OR (D(1).PIN AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND
|
|
NOT LAN_SM_FSM_FFd3 AND NOT $OpTx$FX_DC$8));
|
|
|
|
FDCPE_DQ_DATA2: FDCPE port map (DQ_DATA(2),DQ_DATA_D(2),CLK_EXT,'0',LAN_SM_RST);
|
|
DQ_DATA_D(2) <= ((DQ_DATA(2) AND NOT $OpTx$FX_DC$22)
|
|
OR (A(10).PIN AND $OpTx$FX_SC$28)
|
|
OR (D(2).PIN AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND
|
|
NOT LAN_SM_FSM_FFd3 AND NOT $OpTx$FX_DC$8));
|
|
|
|
FDCPE_DQ_DATA3: FDCPE port map (DQ_DATA(3),DQ_DATA_D(3),CLK_EXT,'0',LAN_SM_RST);
|
|
DQ_DATA_D(3) <= ((DQ_DATA(3) AND NOT $OpTx$FX_DC$22)
|
|
OR (A(11).PIN AND $OpTx$FX_SC$28)
|
|
OR (D(3).PIN AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND
|
|
NOT LAN_SM_FSM_FFd3 AND NOT $OpTx$FX_DC$8));
|
|
|
|
FDCPE_DQ_DATA4: FDCPE port map (DQ_DATA(4),DQ_DATA_D(4),CLK_EXT,'0',LAN_SM_RST);
|
|
DQ_DATA_D(4) <= ((DQ_DATA(4) AND NOT $OpTx$FX_DC$22)
|
|
OR (A(12).PIN AND $OpTx$FX_SC$28)
|
|
OR (D(4).PIN AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND
|
|
NOT LAN_SM_FSM_FFd3 AND NOT $OpTx$FX_DC$8));
|
|
|
|
FDCPE_DQ_DATA5: FDCPE port map (DQ_DATA(5),DQ_DATA_D(5),CLK_EXT,'0',LAN_SM_RST);
|
|
DQ_DATA_D(5) <= ((DQ_DATA(5) AND NOT $OpTx$FX_DC$22)
|
|
OR (A(13).PIN AND $OpTx$FX_SC$28)
|
|
OR (D(5).PIN AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND
|
|
NOT LAN_SM_FSM_FFd3 AND NOT $OpTx$FX_DC$8));
|
|
|
|
FDCPE_DQ_DATA6: FDCPE port map (DQ_DATA(6),DQ_DATA_D(6),CLK_EXT,'0',LAN_SM_RST);
|
|
DQ_DATA_D(6) <= ((DQ_DATA(6) AND NOT $OpTx$FX_DC$22)
|
|
OR (A(14).PIN AND $OpTx$FX_SC$28)
|
|
OR (D(6).PIN AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND
|
|
NOT LAN_SM_FSM_FFd3 AND NOT $OpTx$FX_DC$8));
|
|
|
|
FDCPE_DQ_DATA7: FDCPE port map (DQ_DATA(7),DQ_DATA_D(7),CLK_EXT,'0',LAN_SM_RST);
|
|
DQ_DATA_D(7) <= ((A(15).PIN AND $OpTx$FX_SC$28)
|
|
OR (DQ_DATA(7) AND NOT $OpTx$FX_DC$22)
|
|
OR (D(7).PIN AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND
|
|
NOT LAN_SM_FSM_FFd3 AND NOT $OpTx$FX_DC$8));
|
|
|
|
FDCPE_DQ_DATA8: FDCPE port map (DQ_DATA(8),DQ_DATA_D(8),CLK_EXT,'0',LAN_SM_RST);
|
|
DQ_DATA_D(8) <= ((A(16).PIN AND $OpTx$FX_SC$28)
|
|
OR (DQ_DATA(8) AND NOT $OpTx$FX_DC$22)
|
|
OR (D(8).PIN AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND
|
|
NOT LAN_SM_FSM_FFd3 AND NOT $OpTx$FX_DC$8));
|
|
|
|
FDCPE_DQ_DATA9: FDCPE port map (DQ_DATA(9),DQ_DATA_D(9),CLK_EXT,'0',LAN_SM_RST);
|
|
DQ_DATA_D(9) <= ((A(17).PIN AND $OpTx$FX_SC$28)
|
|
OR (DQ_DATA(9) AND NOT $OpTx$FX_DC$22)
|
|
OR (D(9).PIN AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND
|
|
NOT LAN_SM_FSM_FFd3 AND NOT $OpTx$FX_DC$8));
|
|
|
|
FDCPE_DQ_DATA10: FDCPE port map (DQ_DATA(10),DQ_DATA_D(10),CLK_EXT,'0',LAN_SM_RST);
|
|
DQ_DATA_D(10) <= ((A(18).PIN AND $OpTx$FX_SC$28)
|
|
OR (DQ_DATA(10) AND NOT $OpTx$FX_DC$22)
|
|
OR (D(10).PIN AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND
|
|
NOT LAN_SM_FSM_FFd3 AND NOT $OpTx$FX_DC$8));
|
|
|
|
FDCPE_DQ_DATA11: FDCPE port map (DQ_DATA(11),DQ_DATA_D(11),CLK_EXT,'0',LAN_SM_RST);
|
|
DQ_DATA_D(11) <= ((A(19).PIN AND $OpTx$FX_SC$28)
|
|
OR (DQ_DATA(11) AND NOT $OpTx$FX_DC$22)
|
|
OR (D(11).PIN AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND
|
|
NOT LAN_SM_FSM_FFd3 AND NOT $OpTx$FX_DC$8));
|
|
|
|
FDCPE_DQ_DATA12: FDCPE port map (DQ_DATA(12),DQ_DATA_D(12),CLK_EXT,'0',LAN_SM_RST);
|
|
DQ_DATA_D(12) <= ((A(20).PIN AND $OpTx$FX_SC$28)
|
|
OR (DQ_DATA(12) AND NOT $OpTx$FX_DC$22)
|
|
OR (D(12).PIN AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND
|
|
NOT LAN_SM_FSM_FFd3 AND NOT $OpTx$FX_DC$8));
|
|
|
|
FDCPE_DQ_DATA13: FDCPE port map (DQ_DATA(13),DQ_DATA_D(13),CLK_EXT,'0',LAN_SM_RST);
|
|
DQ_DATA_D(13) <= ((DQ_DATA(13) AND NOT $OpTx$FX_DC$22)
|
|
OR (A(21).PIN AND $OpTx$FX_SC$28)
|
|
OR (D(13).PIN AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND
|
|
NOT LAN_SM_FSM_FFd3 AND NOT $OpTx$FX_DC$8));
|
|
|
|
FDCPE_DQ_DATA14: FDCPE port map (DQ_DATA(14),DQ_DATA_D(14),CLK_EXT,'0',LAN_SM_RST);
|
|
DQ_DATA_D(14) <= ((DQ_DATA(14) AND NOT $OpTx$FX_DC$22)
|
|
OR (A(22).PIN AND $OpTx$FX_SC$28)
|
|
OR (D(14).PIN AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND
|
|
NOT LAN_SM_FSM_FFd3 AND NOT $OpTx$FX_DC$8));
|
|
|
|
FDCPE_DQ_DATA15: FDCPE port map (DQ_DATA(15),DQ_DATA_D(15),CLK_EXT,'0',LAN_SM_RST);
|
|
DQ_DATA_D(15) <= ((DQ_DATA(15) AND NOT $OpTx$FX_DC$22)
|
|
OR (A(23).PIN AND $OpTx$FX_SC$28)
|
|
OR (D(15).PIN AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND
|
|
NOT LAN_SM_FSM_FFd3 AND NOT $OpTx$FX_DC$8));
|
|
|
|
|
|
DQ_SWAP$BUF7/DQ_SWAP$BUF7_TRST <= ((FCS)
|
|
OR (NOT AUTOCONFIG_ACCESS AND NOT CONFIG_READY AND NOT LAN_READY));
|
|
|
|
|
|
DTACK_I <= '0';
|
|
DTACK <= DTACK_I when DTACK_OE = '1' else 'Z';
|
|
DTACK_OE <= NOT DQ_SWAP$BUF7/DQ_SWAP$BUF7_TRST;
|
|
|
|
|
|
D_9_IOBUFE/D_9_IOBUFE_TRST <= (($OpTx$FX_DC$32)
|
|
OR (RW AND AUTOCONFIG_ACCESS AND NOT $OpTx$FX_DC$9));
|
|
|
|
FDCPE_D_OUT0: FDCPE port map (D_OUT(0),D_OUT_D(0),CLK_EXT,'0',NOT RESET);
|
|
D_OUT_D(0) <= (NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND
|
|
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND NOT Z3_ADR(4) AND NOT Z3_ADR(5) AND
|
|
NOT $OpTx$FX_DC$9);
|
|
|
|
FDCPE_D_OUT1: FDCPE port map (D_OUT(1),D_OUT_D(1),CLK_EXT,'0',NOT RESET);
|
|
D_OUT_D(1) <= ((NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND AUTOCONFIG_ACCESS AND
|
|
NOT Z3_ADR(3) AND NOT Z3_ADR(4) AND NOT Z3_ADR(5) AND NOT $OpTx$FX_DC$9)
|
|
OR (NOT Z3_ADR(2) AND NOT Z3_ADR_0 AND AUTOCONFIG_ACCESS AND
|
|
NOT Z3_ADR(3) AND NOT Z3_ADR(4) AND NOT Z3_ADR(5) AND NOT $OpTx$FX_DC$9)
|
|
OR (NOT Z3_ADR_1 AND NOT Z3_ADR_0 AND AUTOCONFIG_ACCESS AND
|
|
NOT Z3_ADR(3) AND NOT Z3_ADR(4) AND NOT Z3_ADR(5) AND NOT $OpTx$FX_DC$9));
|
|
|
|
FDCPE_D_OUT2: FDCPE port map (D_OUT(2),D_OUT_D(2),CLK_EXT,'0',NOT RESET);
|
|
D_OUT_D(2) <= ((Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND
|
|
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND NOT Z3_ADR(4) AND NOT Z3_ADR(5) AND
|
|
NOT $OpTx$FX_DC$9)
|
|
OR (NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND NOT Z3_ADR_0 AND
|
|
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND NOT Z3_ADR(4) AND NOT Z3_ADR(5) AND
|
|
NOT $OpTx$FX_DC$9));
|
|
|
|
FDCPE_D_OUT3: FDCPE port map (D_OUT(3),D_OUT_D(3),CLK_EXT,'0',NOT RESET);
|
|
D_OUT_D(3) <= (NOT Z3_ADR_1 AND AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND
|
|
NOT Z3_ADR(4) AND NOT Z3_ADR(5) AND NOT $OpTx$FX_DC$9);
|
|
|
|
FDCPE_D_OUT4: FDCPE port map (D_OUT(4),D_OUT_D(4),CLK_EXT,'0',NOT RESET);
|
|
D_OUT_D(4) <= ((NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND
|
|
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND NOT Z3_ADR(4) AND NOT Z3_ADR(5) AND
|
|
NOT $OpTx$FX_DC$9)
|
|
OR (NOT Z3_ADR(2) AND NOT Z3_ADR_0 AND NOT Z3_ADR(6) AND
|
|
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND NOT Z3_ADR(4) AND NOT Z3_ADR(5) AND
|
|
NOT $OpTx$FX_DC$9)
|
|
OR (NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND
|
|
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND NOT Z3_ADR(4) AND NOT Z3_ADR(5) AND
|
|
NOT $OpTx$FX_DC$9));
|
|
|
|
FDCPE_D_OUT5: FDCPE port map (D_OUT(5),D_OUT_D(5),CLK_EXT,'0',NOT RESET);
|
|
D_OUT_D(5) <= ((NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND AUTOCONFIG_ACCESS AND
|
|
NOT Z3_ADR(3) AND NOT Z3_ADR(4) AND NOT Z3_ADR(5) AND NOT $OpTx$FX_DC$9)
|
|
OR (NOT Z3_ADR(2) AND NOT Z3_ADR_0 AND Z3_ADR(6) AND
|
|
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND NOT Z3_ADR(4) AND NOT Z3_ADR(5) AND
|
|
NOT $OpTx$FX_DC$9)
|
|
OR (NOT Z3_ADR_1 AND NOT Z3_ADR_0 AND Z3_ADR(6) AND
|
|
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND NOT Z3_ADR(4) AND NOT Z3_ADR(5) AND
|
|
NOT $OpTx$FX_DC$9));
|
|
|
|
FDCPE_D_OUT6: FDCPE port map (D_OUT(6),D_OUT_D(6),CLK_EXT,'0',NOT RESET);
|
|
D_OUT_D(6) <= ((NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND NOT Z3_ADR_0 AND
|
|
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND NOT Z3_ADR(4) AND NOT Z3_ADR(5) AND
|
|
NOT $OpTx$FX_DC$9)
|
|
OR (NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND NOT Z3_ADR(6) AND
|
|
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND NOT Z3_ADR(4) AND NOT Z3_ADR(5) AND
|
|
NOT $OpTx$FX_DC$9)
|
|
OR (Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND Z3_ADR(6) AND
|
|
AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND NOT Z3_ADR(4) AND NOT Z3_ADR(5) AND
|
|
NOT $OpTx$FX_DC$9));
|
|
|
|
FDCPE_D_OUT7: FDCPE port map (D_OUT(7),D_OUT_D(7),CLK_EXT,'0',NOT RESET);
|
|
D_OUT_D(7) <= (NOT Z3_ADR_1 AND Z3_ADR(6) AND AUTOCONFIG_ACCESS AND
|
|
NOT Z3_ADR(3) AND NOT Z3_ADR(4) AND NOT Z3_ADR(5) AND NOT $OpTx$FX_DC$9);
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
IDE_A(0) <= '1';
|
|
|
|
|
|
IDE_A(1) <= '1';
|
|
|
|
|
|
IDE_A(2) <= '1';
|
|
|
|
|
|
IDE_CS(0) <= '1';
|
|
|
|
|
|
IDE_CS(1) <= '1';
|
|
|
|
|
|
IDE_R <= '1';
|
|
|
|
|
|
IDE_W <= '1';
|
|
|
|
|
|
INT_OUT_I <= '0';
|
|
INT_OUT <= INT_OUT_I when INT_OUT_OE = '1' else 'Z';
|
|
INT_OUT_OE <= (LAN_INT_ENABLE AND NOT LAN_IRQ_OUT);
|
|
|
|
FDCPE_LAN_ACCESS: FDCPE port map (LAN_ACCESS,LAN_ACCESS_D,NOT FCS,NOT Z3_ADR_1/Z3_ADR_1_SETF,'0');
|
|
LAN_ACCESS_D <= ((NOT Z3)
|
|
OR (SHUT_UP)
|
|
OR (EXP24_.EXP)
|
|
OR (D(9).PIN AND NOT LAN_BASEADR(9))
|
|
OR (NOT D(9).PIN AND LAN_BASEADR(9))
|
|
OR (NOT D(8).PIN AND LAN_BASEADR(8))
|
|
OR (D(10).PIN AND NOT LAN_BASEADR(10))
|
|
OR (NOT D(10).PIN AND LAN_BASEADR(10))
|
|
OR (EXP27_.EXP)
|
|
OR (D(12).PIN AND NOT LAN_BASEADR(12))
|
|
OR (NOT D(12).PIN AND LAN_BASEADR(12))
|
|
OR (D(11).PIN AND NOT LAN_BASEADR(11))
|
|
OR (NOT D(11).PIN AND LAN_BASEADR(11))
|
|
OR (D(15).PIN AND NOT LAN_BASEADR(15))
|
|
OR (D(8).PIN AND NOT LAN_BASEADR(8)));
|
|
|
|
FDCPE_LAN_A_INIT3: FDCPE port map (LAN_A_INIT(3),'0',CLK_EXT,'0',RESET);
|
|
|
|
FDCPE_LAN_A_INIT6: FDCPE port map (LAN_A_INIT(6),NOT LAN_RST_SM_FSM_FFd1,CLK_EXT,'0',RESET);
|
|
|
|
FDCPE_LAN_BASEADR0: FDCPE port map (LAN_BASEADR(0),LAN_BASEADR_D(0),CLK_EXT,'0',NOT RESET);
|
|
LAN_BASEADR_D(0) <= ((D(0).PIN AND $OpTx$FX_DC$19)
|
|
OR (LAN_BASEADR(0) AND NOT $OpTx$FX_DC$19));
|
|
|
|
FDCPE_LAN_BASEADR1: FDCPE port map (LAN_BASEADR(1),LAN_BASEADR_D(1),CLK_EXT,'0',NOT RESET);
|
|
LAN_BASEADR_D(1) <= ((D(1).PIN AND $OpTx$FX_DC$19)
|
|
OR (LAN_BASEADR(1) AND NOT $OpTx$FX_DC$19));
|
|
|
|
FDCPE_LAN_BASEADR2: FDCPE port map (LAN_BASEADR(2),LAN_BASEADR_D(2),CLK_EXT,'0',NOT RESET);
|
|
LAN_BASEADR_D(2) <= ((D(2).PIN AND $OpTx$FX_DC$19)
|
|
OR (LAN_BASEADR(2) AND NOT $OpTx$FX_DC$19));
|
|
|
|
FDCPE_LAN_BASEADR3: FDCPE port map (LAN_BASEADR(3),LAN_BASEADR_D(3),CLK_EXT,'0',NOT RESET);
|
|
LAN_BASEADR_D(3) <= ((D(3).PIN AND $OpTx$FX_DC$19)
|
|
OR (LAN_BASEADR(3) AND NOT $OpTx$FX_DC$19));
|
|
|
|
FDCPE_LAN_BASEADR4: FDCPE port map (LAN_BASEADR(4),LAN_BASEADR_D(4),CLK_EXT,'0',NOT RESET);
|
|
LAN_BASEADR_D(4) <= ((D(4).PIN AND $OpTx$FX_DC$19)
|
|
OR (LAN_BASEADR(4) AND NOT $OpTx$FX_DC$19));
|
|
|
|
FDCPE_LAN_BASEADR5: FDCPE port map (LAN_BASEADR(5),LAN_BASEADR_D(5),CLK_EXT,'0',NOT RESET);
|
|
LAN_BASEADR_D(5) <= ((D(5).PIN AND $OpTx$FX_DC$19)
|
|
OR (LAN_BASEADR(5) AND NOT $OpTx$FX_DC$19));
|
|
|
|
FDCPE_LAN_BASEADR6: FDCPE port map (LAN_BASEADR(6),LAN_BASEADR_D(6),CLK_EXT,'0',NOT RESET);
|
|
LAN_BASEADR_D(6) <= ((D(6).PIN AND $OpTx$FX_DC$19)
|
|
OR (LAN_BASEADR(6) AND NOT $OpTx$FX_DC$19));
|
|
|
|
FDCPE_LAN_BASEADR7: FDCPE port map (LAN_BASEADR(7),LAN_BASEADR_D(7),CLK_EXT,'0',NOT RESET);
|
|
LAN_BASEADR_D(7) <= ((D(7).PIN AND $OpTx$FX_DC$19)
|
|
OR (LAN_BASEADR(7) AND NOT $OpTx$FX_DC$19));
|
|
|
|
FDCPE_LAN_BASEADR8: FDCPE port map (LAN_BASEADR(8),LAN_BASEADR_D(8),CLK_EXT,'0',NOT RESET);
|
|
LAN_BASEADR_D(8) <= ((D(8).PIN AND $OpTx$FX_DC$19)
|
|
OR (LAN_BASEADR(8) AND NOT $OpTx$FX_DC$19));
|
|
|
|
FDCPE_LAN_BASEADR9: FDCPE port map (LAN_BASEADR(9),LAN_BASEADR_D(9),CLK_EXT,'0',NOT RESET);
|
|
LAN_BASEADR_D(9) <= ((D(9).PIN AND $OpTx$FX_DC$19)
|
|
OR (LAN_BASEADR(9) AND NOT $OpTx$FX_DC$19));
|
|
|
|
FDCPE_LAN_BASEADR10: FDCPE port map (LAN_BASEADR(10),LAN_BASEADR_D(10),CLK_EXT,'0',NOT RESET);
|
|
LAN_BASEADR_D(10) <= ((D(10).PIN AND $OpTx$FX_DC$19)
|
|
OR (LAN_BASEADR(10) AND NOT $OpTx$FX_DC$19));
|
|
|
|
FDCPE_LAN_BASEADR11: FDCPE port map (LAN_BASEADR(11),LAN_BASEADR_D(11),CLK_EXT,'0',NOT RESET);
|
|
LAN_BASEADR_D(11) <= ((D(11).PIN AND $OpTx$FX_DC$19)
|
|
OR (LAN_BASEADR(11) AND NOT $OpTx$FX_DC$19));
|
|
|
|
FDCPE_LAN_BASEADR12: FDCPE port map (LAN_BASEADR(12),LAN_BASEADR_D(12),CLK_EXT,'0',NOT RESET);
|
|
LAN_BASEADR_D(12) <= ((D(12).PIN AND $OpTx$FX_DC$19)
|
|
OR (LAN_BASEADR(12) AND NOT $OpTx$FX_DC$19));
|
|
|
|
FDCPE_LAN_BASEADR13: FDCPE port map (LAN_BASEADR(13),LAN_BASEADR_D(13),CLK_EXT,'0',NOT RESET);
|
|
LAN_BASEADR_D(13) <= ((D(13).PIN AND $OpTx$FX_DC$19)
|
|
OR (LAN_BASEADR(13) AND NOT $OpTx$FX_DC$19));
|
|
|
|
FTCPE_LAN_BASEADR14: FTCPE port map (LAN_BASEADR(14),LAN_BASEADR_T(14),CLK_EXT,'0',NOT RESET);
|
|
LAN_BASEADR_T(14) <= ((D(14).PIN AND NOT LAN_BASEADR(14) AND $OpTx$FX_DC$19)
|
|
OR (NOT D(14).PIN AND NOT RW AND LAN_BASEADR(14) AND NOT Z3_ADR(2) AND
|
|
NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND AUTOCONFIG_ACCESS AND
|
|
NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5) AND NOT $OpTx$FX_DC$9)
|
|
OR (NOT RW AND LAN_BASEADR(14) AND NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND
|
|
Z3_ADR_0 AND NOT Z3_ADR(6) AND AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND
|
|
Z3_ADR(4) AND NOT Z3_ADR(5) AND NOT $OpTx$FX_DC$9 AND NOT $OpTx$FX_DC$19));
|
|
|
|
FDCPE_LAN_BASEADR15: FDCPE port map (LAN_BASEADR(15),LAN_BASEADR_D(15),CLK_EXT,'0',NOT RESET);
|
|
LAN_BASEADR_D(15) <= ((D(15).PIN AND $OpTx$FX_DC$19)
|
|
OR (LAN_BASEADR(15) AND NOT $OpTx$FX_DC$19));
|
|
|
|
|
|
LAN_CFG_I(1) <= '0';
|
|
LAN_CFG(1) <= LAN_CFG_I(1) when LAN_CFG_OE(1) = '1' else 'Z';
|
|
LAN_CFG_OE(1) <= '0';
|
|
|
|
|
|
LAN_CFG_I(2) <= '0';
|
|
LAN_CFG(2) <= LAN_CFG_I(2) when LAN_CFG_OE(2) = '1' else 'Z';
|
|
LAN_CFG_OE(2) <= '0';
|
|
|
|
|
|
LAN_CFG_I(3) <= '0';
|
|
LAN_CFG(3) <= LAN_CFG_I(3) when LAN_CFG_OE(3) = '1' else 'Z';
|
|
LAN_CFG_OE(3) <= '0';
|
|
|
|
|
|
LAN_CFG_I(4) <= '0';
|
|
LAN_CFG(4) <= LAN_CFG_I(4) when LAN_CFG_OE(4) = '1' else 'Z';
|
|
LAN_CFG_OE(4) <= '0';
|
|
|
|
|
|
LAN_CS <= ((RESET AND LAN_ACCESS)
|
|
OR (NOT RESET AND LAN_CS_RST));
|
|
|
|
FDCPE_LAN_CS_RST: FDCPE port map (LAN_CS_RST,LAN_CS_RST_D,CLK_EXT,RESET,'0');
|
|
LAN_CS_RST_D <= (NOT LAN_RST_SM_FSM_FFd2 AND NOT LAN_RST_SM_FSM_FFd3);
|
|
|
|
FDCPE_LAN_D_INIT1: FDCPE port map (LAN_D_INIT(1),LAN_RST_SM_FSM_FFd1,CLK_EXT,RESET,'0');
|
|
|
|
FDCPE_LAN_D_INIT8: FDCPE port map (LAN_D_INIT(8),NOT LAN_RST_SM_FSM_FFd1,CLK_EXT,RESET,'0');
|
|
|
|
FDCPE_LAN_INT_ENABLE: FDCPE port map (LAN_INT_ENABLE,LAN_INT_ENABLE_D,CLK_EXT,NOT RESET,'0');
|
|
LAN_INT_ENABLE_D <= ((D(15).PIN AND $OpTx$FX_DC$33)
|
|
OR (LAN_INT_ENABLE AND NOT $OpTx$FX_DC$33));
|
|
|
|
FDCPE_LAN_IRQ_D0: FDCPE port map (LAN_IRQ_D0,LAN_INT,CLK_EXT,'0',NOT RESET);
|
|
|
|
FDCPE_LAN_IRQ_OUT: FDCPE port map (LAN_IRQ_OUT,LAN_IRQ_OUT_D,CLK_EXT,'0',NOT RESET);
|
|
LAN_IRQ_OUT_D <= ((NOT LAN_INT AND LAN_IRQ_D0)
|
|
OR (NOT D(14).PIN AND LAN_INT_ENABLE AND NOT LAN_INT AND
|
|
$OpTx$FX_DC$33)
|
|
OR (LAN_INT_ENABLE AND NOT LAN_IRQ_OUT AND NOT LAN_INT AND
|
|
NOT $OpTx$FX_DC$33));
|
|
|
|
|
|
LAN_RD <= (LAN_RD_S AND $OpTx$FX_DC$35);
|
|
|
|
FDCPE_LAN_RD_S: FDCPE port map (LAN_RD_S,LAN_RD_S_D,CLK_EXT,LAN_SM_RST,'0');
|
|
LAN_RD_S_D <= ((LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2)
|
|
OR (LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd1 AND
|
|
NOT LAN_SM_FSM_FFd3)
|
|
OR (RW AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3 AND
|
|
NOT Z3_ADR(13) AND NOT $OpTx$FX_DC$29));
|
|
|
|
FDCPE_LAN_READY: FDCPE port map (LAN_READY,LAN_READY_D,CLK_EXT,LAN_SM_RST,'0');
|
|
LAN_READY_D <= ((Z3_DATA(10)/Z3_DATA(10)_CE)
|
|
OR ($OpTx$FX_DC$25 AND Z3_DATA(30)/Z3_DATA(30)_CE)
|
|
OR (NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd1 AND
|
|
LAN_SM_FSM_FFd3)
|
|
OR (LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd1 AND
|
|
NOT LAN_SM_FSM_FFd3 AND $OpTx$FX_DC$25));
|
|
|
|
FTCPE_LAN_RST_SM_FSM_FFd1: FTCPE port map (LAN_RST_SM_FSM_FFd1,LAN_RST_SM_FSM_FFd1_T,CLK_EXT,RESET,'0');
|
|
LAN_RST_SM_FSM_FFd1_T <= (NOT LAN_RST_SM_FSM_FFd1 AND LAN_RST_SM_FSM_FFd2 AND
|
|
NOT LAN_RST_SM_FSM_FFd3);
|
|
|
|
FDCPE_LAN_RST_SM_FSM_FFd2: FDCPE port map (LAN_RST_SM_FSM_FFd2,LAN_RST_SM_FSM_FFd2_D,CLK_EXT,RESET,'0');
|
|
LAN_RST_SM_FSM_FFd2_D <= ((NOT LAN_RST_SM_FSM_FFd1 AND LAN_RST_SM_FSM_FFd3)
|
|
OR (LAN_RST_SM_FSM_FFd2 AND NOT LAN_RST_SM_FSM_FFd3));
|
|
|
|
FDCPE_LAN_RST_SM_FSM_FFd3: FDCPE port map (LAN_RST_SM_FSM_FFd3,LAN_RST_SM_FSM_FFd3_D,CLK_EXT,RESET,'0');
|
|
LAN_RST_SM_FSM_FFd3_D <= LAN_RST_SM_FSM_FFd1
|
|
XOR
|
|
LAN_RST_SM_FSM_FFd3_D <= LAN_RST_SM_FSM_FFd2;
|
|
|
|
FTCPE_LAN_SM_FSM_FFd1: FTCPE port map (LAN_SM_FSM_FFd1,LAN_SM_FSM_FFd1_T,CLK_EXT,LAN_SM_RST,'0');
|
|
LAN_SM_FSM_FFd1_T <= ((NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd1 AND
|
|
LAN_SM_FSM_FFd3)
|
|
OR (LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd1 AND
|
|
NOT LAN_SM_FSM_FFd3 AND NOT $OpTx$FX_DC$25));
|
|
|
|
FTCPE_LAN_SM_FSM_FFd2: FTCPE port map (LAN_SM_FSM_FFd2,LAN_SM_FSM_FFd2_T,CLK_EXT,LAN_SM_RST,'0');
|
|
LAN_SM_FSM_FFd2_T <= ((LAN_SM_FSM_FFd1 AND NOT LAN_SM_FSM_FFd2)
|
|
OR (NOT LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd3)
|
|
OR (LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd1 AND
|
|
NOT LAN_SM_FSM_FFd3)
|
|
OR (NOT RW AND NOT LAN_SM_FSM_FFd2 AND NOT Z3_ADR(13) AND
|
|
$OpTx$FX_DC$8 AND NOT $OpTx$FX_DC$29));
|
|
|
|
FDCPE_LAN_SM_FSM_FFd3: FDCPE port map (LAN_SM_FSM_FFd3,LAN_SM_FSM_FFd3_D,CLK_EXT,LAN_SM_RST,'0');
|
|
LAN_SM_FSM_FFd3_D <= ((NOT RW AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3 AND
|
|
NOT Z3_ADR(13) AND NOT $OpTx$FX_DC$29)
|
|
OR (NOT LAN_SM_FSM_FFd1 AND LAN_SM_FSM_FFd2 AND
|
|
NOT Z3_DATA(10)/Z3_DATA(10)_CE AND NOT Z3_DATA(30)/Z3_DATA(30)_CE)
|
|
OR (NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3 AND NOT Z3_ADR(13) AND
|
|
$OpTx$FX_DC$8 AND NOT $OpTx$FX_DC$29)
|
|
OR (LAN_SM_FSM_FFd1 AND LAN_SM_FSM_FFd3)
|
|
OR ($OpTx$FX_DC$25 AND Z3_DATA(30)/Z3_DATA(30)_CE)
|
|
OR (LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd1 AND
|
|
NOT $OpTx$FX_DC$25)
|
|
OR (LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND
|
|
NOT LAN_SM_FSM_FFd3));
|
|
|
|
FDCPE_LAN_SM_FSM_FFd4: FDCPE port map (LAN_SM_FSM_FFd4,LAN_SM_FSM_FFd4_D,CLK_EXT,LAN_SM_RST,'0');
|
|
LAN_SM_FSM_FFd4_D <= ((NOT LAN_SM_FSM_FFd1 AND LAN_SM_FSM_FFd2 AND
|
|
NOT Z3_DATA(10)/Z3_DATA(10)_CE)
|
|
OR (RW AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3 AND
|
|
NOT Z3_ADR(13) AND NOT $OpTx$FX_DC$29)
|
|
OR (LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND
|
|
NOT LAN_SM_FSM_FFd3)
|
|
OR (NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd1 AND
|
|
NOT LAN_SM_FSM_FFd3)
|
|
OR (LAN_SM_FSM_FFd1 AND NOT LAN_SM_FSM_FFd3 AND
|
|
$OpTx$FX_DC$25));
|
|
|
|
FDCPE_LAN_SM_RST: FDCPE port map (LAN_SM_RST,LAN_SM_RST_D,CLK_EXT,'0','0');
|
|
LAN_SM_RST_D <= (RESET AND NOT $OpTx$FX_DC$9);
|
|
|
|
|
|
LAN_WRH <= ((LAN_WR_RST AND NOT $OpTx$FX_DC$35)
|
|
OR (LAN_WRH_S AND $OpTx$FX_DC$35));
|
|
|
|
FDCPE_LAN_WRH_S: FDCPE port map (LAN_WRH_S,LAN_WRH_S_D,CLK_EXT,LAN_SM_RST,'0');
|
|
LAN_WRH_S_D <= ((NOT LDS AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND
|
|
LAN_SM_FSM_FFd3)
|
|
OR (NOT DS0 AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd1 AND
|
|
LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd3));
|
|
|
|
|
|
LAN_WRL <= ((LAN_WR_RST AND NOT $OpTx$FX_DC$35)
|
|
OR (LAN_WRL_S AND $OpTx$FX_DC$35));
|
|
|
|
FDCPE_LAN_WRL_S: FDCPE port map (LAN_WRL_S,LAN_WRL_S_D,CLK_EXT,LAN_SM_RST,'0');
|
|
LAN_WRL_S_D <= ((NOT UDS AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND
|
|
LAN_SM_FSM_FFd3)
|
|
OR (NOT DS1 AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd1 AND
|
|
LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd3));
|
|
|
|
FDCPE_LAN_WR_RST: FDCPE port map (LAN_WR_RST,LAN_WR_RST_D,CLK_EXT,RESET,'0');
|
|
LAN_WR_RST_D <= (LAN_RST_SM_FSM_FFd2 AND LAN_RST_SM_FSM_FFd3);
|
|
|
|
|
|
MTACK_I <= '0';
|
|
MTACK <= MTACK_I when MTACK_OE = '1' else 'Z';
|
|
MTACK_OE <= '0';
|
|
|
|
|
|
OVR_I <= '0';
|
|
OVR <= OVR_I when OVR_OE = '1' else 'Z';
|
|
OVR_OE <= '0';
|
|
|
|
|
|
OWN_I <= '0';
|
|
OWN <= OWN_I when OWN_OE = '1' else 'Z';
|
|
OWN_OE <= '0';
|
|
|
|
|
|
ROM_B(0) <= '1';
|
|
|
|
|
|
ROM_B(1) <= '1';
|
|
|
|
|
|
ROM_OE <= '1';
|
|
|
|
FDCPE_SHUT_UP: FDCPE port map (SHUT_UP,SHUT_UP_D,CLK_EXT,'0',NOT RESET);
|
|
SHUT_UP_D <= (SHUT_UP AND NOT $OpTx$FX_DC$19);
|
|
|
|
|
|
SLAVE <= ((FCS)
|
|
OR (NOT LAN_ACCESS AND NOT AUTOCONFIG_ACCESS));
|
|
|
|
FDCPE_Z3_ADR2: FDCPE port map (Z3_ADR(2),A(4),NOT FCS,'0',NOT Z3_ADR_1/Z3_ADR_1_SETF);
|
|
|
|
FDCPE_Z3_ADR3: FDCPE port map (Z3_ADR(3),A(5),NOT FCS,'0',NOT Z3_ADR_1/Z3_ADR_1_SETF);
|
|
|
|
FDCPE_Z3_ADR4: FDCPE port map (Z3_ADR(4),A(6),NOT FCS,'0',NOT Z3_ADR_1/Z3_ADR_1_SETF);
|
|
|
|
FDCPE_Z3_ADR5: FDCPE port map (Z3_ADR(5),A(7),NOT FCS,'0',NOT Z3_ADR_1/Z3_ADR_1_SETF);
|
|
|
|
FDCPE_Z3_ADR6: FDCPE port map (Z3_ADR(6),A(8).PIN,NOT FCS,'0',NOT Z3_ADR_1/Z3_ADR_1_SETF);
|
|
|
|
FDCPE_Z3_ADR7: FDCPE port map (Z3_ADR(7),A(9).PIN,NOT FCS,'0',NOT Z3_ADR_1/Z3_ADR_1_SETF);
|
|
|
|
FDCPE_Z3_ADR8: FDCPE port map (Z3_ADR(8),A(10).PIN,NOT FCS,'0',NOT Z3_ADR_1/Z3_ADR_1_SETF);
|
|
|
|
FDCPE_Z3_ADR9: FDCPE port map (Z3_ADR(9),A(11).PIN,NOT FCS,'0',NOT Z3_ADR_1/Z3_ADR_1_SETF);
|
|
|
|
FDCPE_Z3_ADR10: FDCPE port map (Z3_ADR(10),A(12).PIN,NOT FCS,'0',NOT Z3_ADR_1/Z3_ADR_1_SETF);
|
|
|
|
FDCPE_Z3_ADR11: FDCPE port map (Z3_ADR(11),A(13).PIN,NOT FCS,'0',NOT Z3_ADR_1/Z3_ADR_1_SETF);
|
|
|
|
FDCPE_Z3_ADR12: FDCPE port map (Z3_ADR(12),A(14).PIN,NOT FCS,'0',NOT Z3_ADR_1/Z3_ADR_1_SETF);
|
|
|
|
FDCPE_Z3_ADR13: FDCPE port map (Z3_ADR(13),A(15).PIN,NOT FCS,'0',NOT Z3_ADR_1/Z3_ADR_1_SETF);
|
|
|
|
FDCPE_Z3_ADR_0: FDCPE port map (Z3_ADR_0,A(2),NOT FCS,'0',NOT Z3_ADR_1/Z3_ADR_1_SETF);
|
|
|
|
FDCPE_Z3_ADR_1: FDCPE port map (Z3_ADR_1,A(3),NOT FCS,'0',NOT Z3_ADR_1/Z3_ADR_1_SETF);
|
|
|
|
|
|
Z3_ADR_1/Z3_ADR_1_SETF <= (RESET AND BERR);
|
|
|
|
FDCPE_Z3_A_LOW: FDCPE port map (Z3_A_LOW,Z3_A_LOW_D,CLK_EXT,LAN_SM_RST,'0');
|
|
Z3_A_LOW_D <= ((NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND
|
|
NOT LAN_SM_FSM_FFd3 AND LAN_ACCESS AND NOT Z3_ADR(13) AND $OpTx$FX_DC$8 AND
|
|
NOT $OpTx$FX_DC$25)
|
|
OR (NOT $OpTx$FX_DC$25 AND Z3_DATA(30)/Z3_DATA(30)_CE)
|
|
OR (LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd1 AND
|
|
NOT $OpTx$FX_DC$25)
|
|
OR (LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd3 AND
|
|
NOT Z3_DATA(30)/Z3_DATA(30)_CE)
|
|
OR (NOT LAN_SM_FSM_FFd1 AND LAN_SM_FSM_FFd2 AND
|
|
NOT Z3_DATA(10)/Z3_DATA(10)_CE AND NOT Z3_DATA(30)/Z3_DATA(30)_CE));
|
|
|
|
|
|
Z3_DATA(10)/Z3_DATA(10)_CE <= (NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd1 AND
|
|
LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3);
|
|
|
|
FDCPE_Z3_DATA16: FDCPE port map (Z3_DATA(16),DQ(0).PIN,CLK_EXT,'0',LAN_SM_RST,Z3_DATA_CE(16));
|
|
Z3_DATA_CE(16) <= (LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd1 AND
|
|
LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd3);
|
|
|
|
FDCPE_Z3_DATA17: FDCPE port map (Z3_DATA(17),DQ(1).PIN,CLK_EXT,'0',LAN_SM_RST,Z3_DATA_CE(17));
|
|
Z3_DATA_CE(17) <= (LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd1 AND
|
|
LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd3);
|
|
|
|
FDCPE_Z3_DATA18: FDCPE port map (Z3_DATA(18),DQ(2).PIN,CLK_EXT,'0',LAN_SM_RST,Z3_DATA_CE(18));
|
|
Z3_DATA_CE(18) <= (LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd1 AND
|
|
LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd3);
|
|
|
|
FDCPE_Z3_DATA19: FDCPE port map (Z3_DATA(19),DQ(3).PIN,CLK_EXT,'0',LAN_SM_RST,Z3_DATA_CE(19));
|
|
Z3_DATA_CE(19) <= (LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd1 AND
|
|
LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd3);
|
|
|
|
FDCPE_Z3_DATA20: FDCPE port map (Z3_DATA(20),DQ(4).PIN,CLK_EXT,'0',LAN_SM_RST,Z3_DATA_CE(20));
|
|
Z3_DATA_CE(20) <= (LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd1 AND
|
|
LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd3);
|
|
|
|
FDCPE_Z3_DATA21: FDCPE port map (Z3_DATA(21),DQ(5).PIN,CLK_EXT,'0',LAN_SM_RST,Z3_DATA_CE(21));
|
|
Z3_DATA_CE(21) <= (LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd1 AND
|
|
LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd3);
|
|
|
|
FDCPE_Z3_DATA22: FDCPE port map (Z3_DATA(22),DQ(6).PIN,CLK_EXT,'0',LAN_SM_RST,Z3_DATA_CE(22));
|
|
Z3_DATA_CE(22) <= (LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd1 AND
|
|
LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd3);
|
|
|
|
FDCPE_Z3_DATA23: FDCPE port map (Z3_DATA(23),DQ(7).PIN,CLK_EXT,'0',LAN_SM_RST,Z3_DATA_CE(23));
|
|
Z3_DATA_CE(23) <= (LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd1 AND
|
|
LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd3);
|
|
|
|
FDCPE_Z3_DATA24: FDCPE port map (Z3_DATA(24),DQ(8).PIN,CLK_EXT,'0',LAN_SM_RST,Z3_DATA_CE(24));
|
|
Z3_DATA_CE(24) <= (LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd1 AND
|
|
LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd3);
|
|
|
|
FDCPE_Z3_DATA25: FDCPE port map (Z3_DATA(25),DQ(9).PIN,CLK_EXT,'0',LAN_SM_RST,Z3_DATA_CE(25));
|
|
Z3_DATA_CE(25) <= (LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd1 AND
|
|
LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd3);
|
|
|
|
FDCPE_Z3_DATA26: FDCPE port map (Z3_DATA(26),DQ(10).PIN,CLK_EXT,'0',LAN_SM_RST,Z3_DATA_CE(26));
|
|
Z3_DATA_CE(26) <= (LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd1 AND
|
|
LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd3);
|
|
|
|
FDCPE_Z3_DATA27: FDCPE port map (Z3_DATA(27),DQ(11).PIN,CLK_EXT,'0',LAN_SM_RST,Z3_DATA_CE(27));
|
|
Z3_DATA_CE(27) <= (LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd1 AND
|
|
LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd3);
|
|
|
|
FDCPE_Z3_DATA28: FDCPE port map (Z3_DATA(28),DQ(12).PIN,CLK_EXT,'0',LAN_SM_RST,Z3_DATA_CE(28));
|
|
Z3_DATA_CE(28) <= (LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd1 AND
|
|
LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd3);
|
|
|
|
FDCPE_Z3_DATA29: FDCPE port map (Z3_DATA(29),DQ(13).PIN,CLK_EXT,'0',LAN_SM_RST,Z3_DATA_CE(29));
|
|
Z3_DATA_CE(29) <= (LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd1 AND
|
|
LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd3);
|
|
|
|
|
|
Z3_DATA(30)/Z3_DATA(30)_CE <= (LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd1 AND
|
|
LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd3);
|
|
|
|
FDCPE_Z3_DATA30: FDCPE port map (Z3_DATA(30),DQ(14).PIN,CLK_EXT,'0',LAN_SM_RST,Z3_DATA_CE(30));
|
|
Z3_DATA_CE(30) <= (LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd1 AND
|
|
LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd3);
|
|
|
|
FDCPE_Z3_DATA31: FDCPE port map (Z3_DATA(31),DQ(15).PIN,CLK_EXT,'0',LAN_SM_RST,Z3_DATA_CE(31));
|
|
Z3_DATA_CE(31) <= (LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd1 AND
|
|
LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd3);
|
|
|
|
Register Legend:
|
|
FDCPE (Q,D,C,CLR,PRE,CE);
|
|
FTCPE (Q,D,C,CLR,PRE,CE);
|
|
LDCP (Q,D,G,CLR,PRE);
|
|
|
|
****************************** Device Pin Out *****************************
|
|
|
|
Device : XC95288XL-10-TQ144
|
|
|
|
|
|
Pin Signal Pin Signal
|
|
No. Name No. Name
|
|
1 VCC 73 VCC
|
|
2 D<0> 74 A<15>
|
|
3 A_LAN<1> 75 AUTOBOOT_OFF
|
|
4 A_LAN<0> 76 LAN_WRL
|
|
5 A_LAN<3> 77 FCS
|
|
6 A_LAN<2> 78 DS1
|
|
7 A_LAN<5> 79 Z3
|
|
8 VCC 80 TIE
|
|
9 A_LAN<4> 81 UDS
|
|
10 A_LAN<7> 82 LDS
|
|
11 A_LAN<6> 83 RW
|
|
12 LAN_CFG<1> 84 VCC
|
|
13 LAN_CFG<3> 85 DTACK
|
|
14 D<6> 86 A<23>
|
|
15 D<3> 87 A<22>
|
|
16 D<7> 88 A<21>
|
|
17 D<1> 89 GND
|
|
18 GND 90 GND
|
|
19 D<8> 91 A<20>
|
|
20 D<5> 92 A<19>
|
|
21 D<4> 93 DS0
|
|
22 IDE_CS<0> 94 A<18>
|
|
23 IDE_CS<1> 95 A<17>
|
|
24 IDE_A<0> 96 MTACK
|
|
25 IDE_A<2> 97 A<16>
|
|
26 IDE_A<1> 98 BERR
|
|
27 IDE_R 99 GND
|
|
28 IDE_W 100 OVR
|
|
29 GND 101 TIE
|
|
30 CLK_EXT 102 TIE
|
|
31 TIE 103 TIE
|
|
32 INT_OUT 104 CFIN
|
|
33 TIE 105 CFOUT
|
|
34 CP_CS 106 SLAVE
|
|
35 ROM_OE 107 OWN
|
|
36 GND 108 GND
|
|
37 VCC 109 VCC
|
|
38 TIE 110 LAN_CFG<4>
|
|
39 D<2> 111 LAN_INT
|
|
40 D<9> 112 DQ<15>
|
|
41 D<10> 113 DQ<13>
|
|
42 VCC 114 GND
|
|
43 D<11> 115 DQ<11>
|
|
44 D<12> 116 DQ<9>
|
|
45 D<13> 117 DQ<1>
|
|
46 D<14> 118 DQ<0>
|
|
47 GND 119 DQ<3>
|
|
48 D<15> 120 DQ<2>
|
|
49 A<5> 121 DQ<5>
|
|
50 A<4> 122 TDO
|
|
51 A<6> 123 GND
|
|
52 A<3> 124 DQ<4>
|
|
53 A<7> 125 DQ<7>
|
|
54 A<2> 126 DQ<6>
|
|
55 VCC 127 VCC
|
|
56 A<8> 128 DQ<8>
|
|
57 TIE 129 DQ<10>
|
|
58 A<9> 130 DQ<12>
|
|
59 A<10> 131 DQ<14>
|
|
60 A<11> 132 LAN_WRH
|
|
61 A<12> 133 LAN_CS
|
|
62 GND 134 LAN_RD
|
|
63 TDI 135 LAN_CFG<2>
|
|
64 A<13> 136 A_LAN<12>
|
|
65 TMS 137 A_LAN<13>
|
|
66 A<14> 138 A_LAN<10>
|
|
67 TCK 139 A_LAN<11>
|
|
68 ROM_B<0> 140 A_LAN<8>
|
|
69 ROM_B<1> 141 VCC
|
|
70 CP_WE 142 A_LAN<9>
|
|
71 CP_RD 143 RESET
|
|
72 GND 144 GND
|
|
|
|
|
|
Legend : NC = Not Connected, unbonded pin
|
|
PGND = Unused I/O configured as additional Ground pin
|
|
TIE = Unused I/O floating -- must tie to VCC, GND or other signal
|
|
KPR = Unused I/O with weak keeper (leave unconnected)
|
|
VCC = Dedicated Power Pin
|
|
GND = Dedicated Ground Pin
|
|
TDI = Test Data In, JTAG pin
|
|
TDO = Test Data Out, JTAG pin
|
|
TCK = Test Clock, JTAG pin
|
|
TMS = Test Mode Select, JTAG pin
|
|
PROHIBITED = User reserved pin
|
|
**************************** Compiler Options ****************************
|
|
|
|
Following is a list of all global compiler options used by the fitter run.
|
|
|
|
Device(s) Specified : xc95288xl-10-TQ144
|
|
Optimization Method : DENSITY
|
|
Multi-Level Logic Optimization : ON
|
|
Ignore Timing Specifications : OFF
|
|
Default Register Power Up Value : LOW
|
|
Keep User Location Constraints : ON
|
|
What-You-See-Is-What-You-Get : OFF
|
|
Exhaustive Fitting : OFF
|
|
Keep Unused Inputs : OFF
|
|
Slew Rate : FAST
|
|
Power Mode : STD
|
|
Ground on Unused IOs : OFF
|
|
Set I/O Pin Termination : FLOAT
|
|
Global Clock Optimization : ON
|
|
Global Set/Reset Optimization : ON
|
|
Global Ouput Enable Optimization : ON
|
|
Input Limit : 54
|
|
Pterm Limit : 34
|