2547 lines
94 KiB
Plaintext
2547 lines
94 KiB
Plaintext
MDF Database: version 1.0
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MDF_INFO | LAN_IDE_CP | XC95288XL-10-TQ144
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MACROCELL | 3 | 1 | D_OUT<0>
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ATTRIBUTES | 8816390 | 0
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OUTPUTMC | 1 | 3 | 1
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INPUTS | 8 | D<0> | D_OUT_or0002/D_OUT_or0002_D2 | autoconfig | DQ<0>.PIN | $OpTx$FX_DC$3 | DQ<8>.PIN | RW | SLAVE
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INPUTMC | 5 | 3 | 1 | 13 | 4 | 10 | 12 | 5 | 12 | 13 | 13
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INPUTP | 3 | 217 | 231 | 158
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EQ | 7 |
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!D<0>.D = !D<0> & D_OUT_or0002/D_OUT_or0002_D2
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# autoconfig & !DQ<8>.PIN &
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!D_OUT_or0002/D_OUT_or0002_D2 & $OpTx$FX_DC$3
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# autoconfig & !DQ<0>.PIN &
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!D_OUT_or0002/D_OUT_or0002_D2 & !$OpTx$FX_DC$3;
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!D<0>.CLK = CLK_EXT; // GCK
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D<0>.OE = RW & !SLAVE;
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GLOBALS | 1 | 2 | CLK_EXT
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MACROCELL | 4 | 13 | D_OUT<10>
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ATTRIBUTES | 8816390 | 0
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OUTPUTMC | 1 | 4 | 13
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INPUTS | 8 | D<10> | D_OUT_or0002/D_OUT_or0002_D2 | autoconfig | DQ<2>.PIN | $OpTx$FX_DC$1 | DQ<10>.PIN | RW | SLAVE
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INPUTMC | 5 | 4 | 13 | 13 | 4 | 10 | 12 | 5 | 14 | 13 | 13
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INPUTP | 3 | 220 | 234 | 158
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EQ | 7 |
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!D<10>.D = !D<10> & D_OUT_or0002/D_OUT_or0002_D2
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# autoconfig & !DQ<10>.PIN &
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!D_OUT_or0002/D_OUT_or0002_D2 & $OpTx$FX_DC$1
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# autoconfig & !DQ<2>.PIN &
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!D_OUT_or0002/D_OUT_or0002_D2 & !$OpTx$FX_DC$1;
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!D<10>.CLK = CLK_EXT; // GCK
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D<10>.OE = RW & !SLAVE;
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GLOBALS | 1 | 2 | CLK_EXT
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MACROCELL | 4 | 14 | D_OUT<11>
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ATTRIBUTES | 8816390 | 0
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OUTPUTMC | 1 | 4 | 14
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INPUTS | 8 | D<11> | D_OUT_or0002/D_OUT_or0002_D2 | autoconfig | DQ<3>.PIN | $OpTx$FX_DC$1 | DQ<11>.PIN | RW | SLAVE
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INPUTMC | 5 | 4 | 14 | 13 | 4 | 10 | 12 | 5 | 14 | 13 | 13
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INPUTP | 3 | 219 | 207 | 158
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EQ | 7 |
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!D<11>.D = !D<11> & D_OUT_or0002/D_OUT_or0002_D2
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# autoconfig & !DQ<11>.PIN &
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!D_OUT_or0002/D_OUT_or0002_D2 & $OpTx$FX_DC$1
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# autoconfig & !DQ<3>.PIN &
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!D_OUT_or0002/D_OUT_or0002_D2 & !$OpTx$FX_DC$1;
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!D<11>.CLK = CLK_EXT; // GCK
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D<11>.OE = RW & !SLAVE;
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GLOBALS | 1 | 2 | CLK_EXT
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MACROCELL | 1 | 14 | D_OUT<1>
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ATTRIBUTES | 8816390 | 0
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OUTPUTMC | 1 | 1 | 14
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INPUTS | 8 | D<1> | D_OUT_or0002/D_OUT_or0002_D2 | autoconfig | DQ<1>.PIN | $OpTx$FX_DC$3 | DQ<9>.PIN | RW | SLAVE
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INPUTMC | 5 | 1 | 14 | 13 | 4 | 10 | 12 | 5 | 12 | 13 | 13
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INPUTP | 3 | 216 | 209 | 158
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EQ | 7 |
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!D<1>.D = !D<1> & D_OUT_or0002/D_OUT_or0002_D2
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# autoconfig & !DQ<9>.PIN &
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!D_OUT_or0002/D_OUT_or0002_D2 & $OpTx$FX_DC$3
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# autoconfig & !DQ<1>.PIN &
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!D_OUT_or0002/D_OUT_or0002_D2 & !$OpTx$FX_DC$3;
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!D<1>.CLK = CLK_EXT; // GCK
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D<1>.OE = RW & !SLAVE;
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GLOBALS | 1 | 2 | CLK_EXT
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MACROCELL | 4 | 9 | D_OUT<2>
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ATTRIBUTES | 8816390 | 0
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OUTPUTMC | 1 | 4 | 9
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INPUTS | 8 | D<2> | D_OUT_or0002/D_OUT_or0002_D2 | autoconfig | DQ<2>.PIN | $OpTx$FX_DC$3 | DQ<10>.PIN | RW | SLAVE
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INPUTMC | 5 | 4 | 9 | 13 | 4 | 10 | 12 | 5 | 12 | 13 | 13
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INPUTP | 3 | 220 | 234 | 158
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EQ | 7 |
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!D<2>.D = !D<2> & D_OUT_or0002/D_OUT_or0002_D2
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# autoconfig & !DQ<10>.PIN &
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!D_OUT_or0002/D_OUT_or0002_D2 & $OpTx$FX_DC$3
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# autoconfig & !DQ<2>.PIN &
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!D_OUT_or0002/D_OUT_or0002_D2 & !$OpTx$FX_DC$3;
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!D<2>.CLK = CLK_EXT; // GCK
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D<2>.OE = RW & !SLAVE;
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GLOBALS | 1 | 2 | CLK_EXT
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MACROCELL | 1 | 11 | D_OUT<3>
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ATTRIBUTES | 8816390 | 0
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OUTPUTMC | 1 | 1 | 11
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INPUTS | 8 | D<3> | D_OUT_or0002/D_OUT_or0002_D2 | autoconfig | DQ<3>.PIN | $OpTx$FX_DC$3 | DQ<11>.PIN | RW | SLAVE
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INPUTMC | 5 | 1 | 11 | 13 | 4 | 10 | 12 | 5 | 12 | 13 | 13
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INPUTP | 3 | 219 | 207 | 158
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EQ | 7 |
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!D<3>.D = !D<3> & D_OUT_or0002/D_OUT_or0002_D2
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# autoconfig & !DQ<11>.PIN &
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!D_OUT_or0002/D_OUT_or0002_D2 & $OpTx$FX_DC$3
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# autoconfig & !DQ<3>.PIN &
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!D_OUT_or0002/D_OUT_or0002_D2 & !$OpTx$FX_DC$3;
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!D<3>.CLK = CLK_EXT; // GCK
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D<3>.OE = RW & !SLAVE;
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GLOBALS | 1 | 2 | CLK_EXT
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MACROCELL | 0 | 5 | D_OUT<4>
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ATTRIBUTES | 8816390 | 0
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OUTPUTMC | 1 | 0 | 5
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INPUTS | 8 | D<4> | D_OUT_or0002/D_OUT_or0002_D2 | autoconfig | DQ<4>.PIN | $OpTx$FX_DC$3 | DQ<12>.PIN | RW | SLAVE
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INPUTMC | 5 | 0 | 5 | 13 | 4 | 10 | 12 | 5 | 12 | 13 | 13
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INPUTP | 3 | 225 | 235 | 158
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EQ | 7 |
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!D<4>.D = !D<4> & D_OUT_or0002/D_OUT_or0002_D2
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# autoconfig & !DQ<12>.PIN &
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!D_OUT_or0002/D_OUT_or0002_D2 & $OpTx$FX_DC$3
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# autoconfig & !DQ<4>.PIN &
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!D_OUT_or0002/D_OUT_or0002_D2 & !$OpTx$FX_DC$3;
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!D<4>.CLK = CLK_EXT; // GCK
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D<4>.OE = RW & !SLAVE;
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GLOBALS | 1 | 2 | CLK_EXT
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MACROCELL | 0 | 4 | D_OUT<5>
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ATTRIBUTES | 8816390 | 0
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OUTPUTMC | 1 | 0 | 4
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INPUTS | 8 | D<5> | D_OUT_or0002/D_OUT_or0002_D2 | autoconfig | DQ<5>.PIN | $OpTx$FX_DC$3 | DQ<13>.PIN | RW | SLAVE
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INPUTMC | 5 | 0 | 4 | 13 | 4 | 10 | 12 | 5 | 12 | 13 | 13
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INPUTP | 3 | 221 | 204 | 158
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EQ | 7 |
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!D<5>.D = !D<5> & D_OUT_or0002/D_OUT_or0002_D2
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# autoconfig & !DQ<13>.PIN &
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!D_OUT_or0002/D_OUT_or0002_D2 & $OpTx$FX_DC$3
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# autoconfig & !DQ<5>.PIN &
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!D_OUT_or0002/D_OUT_or0002_D2 & !$OpTx$FX_DC$3;
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!D<5>.CLK = CLK_EXT; // GCK
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D<5>.OE = RW & !SLAVE;
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GLOBALS | 1 | 2 | CLK_EXT
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MACROCELL | 1 | 9 | D_OUT<6>
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ATTRIBUTES | 8816390 | 0
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OUTPUTMC | 1 | 1 | 9
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INPUTS | 8 | D<6> | D_OUT_or0002/D_OUT_or0002_D2 | autoconfig | DQ<6>.PIN | $OpTx$FX_DC$3 | DQ<14>.PIN | RW | SLAVE
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INPUTMC | 5 | 1 | 9 | 13 | 4 | 10 | 12 | 5 | 12 | 13 | 13
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INPUTP | 3 | 227 | 236 | 158
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EQ | 7 |
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!D<6>.D = !D<6> & D_OUT_or0002/D_OUT_or0002_D2
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# autoconfig & !DQ<14>.PIN &
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!D_OUT_or0002/D_OUT_or0002_D2 & $OpTx$FX_DC$3
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# autoconfig & !DQ<6>.PIN &
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!D_OUT_or0002/D_OUT_or0002_D2 & !$OpTx$FX_DC$3;
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!D<6>.CLK = CLK_EXT; // GCK
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D<6>.OE = RW & !SLAVE;
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GLOBALS | 1 | 2 | CLK_EXT
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MACROCELL | 1 | 13 | D_OUT<7>
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ATTRIBUTES | 8816390 | 0
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OUTPUTMC | 1 | 1 | 13
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INPUTS | 8 | D<7> | D_OUT_or0002/D_OUT_or0002_D2 | autoconfig | DQ<7>.PIN | $OpTx$FX_DC$3 | DQ<15>.PIN | RW | SLAVE
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INPUTMC | 5 | 1 | 13 | 13 | 4 | 10 | 12 | 5 | 12 | 13 | 13
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INPUTP | 3 | 226 | 202 | 158
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EQ | 7 |
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!D<7>.D = !D<7> & D_OUT_or0002/D_OUT_or0002_D2
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# autoconfig & !DQ<15>.PIN &
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!D_OUT_or0002/D_OUT_or0002_D2 & $OpTx$FX_DC$3
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# autoconfig & !DQ<7>.PIN &
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!D_OUT_or0002/D_OUT_or0002_D2 & !$OpTx$FX_DC$3;
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!D<7>.CLK = CLK_EXT; // GCK
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D<7>.OE = RW & !SLAVE;
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GLOBALS | 1 | 2 | CLK_EXT
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MACROCELL | 1 | 16 | D_OUT<8>
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ATTRIBUTES | 8816390 | 0
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OUTPUTMC | 1 | 1 | 16
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INPUTS | 8 | D<8> | D_OUT_or0002/D_OUT_or0002_D2 | autoconfig | DQ<0>.PIN | $OpTx$FX_DC$1 | DQ<8>.PIN | RW | SLAVE
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INPUTMC | 5 | 1 | 16 | 13 | 4 | 10 | 12 | 5 | 14 | 13 | 13
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INPUTP | 3 | 217 | 231 | 158
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EQ | 7 |
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!D<8>.D = !D<8> & D_OUT_or0002/D_OUT_or0002_D2
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# autoconfig & !DQ<8>.PIN &
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!D_OUT_or0002/D_OUT_or0002_D2 & $OpTx$FX_DC$1
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# autoconfig & !DQ<0>.PIN &
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!D_OUT_or0002/D_OUT_or0002_D2 & !$OpTx$FX_DC$1;
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!D<8>.CLK = CLK_EXT; // GCK
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D<8>.OE = RW & !SLAVE;
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GLOBALS | 1 | 2 | CLK_EXT
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MACROCELL | 4 | 11 | D_OUT<9>
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ATTRIBUTES | 8816390 | 0
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OUTPUTMC | 1 | 4 | 11
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INPUTS | 8 | D<9> | D_OUT_or0002/D_OUT_or0002_D2 | autoconfig | DQ<1>.PIN | $OpTx$FX_DC$1 | DQ<9>.PIN | RW | SLAVE
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INPUTMC | 5 | 4 | 11 | 13 | 4 | 10 | 12 | 5 | 14 | 13 | 13
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INPUTP | 3 | 216 | 209 | 158
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EQ | 7 |
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!D<9>.D = !D<9> & D_OUT_or0002/D_OUT_or0002_D2
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# autoconfig & !DQ<9>.PIN &
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!D_OUT_or0002/D_OUT_or0002_D2 & $OpTx$FX_DC$1
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# autoconfig & !DQ<1>.PIN &
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!D_OUT_or0002/D_OUT_or0002_D2 & !$OpTx$FX_DC$1;
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!D<9>.CLK = CLK_EXT; // GCK
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D<9>.OE = RW & !SLAVE;
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GLOBALS | 1 | 2 | CLK_EXT
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MACROCELL | 4 | 16 | D_OUT<12>
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ATTRIBUTES | 8816390 | 0
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OUTPUTMC | 1 | 4 | 16
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INPUTS | 9 | D<12> | D_OUT_or0002/D_OUT_or0002_D2 | Dout1<0> | autoconfig | DQ<4>.PIN | $OpTx$FX_DC$1 | DQ<12>.PIN | RW | SLAVE
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INPUTMC | 6 | 4 | 16 | 13 | 4 | 13 | 0 | 10 | 12 | 5 | 14 | 13 | 13
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INPUTP | 3 | 225 | 235 | 158
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EQ | 9 |
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D<12>.D = D<12> & D_OUT_or0002/D_OUT_or0002_D2
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# Dout1<0> & !autoconfig &
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!D_OUT_or0002/D_OUT_or0002_D2
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# autoconfig & DQ<12>.PIN &
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!D_OUT_or0002/D_OUT_or0002_D2 & $OpTx$FX_DC$1
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# autoconfig & DQ<4>.PIN &
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!D_OUT_or0002/D_OUT_or0002_D2 & !$OpTx$FX_DC$1;
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!D<12>.CLK = CLK_EXT; // GCK
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D<12>.OE = RW & !SLAVE;
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GLOBALS | 1 | 2 | CLK_EXT
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MACROCELL | 6 | 2 | D_OUT<13>
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ATTRIBUTES | 8816390 | 0
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OUTPUTMC | 1 | 6 | 2
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INPUTS | 9 | D<13> | D_OUT_or0002/D_OUT_or0002_D2 | Dout1<1> | autoconfig | DQ<5>.PIN | $OpTx$FX_DC$1 | DQ<13>.PIN | RW | SLAVE
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INPUTMC | 6 | 6 | 2 | 13 | 4 | 13 | 15 | 10 | 12 | 5 | 14 | 13 | 13
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INPUTP | 3 | 221 | 204 | 158
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EQ | 9 |
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D<13>.D = D<13> & D_OUT_or0002/D_OUT_or0002_D2
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# Dout1<1> & !autoconfig &
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!D_OUT_or0002/D_OUT_or0002_D2
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# autoconfig & DQ<13>.PIN &
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!D_OUT_or0002/D_OUT_or0002_D2 & $OpTx$FX_DC$1
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# autoconfig & DQ<5>.PIN &
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!D_OUT_or0002/D_OUT_or0002_D2 & !$OpTx$FX_DC$1;
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!D<13>.CLK = CLK_EXT; // GCK
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D<13>.OE = RW & !SLAVE;
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GLOBALS | 1 | 2 | CLK_EXT
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MACROCELL | 6 | 4 | D_OUT<14>
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ATTRIBUTES | 8816390 | 0
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OUTPUTMC | 1 | 6 | 4
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INPUTS | 9 | D<14> | D_OUT_or0002/D_OUT_or0002_D2 | Dout1<2> | autoconfig | DQ<6>.PIN | $OpTx$FX_DC$1 | DQ<14>.PIN | RW | SLAVE
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INPUTMC | 6 | 6 | 4 | 13 | 4 | 13 | 3 | 10 | 12 | 5 | 14 | 13 | 13
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INPUTP | 3 | 227 | 236 | 158
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EQ | 9 |
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D<14>.D = D<14> & D_OUT_or0002/D_OUT_or0002_D2
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# Dout1<2> & !autoconfig &
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!D_OUT_or0002/D_OUT_or0002_D2
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# autoconfig & DQ<14>.PIN &
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!D_OUT_or0002/D_OUT_or0002_D2 & $OpTx$FX_DC$1
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# autoconfig & DQ<6>.PIN &
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!D_OUT_or0002/D_OUT_or0002_D2 & !$OpTx$FX_DC$1;
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!D<14>.CLK = CLK_EXT; // GCK
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D<14>.OE = RW & !SLAVE;
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GLOBALS | 1 | 2 | CLK_EXT
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MACROCELL | 6 | 11 | D_OUT<15>
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ATTRIBUTES | 8816390 | 0
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OUTPUTMC | 1 | 6 | 11
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INPUTS | 9 | D<15> | D_OUT_or0002/D_OUT_or0002_D2 | Dout1<3> | autoconfig | DQ<7>.PIN | $OpTx$FX_DC$1 | DQ<15>.PIN | RW | SLAVE
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INPUTMC | 6 | 6 | 11 | 13 | 4 | 8 | 17 | 10 | 12 | 5 | 14 | 13 | 13
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INPUTP | 3 | 226 | 202 | 158
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EQ | 9 |
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D<15>.D = D<15> & D_OUT_or0002/D_OUT_or0002_D2
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# Dout1<3> & !autoconfig &
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!D_OUT_or0002/D_OUT_or0002_D2
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# autoconfig & DQ<15>.PIN &
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!D_OUT_or0002/D_OUT_or0002_D2 & $OpTx$FX_DC$1
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# autoconfig & DQ<7>.PIN &
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!D_OUT_or0002/D_OUT_or0002_D2 & !$OpTx$FX_DC$1;
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!D<15>.CLK = CLK_EXT; // GCK
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D<15>.OE = RW & !SLAVE;
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GLOBALS | 1 | 2 | CLK_EXT
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MACROCELL | 13 | 8 | AUTO_CONFIG_DONE<1>
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ATTRIBUTES | 8520676 | 0
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OUTPUTMC | 12 | 13 | 6 | 13 | 0 | 13 | 14 | 13 | 2 | 8 | 17 | 13 | 10 | 3 | 17 | 13 | 9 | 13 | 1 | 13 | 4 | 13 | 16 | 13 | 17
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INPUTS | 4 | AUTO_CONFIG_DONE_CYCLE<1> | lan_adr_sw/lan_adr_sw_CLKF | RESET | AS
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INPUTMC | 2 | 13 | 6 | 15 | 6
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INPUTP | 2 | 263 | 152
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EQ | 4 |
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AUTO_CONFIG_DONE<1>.D = AUTO_CONFIG_DONE_CYCLE<1>;
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AUTO_CONFIG_DONE<1>.CLK = !lan_adr_sw/lan_adr_sw_CLKF;
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AUTO_CONFIG_DONE<1>.AP = !RESET;
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AUTO_CONFIG_DONE<1>.CE = AS;
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MACROCELL | 13 | 7 | AUTO_CONFIG_DONE<0>
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ATTRIBUTES | 8520676 | 0
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OUTPUTMC | 8 | 13 | 5 | 13 | 6 | 8 | 10 | 13 | 4 | 13 | 1 | 13 | 10 | 3 | 17 | 13 | 16
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INPUTS | 4 | AUTO_CONFIG_DONE_CYCLE<0> | lan_adr_sw/lan_adr_sw_CLKF | RESET | AS
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INPUTMC | 2 | 13 | 5 | 15 | 6
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INPUTP | 2 | 263 | 152
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EQ | 4 |
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AUTO_CONFIG_DONE<0>.D = AUTO_CONFIG_DONE_CYCLE<0>;
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AUTO_CONFIG_DONE<0>.CLK = !lan_adr_sw/lan_adr_sw_CLKF;
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AUTO_CONFIG_DONE<0>.AP = !RESET;
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AUTO_CONFIG_DONE<0>.CE = AS;
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MACROCELL | 9 | 17 | LAN_INT_ENABLE
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ATTRIBUTES | 8520612 | 0
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OUTPUTMC | 3 | 9 | 17 | 2 | 17 | 2 | 13
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INPUTS | 10 | LAN_INT_ENABLE | $OpTx$FX_DC$34 | D<15>.PIN | A<15> | RW | lan_adr | LDS | UDS | lan_adr_sw/lan_adr_sw_CLKF | RESET
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INPUTMC | 4 | 9 | 17 | 0 | 3 | 14 | 13 | 15 | 6
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INPUTP | 6 | 89 | 139 | 158 | 157 | 155 | 263
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EQ | 5 |
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LAN_INT_ENABLE.D = LAN_INT_ENABLE & !$OpTx$FX_DC$34
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# !D<15>.PIN & A<15> & !RW & !lan_adr & !UDS
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# !D<15>.PIN & A<15> & !RW & !lan_adr & !LDS;
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LAN_INT_ENABLE.CLK = !lan_adr_sw/lan_adr_sw_CLKF;
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LAN_INT_ENABLE.AP = !RESET;
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MACROCELL | 13 | 5 | AUTO_CONFIG_DONE_CYCLE<0>
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ATTRIBUTES | 8520612 | 0
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OUTPUTMC | 2 | 13 | 7 | 13 | 5
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INPUTS | 14 | AUTO_CONFIG_DONE_CYCLE<0> | $OpTx$FX_DC$31 | AUTO_CONFIG_DONE<0> | IDE_OFF | RW | A<5> | A<4> | A<2> | A<1> | A<6> | A<3> | AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2 | lan_adr_sw/lan_adr_sw_CLKF | RESET
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INPUTMC | 5 | 13 | 5 | 8 | 11 | 13 | 7 | 0 | 2 | 15 | 6
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INPUTP | 9 | 142 | 158 | 91 | 97 | 101 | 107 | 98 | 99 | 263
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EQ | 7 |
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AUTO_CONFIG_DONE_CYCLE<0>.D = AUTO_CONFIG_DONE_CYCLE<0> & !$OpTx$FX_DC$31
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# !AUTO_CONFIG_DONE<0> & IDE_OFF & $OpTx$FX_DC$31
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# !AUTO_CONFIG_DONE<0> & !RW & !A<5> & !A<4> & A<2> &
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!A<1> & A<6> & A<3> &
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AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2;
|
|
AUTO_CONFIG_DONE_CYCLE<0>.CLK = !lan_adr_sw/lan_adr_sw_CLKF;
|
|
AUTO_CONFIG_DONE_CYCLE<0>.AP = !RESET;
|
|
|
|
MACROCELL | 13 | 6 | AUTO_CONFIG_DONE_CYCLE<1>
|
|
ATTRIBUTES | 8520612 | 0
|
|
OUTPUTMC | 2 | 13 | 8 | 13 | 6
|
|
INPUTS | 14 | AUTO_CONFIG_DONE_CYCLE<1> | $OpTx$FX_DC$31 | AUTO_CONFIG_DONE<1> | AUTO_CONFIG_DONE<0> | RW | A<5> | A<4> | A<1> | A<6> | A<3> | AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2 | A<2> | lan_adr_sw/lan_adr_sw_CLKF | RESET
|
|
INPUTMC | 6 | 13 | 6 | 8 | 11 | 13 | 8 | 13 | 7 | 0 | 2 | 15 | 6
|
|
INPUTP | 8 | 158 | 91 | 97 | 107 | 98 | 99 | 101 | 263
|
|
EQ | 9 |
|
|
AUTO_CONFIG_DONE_CYCLE<1>.D = AUTO_CONFIG_DONE_CYCLE<1> & !$OpTx$FX_DC$31
|
|
# AUTO_CONFIG_DONE<1> & AUTO_CONFIG_DONE<0> & !RW &
|
|
!A<5> & !A<4> & !A<1> & A<6> & A<3> &
|
|
AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2
|
|
# !AUTO_CONFIG_DONE<1> & !AUTO_CONFIG_DONE<0> & !RW &
|
|
!A<5> & !A<4> & A<2> & !A<1> & A<6> & A<3> &
|
|
AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2;
|
|
AUTO_CONFIG_DONE_CYCLE<1>.CLK = !lan_adr_sw/lan_adr_sw_CLKF;
|
|
AUTO_CONFIG_DONE_CYCLE<1>.AP = !RESET;
|
|
|
|
MACROCELL | 2 | 16 | CP_BASEADR<0>
|
|
ATTRIBUTES | 8520612 | 0
|
|
OUTPUTMC | 3 | 2 | 16 | 4 | 0 | 2 | 17
|
|
INPUTS | 11 | D<8>.PIN | CP_BASEADR_not0001/CP_BASEADR_not0001_D2 | CP_BASEADR<0> | lan_adr_sw/lan_adr_sw_CLKF | RESET | A<15> | RW | D<14>.PIN | lan_adr | LAN_IRQ_D0 | LDS
|
|
INPUTMC | 5 | 3 | 17 | 2 | 16 | 15 | 6 | 14 | 13 | 2 | 9
|
|
INPUTP | 6 | 32 | 263 | 139 | 158 | 81 | 157
|
|
EXPORTS | 1 | 2 | 17
|
|
EQ | 8 |
|
|
CP_BASEADR<0>.D = D<8>.PIN &
|
|
CP_BASEADR_not0001/CP_BASEADR_not0001_D2
|
|
# CP_BASEADR<0> &
|
|
!CP_BASEADR_not0001/CP_BASEADR_not0001_D2;
|
|
CP_BASEADR<0>.CLK = !lan_adr_sw/lan_adr_sw_CLKF;
|
|
CP_BASEADR<0>.AP = !RESET;
|
|
CP_BASEADR<0>.EXP = A<15> & !RW & D<14>.PIN & !lan_adr & !LAN_IRQ_D0 &
|
|
!LDS
|
|
|
|
MACROCELL | 2 | 15 | CP_BASEADR<1>
|
|
ATTRIBUTES | 8520612 | 0
|
|
OUTPUTMC | 2 | 2 | 15 | 4 | 0
|
|
INPUTS | 5 | D<9>.PIN | CP_BASEADR_not0001/CP_BASEADR_not0001_D2 | CP_BASEADR<1> | lan_adr_sw/lan_adr_sw_CLKF | RESET
|
|
INPUTMC | 3 | 3 | 17 | 2 | 15 | 15 | 6
|
|
INPUTP | 2 | 73 | 263
|
|
EQ | 6 |
|
|
CP_BASEADR<1>.D = D<9>.PIN &
|
|
CP_BASEADR_not0001/CP_BASEADR_not0001_D2
|
|
# CP_BASEADR<1> &
|
|
!CP_BASEADR_not0001/CP_BASEADR_not0001_D2;
|
|
CP_BASEADR<1>.CLK = !lan_adr_sw/lan_adr_sw_CLKF;
|
|
CP_BASEADR<1>.AP = !RESET;
|
|
|
|
MACROCELL | 12 | 17 | CP_BASEADR<2>
|
|
ATTRIBUTES | 8520612 | 0
|
|
OUTPUTMC | 3 | 12 | 17 | 4 | 0 | 4 | 2
|
|
INPUTS | 5 | D<10>.PIN | CP_BASEADR_not0001/CP_BASEADR_not0001_D2 | CP_BASEADR<2> | lan_adr_sw/lan_adr_sw_CLKF | RESET
|
|
INPUTMC | 3 | 3 | 17 | 12 | 17 | 15 | 6
|
|
INPUTP | 2 | 74 | 263
|
|
EQ | 6 |
|
|
CP_BASEADR<2>.D = D<10>.PIN &
|
|
CP_BASEADR_not0001/CP_BASEADR_not0001_D2
|
|
# CP_BASEADR<2> &
|
|
!CP_BASEADR_not0001/CP_BASEADR_not0001_D2;
|
|
CP_BASEADR<2>.CLK = !lan_adr_sw/lan_adr_sw_CLKF;
|
|
CP_BASEADR<2>.AP = !RESET;
|
|
|
|
MACROCELL | 12 | 16 | CP_BASEADR<3>
|
|
ATTRIBUTES | 8520612 | 0
|
|
OUTPUTMC | 2 | 12 | 16 | 4 | 2
|
|
INPUTS | 5 | D<11>.PIN | CP_BASEADR_not0001/CP_BASEADR_not0001_D2 | CP_BASEADR<3> | lan_adr_sw/lan_adr_sw_CLKF | RESET
|
|
INPUTMC | 3 | 3 | 17 | 12 | 16 | 15 | 6
|
|
INPUTP | 2 | 77 | 263
|
|
EQ | 6 |
|
|
CP_BASEADR<3>.D = D<11>.PIN &
|
|
CP_BASEADR_not0001/CP_BASEADR_not0001_D2
|
|
# CP_BASEADR<3> &
|
|
!CP_BASEADR_not0001/CP_BASEADR_not0001_D2;
|
|
CP_BASEADR<3>.CLK = !lan_adr_sw/lan_adr_sw_CLKF;
|
|
CP_BASEADR<3>.AP = !RESET;
|
|
|
|
MACROCELL | 12 | 15 | CP_BASEADR<4>
|
|
ATTRIBUTES | 8520612 | 0
|
|
OUTPUTMC | 2 | 12 | 15 | 4 | 2
|
|
INPUTS | 5 | D<12>.PIN | CP_BASEADR_not0001/CP_BASEADR_not0001_D2 | CP_BASEADR<4> | lan_adr_sw/lan_adr_sw_CLKF | RESET
|
|
INPUTMC | 3 | 3 | 17 | 12 | 15 | 15 | 6
|
|
INPUTP | 2 | 78 | 263
|
|
EQ | 6 |
|
|
CP_BASEADR<4>.D = D<12>.PIN &
|
|
CP_BASEADR_not0001/CP_BASEADR_not0001_D2
|
|
# CP_BASEADR<4> &
|
|
!CP_BASEADR_not0001/CP_BASEADR_not0001_D2;
|
|
CP_BASEADR<4>.CLK = !lan_adr_sw/lan_adr_sw_CLKF;
|
|
CP_BASEADR<4>.AP = !RESET;
|
|
|
|
MACROCELL | 12 | 14 | CP_BASEADR<5>
|
|
ATTRIBUTES | 8520612 | 0
|
|
OUTPUTMC | 2 | 12 | 14 | 4 | 3
|
|
INPUTS | 5 | D<13>.PIN | CP_BASEADR_not0001/CP_BASEADR_not0001_D2 | CP_BASEADR<5> | lan_adr_sw/lan_adr_sw_CLKF | RESET
|
|
INPUTMC | 3 | 3 | 17 | 12 | 14 | 15 | 6
|
|
INPUTP | 2 | 80 | 263
|
|
EQ | 6 |
|
|
CP_BASEADR<5>.D = D<13>.PIN &
|
|
CP_BASEADR_not0001/CP_BASEADR_not0001_D2
|
|
# CP_BASEADR<5> &
|
|
!CP_BASEADR_not0001/CP_BASEADR_not0001_D2;
|
|
CP_BASEADR<5>.CLK = !lan_adr_sw/lan_adr_sw_CLKF;
|
|
CP_BASEADR<5>.AP = !RESET;
|
|
|
|
MACROCELL | 2 | 14 | CP_BASEADR<6>
|
|
ATTRIBUTES | 8520612 | 0
|
|
OUTPUTMC | 2 | 2 | 14 | 4 | 1
|
|
INPUTS | 5 | D<14>.PIN | CP_BASEADR_not0001/CP_BASEADR_not0001_D2 | CP_BASEADR<6> | lan_adr_sw/lan_adr_sw_CLKF | RESET
|
|
INPUTMC | 3 | 3 | 17 | 2 | 14 | 15 | 6
|
|
INPUTP | 2 | 81 | 263
|
|
EQ | 6 |
|
|
CP_BASEADR<6>.D = D<14>.PIN &
|
|
CP_BASEADR_not0001/CP_BASEADR_not0001_D2
|
|
# CP_BASEADR<6> &
|
|
!CP_BASEADR_not0001/CP_BASEADR_not0001_D2;
|
|
CP_BASEADR<6>.CLK = !lan_adr_sw/lan_adr_sw_CLKF;
|
|
CP_BASEADR<6>.AP = !RESET;
|
|
|
|
MACROCELL | 12 | 12 | CP_BASEADR<7>
|
|
ATTRIBUTES | 8520612 | 0
|
|
OUTPUTMC | 2 | 12 | 12 | 4 | 3
|
|
INPUTS | 5 | D<15>.PIN | CP_BASEADR_not0001/CP_BASEADR_not0001_D2 | CP_BASEADR<7> | lan_adr_sw/lan_adr_sw_CLKF | RESET
|
|
INPUTMC | 3 | 3 | 17 | 12 | 12 | 15 | 6
|
|
INPUTP | 2 | 89 | 263
|
|
EQ | 6 |
|
|
CP_BASEADR<7>.D = D<15>.PIN &
|
|
CP_BASEADR_not0001/CP_BASEADR_not0001_D2
|
|
# CP_BASEADR<7> &
|
|
!CP_BASEADR_not0001/CP_BASEADR_not0001_D2;
|
|
CP_BASEADR<7>.CLK = !lan_adr_sw/lan_adr_sw_CLKF;
|
|
CP_BASEADR<7>.AP = !RESET;
|
|
|
|
MACROCELL | 13 | 0 | Dout1<0>
|
|
ATTRIBUTES | 8520612 | 0
|
|
OUTPUTMC | 2 | 4 | 16 | 13 | 0
|
|
INPUTS | 13 | Dout1<0> | AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2 | A<5> | A<4> | A<2> | A<6> | A<3> | AUTO_CONFIG_DONE<1> | A<1> | EXP29_.EXP | lan_adr_sw/lan_adr_sw_CLKF | RESET | EXP31_.EXP
|
|
INPUTMC | 6 | 13 | 0 | 0 | 2 | 13 | 8 | 13 | 1 | 15 | 6 | 13 | 17
|
|
INPUTP | 7 | 91 | 97 | 101 | 98 | 99 | 107 | 263
|
|
IMPORTS | 2 | 13 | 1 | 13 | 17
|
|
EQ | 25 |
|
|
!Dout1<0>.D = !Dout1<0> &
|
|
!AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2
|
|
# !A<5> & !A<4> & !A<2> & A<6> & !A<3> &
|
|
AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2
|
|
# AUTO_CONFIG_DONE<1> & !A<5> & !A<4> & !A<2> &
|
|
!A<1> & !A<3> &
|
|
AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2
|
|
;Imported pterms FB14_2
|
|
# A<5> & !A<4> & A<2> & A<1> & !A<6> &
|
|
AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2
|
|
# A<5> & !A<4> & A<2> & !A<6> & !A<3> &
|
|
AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2
|
|
# !A<5> & A<4> & !A<2> & !A<6> & A<3> &
|
|
AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2
|
|
# !A<5> & A<4> & A<1> & !A<6> & A<3> &
|
|
AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2
|
|
# AUTO_CONFIG_DONE<1> & AUTO_CONFIG_DONE<0> & !A<4> &
|
|
A<2> & !A<6> & !A<3> &
|
|
AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2
|
|
;Imported pterms FB14_18
|
|
# AUTO_CONFIG_DONE<1> & !A<5> & A<2> & !A<1> &
|
|
!A<6> & !A<3> &
|
|
AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2;
|
|
Dout1<0>.CLK = !lan_adr_sw/lan_adr_sw_CLKF;
|
|
Dout1<0>.AP = !RESET;
|
|
|
|
MACROCELL | 13 | 15 | Dout1<1>
|
|
ATTRIBUTES | 8520612 | 0
|
|
OUTPUTMC | 2 | 6 | 2 | 13 | 15
|
|
INPUTS | 11 | Dout1<1> | AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2 | A<5> | A<4> | A<2> | A<3> | A<6> | ROM_B_0_OBUF$BUF1.EXP | EXP30_.EXP | lan_adr_sw/lan_adr_sw_CLKF | RESET
|
|
INPUTMC | 5 | 13 | 15 | 0 | 2 | 13 | 14 | 13 | 16 | 15 | 6
|
|
INPUTP | 6 | 91 | 97 | 101 | 99 | 98 | 263
|
|
IMPORTS | 2 | 13 | 14 | 13 | 16
|
|
EQ | 29 |
|
|
!Dout1<1>.D = !Dout1<1> &
|
|
!AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2
|
|
# !A<5> & !A<4> & !A<2> & !A<3> &
|
|
AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2
|
|
# !A<5> & A<4> & A<2> & !A<6> & A<3> &
|
|
AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2
|
|
;Imported pterms FB14_15
|
|
# !A<5> & A<4> & !A<1> & !A<6> & A<3> &
|
|
AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2
|
|
# AUTO_CONFIG_DONE<1> & !A<5> & !A<2> & A<1> &
|
|
!A<6> & !A<3> &
|
|
AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2
|
|
# AUTO_CONFIG_DONE<1> & !A<4> & A<2> & !A<1> &
|
|
!A<6> & !A<3> &
|
|
AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2
|
|
# A<5> & !A<4> & A<2> & !A<1> & !A<6> & !A<3> &
|
|
AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2
|
|
;Imported pterms FB14_17
|
|
# !AUTO_CONFIG_DONE<1> & !A<5> & A<4> & A<2> &
|
|
!A<1> & !A<6> &
|
|
AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2
|
|
# !AUTO_CONFIG_DONE<1> & !A<5> & !A<4> & A<1> &
|
|
!A<6> & !A<3> &
|
|
AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2
|
|
# AUTO_CONFIG_DONE<0> & !A<5> & !A<4> & A<1> &
|
|
!A<6> & !A<3> &
|
|
AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2;
|
|
Dout1<1>.CLK = !lan_adr_sw/lan_adr_sw_CLKF;
|
|
Dout1<1>.AP = !RESET;
|
|
|
|
MACROCELL | 13 | 3 | Dout1<2>
|
|
ATTRIBUTES | 8520612 | 0
|
|
OUTPUTMC | 2 | 6 | 4 | 13 | 3
|
|
INPUTS | 12 | Dout1<2> | AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2 | A<5> | A<4> | A<2> | A<6> | A<3> | A<1> | ROM_B_0_OBUF$BUF2.EXP | D_OUT_or0002/D_OUT_or0002_D2.EXP | lan_adr_sw/lan_adr_sw_CLKF | RESET
|
|
INPUTMC | 5 | 13 | 3 | 0 | 2 | 13 | 2 | 13 | 4 | 15 | 6
|
|
INPUTP | 7 | 91 | 97 | 101 | 98 | 99 | 107 | 263
|
|
IMPORTS | 2 | 13 | 2 | 13 | 4
|
|
EQ | 25 |
|
|
!Dout1<2>.D = !Dout1<2> &
|
|
!AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2
|
|
# !A<5> & !A<4> & !A<2> & A<1> & !A<3> &
|
|
AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2
|
|
# !A<5> & !A<4> & !A<2> & A<6> & !A<3> &
|
|
AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2
|
|
;Imported pterms FB14_3
|
|
# !AUTO_CONFIG_DONE<1> & !A<4> & A<2> & A<1> &
|
|
!A<6> & !A<3> &
|
|
AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2
|
|
# !A<5> & A<4> & A<2> & A<1> & !A<6> & !A<3> &
|
|
AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2
|
|
# !A<5> & A<4> & A<2> & !A<1> & !A<6> & A<3> &
|
|
AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2
|
|
;Imported pterms FB14_5
|
|
# !AUTO_CONFIG_DONE<0> & !A<4> & A<2> & A<1> &
|
|
!A<6> & !A<3> &
|
|
AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2
|
|
# A<5> & !A<4> & A<2> & A<1> & !A<6> & !A<3> &
|
|
AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2
|
|
# AUTO_CONFIG_DONE<1> & !A<5> & !A<4> & A<2> &
|
|
!A<1> & !A<6> & !A<3> &
|
|
AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2;
|
|
Dout1<2>.CLK = !lan_adr_sw/lan_adr_sw_CLKF;
|
|
Dout1<2>.AP = !RESET;
|
|
|
|
MACROCELL | 8 | 17 | Dout1<3>
|
|
ATTRIBUTES | 8520612 | 0
|
|
OUTPUTMC | 2 | 6 | 11 | 8 | 17
|
|
INPUTS | 12 | Dout1<3> | AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2 | A<5> | A<2> | A<1> | A<6> | A<3> | AUTO_CONFIG_DONE<1> | EXP26_.EXP | lan_adr_sw/lan_adr_sw_CLKF | RESET | LAN_BASEADR<0>.EXP
|
|
INPUTMC | 6 | 8 | 17 | 0 | 2 | 13 | 8 | 8 | 0 | 15 | 6 | 8 | 16
|
|
INPUTP | 6 | 91 | 101 | 107 | 98 | 99 | 263
|
|
IMPORTS | 2 | 8 | 0 | 8 | 16
|
|
EQ | 19 |
|
|
!Dout1<3>.D = !Dout1<3> &
|
|
!AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2
|
|
# AUTO_CONFIG_DONE<1> & !A<5> & A<1> & !A<6> &
|
|
!A<3> &
|
|
AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2
|
|
# !A<5> & !A<2> & A<1> & !A<6> & !A<3> &
|
|
AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2
|
|
;Imported pterms FB9_1
|
|
# !A<5> & !A<4> & !A<2> & A<6> & !A<3> &
|
|
AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2
|
|
# A<5> & !A<4> & A<2> & !A<1> & !A<6> & !A<3> &
|
|
AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2
|
|
# !A<5> & A<4> & !A<2> & !A<1> & !A<6> & A<3> &
|
|
AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2
|
|
;Imported pterms FB9_17
|
|
# !A<5> & A<4> & A<2> & A<1> & !A<6> &
|
|
AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2;
|
|
Dout1<3>.CLK = !lan_adr_sw/lan_adr_sw_CLKF;
|
|
Dout1<3>.AP = !RESET;
|
|
|
|
MACROCELL | 2 | 12 | IDE_BASEADR<0>
|
|
ATTRIBUTES | 8520612 | 0
|
|
OUTPUTMC | 2 | 2 | 12 | 10 | 16
|
|
INPUTS | 5 | D<8>.PIN | IDE_BASEADR_not0001/IDE_BASEADR_not0001_D2 | IDE_BASEADR<0> | lan_adr_sw/lan_adr_sw_CLKF | RESET
|
|
INPUTMC | 3 | 13 | 9 | 2 | 12 | 15 | 6
|
|
INPUTP | 2 | 32 | 263
|
|
EQ | 6 |
|
|
IDE_BASEADR<0>.D = D<8>.PIN &
|
|
IDE_BASEADR_not0001/IDE_BASEADR_not0001_D2
|
|
# IDE_BASEADR<0> &
|
|
!IDE_BASEADR_not0001/IDE_BASEADR_not0001_D2;
|
|
IDE_BASEADR<0>.CLK = !lan_adr_sw/lan_adr_sw_CLKF;
|
|
IDE_BASEADR<0>.AP = !RESET;
|
|
|
|
MACROCELL | 2 | 11 | IDE_BASEADR<1>
|
|
ATTRIBUTES | 8520612 | 0
|
|
OUTPUTMC | 2 | 2 | 11 | 10 | 16
|
|
INPUTS | 5 | D<9>.PIN | IDE_BASEADR_not0001/IDE_BASEADR_not0001_D2 | IDE_BASEADR<1> | lan_adr_sw/lan_adr_sw_CLKF | RESET
|
|
INPUTMC | 3 | 13 | 9 | 2 | 11 | 15 | 6
|
|
INPUTP | 2 | 73 | 263
|
|
EQ | 6 |
|
|
IDE_BASEADR<1>.D = D<9>.PIN &
|
|
IDE_BASEADR_not0001/IDE_BASEADR_not0001_D2
|
|
# IDE_BASEADR<1> &
|
|
!IDE_BASEADR_not0001/IDE_BASEADR_not0001_D2;
|
|
IDE_BASEADR<1>.CLK = !lan_adr_sw/lan_adr_sw_CLKF;
|
|
IDE_BASEADR<1>.AP = !RESET;
|
|
|
|
MACROCELL | 12 | 11 | IDE_BASEADR<2>
|
|
ATTRIBUTES | 8520612 | 0
|
|
OUTPUTMC | 3 | 12 | 11 | 10 | 16 | 10 | 0
|
|
INPUTS | 5 | D<10>.PIN | IDE_BASEADR_not0001/IDE_BASEADR_not0001_D2 | IDE_BASEADR<2> | lan_adr_sw/lan_adr_sw_CLKF | RESET
|
|
INPUTMC | 3 | 13 | 9 | 12 | 11 | 15 | 6
|
|
INPUTP | 2 | 74 | 263
|
|
EQ | 6 |
|
|
IDE_BASEADR<2>.D = D<10>.PIN &
|
|
IDE_BASEADR_not0001/IDE_BASEADR_not0001_D2
|
|
# IDE_BASEADR<2> &
|
|
!IDE_BASEADR_not0001/IDE_BASEADR_not0001_D2;
|
|
IDE_BASEADR<2>.CLK = !lan_adr_sw/lan_adr_sw_CLKF;
|
|
IDE_BASEADR<2>.AP = !RESET;
|
|
|
|
MACROCELL | 12 | 10 | IDE_BASEADR<3>
|
|
ATTRIBUTES | 8520612 | 0
|
|
OUTPUTMC | 2 | 12 | 10 | 10 | 0
|
|
INPUTS | 5 | D<11>.PIN | IDE_BASEADR_not0001/IDE_BASEADR_not0001_D2 | IDE_BASEADR<3> | lan_adr_sw/lan_adr_sw_CLKF | RESET
|
|
INPUTMC | 3 | 13 | 9 | 12 | 10 | 15 | 6
|
|
INPUTP | 2 | 77 | 263
|
|
EQ | 6 |
|
|
IDE_BASEADR<3>.D = D<11>.PIN &
|
|
IDE_BASEADR_not0001/IDE_BASEADR_not0001_D2
|
|
# IDE_BASEADR<3> &
|
|
!IDE_BASEADR_not0001/IDE_BASEADR_not0001_D2;
|
|
IDE_BASEADR<3>.CLK = !lan_adr_sw/lan_adr_sw_CLKF;
|
|
IDE_BASEADR<3>.AP = !RESET;
|
|
|
|
MACROCELL | 12 | 9 | IDE_BASEADR<4>
|
|
ATTRIBUTES | 8520612 | 0
|
|
OUTPUTMC | 2 | 12 | 9 | 10 | 1
|
|
INPUTS | 5 | D<12>.PIN | IDE_BASEADR_not0001/IDE_BASEADR_not0001_D2 | IDE_BASEADR<4> | lan_adr_sw/lan_adr_sw_CLKF | RESET
|
|
INPUTMC | 3 | 13 | 9 | 12 | 9 | 15 | 6
|
|
INPUTP | 2 | 78 | 263
|
|
EQ | 6 |
|
|
IDE_BASEADR<4>.D = D<12>.PIN &
|
|
IDE_BASEADR_not0001/IDE_BASEADR_not0001_D2
|
|
# IDE_BASEADR<4> &
|
|
!IDE_BASEADR_not0001/IDE_BASEADR_not0001_D2;
|
|
IDE_BASEADR<4>.CLK = !lan_adr_sw/lan_adr_sw_CLKF;
|
|
IDE_BASEADR<4>.AP = !RESET;
|
|
|
|
MACROCELL | 12 | 8 | IDE_BASEADR<5>
|
|
ATTRIBUTES | 8520612 | 0
|
|
OUTPUTMC | 2 | 12 | 8 | 10 | 0
|
|
INPUTS | 5 | D<13>.PIN | IDE_BASEADR_not0001/IDE_BASEADR_not0001_D2 | IDE_BASEADR<5> | lan_adr_sw/lan_adr_sw_CLKF | RESET
|
|
INPUTMC | 3 | 13 | 9 | 12 | 8 | 15 | 6
|
|
INPUTP | 2 | 80 | 263
|
|
EQ | 6 |
|
|
IDE_BASEADR<5>.D = D<13>.PIN &
|
|
IDE_BASEADR_not0001/IDE_BASEADR_not0001_D2
|
|
# IDE_BASEADR<5> &
|
|
!IDE_BASEADR_not0001/IDE_BASEADR_not0001_D2;
|
|
IDE_BASEADR<5>.CLK = !lan_adr_sw/lan_adr_sw_CLKF;
|
|
IDE_BASEADR<5>.AP = !RESET;
|
|
|
|
MACROCELL | 2 | 10 | IDE_BASEADR<6>
|
|
ATTRIBUTES | 8520612 | 0
|
|
OUTPUTMC | 2 | 2 | 10 | 10 | 17
|
|
INPUTS | 5 | D<14>.PIN | IDE_BASEADR_not0001/IDE_BASEADR_not0001_D2 | IDE_BASEADR<6> | lan_adr_sw/lan_adr_sw_CLKF | RESET
|
|
INPUTMC | 3 | 13 | 9 | 2 | 10 | 15 | 6
|
|
INPUTP | 2 | 81 | 263
|
|
EQ | 6 |
|
|
IDE_BASEADR<6>.D = D<14>.PIN &
|
|
IDE_BASEADR_not0001/IDE_BASEADR_not0001_D2
|
|
# IDE_BASEADR<6> &
|
|
!IDE_BASEADR_not0001/IDE_BASEADR_not0001_D2;
|
|
IDE_BASEADR<6>.CLK = !lan_adr_sw/lan_adr_sw_CLKF;
|
|
IDE_BASEADR<6>.AP = !RESET;
|
|
|
|
MACROCELL | 12 | 7 | IDE_BASEADR<7>
|
|
ATTRIBUTES | 8520612 | 0
|
|
OUTPUTMC | 2 | 12 | 7 | 10 | 1
|
|
INPUTS | 5 | D<15>.PIN | IDE_BASEADR_not0001/IDE_BASEADR_not0001_D2 | IDE_BASEADR<7> | lan_adr_sw/lan_adr_sw_CLKF | RESET
|
|
INPUTMC | 3 | 13 | 9 | 12 | 7 | 15 | 6
|
|
INPUTP | 2 | 89 | 263
|
|
EQ | 6 |
|
|
IDE_BASEADR<7>.D = D<15>.PIN &
|
|
IDE_BASEADR_not0001/IDE_BASEADR_not0001_D2
|
|
# IDE_BASEADR<7> &
|
|
!IDE_BASEADR_not0001/IDE_BASEADR_not0001_D2;
|
|
IDE_BASEADR<7>.CLK = !lan_adr_sw/lan_adr_sw_CLKF;
|
|
IDE_BASEADR<7>.AP = !RESET;
|
|
|
|
MACROCELL | 8 | 16 | LAN_BASEADR<0>
|
|
ATTRIBUTES | 8520612 | 0
|
|
OUTPUTMC | 3 | 8 | 16 | 15 | 17 | 8 | 17
|
|
INPUTS | 11 | D<8>.PIN | LAN_BASEADR_not0001/LAN_BASEADR_not0001_D2 | LAN_BASEADR<0> | lan_adr_sw/lan_adr_sw_CLKF | RESET | A<5> | A<4> | A<2> | A<1> | A<6> | AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2
|
|
INPUTMC | 4 | 8 | 10 | 8 | 16 | 15 | 6 | 0 | 2
|
|
INPUTP | 7 | 32 | 263 | 91 | 97 | 101 | 107 | 98
|
|
EXPORTS | 1 | 8 | 17
|
|
EQ | 8 |
|
|
LAN_BASEADR<0>.D = D<8>.PIN &
|
|
LAN_BASEADR_not0001/LAN_BASEADR_not0001_D2
|
|
# LAN_BASEADR<0> &
|
|
!LAN_BASEADR_not0001/LAN_BASEADR_not0001_D2;
|
|
LAN_BASEADR<0>.CLK = !lan_adr_sw/lan_adr_sw_CLKF;
|
|
LAN_BASEADR<0>.AP = !RESET;
|
|
LAN_BASEADR<0>.EXP = !A<5> & A<4> & A<2> & A<1> & !A<6> &
|
|
AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2
|
|
|
|
MACROCELL | 8 | 15 | LAN_BASEADR<1>
|
|
ATTRIBUTES | 8520612 | 0
|
|
OUTPUTMC | 2 | 8 | 15 | 15 | 16
|
|
INPUTS | 5 | D<9>.PIN | LAN_BASEADR_not0001/LAN_BASEADR_not0001_D2 | LAN_BASEADR<1> | lan_adr_sw/lan_adr_sw_CLKF | RESET
|
|
INPUTMC | 3 | 8 | 10 | 8 | 15 | 15 | 6
|
|
INPUTP | 2 | 73 | 263
|
|
EQ | 6 |
|
|
LAN_BASEADR<1>.D = D<9>.PIN &
|
|
LAN_BASEADR_not0001/LAN_BASEADR_not0001_D2
|
|
# LAN_BASEADR<1> &
|
|
!LAN_BASEADR_not0001/LAN_BASEADR_not0001_D2;
|
|
LAN_BASEADR<1>.CLK = !lan_adr_sw/lan_adr_sw_CLKF;
|
|
LAN_BASEADR<1>.AP = !RESET;
|
|
|
|
MACROCELL | 8 | 14 | LAN_BASEADR<2>
|
|
ATTRIBUTES | 8520612 | 0
|
|
OUTPUTMC | 2 | 8 | 14 | 15 | 15
|
|
INPUTS | 5 | D<10>.PIN | LAN_BASEADR_not0001/LAN_BASEADR_not0001_D2 | LAN_BASEADR<2> | lan_adr_sw/lan_adr_sw_CLKF | RESET
|
|
INPUTMC | 3 | 8 | 10 | 8 | 14 | 15 | 6
|
|
INPUTP | 2 | 74 | 263
|
|
EQ | 6 |
|
|
LAN_BASEADR<2>.D = D<10>.PIN &
|
|
LAN_BASEADR_not0001/LAN_BASEADR_not0001_D2
|
|
# LAN_BASEADR<2> &
|
|
!LAN_BASEADR_not0001/LAN_BASEADR_not0001_D2;
|
|
LAN_BASEADR<2>.CLK = !lan_adr_sw/lan_adr_sw_CLKF;
|
|
LAN_BASEADR<2>.AP = !RESET;
|
|
|
|
MACROCELL | 8 | 13 | LAN_BASEADR<3>
|
|
ATTRIBUTES | 8520612 | 0
|
|
OUTPUTMC | 2 | 8 | 13 | 15 | 14
|
|
INPUTS | 5 | D<11>.PIN | LAN_BASEADR_not0001/LAN_BASEADR_not0001_D2 | LAN_BASEADR<3> | lan_adr_sw/lan_adr_sw_CLKF | RESET
|
|
INPUTMC | 3 | 8 | 10 | 8 | 13 | 15 | 6
|
|
INPUTP | 2 | 77 | 263
|
|
EQ | 6 |
|
|
LAN_BASEADR<3>.D = D<11>.PIN &
|
|
LAN_BASEADR_not0001/LAN_BASEADR_not0001_D2
|
|
# LAN_BASEADR<3> &
|
|
!LAN_BASEADR_not0001/LAN_BASEADR_not0001_D2;
|
|
LAN_BASEADR<3>.CLK = !lan_adr_sw/lan_adr_sw_CLKF;
|
|
LAN_BASEADR<3>.AP = !RESET;
|
|
|
|
MACROCELL | 8 | 12 | LAN_BASEADR<4>
|
|
ATTRIBUTES | 8520612 | 0
|
|
OUTPUTMC | 2 | 8 | 12 | 15 | 13
|
|
INPUTS | 5 | D<12>.PIN | LAN_BASEADR_not0001/LAN_BASEADR_not0001_D2 | LAN_BASEADR<4> | lan_adr_sw/lan_adr_sw_CLKF | RESET
|
|
INPUTMC | 3 | 8 | 10 | 8 | 12 | 15 | 6
|
|
INPUTP | 2 | 78 | 263
|
|
EQ | 6 |
|
|
LAN_BASEADR<4>.D = D<12>.PIN &
|
|
LAN_BASEADR_not0001/LAN_BASEADR_not0001_D2
|
|
# LAN_BASEADR<4> &
|
|
!LAN_BASEADR_not0001/LAN_BASEADR_not0001_D2;
|
|
LAN_BASEADR<4>.CLK = !lan_adr_sw/lan_adr_sw_CLKF;
|
|
LAN_BASEADR<4>.AP = !RESET;
|
|
|
|
MACROCELL | 14 | 17 | LAN_BASEADR<5>
|
|
ATTRIBUTES | 8520612 | 0
|
|
OUTPUTMC | 2 | 14 | 17 | 15 | 12
|
|
INPUTS | 5 | D<13>.PIN | LAN_BASEADR_not0001/LAN_BASEADR_not0001_D2 | LAN_BASEADR<5> | lan_adr_sw/lan_adr_sw_CLKF | RESET
|
|
INPUTMC | 3 | 8 | 10 | 14 | 17 | 15 | 6
|
|
INPUTP | 2 | 80 | 263
|
|
EQ | 6 |
|
|
LAN_BASEADR<5>.D = D<13>.PIN &
|
|
LAN_BASEADR_not0001/LAN_BASEADR_not0001_D2
|
|
# LAN_BASEADR<5> &
|
|
!LAN_BASEADR_not0001/LAN_BASEADR_not0001_D2;
|
|
LAN_BASEADR<5>.CLK = !lan_adr_sw/lan_adr_sw_CLKF;
|
|
LAN_BASEADR<5>.AP = !RESET;
|
|
|
|
MACROCELL | 14 | 16 | LAN_BASEADR<6>
|
|
ATTRIBUTES | 8520612 | 0
|
|
OUTPUTMC | 2 | 14 | 16 | 15 | 11
|
|
INPUTS | 5 | D<14>.PIN | LAN_BASEADR_not0001/LAN_BASEADR_not0001_D2 | LAN_BASEADR<6> | lan_adr_sw/lan_adr_sw_CLKF | RESET
|
|
INPUTMC | 3 | 8 | 10 | 14 | 16 | 15 | 6
|
|
INPUTP | 2 | 81 | 263
|
|
EQ | 6 |
|
|
LAN_BASEADR<6>.D = D<14>.PIN &
|
|
LAN_BASEADR_not0001/LAN_BASEADR_not0001_D2
|
|
# LAN_BASEADR<6> &
|
|
!LAN_BASEADR_not0001/LAN_BASEADR_not0001_D2;
|
|
LAN_BASEADR<6>.CLK = !lan_adr_sw/lan_adr_sw_CLKF;
|
|
LAN_BASEADR<6>.AP = !RESET;
|
|
|
|
MACROCELL | 14 | 15 | LAN_BASEADR<7>
|
|
ATTRIBUTES | 8520612 | 0
|
|
OUTPUTMC | 2 | 14 | 15 | 15 | 10
|
|
INPUTS | 5 | D<15>.PIN | LAN_BASEADR_not0001/LAN_BASEADR_not0001_D2 | LAN_BASEADR<7> | lan_adr_sw/lan_adr_sw_CLKF | RESET
|
|
INPUTMC | 3 | 8 | 10 | 14 | 15 | 15 | 6
|
|
INPUTP | 2 | 89 | 263
|
|
EQ | 6 |
|
|
LAN_BASEADR<7>.D = D<15>.PIN &
|
|
LAN_BASEADR_not0001/LAN_BASEADR_not0001_D2
|
|
# LAN_BASEADR<7> &
|
|
!LAN_BASEADR_not0001/LAN_BASEADR_not0001_D2;
|
|
LAN_BASEADR<7>.CLK = !lan_adr_sw/lan_adr_sw_CLKF;
|
|
LAN_BASEADR<7>.AP = !RESET;
|
|
|
|
MACROCELL | 2 | 17 | LAN_IRQ_OUT
|
|
ATTRIBUTES | 8520612 | 0
|
|
OUTPUTMC | 2 | 2 | 17 | 2 | 13
|
|
INPUTS | 9 | LAN_INT | LAN_INT_ENABLE | LAN_IRQ_D0 | LAN_IRQ_OUT | $OpTx$FX_DC$34 | EXP22_.EXP | CP_BASEADR<0>.EXP | lan_adr_sw/lan_adr_sw_CLKF | RESET
|
|
INPUTMC | 7 | 9 | 17 | 2 | 9 | 2 | 17 | 0 | 3 | 2 | 0 | 2 | 16 | 15 | 6
|
|
INPUTP | 2 | 201 | 263
|
|
IMPORTS | 2 | 2 | 0 | 2 | 16
|
|
EQ | 11 |
|
|
LAN_IRQ_OUT.D = LAN_INT
|
|
# LAN_INT_ENABLE & !LAN_IRQ_D0
|
|
# LAN_IRQ_OUT & !LAN_IRQ_D0 & !$OpTx$FX_DC$34
|
|
;Imported pterms FB3_1
|
|
# A<15> & !RW & D<14>.PIN & !lan_adr & !LAN_IRQ_D0 &
|
|
!UDS
|
|
;Imported pterms FB3_17
|
|
# A<15> & !RW & D<14>.PIN & !lan_adr & !LAN_IRQ_D0 &
|
|
!LDS;
|
|
LAN_IRQ_OUT.CLK = !lan_adr_sw/lan_adr_sw_CLKF;
|
|
LAN_IRQ_OUT.AP = !RESET;
|
|
|
|
MACROCELL | 4 | 1 | cp
|
|
ATTRIBUTES | 8782758 | 0
|
|
OUTPUTMC | 23 | 9 | 14 | 9 | 15 | 3 | 5 | 5 | 5 | 5 | 7 | 5 | 2 | 5 | 4 | 3 | 4 | 3 | 11 | 3 | 7 | 1 | 1 | 3 | 13 | 1 | 4 | 1 | 2 | 5 | 9 | 5 | 13 | 13 | 13 | 13 | 4 | 5 | 12 | 5 | 14 | 5 | 17 | 5 | 10 | 5 | 15
|
|
INPUTS | 7 | SHUT_UP<1> | CP_BASEADR<6> | A<22> | EXP23_.EXP | EXP24_.EXP | lan_adr_sw/lan_adr_sw_CLKF | RESET
|
|
INPUTMC | 5 | 2 | 8 | 2 | 14 | 4 | 0 | 4 | 2 | 15 | 6
|
|
INPUTP | 2 | 162 | 263
|
|
IMPORTS | 2 | 4 | 0 | 4 | 2
|
|
EQ | 22 |
|
|
CP_CS.D = SHUT_UP<1>
|
|
# CP_BASEADR<6> & !A<22>
|
|
# !CP_BASEADR<6> & A<22>
|
|
;Imported pterms FB5_1
|
|
# CP_BASEADR<0> & !A<16>
|
|
# !CP_BASEADR<0> & A<16>
|
|
# CP_BASEADR<1> & !A<17>
|
|
# !CP_BASEADR<1> & A<17>
|
|
# !CP_BASEADR<2> & A<18>
|
|
;Imported pterms FB5_3
|
|
# CP_BASEADR<2> & !A<18>
|
|
# CP_BASEADR<3> & !A<19>
|
|
# !CP_BASEADR<3> & A<19>
|
|
# CP_BASEADR<4> & !A<20>
|
|
# !CP_BASEADR<4> & A<20>
|
|
;Imported pterms FB5_4
|
|
# CP_BASEADR<5> & !A<21>
|
|
# !CP_BASEADR<5> & A<21>
|
|
# CP_BASEADR<7> & !A<23>
|
|
# !CP_BASEADR<7> & A<23>;
|
|
CP_CS.CLK = lan_adr_sw/lan_adr_sw_CLKF;
|
|
CP_CS.AP = !RESET;
|
|
|
|
MACROCELL | 9 | 2 | DQ_0_IOBUFE
|
|
ATTRIBUTES | 265986 | 0
|
|
INPUTS | 3 | D_IN<0> | DQ_or0001/DQ_or0001_D2 | DQ_9_IOBUFE/DQ_9_IOBUFE_TRST
|
|
INPUTMC | 3 | 5 | 16 | 5 | 17 | 9 | 6
|
|
EQ | 2 |
|
|
!DQ<0> = !D_IN<0> & !DQ_or0001/DQ_or0001_D2;
|
|
DQ<0>.OE = DQ_9_IOBUFE/DQ_9_IOBUFE_TRST;
|
|
|
|
MACROCELL | 9 | 16 | DQ_10_IOBUFE
|
|
ATTRIBUTES | 265986 | 0
|
|
INPUTS | 3 | D_IN<10> | DQ_or0001/DQ_or0001_D2 | DQ_9_IOBUFE/DQ_9_IOBUFE_TRST
|
|
INPUTMC | 3 | 7 | 17 | 5 | 17 | 9 | 6
|
|
EQ | 2 |
|
|
!DQ<10> = !D_IN<10> & !DQ_or0001/DQ_or0001_D2;
|
|
DQ<10>.OE = DQ_9_IOBUFE/DQ_9_IOBUFE_TRST;
|
|
|
|
MACROCELL | 11 | 9 | DQ_11_IOBUFE
|
|
ATTRIBUTES | 265986 | 0
|
|
INPUTS | 3 | D_IN<11> | DQ_or0001/DQ_or0001_D2 | DQ_9_IOBUFE/DQ_9_IOBUFE_TRST
|
|
INPUTMC | 3 | 7 | 16 | 5 | 17 | 9 | 6
|
|
EQ | 2 |
|
|
!DQ<11> = !D_IN<11> & !DQ_or0001/DQ_or0001_D2;
|
|
DQ<11>.OE = DQ_9_IOBUFE/DQ_9_IOBUFE_TRST;
|
|
|
|
MACROCELL | 7 | 1 | DQ_12_IOBUFE
|
|
ATTRIBUTES | 265986 | 0
|
|
INPUTS | 3 | D_IN<12> | DQ_or0001/DQ_or0001_D2 | DQ_9_IOBUFE/DQ_9_IOBUFE_TRST
|
|
INPUTMC | 3 | 11 | 3 | 5 | 17 | 9 | 6
|
|
EQ | 2 |
|
|
!DQ<12> = !D_IN<12> & !DQ_or0001/DQ_or0001_D2;
|
|
DQ<12>.OE = DQ_9_IOBUFE/DQ_9_IOBUFE_TRST;
|
|
|
|
MACROCELL | 11 | 7 | DQ_13_IOBUFE
|
|
ATTRIBUTES | 265986 | 0
|
|
INPUTS | 3 | D_IN<13> | DQ_or0001/DQ_or0001_D2 | DQ_9_IOBUFE/DQ_9_IOBUFE_TRST
|
|
INPUTMC | 3 | 6 | 15 | 5 | 17 | 9 | 6
|
|
EQ | 2 |
|
|
!DQ<13> = !D_IN<13> & !DQ_or0001/DQ_or0001_D2;
|
|
DQ<13>.OE = DQ_9_IOBUFE/DQ_9_IOBUFE_TRST;
|
|
|
|
MACROCELL | 7 | 2 | DQ_14_IOBUFE
|
|
ATTRIBUTES | 265986 | 0
|
|
INPUTS | 3 | D_IN<14> | DQ_or0001/DQ_or0001_D2 | DQ_9_IOBUFE/DQ_9_IOBUFE_TRST
|
|
INPUTMC | 3 | 11 | 2 | 5 | 17 | 9 | 6
|
|
EQ | 2 |
|
|
!DQ<14> = !D_IN<14> & !DQ_or0001/DQ_or0001_D2;
|
|
DQ<14>.OE = DQ_9_IOBUFE/DQ_9_IOBUFE_TRST;
|
|
|
|
MACROCELL | 11 | 4 | DQ_15_IOBUFE
|
|
ATTRIBUTES | 265986 | 0
|
|
INPUTS | 3 | D_IN<15> | DQ_or0001/DQ_or0001_D2 | DQ_9_IOBUFE/DQ_9_IOBUFE_TRST
|
|
INPUTMC | 3 | 11 | 1 | 5 | 17 | 9 | 6
|
|
EQ | 2 |
|
|
!DQ<15> = !D_IN<15> & !DQ_or0001/DQ_or0001_D2;
|
|
DQ<15>.OE = DQ_9_IOBUFE/DQ_9_IOBUFE_TRST;
|
|
|
|
MACROCELL | 9 | 1 | DQ_1_IOBUFE
|
|
ATTRIBUTES | 265986 | 0
|
|
INPUTS | 3 | D_IN<1> | DQ_or0001/DQ_or0001_D2 | DQ_9_IOBUFE/DQ_9_IOBUFE_TRST
|
|
INPUTMC | 3 | 7 | 15 | 5 | 17 | 9 | 6
|
|
EQ | 2 |
|
|
!DQ<1> = !D_IN<1> & !DQ_or0001/DQ_or0001_D2;
|
|
DQ<1>.OE = DQ_9_IOBUFE/DQ_9_IOBUFE_TRST;
|
|
|
|
MACROCELL | 9 | 5 | DQ_2_IOBUFE
|
|
ATTRIBUTES | 265986 | 0
|
|
INPUTS | 3 | D_IN<2> | DQ_or0001/DQ_or0001_D2 | DQ_9_IOBUFE/DQ_9_IOBUFE_TRST
|
|
INPUTMC | 3 | 7 | 14 | 5 | 17 | 9 | 6
|
|
EQ | 2 |
|
|
!DQ<2> = !D_IN<2> & !DQ_or0001/DQ_or0001_D2;
|
|
DQ<2>.OE = DQ_9_IOBUFE/DQ_9_IOBUFE_TRST;
|
|
|
|
MACROCELL | 9 | 4 | DQ_3_IOBUFE
|
|
ATTRIBUTES | 265986 | 0
|
|
INPUTS | 3 | D_IN<3> | DQ_or0001/DQ_or0001_D2 | DQ_9_IOBUFE/DQ_9_IOBUFE_TRST
|
|
INPUTMC | 3 | 7 | 13 | 5 | 17 | 9 | 6
|
|
EQ | 2 |
|
|
!DQ<3> = !D_IN<3> & !DQ_or0001/DQ_or0001_D2;
|
|
DQ<3>.OE = DQ_9_IOBUFE/DQ_9_IOBUFE_TRST;
|
|
|
|
MACROCELL | 9 | 9 | DQ_4_IOBUFE
|
|
ATTRIBUTES | 265986 | 0
|
|
INPUTS | 3 | D_IN<4> | DQ_or0001/DQ_or0001_D2 | DQ_9_IOBUFE/DQ_9_IOBUFE_TRST
|
|
INPUTMC | 3 | 11 | 17 | 5 | 17 | 9 | 6
|
|
EQ | 2 |
|
|
!DQ<4> = !D_IN<4> & !DQ_or0001/DQ_or0001_D2;
|
|
DQ<4>.OE = DQ_9_IOBUFE/DQ_9_IOBUFE_TRST;
|
|
|
|
MACROCELL | 9 | 7 | DQ_5_IOBUFE
|
|
ATTRIBUTES | 265986 | 0
|
|
INPUTS | 3 | D_IN<5> | DQ_or0001/DQ_or0001_D2 | DQ_9_IOBUFE/DQ_9_IOBUFE_TRST
|
|
INPUTMC | 3 | 6 | 16 | 5 | 17 | 9 | 6
|
|
EQ | 2 |
|
|
!DQ<5> = !D_IN<5> & !DQ_or0001/DQ_or0001_D2;
|
|
DQ<5>.OE = DQ_9_IOBUFE/DQ_9_IOBUFE_TRST;
|
|
|
|
MACROCELL | 9 | 11 | DQ_6_IOBUFE
|
|
ATTRIBUTES | 265986 | 0
|
|
INPUTS | 3 | D_IN<6> | DQ_or0001/DQ_or0001_D2 | DQ_9_IOBUFE/DQ_9_IOBUFE_TRST
|
|
INPUTMC | 3 | 11 | 13 | 5 | 17 | 9 | 6
|
|
EQ | 2 |
|
|
!DQ<6> = !D_IN<6> & !DQ_or0001/DQ_or0001_D2;
|
|
DQ<6>.OE = DQ_9_IOBUFE/DQ_9_IOBUFE_TRST;
|
|
|
|
MACROCELL | 9 | 10 | DQ_7_IOBUFE
|
|
ATTRIBUTES | 265986 | 0
|
|
INPUTS | 3 | D_IN<7> | DQ_or0001/DQ_or0001_D2 | DQ_9_IOBUFE/DQ_9_IOBUFE_TRST
|
|
INPUTMC | 3 | 11 | 12 | 5 | 17 | 9 | 6
|
|
EQ | 2 |
|
|
!DQ<7> = !D_IN<7> & !DQ_or0001/DQ_or0001_D2;
|
|
DQ<7>.OE = DQ_9_IOBUFE/DQ_9_IOBUFE_TRST;
|
|
|
|
MACROCELL | 9 | 13 | DQ_8_IOBUFE
|
|
ATTRIBUTES | 265986 | 0
|
|
INPUTS | 3 | D_IN<8> | DQ_or0001/DQ_or0001_D2 | DQ_9_IOBUFE/DQ_9_IOBUFE_TRST
|
|
INPUTMC | 3 | 7 | 12 | 5 | 17 | 9 | 6
|
|
EQ | 2 |
|
|
!DQ<8> = !D_IN<8> & !DQ_or0001/DQ_or0001_D2;
|
|
DQ<8>.OE = DQ_9_IOBUFE/DQ_9_IOBUFE_TRST;
|
|
|
|
MACROCELL | 11 | 11 | DQ_9_IOBUFE
|
|
ATTRIBUTES | 265986 | 0
|
|
INPUTS | 3 | D_IN<9> | DQ_or0001/DQ_or0001_D2 | DQ_9_IOBUFE/DQ_9_IOBUFE_TRST
|
|
INPUTMC | 3 | 7 | 11 | 5 | 17 | 9 | 6
|
|
EQ | 2 |
|
|
!DQ<9> = !D_IN<9> & !DQ_or0001/DQ_or0001_D2;
|
|
DQ<9>.OE = DQ_9_IOBUFE/DQ_9_IOBUFE_TRST;
|
|
|
|
MACROCELL | 10 | 12 | autoconfig
|
|
ATTRIBUTES | 8520612 | 0
|
|
OUTPUTMC | 19 | 3 | 1 | 4 | 13 | 4 | 14 | 1 | 14 | 4 | 9 | 1 | 11 | 0 | 5 | 0 | 4 | 1 | 9 | 1 | 13 | 1 | 16 | 4 | 11 | 4 | 16 | 6 | 2 | 6 | 4 | 6 | 11 | 13 | 13 | 13 | 4 | 0 | 2
|
|
INPUTS | 12 | A<23> | A<22> | A<21> | A<19> | A<18> | A<17> | A<16> | A<20> | CFIN | CFOUT | lan_adr_sw/lan_adr_sw_CLKF | RESET
|
|
INPUTMC | 2 | 13 | 10 | 15 | 6
|
|
INPUTP | 10 | 161 | 162 | 163 | 169 | 171 | 172 | 175 | 167 | 190 | 263
|
|
EQ | 4 |
|
|
!autoconfig.D = A<23> & A<22> & A<21> & A<19> & !A<18> & !A<17> &
|
|
!A<16> & !A<20> & !CFIN & CFOUT;
|
|
autoconfig.CLK = lan_adr_sw/lan_adr_sw_CLKF;
|
|
autoconfig.AP = !RESET;
|
|
|
|
MACROCELL | 14 | 13 | lan_adr
|
|
ATTRIBUTES | 8520612 | 0
|
|
OUTPUTMC | 32 | 9 | 17 | 2 | 16 | 0 | 10 | 9 | 12 | 9 | 8 | 3 | 5 | 5 | 5 | 5 | 7 | 5 | 2 | 5 | 4 | 3 | 4 | 3 | 11 | 3 | 7 | 1 | 1 | 3 | 13 | 1 | 4 | 1 | 2 | 5 | 9 | 5 | 13 | 5 | 16 | 7 | 15 | 7 | 14 | 7 | 13 | 7 | 7 | 13 | 13 | 13 | 4 | 15 | 5 | 0 | 3 | 5 | 17 | 5 | 10 | 5 | 15 | 2 | 0
|
|
INPUTS | 11 | SHUT_UP<0> | $OpTx$FX_DC$38 | $OpTx$FX_DC$39 | $OpTx$FX_DC$40 | $OpTx$FX_DC$44 | $OpTx$FX_DC$41 | $OpTx$FX_DC$42 | $OpTx$FX_DC$43 | $OpTx$FX_DC$45 | lan_adr_sw/lan_adr_sw_CLKF | RESET
|
|
INPUTMC | 10 | 10 | 14 | 15 | 17 | 15 | 16 | 15 | 15 | 15 | 11 | 15 | 14 | 15 | 13 | 15 | 12 | 15 | 10 | 15 | 6
|
|
INPUTP | 1 | 263
|
|
EQ | 5 |
|
|
!lan_adr.D = !SHUT_UP<0> & !$OpTx$FX_DC$38 & !$OpTx$FX_DC$39 &
|
|
!$OpTx$FX_DC$40 & !$OpTx$FX_DC$44 & !$OpTx$FX_DC$41 & !$OpTx$FX_DC$42 &
|
|
!$OpTx$FX_DC$43 & !$OpTx$FX_DC$45;
|
|
lan_adr.CLK = lan_adr_sw/lan_adr_sw_CLKF;
|
|
lan_adr.AP = !RESET;
|
|
|
|
MACROCELL | 10 | 17 | ide
|
|
ATTRIBUTES | 8520612 | 0
|
|
OUTPUTMC | 14 | 0 | 17 | 0 | 15 | 0 | 12 | 0 | 8 | 5 | 16 | 7 | 15 | 7 | 14 | 7 | 13 | 13 | 13 | 13 | 4 | 9 | 6 | 5 | 17 | 5 | 10 | 5 | 15
|
|
INPUTS | 7 | SHUT_UP<2> | IDE_BASEADR<6> | A<22> | EXP27_.EXP | CP_WE_OBUF.EXP | lan_adr_sw/lan_adr_sw_CLKF | RESET
|
|
INPUTMC | 5 | 12 | 6 | 2 | 10 | 10 | 0 | 10 | 16 | 15 | 6
|
|
INPUTP | 2 | 162 | 263
|
|
IMPORTS | 2 | 10 | 0 | 10 | 16
|
|
EQ | 22 |
|
|
ide.D = SHUT_UP<2>
|
|
# IDE_BASEADR<6> & !A<22>
|
|
# !IDE_BASEADR<6> & A<22>
|
|
;Imported pterms FB11_1
|
|
# IDE_BASEADR<2> & !A<18>
|
|
# IDE_BASEADR<3> & !A<19>
|
|
# !IDE_BASEADR<3> & A<19>
|
|
# IDE_BASEADR<5> & !A<21>
|
|
# !IDE_BASEADR<5> & A<21>
|
|
;Imported pterms FB11_2
|
|
# IDE_BASEADR<4> & !A<20>
|
|
# !IDE_BASEADR<4> & A<20>
|
|
# IDE_BASEADR<7> & !A<23>
|
|
# !IDE_BASEADR<7> & A<23>
|
|
;Imported pterms FB11_17
|
|
# IDE_BASEADR<0> & !A<16>
|
|
# !IDE_BASEADR<0> & A<16>
|
|
# IDE_BASEADR<1> & !A<17>
|
|
# !IDE_BASEADR<1> & A<17>
|
|
# !IDE_BASEADR<2> & A<18>;
|
|
ide.CLK = lan_adr_sw/lan_adr_sw_CLKF;
|
|
ide.AP = !RESET;
|
|
|
|
MACROCELL | 14 | 12 | LAN_RST_SM_FSM_FFd1
|
|
ATTRIBUTES | 8553232 | 0
|
|
OUTPUTMC | 3 | 14 | 12 | 11 | 8 | 11 | 0
|
|
INPUTS | 4 | LAN_RST_SM_FSM_FFd1 | LAN_RST_SM_FSM_FFd2 | RESET | SET_FREQUENCY
|
|
INPUTMC | 3 | 14 | 12 | 14 | 10 | 11 | 0
|
|
INPUTP | 1 | 263
|
|
EQ | 3 |
|
|
!LAN_RST_SM_FSM_FFd1.D = !LAN_RST_SM_FSM_FFd1 & !LAN_RST_SM_FSM_FFd2;
|
|
LAN_RST_SM_FSM_FFd1.CLK = CLK_EXT; // GCK
|
|
LAN_RST_SM_FSM_FFd1.AR = !RESET & SET_FREQUENCY;
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 0 | 17 | IDE_ENABLE
|
|
ATTRIBUTES | 8520676 | 0
|
|
OUTPUTMC | 2 | 0 | 15 | 0 | 8
|
|
INPUTS | 5 | lan_adr_sw/lan_adr_sw_CLKF | RESET | AS | RW | ide
|
|
INPUTMC | 2 | 15 | 6 | 10 | 17
|
|
INPUTP | 3 | 263 | 152 | 158
|
|
EQ | 4 |
|
|
IDE_ENABLE.D = Gnd;
|
|
IDE_ENABLE.CLK = !lan_adr_sw/lan_adr_sw_CLKF;
|
|
IDE_ENABLE.AP = !RESET;
|
|
IDE_ENABLE.CE = !AS & !RW & !ide;
|
|
|
|
MACROCELL | 9 | 14 | CP_WE_S
|
|
ATTRIBUTES | 8520612 | 0
|
|
OUTPUTMC | 1 | 10 | 15
|
|
INPUTS | 5 | RW | CP_CS | $OpTx$FX_DC$19 | lan_adr_sw/lan_adr_sw_CLKF | RESET
|
|
INPUTMC | 3 | 4 | 1 | 9 | 3 | 15 | 6
|
|
INPUTP | 2 | 158 | 263
|
|
EQ | 3 |
|
|
!CP_WE_S.D = !RW & !CP_CS & !$OpTx$FX_DC$19;
|
|
CP_WE_S.CLK = !lan_adr_sw/lan_adr_sw_CLKF;
|
|
CP_WE_S.AP = !RESET;
|
|
|
|
MACROCELL | 2 | 9 | LAN_IRQ_D0
|
|
ATTRIBUTES | 8520612 | 0
|
|
OUTPUTMC | 3 | 2 | 17 | 2 | 0 | 2 | 16
|
|
INPUTS | 3 | LAN_INT | lan_adr_sw/lan_adr_sw_CLKF | RESET
|
|
INPUTMC | 1 | 15 | 6
|
|
INPUTP | 2 | 201 | 263
|
|
EQ | 3 |
|
|
LAN_IRQ_D0.D = LAN_INT;
|
|
LAN_IRQ_D0.CLK = !lan_adr_sw/lan_adr_sw_CLKF;
|
|
LAN_IRQ_D0.AP = !RESET;
|
|
|
|
MACROCELL | 14 | 14 | lan_adr_sw
|
|
ATTRIBUTES | 8520612 | 0
|
|
OUTPUTMC | 1 | 15 | 5
|
|
INPUTS | 13 | SHUT_UP<0> | A<13> | $OpTx$FX_DC$38 | $OpTx$FX_DC$39 | $OpTx$FX_DC$40 | $OpTx$FX_DC$44 | $OpTx$FX_DC$41 | $OpTx$FX_DC$42 | $OpTx$FX_DC$43 | $OpTx$FX_DC$45 | A<14> | lan_adr_sw/lan_adr_sw_CLKF | RESET
|
|
INPUTMC | 10 | 10 | 14 | 15 | 17 | 15 | 16 | 15 | 15 | 15 | 11 | 15 | 14 | 15 | 13 | 15 | 12 | 15 | 10 | 15 | 6
|
|
INPUTP | 3 | 123 | 125 | 263
|
|
EQ | 8 |
|
|
!lan_adr_sw.D = !SHUT_UP<0> & !A<13> & !$OpTx$FX_DC$38 &
|
|
!$OpTx$FX_DC$39 & !$OpTx$FX_DC$40 & !$OpTx$FX_DC$44 & !$OpTx$FX_DC$41 &
|
|
!$OpTx$FX_DC$42 & !$OpTx$FX_DC$43 & !$OpTx$FX_DC$45
|
|
# !SHUT_UP<0> & !A<14> & !$OpTx$FX_DC$38 &
|
|
!$OpTx$FX_DC$39 & !$OpTx$FX_DC$40 & !$OpTx$FX_DC$44 & !$OpTx$FX_DC$41 &
|
|
!$OpTx$FX_DC$42 & !$OpTx$FX_DC$43 & !$OpTx$FX_DC$45;
|
|
lan_adr_sw.CLK = lan_adr_sw/lan_adr_sw_CLKF;
|
|
lan_adr_sw.AP = !RESET;
|
|
|
|
MACROCELL | 15 | 8 | LAN_RST_SM_FSM_FFd3
|
|
ATTRIBUTES | 8553232 | 0
|
|
OUTPUTMC | 2 | 14 | 8 | 14 | 10
|
|
INPUTS | 3 | LAN_RST_SM_FSM_FFd4 | RESET | SET_FREQUENCY
|
|
INPUTMC | 2 | 11 | 6 | 11 | 0
|
|
INPUTP | 1 | 263
|
|
EQ | 3 |
|
|
LAN_RST_SM_FSM_FFd3.D = LAN_RST_SM_FSM_FFd4;
|
|
LAN_RST_SM_FSM_FFd3.CLK = CLK_EXT; // GCK
|
|
LAN_RST_SM_FSM_FFd3.AR = !RESET & SET_FREQUENCY;
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 14 | 9 | LAN_RST_SM_FSM_FFd5
|
|
ATTRIBUTES | 8553232 | 0
|
|
OUTPUTMC | 2 | 11 | 6 | 11 | 10
|
|
INPUTS | 3 | LAN_RST_SM_FSM_FFd6 | RESET | SET_FREQUENCY
|
|
INPUTMC | 2 | 15 | 7 | 11 | 0
|
|
INPUTP | 1 | 263
|
|
EQ | 3 |
|
|
LAN_RST_SM_FSM_FFd5.D = LAN_RST_SM_FSM_FFd6;
|
|
LAN_RST_SM_FSM_FFd5.CLK = CLK_EXT; // GCK
|
|
LAN_RST_SM_FSM_FFd5.AR = !RESET & SET_FREQUENCY;
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 15 | 7 | LAN_RST_SM_FSM_FFd6
|
|
ATTRIBUTES | 8553232 | 0
|
|
OUTPUTMC | 2 | 14 | 9 | 14 | 8
|
|
INPUTS | 3 | LAN_RST_SM_FSM_FFd7 | RESET | SET_FREQUENCY
|
|
INPUTMC | 2 | 11 | 5 | 11 | 0
|
|
INPUTP | 1 | 263
|
|
EQ | 3 |
|
|
LAN_RST_SM_FSM_FFd6.D = LAN_RST_SM_FSM_FFd7;
|
|
LAN_RST_SM_FSM_FFd6.CLK = CLK_EXT; // GCK
|
|
LAN_RST_SM_FSM_FFd6.AR = !RESET & SET_FREQUENCY;
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 14 | 8 | LAN_WR_RST
|
|
ATTRIBUTES | 8553348 | 0
|
|
OUTPUTMC | 2 | 7 | 4 | 12 | 13
|
|
INPUTS | 4 | LAN_RST_SM_FSM_FFd3 | LAN_RST_SM_FSM_FFd6 | RESET | SET_FREQUENCY
|
|
INPUTMC | 3 | 15 | 8 | 15 | 7 | 11 | 0
|
|
INPUTP | 1 | 263
|
|
EQ | 3 |
|
|
LAN_WR_RST.D = !LAN_RST_SM_FSM_FFd3 & !LAN_RST_SM_FSM_FFd6;
|
|
LAN_WR_RST.CLK = CLK_EXT; // GCK
|
|
LAN_WR_RST.AP = !RESET & SET_FREQUENCY;
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 10 | 14 | SHUT_UP<0>
|
|
ATTRIBUTES | 8520612 | 0
|
|
OUTPUTMC | 3 | 14 | 13 | 14 | 14 | 10 | 14
|
|
INPUTS | 4 | SHUT_UP<0> | LAN_BASEADR_not0001/LAN_BASEADR_not0001_D2 | lan_adr_sw/lan_adr_sw_CLKF | RESET
|
|
INPUTMC | 3 | 10 | 14 | 8 | 10 | 15 | 6
|
|
INPUTP | 1 | 263
|
|
EQ | 4 |
|
|
SHUT_UP<0>.D = SHUT_UP<0> &
|
|
!LAN_BASEADR_not0001/LAN_BASEADR_not0001_D2;
|
|
SHUT_UP<0>.CLK = !lan_adr_sw/lan_adr_sw_CLKF;
|
|
SHUT_UP<0>.AP = !RESET;
|
|
|
|
MACROCELL | 2 | 8 | SHUT_UP<1>
|
|
ATTRIBUTES | 8520612 | 0
|
|
OUTPUTMC | 2 | 4 | 1 | 2 | 8
|
|
INPUTS | 4 | SHUT_UP<1> | CP_BASEADR_not0001/CP_BASEADR_not0001_D2 | lan_adr_sw/lan_adr_sw_CLKF | RESET
|
|
INPUTMC | 3 | 2 | 8 | 3 | 17 | 15 | 6
|
|
INPUTP | 1 | 263
|
|
EQ | 4 |
|
|
SHUT_UP<1>.D = SHUT_UP<1> &
|
|
!CP_BASEADR_not0001/CP_BASEADR_not0001_D2;
|
|
SHUT_UP<1>.CLK = !lan_adr_sw/lan_adr_sw_CLKF;
|
|
SHUT_UP<1>.AP = !RESET;
|
|
|
|
MACROCELL | 12 | 6 | SHUT_UP<2>
|
|
ATTRIBUTES | 8520612 | 0
|
|
OUTPUTMC | 2 | 10 | 17 | 12 | 6
|
|
INPUTS | 4 | SHUT_UP<2> | IDE_BASEADR_not0001/IDE_BASEADR_not0001_D2 | lan_adr_sw/lan_adr_sw_CLKF | RESET
|
|
INPUTMC | 3 | 12 | 6 | 13 | 9 | 15 | 6
|
|
INPUTP | 1 | 263
|
|
EQ | 4 |
|
|
SHUT_UP<2>.D = SHUT_UP<2> &
|
|
!IDE_BASEADR_not0001/IDE_BASEADR_not0001_D2;
|
|
SHUT_UP<2>.CLK = !lan_adr_sw/lan_adr_sw_CLKF;
|
|
SHUT_UP<2>.AP = !RESET;
|
|
|
|
MACROCELL | 9 | 15 | CP_RD_S
|
|
ATTRIBUTES | 8520612 | 0
|
|
OUTPUTMC | 1 | 12 | 1
|
|
INPUTS | 5 | AS | RW | CP_CS | lan_adr_sw/lan_adr_sw_CLKF | RESET
|
|
INPUTMC | 2 | 4 | 1 | 15 | 6
|
|
INPUTP | 3 | 152 | 158 | 263
|
|
EQ | 3 |
|
|
!CP_RD_S.D = !AS & RW & !CP_CS;
|
|
CP_RD_S.CLK = !lan_adr_sw/lan_adr_sw_CLKF;
|
|
CP_RD_S.AP = !RESET;
|
|
|
|
MACROCELL | 10 | 15 | CP_WE_QUIRK
|
|
ATTRIBUTES | 8520612 | 0
|
|
OUTPUTMC | 2 | 10 | 15 | 10 | 16
|
|
INPUTS | 5 | CP_WE_S | lan_adr_sw/lan_adr_sw_CLKF | RESET | AS | CP_WE_QUIRK
|
|
INPUTMC | 3 | 9 | 14 | 15 | 6 | 10 | 15
|
|
INPUTP | 2 | 263 | 152
|
|
EXPORTS | 1 | 10 | 16
|
|
EQ | 4 |
|
|
CP_WE_QUIRK.D = CP_WE_S;
|
|
CP_WE_QUIRK.CLK = !lan_adr_sw/lan_adr_sw_CLKF;
|
|
CP_WE_QUIRK.AP = !RESET;
|
|
CP_WE_QUIRK.EXP = !AS & !CP_WE_S & CP_WE_QUIRK
|
|
|
|
MACROCELL | 0 | 15 | IDE_R_S
|
|
ATTRIBUTES | 8520612 | 0
|
|
OUTPUTMC | 1 | 0 | 16
|
|
INPUTS | 6 | RW | ide | IDE_ENABLE | $OpTx$FX_DC$19 | lan_adr_sw/lan_adr_sw_CLKF | RESET
|
|
INPUTMC | 4 | 10 | 17 | 0 | 17 | 9 | 3 | 15 | 6
|
|
INPUTP | 2 | 158 | 263
|
|
EQ | 3 |
|
|
!IDE_R_S.D = RW & !ide & !IDE_ENABLE & !$OpTx$FX_DC$19;
|
|
IDE_R_S.CLK = !lan_adr_sw/lan_adr_sw_CLKF;
|
|
IDE_R_S.AP = !RESET;
|
|
|
|
MACROCELL | 0 | 12 | IDE_W_S
|
|
ATTRIBUTES | 8520612 | 0
|
|
OUTPUTMC | 1 | 2 | 1
|
|
INPUTS | 5 | RW | ide | $OpTx$FX_DC$19 | lan_adr_sw/lan_adr_sw_CLKF | RESET
|
|
INPUTMC | 3 | 10 | 17 | 9 | 3 | 15 | 6
|
|
INPUTP | 2 | 158 | 263
|
|
EQ | 3 |
|
|
!IDE_W_S.D = !RW & !ide & !$OpTx$FX_DC$19;
|
|
IDE_W_S.CLK = !lan_adr_sw/lan_adr_sw_CLKF;
|
|
IDE_W_S.AP = !RESET;
|
|
|
|
MACROCELL | 0 | 10 | LAN_RD_S
|
|
ATTRIBUTES | 8520612 | 0
|
|
OUTPUTMC | 1 | 7 | 9
|
|
INPUTS | 6 | A<15> | RW | lan_adr | $OpTx$FX_DC$19 | lan_adr_sw/lan_adr_sw_CLKF | RESET
|
|
INPUTMC | 3 | 14 | 13 | 9 | 3 | 15 | 6
|
|
INPUTP | 3 | 139 | 158 | 263
|
|
EQ | 3 |
|
|
!LAN_RD_S.D = !A<15> & RW & !lan_adr & !$OpTx$FX_DC$19;
|
|
LAN_RD_S.CLK = !lan_adr_sw/lan_adr_sw_CLKF;
|
|
LAN_RD_S.AP = !RESET;
|
|
|
|
MACROCELL | 9 | 12 | LAN_WRH_S
|
|
ATTRIBUTES | 8520612 | 0
|
|
OUTPUTMC | 1 | 7 | 4
|
|
INPUTS | 6 | A<15> | RW | lan_adr | LDS | lan_adr_sw/lan_adr_sw_CLKF | RESET
|
|
INPUTMC | 2 | 14 | 13 | 15 | 6
|
|
INPUTP | 4 | 139 | 158 | 157 | 263
|
|
EQ | 3 |
|
|
!LAN_WRH_S.D = !A<15> & !RW & !lan_adr & !LDS;
|
|
LAN_WRH_S.CLK = !lan_adr_sw/lan_adr_sw_CLKF;
|
|
LAN_WRH_S.AP = !RESET;
|
|
|
|
MACROCELL | 9 | 8 | LAN_WRL_S
|
|
ATTRIBUTES | 8520612 | 0
|
|
OUTPUTMC | 1 | 12 | 13
|
|
INPUTS | 6 | A<15> | RW | lan_adr | UDS | lan_adr_sw/lan_adr_sw_CLKF | RESET
|
|
INPUTMC | 2 | 14 | 13 | 15 | 6
|
|
INPUTP | 4 | 139 | 158 | 155 | 263
|
|
EQ | 3 |
|
|
!LAN_WRL_S.D = !A<15> & !RW & !lan_adr & !UDS;
|
|
LAN_WRL_S.CLK = !lan_adr_sw/lan_adr_sw_CLKF;
|
|
LAN_WRL_S.AP = !RESET;
|
|
|
|
MACROCELL | 0 | 8 | ROM_OE_S
|
|
ATTRIBUTES | 8520612 | 0
|
|
OUTPUTMC | 1 | 4 | 4
|
|
INPUTS | 6 | RW | ide | IDE_ENABLE | $OpTx$FX_DC$19 | lan_adr_sw/lan_adr_sw_CLKF | RESET
|
|
INPUTMC | 4 | 10 | 17 | 0 | 17 | 9 | 3 | 15 | 6
|
|
INPUTP | 2 | 158 | 263
|
|
EQ | 3 |
|
|
!ROM_OE_S.D = RW & !ide & IDE_ENABLE & !$OpTx$FX_DC$19;
|
|
ROM_OE_S.CLK = !lan_adr_sw/lan_adr_sw_CLKF;
|
|
ROM_OE_S.AP = !RESET;
|
|
|
|
MACROCELL | 11 | 8 | LAN_CS_RST
|
|
ATTRIBUTES | 8553348 | 0
|
|
OUTPUTMC | 1 | 7 | 7
|
|
INPUTS | 4 | LAN_RST_SM_FSM_FFd1 | LAN_RST_SM_FSM_FFd8 | RESET | SET_FREQUENCY
|
|
INPUTMC | 3 | 14 | 12 | 6 | 14 | 11 | 0
|
|
INPUTP | 1 | 263
|
|
EQ | 3 |
|
|
!LAN_CS_RST.D = !LAN_RST_SM_FSM_FFd1 & !LAN_RST_SM_FSM_FFd8;
|
|
LAN_CS_RST.CLK = CLK_EXT; // GCK
|
|
LAN_CS_RST.AP = !RESET & SET_FREQUENCY;
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 14 | 10 | LAN_RST_SM_FSM_FFd2
|
|
ATTRIBUTES | 8553232 | 0
|
|
OUTPUTMC | 1 | 14 | 12
|
|
INPUTS | 3 | LAN_RST_SM_FSM_FFd3 | RESET | SET_FREQUENCY
|
|
INPUTMC | 2 | 15 | 8 | 11 | 0
|
|
INPUTP | 1 | 263
|
|
EQ | 3 |
|
|
LAN_RST_SM_FSM_FFd2.D = LAN_RST_SM_FSM_FFd3;
|
|
LAN_RST_SM_FSM_FFd2.CLK = CLK_EXT; // GCK
|
|
LAN_RST_SM_FSM_FFd2.AR = !RESET & SET_FREQUENCY;
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 11 | 6 | LAN_RST_SM_FSM_FFd4
|
|
ATTRIBUTES | 8553232 | 0
|
|
OUTPUTMC | 1 | 15 | 8
|
|
INPUTS | 3 | LAN_RST_SM_FSM_FFd5 | RESET | SET_FREQUENCY
|
|
INPUTMC | 2 | 14 | 9 | 11 | 0
|
|
INPUTP | 1 | 263
|
|
EQ | 3 |
|
|
LAN_RST_SM_FSM_FFd4.D = LAN_RST_SM_FSM_FFd5;
|
|
LAN_RST_SM_FSM_FFd4.CLK = CLK_EXT; // GCK
|
|
LAN_RST_SM_FSM_FFd4.AR = !RESET & SET_FREQUENCY;
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 11 | 5 | LAN_RST_SM_FSM_FFd7
|
|
ATTRIBUTES | 8553232 | 0
|
|
OUTPUTMC | 1 | 15 | 7
|
|
INPUTS | 3 | LAN_RST_SM_FSM_FFd8 | RESET | SET_FREQUENCY
|
|
INPUTMC | 2 | 6 | 14 | 11 | 0
|
|
INPUTP | 1 | 263
|
|
EQ | 3 |
|
|
LAN_RST_SM_FSM_FFd7.D = LAN_RST_SM_FSM_FFd8;
|
|
LAN_RST_SM_FSM_FFd7.CLK = CLK_EXT; // GCK
|
|
LAN_RST_SM_FSM_FFd7.AR = !RESET & SET_FREQUENCY;
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 3 | 5 | A_LAN_OUT<0>
|
|
ATTRIBUTES | 8815366 | 0
|
|
OUTPUTMC | 1 | 3 | 5
|
|
INPUTS | 5 | CP_CS | A<1> | lan_adr | A_LAN<0> | SET_FREQUENCY
|
|
INPUTMC | 4 | 4 | 1 | 14 | 13 | 3 | 5 | 11 | 0
|
|
INPUTP | 1 | 107
|
|
EQ | 4 |
|
|
!A_LAN<0>.D = !CP_CS
|
|
# !A<1> & !lan_adr
|
|
# lan_adr & !A_LAN<0> & !SET_FREQUENCY;
|
|
!A_LAN<0>.CLK = CLK_EXT; // GCK
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 5 | 5 | A_LAN_OUT<10>
|
|
ATTRIBUTES | 8815366 | 0
|
|
OUTPUTMC | 1 | 5 | 5
|
|
INPUTS | 6 | CP_CS | A<9> | lan_adr | A<11> | A_LAN<10> | SET_FREQUENCY
|
|
INPUTMC | 4 | 4 | 1 | 14 | 13 | 5 | 5 | 11 | 0
|
|
INPUTP | 2 | 108 | 114
|
|
EQ | 4 |
|
|
!A_LAN<10>.D = !CP_CS & !A<9>
|
|
# CP_CS & !lan_adr & !A<11>
|
|
# CP_CS & lan_adr & !A_LAN<10> & !SET_FREQUENCY;
|
|
!A_LAN<10>.CLK = CLK_EXT; // GCK
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 5 | 7 | A_LAN_OUT<11>
|
|
ATTRIBUTES | 8815366 | 0
|
|
OUTPUTMC | 1 | 5 | 7
|
|
INPUTS | 6 | CP_CS | A<10> | lan_adr | A<12> | A_LAN<11> | SET_FREQUENCY
|
|
INPUTMC | 4 | 4 | 1 | 14 | 13 | 5 | 7 | 11 | 0
|
|
INPUTP | 2 | 112 | 115
|
|
EQ | 4 |
|
|
!A_LAN<11>.D = !CP_CS & !A<10>
|
|
# CP_CS & !lan_adr & !A<12>
|
|
# CP_CS & lan_adr & !A_LAN<11> & !SET_FREQUENCY;
|
|
!A_LAN<11>.CLK = CLK_EXT; // GCK
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 5 | 2 | A_LAN_OUT<12>
|
|
ATTRIBUTES | 8815366 | 0
|
|
OUTPUTMC | 1 | 5 | 2
|
|
INPUTS | 6 | CP_CS | A<11> | lan_adr | A<13> | A_LAN<12> | SET_FREQUENCY
|
|
INPUTMC | 4 | 4 | 1 | 14 | 13 | 5 | 2 | 11 | 0
|
|
INPUTP | 2 | 114 | 123
|
|
EQ | 4 |
|
|
!A_LAN<12>.D = !CP_CS & !A<11>
|
|
# CP_CS & !lan_adr & !A<13>
|
|
# CP_CS & lan_adr & !A_LAN<12> & !SET_FREQUENCY;
|
|
!A_LAN<12>.CLK = CLK_EXT; // GCK
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 5 | 4 | A_LAN_OUT<13>
|
|
ATTRIBUTES | 8815366 | 0
|
|
OUTPUTMC | 1 | 5 | 4
|
|
INPUTS | 6 | CP_CS | A<12> | lan_adr | A<14> | A_LAN<13> | SET_FREQUENCY
|
|
INPUTMC | 4 | 4 | 1 | 14 | 13 | 5 | 4 | 11 | 0
|
|
INPUTP | 2 | 115 | 125
|
|
EQ | 4 |
|
|
!A_LAN<13>.D = !CP_CS & !A<12>
|
|
# CP_CS & !lan_adr & !A<14>
|
|
# CP_CS & lan_adr & !A_LAN<13> & !SET_FREQUENCY;
|
|
!A_LAN<13>.CLK = CLK_EXT; // GCK
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 3 | 4 | A_LAN_OUT<1>
|
|
ATTRIBUTES | 8815366 | 0
|
|
OUTPUTMC | 1 | 3 | 4
|
|
INPUTS | 5 | CP_CS | A<2> | lan_adr | A_LAN<1> | SET_FREQUENCY
|
|
INPUTMC | 4 | 4 | 1 | 14 | 13 | 3 | 4 | 11 | 0
|
|
INPUTP | 1 | 101
|
|
EQ | 4 |
|
|
!A_LAN<1>.D = !CP_CS
|
|
# !A<2> & !lan_adr
|
|
# lan_adr & !A_LAN<1> & !SET_FREQUENCY;
|
|
!A_LAN<1>.CLK = CLK_EXT; // GCK
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 3 | 11 | A_LAN_OUT<2>
|
|
ATTRIBUTES | 8815366 | 0
|
|
OUTPUTMC | 1 | 3 | 11
|
|
INPUTS | 6 | A<1> | CP_CS | A<3> | lan_adr | A_LAN<2> | SET_FREQUENCY
|
|
INPUTMC | 4 | 4 | 1 | 14 | 13 | 3 | 11 | 11 | 0
|
|
INPUTP | 2 | 107 | 99
|
|
EQ | 4 |
|
|
!A_LAN<2>.D = !A<1> & !CP_CS
|
|
# !A<3> & CP_CS & !lan_adr
|
|
# CP_CS & lan_adr & !A_LAN<2> & !SET_FREQUENCY;
|
|
!A_LAN<2>.CLK = CLK_EXT; // GCK
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 3 | 7 | A_LAN_OUT<3>
|
|
ATTRIBUTES | 8815366 | 0
|
|
OUTPUTMC | 1 | 3 | 7
|
|
INPUTS | 6 | A<2> | CP_CS | A<4> | lan_adr | A_LAN<3> | SET_FREQUENCY
|
|
INPUTMC | 4 | 4 | 1 | 14 | 13 | 3 | 7 | 11 | 0
|
|
INPUTP | 2 | 101 | 97
|
|
EQ | 4 |
|
|
A_LAN<3>.D = A<2> & !CP_CS
|
|
# A<4> & CP_CS & !lan_adr
|
|
# CP_CS & lan_adr & A_LAN<3> & !SET_FREQUENCY;
|
|
!A_LAN<3>.CLK = CLK_EXT; // GCK
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 1 | 1 | A_LAN_OUT<4>
|
|
ATTRIBUTES | 8815366 | 0
|
|
OUTPUTMC | 1 | 1 | 1
|
|
INPUTS | 6 | A<3> | CP_CS | A<5> | lan_adr | A_LAN<4> | SET_FREQUENCY
|
|
INPUTMC | 4 | 4 | 1 | 14 | 13 | 1 | 1 | 11 | 0
|
|
INPUTP | 2 | 99 | 91
|
|
EQ | 4 |
|
|
!A_LAN<4>.D = !A<3> & !CP_CS
|
|
# !A<5> & CP_CS & !lan_adr
|
|
# CP_CS & lan_adr & !A_LAN<4> & !SET_FREQUENCY;
|
|
!A_LAN<4>.CLK = CLK_EXT; // GCK
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 3 | 13 | A_LAN_OUT<5>
|
|
ATTRIBUTES | 8815366 | 0
|
|
OUTPUTMC | 1 | 3 | 13
|
|
INPUTS | 6 | A<4> | CP_CS | A<6> | lan_adr | A_LAN<5> | SET_FREQUENCY
|
|
INPUTMC | 4 | 4 | 1 | 14 | 13 | 3 | 13 | 11 | 0
|
|
INPUTP | 2 | 97 | 98
|
|
EQ | 4 |
|
|
!A_LAN<5>.D = !A<4> & !CP_CS
|
|
# !A<6> & CP_CS & !lan_adr
|
|
# CP_CS & lan_adr & !A_LAN<5> & !SET_FREQUENCY;
|
|
!A_LAN<5>.CLK = CLK_EXT; // GCK
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 1 | 4 | A_LAN_OUT<6>
|
|
ATTRIBUTES | 8815366 | 0
|
|
OUTPUTMC | 1 | 1 | 4
|
|
INPUTS | 7 | A<5> | CP_CS | lan_adr | A<7> | A_LAN<6> | SET_FREQUENCY | CLEAR_REGISTER
|
|
INPUTMC | 5 | 4 | 1 | 14 | 13 | 1 | 4 | 11 | 0 | 11 | 10
|
|
INPUTP | 2 | 91 | 100
|
|
EQ | 6 |
|
|
A_LAN<6>.D = A<5> & !CP_CS
|
|
# CP_CS & !lan_adr & A<7>
|
|
# CP_CS & lan_adr & A_LAN<6> & !SET_FREQUENCY
|
|
# CP_CS & lan_adr & SET_FREQUENCY &
|
|
CLEAR_REGISTER;
|
|
!A_LAN<6>.CLK = CLK_EXT; // GCK
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 1 | 2 | A_LAN_OUT<7>
|
|
ATTRIBUTES | 8815366 | 0
|
|
OUTPUTMC | 1 | 1 | 2
|
|
INPUTS | 6 | A<6> | CP_CS | lan_adr | A<8> | A_LAN<7> | SET_FREQUENCY
|
|
INPUTMC | 4 | 4 | 1 | 14 | 13 | 1 | 2 | 11 | 0
|
|
INPUTP | 2 | 98 | 106
|
|
EQ | 4 |
|
|
!A_LAN<7>.D = !A<6> & !CP_CS
|
|
# CP_CS & !lan_adr & !A<8>
|
|
# CP_CS & lan_adr & !A_LAN<7> & !SET_FREQUENCY;
|
|
!A_LAN<7>.CLK = CLK_EXT; // GCK
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 5 | 9 | A_LAN_OUT<8>
|
|
ATTRIBUTES | 8815366 | 0
|
|
OUTPUTMC | 1 | 5 | 9
|
|
INPUTS | 6 | CP_CS | A<7> | lan_adr | A<9> | A_LAN<8> | SET_FREQUENCY
|
|
INPUTMC | 4 | 4 | 1 | 14 | 13 | 5 | 9 | 11 | 0
|
|
INPUTP | 2 | 100 | 108
|
|
EQ | 4 |
|
|
!A_LAN<8>.D = !CP_CS & !A<7>
|
|
# CP_CS & !lan_adr & !A<9>
|
|
# CP_CS & lan_adr & !A_LAN<8> & !SET_FREQUENCY;
|
|
!A_LAN<8>.CLK = CLK_EXT; // GCK
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 5 | 13 | A_LAN_OUT<9>
|
|
ATTRIBUTES | 8815366 | 0
|
|
OUTPUTMC | 1 | 5 | 13
|
|
INPUTS | 6 | CP_CS | A<8> | lan_adr | A<10> | A_LAN<9> | SET_FREQUENCY
|
|
INPUTMC | 4 | 4 | 1 | 14 | 13 | 5 | 13 | 11 | 0
|
|
INPUTP | 2 | 106 | 112
|
|
EQ | 4 |
|
|
!A_LAN<9>.D = !CP_CS & !A<8>
|
|
# CP_CS & !lan_adr & !A<10>
|
|
# CP_CS & lan_adr & !A_LAN<9> & !SET_FREQUENCY;
|
|
!A_LAN<9>.CLK = CLK_EXT; // GCK
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 7 | 9 | LAN_RD_OBUF
|
|
ATTRIBUTES | 264962 | 0
|
|
INPUTS | 4 | LAN_RD_S | SET_FREQUENCY | AS_D | $OpTx$FX_DC$30
|
|
INPUTMC | 4 | 0 | 10 | 11 | 0 | 0 | 6 | 5 | 11
|
|
EQ | 2 |
|
|
LAN_RD = !LAN_RD_S & $OpTx$FX_DC$30
|
|
# !LAN_RD_S & !SET_FREQUENCY & !AS_D;
|
|
|
|
MACROCELL | 11 | 0 | SET_FREQUENCY
|
|
ATTRIBUTES | 4358916 | 0
|
|
OUTPUTMC | 47 | 14 | 12 | 15 | 8 | 14 | 9 | 15 | 7 | 14 | 8 | 11 | 8 | 14 | 10 | 11 | 6 | 11 | 5 | 3 | 5 | 5 | 5 | 5 | 7 | 5 | 2 | 5 | 4 | 3 | 4 | 3 | 11 | 3 | 7 | 1 | 1 | 3 | 13 | 1 | 4 | 1 | 2 | 5 | 9 | 5 | 13 | 7 | 9 | 11 | 0 | 11 | 10 | 6 | 14 | 5 | 16 | 7 | 17 | 7 | 16 | 7 | 15 | 7 | 14 | 7 | 13 | 11 | 17 | 6 | 16 | 11 | 13 | 11 | 12 | 7 | 12 | 7 | 11 | 7 | 7 | 5 | 17 | 5 | 11 | 5 | 10 | 11 | 16 | 6 | 17 | 11 | 15 | 11 | 14
|
|
INPUTS | 3 | RESET | LAN_RST_SM_FSM_FFd1 | SET_FREQUENCY
|
|
INPUTMC | 2 | 14 | 12 | 11 | 0
|
|
INPUTP | 1 | 263
|
|
EQ | 2 |
|
|
SET_FREQUENCY.T = RESET & LAN_RST_SM_FSM_FFd1 & SET_FREQUENCY;
|
|
SET_FREQUENCY.CLK = CLK_EXT; // GCK
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 11 | 10 | CLEAR_REGISTER
|
|
ATTRIBUTES | 8553220 | 0
|
|
OUTPUTMC | 7 | 1 | 4 | 11 | 10 | 7 | 17 | 7 | 16 | 11 | 17 | 7 | 12 | 7 | 11
|
|
INPUTS | 4 | LAN_RST_SM_FSM_FFd5 | CLEAR_REGISTER | RESET | SET_FREQUENCY
|
|
INPUTMC | 3 | 14 | 9 | 11 | 10 | 11 | 0
|
|
INPUTP | 1 | 263
|
|
EQ | 3 |
|
|
CLEAR_REGISTER.D = !LAN_RST_SM_FSM_FFd5 & CLEAR_REGISTER
|
|
# !RESET & SET_FREQUENCY & CLEAR_REGISTER;
|
|
CLEAR_REGISTER.CLK = CLK_EXT; // GCK
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 6 | 14 | LAN_RST_SM_FSM_FFd8
|
|
ATTRIBUTES | 8553348 | 0
|
|
OUTPUTMC | 2 | 11 | 8 | 11 | 5
|
|
INPUTS | 2 | RESET | SET_FREQUENCY
|
|
INPUTMC | 1 | 11 | 0
|
|
INPUTP | 1 | 263
|
|
EQ | 3 |
|
|
LAN_RST_SM_FSM_FFd8.D = Gnd;
|
|
LAN_RST_SM_FSM_FFd8.CLK = CLK_EXT; // GCK
|
|
LAN_RST_SM_FSM_FFd8.AP = !RESET & SET_FREQUENCY;
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 0 | 6 | AS_D
|
|
ATTRIBUTES | 8520484 | 0
|
|
OUTPUTMC | 4 | 7 | 9 | 12 | 1 | 4 | 4 | 13 | 13
|
|
INPUTS | 3 | AS | RESET | lan_adr_sw/lan_adr_sw_CLKF
|
|
INPUTMC | 1 | 15 | 6
|
|
INPUTP | 2 | 152 | 263
|
|
EQ | 2 |
|
|
!AS_D.D = !AS & RESET;
|
|
AS_D.CLK = lan_adr_sw/lan_adr_sw_CLKF;
|
|
|
|
MACROCELL | 5 | 16 | D_IN<0>
|
|
ATTRIBUTES | 8553220 | 0
|
|
OUTPUTMC | 1 | 9 | 2
|
|
INPUTS | 6 | SET_FREQUENCY | D<0>.PIN | $OpTx$FX_DC$1 | D<8>.PIN | lan_adr | ide
|
|
INPUTMC | 4 | 11 | 0 | 5 | 14 | 14 | 13 | 10 | 17
|
|
INPUTP | 2 | 4 | 32
|
|
EQ | 4 |
|
|
D_IN<0>.D = D<8>.PIN & !SET_FREQUENCY & !$OpTx$FX_DC$1
|
|
# !SET_FREQUENCY & D<0>.PIN & $OpTx$FX_DC$1
|
|
# lan_adr & ide & !SET_FREQUENCY & $OpTx$FX_DC$1;
|
|
!D_IN<0>.CLK = CLK_EXT; // GCK
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 7 | 17 | D_IN<10>
|
|
ATTRIBUTES | 8553220 | 0
|
|
OUTPUTMC | 1 | 9 | 16
|
|
INPUTS | 6 | SET_FREQUENCY | CLEAR_REGISTER | $OpTx$FX_SC$321 | D<2>.PIN | D_OUT_and0001/D_OUT_and0001_D2 | D<10>.PIN
|
|
INPUTMC | 4 | 11 | 0 | 11 | 10 | 5 | 10 | 15 | 5
|
|
INPUTP | 2 | 71 | 74
|
|
EQ | 6 |
|
|
!D_IN<10>.D = SET_FREQUENCY & !CLEAR_REGISTER & !$OpTx$FX_SC$321
|
|
# !D<10>.PIN & !SET_FREQUENCY &
|
|
!D_OUT_and0001/D_OUT_and0001_D2 & !$OpTx$FX_SC$321
|
|
# !SET_FREQUENCY & !D<2>.PIN &
|
|
D_OUT_and0001/D_OUT_and0001_D2 & !$OpTx$FX_SC$321;
|
|
!D_IN<10>.CLK = CLK_EXT; // GCK
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 7 | 16 | D_IN<11>
|
|
ATTRIBUTES | 8553220 | 0
|
|
OUTPUTMC | 1 | 11 | 9
|
|
INPUTS | 6 | SET_FREQUENCY | CLEAR_REGISTER | $OpTx$FX_SC$321 | D<3>.PIN | D_OUT_and0001/D_OUT_and0001_D2 | D<11>.PIN
|
|
INPUTMC | 4 | 11 | 0 | 11 | 10 | 5 | 10 | 15 | 5
|
|
INPUTP | 2 | 28 | 77
|
|
EQ | 6 |
|
|
!D_IN<11>.D = SET_FREQUENCY & !CLEAR_REGISTER & !$OpTx$FX_SC$321
|
|
# !D<11>.PIN & !SET_FREQUENCY &
|
|
!D_OUT_and0001/D_OUT_and0001_D2 & !$OpTx$FX_SC$321
|
|
# !SET_FREQUENCY & !D<3>.PIN &
|
|
D_OUT_and0001/D_OUT_and0001_D2 & !$OpTx$FX_SC$321;
|
|
!D_IN<11>.CLK = CLK_EXT; // GCK
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 11 | 3 | D_IN<12>
|
|
ATTRIBUTES | 8553220 | 0
|
|
OUTPUTMC | 1 | 7 | 1
|
|
INPUTS | 1 | BUF_D_IN<12>
|
|
INPUTMC | 1 | 11 | 16
|
|
EQ | 2 |
|
|
D_IN<12>.D = BUF_D_IN<12>;
|
|
!D_IN<12>.CLK = CLK_EXT; // GCK
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 6 | 15 | D_IN<13>
|
|
ATTRIBUTES | 8553220 | 0
|
|
OUTPUTMC | 1 | 11 | 7
|
|
INPUTS | 1 | BUF_D_IN<13>
|
|
INPUTMC | 1 | 6 | 17
|
|
EQ | 2 |
|
|
D_IN<13>.D = BUF_D_IN<13>;
|
|
!D_IN<13>.CLK = CLK_EXT; // GCK
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 11 | 2 | D_IN<14>
|
|
ATTRIBUTES | 8553220 | 0
|
|
OUTPUTMC | 1 | 7 | 2
|
|
INPUTS | 1 | BUF_D_IN<14>
|
|
INPUTMC | 1 | 11 | 15
|
|
EQ | 2 |
|
|
D_IN<14>.D = BUF_D_IN<14>;
|
|
!D_IN<14>.CLK = CLK_EXT; // GCK
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 11 | 1 | D_IN<15>
|
|
ATTRIBUTES | 8553220 | 0
|
|
OUTPUTMC | 1 | 11 | 4
|
|
INPUTS | 1 | BUF_D_IN<15>
|
|
INPUTMC | 1 | 11 | 14
|
|
EQ | 2 |
|
|
D_IN<15>.D = BUF_D_IN<15>;
|
|
!D_IN<15>.CLK = CLK_EXT; // GCK
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 7 | 15 | D_IN<1>
|
|
ATTRIBUTES | 8553220 | 0
|
|
OUTPUTMC | 1 | 9 | 1
|
|
INPUTS | 6 | SET_FREQUENCY | D<1>.PIN | $OpTx$FX_DC$1 | D<9>.PIN | lan_adr | ide
|
|
INPUTMC | 4 | 11 | 0 | 5 | 14 | 14 | 13 | 10 | 17
|
|
INPUTP | 2 | 30 | 73
|
|
EQ | 4 |
|
|
D_IN<1>.D = D<9>.PIN & !SET_FREQUENCY & !$OpTx$FX_DC$1
|
|
# !SET_FREQUENCY & D<1>.PIN & $OpTx$FX_DC$1
|
|
# lan_adr & ide & !SET_FREQUENCY & $OpTx$FX_DC$1;
|
|
!D_IN<1>.CLK = CLK_EXT; // GCK
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 7 | 14 | D_IN<2>
|
|
ATTRIBUTES | 8553220 | 0
|
|
OUTPUTMC | 1 | 9 | 5
|
|
INPUTS | 6 | SET_FREQUENCY | D<2>.PIN | $OpTx$FX_DC$1 | D<10>.PIN | lan_adr | ide
|
|
INPUTMC | 4 | 11 | 0 | 5 | 14 | 14 | 13 | 10 | 17
|
|
INPUTP | 2 | 71 | 74
|
|
EQ | 4 |
|
|
D_IN<2>.D = D<10>.PIN & !SET_FREQUENCY & !$OpTx$FX_DC$1
|
|
# !SET_FREQUENCY & D<2>.PIN & $OpTx$FX_DC$1
|
|
# lan_adr & ide & !SET_FREQUENCY & $OpTx$FX_DC$1;
|
|
!D_IN<2>.CLK = CLK_EXT; // GCK
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 7 | 13 | D_IN<3>
|
|
ATTRIBUTES | 8553220 | 0
|
|
OUTPUTMC | 1 | 9 | 4
|
|
INPUTS | 6 | SET_FREQUENCY | D<3>.PIN | $OpTx$FX_DC$1 | D<11>.PIN | lan_adr | ide
|
|
INPUTMC | 4 | 11 | 0 | 5 | 14 | 14 | 13 | 10 | 17
|
|
INPUTP | 2 | 28 | 77
|
|
EQ | 4 |
|
|
D_IN<3>.D = D<11>.PIN & !SET_FREQUENCY & !$OpTx$FX_DC$1
|
|
# !SET_FREQUENCY & D<3>.PIN & $OpTx$FX_DC$1
|
|
# lan_adr & ide & !SET_FREQUENCY & $OpTx$FX_DC$1;
|
|
!D_IN<3>.CLK = CLK_EXT; // GCK
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 11 | 17 | D_IN<4>
|
|
ATTRIBUTES | 8553220 | 0
|
|
OUTPUTMC | 1 | 9 | 9
|
|
INPUTS | 8 | BUF_D_IN<12> | $OpTx$FX_SC$52 | SET_FREQUENCY | CLEAR_REGISTER | D<4>.PIN | $OpTx$FX_DC$1 | D<12>.PIN | D_OUT_and0001/D_OUT_and0001_D2
|
|
INPUTMC | 6 | 11 | 16 | 5 | 15 | 11 | 0 | 11 | 10 | 5 | 14 | 15 | 5
|
|
INPUTP | 2 | 38 | 78
|
|
EQ | 6 |
|
|
D_IN<4>.D = SET_FREQUENCY & !CLEAR_REGISTER
|
|
# BUF_D_IN<12> & $OpTx$FX_SC$52
|
|
# D<12>.PIN & !SET_FREQUENCY &
|
|
D_OUT_and0001/D_OUT_and0001_D2
|
|
# !SET_FREQUENCY & D<4>.PIN & $OpTx$FX_DC$1;
|
|
!D_IN<4>.CLK = CLK_EXT; // GCK
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 6 | 16 | D_IN<5>
|
|
ATTRIBUTES | 8553220 | 0
|
|
OUTPUTMC | 1 | 9 | 7
|
|
INPUTS | 7 | BUF_D_IN<13> | $OpTx$FX_SC$52 | SET_FREQUENCY | D<5>.PIN | $OpTx$FX_DC$1 | D<13>.PIN | D_OUT_and0001/D_OUT_and0001_D2
|
|
INPUTMC | 5 | 6 | 17 | 5 | 15 | 11 | 0 | 5 | 14 | 15 | 5
|
|
INPUTP | 2 | 37 | 80
|
|
EQ | 5 |
|
|
D_IN<5>.D = BUF_D_IN<13> & $OpTx$FX_SC$52
|
|
# D<13>.PIN & !SET_FREQUENCY &
|
|
D_OUT_and0001/D_OUT_and0001_D2
|
|
# !SET_FREQUENCY & D<5>.PIN & $OpTx$FX_DC$1;
|
|
!D_IN<5>.CLK = CLK_EXT; // GCK
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 11 | 13 | D_IN<6>
|
|
ATTRIBUTES | 8553220 | 0
|
|
OUTPUTMC | 1 | 9 | 11
|
|
INPUTS | 7 | BUF_D_IN<14> | $OpTx$FX_SC$52 | SET_FREQUENCY | D<6>.PIN | $OpTx$FX_DC$1 | D<14>.PIN | D_OUT_and0001/D_OUT_and0001_D2
|
|
INPUTMC | 5 | 11 | 15 | 5 | 15 | 11 | 0 | 5 | 14 | 15 | 5
|
|
INPUTP | 2 | 26 | 81
|
|
EQ | 5 |
|
|
D_IN<6>.D = BUF_D_IN<14> & $OpTx$FX_SC$52
|
|
# D<14>.PIN & !SET_FREQUENCY &
|
|
D_OUT_and0001/D_OUT_and0001_D2
|
|
# !SET_FREQUENCY & D<6>.PIN & $OpTx$FX_DC$1;
|
|
!D_IN<6>.CLK = CLK_EXT; // GCK
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 11 | 12 | D_IN<7>
|
|
ATTRIBUTES | 8553220 | 0
|
|
OUTPUTMC | 1 | 9 | 10
|
|
INPUTS | 7 | BUF_D_IN<15> | $OpTx$FX_SC$52 | SET_FREQUENCY | D<7>.PIN | $OpTx$FX_DC$1 | D<15>.PIN | D_OUT_and0001/D_OUT_and0001_D2
|
|
INPUTMC | 5 | 11 | 14 | 5 | 15 | 11 | 0 | 5 | 14 | 15 | 5
|
|
INPUTP | 2 | 29 | 89
|
|
EQ | 5 |
|
|
D_IN<7>.D = BUF_D_IN<15> & $OpTx$FX_SC$52
|
|
# D<15>.PIN & !SET_FREQUENCY &
|
|
D_OUT_and0001/D_OUT_and0001_D2
|
|
# !SET_FREQUENCY & D<7>.PIN & $OpTx$FX_DC$1;
|
|
!D_IN<7>.CLK = CLK_EXT; // GCK
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 7 | 12 | D_IN<8>
|
|
ATTRIBUTES | 8553220 | 0
|
|
OUTPUTMC | 1 | 9 | 13
|
|
INPUTS | 6 | SET_FREQUENCY | CLEAR_REGISTER | $OpTx$FX_SC$321 | D<0>.PIN | D_OUT_and0001/D_OUT_and0001_D2 | D<8>.PIN
|
|
INPUTMC | 4 | 11 | 0 | 11 | 10 | 5 | 10 | 15 | 5
|
|
INPUTP | 2 | 4 | 32
|
|
EQ | 6 |
|
|
!D_IN<8>.D = SET_FREQUENCY & CLEAR_REGISTER & !$OpTx$FX_SC$321
|
|
# !D<8>.PIN & !SET_FREQUENCY &
|
|
!D_OUT_and0001/D_OUT_and0001_D2 & !$OpTx$FX_SC$321
|
|
# !SET_FREQUENCY & !D<0>.PIN &
|
|
D_OUT_and0001/D_OUT_and0001_D2 & !$OpTx$FX_SC$321;
|
|
!D_IN<8>.CLK = CLK_EXT; // GCK
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 7 | 11 | D_IN<9>
|
|
ATTRIBUTES | 8553220 | 0
|
|
OUTPUTMC | 1 | 11 | 11
|
|
INPUTS | 6 | SET_FREQUENCY | CLEAR_REGISTER | $OpTx$FX_SC$321 | D<1>.PIN | D_OUT_and0001/D_OUT_and0001_D2 | D<9>.PIN
|
|
INPUTMC | 4 | 11 | 0 | 11 | 10 | 5 | 10 | 15 | 5
|
|
INPUTP | 2 | 30 | 73
|
|
EQ | 6 |
|
|
!D_IN<9>.D = SET_FREQUENCY & !CLEAR_REGISTER & !$OpTx$FX_SC$321
|
|
# !D<9>.PIN & !SET_FREQUENCY &
|
|
!D_OUT_and0001/D_OUT_and0001_D2 & !$OpTx$FX_SC$321
|
|
# !SET_FREQUENCY & !D<1>.PIN &
|
|
D_OUT_and0001/D_OUT_and0001_D2 & !$OpTx$FX_SC$321;
|
|
!D_IN<9>.CLK = CLK_EXT; // GCK
|
|
GLOBALS | 1 | 2 | CLK_EXT
|
|
|
|
MACROCELL | 13 | 10 | CFOUT_OBUF
|
|
ATTRIBUTES | 396034 | 0
|
|
OUTPUTMC | 2 | 10 | 12 | 8 | 11
|
|
INPUTS | 2 | AUTO_CONFIG_DONE<1> | AUTO_CONFIG_DONE<0>
|
|
INPUTMC | 2 | 13 | 8 | 13 | 7
|
|
EQ | 1 |
|
|
!CFOUT = !AUTO_CONFIG_DONE<1> & !AUTO_CONFIG_DONE<0>;
|
|
|
|
MACROCELL | 12 | 1 | CP_RD_OBUF
|
|
ATTRIBUTES | 264962 | 0
|
|
INPUTS | 3 | CP_RD_S | AS | AS_D
|
|
INPUTMC | 2 | 9 | 15 | 0 | 6
|
|
INPUTP | 1 | 152
|
|
EQ | 2 |
|
|
CP_RD = CP_RD_S
|
|
# AS & AS_D;
|
|
|
|
MACROCELL | 10 | 16 | CP_WE_OBUF
|
|
ATTRIBUTES | 264962 | 0
|
|
OUTPUTMC | 1 | 10 | 17
|
|
INPUTS | 7 | IDE_BASEADR<0> | A<16> | IDE_BASEADR<1> | A<17> | IDE_BASEADR<2> | A<18> | CP_WE_QUIRK.EXP
|
|
INPUTMC | 4 | 2 | 12 | 2 | 11 | 12 | 11 | 10 | 15
|
|
INPUTP | 3 | 175 | 172 | 171
|
|
EXPORTS | 1 | 10 | 17
|
|
IMPORTS | 1 | 10 | 15
|
|
EQ | 7 |
|
|
!CP_WE = ;Imported pterms FB11_16
|
|
!AS & !CP_WE_S & CP_WE_QUIRK;
|
|
CP_WE_OBUF.EXP = IDE_BASEADR<0> & !A<16>
|
|
# !IDE_BASEADR<0> & A<16>
|
|
# IDE_BASEADR<1> & !A<17>
|
|
# !IDE_BASEADR<1> & A<17>
|
|
# !IDE_BASEADR<2> & A<18>
|
|
|
|
MACROCELL | 0 | 16 | IDE_R_OBUF
|
|
ATTRIBUTES | 264962 | 0
|
|
INPUTS | 2 | AS | IDE_R_S
|
|
INPUTMC | 1 | 0 | 15
|
|
INPUTP | 1 | 152
|
|
EQ | 1 |
|
|
!IDE_R = !AS & !IDE_R_S;
|
|
|
|
MACROCELL | 2 | 1 | IDE_W_OBUF
|
|
ATTRIBUTES | 264962 | 0
|
|
INPUTS | 2 | AS | IDE_W_S
|
|
INPUTMC | 1 | 0 | 12
|
|
INPUTP | 1 | 152
|
|
EQ | 1 |
|
|
!IDE_W = !AS & !IDE_W_S;
|
|
|
|
MACROCELL | 7 | 7 | LAN_CS_OBUF
|
|
ATTRIBUTES | 264962 | 0
|
|
INPUTS | 3 | lan_adr | SET_FREQUENCY | LAN_CS_RST
|
|
INPUTMC | 3 | 14 | 13 | 11 | 0 | 11 | 8
|
|
EQ | 2 |
|
|
LAN_CS = !lan_adr & !SET_FREQUENCY
|
|
# !LAN_CS_RST & SET_FREQUENCY;
|
|
|
|
MACROCELL | 7 | 4 | LAN_WRH_OBUF
|
|
ATTRIBUTES | 264962 | 0
|
|
INPUTS | 3 | LAN_WR_RST | $OpTx$FX_DC$30 | LAN_WRH_S
|
|
INPUTMC | 3 | 14 | 8 | 5 | 11 | 9 | 12
|
|
EQ | 2 |
|
|
LAN_WRH = !LAN_WR_RST & !$OpTx$FX_DC$30
|
|
# !LAN_WRH_S & $OpTx$FX_DC$30;
|
|
|
|
MACROCELL | 12 | 13 | LAN_WRL_OBUF
|
|
ATTRIBUTES | 264962 | 0
|
|
INPUTS | 3 | LAN_WR_RST | $OpTx$FX_DC$30 | LAN_WRL_S
|
|
INPUTMC | 3 | 14 | 8 | 5 | 11 | 9 | 8
|
|
EQ | 2 |
|
|
LAN_WRL = !LAN_WR_RST & !$OpTx$FX_DC$30
|
|
# !LAN_WRL_S & $OpTx$FX_DC$30;
|
|
|
|
MACROCELL | 4 | 4 | ROM_OE_OBUF
|
|
ATTRIBUTES | 264962 | 0
|
|
INPUTS | 3 | ROM_OE_S | AS | AS_D
|
|
INPUTMC | 2 | 0 | 8 | 0 | 6
|
|
INPUTP | 1 | 152
|
|
EQ | 2 |
|
|
ROM_OE = ROM_OE_S
|
|
# AS & AS_D;
|
|
|
|
MACROCELL | 13 | 13 | SLAVE_OBUF
|
|
ATTRIBUTES | 396034 | 0
|
|
OUTPUTMC | 16 | 3 | 1 | 4 | 13 | 4 | 14 | 1 | 14 | 4 | 9 | 1 | 11 | 0 | 5 | 0 | 4 | 1 | 9 | 1 | 13 | 1 | 16 | 4 | 11 | 4 | 16 | 6 | 2 | 6 | 4 | 6 | 11
|
|
INPUTS | 6 | AS | AS_D | CP_CS | autoconfig | lan_adr | ide
|
|
INPUTMC | 5 | 0 | 6 | 4 | 1 | 10 | 12 | 14 | 13 | 10 | 17
|
|
INPUTP | 1 | 152
|
|
EQ | 2 |
|
|
SLAVE = AS & AS_D
|
|
# CP_CS & autoconfig & lan_adr & ide;
|
|
|
|
MACROCELL | 5 | 1 | ROM_B_0_OBUF$BUF4
|
|
ATTRIBUTES | 265986 | 0
|
|
INPUTS | 1 | CP_IRQ
|
|
INPUTP | 1 | 59
|
|
EQ | 2 |
|
|
INT6_OUT = Gnd;
|
|
INT6_OUT.OE = !CP_IRQ;
|
|
|
|
MACROCELL | 2 | 13 | ROM_B_0_OBUF$BUF5
|
|
ATTRIBUTES | 265986 | 0
|
|
INPUTS | 2 | LAN_INT_ENABLE | LAN_IRQ_OUT
|
|
INPUTMC | 2 | 9 | 17 | 2 | 17
|
|
EQ | 2 |
|
|
INT2_OUT = Gnd;
|
|
INT2_OUT.OE = !LAN_INT_ENABLE & !LAN_IRQ_OUT;
|
|
|
|
MACROCELL | 0 | 11 | IDE_A_0_OBUF$BUF0
|
|
ATTRIBUTES | 264962 | 0
|
|
INPUTS | 1 | A<9>
|
|
INPUTP | 1 | 108
|
|
EQ | 1 |
|
|
IDE_A<0> = A<9>;
|
|
|
|
MACROCELL | 0 | 14 | IDE_A_1_OBUF$BUF0
|
|
ATTRIBUTES | 264962 | 0
|
|
INPUTS | 1 | A<10>
|
|
INPUTP | 1 | 112
|
|
EQ | 1 |
|
|
IDE_A<1> = A<10>;
|
|
|
|
MACROCELL | 0 | 13 | IDE_A_2_OBUF$BUF0
|
|
ATTRIBUTES | 264962 | 0
|
|
INPUTS | 1 | A<11>
|
|
INPUTP | 1 | 114
|
|
EQ | 1 |
|
|
IDE_A<2> = A<11>;
|
|
|
|
MACROCELL | 0 | 7 | IDE_CS_0_OBUF
|
|
ATTRIBUTES | 264962 | 0
|
|
INPUTS | 1 | A<12>
|
|
INPUTP | 1 | 115
|
|
EQ | 1 |
|
|
IDE_CS<0> = !A<12>;
|
|
|
|
MACROCELL | 0 | 9 | IDE_CS_1_OBUF
|
|
ATTRIBUTES | 264962 | 0
|
|
INPUTS | 1 | A<13>
|
|
INPUTP | 1 | 123
|
|
EQ | 1 |
|
|
IDE_CS<1> = !A<13>;
|
|
|
|
MACROCELL | 13 | 14 | ROM_B_0_OBUF$BUF1
|
|
ATTRIBUTES | 265986 | 0
|
|
OUTPUTMC | 1 | 13 | 15
|
|
INPUTS | 8 | A<5> | A<4> | A<1> | A<6> | A<3> | AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2 | AUTO_CONFIG_DONE<1> | A<2>
|
|
INPUTMC | 2 | 0 | 2 | 13 | 8
|
|
INPUTP | 6 | 91 | 97 | 107 | 98 | 99 | 101
|
|
EXPORTS | 1 | 13 | 15
|
|
EQ | 12 |
|
|
OWN = Gnd;
|
|
OWN.OE = Gnd;
|
|
ROM_B_0_OBUF$BUF1.EXP = !A<5> & A<4> & !A<1> & !A<6> & A<3> &
|
|
AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2
|
|
# AUTO_CONFIG_DONE<1> & !A<5> & !A<2> & A<1> &
|
|
!A<6> & !A<3> &
|
|
AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2
|
|
# AUTO_CONFIG_DONE<1> & !A<4> & A<2> & !A<1> &
|
|
!A<6> & !A<3> &
|
|
AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2
|
|
# A<5> & !A<4> & A<2> & !A<1> & !A<6> & !A<3> &
|
|
AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2
|
|
|
|
MACROCELL | 13 | 2 | ROM_B_0_OBUF$BUF2
|
|
ATTRIBUTES | 265986 | 0
|
|
OUTPUTMC | 1 | 13 | 3
|
|
INPUTS | 8 | AUTO_CONFIG_DONE<1> | A<4> | A<2> | A<1> | A<6> | A<3> | AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2 | A<5>
|
|
INPUTMC | 2 | 13 | 8 | 0 | 2
|
|
INPUTP | 6 | 97 | 101 | 107 | 98 | 99 | 91
|
|
EXPORTS | 1 | 13 | 3
|
|
EQ | 9 |
|
|
OVR = Gnd;
|
|
OVR.OE = Gnd;
|
|
ROM_B_0_OBUF$BUF2.EXP = !AUTO_CONFIG_DONE<1> & !A<4> & A<2> & A<1> &
|
|
!A<6> & !A<3> &
|
|
AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2
|
|
# !A<5> & A<4> & A<2> & A<1> & !A<6> & !A<3> &
|
|
AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2
|
|
# !A<5> & A<4> & A<2> & !A<1> & !A<6> & A<3> &
|
|
AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2
|
|
|
|
MACROCELL | 15 | 9 | ROM_B_0_OBUF$BUF3
|
|
ATTRIBUTES | 265986 | 0
|
|
INPUTS | 0
|
|
EQ | 2 |
|
|
MTACK = Gnd;
|
|
MTACK.OE = Gnd;
|
|
|
|
MACROCELL | 14 | 11 | ROM_B_0_OBUF$BUF6
|
|
ATTRIBUTES | 265986 | 0
|
|
INPUTS | 0
|
|
EQ | 2 |
|
|
DTACK = Gnd;
|
|
DTACK.OE = Gnd;
|
|
|
|
MACROCELL | 10 | 13 | ROM_B_0_OBUF
|
|
ATTRIBUTES | 264962 | 0
|
|
INPUTS | 0
|
|
EQ | 1 |
|
|
ROM_B<1> = Gnd;
|
|
|
|
MACROCELL | 10 | 11 | ROM_B_0_OBUF$BUF0
|
|
ATTRIBUTES | 264962 | 0
|
|
INPUTS | 0
|
|
EQ | 1 |
|
|
ROM_B<0> = Gnd;
|
|
|
|
MACROCELL | 13 | 4 | D_OUT_or0002/D_OUT_or0002_D2
|
|
ATTRIBUTES | 133888 | 0
|
|
OUTPUTMC | 17 | 3 | 1 | 4 | 13 | 4 | 14 | 1 | 14 | 4 | 9 | 1 | 11 | 0 | 5 | 0 | 4 | 1 | 9 | 1 | 13 | 1 | 16 | 4 | 11 | 4 | 16 | 6 | 2 | 6 | 4 | 6 | 11 | 13 | 3
|
|
INPUTS | 14 | $OpTx$FX_DC$19 | CP_CS | autoconfig | lan_adr | ide | AUTO_CONFIG_DONE<0> | A<4> | A<2> | A<1> | A<6> | A<3> | AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2 | A<5> | AUTO_CONFIG_DONE<1>
|
|
INPUTMC | 8 | 9 | 3 | 4 | 1 | 10 | 12 | 14 | 13 | 10 | 17 | 13 | 7 | 0 | 2 | 13 | 8
|
|
INPUTP | 6 | 97 | 101 | 107 | 98 | 99 | 91
|
|
EXPORTS | 1 | 13 | 3
|
|
EQ | 10 |
|
|
D_OUT_or0002/D_OUT_or0002_D2 = $OpTx$FX_DC$19
|
|
# CP_CS & autoconfig & lan_adr & ide;
|
|
D_OUT_or0002/D_OUT_or0002_D2.EXP = !AUTO_CONFIG_DONE<0> & !A<4> & A<2> & A<1> &
|
|
!A<6> & !A<3> &
|
|
AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2
|
|
# A<5> & !A<4> & A<2> & A<1> & !A<6> & !A<3> &
|
|
AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2
|
|
# AUTO_CONFIG_DONE<1> & !A<5> & !A<4> & A<2> &
|
|
!A<1> & !A<6> & !A<3> &
|
|
AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2
|
|
|
|
MACROCELL | 9 | 3 | $OpTx$FX_DC$19
|
|
ATTRIBUTES | 133888 | 0
|
|
OUTPUTMC | 8 | 9 | 14 | 0 | 15 | 0 | 12 | 0 | 10 | 0 | 8 | 13 | 4 | 0 | 3 | 0 | 2
|
|
INPUTS | 2 | UDS | LDS
|
|
INPUTP | 2 | 155 | 157
|
|
EQ | 1 |
|
|
$OpTx$FX_DC$19 = UDS & LDS;
|
|
|
|
MACROCELL | 5 | 12 | $OpTx$FX_DC$3
|
|
ATTRIBUTES | 133888 | 0
|
|
OUTPUTMC | 8 | 3 | 1 | 1 | 14 | 4 | 9 | 1 | 11 | 0 | 5 | 0 | 4 | 1 | 9 | 1 | 13
|
|
INPUTS | 2 | CP_CS | D_OUT_and0001/D_OUT_and0001_D2
|
|
INPUTMC | 2 | 4 | 1 | 15 | 5
|
|
EQ | 1 |
|
|
$OpTx$FX_DC$3 = CP_CS & D_OUT_and0001/D_OUT_and0001_D2;
|
|
|
|
MACROCELL | 15 | 5 | D_OUT_and0001/D_OUT_and0001_D2
|
|
ATTRIBUTES | 133888 | 0
|
|
OUTPUTMC | 15 | 7 | 17 | 7 | 16 | 11 | 17 | 6 | 16 | 11 | 13 | 11 | 12 | 7 | 12 | 7 | 11 | 5 | 12 | 5 | 14 | 11 | 16 | 6 | 17 | 11 | 15 | 11 | 14 | 5 | 15
|
|
INPUTS | 2 | lan_adr | lan_adr_sw
|
|
INPUTMC | 2 | 14 | 13 | 14 | 14
|
|
EQ | 1 |
|
|
D_OUT_and0001/D_OUT_and0001_D2 = !lan_adr & !lan_adr_sw;
|
|
|
|
MACROCELL | 5 | 14 | $OpTx$FX_DC$1
|
|
ATTRIBUTES | 133888 | 0
|
|
OUTPUTMC | 16 | 4 | 13 | 4 | 14 | 1 | 16 | 4 | 11 | 4 | 16 | 6 | 2 | 6 | 4 | 6 | 11 | 5 | 16 | 7 | 15 | 7 | 14 | 7 | 13 | 11 | 17 | 6 | 16 | 11 | 13 | 11 | 12
|
|
INPUTS | 2 | CP_CS | D_OUT_and0001/D_OUT_and0001_D2
|
|
INPUTMC | 2 | 4 | 1 | 15 | 5
|
|
EQ | 1 |
|
|
$OpTx$FX_DC$1 = CP_CS & !D_OUT_and0001/D_OUT_and0001_D2;
|
|
|
|
MACROCELL | 15 | 6 | lan_adr_sw/lan_adr_sw_CLKF
|
|
ATTRIBUTES | 133888 | 0
|
|
OUTPUTMC | 54 | 13 | 8 | 13 | 7 | 9 | 17 | 13 | 5 | 13 | 6 | 2 | 16 | 2 | 15 | 12 | 17 | 12 | 16 | 12 | 15 | 12 | 14 | 2 | 14 | 12 | 12 | 13 | 0 | 13 | 15 | 13 | 3 | 8 | 17 | 2 | 12 | 2 | 11 | 12 | 11 | 12 | 10 | 12 | 9 | 12 | 8 | 2 | 10 | 12 | 7 | 8 | 16 | 8 | 15 | 8 | 14 | 8 | 13 | 8 | 12 | 14 | 17 | 14 | 16 | 14 | 15 | 2 | 17 | 4 | 1 | 10 | 12 | 14 | 13 | 10 | 17 | 0 | 17 | 9 | 14 | 2 | 9 | 14 | 14 | 10 | 14 | 2 | 8 | 12 | 6 | 9 | 15 | 10 | 15 | 0 | 15 | 0 | 12 | 0 | 10 | 9 | 12 | 9 | 8 | 0 | 8 | 0 | 6
|
|
INPUTS | 2 | C3 | C1
|
|
INPUTP | 2 | 187 | 188
|
|
EQ | 2 |
|
|
!lan_adr_sw/lan_adr_sw_CLKF = C3
|
|
$ C1;
|
|
|
|
MACROCELL | 0 | 3 | $OpTx$FX_DC$34
|
|
ATTRIBUTES | 133888 | 0
|
|
OUTPUTMC | 2 | 9 | 17 | 2 | 17
|
|
INPUTS | 4 | A<15> | RW | lan_adr | $OpTx$FX_DC$19
|
|
INPUTMC | 2 | 14 | 13 | 9 | 3
|
|
INPUTP | 2 | 139 | 158
|
|
EQ | 1 |
|
|
$OpTx$FX_DC$34 = A<15> & !RW & !lan_adr & !$OpTx$FX_DC$19;
|
|
|
|
MACROCELL | 0 | 2 | AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2
|
|
ATTRIBUTES | 133888 | 0
|
|
OUTPUTMC | 17 | 13 | 5 | 13 | 6 | 13 | 0 | 13 | 15 | 13 | 3 | 8 | 17 | 8 | 11 | 3 | 17 | 8 | 10 | 8 | 0 | 8 | 16 | 13 | 1 | 13 | 2 | 13 | 4 | 13 | 14 | 13 | 16 | 13 | 17
|
|
INPUTS | 3 | AS | autoconfig | $OpTx$FX_DC$19
|
|
INPUTMC | 2 | 10 | 12 | 9 | 3
|
|
INPUTP | 1 | 152
|
|
EQ | 1 |
|
|
AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2 = !AS & !autoconfig & !$OpTx$FX_DC$19;
|
|
|
|
MACROCELL | 8 | 11 | $OpTx$FX_DC$31
|
|
ATTRIBUTES | 133888 | 0
|
|
OUTPUTMC | 3 | 13 | 5 | 13 | 6 | 13 | 9
|
|
INPUTS | 8 | RW | A<5> | A<4> | A<1> | A<6> | A<3> | CFOUT | AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2
|
|
INPUTMC | 2 | 13 | 10 | 0 | 2
|
|
INPUTP | 6 | 158 | 91 | 97 | 107 | 98 | 99
|
|
EQ | 3 |
|
|
$OpTx$FX_DC$31 = !RW & !A<5> & !A<4> & !A<1> & A<6> & A<3> &
|
|
CFOUT &
|
|
AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2;
|
|
|
|
MACROCELL | 3 | 17 | CP_BASEADR_not0001/CP_BASEADR_not0001_D2
|
|
ATTRIBUTES | 133888 | 0
|
|
OUTPUTMC | 9 | 2 | 16 | 2 | 15 | 12 | 17 | 12 | 16 | 12 | 15 | 12 | 14 | 2 | 14 | 12 | 12 | 2 | 8
|
|
INPUTS | 10 | AUTO_CONFIG_DONE<1> | AUTO_CONFIG_DONE<0> | RW | A<5> | A<4> | A<2> | A<1> | A<6> | A<3> | AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2
|
|
INPUTMC | 3 | 13 | 8 | 13 | 7 | 0 | 2
|
|
INPUTP | 7 | 158 | 91 | 97 | 101 | 107 | 98 | 99
|
|
EQ | 3 |
|
|
CP_BASEADR_not0001/CP_BASEADR_not0001_D2 = AUTO_CONFIG_DONE<1> & !AUTO_CONFIG_DONE<0> & !RW &
|
|
!A<5> & !A<4> & !A<2> & !A<1> & A<6> & A<3> &
|
|
AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2;
|
|
|
|
MACROCELL | 13 | 9 | IDE_BASEADR_not0001/IDE_BASEADR_not0001_D2
|
|
ATTRIBUTES | 133888 | 0
|
|
OUTPUTMC | 10 | 2 | 12 | 2 | 11 | 12 | 11 | 12 | 10 | 12 | 9 | 12 | 8 | 2 | 10 | 12 | 7 | 12 | 6 | 8 | 10
|
|
INPUTS | 3 | AUTO_CONFIG_DONE<1> | A<2> | $OpTx$FX_DC$31
|
|
INPUTMC | 2 | 13 | 8 | 8 | 11
|
|
INPUTP | 1 | 101
|
|
EQ | 1 |
|
|
IDE_BASEADR_not0001/IDE_BASEADR_not0001_D2 = !AUTO_CONFIG_DONE<1> & !A<2> & $OpTx$FX_DC$31;
|
|
|
|
MACROCELL | 8 | 10 | LAN_BASEADR_not0001/LAN_BASEADR_not0001_D2
|
|
ATTRIBUTES | 133888 | 0
|
|
OUTPUTMC | 9 | 8 | 16 | 8 | 15 | 8 | 14 | 8 | 13 | 8 | 12 | 14 | 17 | 14 | 16 | 14 | 15 | 10 | 14
|
|
INPUTS | 10 | AUTO_CONFIG_DONE<0> | RW | A<5> | A<4> | A<2> | A<1> | A<6> | A<3> | AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2 | IDE_BASEADR_not0001/IDE_BASEADR_not0001_D2
|
|
INPUTMC | 3 | 13 | 7 | 0 | 2 | 13 | 9
|
|
INPUTP | 7 | 158 | 91 | 97 | 101 | 107 | 98 | 99
|
|
EQ | 3 |
|
|
LAN_BASEADR_not0001/LAN_BASEADR_not0001_D2 = AUTO_CONFIG_DONE<0> & !RW & !A<5> & !A<4> & !A<2> &
|
|
!A<1> & A<6> & A<3> &
|
|
AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2 & !IDE_BASEADR_not0001/IDE_BASEADR_not0001_D2;
|
|
|
|
MACROCELL | 9 | 6 | DQ_9_IOBUFE/DQ_9_IOBUFE_TRST
|
|
ATTRIBUTES | 133888 | 0
|
|
OUTPUTMC | 16 | 9 | 2 | 9 | 16 | 11 | 9 | 7 | 1 | 11 | 7 | 7 | 2 | 11 | 4 | 9 | 1 | 9 | 5 | 9 | 4 | 9 | 9 | 9 | 7 | 9 | 11 | 9 | 10 | 9 | 13 | 11 | 11
|
|
INPUTS | 4 | DQ_or0001/DQ_or0001_D2 | AS | RW | ide
|
|
INPUTMC | 2 | 5 | 17 | 10 | 17
|
|
INPUTP | 2 | 152 | 158
|
|
EQ | 2 |
|
|
DQ_9_IOBUFE/DQ_9_IOBUFE_TRST = !DQ_or0001/DQ_or0001_D2
|
|
# AS & RW & !ide;
|
|
|
|
MACROCELL | 5 | 17 | DQ_or0001/DQ_or0001_D2
|
|
ATTRIBUTES | 133888 | 0
|
|
OUTPUTMC | 17 | 9 | 2 | 9 | 16 | 11 | 9 | 7 | 1 | 11 | 7 | 7 | 2 | 11 | 4 | 9 | 1 | 9 | 5 | 9 | 4 | 9 | 9 | 9 | 7 | 9 | 11 | 9 | 10 | 9 | 13 | 11 | 11 | 9 | 6
|
|
INPUTS | 6 | AS | SET_FREQUENCY | RW | CP_CS | lan_adr | ide
|
|
INPUTMC | 4 | 11 | 0 | 4 | 1 | 14 | 13 | 10 | 17
|
|
INPUTP | 2 | 152 | 158
|
|
EQ | 3 |
|
|
DQ_or0001/DQ_or0001_D2 = AS & !SET_FREQUENCY
|
|
# RW & !SET_FREQUENCY
|
|
# CP_CS & lan_adr & ide & !SET_FREQUENCY;
|
|
|
|
MACROCELL | 15 | 17 | $OpTx$FX_DC$38
|
|
ATTRIBUTES | 133888 | 0
|
|
OUTPUTMC | 2 | 14 | 13 | 14 | 14
|
|
INPUTS | 2 | A<16> | LAN_BASEADR<0>
|
|
INPUTMC | 1 | 8 | 16
|
|
INPUTP | 1 | 175
|
|
EQ | 2 |
|
|
$OpTx$FX_DC$38 = A<16>
|
|
$ LAN_BASEADR<0>;
|
|
|
|
MACROCELL | 15 | 16 | $OpTx$FX_DC$39
|
|
ATTRIBUTES | 133888 | 0
|
|
OUTPUTMC | 2 | 14 | 13 | 14 | 14
|
|
INPUTS | 2 | A<17> | LAN_BASEADR<1>
|
|
INPUTMC | 1 | 8 | 15
|
|
INPUTP | 1 | 172
|
|
EQ | 2 |
|
|
$OpTx$FX_DC$39 = A<17>
|
|
$ LAN_BASEADR<1>;
|
|
|
|
MACROCELL | 15 | 15 | $OpTx$FX_DC$40
|
|
ATTRIBUTES | 133888 | 0
|
|
OUTPUTMC | 2 | 14 | 13 | 14 | 14
|
|
INPUTS | 2 | A<18> | LAN_BASEADR<2>
|
|
INPUTMC | 1 | 8 | 14
|
|
INPUTP | 1 | 171
|
|
EQ | 2 |
|
|
$OpTx$FX_DC$40 = A<18>
|
|
$ LAN_BASEADR<2>;
|
|
|
|
MACROCELL | 15 | 11 | $OpTx$FX_DC$44
|
|
ATTRIBUTES | 133888 | 0
|
|
OUTPUTMC | 2 | 14 | 13 | 14 | 14
|
|
INPUTS | 2 | A<22> | LAN_BASEADR<6>
|
|
INPUTMC | 1 | 14 | 16
|
|
INPUTP | 1 | 162
|
|
EQ | 2 |
|
|
$OpTx$FX_DC$44 = A<22>
|
|
$ LAN_BASEADR<6>;
|
|
|
|
MACROCELL | 15 | 14 | $OpTx$FX_DC$41
|
|
ATTRIBUTES | 133888 | 0
|
|
OUTPUTMC | 2 | 14 | 13 | 14 | 14
|
|
INPUTS | 2 | A<19> | LAN_BASEADR<3>
|
|
INPUTMC | 1 | 8 | 13
|
|
INPUTP | 1 | 169
|
|
EQ | 2 |
|
|
$OpTx$FX_DC$41 = A<19>
|
|
$ LAN_BASEADR<3>;
|
|
|
|
MACROCELL | 15 | 13 | $OpTx$FX_DC$42
|
|
ATTRIBUTES | 133888 | 0
|
|
OUTPUTMC | 2 | 14 | 13 | 14 | 14
|
|
INPUTS | 2 | A<20> | LAN_BASEADR<4>
|
|
INPUTMC | 1 | 8 | 12
|
|
INPUTP | 1 | 167
|
|
EQ | 2 |
|
|
$OpTx$FX_DC$42 = A<20>
|
|
$ LAN_BASEADR<4>;
|
|
|
|
MACROCELL | 15 | 12 | $OpTx$FX_DC$43
|
|
ATTRIBUTES | 133888 | 0
|
|
OUTPUTMC | 2 | 14 | 13 | 14 | 14
|
|
INPUTS | 2 | A<21> | LAN_BASEADR<5>
|
|
INPUTMC | 1 | 14 | 17
|
|
INPUTP | 1 | 163
|
|
EQ | 2 |
|
|
$OpTx$FX_DC$43 = A<21>
|
|
$ LAN_BASEADR<5>;
|
|
|
|
MACROCELL | 15 | 10 | $OpTx$FX_DC$45
|
|
ATTRIBUTES | 133888 | 0
|
|
OUTPUTMC | 2 | 14 | 13 | 14 | 14
|
|
INPUTS | 2 | A<23> | LAN_BASEADR<7>
|
|
INPUTMC | 1 | 14 | 15
|
|
INPUTP | 1 | 161
|
|
EQ | 2 |
|
|
$OpTx$FX_DC$45 = A<23>
|
|
$ LAN_BASEADR<7>;
|
|
|
|
MACROCELL | 5 | 11 | $OpTx$FX_DC$30
|
|
ATTRIBUTES | 133888 | 0
|
|
OUTPUTMC | 3 | 7 | 9 | 7 | 4 | 12 | 13
|
|
INPUTS | 2 | AS | SET_FREQUENCY
|
|
INPUTMC | 1 | 11 | 0
|
|
INPUTP | 1 | 152
|
|
EQ | 1 |
|
|
$OpTx$FX_DC$30 = !AS & !SET_FREQUENCY;
|
|
|
|
MACROCELL | 5 | 10 | $OpTx$FX_SC$321
|
|
ATTRIBUTES | 133888 | 0
|
|
OUTPUTMC | 8 | 7 | 17 | 7 | 16 | 7 | 12 | 7 | 11 | 11 | 16 | 6 | 17 | 11 | 15 | 11 | 14
|
|
INPUTS | 4 | CP_CS | lan_adr | ide | SET_FREQUENCY
|
|
INPUTMC | 4 | 4 | 1 | 14 | 13 | 10 | 17 | 11 | 0
|
|
EQ | 1 |
|
|
$OpTx$FX_SC$321 = CP_CS & lan_adr & ide & !SET_FREQUENCY;
|
|
|
|
MACROCELL | 11 | 16 | BUF_D_IN<12>
|
|
ATTRIBUTES | 133888 | 0
|
|
OUTPUTMC | 2 | 11 | 3 | 11 | 17
|
|
INPUTS | 5 | $OpTx$FX_SC$321 | SET_FREQUENCY | D<4>.PIN | D_OUT_and0001/D_OUT_and0001_D2 | D<12>.PIN
|
|
INPUTMC | 3 | 5 | 10 | 11 | 0 | 15 | 5
|
|
INPUTP | 2 | 38 | 78
|
|
EQ | 5 |
|
|
BUF_D_IN<12> = $OpTx$FX_SC$321
|
|
# D<12>.PIN & !SET_FREQUENCY &
|
|
!D_OUT_and0001/D_OUT_and0001_D2
|
|
# !SET_FREQUENCY & D<4>.PIN &
|
|
D_OUT_and0001/D_OUT_and0001_D2;
|
|
|
|
MACROCELL | 6 | 17 | BUF_D_IN<13>
|
|
ATTRIBUTES | 133888 | 0
|
|
OUTPUTMC | 2 | 6 | 15 | 6 | 16
|
|
INPUTS | 5 | $OpTx$FX_SC$321 | SET_FREQUENCY | D<5>.PIN | D_OUT_and0001/D_OUT_and0001_D2 | D<13>.PIN
|
|
INPUTMC | 3 | 5 | 10 | 11 | 0 | 15 | 5
|
|
INPUTP | 2 | 37 | 80
|
|
EQ | 5 |
|
|
BUF_D_IN<13> = $OpTx$FX_SC$321
|
|
# D<13>.PIN & !SET_FREQUENCY &
|
|
!D_OUT_and0001/D_OUT_and0001_D2
|
|
# !SET_FREQUENCY & D<5>.PIN &
|
|
D_OUT_and0001/D_OUT_and0001_D2;
|
|
|
|
MACROCELL | 11 | 15 | BUF_D_IN<14>
|
|
ATTRIBUTES | 133888 | 0
|
|
OUTPUTMC | 2 | 11 | 2 | 11 | 13
|
|
INPUTS | 5 | $OpTx$FX_SC$321 | SET_FREQUENCY | D<6>.PIN | D_OUT_and0001/D_OUT_and0001_D2 | D<14>.PIN
|
|
INPUTMC | 3 | 5 | 10 | 11 | 0 | 15 | 5
|
|
INPUTP | 2 | 26 | 81
|
|
EQ | 5 |
|
|
BUF_D_IN<14> = $OpTx$FX_SC$321
|
|
# D<14>.PIN & !SET_FREQUENCY &
|
|
!D_OUT_and0001/D_OUT_and0001_D2
|
|
# !SET_FREQUENCY & D<6>.PIN &
|
|
D_OUT_and0001/D_OUT_and0001_D2;
|
|
|
|
MACROCELL | 11 | 14 | BUF_D_IN<15>
|
|
ATTRIBUTES | 133888 | 0
|
|
OUTPUTMC | 2 | 11 | 1 | 11 | 12
|
|
INPUTS | 5 | $OpTx$FX_SC$321 | SET_FREQUENCY | D<7>.PIN | D_OUT_and0001/D_OUT_and0001_D2 | D<15>.PIN
|
|
INPUTMC | 3 | 5 | 10 | 11 | 0 | 15 | 5
|
|
INPUTP | 2 | 29 | 89
|
|
EQ | 5 |
|
|
BUF_D_IN<15> = $OpTx$FX_SC$321
|
|
# D<15>.PIN & !SET_FREQUENCY &
|
|
!D_OUT_and0001/D_OUT_and0001_D2
|
|
# !SET_FREQUENCY & D<7>.PIN &
|
|
D_OUT_and0001/D_OUT_and0001_D2;
|
|
|
|
MACROCELL | 5 | 15 | $OpTx$FX_SC$52
|
|
ATTRIBUTES | 133888 | 0
|
|
OUTPUTMC | 4 | 11 | 17 | 6 | 16 | 11 | 13 | 11 | 12
|
|
INPUTS | 4 | CP_CS | D_OUT_and0001/D_OUT_and0001_D2 | lan_adr | ide
|
|
INPUTMC | 4 | 4 | 1 | 15 | 5 | 14 | 13 | 10 | 17
|
|
EQ | 2 |
|
|
$OpTx$FX_SC$52 = !CP_CS & !D_OUT_and0001/D_OUT_and0001_D2
|
|
# lan_adr & ide & !D_OUT_and0001/D_OUT_and0001_D2;
|
|
|
|
MACROCELL | 2 | 0 | EXP22_
|
|
ATTRIBUTES | 2048 | 0
|
|
OUTPUTMC | 1 | 2 | 17
|
|
INPUTS | 6 | A<15> | RW | D<14>.PIN | lan_adr | LAN_IRQ_D0 | UDS
|
|
INPUTMC | 2 | 14 | 13 | 2 | 9
|
|
INPUTP | 4 | 139 | 158 | 81 | 155
|
|
EXPORTS | 1 | 2 | 17
|
|
EQ | 2 |
|
|
EXP22_.EXP = A<15> & !RW & D<14>.PIN & !lan_adr & !LAN_IRQ_D0 &
|
|
!UDS
|
|
|
|
MACROCELL | 4 | 0 | EXP23_
|
|
ATTRIBUTES | 2048 | 0
|
|
OUTPUTMC | 1 | 4 | 1
|
|
INPUTS | 6 | CP_BASEADR<0> | A<16> | CP_BASEADR<1> | A<17> | CP_BASEADR<2> | A<18>
|
|
INPUTMC | 3 | 2 | 16 | 2 | 15 | 12 | 17
|
|
INPUTP | 3 | 175 | 172 | 171
|
|
EXPORTS | 1 | 4 | 1
|
|
EQ | 5 |
|
|
EXP23_.EXP = CP_BASEADR<0> & !A<16>
|
|
# !CP_BASEADR<0> & A<16>
|
|
# CP_BASEADR<1> & !A<17>
|
|
# !CP_BASEADR<1> & A<17>
|
|
# !CP_BASEADR<2> & A<18>
|
|
|
|
MACROCELL | 4 | 2 | EXP24_
|
|
ATTRIBUTES | 2048 | 0
|
|
OUTPUTMC | 1 | 4 | 1
|
|
INPUTS | 7 | CP_BASEADR<2> | A<18> | CP_BASEADR<3> | A<19> | CP_BASEADR<4> | A<20> | EXP25_.EXP
|
|
INPUTMC | 4 | 12 | 17 | 12 | 16 | 12 | 15 | 4 | 3
|
|
INPUTP | 3 | 171 | 169 | 167
|
|
EXPORTS | 1 | 4 | 1
|
|
IMPORTS | 1 | 4 | 3
|
|
EQ | 10 |
|
|
EXP24_.EXP = CP_BASEADR<2> & !A<18>
|
|
# CP_BASEADR<3> & !A<19>
|
|
# !CP_BASEADR<3> & A<19>
|
|
# CP_BASEADR<4> & !A<20>
|
|
# !CP_BASEADR<4> & A<20>
|
|
;Imported pterms FB5_4
|
|
# CP_BASEADR<5> & !A<21>
|
|
# !CP_BASEADR<5> & A<21>
|
|
# CP_BASEADR<7> & !A<23>
|
|
# !CP_BASEADR<7> & A<23>
|
|
|
|
MACROCELL | 4 | 3 | EXP25_
|
|
ATTRIBUTES | 2048 | 0
|
|
OUTPUTMC | 1 | 4 | 2
|
|
INPUTS | 4 | CP_BASEADR<5> | A<21> | CP_BASEADR<7> | A<23>
|
|
INPUTMC | 2 | 12 | 14 | 12 | 12
|
|
INPUTP | 2 | 163 | 161
|
|
EXPORTS | 1 | 4 | 2
|
|
EQ | 4 |
|
|
EXP25_.EXP = CP_BASEADR<5> & !A<21>
|
|
# !CP_BASEADR<5> & A<21>
|
|
# CP_BASEADR<7> & !A<23>
|
|
# !CP_BASEADR<7> & A<23>
|
|
|
|
MACROCELL | 8 | 0 | EXP26_
|
|
ATTRIBUTES | 2048 | 0
|
|
OUTPUTMC | 1 | 8 | 17
|
|
INPUTS | 7 | A<5> | A<4> | A<2> | A<6> | A<3> | AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2 | A<1>
|
|
INPUTMC | 1 | 0 | 2
|
|
INPUTP | 6 | 91 | 97 | 101 | 98 | 99 | 107
|
|
EXPORTS | 1 | 8 | 17
|
|
EQ | 6 |
|
|
EXP26_.EXP = !A<5> & !A<4> & !A<2> & A<6> & !A<3> &
|
|
AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2
|
|
# A<5> & !A<4> & A<2> & !A<1> & !A<6> & !A<3> &
|
|
AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2
|
|
# !A<5> & A<4> & !A<2> & !A<1> & !A<6> & A<3> &
|
|
AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2
|
|
|
|
MACROCELL | 10 | 0 | EXP27_
|
|
ATTRIBUTES | 2048 | 0
|
|
OUTPUTMC | 1 | 10 | 17
|
|
INPUTS | 7 | IDE_BASEADR<2> | A<18> | IDE_BASEADR<3> | A<19> | IDE_BASEADR<5> | A<21> | EXP28_.EXP
|
|
INPUTMC | 4 | 12 | 11 | 12 | 10 | 12 | 8 | 10 | 1
|
|
INPUTP | 3 | 171 | 169 | 163
|
|
EXPORTS | 1 | 10 | 17
|
|
IMPORTS | 1 | 10 | 1
|
|
EQ | 10 |
|
|
EXP27_.EXP = IDE_BASEADR<2> & !A<18>
|
|
# IDE_BASEADR<3> & !A<19>
|
|
# !IDE_BASEADR<3> & A<19>
|
|
# IDE_BASEADR<5> & !A<21>
|
|
# !IDE_BASEADR<5> & A<21>
|
|
;Imported pterms FB11_2
|
|
# IDE_BASEADR<4> & !A<20>
|
|
# !IDE_BASEADR<4> & A<20>
|
|
# IDE_BASEADR<7> & !A<23>
|
|
# !IDE_BASEADR<7> & A<23>
|
|
|
|
MACROCELL | 10 | 1 | EXP28_
|
|
ATTRIBUTES | 2048 | 0
|
|
OUTPUTMC | 1 | 10 | 0
|
|
INPUTS | 4 | IDE_BASEADR<4> | A<20> | IDE_BASEADR<7> | A<23>
|
|
INPUTMC | 2 | 12 | 9 | 12 | 7
|
|
INPUTP | 2 | 167 | 161
|
|
EXPORTS | 1 | 10 | 0
|
|
EQ | 4 |
|
|
EXP28_.EXP = IDE_BASEADR<4> & !A<20>
|
|
# !IDE_BASEADR<4> & A<20>
|
|
# IDE_BASEADR<7> & !A<23>
|
|
# !IDE_BASEADR<7> & A<23>
|
|
|
|
MACROCELL | 13 | 1 | EXP29_
|
|
ATTRIBUTES | 2048 | 0
|
|
OUTPUTMC | 1 | 13 | 0
|
|
INPUTS | 9 | A<5> | A<4> | A<2> | A<1> | A<6> | AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2 | A<3> | AUTO_CONFIG_DONE<1> | AUTO_CONFIG_DONE<0>
|
|
INPUTMC | 3 | 0 | 2 | 13 | 8 | 13 | 7
|
|
INPUTP | 6 | 91 | 97 | 101 | 107 | 98 | 99
|
|
EXPORTS | 1 | 13 | 0
|
|
EQ | 11 |
|
|
EXP29_.EXP = A<5> & !A<4> & A<2> & A<1> & !A<6> &
|
|
AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2
|
|
# A<5> & !A<4> & A<2> & !A<6> & !A<3> &
|
|
AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2
|
|
# !A<5> & A<4> & !A<2> & !A<6> & A<3> &
|
|
AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2
|
|
# !A<5> & A<4> & A<1> & !A<6> & A<3> &
|
|
AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2
|
|
# AUTO_CONFIG_DONE<1> & AUTO_CONFIG_DONE<0> & !A<4> &
|
|
A<2> & !A<6> & !A<3> &
|
|
AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2
|
|
|
|
MACROCELL | 13 | 16 | EXP30_
|
|
ATTRIBUTES | 2048 | 0
|
|
OUTPUTMC | 1 | 13 | 15
|
|
INPUTS | 9 | AUTO_CONFIG_DONE<1> | A<5> | A<4> | A<2> | A<1> | A<6> | AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2 | A<3> | AUTO_CONFIG_DONE<0>
|
|
INPUTMC | 3 | 13 | 8 | 0 | 2 | 13 | 7
|
|
INPUTP | 6 | 91 | 97 | 101 | 107 | 98 | 99
|
|
EXPORTS | 1 | 13 | 15
|
|
EQ | 9 |
|
|
EXP30_.EXP = !AUTO_CONFIG_DONE<1> & !A<5> & A<4> & A<2> &
|
|
!A<1> & !A<6> &
|
|
AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2
|
|
# !AUTO_CONFIG_DONE<1> & !A<5> & !A<4> & A<1> &
|
|
!A<6> & !A<3> &
|
|
AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2
|
|
# AUTO_CONFIG_DONE<0> & !A<5> & !A<4> & A<1> &
|
|
!A<6> & !A<3> &
|
|
AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2
|
|
|
|
MACROCELL | 13 | 17 | EXP31_
|
|
ATTRIBUTES | 2048 | 0
|
|
OUTPUTMC | 1 | 13 | 0
|
|
INPUTS | 7 | AUTO_CONFIG_DONE<1> | A<5> | A<2> | A<1> | A<6> | A<3> | AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2
|
|
INPUTMC | 2 | 13 | 8 | 0 | 2
|
|
INPUTP | 5 | 91 | 101 | 107 | 98 | 99
|
|
EXPORTS | 1 | 13 | 0
|
|
EQ | 3 |
|
|
EXP31_.EXP = AUTO_CONFIG_DONE<1> & !A<5> & A<2> & !A<1> &
|
|
!A<6> & !A<3> &
|
|
AUTO_CONFIG_DONE_CYCLE_0_N2/AUTO_CONFIG_DONE_CYCLE_0_N2_D2
|
|
|
|
PIN | CLK_EXT | 4096 | 0 | N/A | 57 | 58 | 14 | 12 | 15 | 8 | 14 | 9 | 15 | 7 | 14 | 8 | 11 | 8 | 14 | 10 | 11 | 6 | 11 | 5 | 11 | 0 | 11 | 10 | 6 | 14 | 3 | 1 | 4 | 13 | 4 | 14 | 1 | 14 | 4 | 9 | 1 | 11 | 0 | 5 | 0 | 4 | 1 | 9 | 1 | 13 | 1 | 16 | 4 | 11 | 4 | 16 | 6 | 2 | 6 | 4 | 6 | 11 | 3 | 5 | 5 | 5 | 5 | 7 | 5 | 2 | 5 | 4 | 3 | 4 | 3 | 11 | 3 | 7 | 1 | 1 | 3 | 13 | 1 | 4 | 1 | 2 | 5 | 9 | 5 | 13 | 5 | 16 | 7 | 17 | 7 | 16 | 11 | 3 | 6 | 15 | 11 | 2 | 11 | 1 | 7 | 15 | 7 | 14 | 7 | 13 | 11 | 17 | 6 | 16 | 11 | 13 | 11 | 12 | 7 | 12 | 7 | 11
|
|
PIN | RW | 64 | 0 | N/A | 158 | 36 | 3 | 1 | 4 | 13 | 4 | 14 | 1 | 14 | 4 | 9 | 1 | 11 | 0 | 5 | 0 | 4 | 1 | 9 | 1 | 13 | 1 | 16 | 4 | 11 | 4 | 16 | 6 | 2 | 6 | 4 | 6 | 11 | 9 | 17 | 13 | 5 | 13 | 6 | 2 | 16 | 0 | 17 | 9 | 14 | 9 | 15 | 0 | 15 | 0 | 12 | 0 | 10 | 9 | 12 | 9 | 8 | 0 | 8 | 0 | 3 | 8 | 11 | 3 | 17 | 8 | 10 | 9 | 6 | 5 | 17 | 2 | 0
|
|
PIN | AS | 64 | 0 | N/A | 152 | 15 | 13 | 8 | 13 | 7 | 0 | 17 | 9 | 15 | 0 | 6 | 12 | 1 | 10 | 15 | 0 | 16 | 2 | 1 | 4 | 4 | 13 | 13 | 0 | 2 | 9 | 6 | 5 | 17 | 5 | 11
|
|
PIN | RESET | 64 | 0 | N/A | 263 | 66 | 13 | 8 | 13 | 7 | 9 | 17 | 13 | 5 | 13 | 6 | 2 | 16 | 2 | 15 | 12 | 17 | 12 | 16 | 12 | 15 | 12 | 14 | 2 | 14 | 12 | 12 | 13 | 0 | 13 | 15 | 13 | 3 | 8 | 17 | 2 | 12 | 2 | 11 | 12 | 11 | 12 | 10 | 12 | 9 | 12 | 8 | 2 | 10 | 12 | 7 | 8 | 16 | 8 | 15 | 8 | 14 | 8 | 13 | 8 | 12 | 14 | 17 | 14 | 16 | 14 | 15 | 2 | 17 | 4 | 1 | 10 | 12 | 14 | 13 | 10 | 17 | 14 | 12 | 0 | 17 | 9 | 14 | 2 | 9 | 14 | 14 | 15 | 8 | 14 | 9 | 15 | 7 | 14 | 8 | 10 | 14 | 2 | 8 | 12 | 6 | 9 | 15 | 10 | 15 | 0 | 15 | 0 | 12 | 0 | 10 | 9 | 12 | 9 | 8 | 0 | 8 | 11 | 8 | 14 | 10 | 11 | 6 | 11 | 5 | 11 | 0 | 11 | 10 | 6 | 14 | 0 | 6
|
|
PIN | A<15> | 64 | 0 | N/A | 139 | 7 | 9 | 17 | 2 | 16 | 0 | 10 | 9 | 12 | 9 | 8 | 0 | 3 | 2 | 0
|
|
PIN | LDS | 64 | 0 | N/A | 157 | 4 | 9 | 17 | 2 | 16 | 9 | 12 | 9 | 3
|
|
PIN | UDS | 64 | 0 | N/A | 155 | 4 | 9 | 17 | 2 | 0 | 9 | 8 | 9 | 3
|
|
PIN | IDE_OFF | 64 | 0 | N/A | 142 | 1 | 13 | 5
|
|
PIN | A<2> | 64 | 0 | N/A | 101 | 19 | 13 | 5 | 13 | 6 | 13 | 0 | 13 | 15 | 13 | 3 | 8 | 17 | 3 | 4 | 3 | 7 | 3 | 17 | 13 | 9 | 8 | 10 | 8 | 0 | 8 | 16 | 13 | 1 | 13 | 2 | 13 | 4 | 13 | 14 | 13 | 16 | 13 | 17
|
|
PIN | A<4> | 64 | 0 | N/A | 97 | 17 | 13 | 5 | 13 | 6 | 13 | 0 | 13 | 15 | 13 | 3 | 8 | 16 | 3 | 7 | 3 | 13 | 8 | 11 | 3 | 17 | 8 | 10 | 8 | 0 | 13 | 1 | 13 | 2 | 13 | 4 | 13 | 14 | 13 | 16
|
|
PIN | A<3> | 64 | 0 | N/A | 99 | 18 | 13 | 5 | 13 | 6 | 13 | 0 | 13 | 15 | 13 | 3 | 8 | 17 | 3 | 11 | 1 | 1 | 8 | 11 | 3 | 17 | 8 | 10 | 8 | 0 | 13 | 1 | 13 | 2 | 13 | 4 | 13 | 14 | 13 | 16 | 13 | 17
|
|
PIN | A<5> | 64 | 0 | N/A | 91 | 19 | 13 | 5 | 13 | 6 | 13 | 0 | 13 | 15 | 13 | 3 | 8 | 17 | 1 | 1 | 1 | 4 | 8 | 11 | 3 | 17 | 8 | 10 | 8 | 0 | 8 | 16 | 13 | 1 | 13 | 2 | 13 | 4 | 13 | 14 | 13 | 16 | 13 | 17
|
|
PIN | A<1> | 64 | 0 | N/A | 107 | 18 | 13 | 5 | 13 | 6 | 13 | 0 | 13 | 14 | 13 | 3 | 8 | 17 | 3 | 5 | 3 | 11 | 8 | 11 | 3 | 17 | 8 | 10 | 8 | 0 | 8 | 16 | 13 | 1 | 13 | 2 | 13 | 4 | 13 | 16 | 13 | 17
|
|
PIN | A<6> | 64 | 0 | N/A | 98 | 19 | 13 | 5 | 13 | 6 | 13 | 0 | 13 | 15 | 13 | 3 | 8 | 17 | 3 | 13 | 1 | 2 | 8 | 11 | 3 | 17 | 8 | 10 | 8 | 0 | 8 | 16 | 13 | 1 | 13 | 2 | 13 | 4 | 13 | 14 | 13 | 16 | 13 | 17
|
|
PIN | LAN_INT | 64 | 0 | N/A | 201 | 2 | 2 | 17 | 2 | 9
|
|
PIN | A<23> | 64 | 0 | N/A | 161 | 4 | 15 | 10 | 10 | 12 | 10 | 1 | 4 | 3
|
|
PIN | A<22> | 64 | 0 | N/A | 162 | 4 | 4 | 1 | 10 | 12 | 10 | 17 | 15 | 11
|
|
PIN | A<21> | 64 | 0 | N/A | 163 | 4 | 15 | 12 | 10 | 12 | 10 | 0 | 4 | 3
|
|
PIN | A<19> | 64 | 0 | N/A | 169 | 4 | 15 | 14 | 10 | 12 | 10 | 0 | 4 | 2
|
|
PIN | A<18> | 64 | 0 | N/A | 171 | 6 | 4 | 0 | 10 | 12 | 10 | 16 | 15 | 15 | 4 | 2 | 10 | 0
|
|
PIN | A<17> | 64 | 0 | N/A | 172 | 4 | 4 | 0 | 10 | 12 | 10 | 16 | 15 | 16
|
|
PIN | A<16> | 64 | 0 | N/A | 175 | 4 | 4 | 0 | 10 | 12 | 10 | 16 | 15 | 17
|
|
PIN | A<20> | 64 | 0 | N/A | 167 | 4 | 15 | 13 | 10 | 12 | 10 | 1 | 4 | 2
|
|
PIN | CFIN | 64 | 0 | N/A | 190 | 1 | 10 | 12
|
|
PIN | A<13> | 64 | 0 | N/A | 123 | 3 | 14 | 14 | 5 | 2 | 0 | 9
|
|
PIN | A<14> | 64 | 0 | N/A | 125 | 2 | 14 | 14 | 5 | 4
|
|
PIN | A<9> | 64 | 0 | N/A | 108 | 3 | 5 | 5 | 5 | 9 | 0 | 11
|
|
PIN | A<11> | 64 | 0 | N/A | 114 | 3 | 5 | 5 | 5 | 2 | 0 | 13
|
|
PIN | A<10> | 64 | 0 | N/A | 112 | 3 | 5 | 7 | 5 | 13 | 0 | 14
|
|
PIN | A<12> | 64 | 0 | N/A | 115 | 3 | 5 | 7 | 5 | 4 | 0 | 7
|
|
PIN | A<7> | 64 | 0 | N/A | 100 | 2 | 1 | 4 | 5 | 9
|
|
PIN | A<8> | 64 | 0 | N/A | 106 | 2 | 1 | 2 | 5 | 13
|
|
PIN | C1 | 64 | 0 | N/A | 188 | 1 | 15 | 6
|
|
PIN | C3 | 64 | 0 | N/A | 187 | 1 | 15 | 6
|
|
PIN | CP_IRQ | 64 | 0 | N/A | 59 | 1 | 5 | 1
|
|
PIN | CP_CS | 536871040 | 0 | N/A | 63
|
|
PIN | A_LAN<0> | 536871040 | 0 | N/A | 7
|
|
PIN | A_LAN<10> | 536871040 | 0 | N/A | 255
|
|
PIN | A_LAN<11> | 536871040 | 0 | N/A | 256
|
|
PIN | A_LAN<12> | 536871040 | 0 | N/A | 253
|
|
PIN | A_LAN<13> | 536871040 | 0 | N/A | 254
|
|
PIN | A_LAN<1> | 536871040 | 0 | N/A | 6
|
|
PIN | A_LAN<2> | 536871040 | 0 | N/A | 12
|
|
PIN | A_LAN<3> | 536871040 | 0 | N/A | 8
|
|
PIN | A_LAN<4> | 536871040 | 0 | N/A | 20
|
|
PIN | A_LAN<5> | 536871040 | 0 | N/A | 13
|
|
PIN | A_LAN<6> | 536871040 | 0 | N/A | 22
|
|
PIN | A_LAN<7> | 536871040 | 0 | N/A | 21
|
|
PIN | A_LAN<8> | 536871040 | 0 | N/A | 258
|
|
PIN | A_LAN<9> | 536871040 | 0 | N/A | 262
|
|
PIN | LAN_RD | 536871040 | 0 | N/A | 242
|
|
PIN | CFOUT | 536871040 | 0 | N/A | 191
|
|
PIN | CP_RD | 536871040 | 0 | N/A | 132
|
|
PIN | CP_WE | 536871040 | 0 | N/A | 131
|
|
PIN | IDE_R | 536871040 | 0 | N/A | 46
|
|
PIN | IDE_W | 536871040 | 0 | N/A | 47
|
|
PIN | LAN_CS | 536871040 | 0 | N/A | 240
|
|
PIN | LAN_WRH | 536871040 | 0 | N/A | 237
|
|
PIN | LAN_WRL | 536871040 | 0 | N/A | 145
|
|
PIN | ROM_OE | 536871040 | 0 | N/A | 65
|
|
PIN | SLAVE | 536871040 | 0 | N/A | 193
|
|
PIN | INT6_OUT | 536871040 | 0 | N/A | 251
|
|
PIN | INT2_OUT | 536871040 | 0 | N/A | 60
|
|
PIN | IDE_A<0> | 536871040 | 0 | N/A | 43
|
|
PIN | IDE_A<1> | 536871040 | 0 | N/A | 45
|
|
PIN | IDE_A<2> | 536871040 | 0 | N/A | 44
|
|
PIN | IDE_CS<0> | 536871040 | 0 | N/A | 39
|
|
PIN | IDE_CS<1> | 536871040 | 0 | N/A | 41
|
|
PIN | OWN | 536871040 | 0 | N/A | 195
|
|
PIN | OVR | 536871040 | 0 | N/A | 185
|
|
PIN | MTACK | 536871040 | 0 | N/A | 174
|
|
PIN | DTACK | 536871040 | 0 | N/A | 160
|
|
PIN | ROM_B<1> | 536871040 | 0 | N/A | 129
|
|
PIN | ROM_B<0> | 536871040 | 0 | N/A | 127
|
|
PIN | D<0> | 536870976 | 0 | N/A | 4 | 2 | 5 | 16 | 7 | 12
|
|
PIN | D<10> | 536870976 | 0 | N/A | 74 | 5 | 12 | 17 | 12 | 11 | 8 | 14 | 7 | 17 | 7 | 14
|
|
PIN | D<11> | 536870976 | 0 | N/A | 77 | 5 | 12 | 16 | 12 | 10 | 8 | 13 | 7 | 16 | 7 | 13
|
|
PIN | D<1> | 536870976 | 0 | N/A | 30 | 2 | 7 | 15 | 7 | 11
|
|
PIN | D<2> | 536870976 | 0 | N/A | 71 | 2 | 7 | 17 | 7 | 14
|
|
PIN | D<3> | 536870976 | 0 | N/A | 28 | 2 | 7 | 16 | 7 | 13
|
|
PIN | D<4> | 536870976 | 0 | N/A | 38 | 2 | 11 | 17 | 11 | 16
|
|
PIN | D<5> | 536870976 | 0 | N/A | 37 | 2 | 6 | 16 | 6 | 17
|
|
PIN | D<6> | 536870976 | 0 | N/A | 26 | 2 | 11 | 13 | 11 | 15
|
|
PIN | D<7> | 536870976 | 0 | N/A | 29 | 2 | 11 | 12 | 11 | 14
|
|
PIN | D<8> | 536870976 | 0 | N/A | 32 | 5 | 2 | 16 | 2 | 12 | 8 | 16 | 5 | 16 | 7 | 12
|
|
PIN | D<9> | 536870976 | 0 | N/A | 73 | 5 | 2 | 15 | 2 | 11 | 8 | 15 | 7 | 15 | 7 | 11
|
|
PIN | D<12> | 536870976 | 0 | N/A | 78 | 5 | 12 | 15 | 12 | 9 | 8 | 12 | 11 | 17 | 11 | 16
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PIN | D<13> | 536870976 | 0 | N/A | 80 | 5 | 12 | 14 | 12 | 8 | 14 | 17 | 6 | 16 | 6 | 17
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PIN | D<14> | 536870976 | 0 | N/A | 81 | 7 | 2 | 14 | 2 | 10 | 14 | 16 | 2 | 16 | 11 | 13 | 11 | 15 | 2 | 0
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PIN | D<15> | 536870976 | 0 | N/A | 89 | 6 | 9 | 17 | 12 | 12 | 12 | 7 | 14 | 15 | 11 | 12 | 11 | 14
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PIN | DQ<0> | 536870976 | 0 | N/A | 217 | 2 | 3 | 1 | 1 | 16
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PIN | DQ<10> | 536870976 | 0 | N/A | 234 | 2 | 4 | 13 | 4 | 9
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PIN | DQ<11> | 536870976 | 0 | N/A | 207 | 2 | 4 | 14 | 1 | 11
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PIN | DQ<12> | 536870976 | 0 | N/A | 235 | 2 | 0 | 5 | 4 | 16
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PIN | DQ<13> | 536870976 | 0 | N/A | 204 | 2 | 0 | 4 | 6 | 2
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PIN | DQ<14> | 536870976 | 0 | N/A | 236 | 2 | 1 | 9 | 6 | 4
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PIN | DQ<15> | 536870976 | 0 | N/A | 202 | 2 | 1 | 13 | 6 | 11
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PIN | DQ<1> | 536870976 | 0 | N/A | 216 | 2 | 1 | 14 | 4 | 11
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PIN | DQ<2> | 536870976 | 0 | N/A | 220 | 2 | 4 | 13 | 4 | 9
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PIN | DQ<3> | 536870976 | 0 | N/A | 219 | 2 | 4 | 14 | 1 | 11
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PIN | DQ<4> | 536870976 | 0 | N/A | 225 | 2 | 0 | 5 | 4 | 16
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PIN | DQ<5> | 536870976 | 0 | N/A | 221 | 2 | 0 | 4 | 6 | 2
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PIN | DQ<6> | 536870976 | 0 | N/A | 227 | 2 | 1 | 9 | 6 | 4
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PIN | DQ<7> | 536870976 | 0 | N/A | 226 | 2 | 1 | 13 | 6 | 11
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PIN | DQ<8> | 536870976 | 0 | N/A | 231 | 2 | 3 | 1 | 1 | 16
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PIN | DQ<9> | 536870976 | 0 | N/A | 209 | 2 | 1 | 14 | 4 | 11
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