461 lines
12 KiB
VHDL
461 lines
12 KiB
VHDL
--------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date: 23:59:54 01/15/2017
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-- Design Name:
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-- Module Name: C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP_TB.vhd
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-- Project Name: LAN_IDE
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-- Target Device:
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-- Tool versions:
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-- Description:
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--
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-- VHDL Test Bench Created by ISE for module: LAN_IDE_CP
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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-- Notes:
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-- This testbench has been automatically generated using types std_logic and
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-- std_logic_vector for the ports of the unit under test. Xilinx recommends
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-- that these types always be used for the top-level I/O of a design in order
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-- to guarantee that the testbench will bind correctly to the post-implementation
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-- simulation model.
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--------------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--USE ieee.numeric_std.ALL;
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ENTITY LAN_IDE_CP_TB IS
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END LAN_IDE_CP_TB;
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ARCHITECTURE behavior OF LAN_IDE_CP_TB IS
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-- Component Declaration for the Unit Under Test (UUT)
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COMPONENT LAN_IDE_CP
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PORT(
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A : INOUT std_logic_vector(23 downto 1);
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D : INOUT std_logic_vector(15 downto 0);
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DQ : INOUT std_logic_vector(15 downto 0);
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A_LAN : OUT std_logic_vector(13 downto 0);
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OWN : OUT std_logic;
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SLAVE : OUT std_logic;
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CFOUT : OUT std_logic;
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CFIN : IN std_logic;
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C1 : IN std_logic;
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C3 : IN std_logic;
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MTCR : IN std_logic;
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OVR : OUT std_logic;
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BERR : IN std_logic;
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MTACK : OUT std_logic;
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DS0 : IN std_logic;
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DTACK : OUT std_logic;
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UDS : IN std_logic;
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LDS : IN std_logic;
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AS : IN std_logic;
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RW : IN std_logic;
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Z3 : IN std_logic;
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DS1 : IN std_logic;
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FCS : IN std_logic;
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RESET : IN std_logic;
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INT_OUT : OUT std_logic;
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AUTOBOOT_OFF : IN std_logic;
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ROM_B : OUT std_logic_vector(1 downto 0);
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ROM_OE : OUT std_logic;
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IDE_WAIT : IN std_logic;
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CLK_EXT : IN std_logic;
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IDE_W : OUT std_logic;
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IDE_R : OUT std_logic;
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IDE_A : OUT std_logic_vector(2 downto 0);
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IDE_CS : OUT std_logic_vector(1 downto 0);
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LAN_CFG : OUT std_logic_vector(4 downto 1);
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LAN_RD : OUT std_logic;
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LAN_CS : OUT std_logic;
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LAN_WRH : OUT std_logic;
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LAN_WRL : OUT std_logic;
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LAN_INT : IN std_logic;
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CP_RD : OUT std_logic;
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CP_WE : OUT std_logic;
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CP_CS : OUT std_logic;
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CP_IRQ : IN std_logic
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);
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END COMPONENT;
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--Inputs
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signal CFIN : std_logic := '0';
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signal C1 : std_logic := '0';
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signal C3 : std_logic := '0';
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signal MTCR : std_logic := '0';
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signal BERR : std_logic := '0';
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signal DS0 : std_logic := '0';
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signal UDS : std_logic := '0';
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signal LDS : std_logic := '0';
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signal AS : std_logic := '0';
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signal RW : std_logic := '0';
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signal Z3 : std_logic := '0';
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signal DS1 : std_logic := '0';
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signal FCS : std_logic := '0';
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signal RESET : std_logic := '0';
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signal AUTOBOOT_OFF : std_logic := '0';
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signal IDE_WAIT : std_logic := '0';
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signal CLK_EXT : std_logic := '0';
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signal LAN_INT : std_logic := '0';
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signal CP_IRQ : std_logic := '0';
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--BiDirs
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signal A : std_logic_vector(23 downto 1);
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signal D : std_logic_vector(15 downto 0);
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signal DQ : std_logic_vector(15 downto 0);
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--Outputs
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signal A_LAN : std_logic_vector(13 downto 0);
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signal OWN : std_logic;
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signal SLAVE : std_logic;
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signal CFOUT : std_logic;
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signal OVR : std_logic;
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signal MTACK : std_logic;
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signal DTACK : std_logic;
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signal INT_OUT : std_logic;
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signal ROM_B : std_logic_vector(1 downto 0);
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signal ROM_OE : std_logic;
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signal IDE_W : std_logic;
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signal IDE_R : std_logic;
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signal IDE_A : std_logic_vector(2 downto 0);
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signal IDE_CS : std_logic_vector(1 downto 0);
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signal LAN_CFG : std_logic_vector(4 downto 1);
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signal LAN_RD : std_logic;
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signal LAN_CS : std_logic;
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signal LAN_WRH : std_logic;
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signal LAN_WRL : std_logic;
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signal CP_RD : std_logic;
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signal CP_WE : std_logic;
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signal CP_CS : std_logic;
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-- Clock period definitions
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signal AMIGA_CLK :std_logic;
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constant CLK_EXT_period : time := 40 ns;
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constant CLK_AMIGA_period : time := 140 ns;
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BEGIN
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-- Instantiate the Unit Under Test (UUT)
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uut: LAN_IDE_CP PORT MAP (
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A => A,
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D => D,
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DQ => DQ,
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A_LAN => A_LAN,
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OWN => OWN,
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SLAVE => SLAVE,
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CFOUT => CFOUT,
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CFIN => CFIN,
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C1 => C1,
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C3 => C3,
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MTCR => MTCR,
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OVR => OVR,
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BERR => BERR,
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MTACK => MTACK,
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DS0 => DS0,
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DTACK => DTACK,
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UDS => UDS,
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LDS => LDS,
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AS => AS,
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RW => RW,
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Z3 => Z3,
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DS1 => DS1,
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FCS => FCS,
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RESET => RESET,
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INT_OUT => INT_OUT,
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AUTOBOOT_OFF => AUTOBOOT_OFF,
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ROM_B => ROM_B,
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ROM_OE => ROM_OE,
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IDE_WAIT => IDE_WAIT,
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CLK_EXT => CLK_EXT,
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IDE_W => IDE_W,
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IDE_R => IDE_R,
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IDE_A => IDE_A,
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IDE_CS => IDE_CS,
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LAN_CFG => LAN_CFG,
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LAN_RD => LAN_RD,
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LAN_CS => LAN_CS,
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LAN_WRH => LAN_WRH,
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LAN_WRL => LAN_WRL,
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LAN_INT => LAN_INT,
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CP_RD => CP_RD,
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CP_WE => CP_WE,
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CP_CS => CP_CS,
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CP_IRQ => CP_IRQ
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);
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AMIGA_CLK <= not (C1 xor C3);
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-- Clock process definitions
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CLK_EXT_process :process
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begin
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CLK_EXT <= '0';
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wait for CLK_EXT_period/2;
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CLK_EXT <= '1';
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wait for CLK_EXT_period/2;
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end process;
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-- Clock process definitions
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CLK_13_process :process
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begin
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C1 <= '1';
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C3 <= '0';
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wait for CLK_AMIGA_period/2;
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C1 <= '0';
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C3 <= '0';
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wait for CLK_AMIGA_period/2;
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C1 <= '0';
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C3 <= '1';
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wait for CLK_AMIGA_period/2;
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C1 <= '1';
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C3 <= '1';
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wait for CLK_AMIGA_period/2;
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end process;
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-- Stimulus process
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stim_proc: process
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begin
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-- hold reset state for 100 ns.
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RESET <='0';
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AS <='1';
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BERR <='1';
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D <= (others=>'Z');
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DQ <= (others=>'Z');
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A <= (others=>'Z');
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RW <='1';
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UDS <='1';
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LDS <='1';
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CFIN <='0';
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MTCR <='1';
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DS0 <='1';
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Z3 <='0';
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DS1 <='1';
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FCS <='1';
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AUTOBOOT_OFF <='1';
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IDE_WAIT <='1';
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LAN_INT <='1';
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CP_IRQ <='1';
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wait for 100 ns;
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reset <='1';
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wait for CLK_AMIGA_period*10;
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--make a quick autoconfig
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wait until rising_edge(AMIGA_CLK); --S0
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RW <='1';
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wait until falling_edge(AMIGA_CLK); --S1
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A(23 downto 16) <= x"E8";
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A(15 downto 8) <= x"00";
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A(7 downto 1) <= "0100100";
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wait until rising_edge(AMIGA_CLK); --S2
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AS<='0';
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RW<='0';
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wait until falling_edge(AMIGA_CLK); --S3
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D <= x"EAEA"; --address config 1
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wait until rising_edge(AMIGA_CLK); --S4
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UDS <='0';
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wait until falling_edge(AMIGA_CLK); --S5
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wait until rising_edge(AMIGA_CLK); --S6
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wait until falling_edge(AMIGA_CLK); --S7
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AS <='1';
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UDS <='1';
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LDS <='1';
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D <= (others=>'Z');
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wait until rising_edge(AMIGA_CLK); --S0
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RW <='1';
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wait until falling_edge(AMIGA_CLK); --S1
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A(23 downto 16) <= x"E8";
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A(15 downto 8) <= x"00";
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A(7 downto 1) <= "0100100";
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wait until rising_edge(AMIGA_CLK); --S2
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AS<='0';
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RW<='0';
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wait until falling_edge(AMIGA_CLK); --S3
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D <= x"EBEB"; --address config 2
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wait until rising_edge(AMIGA_CLK); --S4
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UDS <='0';
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wait until falling_edge(AMIGA_CLK); --S5
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wait until rising_edge(AMIGA_CLK); --S6
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wait until falling_edge(AMIGA_CLK); --S7
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AS <='1';
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UDS <='1';
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LDS <='1';
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D <= (others=>'Z');
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wait until rising_edge(AMIGA_CLK); --S0
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RW <='1';
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wait until falling_edge(AMIGA_CLK); --S1
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A(23 downto 16) <= x"E8";
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A(15 downto 8) <= x"00";
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A(7 downto 1) <= "0100100";
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wait until rising_edge(AMIGA_CLK); --S2
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AS<='0';
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RW<='0';
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wait until falling_edge(AMIGA_CLK); --S3
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D <= x"ECEC"; --address config 3
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wait until rising_edge(AMIGA_CLK); --S4
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UDS <='0';
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wait until falling_edge(AMIGA_CLK); --S5
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wait until rising_edge(AMIGA_CLK); --S6
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wait until falling_edge(AMIGA_CLK); --S7
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AS <='1';
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UDS <='1';
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LDS <='1';
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D <= (others=>'Z');
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--now do some I/O on LAN
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wait until rising_edge(AMIGA_CLK); --S0
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RW <='1';
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wait until falling_edge(AMIGA_CLK); --S1
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A(23 downto 16) <= x"EA";
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A(15 downto 8) <= x"00";
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A(7 downto 1) <= "0100100";
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wait until rising_edge(AMIGA_CLK); --S2
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AS<='0';
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RW<='0';
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wait until falling_edge(AMIGA_CLK); --S3
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D <= x"B00B"; --Testdata
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wait until rising_edge(AMIGA_CLK); --S4
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UDS <='0';
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LDS <='0';
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wait until falling_edge(AMIGA_CLK); --S5
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wait until rising_edge(AMIGA_CLK); --S6
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wait until falling_edge(AMIGA_CLK); --S7
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AS <='1';
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UDS <='1';
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LDS <='1';
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D <= (others=>'Z');
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wait until rising_edge(AMIGA_CLK); --S0
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RW <='1';
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wait until falling_edge(AMIGA_CLK); --S1
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A(23 downto 16) <= x"EA";
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A(15 downto 8) <= x"00";
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A(7 downto 1) <= "0100100";
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wait until rising_edge(AMIGA_CLK); --S2
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AS<='0';
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RW<='1';
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UDS <='0';
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LDS <='0';
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wait until falling_edge(AMIGA_CLK); --S3
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wait until rising_edge(AMIGA_CLK); --S4
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wait until falling_edge(AMIGA_CLK); --S5
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wait until rising_edge(AMIGA_CLK); --S6
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wait until falling_edge(AMIGA_CLK); --S7
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AS <='1';
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UDS <='1';
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LDS <='1';
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D <= (others=>'Z');
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--now do some I/O on CS
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wait until rising_edge(AMIGA_CLK); --S0
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RW <='1';
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wait until falling_edge(AMIGA_CLK); --S1
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A(23 downto 16) <= x"EB";
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A(15 downto 8) <= x"00";
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A(7 downto 1) <= "0100100";
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wait until rising_edge(AMIGA_CLK); --S2
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AS<='0';
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RW<='0';
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wait until falling_edge(AMIGA_CLK); --S3
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D <= x"B00B"; --Testdata
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wait until rising_edge(AMIGA_CLK); --S4
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UDS <='0';
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LDS <='0';
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wait until falling_edge(AMIGA_CLK); --S5
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wait until rising_edge(AMIGA_CLK); --S6
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wait until falling_edge(AMIGA_CLK); --S7
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AS <='1';
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UDS <='1';
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LDS <='1';
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D <= (others=>'Z');
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wait until rising_edge(AMIGA_CLK); --S0
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RW <='1';
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wait until falling_edge(AMIGA_CLK); --S1
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A(23 downto 16) <= x"EB";
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A(15 downto 8) <= x"00";
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A(7 downto 1) <= "0100100";
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wait until rising_edge(AMIGA_CLK); --S2
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AS<='0';
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RW<='1';
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UDS <='0';
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LDS <='0';
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wait until falling_edge(AMIGA_CLK); --S3
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wait until rising_edge(AMIGA_CLK); --S4
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wait until falling_edge(AMIGA_CLK); --S5
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wait until rising_edge(AMIGA_CLK); --S6
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wait until falling_edge(AMIGA_CLK); --S7
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AS <='1';
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UDS <='1';
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LDS <='1';
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D <= (others=>'Z');
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--now do some I/O on IDE
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wait until rising_edge(AMIGA_CLK); --S0
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RW <='1';
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wait until falling_edge(AMIGA_CLK); --S1
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A(23 downto 16) <= x"EC";
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A(15 downto 8) <= x"00";
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A(7 downto 1) <= "0100100";
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wait until rising_edge(AMIGA_CLK); --S2
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AS<='0';
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RW<='0';
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wait until falling_edge(AMIGA_CLK); --S3
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D <= x"B00B"; --Testdata
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wait until rising_edge(AMIGA_CLK); --S4
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UDS <='0';
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LDS <='0';
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wait until falling_edge(AMIGA_CLK); --S5
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wait until rising_edge(AMIGA_CLK); --S6
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wait until falling_edge(AMIGA_CLK); --S7
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AS <='1';
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UDS <='1';
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LDS <='1';
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D <= (others=>'Z');
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wait until rising_edge(AMIGA_CLK); --S0
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RW <='1';
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wait until falling_edge(AMIGA_CLK); --S1
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A(23 downto 16) <= x"EC";
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A(15 downto 8) <= x"00";
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A(7 downto 1) <= "0100100";
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wait until rising_edge(AMIGA_CLK); --S2
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AS<='0';
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RW<='1';
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UDS <='0';
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LDS <='0';
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wait until falling_edge(AMIGA_CLK); --S3
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wait until rising_edge(AMIGA_CLK); --S4
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wait until falling_edge(AMIGA_CLK); --S5
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wait until rising_edge(AMIGA_CLK); --S6
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wait until falling_edge(AMIGA_CLK); --S7
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AS <='1';
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UDS <='1';
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LDS <='1';
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D <= (others=>'Z');
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wait until rising_edge(AMIGA_CLK);
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wait until falling_edge(AMIGA_CLK);
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wait;
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end process;
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END;
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