429 lines
25 KiB
Plaintext
429 lines
25 KiB
Plaintext
Release 14.7 - xst P.20131013 (nt64)
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Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
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--> Parameter TMPDIR set to xst/projnav.tmp
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Total REAL time to Xst completion: 1.00 secs
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Total CPU time to Xst completion: 0.14 secs
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--> Parameter xsthdpdir set to xst
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Total REAL time to Xst completion: 1.00 secs
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Total CPU time to Xst completion: 0.14 secs
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--> Reading design: LAN_IDE_CP.prj
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TABLE OF CONTENTS
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1) Synthesis Options Summary
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2) HDL Compilation
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3) Design Hierarchy Analysis
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4) HDL Analysis
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5) HDL Synthesis
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5.1) HDL Synthesis Report
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6) Advanced HDL Synthesis
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6.1) Advanced HDL Synthesis Report
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7) Low Level Synthesis
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8) Partition Report
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9) Final Report
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=========================================================================
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* Synthesis Options Summary *
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=========================================================================
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---- Source Parameters
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Input File Name : "LAN_IDE_CP.prj"
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Input Format : mixed
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Ignore Synthesis Constraint File : NO
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---- Target Parameters
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Output File Name : "LAN_IDE_CP"
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Output Format : NGC
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Target Device : XC9500XL CPLDs
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---- Source Options
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Top Module Name : LAN_IDE_CP
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Automatic FSM Extraction : YES
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FSM Encoding Algorithm : Auto
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Safe Implementation : No
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Mux Extraction : Yes
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Resource Sharing : YES
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---- Target Options
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Add IO Buffers : YES
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MACRO Preserve : YES
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XOR Preserve : YES
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Equivalent register Removal : YES
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---- General Options
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Optimization Goal : Speed
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Optimization Effort : 1
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Keep Hierarchy : Yes
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Netlist Hierarchy : As_Optimized
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RTL Output : Yes
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Hierarchy Separator : /
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Bus Delimiter : <>
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Case Specifier : Maintain
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Verilog 2001 : YES
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---- Other Options
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Clock Enable : YES
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wysiwyg : NO
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=========================================================================
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=========================================================================
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* HDL Compilation *
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=========================================================================
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Compiling vhdl file "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.vhd" in Library work.
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Entity <lan_ide_cp> compiled.
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Entity <lan_ide_cp> (Architecture <behavioral>) compiled.
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=========================================================================
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* Design Hierarchy Analysis *
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=========================================================================
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Analyzing hierarchy for entity <LAN_IDE_CP> in library <work> (architecture <behavioral>).
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=========================================================================
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* HDL Analysis *
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=========================================================================
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Analyzing Entity <LAN_IDE_CP> in library <work> (Architecture <behavioral>).
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Entity <LAN_IDE_CP> analyzed. Unit <LAN_IDE_CP> generated.
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=========================================================================
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* HDL Synthesis *
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=========================================================================
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Performing bidirectional port resolution...
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INFO:Xst:2561 - Always blocking tristate driving signal <A> in unit <LAN_IDE_CP> is removed.
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INFO:Xst:2561 - Always blocking tristate driving signal <A> in unit <LAN_IDE_CP> is removed.
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INFO:Xst:2561 - Always blocking tristate driving signal <A> in unit <LAN_IDE_CP> is removed.
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INFO:Xst:2561 - Always blocking tristate driving signal <A> in unit <LAN_IDE_CP> is removed.
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INFO:Xst:2561 - Always blocking tristate driving signal <A> in unit <LAN_IDE_CP> is removed.
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INFO:Xst:2561 - Always blocking tristate driving signal <A> in unit <LAN_IDE_CP> is removed.
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INFO:Xst:2561 - Always blocking tristate driving signal <A> in unit <LAN_IDE_CP> is removed.
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Synthesizing Unit <LAN_IDE_CP>.
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Related source file is "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.vhd".
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WARNING:Xst:647 - Input <C3> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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WARNING:Xst:647 - Input <IDE_WAIT> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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WARNING:Xst:647 - Input <AS> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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WARNING:Xst:647 - Input <CP_IRQ> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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WARNING:Xst:2565 - Inout <A<1>> is never assigned.
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WARNING:Xst:647 - Input <MTCR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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WARNING:Xst:647 - Input <C1> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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INFO:Xst:1799 - State start_read_upper is never reached in FSM <LAN_SM>.
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Found finite state machine <FSM_0> for signal <LAN_SM>.
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-----------------------------------------------------------------------
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| States | 12 |
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| Transitions | 17 |
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| Inputs | 3 |
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| Outputs | 12 |
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| Clock | CLK_EXT (rising_edge) |
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| Reset | LAN_SM_RST (positive) |
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| Reset type | asynchronous |
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| Reset State | nop |
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| Power Up State | nop |
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| Encoding | automatic |
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| Implementation | automatic |
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-----------------------------------------------------------------------
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Found finite state machine <FSM_1> for signal <LAN_RST_SM>.
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-----------------------------------------------------------------------
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| States | 8 |
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| Transitions | 8 |
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| Inputs | 0 |
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| Outputs | 30 |
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| Clock | CLK_EXT (rising_edge) |
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| Reset | RESET (positive) |
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| Reset type | asynchronous |
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| Reset State | nop |
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| Power Up State | nop |
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| Encoding | automatic |
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| Implementation | automatic |
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-----------------------------------------------------------------------
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Found 16x8-bit ROM for signal <D_OUT$mux0004>.
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Found 16-bit tristate buffer for signal <D>.
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Found 16-bit tristate buffer for signal <DQ>.
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Found 1-bit tristate buffer for signal <OWN>.
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Found 1-bit tristate buffer for signal <OVR>.
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Found 1-bit tristate buffer for signal <MTACK>.
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Found 1-bit tristate buffer for signal <DTACK>.
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Found 1-bit tristate buffer for signal <INT_OUT>.
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Found 4-bit tristate buffer for signal <LAN_CFG>.
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Found 1-bit tristate buffer for signal <A<23>>.
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Found 1-bit tristate buffer for signal <A<22>>.
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Found 1-bit tristate buffer for signal <A<21>>.
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Found 1-bit tristate buffer for signal <A<20>>.
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Found 1-bit tristate buffer for signal <A<19>>.
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Found 1-bit tristate buffer for signal <A<18>>.
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Found 1-bit tristate buffer for signal <A<17>>.
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Found 1-bit tristate buffer for signal <A<16>>.
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Found 1-bit tristate buffer for signal <A<15>>.
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Found 1-bit tristate buffer for signal <A<14>>.
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Found 1-bit tristate buffer for signal <A<13>>.
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Found 1-bit tristate buffer for signal <A<12>>.
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Found 1-bit tristate buffer for signal <A<11>>.
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Found 1-bit tristate buffer for signal <A<10>>.
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Found 1-bit tristate buffer for signal <A<9>>.
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Found 1-bit tristate buffer for signal <A<8>>.
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Found 1-bit register for signal <AUTO_CONFIG_DONE>.
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Found 1-bit register for signal <AUTO_CONFIG_DONE_CYCLE>.
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Found 1-bit register for signal <AUTOCONFIG_ACCESS>.
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Found 1-bit register for signal <CONFIG_READY>.
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Found 8-bit register for signal <D_OUT>.
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Found 4-bit comparator less for signal <DQ$cmp_lt0000> created at line 533.
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Found 16-bit register for signal <DQ_DATA>.
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Found 1-bit register for signal <DQ_SWAP>.
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Found 2-bit comparator less for signal <DQ_SWAP$cmp_lt0000> created at line 249.
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Found 14-bit register for signal <LAN_A_INIT>.
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Found 1-bit register for signal <LAN_ACCESS>.
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Found 16-bit comparator equal for signal <LAN_ACCESS$cmp_eq0000> created at line 248.
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Found 16-bit register for signal <LAN_BASEADR>.
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Found 1-bit register for signal <LAN_CS_RST>.
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Found 16-bit register for signal <LAN_D_INIT>.
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Found 1-bit register for signal <LAN_INT_ENABLE>.
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Found 1-bit register for signal <LAN_IRQ_D0>.
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Found 1-bit register for signal <LAN_IRQ_OUT>.
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Found 1-bit register for signal <LAN_RD_S>.
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Found 1-bit register for signal <LAN_READY>.
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Found 2-bit comparator less for signal <LAN_SM$cmp_lt0000> created at line 367.
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Found 1-bit register for signal <LAN_SM_RST>.
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Found 1-bit register for signal <LAN_WR_RST>.
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Found 1-bit register for signal <LAN_WRH_S>.
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Found 1-bit register for signal <LAN_WRL_S>.
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Found 1-bit register for signal <SHUT_UP>.
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Found 1-bit register for signal <Z3_A_LOW>.
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Found 14-bit register for signal <Z3_ADR>.
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Found 32-bit register for signal <Z3_DATA>.
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Summary:
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inferred 2 Finite State Machine(s).
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inferred 1 ROM(s).
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inferred 49 D-type flip-flop(s).
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inferred 4 Comparator(s).
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inferred 57 Tristate(s).
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Unit <LAN_IDE_CP> synthesized.
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=========================================================================
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HDL Synthesis Report
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Macro Statistics
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# ROMs : 1
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16x8-bit ROM : 1
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# Registers : 56
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1-bit register : 50
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14-bit register : 2
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16-bit register : 3
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8-bit register : 1
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# Comparators : 4
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16-bit comparator equal : 1
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2-bit comparator less : 2
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4-bit comparator less : 1
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# Tristates : 27
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1-bit tristate buffer : 25
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16-bit tristate buffer : 2
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=========================================================================
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=========================================================================
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* Advanced HDL Synthesis *
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=========================================================================
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Analyzing FSM <FSM_1> for best encoding.
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Optimizing FSM <LAN_RST_SM/FSM> on signal <LAN_RST_SM[1:3]> with gray encoding.
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------------------------
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State | Encoding
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------------------------
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nop | 000
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wait0 | 001
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clr | 011
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clr_commit | 010
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wait1 | 110
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set | 111
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set_commit | 101
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done | 100
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------------------------
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Analyzing FSM <FSM_0> for best encoding.
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Optimizing FSM <LAN_SM/FSM> on signal <LAN_SM[1:12]> with one-hot encoding.
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-----------------------------------
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State | Encoding
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-----------------------------------
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nop | 000000000001
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start_read_upper | unreached
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wait_read_upper | 000000000010
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end_read_upper | 000000100000
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start_read_lower | 000001000000
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wait_read_lower | 000000000100
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end_read_lower | 000010000000
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start_write_upper | 000000001000
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wait_write_upper | 000100000000
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end_write_upper | 001000000000
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start_write_lower | 000000010000
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wait_write_lower | 010000000000
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end_write_lower | 100000000000
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-----------------------------------
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WARNING:Xst:1293 - FF/Latch <0> has a constant value of 1 in block <13>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1293 - FF/Latch <0> has a constant value of 1 in block <12>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1293 - FF/Latch <0> has a constant value of 1 in block <11>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1293 - FF/Latch <0> has a constant value of 1 in block <10>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1293 - FF/Latch <0> has a constant value of 1 in block <9>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1293 - FF/Latch <0> has a constant value of 1 in block <8>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1293 - FF/Latch <0> has a constant value of 1 in block <7>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1293 - FF/Latch <0> has a constant value of 1 in block <5>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1293 - FF/Latch <0> has a constant value of 1 in block <4>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1293 - FF/Latch <0> has a constant value of 1 in block <2>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1293 - FF/Latch <0> has a constant value of 1 in block <1>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1293 - FF/Latch <0> has a constant value of 1 in block <0>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <15>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <14>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <13>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <12>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <7>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <6>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <5>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <3>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <2>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <0>. This FF/Latch will be trimmed during the optimization process.
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=========================================================================
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Advanced HDL Synthesis Report
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Macro Statistics
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# FSMs : 2
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# ROMs : 1
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16x8-bit ROM : 1
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# Registers : 49
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Flip-Flops : 49
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# Comparators : 1
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16-bit comparator equal : 1
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=========================================================================
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=========================================================================
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* Low Level Synthesis *
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=========================================================================
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WARNING:Xst:1293 - FF/Latch <LAN_D_INIT_15> has a constant value of 0 in block <LAN_IDE_CP>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <LAN_D_INIT_14> has a constant value of 0 in block <LAN_IDE_CP>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <LAN_D_INIT_13> has a constant value of 0 in block <LAN_IDE_CP>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <LAN_D_INIT_12> has a constant value of 0 in block <LAN_IDE_CP>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <LAN_D_INIT_7> has a constant value of 0 in block <LAN_IDE_CP>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <LAN_D_INIT_6> has a constant value of 0 in block <LAN_IDE_CP>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <LAN_D_INIT_5> has a constant value of 0 in block <LAN_IDE_CP>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <LAN_D_INIT_3> has a constant value of 0 in block <LAN_IDE_CP>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <LAN_D_INIT_2> has a constant value of 0 in block <LAN_IDE_CP>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <LAN_D_INIT_0> has a constant value of 0 in block <LAN_IDE_CP>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <LAN_A_INIT_13> has a constant value of 1 in block <LAN_IDE_CP>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <LAN_A_INIT_12> has a constant value of 1 in block <LAN_IDE_CP>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <LAN_A_INIT_11> has a constant value of 1 in block <LAN_IDE_CP>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <LAN_A_INIT_10> has a constant value of 1 in block <LAN_IDE_CP>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <LAN_A_INIT_9> has a constant value of 1 in block <LAN_IDE_CP>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <LAN_A_INIT_8> has a constant value of 1 in block <LAN_IDE_CP>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <LAN_A_INIT_7> has a constant value of 1 in block <LAN_IDE_CP>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <LAN_A_INIT_5> has a constant value of 1 in block <LAN_IDE_CP>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <LAN_A_INIT_4> has a constant value of 1 in block <LAN_IDE_CP>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <LAN_A_INIT_2> has a constant value of 1 in block <LAN_IDE_CP>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <LAN_A_INIT_1> has a constant value of 1 in block <LAN_IDE_CP>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <LAN_A_INIT_0> has a constant value of 1 in block <LAN_IDE_CP>. This FF/Latch will be trimmed during the optimization process.
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INFO:Xst:2261 - The FF/Latch <LAN_D_INIT_8> in Unit <LAN_IDE_CP> is equivalent to the following 2 FFs/Latches, which will be removed : <LAN_D_INIT_10> <LAN_D_INIT_11>
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INFO:Xst:2261 - The FF/Latch <LAN_D_INIT_1> in Unit <LAN_IDE_CP> is equivalent to the following 2 FFs/Latches, which will be removed : <LAN_D_INIT_4> <LAN_D_INIT_9>
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Optimizing unit <LAN_IDE_CP> ...
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implementation constraint: INIT=s : LAN_SM_FSM_FFd12
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implementation constraint: INIT=s : D_OUT_7
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implementation constraint: INIT=s : D_OUT_6
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implementation constraint: INIT=s : D_OUT_5
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implementation constraint: INIT=s : LAN_A_INIT_3
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implementation constraint: INIT=s : D_OUT_4
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implementation constraint: INIT=s : D_OUT_3
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implementation constraint: INIT=s : LAN_A_INIT_6
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implementation constraint: INIT=s : D_OUT_2
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implementation constraint: INIT=s : D_OUT_1
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implementation constraint: INIT=s : D_OUT_0
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implementation constraint: INIT=r : LAN_D_INIT_1
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implementation constraint: INIT=r : LAN_D_INIT_8
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implementation constraint: INIT=r : LAN_RST_SM_FSM_FFd1
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implementation constraint: INIT=r : LAN_RST_SM_FSM_FFd2
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implementation constraint: INIT=r : LAN_RST_SM_FSM_FFd3
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implementation constraint: INIT=r : LAN_SM_FSM_FFd1
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implementation constraint: INIT=r : LAN_SM_FSM_FFd2
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implementation constraint: INIT=r : LAN_SM_FSM_FFd3
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implementation constraint: INIT=r : LAN_SM_FSM_FFd4
|
|
implementation constraint: INIT=r : LAN_SM_FSM_FFd5
|
|
implementation constraint: INIT=r : LAN_SM_FSM_FFd6
|
|
implementation constraint: INIT=r : LAN_SM_FSM_FFd7
|
|
implementation constraint: INIT=r : LAN_SM_FSM_FFd8
|
|
implementation constraint: INIT=r : LAN_SM_FSM_FFd9
|
|
implementation constraint: INIT=r : LAN_SM_FSM_FFd10
|
|
implementation constraint: INIT=r : LAN_SM_FSM_FFd11
|
|
|
|
=========================================================================
|
|
* Partition Report *
|
|
=========================================================================
|
|
|
|
Partition Implementation Status
|
|
-------------------------------
|
|
|
|
No Partitions were found in this design.
|
|
|
|
-------------------------------
|
|
|
|
=========================================================================
|
|
* Final Report *
|
|
=========================================================================
|
|
Final Results
|
|
RTL Top Level Output File Name : LAN_IDE_CP.ngr
|
|
Top Level Output File Name : LAN_IDE_CP
|
|
Output Format : NGC
|
|
Optimization Goal : Speed
|
|
Keep Hierarchy : Yes
|
|
Target Technology : XC9500XL CPLDs
|
|
Macro Preserve : YES
|
|
XOR Preserve : YES
|
|
Clock Enable : YES
|
|
wysiwyg : NO
|
|
|
|
Design Statistics
|
|
# IOs : 116
|
|
|
|
Cell Usage :
|
|
# BELS : 903
|
|
# AND2 : 216
|
|
# AND3 : 77
|
|
# AND4 : 5
|
|
# AND8 : 4
|
|
# GND : 1
|
|
# INV : 268
|
|
# OR2 : 287
|
|
# OR3 : 8
|
|
# OR4 : 3
|
|
# OR8 : 16
|
|
# VCC : 1
|
|
# XOR2 : 17
|
|
# FlipFlops/Latches : 123
|
|
# FD : 1
|
|
# FDC : 25
|
|
# FDCE : 4
|
|
# FDP : 43
|
|
# FDPE : 50
|
|
# IO Buffers : 109
|
|
# IBUF : 19
|
|
# IOBUFE : 48
|
|
# OBUF : 33
|
|
# OBUFE : 9
|
|
=========================================================================
|
|
|
|
|
|
Total REAL time to Xst completion: 9.00 secs
|
|
Total CPU time to Xst completion: 8.66 secs
|
|
|
|
-->
|
|
|
|
Total memory usage is 4534828 kilobytes
|
|
|
|
Number of errors : 0 ( 0 filtered)
|
|
Number of warnings : 51 ( 0 filtered)
|
|
Number of infos : 10 ( 0 filtered)
|
|
|