Dominick.Vansevenant/Zorro-LAN-IDE
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Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.mfd
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MDF Database: version 1.0
MDF_INFO | LAN_IDE_CP | XC95288XL-10-TQ144
MACROCELL | 8 | 10 | Z3_DATA<0>
ATTRIBUTES | 8685506 | 0
INPUTS | 8 | DQ_SWAP | DQ<8>.PIN | DQ<0>.PIN | LAN_SM_RST | RW | FCS | $OpTx$FX_DC$39 | LAN_SM_FSM_FFd5
INPUTMC | 4 | 12 | 17 | 3 | 8 | 8 | 6 | 8 | 3
INPUTP | 4 | 231 | 217 | 158 | 147
EQ | 6 |
A<8>.D = DQ_SWAP & DQ<8>.PIN
# !DQ_SWAP & DQ<0>.PIN;
A<8>.CLK = CLK_EXT; // GCK
A<8>.AP = LAN_SM_RST;
A<8>.OE = RW & !FCS & !$OpTx$FX_DC$39;
A<8>.CE = LAN_SM_FSM_FFd5;
GLOBALS | 1 | 2 | CLK_EXT
MACROCELL | 15 | 5 | Z3_DATA<10>
ATTRIBUTES | 8685506 | 0
INPUTS | 8 | DQ_SWAP | DQ<2>.PIN | DQ<10>.PIN | LAN_SM_RST | RW | FCS | $OpTx$FX_DC$39 | LAN_SM_FSM_FFd5
INPUTMC | 4 | 12 | 17 | 3 | 8 | 8 | 6 | 8 | 3
INPUTP | 4 | 220 | 234 | 158 | 147
EQ | 6 |
A<18>.D = DQ_SWAP & DQ<2>.PIN
# !DQ_SWAP & DQ<10>.PIN;
A<18>.CLK = CLK_EXT; // GCK
A<18>.AP = LAN_SM_RST;
A<18>.OE = RW & !FCS & !$OpTx$FX_DC$39;
A<18>.CE = LAN_SM_FSM_FFd5;
GLOBALS | 1 | 2 | CLK_EXT
MACROCELL | 15 | 2 | Z3_DATA<11>
ATTRIBUTES | 8685506 | 0
INPUTS | 8 | DQ_SWAP | DQ<3>.PIN | DQ<11>.PIN | LAN_SM_RST | RW | FCS | $OpTx$FX_DC$39 | LAN_SM_FSM_FFd5
INPUTMC | 4 | 12 | 17 | 3 | 8 | 8 | 6 | 8 | 3
INPUTP | 4 | 219 | 207 | 158 | 147
EQ | 6 |
A<19>.D = DQ_SWAP & DQ<3>.PIN
# !DQ_SWAP & DQ<11>.PIN;
A<19>.CLK = CLK_EXT; // GCK
A<19>.AP = LAN_SM_RST;
A<19>.OE = RW & !FCS & !$OpTx$FX_DC$39;
A<19>.CE = LAN_SM_FSM_FFd5;
GLOBALS | 1 | 2 | CLK_EXT
MACROCELL | 15 | 1 | Z3_DATA<12>
ATTRIBUTES | 8685506 | 0
INPUTS | 8 | DQ_SWAP | DQ<4>.PIN | DQ<12>.PIN | LAN_SM_RST | RW | FCS | $OpTx$FX_DC$39 | LAN_SM_FSM_FFd5
INPUTMC | 4 | 12 | 17 | 3 | 8 | 8 | 6 | 8 | 3
INPUTP | 4 | 225 | 235 | 158 | 147
EQ | 6 |
A<20>.D = DQ_SWAP & DQ<4>.PIN
# !DQ_SWAP & DQ<12>.PIN;
A<20>.CLK = CLK_EXT; // GCK
A<20>.AP = LAN_SM_RST;
A<20>.OE = RW & !FCS & !$OpTx$FX_DC$39;
A<20>.CE = LAN_SM_FSM_FFd5;
GLOBALS | 1 | 2 | CLK_EXT
MACROCELL | 14 | 16 | Z3_DATA<13>
ATTRIBUTES | 8685506 | 0
INPUTS | 8 | DQ_SWAP | DQ<5>.PIN | DQ<13>.PIN | LAN_SM_RST | RW | FCS | $OpTx$FX_DC$39 | LAN_SM_FSM_FFd5
INPUTMC | 4 | 12 | 17 | 3 | 8 | 8 | 6 | 8 | 3
INPUTP | 4 | 221 | 204 | 158 | 147
EQ | 6 |
A<21>.D = DQ_SWAP & DQ<5>.PIN
# !DQ_SWAP & DQ<13>.PIN;
A<21>.CLK = CLK_EXT; // GCK
A<21>.AP = LAN_SM_RST;
A<21>.OE = RW & !FCS & !$OpTx$FX_DC$39;
A<21>.CE = LAN_SM_FSM_FFd5;
GLOBALS | 1 | 2 | CLK_EXT
MACROCELL | 14 | 14 | Z3_DATA<14>
ATTRIBUTES | 8685506 | 0
INPUTS | 8 | DQ_SWAP | DQ<6>.PIN | DQ<14>.PIN | LAN_SM_RST | RW | FCS | $OpTx$FX_DC$39 | LAN_SM_FSM_FFd5
INPUTMC | 4 | 12 | 17 | 3 | 8 | 8 | 6 | 8 | 3
INPUTP | 4 | 227 | 236 | 158 | 147
EQ | 6 |
A<22>.D = DQ_SWAP & DQ<6>.PIN
# !DQ_SWAP & DQ<14>.PIN;
A<22>.CLK = CLK_EXT; // GCK
A<22>.AP = LAN_SM_RST;
A<22>.OE = RW & !FCS & !$OpTx$FX_DC$39;
A<22>.CE = LAN_SM_FSM_FFd5;
GLOBALS | 1 | 2 | CLK_EXT
MACROCELL | 14 | 13 | Z3_DATA<15>
ATTRIBUTES | 8685506 | 0
INPUTS | 8 | DQ_SWAP | DQ<7>.PIN | DQ<15>.PIN | LAN_SM_RST | RW | FCS | $OpTx$FX_DC$39 | LAN_SM_FSM_FFd5
INPUTMC | 4 | 12 | 17 | 3 | 8 | 8 | 6 | 8 | 3
INPUTP | 4 | 226 | 202 | 158 | 147
EQ | 6 |
A<23>.D = DQ_SWAP & DQ<7>.PIN
# !DQ_SWAP & DQ<15>.PIN;
A<23>.CLK = CLK_EXT; // GCK
A<23>.AP = LAN_SM_RST;
A<23>.OE = RW & !FCS & !$OpTx$FX_DC$39;
A<23>.CE = LAN_SM_FSM_FFd5;
GLOBALS | 1 | 2 | CLK_EXT
MACROCELL | 8 | 13 | Z3_DATA<1>
ATTRIBUTES | 8685506 | 0
INPUTS | 8 | DQ_SWAP | DQ<9>.PIN | DQ<1>.PIN | LAN_SM_RST | RW | FCS | $OpTx$FX_DC$39 | LAN_SM_FSM_FFd5
INPUTMC | 4 | 12 | 17 | 3 | 8 | 8 | 6 | 8 | 3
INPUTP | 4 | 209 | 216 | 158 | 147
EQ | 6 |
A<9>.D = DQ_SWAP & DQ<9>.PIN
# !DQ_SWAP & DQ<1>.PIN;
A<9>.CLK = CLK_EXT; // GCK
A<9>.AP = LAN_SM_RST;
A<9>.OE = RW & !FCS & !$OpTx$FX_DC$39;
A<9>.CE = LAN_SM_FSM_FFd5;
GLOBALS | 1 | 2 | CLK_EXT
MACROCELL | 8 | 16 | Z3_DATA<2>
ATTRIBUTES | 8685506 | 0
INPUTS | 8 | DQ_SWAP | DQ<2>.PIN | DQ<10>.PIN | LAN_SM_RST | RW | FCS | $OpTx$FX_DC$39 | LAN_SM_FSM_FFd5
INPUTMC | 4 | 12 | 17 | 3 | 8 | 8 | 6 | 8 | 3
INPUTP | 4 | 220 | 234 | 158 | 147
EQ | 6 |
A<10>.D = DQ_SWAP & DQ<10>.PIN
# !DQ_SWAP & DQ<2>.PIN;
A<10>.CLK = CLK_EXT; // GCK
A<10>.AP = LAN_SM_RST;
A<10>.OE = RW & !FCS & !$OpTx$FX_DC$39;
A<10>.CE = LAN_SM_FSM_FFd5;
GLOBALS | 1 | 2 | CLK_EXT
MACROCELL | 10 | 2 | Z3_DATA<3>
ATTRIBUTES | 8685506 | 0
INPUTS | 8 | DQ_SWAP | DQ<3>.PIN | DQ<11>.PIN | LAN_SM_RST | RW | FCS | $OpTx$FX_DC$39 | LAN_SM_FSM_FFd5
INPUTMC | 4 | 12 | 17 | 3 | 8 | 8 | 6 | 8 | 3
INPUTP | 4 | 219 | 207 | 158 | 147
EQ | 6 |
A<11>.D = DQ_SWAP & DQ<11>.PIN
# !DQ_SWAP & DQ<3>.PIN;
A<11>.CLK = CLK_EXT; // GCK
A<11>.AP = LAN_SM_RST;
A<11>.OE = RW & !FCS & !$OpTx$FX_DC$39;
A<11>.CE = LAN_SM_FSM_FFd5;
GLOBALS | 1 | 2 | CLK_EXT
MACROCELL | 10 | 4 | Z3_DATA<4>
ATTRIBUTES | 8685506 | 0
INPUTS | 8 | DQ_SWAP | DQ<4>.PIN | DQ<12>.PIN | LAN_SM_RST | RW | FCS | $OpTx$FX_DC$39 | LAN_SM_FSM_FFd5
INPUTMC | 4 | 12 | 17 | 3 | 8 | 8 | 6 | 8 | 3
INPUTP | 4 | 225 | 235 | 158 | 147
EQ | 6 |
A<12>.D = DQ_SWAP & DQ<12>.PIN
# !DQ_SWAP & DQ<4>.PIN;
A<12>.CLK = CLK_EXT; // GCK
A<12>.AP = LAN_SM_RST;
A<12>.OE = RW & !FCS & !$OpTx$FX_DC$39;
A<12>.CE = LAN_SM_FSM_FFd5;
GLOBALS | 1 | 2 | CLK_EXT
MACROCELL | 10 | 9 | Z3_DATA<5>
ATTRIBUTES | 8685506 | 0
INPUTS | 8 | DQ_SWAP | DQ<5>.PIN | DQ<13>.PIN | LAN_SM_RST | RW | FCS | $OpTx$FX_DC$39 | LAN_SM_FSM_FFd5
INPUTMC | 4 | 12 | 17 | 3 | 8 | 8 | 6 | 8 | 3
INPUTP | 4 | 221 | 204 | 158 | 147
EQ | 6 |
A<13>.D = DQ_SWAP & DQ<13>.PIN
# !DQ_SWAP & DQ<5>.PIN;
A<13>.CLK = CLK_EXT; // GCK
A<13>.AP = LAN_SM_RST;
A<13>.OE = RW & !FCS & !$OpTx$FX_DC$39;
A<13>.CE = LAN_SM_FSM_FFd5;
GLOBALS | 1 | 2 | CLK_EXT
MACROCELL | 10 | 10 | Z3_DATA<6>
ATTRIBUTES | 8685506 | 0
INPUTS | 8 | DQ_SWAP | DQ<6>.PIN | DQ<14>.PIN | LAN_SM_RST | RW | FCS | $OpTx$FX_DC$39 | LAN_SM_FSM_FFd5
INPUTMC | 4 | 12 | 17 | 3 | 8 | 8 | 6 | 8 | 3
INPUTP | 4 | 227 | 236 | 158 | 147
EQ | 6 |
A<14>.D = DQ_SWAP & DQ<14>.PIN
# !DQ_SWAP & DQ<6>.PIN;
A<14>.CLK = CLK_EXT; // GCK
A<14>.AP = LAN_SM_RST;
A<14>.OE = RW & !FCS & !$OpTx$FX_DC$39;
A<14>.CE = LAN_SM_FSM_FFd5;
GLOBALS | 1 | 2 | CLK_EXT
MACROCELL | 12 | 7 | Z3_DATA<7>
ATTRIBUTES | 8685506 | 0
INPUTS | 8 | DQ_SWAP | DQ<7>.PIN | DQ<15>.PIN | LAN_SM_RST | RW | FCS | $OpTx$FX_DC$39 | LAN_SM_FSM_FFd5
INPUTMC | 4 | 12 | 17 | 3 | 8 | 8 | 6 | 8 | 3
INPUTP | 4 | 226 | 202 | 158 | 147
EQ | 6 |
A<15>.D = DQ_SWAP & DQ<15>.PIN
# !DQ_SWAP & DQ<7>.PIN;
A<15>.CLK = CLK_EXT; // GCK
A<15>.AP = LAN_SM_RST;
A<15>.OE = RW & !FCS & !$OpTx$FX_DC$39;
A<15>.CE = LAN_SM_FSM_FFd5;
GLOBALS | 1 | 2 | CLK_EXT
MACROCELL | 15 | 10 | Z3_DATA<8>
ATTRIBUTES | 8685506 | 0
INPUTS | 8 | DQ_SWAP | DQ<8>.PIN | DQ<0>.PIN | LAN_SM_RST | RW | FCS | $OpTx$FX_DC$39 | LAN_SM_FSM_FFd5
INPUTMC | 4 | 12 | 17 | 3 | 8 | 8 | 6 | 8 | 3
INPUTP | 4 | 231 | 217 | 158 | 147
EQ | 6 |
A<16>.D = DQ_SWAP & DQ<0>.PIN
# !DQ_SWAP & DQ<8>.PIN;
A<16>.CLK = CLK_EXT; // GCK
A<16>.AP = LAN_SM_RST;
A<16>.OE = RW & !FCS & !$OpTx$FX_DC$39;
A<16>.CE = LAN_SM_FSM_FFd5;
GLOBALS | 1 | 2 | CLK_EXT
MACROCELL | 15 | 7 | Z3_DATA<9>
ATTRIBUTES | 8685506 | 0
INPUTS | 8 | DQ_SWAP | DQ<9>.PIN | DQ<1>.PIN | LAN_SM_RST | RW | FCS | $OpTx$FX_DC$39 | LAN_SM_FSM_FFd5
INPUTMC | 4 | 12 | 17 | 3 | 8 | 8 | 6 | 8 | 3
INPUTP | 4 | 209 | 216 | 158 | 147
EQ | 6 |
A<17>.D = DQ_SWAP & DQ<1>.PIN
# !DQ_SWAP & DQ<9>.PIN;
A<17>.CLK = CLK_EXT; // GCK
A<17>.AP = LAN_SM_RST;
A<17>.OE = RW & !FCS & !$OpTx$FX_DC$39;
A<17>.CE = LAN_SM_FSM_FFd5;
GLOBALS | 1 | 2 | CLK_EXT
MACROCELL | 14 | 4 | AUTO_CONFIG_DONE_CYCLE
ATTRIBUTES | 4358992 | 0
OUTPUTMC | 2 | 14 | 4 | 13 | 10
INPUTS | 12 | RW | AUTO_CONFIG_DONE_CYCLE | Z3_ADR<2> | Z3_ADR_0 | Z3_ADR<6> | Z3_ADR<3> | Z3_ADR<4> | Z3_ADR<5> | RESET | FCS | UDS | AUTOCONFIG_ACCESS
INPUTMC | 8 | 14 | 4 | 12 | 10 | 6 | 9 | 6 | 14 | 13 | 12 | 6 | 16 | 6 | 15 | 5 | 16
INPUTP | 4 | 158 | 263 | 147 | 155
EQ | 5 |
AUTO_CONFIG_DONE_CYCLE.T = !RW & !AUTO_CONFIG_DONE_CYCLE & !Z3_ADR<2> &
Z3_ADR_0 & !Z3_ADR<6> & !Z3_ADR<3> & Z3_ADR<4> & !Z3_ADR<5>;
AUTO_CONFIG_DONE_CYCLE.CLK = CLK_EXT; // GCK
AUTO_CONFIG_DONE_CYCLE.AR = !RESET;
AUTO_CONFIG_DONE_CYCLE.CE = !FCS & !UDS & AUTOCONFIG_ACCESS;
GLOBALS | 1 | 2 | CLK_EXT
MACROCELL | 10 | 14 | LAN_BASEADR<0>
ATTRIBUTES | 8553408 | 0
OUTPUTMC | 1 | 13 | 0
INPUTS | 13 | D<0>.PIN | RESET | RW | FCS | UDS | Z3_ADR<2> | Z3_ADR_1 | Z3_ADR_0 | Z3_ADR<6> | AUTOCONFIG_ACCESS | Z3_ADR<3> | Z3_ADR<4> | Z3_ADR<5>
INPUTMC | 8 | 12 | 10 | 6 | 8 | 6 | 9 | 6 | 14 | 5 | 16 | 13 | 12 | 6 | 16 | 6 | 15
INPUTP | 5 | 4 | 263 | 158 | 147 | 155
EQ | 6 |
LAN_BASEADR<0>.D = D<0>.PIN;
LAN_BASEADR<0>.CLK = CLK_EXT; // GCK
LAN_BASEADR<0>.AP = !RESET;
LAN_BASEADR<0>.CE = !RW & !FCS & !UDS & !Z3_ADR<2> & !Z3_ADR_1 &
Z3_ADR_0 & !Z3_ADR<6> & AUTOCONFIG_ACCESS & !Z3_ADR<3> &
Z3_ADR<4> & !Z3_ADR<5>;
GLOBALS | 1 | 2 | CLK_EXT
MACROCELL | 10 | 12 | LAN_BASEADR<10>
ATTRIBUTES | 8553408 | 0
OUTPUTMC | 1 | 13 | 9
INPUTS | 13 | D<10>.PIN | RESET | RW | FCS | UDS | Z3_ADR<2> | Z3_ADR_1 | Z3_ADR_0 | Z3_ADR<6> | AUTOCONFIG_ACCESS | Z3_ADR<3> | Z3_ADR<4> | Z3_ADR<5>
INPUTMC | 8 | 12 | 10 | 6 | 8 | 6 | 9 | 6 | 14 | 5 | 16 | 13 | 12 | 6 | 16 | 6 | 15
INPUTP | 5 | 74 | 263 | 158 | 147 | 155
EQ | 6 |
LAN_BASEADR<10>.D = D<10>.PIN;
LAN_BASEADR<10>.CLK = CLK_EXT; // GCK
LAN_BASEADR<10>.AP = !RESET;
LAN_BASEADR<10>.CE = !RW & !FCS & !UDS & !Z3_ADR<2> & !Z3_ADR_1 &
Z3_ADR_0 & !Z3_ADR<6> & AUTOCONFIG_ACCESS & !Z3_ADR<3> &
Z3_ADR<4> & !Z3_ADR<5>;
GLOBALS | 1 | 2 | CLK_EXT
MACROCELL | 10 | 8 | LAN_BASEADR<11>
ATTRIBUTES | 8553408 | 0
OUTPUTMC | 1 | 13 | 11
INPUTS | 13 | D<11>.PIN | RESET | RW | FCS | UDS | Z3_ADR<2> | Z3_ADR_1 | Z3_ADR_0 | Z3_ADR<6> | AUTOCONFIG_ACCESS | Z3_ADR<3> | Z3_ADR<4> | Z3_ADR<5>
INPUTMC | 8 | 12 | 10 | 6 | 8 | 6 | 9 | 6 | 14 | 5 | 16 | 13 | 12 | 6 | 16 | 6 | 15
INPUTP | 5 | 77 | 263 | 158 | 147 | 155
EQ | 6 |
LAN_BASEADR<11>.D = D<11>.PIN;
LAN_BASEADR<11>.CLK = CLK_EXT; // GCK
LAN_BASEADR<11>.AP = !RESET;
LAN_BASEADR<11>.CE = !RW & !FCS & !UDS & !Z3_ADR<2> & !Z3_ADR_1 &
Z3_ADR_0 & !Z3_ADR<6> & AUTOCONFIG_ACCESS & !Z3_ADR<3> &
Z3_ADR<4> & !Z3_ADR<5>;
GLOBALS | 1 | 2 | CLK_EXT
MACROCELL | 10 | 7 | LAN_BASEADR<12>
ATTRIBUTES | 8553408 | 0
OUTPUTMC | 2 | 12 | 17 | 12 | 16
INPUTS | 13 | D<12>.PIN | RESET | RW | FCS | UDS | Z3_ADR<2> | Z3_ADR_1 | Z3_ADR_0 | Z3_ADR<6> | AUTOCONFIG_ACCESS | Z3_ADR<3> | Z3_ADR<4> | Z3_ADR<5>
INPUTMC | 8 | 12 | 10 | 6 | 8 | 6 | 9 | 6 | 14 | 5 | 16 | 13 | 12 | 6 | 16 | 6 | 15
INPUTP | 5 | 78 | 263 | 158 | 147 | 155
EQ | 6 |
LAN_BASEADR<12>.D = D<12>.PIN;
LAN_BASEADR<12>.CLK = CLK_EXT; // GCK
LAN_BASEADR<12>.AP = !RESET;
LAN_BASEADR<12>.CE = !RW & !FCS & !UDS & !Z3_ADR<2> & !Z3_ADR_1 &
Z3_ADR_0 & !Z3_ADR<6> & AUTOCONFIG_ACCESS & !Z3_ADR<3> &
Z3_ADR<4> & !Z3_ADR<5>;
GLOBALS | 1 | 2 | CLK_EXT
MACROCELL | 10 | 6 | LAN_BASEADR<13>
ATTRIBUTES | 8553408 | 0
OUTPUTMC | 1 | 5 | 17
INPUTS | 13 | D<13>.PIN | RESET | RW | FCS | UDS | Z3_ADR<2> | Z3_ADR_1 | Z3_ADR_0 | Z3_ADR<6> | AUTOCONFIG_ACCESS | Z3_ADR<3> | Z3_ADR<4> | Z3_ADR<5>
INPUTMC | 8 | 12 | 10 | 6 | 8 | 6 | 9 | 6 | 14 | 5 | 16 | 13 | 12 | 6 | 16 | 6 | 15
INPUTP | 5 | 80 | 263 | 158 | 147 | 155
EQ | 6 |
LAN_BASEADR<13>.D = D<13>.PIN;
LAN_BASEADR<13>.CLK = CLK_EXT; // GCK
LAN_BASEADR<13>.AP = !RESET;
LAN_BASEADR<13>.CE = !RW & !FCS & !UDS & !Z3_ADR<2> & !Z3_ADR_1 &
Z3_ADR_0 & !Z3_ADR<6> & AUTOCONFIG_ACCESS & !Z3_ADR<3> &
Z3_ADR<4> & !Z3_ADR<5>;
GLOBALS | 1 | 2 | CLK_EXT
MACROCELL | 1 | 17 | LAN_BASEADR<14>
ATTRIBUTES | 8553408 | 0
OUTPUTMC | 2 | 13 | 1 | 13 | 16
INPUTS | 13 | D<14>.PIN | RESET | RW | FCS | UDS | Z3_ADR<2> | Z3_ADR_1 | Z3_ADR_0 | Z3_ADR<6> | AUTOCONFIG_ACCESS | Z3_ADR<3> | Z3_ADR<4> | Z3_ADR<5>
INPUTMC | 8 | 12 | 10 | 6 | 8 | 6 | 9 | 6 | 14 | 5 | 16 | 13 | 12 | 6 | 16 | 6 | 15
INPUTP | 5 | 81 | 263 | 158 | 147 | 155
EQ | 6 |
LAN_BASEADR<14>.D = D<14>.PIN;
LAN_BASEADR<14>.CLK = CLK_EXT; // GCK
LAN_BASEADR<14>.AP = !RESET;
LAN_BASEADR<14>.CE = !RW & !FCS & !UDS & !Z3_ADR<2> & !Z3_ADR_1 &
Z3_ADR_0 & !Z3_ADR<6> & AUTOCONFIG_ACCESS & !Z3_ADR<3> &
Z3_ADR<4> & !Z3_ADR<5>;
GLOBALS | 1 | 2 | CLK_EXT
MACROCELL | 1 | 15 | LAN_BASEADR<15>
ATTRIBUTES | 8553408 | 0
OUTPUTMC | 1 | 0 | 15
INPUTS | 13 | D<15>.PIN | RESET | RW | FCS | UDS | Z3_ADR<2> | Z3_ADR_1 | Z3_ADR_0 | Z3_ADR<6> | AUTOCONFIG_ACCESS | Z3_ADR<3> | Z3_ADR<4> | Z3_ADR<5>
INPUTMC | 8 | 12 | 10 | 6 | 8 | 6 | 9 | 6 | 14 | 5 | 16 | 13 | 12 | 6 | 16 | 6 | 15
INPUTP | 5 | 89 | 263 | 158 | 147 | 155
EQ | 6 |
LAN_BASEADR<15>.D = D<15>.PIN;
LAN_BASEADR<15>.CLK = CLK_EXT; // GCK
LAN_BASEADR<15>.AP = !RESET;
LAN_BASEADR<15>.CE = !RW & !FCS & !UDS & !Z3_ADR<2> & !Z3_ADR_1 &
Z3_ADR_0 & !Z3_ADR<6> & AUTOCONFIG_ACCESS & !Z3_ADR<3> &
Z3_ADR<4> & !Z3_ADR<5>;
GLOBALS | 1 | 2 | CLK_EXT
MACROCELL | 1 | 12 | LAN_BASEADR<1>
ATTRIBUTES | 8553408 | 0
OUTPUTMC | 1 | 13 | 0
INPUTS | 13 | D<1>.PIN | RESET | RW | FCS | UDS | Z3_ADR<2> | Z3_ADR_1 | Z3_ADR_0 | Z3_ADR<6> | AUTOCONFIG_ACCESS | Z3_ADR<3> | Z3_ADR<4> | Z3_ADR<5>
INPUTMC | 8 | 12 | 10 | 6 | 8 | 6 | 9 | 6 | 14 | 5 | 16 | 13 | 12 | 6 | 16 | 6 | 15
INPUTP | 5 | 30 | 263 | 158 | 147 | 155
EQ | 6 |
LAN_BASEADR<1>.D = D<1>.PIN;
LAN_BASEADR<1>.CLK = CLK_EXT; // GCK
LAN_BASEADR<1>.AP = !RESET;
LAN_BASEADR<1>.CE = !RW & !FCS & !UDS & !Z3_ADR<2> & !Z3_ADR_1 &
Z3_ADR_0 & !Z3_ADR<6> & AUTOCONFIG_ACCESS & !Z3_ADR<3> &
Z3_ADR<4> & !Z3_ADR<5>;
GLOBALS | 1 | 2 | CLK_EXT
MACROCELL | 1 | 10 | LAN_BASEADR<2>
ATTRIBUTES | 8553408 | 0
OUTPUTMC | 2 | 13 | 0 | 13 | 17
INPUTS | 13 | D<2>.PIN | RESET | RW | FCS | UDS | Z3_ADR<2> | Z3_ADR_1 | Z3_ADR_0 | Z3_ADR<6> | AUTOCONFIG_ACCESS | Z3_ADR<3> | Z3_ADR<4> | Z3_ADR<5>
INPUTMC | 8 | 12 | 10 | 6 | 8 | 6 | 9 | 6 | 14 | 5 | 16 | 13 | 12 | 6 | 16 | 6 | 15
INPUTP | 5 | 71 | 263 | 158 | 147 | 155
EQ | 6 |
LAN_BASEADR<2>.D = D<2>.PIN;
LAN_BASEADR<2>.CLK = CLK_EXT; // GCK
LAN_BASEADR<2>.AP = !RESET;
LAN_BASEADR<2>.CE = !RW & !FCS & !UDS & !Z3_ADR<2> & !Z3_ADR_1 &
Z3_ADR_0 & !Z3_ADR<6> & AUTOCONFIG_ACCESS & !Z3_ADR<3> &
Z3_ADR<4> & !Z3_ADR<5>;
GLOBALS | 1 | 2 | CLK_EXT
MACROCELL | 1 | 8 | LAN_BASEADR<3>
ATTRIBUTES | 8553408 | 0
OUTPUTMC | 1 | 13 | 17
INPUTS | 13 | D<3>.PIN | RESET | RW | FCS | UDS | Z3_ADR<2> | Z3_ADR_1 | Z3_ADR_0 | Z3_ADR<6> | AUTOCONFIG_ACCESS | Z3_ADR<3> | Z3_ADR<4> | Z3_ADR<5>
INPUTMC | 8 | 12 | 10 | 6 | 8 | 6 | 9 | 6 | 14 | 5 | 16 | 13 | 12 | 6 | 16 | 6 | 15
INPUTP | 5 | 28 | 263 | 158 | 147 | 155
EQ | 6 |
LAN_BASEADR<3>.D = D<3>.PIN;
LAN_BASEADR<3>.CLK = CLK_EXT; // GCK
LAN_BASEADR<3>.AP = !RESET;
LAN_BASEADR<3>.CE = !RW & !FCS & !UDS & !Z3_ADR<2> & !Z3_ADR_1 &
Z3_ADR_0 & !Z3_ADR<6> & AUTOCONFIG_ACCESS & !Z3_ADR<3> &
Z3_ADR<4> & !Z3_ADR<5>;
GLOBALS | 1 | 2 | CLK_EXT
MACROCELL | 1 | 6 | LAN_BASEADR<4>
ATTRIBUTES | 8553408 | 0
OUTPUTMC | 1 | 13 | 17
INPUTS | 13 | D<4>.PIN | RESET | RW | FCS | UDS | Z3_ADR<2> | Z3_ADR_1 | Z3_ADR_0 | Z3_ADR<6> | AUTOCONFIG_ACCESS | Z3_ADR<3> | Z3_ADR<4> | Z3_ADR<5>
INPUTMC | 8 | 12 | 10 | 6 | 8 | 6 | 9 | 6 | 14 | 5 | 16 | 13 | 12 | 6 | 16 | 6 | 15
INPUTP | 5 | 38 | 263 | 158 | 147 | 155
EQ | 6 |
LAN_BASEADR<4>.D = D<4>.PIN;
LAN_BASEADR<4>.CLK = CLK_EXT; // GCK
LAN_BASEADR<4>.AP = !RESET;
LAN_BASEADR<4>.CE = !RW & !FCS & !UDS & !Z3_ADR<2> & !Z3_ADR_1 &
Z3_ADR_0 & !Z3_ADR<6> & AUTOCONFIG_ACCESS & !Z3_ADR<3> &
Z3_ADR<4> & !Z3_ADR<5>;
GLOBALS | 1 | 2 | CLK_EXT
MACROCELL | 1 | 3 | LAN_BASEADR<5>
ATTRIBUTES | 8553408 | 0
OUTPUTMC | 1 | 13 | 1
INPUTS | 13 | D<5>.PIN | RESET | RW | FCS | UDS | Z3_ADR<2> | Z3_ADR_1 | Z3_ADR_0 | Z3_ADR<6> | AUTOCONFIG_ACCESS | Z3_ADR<3> | Z3_ADR<4> | Z3_ADR<5>
INPUTMC | 8 | 12 | 10 | 6 | 8 | 6 | 9 | 6 | 14 | 5 | 16 | 13 | 12 | 6 | 16 | 6 | 15
INPUTP | 5 | 37 | 263 | 158 | 147 | 155
EQ | 6 |
LAN_BASEADR<5>.D = D<5>.PIN;
LAN_BASEADR<5>.CLK = CLK_EXT; // GCK
LAN_BASEADR<5>.AP = !RESET;
LAN_BASEADR<5>.CE = !RW & !FCS & !UDS & !Z3_ADR<2> & !Z3_ADR_1 &
Z3_ADR_0 & !Z3_ADR<6> & AUTOCONFIG_ACCESS & !Z3_ADR<3> &
Z3_ADR<4> & !Z3_ADR<5>;
GLOBALS | 1 | 2 | CLK_EXT
MACROCELL | 10 | 5 | LAN_BASEADR<6>
ATTRIBUTES | 8553408 | 0
OUTPUTMC | 1 | 5 | 17
INPUTS | 13 | D<6>.PIN | RESET | RW | FCS | UDS | Z3_ADR<2> | Z3_ADR_1 | Z3_ADR_0 | Z3_ADR<6> | AUTOCONFIG_ACCESS | Z3_ADR<3> | Z3_ADR<4> | Z3_ADR<5>
INPUTMC | 8 | 12 | 10 | 6 | 8 | 6 | 9 | 6 | 14 | 5 | 16 | 13 | 12 | 6 | 16 | 6 | 15
INPUTP | 5 | 26 | 263 | 158 | 147 | 155
EQ | 6 |
LAN_BASEADR<6>.D = D<6>.PIN;
LAN_BASEADR<6>.CLK = CLK_EXT; // GCK
LAN_BASEADR<6>.AP = !RESET;
LAN_BASEADR<6>.CE = !RW & !FCS & !UDS & !Z3_ADR<2> & !Z3_ADR_1 &
Z3_ADR_0 & !Z3_ADR<6> & AUTOCONFIG_ACCESS & !Z3_ADR<3> &
Z3_ADR<4> & !Z3_ADR<5>;
GLOBALS | 1 | 2 | CLK_EXT
MACROCELL | 10 | 3 | LAN_BASEADR<7>
ATTRIBUTES | 8553408 | 0
OUTPUTMC | 1 | 13 | 1
INPUTS | 13 | D<7>.PIN | RESET | RW | FCS | UDS | Z3_ADR<2> | Z3_ADR_1 | Z3_ADR_0 | Z3_ADR<6> | AUTOCONFIG_ACCESS | Z3_ADR<3> | Z3_ADR<4> | Z3_ADR<5>
INPUTMC | 8 | 12 | 10 | 6 | 8 | 6 | 9 | 6 | 14 | 5 | 16 | 13 | 12 | 6 | 16 | 6 | 15
INPUTP | 5 | 29 | 263 | 158 | 147 | 155
EQ | 6 |
LAN_BASEADR<7>.D = D<7>.PIN;
LAN_BASEADR<7>.CLK = CLK_EXT; // GCK
LAN_BASEADR<7>.AP = !RESET;
LAN_BASEADR<7>.CE = !RW & !FCS & !UDS & !Z3_ADR<2> & !Z3_ADR_1 &
Z3_ADR_0 & !Z3_ADR<6> & AUTOCONFIG_ACCESS & !Z3_ADR<3> &
Z3_ADR<4> & !Z3_ADR<5>;
GLOBALS | 1 | 2 | CLK_EXT
MACROCELL | 10 | 1 | LAN_BASEADR<8>
ATTRIBUTES | 8553408 | 0
OUTPUTMC | 1 | 0 | 17
INPUTS | 13 | D<8>.PIN | RESET | RW | FCS | UDS | Z3_ADR<2> | Z3_ADR_1 | Z3_ADR_0 | Z3_ADR<6> | AUTOCONFIG_ACCESS | Z3_ADR<3> | Z3_ADR<4> | Z3_ADR<5>
INPUTMC | 8 | 12 | 10 | 6 | 8 | 6 | 9 | 6 | 14 | 5 | 16 | 13 | 12 | 6 | 16 | 6 | 15
INPUTP | 5 | 32 | 263 | 158 | 147 | 155
EQ | 6 |
LAN_BASEADR<8>.D = D<8>.PIN;
LAN_BASEADR<8>.CLK = CLK_EXT; // GCK
LAN_BASEADR<8>.AP = !RESET;
LAN_BASEADR<8>.CE = !RW & !FCS & !UDS & !Z3_ADR<2> & !Z3_ADR_1 &
Z3_ADR_0 & !Z3_ADR<6> & AUTOCONFIG_ACCESS & !Z3_ADR<3> &
Z3_ADR<4> & !Z3_ADR<5>;
GLOBALS | 1 | 2 | CLK_EXT
MACROCELL | 10 | 0 | LAN_BASEADR<9>
ATTRIBUTES | 8553408 | 0
OUTPUTMC | 1 | 6 | 7
INPUTS | 13 | D<9>.PIN | RESET | RW | FCS | UDS | Z3_ADR<2> | Z3_ADR_1 | Z3_ADR_0 | Z3_ADR<6> | AUTOCONFIG_ACCESS | Z3_ADR<3> | Z3_ADR<4> | Z3_ADR<5>
INPUTMC | 8 | 12 | 10 | 6 | 8 | 6 | 9 | 6 | 14 | 5 | 16 | 13 | 12 | 6 | 16 | 6 | 15
INPUTP | 5 | 73 | 263 | 158 | 147 | 155
EQ | 6 |
LAN_BASEADR<9>.D = D<9>.PIN;
LAN_BASEADR<9>.CLK = CLK_EXT; // GCK
LAN_BASEADR<9>.AP = !RESET;
LAN_BASEADR<9>.CE = !RW & !FCS & !UDS & !Z3_ADR<2> & !Z3_ADR_1 &
Z3_ADR_0 & !Z3_ADR<6> & AUTOCONFIG_ACCESS & !Z3_ADR<3> &
Z3_ADR<4> & !Z3_ADR<5>;
GLOBALS | 1 | 2 | CLK_EXT
MACROCELL | 3 | 16 | LAN_INT_ENABLE
ATTRIBUTES | 8553232 | 0
OUTPUTMC | 2 | 3 | 16 | 2 | 13
INPUTS | 7 | LAN_INT_ENABLE | CONFIG_READY/CONFIG_READY_CE | D<15>.PIN | UDS | LDS | A<23>.PIN | RESET
INPUTMC | 2 | 3 | 16 | 3 | 9
INPUTP | 5 | 89 | 155 | 157 | 161 | 263
EQ | 7 |
LAN_INT_ENABLE.D = LAN_INT_ENABLE & !CONFIG_READY/CONFIG_READY_CE
# D<15>.PIN & !UDS & CONFIG_READY/CONFIG_READY_CE
# UDS & LDS & LAN_INT_ENABLE
# UDS & !LDS & A<23>.PIN &
CONFIG_READY/CONFIG_READY_CE;
LAN_INT_ENABLE.CLK = CLK_EXT; // GCK
LAN_INT_ENABLE.AR = !RESET;
GLOBALS | 1 | 2 | CLK_EXT
MACROCELL | 5 | 15 | LAN_IRQ_OUT
ATTRIBUTES | 8553344 | 0
OUTPUTMC | 2 | 5 | 15 | 2 | 13
INPUTS | 4 | LAN_IRQ_OUT | LAN_IRQ_D0 | LAN_INT | RESET
INPUTMC | 2 | 5 | 15 | 3 | 12
INPUTP | 2 | 201 | 263
EQ | 4 |
LAN_IRQ_OUT.D = LAN_INT
# LAN_IRQ_OUT & !LAN_IRQ_D0;
LAN_IRQ_OUT.CLK = CLK_EXT; // GCK
LAN_IRQ_OUT.AP = !RESET;
GLOBALS | 1 | 2 | CLK_EXT
MACROCELL | 15 | 16 | Z3_DATA<16>
ATTRIBUTES | 8553408 | 0
OUTPUTMC | 2 | 3 | 1 | 15 | 17
INPUTS | 11 | DQ_SWAP | DQ<8>.PIN | DQ<0>.PIN | LAN_SM_RST | LAN_SM_FSM_FFd7 | LDS | LAN_SM_FSM_FFd10 | LAN_SM_FSM_FFd3 | LAN_SM_FSM_FFd8 | LAN_SM_FSM_FFd2 | LAN_SM_FSM_FFd6
INPUTMC | 8 | 12 | 17 | 3 | 8 | 8 | 9 | 8 | 14 | 8 | 11 | 8 | 8 | 12 | 6 | 8 | 2
INPUTP | 3 | 231 | 217 | 157
EXPORTS | 1 | 15 | 17
EQ | 8 |
Z3_DATA<16>.D = DQ_SWAP & DQ<8>.PIN
# !DQ_SWAP & DQ<0>.PIN;
Z3_DATA<16>.CLK = CLK_EXT; // GCK
Z3_DATA<16>.AP = LAN_SM_RST;
Z3_DATA<16>.CE = LAN_SM_FSM_FFd7;
Z3_DATA<16>.EXP = !LDS & !LAN_SM_FSM_FFd7 & !LAN_SM_FSM_FFd10 &
!LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd8 & !LAN_SM_FSM_FFd2 &
!LAN_SM_FSM_FFd6
GLOBALS | 1 | 2 | CLK_EXT
MACROCELL | 15 | 15 | Z3_DATA<17>
ATTRIBUTES | 8553408 | 0
OUTPUTMC | 1 | 1 | 14
INPUTS | 5 | DQ_SWAP | DQ<9>.PIN | DQ<1>.PIN | LAN_SM_RST | LAN_SM_FSM_FFd7
INPUTMC | 3 | 12 | 17 | 3 | 8 | 8 | 9
INPUTP | 2 | 209 | 216
EQ | 5 |
Z3_DATA<17>.D = DQ_SWAP & DQ<9>.PIN
# !DQ_SWAP & DQ<1>.PIN;
Z3_DATA<17>.CLK = CLK_EXT; // GCK
Z3_DATA<17>.AP = LAN_SM_RST;
Z3_DATA<17>.CE = LAN_SM_FSM_FFd7;
GLOBALS | 1 | 2 | CLK_EXT
MACROCELL | 15 | 14 | Z3_DATA<18>
ATTRIBUTES | 8553408 | 0
OUTPUTMC | 1 | 4 | 9
INPUTS | 5 | DQ_SWAP | DQ<2>.PIN | DQ<10>.PIN | LAN_SM_RST | LAN_SM_FSM_FFd7
INPUTMC | 3 | 12 | 17 | 3 | 8 | 8 | 9
INPUTP | 2 | 220 | 234
EQ | 5 |
Z3_DATA<18>.D = DQ_SWAP & DQ<10>.PIN
# !DQ_SWAP & DQ<2>.PIN;
Z3_DATA<18>.CLK = CLK_EXT; // GCK
Z3_DATA<18>.AP = LAN_SM_RST;
Z3_DATA<18>.CE = LAN_SM_FSM_FFd7;
GLOBALS | 1 | 2 | CLK_EXT
MACROCELL | 15 | 13 | Z3_DATA<19>
ATTRIBUTES | 8553408 | 0
OUTPUTMC | 1 | 1 | 11
INPUTS | 5 | DQ_SWAP | DQ<3>.PIN | DQ<11>.PIN | LAN_SM_RST | LAN_SM_FSM_FFd7
INPUTMC | 3 | 12 | 17 | 3 | 8 | 8 | 9
INPUTP | 2 | 219 | 207
EQ | 5 |
Z3_DATA<19>.D = DQ_SWAP & DQ<11>.PIN
# !DQ_SWAP & DQ<3>.PIN;
Z3_DATA<19>.CLK = CLK_EXT; // GCK
Z3_DATA<19>.AP = LAN_SM_RST;
Z3_DATA<19>.CE = LAN_SM_FSM_FFd7;
GLOBALS | 1 | 2 | CLK_EXT
MACROCELL | 15 | 12 | Z3_DATA<20>
ATTRIBUTES | 8553408 | 0
OUTPUTMC | 1 | 0 | 5
INPUTS | 5 | DQ_SWAP | DQ<4>.PIN | DQ<12>.PIN | LAN_SM_RST | LAN_SM_FSM_FFd7
INPUTMC | 3 | 12 | 17 | 3 | 8 | 8 | 9
INPUTP | 2 | 225 | 235
EQ | 5 |
Z3_DATA<20>.D = DQ_SWAP & DQ<12>.PIN
# !DQ_SWAP & DQ<4>.PIN;
Z3_DATA<20>.CLK = CLK_EXT; // GCK
Z3_DATA<20>.AP = LAN_SM_RST;
Z3_DATA<20>.CE = LAN_SM_FSM_FFd7;
GLOBALS | 1 | 2 | CLK_EXT
MACROCELL | 14 | 10 | Z3_DATA<21>
ATTRIBUTES | 8553408 | 0
OUTPUTMC | 1 | 0 | 4
INPUTS | 5 | DQ_SWAP | DQ<5>.PIN | DQ<13>.PIN | LAN_SM_RST | LAN_SM_FSM_FFd7
INPUTMC | 3 | 12 | 17 | 3 | 8 | 8 | 9
INPUTP | 2 | 221 | 204
EQ | 5 |
Z3_DATA<21>.D = DQ_SWAP & DQ<13>.PIN
# !DQ_SWAP & DQ<5>.PIN;
Z3_DATA<21>.CLK = CLK_EXT; // GCK
Z3_DATA<21>.AP = LAN_SM_RST;
Z3_DATA<21>.CE = LAN_SM_FSM_FFd7;
GLOBALS | 1 | 2 | CLK_EXT
MACROCELL | 14 | 9 | Z3_DATA<22>
ATTRIBUTES | 8553408 | 0
OUTPUTMC | 1 | 1 | 9
INPUTS | 5 | DQ_SWAP | DQ<6>.PIN | DQ<14>.PIN | LAN_SM_RST | LAN_SM_FSM_FFd7
INPUTMC | 3 | 12 | 17 | 3 | 8 | 8 | 9
INPUTP | 2 | 227 | 236
EQ | 5 |
Z3_DATA<22>.D = DQ_SWAP & DQ<14>.PIN
# !DQ_SWAP & DQ<6>.PIN;
Z3_DATA<22>.CLK = CLK_EXT; // GCK
Z3_DATA<22>.AP = LAN_SM_RST;
Z3_DATA<22>.CE = LAN_SM_FSM_FFd7;
GLOBALS | 1 | 2 | CLK_EXT
MACROCELL | 14 | 8 | Z3_DATA<23>
ATTRIBUTES | 8553408 | 0
OUTPUTMC | 1 | 1 | 13
INPUTS | 5 | DQ_SWAP | DQ<7>.PIN | DQ<15>.PIN | LAN_SM_RST | LAN_SM_FSM_FFd7
INPUTMC | 3 | 12 | 17 | 3 | 8 | 8 | 9
INPUTP | 2 | 226 | 202
EQ | 5 |
Z3_DATA<23>.D = DQ_SWAP & DQ<15>.PIN
# !DQ_SWAP & DQ<7>.PIN;
Z3_DATA<23>.CLK = CLK_EXT; // GCK
Z3_DATA<23>.AP = LAN_SM_RST;
Z3_DATA<23>.CE = LAN_SM_FSM_FFd7;
GLOBALS | 1 | 2 | CLK_EXT
MACROCELL | 15 | 11 | Z3_DATA<24>
ATTRIBUTES | 8553408 | 0
OUTPUTMC | 1 | 1 | 16
INPUTS | 5 | DQ_SWAP | DQ<8>.PIN | DQ<0>.PIN | LAN_SM_RST | LAN_SM_FSM_FFd7
INPUTMC | 3 | 12 | 17 | 3 | 8 | 8 | 9
INPUTP | 2 | 231 | 217
EQ | 5 |
Z3_DATA<24>.D = DQ_SWAP & DQ<0>.PIN
# !DQ_SWAP & DQ<8>.PIN;
Z3_DATA<24>.CLK = CLK_EXT; // GCK
Z3_DATA<24>.AP = LAN_SM_RST;
Z3_DATA<24>.CE = LAN_SM_FSM_FFd7;
GLOBALS | 1 | 2 | CLK_EXT
MACROCELL | 15 | 8 | Z3_DATA<25>
ATTRIBUTES | 8553408 | 0
OUTPUTMC | 1 | 4 | 11
INPUTS | 5 | DQ_SWAP | DQ<9>.PIN | DQ<1>.PIN | LAN_SM_RST | LAN_SM_FSM_FFd7
INPUTMC | 3 | 12 | 17 | 3 | 8 | 8 | 9
INPUTP | 2 | 209 | 216
EQ | 5 |
Z3_DATA<25>.D = DQ_SWAP & DQ<1>.PIN
# !DQ_SWAP & DQ<9>.PIN;
Z3_DATA<25>.CLK = CLK_EXT; // GCK
Z3_DATA<25>.AP = LAN_SM_RST;
Z3_DATA<25>.CE = LAN_SM_FSM_FFd7;
GLOBALS | 1 | 2 | CLK_EXT
MACROCELL | 15 | 6 | Z3_DATA<26>
ATTRIBUTES | 8553408 | 0
OUTPUTMC | 1 | 4 | 13
INPUTS | 5 | DQ_SWAP | DQ<2>.PIN | DQ<10>.PIN | LAN_SM_RST | LAN_SM_FSM_FFd7
INPUTMC | 3 | 12 | 17 | 3 | 8 | 8 | 9
INPUTP | 2 | 220 | 234
EQ | 5 |
Z3_DATA<26>.D = DQ_SWAP & DQ<2>.PIN
# !DQ_SWAP & DQ<10>.PIN;
Z3_DATA<26>.CLK = CLK_EXT; // GCK
Z3_DATA<26>.AP = LAN_SM_RST;
Z3_DATA<26>.CE = LAN_SM_FSM_FFd7;
GLOBALS | 1 | 2 | CLK_EXT
MACROCELL | 15 | 4 | Z3_DATA<27>
ATTRIBUTES | 8553408 | 0
OUTPUTMC | 1 | 4 | 14
INPUTS | 5 | DQ_SWAP | DQ<3>.PIN | DQ<11>.PIN | LAN_SM_RST | LAN_SM_FSM_FFd7
INPUTMC | 3 | 12 | 17 | 3 | 8 | 8 | 9
INPUTP | 2 | 219 | 207
EQ | 5 |
Z3_DATA<27>.D = DQ_SWAP & DQ<3>.PIN
# !DQ_SWAP & DQ<11>.PIN;
Z3_DATA<27>.CLK = CLK_EXT; // GCK
Z3_DATA<27>.AP = LAN_SM_RST;
Z3_DATA<27>.CE = LAN_SM_FSM_FFd7;
GLOBALS | 1 | 2 | CLK_EXT
MACROCELL | 15 | 3 | Z3_DATA<28>
ATTRIBUTES | 8553408 | 0
OUTPUTMC | 1 | 4 | 16
INPUTS | 5 | DQ_SWAP | DQ<4>.PIN | DQ<12>.PIN | LAN_SM_RST | LAN_SM_FSM_FFd7
INPUTMC | 3 | 12 | 17 | 3 | 8 | 8 | 9
INPUTP | 2 | 225 | 235
EQ | 5 |
Z3_DATA<28>.D = DQ_SWAP & DQ<4>.PIN
# !DQ_SWAP & DQ<12>.PIN;
Z3_DATA<28>.CLK = CLK_EXT; // GCK
Z3_DATA<28>.AP = LAN_SM_RST;
Z3_DATA<28>.CE = LAN_SM_FSM_FFd7;
GLOBALS | 1 | 2 | CLK_EXT
MACROCELL | 14 | 7 | Z3_DATA<29>
ATTRIBUTES | 8553408 | 0
OUTPUTMC | 1 | 6 | 2
INPUTS | 5 | DQ_SWAP | DQ<5>.PIN | DQ<13>.PIN | LAN_SM_RST | LAN_SM_FSM_FFd7
INPUTMC | 3 | 12 | 17 | 3 | 8 | 8 | 9
INPUTP | 2 | 221 | 204
EQ | 5 |
Z3_DATA<29>.D = DQ_SWAP & DQ<5>.PIN
# !DQ_SWAP & DQ<13>.PIN;
Z3_DATA<29>.CLK = CLK_EXT; // GCK
Z3_DATA<29>.AP = LAN_SM_RST;
Z3_DATA<29>.CE = LAN_SM_FSM_FFd7;
GLOBALS | 1 | 2 | CLK_EXT
MACROCELL | 14 | 6 | Z3_DATA<30>
ATTRIBUTES | 8553408 | 0
OUTPUTMC | 1 | 6 | 4
INPUTS | 5 | DQ_SWAP | DQ<6>.PIN | DQ<14>.PIN | LAN_SM_RST | LAN_SM_FSM_FFd7
INPUTMC | 3 | 12 | 17 | 3 | 8 | 8 | 9
INPUTP | 2 | 227 | 236
EQ | 5 |
Z3_DATA<30>.D = DQ_SWAP & DQ<6>.PIN
# !DQ_SWAP & DQ<14>.PIN;
Z3_DATA<30>.CLK = CLK_EXT; // GCK
Z3_DATA<30>.AP = LAN_SM_RST;
Z3_DATA<30>.CE = LAN_SM_FSM_FFd7;
GLOBALS | 1 | 2 | CLK_EXT
MACROCELL | 14 | 5 | Z3_DATA<31>
ATTRIBUTES | 8553408 | 0
OUTPUTMC | 1 | 6 | 11
INPUTS | 5 | DQ_SWAP | DQ<7>.PIN | DQ<15>.PIN | LAN_SM_RST | LAN_SM_FSM_FFd7
INPUTMC | 3 | 12 | 17 | 3 | 8 | 8 | 9
INPUTP | 2 | 226 | 202
EQ | 5 |
Z3_DATA<31>.D = DQ_SWAP & DQ<7>.PIN
# !DQ_SWAP & DQ<15>.PIN;
Z3_DATA<31>.CLK = CLK_EXT; // GCK
Z3_DATA<31>.AP = LAN_SM_RST;
Z3_DATA<31>.CE = LAN_SM_FSM_FFd7;
GLOBALS | 1 | 2 | CLK_EXT
MACROCELL | 9 | 16 | DQ_10_IOBUFE
ATTRIBUTES | 265986 | 0
OUTPUTMC | 1 | 9 | 15
INPUTS | 8 | RESET | LAN_D_INIT<8> | DQ_DATA<10> | DQ_10_IOBUFE/DQ_10_IOBUFE_TRST | LDS | D<2>.PIN | LAN_SM_FSM_FFd12 | $OpTx$FX_DC$11
INPUTMC | 5 | 4 | 3 | 9 | 15 | 3 | 14 | 9 | 6 | 12 | 4
INPUTP | 3 | 263 | 157 | 71
EXPORTS | 1 | 9 | 15
EQ | 5 |
DQ<10> = RESET & DQ_DATA<10>
# !RESET & LAN_D_INIT<8>;
DQ<10>.OE = DQ_10_IOBUFE/DQ_10_IOBUFE_TRST;
DQ_10_IOBUFE.EXP = !LDS & D<2>.PIN & LAN_SM_FSM_FFd12 &
!$OpTx$FX_DC$11
MACROCELL | 11 | 9 | DQ_11_IOBUFE
ATTRIBUTES | 265986 | 0
INPUTS | 4 | RESET | LAN_D_INIT<8> | DQ_DATA<11> | DQ_10_IOBUFE/DQ_10_IOBUFE_TRST
INPUTMC | 3 | 4 | 3 | 8 | 17 | 3 | 14
INPUTP | 1 | 263
EQ | 3 |
DQ<11> = RESET & DQ_DATA<11>
# !RESET & LAN_D_INIT<8>;
DQ<11>.OE = DQ_10_IOBUFE/DQ_10_IOBUFE_TRST;
MACROCELL | 9 | 1 | DQ_1_IOBUFE
ATTRIBUTES | 265986 | 0
INPUTS | 4 | RESET | LAN_D_INIT<1> | DQ_DATA<1> | DQ_10_IOBUFE/DQ_10_IOBUFE_TRST
INPUTMC | 3 | 4 | 5 | 6 | 17 | 3 | 14
INPUTP | 1 | 263
EQ | 3 |
DQ<1> = RESET & DQ_DATA<1>
# !RESET & LAN_D_INIT<1>;
DQ<1>.OE = DQ_10_IOBUFE/DQ_10_IOBUFE_TRST;
MACROCELL | 9 | 9 | DQ_4_IOBUFE
ATTRIBUTES | 265986 | 0
INPUTS | 4 | RESET | LAN_D_INIT<1> | DQ_DATA<4> | DQ_10_IOBUFE/DQ_10_IOBUFE_TRST
INPUTMC | 3 | 4 | 5 | 4 | 15 | 3 | 14
INPUTP | 1 | 263
EQ | 3 |
DQ<4> = RESET & DQ_DATA<4>
# !RESET & LAN_D_INIT<1>;
DQ<4>.OE = DQ_10_IOBUFE/DQ_10_IOBUFE_TRST;
MACROCELL | 9 | 13 | DQ_8_IOBUFE
ATTRIBUTES | 265986 | 0
OUTPUTMC | 1 | 9 | 14
INPUTS | 8 | RESET | LAN_D_INIT<8> | DQ_DATA<8> | DQ_10_IOBUFE/DQ_10_IOBUFE_TRST | LDS | D<2>.PIN | LAN_SM_FSM_FFd12 | $OpTx$FX_DC$10
INPUTMC | 5 | 4 | 3 | 9 | 12 | 3 | 14 | 9 | 6 | 8 | 1
INPUTP | 3 | 263 | 157 | 71
EXPORTS | 1 | 9 | 14
EQ | 5 |
DQ<8> = RESET & DQ_DATA<8>
# !RESET & LAN_D_INIT<8>;
DQ<8>.OE = DQ_10_IOBUFE/DQ_10_IOBUFE_TRST;
DQ_8_IOBUFE.EXP = !LDS & D<2>.PIN & LAN_SM_FSM_FFd12 &
!$OpTx$FX_DC$10
MACROCELL | 11 | 11 | DQ_9_IOBUFE
ATTRIBUTES | 265986 | 0
INPUTS | 4 | RESET | LAN_D_INIT<1> | DQ_DATA<9> | DQ_10_IOBUFE/DQ_10_IOBUFE_TRST
INPUTMC | 3 | 4 | 5 | 11 | 15 | 3 | 14
INPUTP | 1 | 263
EQ | 3 |
DQ<9> = RESET & DQ_DATA<9>
# !RESET & LAN_D_INIT<1>;
DQ<9>.OE = DQ_10_IOBUFE/DQ_10_IOBUFE_TRST;
MACROCELL | 3 | 1 | D_0_IOBUFE
ATTRIBUTES | 265986 | 0
INPUTS | 3 | Z3_DATA<16> | Z3_DATA<8>/Z3_DATA<8>_TRST | D_9_IOBUFE/D_9_IOBUFE_TRST
INPUTMC | 3 | 15 | 16 | 8 | 0 | 14 | 17
EQ | 2 |
!D<0> = !Z3_DATA<16> & Z3_DATA<8>/Z3_DATA<8>_TRST;
D<0>.OE = D_9_IOBUFE/D_9_IOBUFE_TRST;
MACROCELL | 4 | 13 | D_10_IOBUFE
ATTRIBUTES | 265986 | 0
INPUTS | 4 | D_OUT<2> | Z3_DATA<8>/Z3_DATA<8>_TRST | Z3_DATA<26> | D_9_IOBUFE/D_9_IOBUFE_TRST
INPUTMC | 4 | 14 | 3 | 8 | 0 | 15 | 6 | 14 | 17
EQ | 3 |
D<10> = Z3_DATA<26> & Z3_DATA<8>/Z3_DATA<8>_TRST
# D_OUT<2> & !Z3_DATA<8>/Z3_DATA<8>_TRST;
D<10>.OE = D_9_IOBUFE/D_9_IOBUFE_TRST;
MACROCELL | 4 | 14 | D_11_IOBUFE
ATTRIBUTES | 265986 | 0
OUTPUTMC | 1 | 4 | 15
INPUTS | 8 | D_OUT<3> | Z3_DATA<8>/Z3_DATA<8>_TRST | Z3_DATA<27> | D_9_IOBUFE/D_9_IOBUFE_TRST | LDS | D<4>.PIN | LAN_SM_FSM_FFd12 | $OpTx$FX_DC$10
INPUTMC | 6 | 14 | 1 | 8 | 0 | 15 | 4 | 14 | 17 | 9 | 6 | 8 | 1
INPUTP | 2 | 157 | 38
EXPORTS | 1 | 4 | 15
EQ | 5 |
D<11> = Z3_DATA<27> & Z3_DATA<8>/Z3_DATA<8>_TRST
# D_OUT<3> & !Z3_DATA<8>/Z3_DATA<8>_TRST;
D<11>.OE = D_9_IOBUFE/D_9_IOBUFE_TRST;
D_11_IOBUFE.EXP = !LDS & D<4>.PIN & LAN_SM_FSM_FFd12 &
!$OpTx$FX_DC$10
MACROCELL | 4 | 16 | D_12_IOBUFE
ATTRIBUTES | 265986 | 0
OUTPUTMC | 1 | 4 | 17
INPUTS | 8 | D_OUT<4> | Z3_DATA<8>/Z3_DATA<8>_TRST | Z3_DATA<28> | D_9_IOBUFE/D_9_IOBUFE_TRST | LDS | D<4>.PIN | LAN_SM_FSM_FFd12 | $OpTx$FX_DC$11
INPUTMC | 6 | 10 | 17 | 8 | 0 | 15 | 3 | 14 | 17 | 9 | 6 | 12 | 4
INPUTP | 2 | 157 | 38
EXPORTS | 1 | 4 | 17
EQ | 5 |
D<12> = Z3_DATA<28> & Z3_DATA<8>/Z3_DATA<8>_TRST
# D_OUT<4> & !Z3_DATA<8>/Z3_DATA<8>_TRST;
D<12>.OE = D_9_IOBUFE/D_9_IOBUFE_TRST;
D_12_IOBUFE.EXP = !LDS & D<4>.PIN & LAN_SM_FSM_FFd12 &
!$OpTx$FX_DC$11
MACROCELL | 6 | 2 | D_13_IOBUFE
ATTRIBUTES | 265986 | 0
INPUTS | 4 | D_OUT<5> | Z3_DATA<8>/Z3_DATA<8>_TRST | Z3_DATA<29> | D_9_IOBUFE/D_9_IOBUFE_TRST
INPUTMC | 4 | 10 | 15 | 8 | 0 | 14 | 7 | 14 | 17
EQ | 3 |
D<13> = Z3_DATA<29> & Z3_DATA<8>/Z3_DATA<8>_TRST
# D_OUT<5> & !Z3_DATA<8>/Z3_DATA<8>_TRST;
D<13>.OE = D_9_IOBUFE/D_9_IOBUFE_TRST;
MACROCELL | 6 | 4 | D_14_IOBUFE
ATTRIBUTES | 265986 | 0
INPUTS | 4 | D_OUT<6> | Z3_DATA<8>/Z3_DATA<8>_TRST | Z3_DATA<30> | D_9_IOBUFE/D_9_IOBUFE_TRST
INPUTMC | 4 | 14 | 12 | 8 | 0 | 14 | 6 | 14 | 17
EQ | 3 |
D<14> = Z3_DATA<30> & Z3_DATA<8>/Z3_DATA<8>_TRST
# D_OUT<6> & !Z3_DATA<8>/Z3_DATA<8>_TRST;
D<14>.OE = D_9_IOBUFE/D_9_IOBUFE_TRST;
MACROCELL | 6 | 11 | D_15_IOBUFE
ATTRIBUTES | 265986 | 0
INPUTS | 4 | D_OUT<7> | Z3_DATA<8>/Z3_DATA<8>_TRST | Z3_DATA<31> | D_9_IOBUFE/D_9_IOBUFE_TRST
INPUTMC | 4 | 14 | 0 | 8 | 0 | 14 | 5 | 14 | 17
EQ | 3 |
D<15> = Z3_DATA<31> & Z3_DATA<8>/Z3_DATA<8>_TRST
# D_OUT<7> & !Z3_DATA<8>/Z3_DATA<8>_TRST;
D<15>.OE = D_9_IOBUFE/D_9_IOBUFE_TRST;
MACROCELL | 1 | 14 | D_1_IOBUFE
ATTRIBUTES | 265986 | 0
INPUTS | 3 | Z3_DATA<17> | Z3_DATA<8>/Z3_DATA<8>_TRST | D_9_IOBUFE/D_9_IOBUFE_TRST
INPUTMC | 3 | 15 | 15 | 8 | 0 | 14 | 17
EQ | 2 |
!D<1> = !Z3_DATA<17> & Z3_DATA<8>/Z3_DATA<8>_TRST;
D<1>.OE = D_9_IOBUFE/D_9_IOBUFE_TRST;
MACROCELL | 4 | 9 | D_2_IOBUFE
ATTRIBUTES | 265986 | 0
INPUTS | 3 | Z3_DATA<18> | Z3_DATA<8>/Z3_DATA<8>_TRST | D_9_IOBUFE/D_9_IOBUFE_TRST
INPUTMC | 3 | 15 | 14 | 8 | 0 | 14 | 17
EQ | 2 |
!D<2> = !Z3_DATA<18> & Z3_DATA<8>/Z3_DATA<8>_TRST;
D<2>.OE = D_9_IOBUFE/D_9_IOBUFE_TRST;
MACROCELL | 1 | 11 | D_3_IOBUFE
ATTRIBUTES | 265986 | 0
INPUTS | 3 | Z3_DATA<19> | Z3_DATA<8>/Z3_DATA<8>_TRST | D_9_IOBUFE/D_9_IOBUFE_TRST
INPUTMC | 3 | 15 | 13 | 8 | 0 | 14 | 17
EQ | 2 |
!D<3> = !Z3_DATA<19> & Z3_DATA<8>/Z3_DATA<8>_TRST;
D<3>.OE = D_9_IOBUFE/D_9_IOBUFE_TRST;
MACROCELL | 0 | 5 | D_4_IOBUFE
ATTRIBUTES | 265986 | 0
INPUTS | 3 | Z3_DATA<20> | Z3_DATA<8>/Z3_DATA<8>_TRST | D_9_IOBUFE/D_9_IOBUFE_TRST
INPUTMC | 3 | 15 | 12 | 8 | 0 | 14 | 17
EQ | 2 |
!D<4> = !Z3_DATA<20> & Z3_DATA<8>/Z3_DATA<8>_TRST;
D<4>.OE = D_9_IOBUFE/D_9_IOBUFE_TRST;
MACROCELL | 0 | 4 | D_5_IOBUFE
ATTRIBUTES | 265986 | 0
INPUTS | 3 | Z3_DATA<21> | Z3_DATA<8>/Z3_DATA<8>_TRST | D_9_IOBUFE/D_9_IOBUFE_TRST
INPUTMC | 3 | 14 | 10 | 8 | 0 | 14 | 17
EQ | 2 |
!D<5> = !Z3_DATA<21> & Z3_DATA<8>/Z3_DATA<8>_TRST;
D<5>.OE = D_9_IOBUFE/D_9_IOBUFE_TRST;
MACROCELL | 1 | 9 | D_6_IOBUFE
ATTRIBUTES | 265986 | 0
INPUTS | 3 | Z3_DATA<22> | Z3_DATA<8>/Z3_DATA<8>_TRST | D_9_IOBUFE/D_9_IOBUFE_TRST
INPUTMC | 3 | 14 | 9 | 8 | 0 | 14 | 17
EQ | 2 |
!D<6> = !Z3_DATA<22> & Z3_DATA<8>/Z3_DATA<8>_TRST;
D<6>.OE = D_9_IOBUFE/D_9_IOBUFE_TRST;
MACROCELL | 1 | 13 | D_7_IOBUFE
ATTRIBUTES | 265986 | 0
INPUTS | 3 | Z3_DATA<23> | Z3_DATA<8>/Z3_DATA<8>_TRST | D_9_IOBUFE/D_9_IOBUFE_TRST
INPUTMC | 3 | 14 | 8 | 8 | 0 | 14 | 17
EQ | 2 |
!D<7> = !Z3_DATA<23> & Z3_DATA<8>/Z3_DATA<8>_TRST;
D<7>.OE = D_9_IOBUFE/D_9_IOBUFE_TRST;
MACROCELL | 1 | 16 | D_8_IOBUFE
ATTRIBUTES | 265986 | 0
INPUTS | 4 | D_OUT<0> | Z3_DATA<8>/Z3_DATA<8>_TRST | Z3_DATA<24> | D_9_IOBUFE/D_9_IOBUFE_TRST
INPUTMC | 4 | 14 | 2 | 8 | 0 | 15 | 11 | 14 | 17
EQ | 3 |
D<8> = Z3_DATA<24> & Z3_DATA<8>/Z3_DATA<8>_TRST
# D_OUT<0> & !Z3_DATA<8>/Z3_DATA<8>_TRST;
D<8>.OE = D_9_IOBUFE/D_9_IOBUFE_TRST;
MACROCELL | 4 | 11 | D_9_IOBUFE
ATTRIBUTES | 265986 | 0
INPUTS | 4 | D_OUT<1> | Z3_DATA<8>/Z3_DATA<8>_TRST | Z3_DATA<25> | D_9_IOBUFE/D_9_IOBUFE_TRST
INPUTMC | 4 | 14 | 15 | 8 | 0 | 15 | 8 | 14 | 17
EQ | 3 |
D<9> = Z3_DATA<25> & Z3_DATA<8>/Z3_DATA<8>_TRST
# D_OUT<1> & !Z3_DATA<8>/Z3_DATA<8>_TRST;
D<9>.OE = D_9_IOBUFE/D_9_IOBUFE_TRST;
MACROCELL | 9 | 2 | DQ_0_IOBUFE
ATTRIBUTES | 265986 | 0
INPUTS | 3 | RESET | DQ_DATA<0> | DQ_10_IOBUFE/DQ_10_IOBUFE_TRST
INPUTMC | 2 | 9 | 17 | 3 | 14
INPUTP | 1 | 263
EQ | 2 |
DQ<0> = RESET & DQ_DATA<0>;
DQ<0>.OE = DQ_10_IOBUFE/DQ_10_IOBUFE_TRST;
MACROCELL | 7 | 1 | DQ_12_IOBUFE
ATTRIBUTES | 265986 | 0
INPUTS | 3 | RESET | DQ_DATA<12> | DQ_10_IOBUFE/DQ_10_IOBUFE_TRST
INPUTMC | 2 | 4 | 17 | 3 | 14
INPUTP | 1 | 263
EQ | 2 |
DQ<12> = RESET & DQ_DATA<12>;
DQ<12>.OE = DQ_10_IOBUFE/DQ_10_IOBUFE_TRST;
MACROCELL | 11 | 7 | DQ_13_IOBUFE
ATTRIBUTES | 265986 | 0
INPUTS | 3 | RESET | DQ_DATA<13> | DQ_10_IOBUFE/DQ_10_IOBUFE_TRST
INPUTMC | 2 | 7 | 17 | 3 | 14
INPUTP | 1 | 263
EQ | 2 |
DQ<13> = RESET & DQ_DATA<13>;
DQ<13>.OE = DQ_10_IOBUFE/DQ_10_IOBUFE_TRST;
MACROCELL | 7 | 2 | DQ_14_IOBUFE
ATTRIBUTES | 265986 | 0
INPUTS | 3 | RESET | DQ_DATA<14> | DQ_10_IOBUFE/DQ_10_IOBUFE_TRST
INPUTMC | 2 | 7 | 16 | 3 | 14
INPUTP | 1 | 263
EQ | 2 |
DQ<14> = RESET & DQ_DATA<14>;
DQ<14>.OE = DQ_10_IOBUFE/DQ_10_IOBUFE_TRST;
MACROCELL | 11 | 4 | DQ_15_IOBUFE
ATTRIBUTES | 265986 | 0
INPUTS | 3 | RESET | DQ_DATA<15> | DQ_10_IOBUFE/DQ_10_IOBUFE_TRST
INPUTMC | 2 | 3 | 17 | 3 | 14
INPUTP | 1 | 263
EQ | 2 |
DQ<15> = RESET & DQ_DATA<15>;
DQ<15>.OE = DQ_10_IOBUFE/DQ_10_IOBUFE_TRST;
MACROCELL | 9 | 5 | DQ_2_IOBUFE
ATTRIBUTES | 265986 | 0
INPUTS | 3 | RESET | DQ_DATA<2> | DQ_10_IOBUFE/DQ_10_IOBUFE_TRST
INPUTMC | 2 | 9 | 14 | 3 | 14
INPUTP | 1 | 263
EQ | 2 |
DQ<2> = RESET & DQ_DATA<2>;
DQ<2>.OE = DQ_10_IOBUFE/DQ_10_IOBUFE_TRST;
MACROCELL | 9 | 4 | DQ_3_IOBUFE
ATTRIBUTES | 265986 | 0
INPUTS | 3 | RESET | DQ_DATA<3> | DQ_10_IOBUFE/DQ_10_IOBUFE_TRST
INPUTMC | 2 | 11 | 17 | 3 | 14
INPUTP | 1 | 263
EQ | 2 |
DQ<3> = RESET & DQ_DATA<3>;
DQ<3>.OE = DQ_10_IOBUFE/DQ_10_IOBUFE_TRST;
MACROCELL | 9 | 7 | DQ_5_IOBUFE
ATTRIBUTES | 265986 | 0
INPUTS | 3 | RESET | DQ_DATA<5> | DQ_10_IOBUFE/DQ_10_IOBUFE_TRST
INPUTMC | 2 | 7 | 15 | 3 | 14
INPUTP | 1 | 263
EQ | 2 |
DQ<5> = RESET & DQ_DATA<5>;
DQ<5>.OE = DQ_10_IOBUFE/DQ_10_IOBUFE_TRST;
MACROCELL | 9 | 11 | DQ_6_IOBUFE
ATTRIBUTES | 265986 | 0
OUTPUTMC | 1 | 9 | 12
INPUTS | 7 | RESET | DQ_DATA<6> | DQ_10_IOBUFE/DQ_10_IOBUFE_TRST | LDS | D<0>.PIN | LAN_SM_FSM_FFd12 | $OpTx$FX_DC$11
INPUTMC | 4 | 7 | 14 | 3 | 14 | 9 | 6 | 12 | 4
INPUTP | 3 | 263 | 157 | 4
EXPORTS | 1 | 9 | 12
EQ | 4 |
DQ<6> = RESET & DQ_DATA<6>;
DQ<6>.OE = DQ_10_IOBUFE/DQ_10_IOBUFE_TRST;
DQ_6_IOBUFE.EXP = !LDS & D<0>.PIN & LAN_SM_FSM_FFd12 &
!$OpTx$FX_DC$11
MACROCELL | 9 | 10 | DQ_7_IOBUFE
ATTRIBUTES | 265986 | 0
INPUTS | 3 | RESET | DQ_DATA<7> | DQ_10_IOBUFE/DQ_10_IOBUFE_TRST
INPUTMC | 2 | 11 | 16 | 3 | 14
INPUTP | 1 | 263
EQ | 2 |
DQ<7> = RESET & DQ_DATA<7>;
DQ<7>.OE = DQ_10_IOBUFE/DQ_10_IOBUFE_TRST;
MACROCELL | 12 | 17 | DQ_SWAP
ATTRIBUTES | 8520608 | 0
OUTPUTMC | 36 | 8 | 10 | 15 | 5 | 15 | 2 | 15 | 1 | 14 | 16 | 14 | 14 | 14 | 13 | 8 | 13 | 8 | 16 | 10 | 2 | 10 | 4 | 10 | 9 | 10 | 10 | 12 | 7 | 15 | 10 | 15 | 7 | 15 | 16 | 15 | 15 | 15 | 14 | 15 | 13 | 15 | 12 | 14 | 10 | 14 | 9 | 14 | 8 | 15 | 11 | 15 | 8 | 15 | 6 | 15 | 4 | 15 | 3 | 14 | 7 | 14 | 6 | 14 | 5 | 8 | 1 | 12 | 8 | 12 | 4 | 12 | 9
INPUTS | 15 | Z3 | D<12>.PIN | LAN_BASEADR<12> | SHUT_UP | A<13>.PIN | A<14>.PIN | $OpTx$FX_DC$46 | $OpTx$FX_DC$45 | $OpTx$FX_DC$44 | $OpTx$FX_DC$43 | $OpTx$FX_DC$47 | $OpTx$INV$2 | $OpTx$INV$1 | FCS | Z3_ADR_1/Z3_ADR_1_SETF
INPUTMC | 10 | 10 | 7 | 1 | 0 | 0 | 17 | 6 | 7 | 13 | 9 | 13 | 11 | 0 | 15 | 5 | 17 | 13 | 0 | 7 | 0
INPUTP | 5 | 151 | 78 | 123 | 125 | 147
EQ | 10 |
!DQ_SWAP.D = Z3 & D<12>.PIN & LAN_BASEADR<12> & !SHUT_UP &
A<13>.PIN & A<14>.PIN & !$OpTx$FX_DC$46 & !$OpTx$FX_DC$45 &
!$OpTx$FX_DC$44 & !$OpTx$FX_DC$43 & !$OpTx$FX_DC$47 & !$OpTx$INV$2 &
!$OpTx$INV$1
# Z3 & !D<12>.PIN & !LAN_BASEADR<12> & !SHUT_UP &
A<13>.PIN & A<14>.PIN & !$OpTx$FX_DC$46 & !$OpTx$FX_DC$45 &
!$OpTx$FX_DC$44 & !$OpTx$FX_DC$43 & !$OpTx$FX_DC$47 & !$OpTx$INV$2 &
!$OpTx$INV$1;
DQ_SWAP.CLK = !FCS;
DQ_SWAP.AP = !Z3_ADR_1/Z3_ADR_1_SETF;
MACROCELL | 8 | 9 | LAN_SM_FSM_FFd7
ATTRIBUTES | 8553232 | 0
OUTPUTMC | 21 | 15 | 16 | 15 | 15 | 15 | 14 | 15 | 13 | 15 | 12 | 14 | 10 | 14 | 9 | 14 | 8 | 15 | 11 | 15 | 8 | 15 | 6 | 15 | 4 | 15 | 3 | 14 | 7 | 14 | 6 | 14 | 5 | 8 | 9 | 8 | 2 | 15 | 0 | 15 | 17 | 0 | 12
INPUTS | 4 | LAN_SM_FSM_FFd11 | LAN_SM_FSM_FFd7 | $OpTx$FX_DC$7 | LAN_SM_RST
INPUTMC | 4 | 8 | 12 | 8 | 9 | 12 | 3 | 3 | 8
EQ | 4 |
LAN_SM_FSM_FFd7.D = LAN_SM_FSM_FFd11
# LAN_SM_FSM_FFd7 & $OpTx$FX_DC$7;
LAN_SM_FSM_FFd7.CLK = CLK_EXT; // GCK
LAN_SM_FSM_FFd7.AR = LAN_SM_RST;
GLOBALS | 1 | 2 | CLK_EXT
MACROCELL | 8 | 3 | LAN_SM_FSM_FFd5
ATTRIBUTES | 8553232 | 0
OUTPUTMC | 19 | 8 | 10 | 15 | 5 | 15 | 2 | 15 | 1 | 14 | 16 | 14 | 14 | 14 | 13 | 8 | 13 | 8 | 16 | 10 | 2 | 10 | 4 | 10 | 9 | 10 | 10 | 12 | 7 | 15 | 10 | 15 | 7 | 8 | 3 | 15 | 0 | 0 | 12
INPUTS | 3 | LAN_SM_FSM_FFd5 | LAN_SM_FSM_FFd10 | LAN_SM_RST
INPUTMC | 3 | 8 | 3 | 8 | 14 | 3 | 8
EQ | 3 |
!LAN_SM_FSM_FFd5.D = !LAN_SM_FSM_FFd5 & !LAN_SM_FSM_FFd10;
LAN_SM_FSM_FFd5.CLK = CLK_EXT; // GCK
LAN_SM_FSM_FFd5.AR = LAN_SM_RST;
GLOBALS | 1 | 2 | CLK_EXT
MACROCELL | 8 | 14 | LAN_SM_FSM_FFd10
ATTRIBUTES | 8553232 | 0
OUTPUTMC | 6 | 8 | 3 | 8 | 15 | 15 | 0 | 15 | 17 | 0 | 12 | 15 | 16
INPUTS | 6 | LAN_SM_FSM_FFd6 | RW | UDS | LDS | LAN_SM_FSM_FFd12 | LAN_SM_RST
INPUTMC | 3 | 8 | 2 | 9 | 6 | 3 | 8
INPUTP | 3 | 158 | 155 | 157
EQ | 4 |
LAN_SM_FSM_FFd10.D = LAN_SM_FSM_FFd6
# RW & UDS & LDS & LAN_SM_FSM_FFd12;
LAN_SM_FSM_FFd10.CLK = CLK_EXT; // GCK
LAN_SM_FSM_FFd10.AR = LAN_SM_RST;
GLOBALS | 1 | 2 | CLK_EXT
MACROCELL | 8 | 11 | LAN_SM_FSM_FFd3
ATTRIBUTES | 8553232 | 0
OUTPUTMC | 6 | 8 | 11 | 8 | 8 | 15 | 0 | 15 | 17 | 8 | 5 | 15 | 16
INPUTS | 4 | LAN_SM_FSM_FFd4 | LAN_SM_FSM_FFd3 | $OpTx$FX_DC$7 | LAN_SM_RST
INPUTMC | 4 | 12 | 5 | 8 | 11 | 12 | 3 | 3 | 8
EQ | 4 |
LAN_SM_FSM_FFd3.D = LAN_SM_FSM_FFd4
# LAN_SM_FSM_FFd3 & $OpTx$FX_DC$7;
LAN_SM_FSM_FFd3.CLK = CLK_EXT; // GCK
LAN_SM_FSM_FFd3.AR = LAN_SM_RST;
GLOBALS | 1 | 2 | CLK_EXT
MACROCELL | 8 | 8 | LAN_SM_FSM_FFd8
ATTRIBUTES | 8553232 | 0
OUTPUTMC | 7 | 12 | 6 | 12 | 15 | 12 | 14 | 15 | 17 | 0 | 12 | 15 | 0 | 15 | 16
INPUTS | 7 | LAN_SM_FSM_FFd3 | $OpTx$FX_DC$7 | RW | UDS | LDS | LAN_SM_FSM_FFd12 | LAN_SM_RST
INPUTMC | 4 | 8 | 11 | 12 | 3 | 9 | 6 | 3 | 8
INPUTP | 3 | 158 | 155 | 157
EQ | 4 |
LAN_SM_FSM_FFd8.D = LAN_SM_FSM_FFd3 & !$OpTx$FX_DC$7
# !RW & UDS & LDS & LAN_SM_FSM_FFd12;
LAN_SM_FSM_FFd8.CLK = CLK_EXT; // GCK
LAN_SM_FSM_FFd8.AR = LAN_SM_RST;
GLOBALS | 1 | 2 | CLK_EXT
MACROCELL | 12 | 6 | LAN_SM_FSM_FFd2
ATTRIBUTES | 8553232 | 0
OUTPUTMC | 5 | 6 | 6 | 15 | 0 | 15 | 17 | 0 | 12 | 15 | 16
INPUTS | 2 | LAN_SM_FSM_FFd8 | LAN_SM_RST
INPUTMC | 2 | 8 | 8 | 3 | 8
EQ | 3 |
LAN_SM_FSM_FFd2.D = LAN_SM_FSM_FFd8;
LAN_SM_FSM_FFd2.CLK = CLK_EXT; // GCK
LAN_SM_FSM_FFd2.AR = LAN_SM_RST;
GLOBALS | 1 | 2 | CLK_EXT
MACROCELL | 8 | 2 | LAN_SM_FSM_FFd6
ATTRIBUTES | 8553232 | 0
OUTPUTMC | 6 | 8 | 14 | 8 | 15 | 15 | 17 | 0 | 12 | 15 | 0 | 15 | 16
INPUTS | 3 | LAN_SM_FSM_FFd7 | $OpTx$FX_DC$7 | LAN_SM_RST
INPUTMC | 3 | 8 | 9 | 12 | 3 | 3 | 8
EQ | 3 |
LAN_SM_FSM_FFd6.D = LAN_SM_FSM_FFd7 & !$OpTx$FX_DC$7;
LAN_SM_FSM_FFd6.CLK = CLK_EXT; // GCK
LAN_SM_FSM_FFd6.AR = LAN_SM_RST;
GLOBALS | 1 | 2 | CLK_EXT
MACROCELL | 8 | 7 | LAN_SM_FSM_FFd9
ATTRIBUTES | 8553232 | 0
OUTPUTMC | 4 | 12 | 5 | 12 | 15 | 12 | 14 | 0 | 12
INPUTS | 5 | RW | LDS | LAN_SM_FSM_FFd12 | UDS | LAN_SM_RST
INPUTMC | 2 | 9 | 6 | 3 | 8
INPUTP | 3 | 158 | 157 | 155
EQ | 4 |
LAN_SM_FSM_FFd9.D = !RW & !UDS & LAN_SM_FSM_FFd12
# !RW & !LDS & LAN_SM_FSM_FFd12;
LAN_SM_FSM_FFd9.CLK = CLK_EXT; // GCK
LAN_SM_FSM_FFd9.AR = LAN_SM_RST;
GLOBALS | 1 | 2 | CLK_EXT
MACROCELL | 6 | 6 | LAN_SM_FSM_FFd1
ATTRIBUTES | 8553232 | 0
OUTPUTMC | 3 | 6 | 6 | 15 | 0 | 0 | 12
INPUTS | 3 | LAN_SM_FSM_FFd2 | LAN_SM_FSM_FFd1 | LAN_SM_RST
INPUTMC | 3 | 12 | 6 | 6 | 6 | 3 | 8
EQ | 3 |
!LAN_SM_FSM_FFd1.D = !LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1;
LAN_SM_FSM_FFd1.CLK = CLK_EXT; // GCK
LAN_SM_FSM_FFd1.AR = LAN_SM_RST;
GLOBALS | 1 | 2 | CLK_EXT
MACROCELL | 8 | 12 | LAN_SM_FSM_FFd11
ATTRIBUTES | 8553232 | 0
OUTPUTMC | 3 | 8 | 9 | 8 | 15 | 0 | 12
INPUTS | 5 | RW | LDS | LAN_SM_FSM_FFd12 | UDS | LAN_SM_RST
INPUTMC | 2 | 9 | 6 | 3 | 8
INPUTP | 3 | 158 | 157 | 155
EQ | 4 |
LAN_SM_FSM_FFd11.D = RW & !UDS & LAN_SM_FSM_FFd12
# RW & !LDS & LAN_SM_FSM_FFd12;
LAN_SM_FSM_FFd11.CLK = CLK_EXT; // GCK
LAN_SM_FSM_FFd11.AR = LAN_SM_RST;
GLOBALS | 1 | 2 | CLK_EXT
MACROCELL | 12 | 5 | LAN_SM_FSM_FFd4
ATTRIBUTES | 8553232 | 0
OUTPUTMC | 2 | 8 | 11 | 0 | 12
INPUTS | 2 | LAN_SM_FSM_FFd9 | LAN_SM_RST
INPUTMC | 2 | 8 | 7 | 3 | 8
EQ | 3 |
LAN_SM_FSM_FFd4.D = LAN_SM_FSM_FFd9;
LAN_SM_FSM_FFd4.CLK = CLK_EXT; // GCK
LAN_SM_FSM_FFd4.AR = LAN_SM_RST;
GLOBALS | 1 | 2 | CLK_EXT
MACROCELL | 12 | 10 | Z3_ADR<2>
ATTRIBUTES | 8520608 | 0
OUTPUTMC | 25 | 14 | 4 | 10 | 14 | 10 | 12 | 10 | 8 | 10 | 7 | 10 | 6 | 1 | 17 | 1 | 15 | 1 | 12 | 1 | 10 | 1 | 8 | 1 | 6 | 1 | 3 | 10 | 5 | 10 | 3 | 10 | 1 | 10 | 0 | 1 | 0 | 14 | 2 | 14 | 15 | 14 | 3 | 10 | 17 | 10 | 15 | 14 | 12 | 3 | 7
INPUTS | 3 | A<4> | FCS | Z3_ADR_1/Z3_ADR_1_SETF
INPUTMC | 1 | 7 | 0
INPUTP | 2 | 97 | 147
EQ | 3 |
Z3_ADR<2>.D = A<4>;
Z3_ADR<2>.CLK = !FCS;
Z3_ADR<2>.AP = !Z3_ADR_1/Z3_ADR_1_SETF;
MACROCELL | 6 | 8 | Z3_ADR_1
ATTRIBUTES | 8520608 | 0
OUTPUTMC | 26 | 10 | 14 | 10 | 12 | 10 | 8 | 10 | 7 | 10 | 6 | 1 | 17 | 1 | 15 | 1 | 12 | 1 | 10 | 1 | 8 | 1 | 6 | 1 | 3 | 10 | 5 | 10 | 3 | 10 | 1 | 10 | 0 | 1 | 0 | 14 | 2 | 14 | 15 | 14 | 3 | 14 | 1 | 10 | 17 | 10 | 15 | 14 | 12 | 14 | 0 | 3 | 11
INPUTS | 3 | A<3> | FCS | Z3_ADR_1/Z3_ADR_1_SETF
INPUTMC | 1 | 7 | 0
INPUTP | 2 | 99 | 147
EQ | 3 |
Z3_ADR_1.D = A<3>;
Z3_ADR_1.CLK = !FCS;
Z3_ADR_1.AP = !Z3_ADR_1/Z3_ADR_1_SETF;
MACROCELL | 6 | 9 | Z3_ADR_0
ATTRIBUTES | 8520608 | 0
OUTPUTMC | 25 | 14 | 4 | 10 | 14 | 10 | 12 | 10 | 8 | 10 | 7 | 10 | 6 | 1 | 17 | 1 | 15 | 1 | 12 | 1 | 10 | 1 | 8 | 1 | 6 | 1 | 3 | 10 | 5 | 10 | 3 | 10 | 1 | 10 | 0 | 1 | 0 | 14 | 2 | 14 | 15 | 14 | 3 | 10 | 17 | 10 | 15 | 14 | 12 | 3 | 4
INPUTS | 3 | A<2> | FCS | Z3_ADR_1/Z3_ADR_1_SETF
INPUTMC | 1 | 7 | 0
INPUTP | 2 | 101 | 147
EQ | 3 |
Z3_ADR_0.D = A<2>;
Z3_ADR_0.CLK = !FCS;
Z3_ADR_0.AP = !Z3_ADR_1/Z3_ADR_1_SETF;
MACROCELL | 6 | 14 | Z3_ADR<6>
ATTRIBUTES | 8520608 | 0
OUTPUTMC | 23 | 14 | 4 | 10 | 14 | 10 | 12 | 10 | 8 | 10 | 7 | 10 | 6 | 1 | 17 | 1 | 15 | 1 | 12 | 1 | 10 | 1 | 8 | 1 | 6 | 1 | 3 | 10 | 5 | 10 | 3 | 10 | 1 | 10 | 0 | 1 | 0 | 10 | 17 | 10 | 15 | 14 | 12 | 14 | 0 | 1 | 2
INPUTS | 3 | A<8>.PIN | FCS | Z3_ADR_1/Z3_ADR_1_SETF
INPUTMC | 1 | 7 | 0
INPUTP | 2 | 106 | 147
EQ | 3 |
Z3_ADR<6>.D = A<8>.PIN;
Z3_ADR<6>.CLK = !FCS;
Z3_ADR<6>.AP = !Z3_ADR_1/Z3_ADR_1_SETF;
MACROCELL | 12 | 16 | LAN_ACCESS
ATTRIBUTES | 8520496 | 0
OUTPUTMC | 5 | 3 | 15 | 7 | 7 | 13 | 13 | 8 | 6 | 3 | 9
INPUTS | 13 | Z3 | D<12>.PIN | LAN_BASEADR<12> | SHUT_UP | $OpTx$FX_DC$46 | $OpTx$FX_DC$45 | $OpTx$FX_DC$44 | $OpTx$FX_DC$43 | $OpTx$FX_DC$47 | $OpTx$INV$2 | $OpTx$INV$1 | FCS | Z3_ADR_1/Z3_ADR_1_SETF
INPUTMC | 10 | 10 | 7 | 1 | 0 | 0 | 17 | 6 | 7 | 13 | 9 | 13 | 11 | 0 | 15 | 5 | 17 | 13 | 0 | 7 | 0
INPUTP | 3 | 151 | 78 | 147
EQ | 8 |
LAN_ACCESS.D = Z3 & D<12>.PIN & LAN_BASEADR<12> & !SHUT_UP &
!$OpTx$FX_DC$46 & !$OpTx$FX_DC$45 & !$OpTx$FX_DC$44 & !$OpTx$FX_DC$43 &
!$OpTx$FX_DC$47 & !$OpTx$INV$2 & !$OpTx$INV$1
# Z3 & !D<12>.PIN & !LAN_BASEADR<12> & !SHUT_UP &
!$OpTx$FX_DC$46 & !$OpTx$FX_DC$45 & !$OpTx$FX_DC$44 & !$OpTx$FX_DC$43 &
!$OpTx$FX_DC$47 & !$OpTx$INV$2 & !$OpTx$INV$1;
LAN_ACCESS.CLK = !FCS;
LAN_ACCESS.AR = !Z3_ADR_1/Z3_ADR_1_SETF;
MACROCELL | 4 | 2 | LAN_RST_SM_FSM_FFd1
ATTRIBUTES | 4358928 | 0
OUTPUTMC | 6 | 4 | 2 | 4 | 12 | 4 | 10 | 4 | 5 | 4 | 3 | 4 | 7
INPUTS | 4 | LAN_RST_SM_FSM_FFd1 | LAN_RST_SM_FSM_FFd2 | LAN_RST_SM_FSM_FFd3 | RESET
INPUTMC | 3 | 4 | 2 | 4 | 12 | 4 | 10
INPUTP | 1 | 263
EQ | 4 |
LAN_RST_SM_FSM_FFd1.T = !LAN_RST_SM_FSM_FFd1 & LAN_RST_SM_FSM_FFd2 &
!LAN_RST_SM_FSM_FFd3;
LAN_RST_SM_FSM_FFd1.CLK = CLK_EXT; // GCK
LAN_RST_SM_FSM_FFd1.AR = RESET;
GLOBALS | 1 | 2 | CLK_EXT
MACROCELL | 5 | 16 | AUTOCONFIG_ACCESS
ATTRIBUTES | 8520496 | 0
OUTPUTMC | 29 | 14 | 4 | 10 | 14 | 10 | 12 | 10 | 8 | 10 | 7 | 10 | 6 | 1 | 17 | 1 | 15 | 1 | 12 | 1 | 10 | 1 | 8 | 1 | 6 | 1 | 3 | 10 | 5 | 10 | 3 | 10 | 1 | 10 | 0 | 1 | 0 | 14 | 2 | 14 | 15 | 14 | 3 | 14 | 1 | 10 | 17 | 10 | 15 | 14 | 12 | 14 | 0 | 13 | 13 | 14 | 17 | 13 | 8
INPUTS | 21 | Z3 | D<9>.PIN | D<8>.PIN | D<14>.PIN | D<13>.PIN | D<12>.PIN | D<11>.PIN | D<10>.PIN | D<15>.PIN | CFIN | A<20>.PIN | A<19>.PIN | A<18>.PIN | A<17>.PIN | A<16>.PIN | A<23>.PIN | A<22>.PIN | A<21>.PIN | CFOUT | FCS | Z3_ADR_1/Z3_ADR_1_SETF
INPUTMC | 2 | 13 | 10 | 7 | 0
INPUTP | 19 | 151 | 73 | 32 | 81 | 80 | 78 | 77 | 74 | 89 | 190 | 167 | 169 | 171 | 172 | 175 | 161 | 162 | 163 | 147
EQ | 6 |
AUTOCONFIG_ACCESS.D = Z3 & D<9>.PIN & D<8>.PIN & D<14>.PIN &
D<13>.PIN & D<12>.PIN & D<11>.PIN & D<10>.PIN & D<15>.PIN &
!CFIN & !A<20>.PIN & !A<19>.PIN & !A<18>.PIN & !A<17>.PIN &
!A<16>.PIN & !A<23>.PIN & !A<22>.PIN & !A<21>.PIN & CFOUT;
AUTOCONFIG_ACCESS.CLK = !FCS;
AUTOCONFIG_ACCESS.AR = !Z3_ADR_1/Z3_ADR_1_SETF;
MACROCELL | 4 | 12 | LAN_RST_SM_FSM_FFd2
ATTRIBUTES | 8553232 | 0
OUTPUTMC | 5 | 4 | 2 | 4 | 12 | 4 | 10 | 4 | 0 | 4 | 6
INPUTS | 4 | LAN_RST_SM_FSM_FFd2 | LAN_RST_SM_FSM_FFd3 | LAN_RST_SM_FSM_FFd1 | RESET
INPUTMC | 3 | 4 | 12 | 4 | 10 | 4 | 2
INPUTP | 1 | 263
EQ | 4 |
LAN_RST_SM_FSM_FFd2.D = !LAN_RST_SM_FSM_FFd1 & LAN_RST_SM_FSM_FFd3
# LAN_RST_SM_FSM_FFd2 & !LAN_RST_SM_FSM_FFd3;
LAN_RST_SM_FSM_FFd2.CLK = CLK_EXT; // GCK
LAN_RST_SM_FSM_FFd2.AR = RESET;
GLOBALS | 1 | 2 | CLK_EXT
MACROCELL | 4 | 10 | LAN_RST_SM_FSM_FFd3
ATTRIBUTES | 8553232 | 0
OUTPUTMC | 4 | 4 | 2 | 4 | 12 | 4 | 0 | 4 | 6
INPUTS | 3 | LAN_RST_SM_FSM_FFd1 | LAN_RST_SM_FSM_FFd2 | RESET
INPUTMC | 2 | 4 | 2 | 4 | 12
INPUTP | 1 | 263
EQ | 4 |
!LAN_RST_SM_FSM_FFd3.D = LAN_RST_SM_FSM_FFd1
$ LAN_RST_SM_FSM_FFd2;
LAN_RST_SM_FSM_FFd3.CLK = CLK_EXT; // GCK
LAN_RST_SM_FSM_FFd3.AR = RESET;
GLOBALS | 1 | 2 | CLK_EXT
MACROCELL | 13 | 12 | Z3_ADR<3>
ATTRIBUTES | 8520608 | 0
OUTPUTMC | 27 | 14 | 4 | 10 | 14 | 10 | 12 | 10 | 8 | 10 | 7 | 10 | 6 | 1 | 17 | 1 | 15 | 1 | 12 | 1 | 10 | 1 | 8 | 1 | 6 | 1 | 3 | 10 | 5 | 10 | 3 | 10 | 1 | 10 | 0 | 1 | 0 | 14 | 2 | 14 | 15 | 14 | 3 | 14 | 1 | 10 | 17 | 10 | 15 | 14 | 12 | 14 | 0 | 1 | 1
INPUTS | 3 | A<5> | FCS | Z3_ADR_1/Z3_ADR_1_SETF
INPUTMC | 1 | 7 | 0
INPUTP | 2 | 91 | 147
EQ | 3 |
Z3_ADR<3>.D = A<5>;
Z3_ADR<3>.CLK = !FCS;
Z3_ADR<3>.AP = !Z3_ADR_1/Z3_ADR_1_SETF;
MACROCELL | 6 | 16 | Z3_ADR<4>
ATTRIBUTES | 8520608 | 0
OUTPUTMC | 28 | 14 | 4 | 10 | 14 | 10 | 12 | 10 | 8 | 10 | 7 | 10 | 6 | 1 | 17 | 1 | 15 | 1 | 12 | 1 | 10 | 1 | 8 | 1 | 6 | 1 | 3 | 10 | 5 | 10 | 3 | 10 | 1 | 10 | 0 | 1 | 0 | 14 | 2 | 14 | 15 | 14 | 3 | 14 | 1 | 10 | 17 | 10 | 15 | 14 | 12 | 14 | 0 | 3 | 13 | 6 | 17
INPUTS | 7 | A<6> | FCS | Z3_ADR_1/Z3_ADR_1_SETF | LDS | D<1>.PIN | LAN_SM_FSM_FFd12 | $OpTx$FX_DC$10
INPUTMC | 3 | 7 | 0 | 9 | 6 | 8 | 1
INPUTP | 4 | 98 | 147 | 157 | 30
EXPORTS | 1 | 6 | 17
EQ | 5 |
Z3_ADR<4>.D = A<6>;
Z3_ADR<4>.CLK = !FCS;
Z3_ADR<4>.AP = !Z3_ADR_1/Z3_ADR_1_SETF;
Z3_ADR<4>.EXP = !LDS & D<1>.PIN & LAN_SM_FSM_FFd12 &
!$OpTx$FX_DC$10
MACROCELL | 6 | 15 | Z3_ADR<5>
ATTRIBUTES | 8520608 | 0
OUTPUTMC | 27 | 14 | 4 | 10 | 14 | 10 | 12 | 10 | 8 | 10 | 7 | 10 | 6 | 1 | 17 | 1 | 15 | 1 | 12 | 1 | 10 | 1 | 8 | 1 | 6 | 1 | 3 | 10 | 5 | 10 | 3 | 10 | 1 | 10 | 0 | 1 | 0 | 14 | 2 | 14 | 15 | 14 | 3 | 14 | 1 | 10 | 17 | 10 | 15 | 14 | 12 | 14 | 0 | 1 | 4
INPUTS | 3 | A<7> | FCS | Z3_ADR_1/Z3_ADR_1_SETF
INPUTMC | 1 | 7 | 0
INPUTP | 2 | 100 | 147
EQ | 3 |
Z3_ADR<5>.D = A<7>;
Z3_ADR<5>.CLK = !FCS;
Z3_ADR<5>.AP = !Z3_ADR_1/Z3_ADR_1_SETF;
MACROCELL | 12 | 11 | Z3_ADR<13>
ATTRIBUTES | 8520608 | 0
OUTPUTMC | 3 | 3 | 15 | 3 | 8 | 3 | 9
INPUTS | 3 | A<15>.PIN | FCS | Z3_ADR_1/Z3_ADR_1_SETF
INPUTMC | 1 | 7 | 0
INPUTP | 2 | 139 | 147
EQ | 3 |
Z3_ADR<13>.D = A<15>.PIN;
Z3_ADR<13>.CLK = !FCS;
Z3_ADR<13>.AP = !Z3_ADR_1/Z3_ADR_1_SETF;
MACROCELL | 4 | 5 | LAN_D_INIT<1>
ATTRIBUTES | 8553232 | 0
OUTPUTMC | 3 | 9 | 1 | 9 | 9 | 11 | 11
INPUTS | 2 | LAN_RST_SM_FSM_FFd1 | RESET
INPUTMC | 1 | 4 | 2
INPUTP | 1 | 263
EQ | 3 |
LAN_D_INIT<1>.D = LAN_RST_SM_FSM_FFd1;
LAN_D_INIT<1>.CLK = CLK_EXT; // GCK
LAN_D_INIT<1>.AR = RESET;
GLOBALS | 1 | 2 | CLK_EXT
MACROCELL | 4 | 3 | LAN_D_INIT<8>
ATTRIBUTES | 8553232 | 0
OUTPUTMC | 3 | 9 | 16 | 11 | 9 | 9 | 13
INPUTS | 2 | LAN_RST_SM_FSM_FFd1 | RESET
INPUTMC | 1 | 4 | 2
INPUTP | 1 | 263
EQ | 3 |
LAN_D_INIT<8>.D = !LAN_RST_SM_FSM_FFd1;
LAN_D_INIT<8>.CLK = CLK_EXT; // GCK
LAN_D_INIT<8>.AR = RESET;
GLOBALS | 1 | 2 | CLK_EXT
MACROCELL | 9 | 17 | DQ_DATA<0>
ATTRIBUTES | 8553344 | 0
OUTPUTMC | 2 | 9 | 2 | 9 | 17
INPUTS | 10 | D<8>.PIN | $OpTx$FX_SC$33 | DQ_DATA<0> | $OpTx$FX_DC$22 | A<8>.PIN | $OpTx$FX_DC$18 | $OpTx$FX_DC$734 | A<16>.PIN | EXP24_.EXP | LAN_SM_RST
INPUTMC | 7 | 4 | 8 | 9 | 17 | 0 | 12 | 12 | 8 | 8 | 5 | 9 | 0 | 3 | 8
INPUTP | 3 | 32 | 106 | 175
IMPORTS | 1 | 9 | 0
EQ | 9 |
DQ_DATA<0>.D = D<8>.PIN & $OpTx$FX_SC$33
# DQ_DATA<0> & !$OpTx$FX_DC$22
# A<16>.PIN & !$OpTx$FX_DC$18 & $OpTx$FX_DC$734
# A<8>.PIN & $OpTx$FX_DC$18 & $OpTx$FX_DC$734
;Imported pterms FB10_1
# !LDS & D<0>.PIN & LAN_SM_FSM_FFd12 &
!$OpTx$FX_DC$10;
DQ_DATA<0>.CLK = CLK_EXT; // GCK
DQ_DATA<0>.AP = LAN_SM_RST;
GLOBALS | 1 | 2 | CLK_EXT
MACROCELL | 9 | 15 | DQ_DATA<10>
ATTRIBUTES | 8553344 | 0
OUTPUTMC | 2 | 9 | 16 | 9 | 15
INPUTS | 10 | D<10>.PIN | $OpTx$FX_SC$31 | DQ_DATA<10> | $OpTx$FX_DC$22 | A<10>.PIN | $OpTx$FX_DC$734 | $OpTx$FX_DC$17 | A<18>.PIN | DQ_10_IOBUFE.EXP | LAN_SM_RST
INPUTMC | 7 | 8 | 4 | 9 | 15 | 0 | 12 | 8 | 5 | 12 | 9 | 9 | 16 | 3 | 8
INPUTP | 3 | 74 | 112 | 171
IMPORTS | 1 | 9 | 16
EQ | 9 |
DQ_DATA<10>.D = D<10>.PIN & $OpTx$FX_SC$31
# DQ_DATA<10> & !$OpTx$FX_DC$22
# A<18>.PIN & $OpTx$FX_DC$734 & $OpTx$FX_DC$17
# A<10>.PIN & $OpTx$FX_DC$734 & !$OpTx$FX_DC$17
;Imported pterms FB10_17
# !LDS & D<2>.PIN & LAN_SM_FSM_FFd12 &
!$OpTx$FX_DC$11;
DQ_DATA<10>.CLK = CLK_EXT; // GCK
DQ_DATA<10>.AP = LAN_SM_RST;
GLOBALS | 1 | 2 | CLK_EXT
MACROCELL | 8 | 17 | DQ_DATA<11>
ATTRIBUTES | 8553344 | 0
OUTPUTMC | 2 | 11 | 9 | 8 | 17
INPUTS | 10 | D<11>.PIN | $OpTx$FX_SC$31 | DQ_DATA<11> | $OpTx$FX_DC$22 | A<11>.PIN | $OpTx$FX_DC$734 | $OpTx$FX_DC$17 | A<19>.PIN | Z3_DATA<8>/Z3_DATA<8>_TRST.EXP | LAN_SM_RST
INPUTMC | 7 | 8 | 4 | 8 | 17 | 0 | 12 | 8 | 5 | 12 | 9 | 8 | 0 | 3 | 8
INPUTP | 3 | 77 | 114 | 169
IMPORTS | 1 | 8 | 0
EQ | 9 |
DQ_DATA<11>.D = D<11>.PIN & $OpTx$FX_SC$31
# DQ_DATA<11> & !$OpTx$FX_DC$22
# A<19>.PIN & $OpTx$FX_DC$734 & $OpTx$FX_DC$17
# A<11>.PIN & $OpTx$FX_DC$734 & !$OpTx$FX_DC$17
;Imported pterms FB9_1
# !LDS & D<3>.PIN & LAN_SM_FSM_FFd12 &
!$OpTx$FX_DC$11;
DQ_DATA<11>.CLK = CLK_EXT; // GCK
DQ_DATA<11>.AP = LAN_SM_RST;
GLOBALS | 1 | 2 | CLK_EXT
MACROCELL | 4 | 17 | DQ_DATA<12>
ATTRIBUTES | 8553344 | 0
OUTPUTMC | 2 | 7 | 1 | 4 | 17
INPUTS | 10 | D<12>.PIN | $OpTx$FX_SC$31 | DQ_DATA<12> | $OpTx$FX_DC$22 | A<12>.PIN | $OpTx$FX_DC$734 | $OpTx$FX_DC$17 | A<20>.PIN | D_12_IOBUFE.EXP | LAN_SM_RST
INPUTMC | 7 | 8 | 4 | 4 | 17 | 0 | 12 | 8 | 5 | 12 | 9 | 4 | 16 | 3 | 8
INPUTP | 3 | 78 | 115 | 167
IMPORTS | 1 | 4 | 16
EQ | 9 |
DQ_DATA<12>.D = D<12>.PIN & $OpTx$FX_SC$31
# DQ_DATA<12> & !$OpTx$FX_DC$22
# A<20>.PIN & $OpTx$FX_DC$734 & $OpTx$FX_DC$17
# A<12>.PIN & $OpTx$FX_DC$734 & !$OpTx$FX_DC$17
;Imported pterms FB5_17
# !LDS & D<4>.PIN & LAN_SM_FSM_FFd12 &
!$OpTx$FX_DC$11;
DQ_DATA<12>.CLK = CLK_EXT; // GCK
DQ_DATA<12>.AP = LAN_SM_RST;
GLOBALS | 1 | 2 | CLK_EXT
MACROCELL | 7 | 17 | DQ_DATA<13>
ATTRIBUTES | 8553344 | 0
OUTPUTMC | 3 | 11 | 7 | 7 | 17 | 7 | 16
INPUTS | 13 | D<13>.PIN | $OpTx$FX_SC$31 | DQ_DATA<13> | $OpTx$FX_DC$22 | A<13>.PIN | $OpTx$FX_DC$734 | $OpTx$FX_DC$17 | LDS | D<6>.PIN | LAN_SM_FSM_FFd12 | $OpTx$FX_DC$11 | Z3_ADR_1/Z3_ADR_1_SETF.EXP | LAN_SM_RST
INPUTMC | 9 | 8 | 4 | 7 | 17 | 0 | 12 | 8 | 5 | 12 | 9 | 9 | 6 | 12 | 4 | 7 | 0 | 3 | 8
INPUTP | 4 | 80 | 123 | 157 | 26
EXPORTS | 1 | 7 | 16
IMPORTS | 1 | 7 | 0
EQ | 11 |
DQ_DATA<13>.D = D<13>.PIN & $OpTx$FX_SC$31
# DQ_DATA<13> & !$OpTx$FX_DC$22
# A<13>.PIN & $OpTx$FX_DC$734 & !$OpTx$FX_DC$17
;Imported pterms FB8_1
# A<21>.PIN & $OpTx$FX_DC$734 & $OpTx$FX_DC$17
# !LDS & D<5>.PIN & LAN_SM_FSM_FFd12 &
!$OpTx$FX_DC$11;
DQ_DATA<13>.CLK = CLK_EXT; // GCK
DQ_DATA<13>.AP = LAN_SM_RST;
DQ_DATA<13>.EXP = !LDS & D<6>.PIN & LAN_SM_FSM_FFd12 &
!$OpTx$FX_DC$11
GLOBALS | 1 | 2 | CLK_EXT
MACROCELL | 7 | 16 | DQ_DATA<14>
ATTRIBUTES | 8553344 | 0
OUTPUTMC | 2 | 7 | 2 | 7 | 16
INPUTS | 10 | D<14>.PIN | $OpTx$FX_SC$31 | DQ_DATA<14> | $OpTx$FX_DC$22 | A<14>.PIN | $OpTx$FX_DC$734 | $OpTx$FX_DC$17 | A<22>.PIN | DQ_DATA<13>.EXP | LAN_SM_RST
INPUTMC | 7 | 8 | 4 | 7 | 16 | 0 | 12 | 8 | 5 | 12 | 9 | 7 | 17 | 3 | 8
INPUTP | 3 | 81 | 125 | 162
IMPORTS | 1 | 7 | 17
EQ | 9 |
DQ_DATA<14>.D = D<14>.PIN & $OpTx$FX_SC$31
# DQ_DATA<14> & !$OpTx$FX_DC$22
# A<14>.PIN & $OpTx$FX_DC$734 & !$OpTx$FX_DC$17
# A<22>.PIN & $OpTx$FX_DC$734 & $OpTx$FX_DC$17
;Imported pterms FB8_18
# !LDS & D<6>.PIN & LAN_SM_FSM_FFd12 &
!$OpTx$FX_DC$11;
DQ_DATA<14>.CLK = CLK_EXT; // GCK
DQ_DATA<14>.AP = LAN_SM_RST;
GLOBALS | 1 | 2 | CLK_EXT
MACROCELL | 3 | 17 | DQ_DATA<15>
ATTRIBUTES | 8553344 | 0
OUTPUTMC | 2 | 11 | 4 | 3 | 17
INPUTS | 10 | D<15>.PIN | $OpTx$FX_SC$31 | DQ_DATA<15> | $OpTx$FX_DC$22 | A<15>.PIN | $OpTx$FX_DC$734 | $OpTx$FX_DC$17 | A<23>.PIN | EXP22_.EXP | LAN_SM_RST
INPUTMC | 7 | 8 | 4 | 3 | 17 | 0 | 12 | 8 | 5 | 12 | 9 | 3 | 0 | 3 | 8
INPUTP | 3 | 89 | 139 | 161
IMPORTS | 1 | 3 | 0
EQ | 9 |
DQ_DATA<15>.D = D<15>.PIN & $OpTx$FX_SC$31
# DQ_DATA<15> & !$OpTx$FX_DC$22
# A<15>.PIN & $OpTx$FX_DC$734 & !$OpTx$FX_DC$17
# A<23>.PIN & $OpTx$FX_DC$734 & $OpTx$FX_DC$17
;Imported pterms FB4_1
# !LDS & D<7>.PIN & LAN_SM_FSM_FFd12 &
!$OpTx$FX_DC$11;
DQ_DATA<15>.CLK = CLK_EXT; // GCK
DQ_DATA<15>.AP = LAN_SM_RST;
GLOBALS | 1 | 2 | CLK_EXT
MACROCELL | 6 | 17 | DQ_DATA<1>
ATTRIBUTES | 8553344 | 0
OUTPUTMC | 2 | 9 | 1 | 6 | 17
INPUTS | 10 | D<9>.PIN | $OpTx$FX_SC$33 | DQ_DATA<1> | $OpTx$FX_DC$22 | A<9>.PIN | $OpTx$FX_DC$18 | $OpTx$FX_DC$734 | A<17>.PIN | Z3_ADR<4>.EXP | LAN_SM_RST
INPUTMC | 7 | 4 | 8 | 6 | 17 | 0 | 12 | 12 | 8 | 8 | 5 | 6 | 16 | 3 | 8
INPUTP | 3 | 73 | 108 | 172
IMPORTS | 1 | 6 | 16
EQ | 9 |
DQ_DATA<1>.D = D<9>.PIN & $OpTx$FX_SC$33
# DQ_DATA<1> & !$OpTx$FX_DC$22
# A<17>.PIN & !$OpTx$FX_DC$18 & $OpTx$FX_DC$734
# A<9>.PIN & $OpTx$FX_DC$18 & $OpTx$FX_DC$734
;Imported pterms FB7_17
# !LDS & D<1>.PIN & LAN_SM_FSM_FFd12 &
!$OpTx$FX_DC$10;
DQ_DATA<1>.CLK = CLK_EXT; // GCK
DQ_DATA<1>.AP = LAN_SM_RST;
GLOBALS | 1 | 2 | CLK_EXT
MACROCELL | 9 | 14 | DQ_DATA<2>
ATTRIBUTES | 8553344 | 0
OUTPUTMC | 2 | 9 | 5 | 9 | 14
INPUTS | 10 | D<10>.PIN | $OpTx$FX_SC$33 | DQ_DATA<2> | $OpTx$FX_DC$22 | A<10>.PIN | $OpTx$FX_DC$18 | $OpTx$FX_DC$734 | A<18>.PIN | DQ_8_IOBUFE.EXP | LAN_SM_RST
INPUTMC | 7 | 4 | 8 | 9 | 14 | 0 | 12 | 12 | 8 | 8 | 5 | 9 | 13 | 3 | 8
INPUTP | 3 | 74 | 112 | 171
IMPORTS | 1 | 9 | 13
EQ | 9 |
DQ_DATA<2>.D = D<10>.PIN & $OpTx$FX_SC$33
# DQ_DATA<2> & !$OpTx$FX_DC$22
# A<18>.PIN & !$OpTx$FX_DC$18 & $OpTx$FX_DC$734
# A<10>.PIN & $OpTx$FX_DC$18 & $OpTx$FX_DC$734
;Imported pterms FB10_14
# !LDS & D<2>.PIN & LAN_SM_FSM_FFd12 &
!$OpTx$FX_DC$10;
DQ_DATA<2>.CLK = CLK_EXT; // GCK
DQ_DATA<2>.AP = LAN_SM_RST;
GLOBALS | 1 | 2 | CLK_EXT
MACROCELL | 11 | 17 | DQ_DATA<3>
ATTRIBUTES | 8553344 | 0
OUTPUTMC | 3 | 9 | 4 | 11 | 17 | 11 | 16
INPUTS | 13 | D<11>.PIN | $OpTx$FX_SC$33 | DQ_DATA<3> | $OpTx$FX_DC$22 | A<11>.PIN | $OpTx$FX_DC$18 | $OpTx$FX_DC$734 | LDS | D<7>.PIN | LAN_SM_FSM_FFd12 | $OpTx$FX_DC$10 | EXP25_.EXP | LAN_SM_RST
INPUTMC | 9 | 4 | 8 | 11 | 17 | 0 | 12 | 12 | 8 | 8 | 5 | 9 | 6 | 8 | 1 | 11 | 0 | 3 | 8
INPUTP | 4 | 77 | 114 | 157 | 29
EXPORTS | 1 | 11 | 16
IMPORTS | 1 | 11 | 0
EQ | 11 |
DQ_DATA<3>.D = D<11>.PIN & $OpTx$FX_SC$33
# DQ_DATA<3> & !$OpTx$FX_DC$22
# A<11>.PIN & $OpTx$FX_DC$18 & $OpTx$FX_DC$734
;Imported pterms FB12_1
# A<19>.PIN & !$OpTx$FX_DC$18 & $OpTx$FX_DC$734
# !LDS & D<3>.PIN & LAN_SM_FSM_FFd12 &
!$OpTx$FX_DC$10;
DQ_DATA<3>.CLK = CLK_EXT; // GCK
DQ_DATA<3>.AP = LAN_SM_RST;
DQ_DATA<3>.EXP = !LDS & D<7>.PIN & LAN_SM_FSM_FFd12 &
!$OpTx$FX_DC$10
GLOBALS | 1 | 2 | CLK_EXT
MACROCELL | 4 | 15 | DQ_DATA<4>
ATTRIBUTES | 8553344 | 0
OUTPUTMC | 2 | 9 | 9 | 4 | 15
INPUTS | 10 | D<12>.PIN | $OpTx$FX_SC$33 | DQ_DATA<4> | $OpTx$FX_DC$22 | A<12>.PIN | $OpTx$FX_DC$18 | $OpTx$FX_DC$734 | A<20>.PIN | D_11_IOBUFE.EXP | LAN_SM_RST
INPUTMC | 7 | 4 | 8 | 4 | 15 | 0 | 12 | 12 | 8 | 8 | 5 | 4 | 14 | 3 | 8
INPUTP | 3 | 78 | 115 | 167
IMPORTS | 1 | 4 | 14
EQ | 9 |
DQ_DATA<4>.D = D<12>.PIN & $OpTx$FX_SC$33
# DQ_DATA<4> & !$OpTx$FX_DC$22
# A<20>.PIN & !$OpTx$FX_DC$18 & $OpTx$FX_DC$734
# A<12>.PIN & $OpTx$FX_DC$18 & $OpTx$FX_DC$734
;Imported pterms FB5_15
# !LDS & D<4>.PIN & LAN_SM_FSM_FFd12 &
!$OpTx$FX_DC$10;
DQ_DATA<4>.CLK = CLK_EXT; // GCK
DQ_DATA<4>.AP = LAN_SM_RST;
GLOBALS | 1 | 2 | CLK_EXT
MACROCELL | 7 | 15 | DQ_DATA<5>
ATTRIBUTES | 8553344 | 0
OUTPUTMC | 2 | 9 | 7 | 7 | 15
INPUTS | 10 | D<13>.PIN | $OpTx$FX_SC$33 | DQ_DATA<5> | $OpTx$FX_DC$22 | A<13>.PIN | $OpTx$FX_DC$18 | $OpTx$FX_DC$734 | A<21>.PIN | DQ_DATA<6>.EXP | LAN_SM_RST
INPUTMC | 7 | 4 | 8 | 7 | 15 | 0 | 12 | 12 | 8 | 8 | 5 | 7 | 14 | 3 | 8
INPUTP | 3 | 80 | 123 | 163
IMPORTS | 1 | 7 | 14
EQ | 9 |
DQ_DATA<5>.D = D<13>.PIN & $OpTx$FX_SC$33
# DQ_DATA<5> & !$OpTx$FX_DC$22
# A<13>.PIN & $OpTx$FX_DC$18 & $OpTx$FX_DC$734
# A<21>.PIN & !$OpTx$FX_DC$18 & $OpTx$FX_DC$734
;Imported pterms FB8_15
# !LDS & D<5>.PIN & LAN_SM_FSM_FFd12 &
!$OpTx$FX_DC$10;
DQ_DATA<5>.CLK = CLK_EXT; // GCK
DQ_DATA<5>.AP = LAN_SM_RST;
GLOBALS | 1 | 2 | CLK_EXT
MACROCELL | 7 | 14 | DQ_DATA<6>
ATTRIBUTES | 8553344 | 0
OUTPUTMC | 3 | 9 | 11 | 7 | 14 | 7 | 15
INPUTS | 13 | D<14>.PIN | $OpTx$FX_SC$33 | DQ_DATA<6> | $OpTx$FX_DC$22 | A<14>.PIN | $OpTx$FX_DC$18 | $OpTx$FX_DC$734 | LDS | D<5>.PIN | LAN_SM_FSM_FFd12 | $OpTx$FX_DC$10 | EXP23_.EXP | LAN_SM_RST
INPUTMC | 9 | 4 | 8 | 7 | 14 | 0 | 12 | 12 | 8 | 8 | 5 | 9 | 6 | 8 | 1 | 7 | 13 | 3 | 8
INPUTP | 4 | 81 | 125 | 157 | 37
EXPORTS | 1 | 7 | 15
IMPORTS | 1 | 7 | 13
EQ | 11 |
DQ_DATA<6>.D = D<14>.PIN & $OpTx$FX_SC$33
# DQ_DATA<6> & !$OpTx$FX_DC$22
# A<14>.PIN & $OpTx$FX_DC$18 & $OpTx$FX_DC$734
;Imported pterms FB8_14
# A<22>.PIN & !$OpTx$FX_DC$18 & $OpTx$FX_DC$734
# !LDS & D<6>.PIN & LAN_SM_FSM_FFd12 &
!$OpTx$FX_DC$10;
DQ_DATA<6>.CLK = CLK_EXT; // GCK
DQ_DATA<6>.AP = LAN_SM_RST;
DQ_DATA<6>.EXP = !LDS & D<5>.PIN & LAN_SM_FSM_FFd12 &
!$OpTx$FX_DC$10
GLOBALS | 1 | 2 | CLK_EXT
MACROCELL | 11 | 16 | DQ_DATA<7>
ATTRIBUTES | 8553344 | 0
OUTPUTMC | 2 | 9 | 10 | 11 | 16
INPUTS | 10 | D<15>.PIN | $OpTx$FX_SC$33 | DQ_DATA<7> | $OpTx$FX_DC$22 | A<15>.PIN | $OpTx$FX_DC$18 | $OpTx$FX_DC$734 | A<23>.PIN | DQ_DATA<3>.EXP | LAN_SM_RST
INPUTMC | 7 | 4 | 8 | 11 | 16 | 0 | 12 | 12 | 8 | 8 | 5 | 11 | 17 | 3 | 8
INPUTP | 3 | 89 | 139 | 161
IMPORTS | 1 | 11 | 17
EQ | 9 |
DQ_DATA<7>.D = D<15>.PIN & $OpTx$FX_SC$33
# DQ_DATA<7> & !$OpTx$FX_DC$22
# A<15>.PIN & $OpTx$FX_DC$18 & $OpTx$FX_DC$734
# A<23>.PIN & !$OpTx$FX_DC$18 & $OpTx$FX_DC$734
;Imported pterms FB12_18
# !LDS & D<7>.PIN & LAN_SM_FSM_FFd12 &
!$OpTx$FX_DC$10;
DQ_DATA<7>.CLK = CLK_EXT; // GCK
DQ_DATA<7>.AP = LAN_SM_RST;
GLOBALS | 1 | 2 | CLK_EXT
MACROCELL | 9 | 12 | DQ_DATA<8>
ATTRIBUTES | 8553344 | 0
OUTPUTMC | 2 | 9 | 13 | 9 | 12
INPUTS | 10 | D<8>.PIN | $OpTx$FX_SC$31 | DQ_DATA<8> | $OpTx$FX_DC$22 | A<8>.PIN | $OpTx$FX_DC$734 | $OpTx$FX_DC$17 | A<16>.PIN | DQ_6_IOBUFE.EXP | LAN_SM_RST
INPUTMC | 7 | 8 | 4 | 9 | 12 | 0 | 12 | 8 | 5 | 12 | 9 | 9 | 11 | 3 | 8
INPUTP | 3 | 32 | 106 | 175
IMPORTS | 1 | 9 | 11
EQ | 9 |
DQ_DATA<8>.D = D<8>.PIN & $OpTx$FX_SC$31
# DQ_DATA<8> & !$OpTx$FX_DC$22
# A<16>.PIN & $OpTx$FX_DC$734 & $OpTx$FX_DC$17
# A<8>.PIN & $OpTx$FX_DC$734 & !$OpTx$FX_DC$17
;Imported pterms FB10_12
# !LDS & D<0>.PIN & LAN_SM_FSM_FFd12 &
!$OpTx$FX_DC$11;
DQ_DATA<8>.CLK = CLK_EXT; // GCK
DQ_DATA<8>.AP = LAN_SM_RST;
GLOBALS | 1 | 2 | CLK_EXT
MACROCELL | 11 | 15 | DQ_DATA<9>
ATTRIBUTES | 8553344 | 0
OUTPUTMC | 2 | 11 | 11 | 11 | 15
INPUTS | 10 | D<9>.PIN | $OpTx$FX_SC$31 | DQ_DATA<9> | $OpTx$FX_DC$22 | A<9>.PIN | $OpTx$FX_DC$734 | $OpTx$FX_DC$17 | A<17>.PIN | EXP26_.EXP | LAN_SM_RST
INPUTMC | 7 | 8 | 4 | 11 | 15 | 0 | 12 | 8 | 5 | 12 | 9 | 11 | 14 | 3 | 8
INPUTP | 3 | 73 | 108 | 172
IMPORTS | 1 | 11 | 14
EQ | 9 |
DQ_DATA<9>.D = D<9>.PIN & $OpTx$FX_SC$31
# DQ_DATA<9> & !$OpTx$FX_DC$22
# A<17>.PIN & $OpTx$FX_DC$734 & $OpTx$FX_DC$17
# A<9>.PIN & $OpTx$FX_DC$734 & !$OpTx$FX_DC$17
;Imported pterms FB12_15
# !LDS & D<1>.PIN & LAN_SM_FSM_FFd12 &
!$OpTx$FX_DC$11;
DQ_DATA<9>.CLK = CLK_EXT; // GCK
DQ_DATA<9>.AP = LAN_SM_RST;
GLOBALS | 1 | 2 | CLK_EXT
MACROCELL | 4 | 0 | LAN_WR_RST
ATTRIBUTES | 8553232 | 0
OUTPUTMC | 2 | 7 | 4 | 12 | 13
INPUTS | 3 | LAN_RST_SM_FSM_FFd2 | LAN_RST_SM_FSM_FFd3 | RESET
INPUTMC | 2 | 4 | 12 | 4 | 10
INPUTP | 1 | 263
EQ | 3 |
LAN_WR_RST.D = LAN_RST_SM_FSM_FFd2 & LAN_RST_SM_FSM_FFd3;
LAN_WR_RST.CLK = CLK_EXT; // GCK
LAN_WR_RST.AR = RESET;
GLOBALS | 1 | 2 | CLK_EXT
MACROCELL | 3 | 15 | CONFIG_READY
ATTRIBUTES | 8553296 | 0
OUTPUTMC | 1 | 13 | 8
INPUTS | 5 | RESET | RW | FCS | LAN_ACCESS | Z3_ADR<13>
INPUTMC | 2 | 12 | 16 | 12 | 11
INPUTP | 3 | 263 | 158 | 147
EQ | 4 |
CONFIG_READY.D = Vcc;
CONFIG_READY.CLK = CLK_EXT; // GCK
CONFIG_READY.AR = !RESET;
CONFIG_READY.CE = !RW & !FCS & LAN_ACCESS & Z3_ADR<13>;
GLOBALS | 1 | 2 | CLK_EXT
MACROCELL | 1 | 0 | SHUT_UP
ATTRIBUTES | 8553408 | 0
OUTPUTMC | 2 | 12 | 17 | 12 | 16
INPUTS | 12 | RESET | RW | FCS | UDS | Z3_ADR<2> | Z3_ADR_1 | Z3_ADR_0 | Z3_ADR<6> | AUTOCONFIG_ACCESS | Z3_ADR<3> | Z3_ADR<4> | Z3_ADR<5>
INPUTMC | 8 | 12 | 10 | 6 | 8 | 6 | 9 | 6 | 14 | 5 | 16 | 13 | 12 | 6 | 16 | 6 | 15
INPUTP | 4 | 263 | 158 | 147 | 155
EQ | 6 |
SHUT_UP.D = Gnd;
SHUT_UP.CLK = CLK_EXT; // GCK
SHUT_UP.AP = !RESET;
SHUT_UP.CE = !RW & !FCS & !UDS & !Z3_ADR<2> & !Z3_ADR_1 &
Z3_ADR_0 & !Z3_ADR<6> & AUTOCONFIG_ACCESS & !Z3_ADR<3> &
Z3_ADR<4> & !Z3_ADR<5>;
GLOBALS | 1 | 2 | CLK_EXT
MACROCELL | 13 | 16 | Z3_ADR<10>
ATTRIBUTES | 8520608 | 0
OUTPUTMC | 2 | 5 | 7 | 13 | 17
INPUTS | 5 | A<12>.PIN | FCS | Z3_ADR_1/Z3_ADR_1_SETF | D<14>.PIN | LAN_BASEADR<14>
INPUTMC | 2 | 7 | 0 | 1 | 17
INPUTP | 3 | 115 | 147 | 81
EXPORTS | 1 | 13 | 17
EQ | 4 |
Z3_ADR<10>.D = A<12>.PIN;
Z3_ADR<10>.CLK = !FCS;
Z3_ADR<10>.AP = !Z3_ADR_1/Z3_ADR_1_SETF;
Z3_ADR<10>.EXP = !D<14>.PIN & LAN_BASEADR<14>
MACROCELL | 13 | 15 | Z3_ADR<11>
ATTRIBUTES | 8520608 | 0
OUTPUTMC | 1 | 5 | 2
INPUTS | 3 | A<13>.PIN | FCS | Z3_ADR_1/Z3_ADR_1_SETF
INPUTMC | 1 | 7 | 0
INPUTP | 2 | 123 | 147
EQ | 3 |
Z3_ADR<11>.D = A<13>.PIN;
Z3_ADR<11>.CLK = !FCS;
Z3_ADR<11>.AP = !Z3_ADR_1/Z3_ADR_1_SETF;
MACROCELL | 12 | 12 | Z3_ADR<12>
ATTRIBUTES | 8520608 | 0
OUTPUTMC | 1 | 5 | 4
INPUTS | 3 | A<14>.PIN | FCS | Z3_ADR_1/Z3_ADR_1_SETF
INPUTMC | 1 | 7 | 0
INPUTP | 2 | 125 | 147
EQ | 3 |
Z3_ADR<12>.D = A<14>.PIN;
Z3_ADR<12>.CLK = !FCS;
Z3_ADR<12>.AP = !Z3_ADR_1/Z3_ADR_1_SETF;
MACROCELL | 6 | 13 | Z3_ADR<7>
ATTRIBUTES | 8520608 | 0
OUTPUTMC | 1 | 5 | 9
INPUTS | 3 | A<9>.PIN | FCS | Z3_ADR_1/Z3_ADR_1_SETF
INPUTMC | 1 | 7 | 0
INPUTP | 2 | 108 | 147
EQ | 3 |
Z3_ADR<7>.D = A<9>.PIN;
Z3_ADR<7>.CLK = !FCS;
Z3_ADR<7>.AP = !Z3_ADR_1/Z3_ADR_1_SETF;
MACROCELL | 6 | 12 | Z3_ADR<8>
ATTRIBUTES | 8520608 | 0
OUTPUTMC | 1 | 5 | 13
INPUTS | 3 | A<10>.PIN | FCS | Z3_ADR_1/Z3_ADR_1_SETF
INPUTMC | 1 | 7 | 0
INPUTP | 2 | 112 | 147
EQ | 3 |
Z3_ADR<8>.D = A<10>.PIN;
Z3_ADR<8>.CLK = !FCS;
Z3_ADR<8>.AP = !Z3_ADR_1/Z3_ADR_1_SETF;
MACROCELL | 6 | 10 | Z3_ADR<9>
ATTRIBUTES | 8520608 | 0
OUTPUTMC | 1 | 5 | 5
INPUTS | 3 | A<11>.PIN | FCS | Z3_ADR_1/Z3_ADR_1_SETF
INPUTMC | 1 | 7 | 0
INPUTP | 2 | 114 | 147
EQ | 3 |
Z3_ADR<9>.D = A<11>.PIN;
Z3_ADR<9>.CLK = !FCS;
Z3_ADR<9>.AP = !Z3_ADR_1/Z3_ADR_1_SETF;
MACROCELL | 14 | 2 | D_OUT<0>
ATTRIBUTES | 8553348 | 0
OUTPUTMC | 1 | 1 | 16
INPUTS | 10 | FCS | UDS | Z3_ADR<2> | Z3_ADR_1 | Z3_ADR_0 | AUTOCONFIG_ACCESS | Z3_ADR<3> | Z3_ADR<4> | Z3_ADR<5> | RESET
INPUTMC | 7 | 12 | 10 | 6 | 8 | 6 | 9 | 5 | 16 | 13 | 12 | 6 | 16 | 6 | 15
INPUTP | 3 | 147 | 155 | 263
EQ | 4 |
!D_OUT<0>.D = !FCS & !UDS & !Z3_ADR<2> & !Z3_ADR_1 & Z3_ADR_0 &
AUTOCONFIG_ACCESS & !Z3_ADR<3> & !Z3_ADR<4> & !Z3_ADR<5>;
D_OUT<0>.CLK = CLK_EXT; // GCK
D_OUT<0>.AP = !RESET;
GLOBALS | 1 | 2 | CLK_EXT
MACROCELL | 14 | 15 | D_OUT<1>
ATTRIBUTES | 8553348 | 0
OUTPUTMC | 1 | 4 | 11
INPUTS | 10 | FCS | UDS | Z3_ADR<2> | Z3_ADR_0 | AUTOCONFIG_ACCESS | Z3_ADR<3> | Z3_ADR<4> | Z3_ADR<5> | Z3_ADR_1 | RESET
INPUTMC | 7 | 12 | 10 | 6 | 9 | 5 | 16 | 13 | 12 | 6 | 16 | 6 | 15 | 6 | 8
INPUTP | 3 | 147 | 155 | 263
EQ | 8 |
!D_OUT<1>.D = !FCS & !UDS & !Z3_ADR<2> & !Z3_ADR_1 &
AUTOCONFIG_ACCESS & !Z3_ADR<3> & !Z3_ADR<4> & !Z3_ADR<5>
# !FCS & !UDS & !Z3_ADR<2> & !Z3_ADR_0 &
AUTOCONFIG_ACCESS & !Z3_ADR<3> & !Z3_ADR<4> & !Z3_ADR<5>
# !FCS & !UDS & !Z3_ADR_1 & !Z3_ADR_0 &
AUTOCONFIG_ACCESS & !Z3_ADR<3> & !Z3_ADR<4> & !Z3_ADR<5>;
D_OUT<1>.CLK = CLK_EXT; // GCK
D_OUT<1>.AP = !RESET;
GLOBALS | 1 | 2 | CLK_EXT
MACROCELL | 14 | 3 | D_OUT<2>
ATTRIBUTES | 8553348 | 0
OUTPUTMC | 1 | 4 | 13
INPUTS | 10 | FCS | UDS | Z3_ADR<2> | Z3_ADR_1 | Z3_ADR_0 | AUTOCONFIG_ACCESS | Z3_ADR<3> | Z3_ADR<4> | Z3_ADR<5> | RESET
INPUTMC | 7 | 12 | 10 | 6 | 8 | 6 | 9 | 5 | 16 | 13 | 12 | 6 | 16 | 6 | 15
INPUTP | 3 | 147 | 155 | 263
EQ | 6 |
!D_OUT<2>.D = !FCS & !UDS & Z3_ADR<2> & !Z3_ADR_1 & Z3_ADR_0 &
AUTOCONFIG_ACCESS & !Z3_ADR<3> & !Z3_ADR<4> & !Z3_ADR<5>
# !FCS & !UDS & !Z3_ADR<2> & !Z3_ADR_1 & !Z3_ADR_0 &
AUTOCONFIG_ACCESS & !Z3_ADR<3> & !Z3_ADR<4> & !Z3_ADR<5>;
D_OUT<2>.CLK = CLK_EXT; // GCK
D_OUT<2>.AP = !RESET;
GLOBALS | 1 | 2 | CLK_EXT
MACROCELL | 14 | 1 | D_OUT<3>
ATTRIBUTES | 8553348 | 0
OUTPUTMC | 1 | 4 | 14
INPUTS | 8 | FCS | UDS | Z3_ADR_1 | AUTOCONFIG_ACCESS | Z3_ADR<3> | Z3_ADR<4> | Z3_ADR<5> | RESET
INPUTMC | 5 | 6 | 8 | 5 | 16 | 13 | 12 | 6 | 16 | 6 | 15
INPUTP | 3 | 147 | 155 | 263
EQ | 4 |
!D_OUT<3>.D = !FCS & !UDS & !Z3_ADR_1 & AUTOCONFIG_ACCESS &
!Z3_ADR<3> & !Z3_ADR<4> & !Z3_ADR<5>;
D_OUT<3>.CLK = CLK_EXT; // GCK
D_OUT<3>.AP = !RESET;
GLOBALS | 1 | 2 | CLK_EXT
MACROCELL | 10 | 17 | D_OUT<4>
ATTRIBUTES | 8553348 | 0
OUTPUTMC | 1 | 4 | 16
INPUTS | 11 | FCS | UDS | Z3_ADR<2> | Z3_ADR_1 | Z3_ADR_0 | AUTOCONFIG_ACCESS | Z3_ADR<3> | Z3_ADR<4> | Z3_ADR<5> | Z3_ADR<6> | RESET
INPUTMC | 8 | 12 | 10 | 6 | 8 | 6 | 9 | 5 | 16 | 13 | 12 | 6 | 16 | 6 | 15 | 6 | 14
INPUTP | 3 | 147 | 155 | 263
EQ | 8 |
!D_OUT<4>.D = !FCS & !UDS & !Z3_ADR<2> & !Z3_ADR_1 & Z3_ADR_0 &
AUTOCONFIG_ACCESS & !Z3_ADR<3> & !Z3_ADR<4> & !Z3_ADR<5>
# !FCS & !UDS & !Z3_ADR<2> & !Z3_ADR_0 & !Z3_ADR<6> &
AUTOCONFIG_ACCESS & !Z3_ADR<3> & !Z3_ADR<4> & !Z3_ADR<5>
# !FCS & !UDS & !Z3_ADR_1 & Z3_ADR_0 & !Z3_ADR<6> &
AUTOCONFIG_ACCESS & !Z3_ADR<3> & !Z3_ADR<4> & !Z3_ADR<5>;
D_OUT<4>.CLK = CLK_EXT; // GCK
D_OUT<4>.AP = !RESET;
GLOBALS | 1 | 2 | CLK_EXT
MACROCELL | 10 | 15 | D_OUT<5>
ATTRIBUTES | 8553348 | 0
OUTPUTMC | 1 | 6 | 2
INPUTS | 11 | FCS | UDS | Z3_ADR<2> | Z3_ADR_1 | AUTOCONFIG_ACCESS | Z3_ADR<3> | Z3_ADR<4> | Z3_ADR<5> | Z3_ADR_0 | Z3_ADR<6> | RESET
INPUTMC | 8 | 12 | 10 | 6 | 8 | 5 | 16 | 13 | 12 | 6 | 16 | 6 | 15 | 6 | 9 | 6 | 14
INPUTP | 3 | 147 | 155 | 263
EQ | 8 |
!D_OUT<5>.D = !FCS & !UDS & !Z3_ADR<2> & !Z3_ADR_1 &
AUTOCONFIG_ACCESS & !Z3_ADR<3> & !Z3_ADR<4> & !Z3_ADR<5>
# !FCS & !UDS & !Z3_ADR<2> & !Z3_ADR_0 & Z3_ADR<6> &
AUTOCONFIG_ACCESS & !Z3_ADR<3> & !Z3_ADR<4> & !Z3_ADR<5>
# !FCS & !UDS & !Z3_ADR_1 & !Z3_ADR_0 & Z3_ADR<6> &
AUTOCONFIG_ACCESS & !Z3_ADR<3> & !Z3_ADR<4> & !Z3_ADR<5>;
D_OUT<5>.CLK = CLK_EXT; // GCK
D_OUT<5>.AP = !RESET;
GLOBALS | 1 | 2 | CLK_EXT
MACROCELL | 14 | 12 | D_OUT<6>
ATTRIBUTES | 8553348 | 0
OUTPUTMC | 1 | 6 | 4
INPUTS | 11 | FCS | UDS | Z3_ADR<2> | Z3_ADR_1 | Z3_ADR<6> | AUTOCONFIG_ACCESS | Z3_ADR<3> | Z3_ADR<4> | Z3_ADR<5> | Z3_ADR_0 | RESET
INPUTMC | 8 | 12 | 10 | 6 | 8 | 6 | 14 | 5 | 16 | 13 | 12 | 6 | 16 | 6 | 15 | 6 | 9
INPUTP | 3 | 147 | 155 | 263
EQ | 9 |
!D_OUT<6>.D = !FCS & !UDS & !Z3_ADR<2> & !Z3_ADR_1 & !Z3_ADR_0 &
AUTOCONFIG_ACCESS & !Z3_ADR<3> & !Z3_ADR<4> & !Z3_ADR<5>
# !FCS & !UDS & !Z3_ADR<2> & !Z3_ADR_1 & !Z3_ADR<6> &
AUTOCONFIG_ACCESS & !Z3_ADR<3> & !Z3_ADR<4> & !Z3_ADR<5>
# !FCS & !UDS & Z3_ADR<2> & !Z3_ADR_1 & Z3_ADR_0 &
Z3_ADR<6> & AUTOCONFIG_ACCESS & !Z3_ADR<3> & !Z3_ADR<4> &
!Z3_ADR<5>;
D_OUT<6>.CLK = CLK_EXT; // GCK
D_OUT<6>.AP = !RESET;
GLOBALS | 1 | 2 | CLK_EXT
MACROCELL | 14 | 0 | D_OUT<7>
ATTRIBUTES | 8553348 | 0
OUTPUTMC | 1 | 6 | 11
INPUTS | 9 | FCS | UDS | Z3_ADR_1 | Z3_ADR<6> | AUTOCONFIG_ACCESS | Z3_ADR<3> | Z3_ADR<4> | Z3_ADR<5> | RESET
INPUTMC | 6 | 6 | 8 | 6 | 14 | 5 | 16 | 13 | 12 | 6 | 16 | 6 | 15
INPUTP | 3 | 147 | 155 | 263
EQ | 4 |
!D_OUT<7>.D = !FCS & !UDS & !Z3_ADR_1 & Z3_ADR<6> &
AUTOCONFIG_ACCESS & !Z3_ADR<3> & !Z3_ADR<4> & !Z3_ADR<5>;
D_OUT<7>.CLK = CLK_EXT; // GCK
D_OUT<7>.AP = !RESET;
GLOBALS | 1 | 2 | CLK_EXT
MACROCELL | 4 | 7 | LAN_A_INIT<6>
ATTRIBUTES | 8553348 | 0
OUTPUTMC | 1 | 1 | 4
INPUTS | 2 | LAN_RST_SM_FSM_FFd1 | RESET
INPUTMC | 1 | 4 | 2
INPUTP | 1 | 263
EQ | 3 |
LAN_A_INIT<6>.D = !LAN_RST_SM_FSM_FFd1;
LAN_A_INIT<6>.CLK = CLK_EXT; // GCK
LAN_A_INIT<6>.AP = RESET;
GLOBALS | 1 | 2 | CLK_EXT
MACROCELL | 4 | 6 | LAN_CS_RST
ATTRIBUTES | 8553232 | 0
OUTPUTMC | 1 | 7 | 7
INPUTS | 3 | LAN_RST_SM_FSM_FFd2 | LAN_RST_SM_FSM_FFd3 | RESET
INPUTMC | 2 | 4 | 12 | 4 | 10
INPUTP | 1 | 263
EQ | 3 |
!LAN_CS_RST.D = !LAN_RST_SM_FSM_FFd2 & !LAN_RST_SM_FSM_FFd3;
LAN_CS_RST.CLK = CLK_EXT; // GCK
LAN_CS_RST.AR = RESET;
GLOBALS | 1 | 2 | CLK_EXT
MACROCELL | 3 | 12 | LAN_IRQ_D0
ATTRIBUTES | 8553344 | 0
OUTPUTMC | 1 | 5 | 15
INPUTS | 2 | LAN_INT | RESET
INPUTP | 2 | 201 | 263
EQ | 3 |
LAN_IRQ_D0.D = LAN_INT;
LAN_IRQ_D0.CLK = CLK_EXT; // GCK
LAN_IRQ_D0.AP = !RESET;
GLOBALS | 1 | 2 | CLK_EXT
MACROCELL | 8 | 15 | LAN_RD_S
ATTRIBUTES | 8553232 | 0
OUTPUTMC | 1 | 7 | 9
INPUTS | 6 | LAN_SM_FSM_FFd10 | LAN_SM_FSM_FFd6 | LAN_SM_FSM_FFd11 | LAN_SM_FSM_FFd12 | RW | LAN_SM_RST
INPUTMC | 5 | 8 | 14 | 8 | 2 | 8 | 12 | 9 | 6 | 3 | 8
INPUTP | 1 | 158
EQ | 6 |
!LAN_RD_S.D = !RW & !LAN_SM_FSM_FFd10 & !LAN_SM_FSM_FFd6 &
!LAN_SM_FSM_FFd11
# !LAN_SM_FSM_FFd10 & !LAN_SM_FSM_FFd6 &
!LAN_SM_FSM_FFd11 & !LAN_SM_FSM_FFd12;
LAN_RD_S.CLK = CLK_EXT; // GCK
LAN_RD_S.AR = LAN_SM_RST;
GLOBALS | 1 | 2 | CLK_EXT
MACROCELL | 15 | 0 | LAN_READY
ATTRIBUTES | 8553232 | 0
OUTPUTMC | 2 | 13 | 8 | 15 | 17
INPUTS | 11 | LAN_SM_FSM_FFd5 | LAN_SM_FSM_FFd10 | LAN_SM_FSM_FFd2 | LAN_SM_FSM_FFd1 | $OpTx$FX_DC$7 | LAN_SM_FSM_FFd7 | LAN_SM_FSM_FFd3 | LAN_SM_RST | LAN_SM_FSM_FFd8 | LAN_SM_FSM_FFd6 | LAN_SM_FSM_FFd12
INPUTMC | 11 | 8 | 3 | 8 | 14 | 12 | 6 | 6 | 6 | 12 | 3 | 8 | 9 | 8 | 11 | 3 | 8 | 8 | 8 | 8 | 2 | 9 | 6
EXPORTS | 1 | 15 | 17
EQ | 10 |
!LAN_READY.D = !LAN_SM_FSM_FFd5 & !LAN_SM_FSM_FFd10 &
!LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1 & !$OpTx$FX_DC$7
# !LAN_SM_FSM_FFd7 & !LAN_SM_FSM_FFd5 &
!LAN_SM_FSM_FFd10 & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd2 &
!LAN_SM_FSM_FFd1;
LAN_READY.CLK = CLK_EXT; // GCK
LAN_READY.AR = LAN_SM_RST;
LAN_READY.EXP = !LAN_SM_FSM_FFd7 & !LAN_SM_FSM_FFd10 &
!LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd8 & !LAN_SM_FSM_FFd2 &
!LAN_SM_FSM_FFd6 & !LAN_SM_FSM_FFd12
GLOBALS | 1 | 2 | CLK_EXT
MACROCELL | 12 | 15 | LAN_WRH_S
ATTRIBUTES | 8553232 | 0
OUTPUTMC | 1 | 7 | 4
INPUTS | 5 | LDS | LAN_SM_FSM_FFd9 | DS0 | LAN_SM_FSM_FFd8 | LAN_SM_RST
INPUTMC | 3 | 8 | 7 | 8 | 8 | 3 | 8
INPUTP | 2 | 157 | 170
EQ | 4 |
LAN_WRH_S.D = !LDS & LAN_SM_FSM_FFd9
# !DS0 & LAN_SM_FSM_FFd8;
LAN_WRH_S.CLK = CLK_EXT; // GCK
LAN_WRH_S.AR = LAN_SM_RST;
GLOBALS | 1 | 2 | CLK_EXT
MACROCELL | 12 | 14 | LAN_WRL_S
ATTRIBUTES | 8553232 | 0
OUTPUTMC | 1 | 12 | 13
INPUTS | 5 | UDS | LAN_SM_FSM_FFd9 | DS1 | LAN_SM_FSM_FFd8 | LAN_SM_RST
INPUTMC | 3 | 8 | 7 | 8 | 8 | 3 | 8
INPUTP | 2 | 155 | 148
EQ | 4 |
LAN_WRL_S.D = !UDS & LAN_SM_FSM_FFd9
# !DS1 & LAN_SM_FSM_FFd8;
LAN_WRL_S.CLK = CLK_EXT; // GCK
LAN_WRL_S.AR = LAN_SM_RST;
GLOBALS | 1 | 2 | CLK_EXT
MACROCELL | 15 | 17 | Z3_A_LOW
ATTRIBUTES | 8553232 | 0
OUTPUTMC | 1 | 3 | 5
INPUTS | 13 | UDS | LAN_SM_FSM_FFd10 | LAN_SM_FSM_FFd8 | LAN_SM_FSM_FFd2 | LAN_SM_FSM_FFd6 | $OpTx$FX_DC$7 | LDS | LAN_SM_FSM_FFd12 | LAN_SM_FSM_FFd7 | LAN_SM_FSM_FFd3 | LAN_SM_RST | LAN_READY.EXP | Z3_DATA<16>.EXP
INPUTMC | 11 | 8 | 14 | 8 | 8 | 12 | 6 | 8 | 2 | 12 | 3 | 9 | 6 | 8 | 9 | 8 | 11 | 3 | 8 | 15 | 0 | 15 | 16
INPUTP | 2 | 155 | 157
IMPORTS | 2 | 15 | 0 | 15 | 16
EQ | 20 |
!Z3_A_LOW.D = !UDS & !LAN_SM_FSM_FFd10 & !LAN_SM_FSM_FFd8 &
!LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd6 & $OpTx$FX_DC$7
# !LDS & !LAN_SM_FSM_FFd10 & !LAN_SM_FSM_FFd8 &
!LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd6 & $OpTx$FX_DC$7
# !LAN_SM_FSM_FFd10 & !LAN_SM_FSM_FFd8 &
!LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd6 & !LAN_SM_FSM_FFd12 &
$OpTx$FX_DC$7
# !UDS & !LAN_SM_FSM_FFd7 & !LAN_SM_FSM_FFd10 &
!LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd8 & !LAN_SM_FSM_FFd2 &
!LAN_SM_FSM_FFd6
;Imported pterms FB16_1
# !LAN_SM_FSM_FFd7 & !LAN_SM_FSM_FFd10 &
!LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd8 & !LAN_SM_FSM_FFd2 &
!LAN_SM_FSM_FFd6 & !LAN_SM_FSM_FFd12
;Imported pterms FB16_17
# !LDS & !LAN_SM_FSM_FFd7 & !LAN_SM_FSM_FFd10 &
!LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd8 & !LAN_SM_FSM_FFd2 &
!LAN_SM_FSM_FFd6;
Z3_A_LOW.CLK = CLK_EXT; // GCK
Z3_A_LOW.AR = LAN_SM_RST;
GLOBALS | 1 | 2 | CLK_EXT
MACROCELL | 3 | 8 | LAN_SM_RST
ATTRIBUTES | 8553216 | 0
OUTPUTMC | 65 | 8 | 10 | 15 | 5 | 15 | 2 | 15 | 1 | 14 | 16 | 14 | 14 | 14 | 13 | 8 | 13 | 8 | 16 | 10 | 2 | 10 | 4 | 10 | 9 | 10 | 10 | 12 | 7 | 15 | 10 | 15 | 7 | 15 | 16 | 15 | 15 | 15 | 14 | 15 | 13 | 15 | 12 | 14 | 10 | 14 | 9 | 14 | 8 | 15 | 11 | 15 | 8 | 15 | 6 | 15 | 4 | 15 | 3 | 14 | 7 | 14 | 6 | 14 | 5 | 8 | 9 | 8 | 3 | 8 | 14 | 8 | 11 | 8 | 8 | 12 | 6 | 8 | 2 | 8 | 7 | 6 | 6 | 8 | 12 | 12 | 5 | 9 | 17 | 9 | 15 | 8 | 17 | 4 | 17 | 7 | 17 | 7 | 16 | 3 | 17 | 6 | 17 | 9 | 14 | 11 | 17 | 4 | 15 | 7 | 15 | 7 | 14 | 11 | 16 | 9 | 12 | 11 | 15 | 8 | 15 | 15 | 0 | 12 | 15 | 12 | 14 | 15 | 17 | 9 | 6
INPUTS | 3 | Z3_ADR<13> | $OpTx$FX_DC$39 | $OpTx$FX_DC$27
INPUTMC | 3 | 12 | 11 | 8 | 6 | 3 | 10
EQ | 2 |
!LAN_SM_RST.D = !Z3_ADR<13> & !$OpTx$FX_DC$39 & $OpTx$FX_DC$27;
!LAN_SM_RST.CLK = CLK_EXT; // GCK
GLOBALS | 1 | 2 | CLK_EXT
MACROCELL | 9 | 6 | LAN_SM_FSM_FFd12
ATTRIBUTES | 8553348 | 0
OUTPUTMC | 26 | 8 | 14 | 8 | 8 | 8 | 7 | 8 | 12 | 9 | 16 | 9 | 0 | 8 | 0 | 4 | 16 | 8 | 4 | 7 | 0 | 3 | 0 | 6 | 16 | 9 | 13 | 7 | 17 | 4 | 14 | 7 | 14 | 7 | 13 | 11 | 0 | 9 | 11 | 11 | 14 | 8 | 15 | 15 | 17 | 4 | 8 | 8 | 5 | 11 | 17 | 15 | 0
INPUTS | 1 | LAN_SM_RST
INPUTMC | 1 | 3 | 8
EQ | 3 |
LAN_SM_FSM_FFd12.D = Gnd;
LAN_SM_FSM_FFd12.CLK = CLK_EXT; // GCK
LAN_SM_FSM_FFd12.AP = LAN_SM_RST;
GLOBALS | 1 | 2 | CLK_EXT
MACROCELL | 9 | 8 | LAN_A_INIT<3>
ATTRIBUTES | 8553348 | 0
OUTPUTMC | 1 | 3 | 7
INPUTS | 1 | RESET
INPUTP | 1 | 263
EQ | 3 |
LAN_A_INIT<3>.D = Gnd;
LAN_A_INIT<3>.CLK = CLK_EXT; // GCK
LAN_A_INIT<3>.AP = RESET;
GLOBALS | 1 | 2 | CLK_EXT
MACROCELL | 3 | 5 | A_LAN_0_OBUF
ATTRIBUTES | 264962 | 0
INPUTS | 2 | RESET | Z3_A_LOW
INPUTMC | 1 | 15 | 17
INPUTP | 1 | 263
EQ | 1 |
!A_LAN<0> = RESET & !Z3_A_LOW;
MACROCELL | 5 | 5 | A_LAN_10_OBUF
ATTRIBUTES | 264962 | 0
INPUTS | 2 | RESET | Z3_ADR<9>
INPUTMC | 1 | 6 | 10
INPUTP | 1 | 263
EQ | 1 |
!A_LAN<10> = RESET & !Z3_ADR<9>;
MACROCELL | 5 | 7 | A_LAN_11_OBUF
ATTRIBUTES | 264962 | 0
INPUTS | 2 | RESET | Z3_ADR<10>
INPUTMC | 1 | 13 | 16
INPUTP | 1 | 263
EQ | 1 |
!A_LAN<11> = RESET & !Z3_ADR<10>;
MACROCELL | 5 | 2 | A_LAN_12_OBUF
ATTRIBUTES | 264962 | 0
INPUTS | 2 | RESET | Z3_ADR<11>
INPUTMC | 1 | 13 | 15
INPUTP | 1 | 263
EQ | 1 |
!A_LAN<12> = RESET & !Z3_ADR<11>;
MACROCELL | 5 | 4 | A_LAN_13_OBUF
ATTRIBUTES | 264962 | 0
INPUTS | 2 | RESET | Z3_ADR<12>
INPUTMC | 1 | 12 | 12
INPUTP | 1 | 263
EQ | 1 |
!A_LAN<13> = RESET & !Z3_ADR<12>;
MACROCELL | 3 | 4 | A_LAN_1_OBUF
ATTRIBUTES | 264962 | 0
INPUTS | 2 | RESET | Z3_ADR_0
INPUTMC | 1 | 6 | 9
INPUTP | 1 | 263
EQ | 1 |
!A_LAN<1> = RESET & !Z3_ADR_0;
MACROCELL | 3 | 11 | A_LAN_2_OBUF
ATTRIBUTES | 264962 | 0
INPUTS | 2 | RESET | Z3_ADR_1
INPUTMC | 1 | 6 | 8
INPUTP | 1 | 263
EQ | 1 |
!A_LAN<2> = RESET & !Z3_ADR_1;
MACROCELL | 3 | 7 | A_LAN_3_OBUF
ATTRIBUTES | 264962 | 0
INPUTS | 3 | RESET | LAN_A_INIT<3> | Z3_ADR<2>
INPUTMC | 2 | 9 | 8 | 12 | 10
INPUTP | 1 | 263
EQ | 2 |
A_LAN<3> = RESET & Z3_ADR<2>
# !RESET & LAN_A_INIT<3>;
MACROCELL | 1 | 1 | A_LAN_4_OBUF
ATTRIBUTES | 264962 | 0
INPUTS | 2 | RESET | Z3_ADR<3>
INPUTMC | 1 | 13 | 12
INPUTP | 1 | 263
EQ | 1 |
!A_LAN<4> = RESET & !Z3_ADR<3>;
MACROCELL | 3 | 13 | A_LAN_5_OBUF
ATTRIBUTES | 264962 | 0
INPUTS | 2 | RESET | Z3_ADR<4>
INPUTMC | 1 | 6 | 16
INPUTP | 1 | 263
EQ | 1 |
!A_LAN<5> = RESET & !Z3_ADR<4>;
MACROCELL | 1 | 4 | A_LAN_6_OBUF
ATTRIBUTES | 264962 | 0
INPUTS | 3 | RESET | Z3_ADR<5> | LAN_A_INIT<6>
INPUTMC | 2 | 6 | 15 | 4 | 7
INPUTP | 1 | 263
EQ | 2 |
A_LAN<6> = RESET & Z3_ADR<5>
# !RESET & LAN_A_INIT<6>;
MACROCELL | 1 | 2 | A_LAN_7_OBUF
ATTRIBUTES | 264962 | 0
INPUTS | 2 | RESET | Z3_ADR<6>
INPUTMC | 1 | 6 | 14
INPUTP | 1 | 263
EQ | 1 |
!A_LAN<7> = RESET & !Z3_ADR<6>;
MACROCELL | 5 | 9 | A_LAN_8_OBUF
ATTRIBUTES | 264962 | 0
INPUTS | 2 | RESET | Z3_ADR<7>
INPUTMC | 1 | 6 | 13
INPUTP | 1 | 263
EQ | 1 |
!A_LAN<8> = RESET & !Z3_ADR<7>;
MACROCELL | 5 | 13 | A_LAN_9_OBUF
ATTRIBUTES | 264962 | 0
INPUTS | 2 | RESET | Z3_ADR<8>
INPUTMC | 1 | 6 | 12
INPUTP | 1 | 263
EQ | 1 |
!A_LAN<9> = RESET & !Z3_ADR<8>;
MACROCELL | 7 | 7 | LAN_CS_OBUF
ATTRIBUTES | 264962 | 0
INPUTS | 3 | RESET | LAN_CS_RST | LAN_ACCESS
INPUTMC | 2 | 4 | 6 | 12 | 16
INPUTP | 1 | 263
EQ | 2 |
LAN_CS = RESET & LAN_ACCESS
# !RESET & LAN_CS_RST;
MACROCELL | 7 | 4 | LAN_WRH_OBUF
ATTRIBUTES | 264962 | 0
INPUTS | 3 | LAN_WR_RST | $OpTx$FX_DC$27 | LAN_WRH_S
INPUTMC | 3 | 4 | 0 | 3 | 10 | 12 | 15
EQ | 2 |
LAN_WRH = LAN_WR_RST & !$OpTx$FX_DC$27
# LAN_WRH_S & $OpTx$FX_DC$27;
MACROCELL | 12 | 13 | LAN_WRL_OBUF
ATTRIBUTES | 264962 | 0
INPUTS | 3 | LAN_WR_RST | $OpTx$FX_DC$27 | LAN_WRL_S
INPUTMC | 3 | 4 | 0 | 3 | 10 | 12 | 14
EQ | 2 |
LAN_WRL = LAN_WR_RST & !$OpTx$FX_DC$27
# LAN_WRL_S & $OpTx$FX_DC$27;
MACROCELL | 7 | 9 | LAN_RD_OBUF
ATTRIBUTES | 264962 | 0
INPUTS | 2 | LAN_RD_S | $OpTx$FX_DC$27
INPUTMC | 2 | 8 | 15 | 3 | 10
EQ | 1 |
LAN_RD = LAN_RD_S & $OpTx$FX_DC$27;
MACROCELL | 13 | 2 | N0$BUF0
ATTRIBUTES | 265986 | 0
INPUTS | 1 | SLAVE
INPUTMC | 1 | 13 | 13
EQ | 2 |
OVR = Gnd;
OVR.OE = !SLAVE;
MACROCELL | 2 | 13 | N0$BUF6
ATTRIBUTES | 265986 | 0
INPUTS | 2 | LAN_INT_ENABLE | LAN_IRQ_OUT
INPUTMC | 2 | 3 | 16 | 5 | 15
EQ | 2 |
INT_OUT = Gnd;
INT_OUT.OE = LAN_INT_ENABLE & !LAN_IRQ_OUT;
MACROCELL | 14 | 11 | N0$BUF7
ATTRIBUTES | 265986 | 0
INPUTS | 1 | N0$BUF7/N0$BUF7_TRST
INPUTMC | 1 | 13 | 8
EQ | 2 |
DTACK = Gnd;
DTACK.OE = !N0$BUF7/N0$BUF7_TRST;
MACROCELL | 13 | 10 | CFOUT_OBUF
ATTRIBUTES | 8815558 | 0
OUTPUTMC | 1 | 5 | 16
INPUTS | 4 | AUTO_CONFIG_DONE_CYCLE | AUTOBOOT_OFF | RESET | FCS
INPUTMC | 1 | 14 | 4
INPUTP | 3 | 142 | 263 | 147
EQ | 4 |
CFOUT.D = !AUTO_CONFIG_DONE_CYCLE & AUTOBOOT_OFF;
CFOUT.CLK = CLK_EXT; // GCK
CFOUT.AP = !RESET;
CFOUT.CE = FCS;
GLOBALS | 1 | 2 | CLK_EXT
MACROCELL | 13 | 13 | SLAVE_OBUF
ATTRIBUTES | 396034 | 0
OUTPUTMC | 2 | 13 | 2 | 14 | 17
INPUTS | 3 | FCS | LAN_ACCESS | AUTOCONFIG_ACCESS
INPUTMC | 2 | 12 | 16 | 5 | 16
INPUTP | 1 | 147
EQ | 2 |
SLAVE = FCS
# !LAN_ACCESS & !AUTOCONFIG_ACCESS;
MACROCELL | 13 | 14 | N0
ATTRIBUTES | 265986 | 0
INPUTS | 0
EQ | 2 |
OWN = Gnd;
OWN.OE = Gnd;
MACROCELL | 15 | 9 | N0$BUF1
ATTRIBUTES | 265986 | 0
INPUTS | 0
EQ | 2 |
MTACK = Gnd;
MTACK.OE = Gnd;
MACROCELL | 11 | 1 | N0$BUF2
ATTRIBUTES | 265986 | 0
INPUTS | 0
EQ | 2 |
LAN_CFG<4> = Gnd;
LAN_CFG<4>.OE = Gnd;
MACROCELL | 1 | 7 | N0$BUF3
ATTRIBUTES | 265986 | 0
INPUTS | 0
EQ | 2 |
LAN_CFG<3> = Gnd;
LAN_CFG<3>.OE = Gnd;
MACROCELL | 5 | 1 | N0$BUF4
ATTRIBUTES | 265986 | 0
INPUTS | 0
EQ | 2 |
LAN_CFG<2> = Gnd;
LAN_CFG<2>.OE = Gnd;
MACROCELL | 1 | 5 | N0$BUF5
ATTRIBUTES | 265986 | 0
INPUTS | 0
EQ | 2 |
LAN_CFG<1> = Gnd;
LAN_CFG<1>.OE = Gnd;
MACROCELL | 4 | 4 | ROM_B_0_OBUF
ATTRIBUTES | 264962 | 0
INPUTS | 0
EQ | 1 |
ROM_OE = Vcc;
MACROCELL | 10 | 13 | ROM_B_0_OBUF$BUF0
ATTRIBUTES | 264962 | 0
INPUTS | 0
EQ | 1 |
ROM_B<1> = Vcc;
MACROCELL | 10 | 11 | ROM_B_0_OBUF$BUF1
ATTRIBUTES | 264962 | 0
INPUTS | 0
EQ | 1 |
ROM_B<0> = Vcc;
MACROCELL | 12 | 1 | ROM_B_0_OBUF$BUF10
ATTRIBUTES | 264962 | 0
INPUTS | 0
EQ | 1 |
CP_RD = Vcc;
MACROCELL | 4 | 1 | ROM_B_0_OBUF$BUF11
ATTRIBUTES | 264962 | 0
INPUTS | 0
EQ | 1 |
CP_CS = Vcc;
MACROCELL | 2 | 1 | ROM_B_0_OBUF$BUF2
ATTRIBUTES | 264962 | 0
INPUTS | 0
EQ | 1 |
IDE_W = Vcc;
MACROCELL | 0 | 16 | ROM_B_0_OBUF$BUF3
ATTRIBUTES | 264962 | 0
INPUTS | 0
EQ | 1 |
IDE_R = Vcc;
MACROCELL | 0 | 9 | ROM_B_0_OBUF$BUF4
ATTRIBUTES | 264962 | 0
INPUTS | 0
EQ | 1 |
IDE_CS<1> = Vcc;
MACROCELL | 0 | 7 | ROM_B_0_OBUF$BUF5
ATTRIBUTES | 264962 | 0
INPUTS | 0
EQ | 1 |
IDE_CS<0> = Vcc;
MACROCELL | 0 | 13 | ROM_B_0_OBUF$BUF6
ATTRIBUTES | 264962 | 0
INPUTS | 0
EQ | 1 |
IDE_A<2> = Vcc;
MACROCELL | 0 | 14 | ROM_B_0_OBUF$BUF7
ATTRIBUTES | 264962 | 0
INPUTS | 0
EQ | 1 |
IDE_A<1> = Vcc;
MACROCELL | 0 | 11 | ROM_B_0_OBUF$BUF8
ATTRIBUTES | 264962 | 0
INPUTS | 0
EQ | 1 |
IDE_A<0> = Vcc;
MACROCELL | 10 | 16 | ROM_B_0_OBUF$BUF9
ATTRIBUTES | 264962 | 0
INPUTS | 0
EQ | 1 |
CP_WE = Vcc;
MACROCELL | 8 | 6 | $OpTx$FX_DC$39
ATTRIBUTES | 133888 | 0
OUTPUTMC | 19 | 8 | 10 | 15 | 5 | 15 | 2 | 15 | 1 | 14 | 16 | 14 | 14 | 14 | 13 | 8 | 13 | 8 | 16 | 10 | 2 | 10 | 4 | 10 | 9 | 10 | 10 | 12 | 7 | 15 | 10 | 15 | 7 | 3 | 8 | 3 | 14 | 8 | 0
INPUTS | 4 | LAN_ACCESS | UDS | LDS | $OpTx$FX_DC$7
INPUTMC | 2 | 12 | 16 | 12 | 3
INPUTP | 2 | 155 | 157
EQ | 2 |
$OpTx$FX_DC$39 = !LAN_ACCESS
# UDS & LDS & $OpTx$FX_DC$7;
MACROCELL | 12 | 3 | $OpTx$FX_DC$7
ATTRIBUTES | 133888 | 0
OUTPUTMC | 8 | 8 | 9 | 8 | 11 | 8 | 8 | 8 | 2 | 15 | 0 | 15 | 17 | 8 | 6 | 14 | 17
INPUTS | 2 | DS1 | DS0
INPUTP | 2 | 148 | 170
EQ | 1 |
$OpTx$FX_DC$7 = DS1 & DS0;
MACROCELL | 3 | 9 | CONFIG_READY/CONFIG_READY_CE
ATTRIBUTES | 133888 | 0
OUTPUTMC | 1 | 3 | 16
INPUTS | 4 | RW | FCS | LAN_ACCESS | Z3_ADR<13>
INPUTMC | 2 | 12 | 16 | 12 | 11
INPUTP | 2 | 158 | 147
EQ | 1 |
CONFIG_READY/CONFIG_READY_CE = !RW & !FCS & LAN_ACCESS & Z3_ADR<13>;
MACROCELL | 3 | 14 | DQ_10_IOBUFE/DQ_10_IOBUFE_TRST
ATTRIBUTES | 133888 | 0
OUTPUTMC | 16 | 9 | 16 | 11 | 9 | 9 | 1 | 9 | 9 | 9 | 13 | 11 | 11 | 9 | 2 | 7 | 1 | 11 | 7 | 7 | 2 | 11 | 4 | 9 | 5 | 9 | 4 | 9 | 7 | 9 | 11 | 9 | 10
INPUTS | 4 | RESET | FCS | $OpTx$FX_DC$39 | Z3_DATA<8>/Z3_DATA<8>_TRST
INPUTMC | 2 | 8 | 6 | 8 | 0
INPUTP | 2 | 263 | 147
EQ | 3 |
DQ_10_IOBUFE/DQ_10_IOBUFE_TRST = !RESET
# !FCS & !$OpTx$FX_DC$39 &
!Z3_DATA<8>/Z3_DATA<8>_TRST;
MACROCELL | 8 | 0 | Z3_DATA<8>/Z3_DATA<8>_TRST
ATTRIBUTES | 133888 | 0
OUTPUTMC | 19 | 3 | 1 | 4 | 13 | 4 | 14 | 4 | 16 | 6 | 2 | 6 | 4 | 6 | 11 | 1 | 14 | 4 | 9 | 1 | 11 | 0 | 5 | 0 | 4 | 1 | 9 | 1 | 13 | 1 | 16 | 4 | 11 | 3 | 14 | 14 | 17 | 8 | 17
INPUTS | 7 | RW | FCS | $OpTx$FX_DC$39 | LDS | D<3>.PIN | LAN_SM_FSM_FFd12 | $OpTx$FX_DC$11
INPUTMC | 3 | 8 | 6 | 9 | 6 | 12 | 4
INPUTP | 4 | 158 | 147 | 157 | 28
EXPORTS | 1 | 8 | 17
EQ | 3 |
Z3_DATA<8>/Z3_DATA<8>_TRST = RW & !FCS & !$OpTx$FX_DC$39;
Z3_DATA<8>/Z3_DATA<8>_TRST.EXP = !LDS & D<3>.PIN & LAN_SM_FSM_FFd12 &
!$OpTx$FX_DC$11
MACROCELL | 14 | 17 | D_9_IOBUFE/D_9_IOBUFE_TRST
ATTRIBUTES | 133888 | 0
OUTPUTMC | 16 | 3 | 1 | 4 | 13 | 4 | 14 | 4 | 16 | 6 | 2 | 6 | 4 | 6 | 11 | 1 | 14 | 4 | 9 | 1 | 11 | 0 | 5 | 0 | 4 | 1 | 9 | 1 | 13 | 1 | 16 | 4 | 11
INPUTS | 8 | Z3_DATA<8>/Z3_DATA<8>_TRST | RW | LDS | SLAVE | $OpTx$FX_DC$7 | FCS | UDS | AUTOCONFIG_ACCESS
INPUTMC | 4 | 8 | 0 | 13 | 13 | 12 | 3 | 5 | 16
INPUTP | 4 | 158 | 157 | 147 | 155
EQ | 4 |
D_9_IOBUFE/D_9_IOBUFE_TRST = Z3_DATA<8>/Z3_DATA<8>_TRST
# RW & !LDS & !SLAVE
# RW & !SLAVE & !$OpTx$FX_DC$7
# RW & !FCS & !UDS & AUTOCONFIG_ACCESS;
MACROCELL | 7 | 0 | Z3_ADR_1/Z3_ADR_1_SETF
ATTRIBUTES | 133888 | 0
OUTPUTMC | 18 | 12 | 17 | 12 | 10 | 6 | 8 | 6 | 9 | 6 | 14 | 12 | 16 | 5 | 16 | 13 | 12 | 6 | 16 | 6 | 15 | 12 | 11 | 13 | 16 | 13 | 15 | 12 | 12 | 6 | 13 | 6 | 12 | 6 | 10 | 7 | 17
INPUTS | 9 | RESET | BERR | A<21>.PIN | $OpTx$FX_DC$734 | $OpTx$FX_DC$17 | LDS | D<5>.PIN | LAN_SM_FSM_FFd12 | $OpTx$FX_DC$11
INPUTMC | 4 | 8 | 5 | 12 | 9 | 9 | 6 | 12 | 4
INPUTP | 5 | 263 | 176 | 163 | 157 | 37
EXPORTS | 1 | 7 | 17
EQ | 4 |
Z3_ADR_1/Z3_ADR_1_SETF = RESET & BERR;
Z3_ADR_1/Z3_ADR_1_SETF.EXP = A<21>.PIN & $OpTx$FX_DC$734 & $OpTx$FX_DC$17
# !LDS & D<5>.PIN & LAN_SM_FSM_FFd12 &
!$OpTx$FX_DC$11
MACROCELL | 0 | 17 | $OpTx$FX_DC$46
ATTRIBUTES | 133888 | 0
OUTPUTMC | 2 | 12 | 17 | 12 | 16
INPUTS | 2 | D<8>.PIN | LAN_BASEADR<8>
INPUTMC | 1 | 10 | 1
INPUTP | 1 | 32
EQ | 2 |
$OpTx$FX_DC$46 = D<8>.PIN
$ LAN_BASEADR<8>;
MACROCELL | 6 | 7 | $OpTx$FX_DC$45
ATTRIBUTES | 133888 | 0
OUTPUTMC | 2 | 12 | 17 | 12 | 16
INPUTS | 2 | D<9>.PIN | LAN_BASEADR<9>
INPUTMC | 1 | 10 | 0
INPUTP | 1 | 73
EQ | 2 |
$OpTx$FX_DC$45 = D<9>.PIN
$ LAN_BASEADR<9>;
MACROCELL | 13 | 9 | $OpTx$FX_DC$44
ATTRIBUTES | 133888 | 0
OUTPUTMC | 2 | 12 | 17 | 12 | 16
INPUTS | 2 | D<10>.PIN | LAN_BASEADR<10>
INPUTMC | 1 | 10 | 12
INPUTP | 1 | 74
EQ | 2 |
$OpTx$FX_DC$44 = D<10>.PIN
$ LAN_BASEADR<10>;
MACROCELL | 13 | 11 | $OpTx$FX_DC$43
ATTRIBUTES | 133888 | 0
OUTPUTMC | 2 | 12 | 17 | 12 | 16
INPUTS | 2 | D<11>.PIN | LAN_BASEADR<11>
INPUTMC | 1 | 10 | 8
INPUTP | 1 | 77
EQ | 2 |
$OpTx$FX_DC$43 = D<11>.PIN
$ LAN_BASEADR<11>;
MACROCELL | 0 | 15 | $OpTx$FX_DC$47
ATTRIBUTES | 133888 | 0
OUTPUTMC | 2 | 12 | 17 | 12 | 16
INPUTS | 2 | D<15>.PIN | LAN_BASEADR<15>
INPUTMC | 1 | 1 | 15
INPUTP | 1 | 89
EQ | 2 |
$OpTx$FX_DC$47 = D<15>.PIN
$ LAN_BASEADR<15>;
MACROCELL | 5 | 17 | $OpTx$INV$2
ATTRIBUTES | 133888 | 0
OUTPUTMC | 2 | 12 | 17 | 12 | 16
INPUTS | 4 | LAN_BASEADR<6> | A<22>.PIN | D<13>.PIN | LAN_BASEADR<13>
INPUTMC | 2 | 10 | 5 | 10 | 6
INPUTP | 2 | 162 | 80
EQ | 4 |
$OpTx$INV$2 = D<13>.PIN & !LAN_BASEADR<13>
# !D<13>.PIN & LAN_BASEADR<13>
# LAN_BASEADR<6> & !A<22>.PIN
# !LAN_BASEADR<6> & A<22>.PIN;
MACROCELL | 13 | 0 | $OpTx$INV$1
ATTRIBUTES | 133888 | 0
OUTPUTMC | 2 | 12 | 17 | 12 | 16
INPUTS | 8 | A<16>.PIN | LAN_BASEADR<0> | A<17>.PIN | LAN_BASEADR<1> | A<18>.PIN | LAN_BASEADR<2> | EXP27_.EXP | EXP28_.EXP
INPUTMC | 5 | 10 | 14 | 1 | 12 | 1 | 10 | 13 | 1 | 13 | 17
INPUTP | 3 | 175 | 172 | 171
IMPORTS | 2 | 13 | 1 | 13 | 17
EQ | 19 |
$OpTx$INV$1 = A<18>.PIN & !LAN_BASEADR<2>
# A<17>.PIN & !LAN_BASEADR<1>
# !A<17>.PIN & LAN_BASEADR<1>
# A<16>.PIN & !LAN_BASEADR<0>
# !A<16>.PIN & LAN_BASEADR<0>
;Imported pterms FB14_2
# D<14>.PIN & !LAN_BASEADR<14>
# LAN_BASEADR<5> & !A<21>.PIN
# !LAN_BASEADR<5> & A<21>.PIN
# LAN_BASEADR<7> & !A<23>.PIN
# !LAN_BASEADR<7> & A<23>.PIN
;Imported pterms FB14_18
# A<20>.PIN & !LAN_BASEADR<4>
# !A<20>.PIN & LAN_BASEADR<4>
# A<19>.PIN & !LAN_BASEADR<3>
# !A<19>.PIN & LAN_BASEADR<3>
# !A<18>.PIN & LAN_BASEADR<2>
;Imported pterms FB14_17
# !D<14>.PIN & LAN_BASEADR<14>;
MACROCELL | 4 | 8 | $OpTx$FX_SC$33
ATTRIBUTES | 133888 | 0
OUTPUTMC | 8 | 9 | 17 | 6 | 17 | 9 | 14 | 11 | 17 | 4 | 15 | 7 | 15 | 7 | 14 | 11 | 16
INPUTS | 4 | LAN_SM_FSM_FFd12 | $OpTx$FX_DC$10 | UDS | LDS
INPUTMC | 2 | 9 | 6 | 8 | 1
INPUTP | 2 | 155 | 157
EQ | 2 |
$OpTx$FX_SC$33 = LAN_SM_FSM_FFd12 & $OpTx$FX_DC$10
# !UDS & LDS & LAN_SM_FSM_FFd12;
MACROCELL | 8 | 1 | $OpTx$FX_DC$10
ATTRIBUTES | 133888 | 0
OUTPUTMC | 9 | 9 | 0 | 6 | 16 | 9 | 13 | 4 | 8 | 4 | 14 | 7 | 14 | 7 | 13 | 11 | 0 | 11 | 17
INPUTS | 2 | UDS | DQ_SWAP
INPUTMC | 1 | 12 | 17
INPUTP | 1 | 155
EQ | 1 |
$OpTx$FX_DC$10 = !UDS & DQ_SWAP;
MACROCELL | 0 | 12 | $OpTx$FX_DC$22
ATTRIBUTES | 133888 | 0
OUTPUTMC | 16 | 9 | 17 | 9 | 15 | 8 | 17 | 4 | 17 | 7 | 17 | 7 | 16 | 3 | 17 | 6 | 17 | 9 | 14 | 11 | 17 | 4 | 15 | 7 | 15 | 7 | 14 | 11 | 16 | 9 | 12 | 11 | 15
INPUTS | 10 | LAN_SM_FSM_FFd7 | LAN_SM_FSM_FFd5 | LAN_SM_FSM_FFd10 | LAN_SM_FSM_FFd8 | LAN_SM_FSM_FFd2 | LAN_SM_FSM_FFd6 | LAN_SM_FSM_FFd9 | LAN_SM_FSM_FFd1 | LAN_SM_FSM_FFd11 | LAN_SM_FSM_FFd4
INPUTMC | 10 | 8 | 9 | 8 | 3 | 8 | 14 | 8 | 8 | 12 | 6 | 8 | 2 | 8 | 7 | 6 | 6 | 8 | 12 | 12 | 5
EQ | 4 |
$OpTx$FX_DC$22 = !LAN_SM_FSM_FFd7 & !LAN_SM_FSM_FFd5 &
!LAN_SM_FSM_FFd10 & !LAN_SM_FSM_FFd8 & !LAN_SM_FSM_FFd2 &
!LAN_SM_FSM_FFd6 & !LAN_SM_FSM_FFd9 & !LAN_SM_FSM_FFd1 &
!LAN_SM_FSM_FFd11 & !LAN_SM_FSM_FFd4;
MACROCELL | 12 | 8 | $OpTx$FX_DC$18
ATTRIBUTES | 133888 | 0
OUTPUTMC | 10 | 9 | 17 | 6 | 17 | 9 | 14 | 11 | 17 | 4 | 15 | 7 | 15 | 7 | 14 | 11 | 16 | 7 | 13 | 11 | 0
INPUTS | 3 | DS1 | DS0 | DQ_SWAP
INPUTMC | 1 | 12 | 17
INPUTP | 2 | 148 | 170
EQ | 2 |
$OpTx$FX_DC$18 = DS1
# !DS0 & !DQ_SWAP;
MACROCELL | 8 | 5 | $OpTx$FX_DC$734
ATTRIBUTES | 133888 | 0
OUTPUTMC | 19 | 9 | 17 | 9 | 15 | 8 | 17 | 4 | 17 | 7 | 17 | 7 | 16 | 3 | 17 | 6 | 17 | 9 | 14 | 11 | 17 | 4 | 15 | 7 | 15 | 7 | 14 | 11 | 16 | 9 | 12 | 11 | 15 | 7 | 0 | 7 | 13 | 11 | 0
INPUTS | 4 | LAN_SM_FSM_FFd3 | UDS | LDS | LAN_SM_FSM_FFd12
INPUTMC | 2 | 8 | 11 | 9 | 6
INPUTP | 2 | 155 | 157
EQ | 2 |
$OpTx$FX_DC$734 = LAN_SM_FSM_FFd3
# UDS & LDS & LAN_SM_FSM_FFd12;
MACROCELL | 8 | 4 | $OpTx$FX_SC$31
ATTRIBUTES | 133888 | 0
OUTPUTMC | 8 | 9 | 15 | 8 | 17 | 4 | 17 | 7 | 17 | 7 | 16 | 3 | 17 | 9 | 12 | 11 | 15
INPUTS | 4 | LAN_SM_FSM_FFd12 | $OpTx$FX_DC$11 | UDS | LDS
INPUTMC | 2 | 9 | 6 | 12 | 4
INPUTP | 2 | 155 | 157
EQ | 2 |
$OpTx$FX_SC$31 = LAN_SM_FSM_FFd12 & $OpTx$FX_DC$11
# !UDS & LDS & LAN_SM_FSM_FFd12;
MACROCELL | 12 | 4 | $OpTx$FX_DC$11
ATTRIBUTES | 133888 | 0
OUTPUTMC | 9 | 7 | 17 | 8 | 0 | 4 | 16 | 8 | 4 | 7 | 0 | 3 | 0 | 9 | 11 | 11 | 14 | 9 | 16
INPUTS | 2 | UDS | DQ_SWAP
INPUTMC | 1 | 12 | 17
INPUTP | 1 | 155
EQ | 1 |
$OpTx$FX_DC$11 = !UDS & !DQ_SWAP;
MACROCELL | 12 | 9 | $OpTx$FX_DC$17
ATTRIBUTES | 133888 | 0
OUTPUTMC | 9 | 9 | 15 | 8 | 17 | 4 | 17 | 7 | 17 | 7 | 16 | 3 | 17 | 9 | 12 | 11 | 15 | 7 | 0
INPUTS | 3 | DS0 | DS1 | DQ_SWAP
INPUTMC | 1 | 12 | 17
INPUTP | 2 | 170 | 148
EQ | 2 |
$OpTx$FX_DC$17 = DS0
# !DS1 & !DQ_SWAP;
MACROCELL | 3 | 10 | $OpTx$FX_DC$27
ATTRIBUTES | 133888 | 0
OUTPUTMC | 4 | 3 | 8 | 7 | 4 | 12 | 13 | 7 | 9
INPUTS | 2 | FCS | RESET
INPUTP | 2 | 147 | 263
EQ | 1 |
$OpTx$FX_DC$27 = !FCS & RESET;
MACROCELL | 13 | 8 | N0$BUF7/N0$BUF7_TRST
ATTRIBUTES | 133888 | 0
OUTPUTMC | 1 | 14 | 11
INPUTS | 4 | FCS | AUTOCONFIG_ACCESS | CONFIG_READY | LAN_READY
INPUTMC | 3 | 5 | 16 | 3 | 15 | 15 | 0
INPUTP | 1 | 147
EQ | 2 |
N0$BUF7/N0$BUF7_TRST = FCS
# !AUTOCONFIG_ACCESS & !CONFIG_READY & !LAN_READY;
MACROCELL | 3 | 0 | EXP22_
ATTRIBUTES | 2048 | 0
OUTPUTMC | 1 | 3 | 17
INPUTS | 4 | LDS | D<7>.PIN | LAN_SM_FSM_FFd12 | $OpTx$FX_DC$11
INPUTMC | 2 | 9 | 6 | 12 | 4
INPUTP | 2 | 157 | 29
EXPORTS | 1 | 3 | 17
EQ | 2 |
EXP22_.EXP = !LDS & D<7>.PIN & LAN_SM_FSM_FFd12 &
!$OpTx$FX_DC$11
MACROCELL | 7 | 13 | EXP23_
ATTRIBUTES | 2048 | 0
OUTPUTMC | 1 | 7 | 14
INPUTS | 7 | A<22>.PIN | $OpTx$FX_DC$18 | $OpTx$FX_DC$734 | LDS | D<6>.PIN | LAN_SM_FSM_FFd12 | $OpTx$FX_DC$10
INPUTMC | 4 | 12 | 8 | 8 | 5 | 9 | 6 | 8 | 1
INPUTP | 3 | 162 | 157 | 26
EXPORTS | 1 | 7 | 14
EQ | 3 |
EXP23_.EXP = A<22>.PIN & !$OpTx$FX_DC$18 & $OpTx$FX_DC$734
# !LDS & D<6>.PIN & LAN_SM_FSM_FFd12 &
!$OpTx$FX_DC$10
MACROCELL | 9 | 0 | EXP24_
ATTRIBUTES | 2048 | 0
OUTPUTMC | 1 | 9 | 17
INPUTS | 4 | LDS | D<0>.PIN | LAN_SM_FSM_FFd12 | $OpTx$FX_DC$10
INPUTMC | 2 | 9 | 6 | 8 | 1
INPUTP | 2 | 157 | 4
EXPORTS | 1 | 9 | 17
EQ | 2 |
EXP24_.EXP = !LDS & D<0>.PIN & LAN_SM_FSM_FFd12 &
!$OpTx$FX_DC$10
MACROCELL | 11 | 0 | EXP25_
ATTRIBUTES | 2048 | 0
OUTPUTMC | 1 | 11 | 17
INPUTS | 7 | A<19>.PIN | $OpTx$FX_DC$18 | $OpTx$FX_DC$734 | LDS | D<3>.PIN | LAN_SM_FSM_FFd12 | $OpTx$FX_DC$10
INPUTMC | 4 | 12 | 8 | 8 | 5 | 9 | 6 | 8 | 1
INPUTP | 3 | 169 | 157 | 28
EXPORTS | 1 | 11 | 17
EQ | 3 |
EXP25_.EXP = A<19>.PIN & !$OpTx$FX_DC$18 & $OpTx$FX_DC$734
# !LDS & D<3>.PIN & LAN_SM_FSM_FFd12 &
!$OpTx$FX_DC$10
MACROCELL | 11 | 14 | EXP26_
ATTRIBUTES | 2048 | 0
OUTPUTMC | 1 | 11 | 15
INPUTS | 4 | LDS | D<1>.PIN | LAN_SM_FSM_FFd12 | $OpTx$FX_DC$11
INPUTMC | 2 | 9 | 6 | 12 | 4
INPUTP | 2 | 157 | 30
EXPORTS | 1 | 11 | 15
EQ | 2 |
EXP26_.EXP = !LDS & D<1>.PIN & LAN_SM_FSM_FFd12 &
!$OpTx$FX_DC$11
MACROCELL | 13 | 1 | EXP27_
ATTRIBUTES | 2048 | 0
OUTPUTMC | 1 | 13 | 0
INPUTS | 6 | D<14>.PIN | LAN_BASEADR<14> | LAN_BASEADR<5> | A<21>.PIN | LAN_BASEADR<7> | A<23>.PIN
INPUTMC | 3 | 1 | 17 | 1 | 3 | 10 | 3
INPUTP | 3 | 81 | 163 | 161
EXPORTS | 1 | 13 | 0
EQ | 5 |
EXP27_.EXP = D<14>.PIN & !LAN_BASEADR<14>
# LAN_BASEADR<5> & !A<21>.PIN
# !LAN_BASEADR<5> & A<21>.PIN
# LAN_BASEADR<7> & !A<23>.PIN
# !LAN_BASEADR<7> & A<23>.PIN
MACROCELL | 13 | 17 | EXP28_
ATTRIBUTES | 2048 | 0
OUTPUTMC | 1 | 13 | 0
INPUTS | 7 | A<20>.PIN | LAN_BASEADR<4> | A<19>.PIN | LAN_BASEADR<3> | A<18>.PIN | LAN_BASEADR<2> | Z3_ADR<10>.EXP
INPUTMC | 4 | 1 | 6 | 1 | 8 | 1 | 10 | 13 | 16
INPUTP | 3 | 167 | 169 | 171
EXPORTS | 1 | 13 | 0
IMPORTS | 1 | 13 | 16
EQ | 7 |
EXP28_.EXP = A<20>.PIN & !LAN_BASEADR<4>
# !A<20>.PIN & LAN_BASEADR<4>
# A<19>.PIN & !LAN_BASEADR<3>
# !A<19>.PIN & LAN_BASEADR<3>
# !A<18>.PIN & LAN_BASEADR<2>
;Imported pterms FB14_17
# !D<14>.PIN & LAN_BASEADR<14>
PIN | Z3 | 64 | 0 | N/A | 151 | 3 | 12 | 17 | 12 | 16 | 5 | 16
PIN | CFIN | 64 | 0 | N/A | 190 | 1 | 5 | 16
PIN | CLK_EXT | 4096 | 0 | N/A | 57 | 106 | 8 | 10 | 15 | 5 | 15 | 2 | 15 | 1 | 14 | 16 | 14 | 14 | 14 | 13 | 8 | 13 | 8 | 16 | 10 | 2 | 10 | 4 | 10 | 9 | 10 | 10 | 12 | 7 | 15 | 10 | 15 | 7 | 14 | 4 | 10 | 14 | 10 | 12 | 10 | 8 | 10 | 7 | 10 | 6 | 1 | 17 | 1 | 15 | 1 | 12 | 1 | 10 | 1 | 8 | 1 | 6 | 1 | 3 | 10 | 5 | 10 | 3 | 10 | 1 | 10 | 0 | 3 | 16 | 5 | 15 | 15 | 16 | 15 | 15 | 15 | 14 | 15 | 13 | 15 | 12 | 14 | 10 | 14 | 9 | 14 | 8 | 15 | 11 | 15 | 8 | 15 | 6 | 15 | 4 | 15 | 3 | 14 | 7 | 14 | 6 | 14 | 5 | 8 | 9 | 8 | 3 | 8 | 14 | 8 | 11 | 8 | 8 | 12 | 6 | 8 | 2 | 8 | 7 | 6 | 6 | 8 | 12 | 12 | 5 | 4 | 2 | 4 | 12 | 4 | 10 | 4 | 5 | 4 | 3 | 9 | 17 | 9 | 15 | 8 | 17 | 4 | 17 | 7 | 17 | 7 | 16 | 3 | 17 | 6 | 17 | 9 | 14 | 11 | 17 | 4 | 15 | 7 | 15 | 7 | 14 | 11 | 16 | 9 | 12 | 11 | 15 | 4 | 0 | 3 | 15 | 1 | 0 | 14 | 2 | 14 | 15 | 14 | 3 | 14 | 1 | 10 | 17 | 10 | 15 | 14 | 12 | 14 | 0 | 4 | 7 | 4 | 6 | 3 | 12 | 8 | 15 | 15 | 0 | 12 | 15 | 12 | 14 | 15 | 17 | 9 | 6 | 9 | 8 | 13 | 10 | 3 | 8
PIN | FCS | 64 | 0 | N/A | 147 | 68 | 8 | 10 | 15 | 5 | 15 | 2 | 15 | 1 | 14 | 16 | 14 | 14 | 14 | 13 | 8 | 13 | 8 | 16 | 10 | 2 | 10 | 4 | 10 | 9 | 10 | 10 | 12 | 7 | 15 | 10 | 15 | 7 | 14 | 4 | 10 | 14 | 10 | 12 | 10 | 8 | 10 | 7 | 10 | 6 | 1 | 17 | 1 | 15 | 1 | 12 | 1 | 10 | 1 | 8 | 1 | 6 | 1 | 3 | 10 | 5 | 10 | 3 | 10 | 1 | 10 | 0 | 12 | 17 | 12 | 10 | 6 | 8 | 6 | 9 | 6 | 14 | 12 | 16 | 5 | 16 | 13 | 12 | 6 | 16 | 6 | 15 | 12 | 11 | 3 | 15 | 1 | 0 | 13 | 16 | 13 | 15 | 12 | 12 | 6 | 13 | 6 | 12 | 6 | 10 | 14 | 2 | 14 | 15 | 14 | 3 | 14 | 1 | 10 | 17 | 10 | 15 | 14 | 12 | 14 | 0 | 13 | 10 | 13 | 13 | 3 | 9 | 3 | 14 | 8 | 0 | 14 | 17 | 3 | 10 | 13 | 8
PIN | RW | 64 | 0 | N/A | 158 | 43 | 8 | 10 | 15 | 5 | 15 | 2 | 15 | 1 | 14 | 16 | 14 | 14 | 14 | 13 | 8 | 13 | 8 | 16 | 10 | 2 | 10 | 4 | 10 | 9 | 10 | 10 | 12 | 7 | 15 | 10 | 15 | 7 | 14 | 4 | 10 | 14 | 10 | 12 | 10 | 8 | 10 | 7 | 10 | 6 | 1 | 17 | 1 | 15 | 1 | 12 | 1 | 10 | 1 | 8 | 1 | 6 | 1 | 3 | 10 | 5 | 10 | 3 | 10 | 1 | 10 | 0 | 8 | 14 | 8 | 8 | 8 | 7 | 8 | 12 | 3 | 15 | 1 | 0 | 8 | 15 | 3 | 9 | 8 | 0 | 14 | 17
PIN | UDS | 64 | 0 | N/A | 155 | 40 | 14 | 4 | 10 | 14 | 10 | 12 | 10 | 8 | 10 | 7 | 10 | 6 | 1 | 17 | 1 | 15 | 1 | 12 | 1 | 10 | 1 | 8 | 1 | 6 | 1 | 3 | 10 | 5 | 10 | 3 | 10 | 1 | 10 | 0 | 3 | 16 | 8 | 14 | 8 | 8 | 8 | 7 | 8 | 12 | 1 | 0 | 14 | 2 | 14 | 15 | 14 | 3 | 14 | 1 | 10 | 17 | 10 | 15 | 14 | 12 | 14 | 0 | 12 | 14 | 15 | 17 | 8 | 6 | 14 | 17 | 4 | 8 | 8 | 1 | 8 | 5 | 8 | 4 | 12 | 4
PIN | LDS | 64 | 0 | N/A | 157 | 29 | 3 | 16 | 8 | 14 | 8 | 8 | 8 | 7 | 8 | 12 | 9 | 16 | 9 | 0 | 8 | 0 | 4 | 16 | 8 | 4 | 7 | 0 | 3 | 0 | 6 | 16 | 9 | 13 | 7 | 17 | 4 | 14 | 7 | 14 | 7 | 13 | 11 | 0 | 9 | 11 | 11 | 14 | 12 | 15 | 15 | 17 | 8 | 6 | 14 | 17 | 4 | 8 | 8 | 5 | 11 | 17 | 15 | 16
PIN | DS1 | 64 | 0 | N/A | 148 | 4 | 12 | 14 | 12 | 3 | 12 | 8 | 12 | 9
PIN | DS0 | 64 | 0 | N/A | 170 | 4 | 12 | 15 | 12 | 3 | 12 | 8 | 12 | 9
PIN | RESET | 64 | 0 | N/A | 263 | 74 | 14 | 4 | 10 | 14 | 10 | 12 | 10 | 8 | 10 | 7 | 10 | 6 | 1 | 17 | 1 | 15 | 1 | 12 | 1 | 10 | 1 | 8 | 1 | 6 | 1 | 3 | 10 | 5 | 10 | 3 | 10 | 1 | 10 | 0 | 3 | 16 | 5 | 15 | 9 | 16 | 11 | 9 | 9 | 1 | 9 | 9 | 9 | 13 | 11 | 11 | 9 | 2 | 7 | 1 | 11 | 7 | 7 | 2 | 11 | 4 | 9 | 5 | 9 | 4 | 9 | 7 | 9 | 11 | 9 | 10 | 4 | 2 | 4 | 12 | 4 | 10 | 4 | 5 | 4 | 3 | 4 | 0 | 3 | 15 | 1 | 0 | 14 | 2 | 14 | 15 | 14 | 3 | 14 | 1 | 10 | 17 | 10 | 15 | 14 | 12 | 14 | 0 | 4 | 7 | 4 | 6 | 3 | 12 | 9 | 8 | 3 | 5 | 5 | 5 | 5 | 7 | 5 | 2 | 5 | 4 | 3 | 4 | 3 | 11 | 3 | 7 | 1 | 1 | 3 | 13 | 1 | 4 | 1 | 2 | 5 | 9 | 5 | 13 | 7 | 7 | 13 | 10 | 3 | 14 | 7 | 0 | 3 | 10
PIN | LAN_INT | 64 | 0 | N/A | 201 | 2 | 5 | 15 | 3 | 12
PIN | A<4> | 64 | 0 | N/A | 97 | 1 | 12 | 10
PIN | A<3> | 64 | 0 | N/A | 99 | 1 | 6 | 8
PIN | A<2> | 64 | 0 | N/A | 101 | 1 | 6 | 9
PIN | A<5> | 64 | 0 | N/A | 91 | 1 | 13 | 12
PIN | A<6> | 64 | 0 | N/A | 98 | 1 | 6 | 16
PIN | A<7> | 64 | 0 | N/A | 100 | 1 | 6 | 15
PIN | BERR | 64 | 0 | N/A | 176 | 1 | 7 | 0
PIN | AUTOBOOT_OFF | 64 | 0 | N/A | 142 | 1 | 13 | 10
PIN | A_LAN<0> | 536871040 | 0 | N/A | 7
PIN | A_LAN<10> | 536871040 | 0 | N/A | 255
PIN | A_LAN<11> | 536871040 | 0 | N/A | 256
PIN | A_LAN<12> | 536871040 | 0 | N/A | 253
PIN | A_LAN<13> | 536871040 | 0 | N/A | 254
PIN | A_LAN<1> | 536871040 | 0 | N/A | 6
PIN | A_LAN<2> | 536871040 | 0 | N/A | 12
PIN | A_LAN<3> | 536871040 | 0 | N/A | 8
PIN | A_LAN<4> | 536871040 | 0 | N/A | 20
PIN | A_LAN<5> | 536871040 | 0 | N/A | 13
PIN | A_LAN<6> | 536871040 | 0 | N/A | 22
PIN | A_LAN<7> | 536871040 | 0 | N/A | 21
PIN | A_LAN<8> | 536871040 | 0 | N/A | 258
PIN | A_LAN<9> | 536871040 | 0 | N/A | 262
PIN | LAN_CS | 536871040 | 0 | N/A | 240
PIN | LAN_WRH | 536871040 | 0 | N/A | 237
PIN | LAN_WRL | 536871040 | 0 | N/A | 145
PIN | LAN_RD | 536871040 | 0 | N/A | 242
PIN | OVR | 536871040 | 0 | N/A | 185
PIN | INT_OUT | 536871040 | 0 | N/A | 60
PIN | DTACK | 536871040 | 0 | N/A | 160
PIN | CFOUT | 536871040 | 0 | N/A | 191
PIN | SLAVE | 536871040 | 0 | N/A | 193
PIN | OWN | 536871040 | 0 | N/A | 195
PIN | MTACK | 536871040 | 0 | N/A | 174
PIN | LAN_CFG<4> | 536871040 | 0 | N/A | 199
PIN | LAN_CFG<3> | 536871040 | 0 | N/A | 24
PIN | LAN_CFG<2> | 536871040 | 0 | N/A | 251
PIN | LAN_CFG<1> | 536871040 | 0 | N/A | 23
PIN | ROM_OE | 536871040 | 0 | N/A | 65
PIN | ROM_B<1> | 536871040 | 0 | N/A | 129
PIN | ROM_B<0> | 536871040 | 0 | N/A | 127
PIN | CP_RD | 536871040 | 0 | N/A | 132
PIN | CP_CS | 536871040 | 0 | N/A | 63
PIN | IDE_W | 536871040 | 0 | N/A | 47
PIN | IDE_R | 536871040 | 0 | N/A | 46
PIN | IDE_CS<1> | 536871040 | 0 | N/A | 41
PIN | IDE_CS<0> | 536871040 | 0 | N/A | 39
PIN | IDE_A<2> | 536871040 | 0 | N/A | 44
PIN | IDE_A<1> | 536871040 | 0 | N/A | 45
PIN | IDE_A<0> | 536871040 | 0 | N/A | 43
PIN | CP_WE | 536871040 | 0 | N/A | 131
PIN | A<8> | 536870976 | 0 | N/A | 106 | 3 | 6 | 14 | 9 | 17 | 9 | 12
PIN | A<18> | 536870976 | 0 | N/A | 171 | 5 | 5 | 16 | 9 | 15 | 9 | 14 | 13 | 0 | 13 | 17
PIN | A<19> | 536870976 | 0 | N/A | 169 | 4 | 5 | 16 | 8 | 17 | 11 | 0 | 13 | 17
PIN | A<20> | 536870976 | 0 | N/A | 167 | 4 | 5 | 16 | 4 | 17 | 4 | 15 | 13 | 17
PIN | A<21> | 536870976 | 0 | N/A | 163 | 4 | 5 | 16 | 7 | 0 | 7 | 15 | 13 | 1
PIN | A<22> | 536870976 | 0 | N/A | 162 | 4 | 5 | 16 | 7 | 16 | 7 | 13 | 5 | 17
PIN | A<23> | 536870976 | 0 | N/A | 161 | 5 | 3 | 16 | 5 | 16 | 3 | 17 | 11 | 16 | 13 | 1
PIN | A<9> | 536870976 | 0 | N/A | 108 | 3 | 6 | 17 | 11 | 15 | 6 | 13
PIN | A<10> | 536870976 | 0 | N/A | 112 | 3 | 9 | 15 | 9 | 14 | 6 | 12
PIN | A<11> | 536870976 | 0 | N/A | 114 | 3 | 8 | 17 | 11 | 17 | 6 | 10
PIN | A<12> | 536870976 | 0 | N/A | 115 | 3 | 4 | 17 | 4 | 15 | 13 | 16
PIN | A<13> | 536870976 | 0 | N/A | 123 | 4 | 12 | 17 | 7 | 17 | 7 | 15 | 13 | 15
PIN | A<14> | 536870976 | 0 | N/A | 125 | 4 | 12 | 17 | 7 | 16 | 7 | 14 | 12 | 12
PIN | A<15> | 536870976 | 0 | N/A | 139 | 3 | 12 | 11 | 3 | 17 | 11 | 16
PIN | A<16> | 536870976 | 0 | N/A | 175 | 4 | 5 | 16 | 9 | 17 | 9 | 12 | 13 | 0
PIN | A<17> | 536870976 | 0 | N/A | 172 | 4 | 5 | 16 | 6 | 17 | 11 | 15 | 13 | 0
PIN | DQ<10> | 536870976 | 0 | N/A | 234 | 4 | 15 | 5 | 8 | 16 | 15 | 14 | 15 | 6
PIN | DQ<11> | 536870976 | 0 | N/A | 207 | 4 | 15 | 2 | 10 | 2 | 15 | 13 | 15 | 4
PIN | DQ<1> | 536870976 | 0 | N/A | 216 | 4 | 8 | 13 | 15 | 7 | 15 | 15 | 15 | 8
PIN | DQ<4> | 536870976 | 0 | N/A | 225 | 4 | 15 | 1 | 10 | 4 | 15 | 12 | 15 | 3
PIN | DQ<8> | 536870976 | 0 | N/A | 231 | 4 | 8 | 10 | 15 | 10 | 15 | 16 | 15 | 11
PIN | DQ<9> | 536870976 | 0 | N/A | 209 | 4 | 8 | 13 | 15 | 7 | 15 | 15 | 15 | 8
PIN | D<0> | 536870976 | 0 | N/A | 4 | 3 | 10 | 14 | 9 | 0 | 9 | 11
PIN | D<10> | 536870976 | 0 | N/A | 74 | 5 | 10 | 12 | 5 | 16 | 9 | 15 | 9 | 14 | 13 | 9
PIN | D<11> | 536870976 | 0 | N/A | 77 | 5 | 10 | 8 | 5 | 16 | 8 | 17 | 11 | 17 | 13 | 11
PIN | D<12> | 536870976 | 0 | N/A | 78 | 6 | 10 | 7 | 12 | 17 | 12 | 16 | 5 | 16 | 4 | 17 | 4 | 15
PIN | D<13> | 536870976 | 0 | N/A | 80 | 5 | 10 | 6 | 5 | 16 | 7 | 17 | 7 | 15 | 5 | 17
PIN | D<14> | 536870976 | 0 | N/A | 81 | 6 | 1 | 17 | 5 | 16 | 7 | 16 | 7 | 14 | 13 | 1 | 13 | 16
PIN | D<15> | 536870976 | 0 | N/A | 89 | 6 | 1 | 15 | 3 | 16 | 5 | 16 | 3 | 17 | 11 | 16 | 0 | 15
PIN | D<1> | 536870976 | 0 | N/A | 30 | 3 | 1 | 12 | 6 | 16 | 11 | 14
PIN | D<2> | 536870976 | 0 | N/A | 71 | 3 | 1 | 10 | 9 | 13 | 9 | 16
PIN | D<3> | 536870976 | 0 | N/A | 28 | 3 | 1 | 8 | 8 | 0 | 11 | 0
PIN | D<4> | 536870976 | 0 | N/A | 38 | 3 | 1 | 6 | 4 | 16 | 4 | 14
PIN | D<5> | 536870976 | 0 | N/A | 37 | 3 | 1 | 3 | 7 | 0 | 7 | 14
PIN | D<6> | 536870976 | 0 | N/A | 26 | 3 | 10 | 5 | 7 | 13 | 7 | 17
PIN | D<7> | 536870976 | 0 | N/A | 29 | 3 | 10 | 3 | 3 | 0 | 11 | 17
PIN | D<8> | 536870976 | 0 | N/A | 32 | 5 | 10 | 1 | 5 | 16 | 9 | 17 | 9 | 12 | 0 | 17
PIN | D<9> | 536870976 | 0 | N/A | 73 | 5 | 10 | 0 | 5 | 16 | 6 | 17 | 11 | 15 | 6 | 7
PIN | DQ<0> | 536870976 | 0 | N/A | 217 | 4 | 8 | 10 | 15 | 10 | 15 | 16 | 15 | 11
PIN | DQ<12> | 536870976 | 0 | N/A | 235 | 4 | 15 | 1 | 10 | 4 | 15 | 12 | 15 | 3
PIN | DQ<13> | 536870976 | 0 | N/A | 204 | 4 | 14 | 16 | 10 | 9 | 14 | 10 | 14 | 7
PIN | DQ<14> | 536870976 | 0 | N/A | 236 | 4 | 14 | 14 | 10 | 10 | 14 | 9 | 14 | 6
PIN | DQ<15> | 536870976 | 0 | N/A | 202 | 4 | 14 | 13 | 12 | 7 | 14 | 8 | 14 | 5
PIN | DQ<2> | 536870976 | 0 | N/A | 220 | 4 | 15 | 5 | 8 | 16 | 15 | 14 | 15 | 6
PIN | DQ<3> | 536870976 | 0 | N/A | 219 | 4 | 15 | 2 | 10 | 2 | 15 | 13 | 15 | 4
PIN | DQ<5> | 536870976 | 0 | N/A | 221 | 4 | 14 | 16 | 10 | 9 | 14 | 10 | 14 | 7
PIN | DQ<6> | 536870976 | 0 | N/A | 227 | 4 | 14 | 14 | 10 | 10 | 14 | 9 | 14 | 6
PIN | DQ<7> | 536870976 | 0 | N/A | 226 | 4 | 14 | 13 | 12 | 7 | 14 | 8 | 14 | 5
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