Performance Summary Report -------------------------- Design: LAN_IDE_CP Device: XC95288XL-10-TQ144 Speed File: Version 3.0 Program: Timing Report Generator: version P.68d Date: Sat Jan 07 23:31:29 2017 Performance Summary: Pad to Pad (tPD) : 18.7ns (2 macrocell levels) Pad 'RW' to Pad 'DQ<0>' Clock net 'AS' path delays: Clock Pad to Output Pad (tCO) : 26.6ns (3 macrocell levels) Clock Pad 'AS' to Output Pad 'DQ<0>' (Pterm Clock) Setup to Clock at the Pad (tSU) : 3.5ns (0 macrocell levels) Data signal 'A<22>' to DFF D input Pin at 'LAN_CS.D' Clock pad 'AS' (Pterm Clock) Minimum Clock Period: 14.0ns Maximum Internal Clock Speed: 71.4Mhz (Limited by Clock Pulse Width) Clock net 'C1' path delays: Clock Pad to Output Pad (tCO) : 34.3ns (4 macrocell levels) Clock Pad 'C1' to Output Pad 'INT_OUT' (Pterm Clock) Clock to Setup (tCYC) : 11.4ns (1 macrocell levels) Clock to Q, net 'AUTO_CONFIG_DONE_CYCLE<0>.Q' to TFF Setup(D) at 'AUTO_CONFIG_DONE_CYCLE<1>.D'(Pterm Clock) Target FF drives output net 'AUTO_CONFIG_DONE_CYCLE<1>' Setup to Clock at the Pad (tSU) : -4.2ns (0 macrocell levels) Data signal 'A<2>' to TFF D input Pin at 'AUTO_CONFIG_DONE_CYCLE<1>.D' Clock pad 'C1' (Pterm Clock) Minimum Clock Period: 14.0ns Maximum Internal Clock Speed: 71.4Mhz (Limited by Clock Pulse Width) Clock net 'C3' path delays: Clock Pad to Output Pad (tCO) : 34.3ns (4 macrocell levels) Clock Pad 'C3' to Output Pad 'INT_OUT' (Pterm Clock) Clock to Setup (tCYC) : 11.4ns (1 macrocell levels) Clock to Q, net 'AUTO_CONFIG_DONE_CYCLE<0>.Q' to TFF Setup(D) at 'AUTO_CONFIG_DONE_CYCLE<1>.D'(Pterm Clock) Target FF drives output net 'AUTO_CONFIG_DONE_CYCLE<1>' Setup to Clock at the Pad (tSU) : -4.2ns (0 macrocell levels) Data signal 'A<2>' to TFF D input Pin at 'AUTO_CONFIG_DONE_CYCLE<1>.D' Clock pad 'C3' (Pterm Clock) Minimum Clock Period: 14.0ns Maximum Internal Clock Speed: 71.4Mhz (Limited by Clock Pulse Width) -------------------------------------------------------------------------------- Pad to Pad (tPD) (nsec) \ From A A A A A A A A A A A \ < < < < < < < < < < < \ 1 1 1 1 1 1 2 3 4 5 6 \ 0 1 2 3 4 > > > > > > \ > > > > > \ \ \ \ To \------------------------------------------------------------------ A_LAN<0> 10.0 A_LAN<10> 10.0 A_LAN<11> 10.0 A_LAN<12> 10.0 A_LAN<13> 10.0 A_LAN<1> 10.0 A_LAN<2> 10.0 A_LAN<3> 10.0 A_LAN<4> 10.0 A_LAN<5> 11.0 A_LAN<6> A_LAN<7> A_LAN<8> A_LAN<9> 10.0 CP_RD CP_WE D<0> D<10> D<11> D<12> D<13> D<14> D<15> D<1> D<2> D<3> D<4> D<5> D<6> D<7> D<8> D<9> DQ<0> DQ<10> DQ<11> DQ<12> DQ<13> DQ<14> DQ<15> DQ<1> DQ<2> DQ<3> DQ<4> DQ<5> DQ<6> DQ<7> DQ<8> DQ<9> DTACK IDE_A<0> IDE_A<1> 10.0 IDE_A<2> 10.0 IDE_CS<0> 10.0 IDE_CS<1> 10.0 IDE_R IDE_W INT_OUT LAN_RD LAN_WRH LAN_WRL OVR OWN ROM_OE SLAVE -------------------------------------------------------------------------------- Pad to Pad (tPD) (nsec) \ From A A A A C D D D D D D \ < < < S P < < < < < < \ 7 8 9 _ 0 1 1 1 1 1 \ > > > I > 0 1 2 3 4 \ R > > > > > \ Q \ \ \ To \------------------------------------------------------------------ A_LAN<0> A_LAN<10> A_LAN<11> A_LAN<12> A_LAN<13> A_LAN<1> A_LAN<2> A_LAN<3> A_LAN<4> A_LAN<5> A_LAN<6> 10.0 A_LAN<7> 10.0 A_LAN<8> 10.0 A_LAN<9> CP_RD 10.0 CP_WE 10.0 D<0> D<10> D<11> D<12> D<13> D<14> D<15> D<1> D<2> D<3> D<4> D<5> D<6> D<7> D<8> D<9> DQ<0> 10.0 DQ<10> 6.5 DQ<11> 6.5 DQ<12> 6.5 DQ<13> 6.5 DQ<14> 6.5 DQ<15> DQ<1> DQ<2> DQ<3> DQ<4> DQ<5> DQ<6> DQ<7> DQ<8> DQ<9> DTACK 11.0 IDE_A<0> 10.0 IDE_A<1> IDE_A<2> IDE_CS<0> IDE_CS<1> IDE_R 10.0 IDE_W 10.0 INT_OUT 18.7 LAN_RD 10.0 LAN_WRH 10.0 LAN_WRL 10.0 OVR 11.0 OWN 18.7 ROM_OE 10.0 SLAVE 10.0 -------------------------------------------------------------------------------- Pad to Pad (tPD) (nsec) \ From D D D D D D D D D D D \ < < < < < < < < < < Q \ 1 1 2 3 4 5 6 7 8 9 < \ 5 > > > > > > > > > 0 \ > > \ \ \ \ To \------------------------------------------------------------------ A_LAN<0> A_LAN<10> A_LAN<11> A_LAN<12> A_LAN<13> A_LAN<1> A_LAN<2> A_LAN<3> A_LAN<4> A_LAN<5> A_LAN<6> A_LAN<7> A_LAN<8> A_LAN<9> CP_RD CP_WE D<0> 10.0 D<10> D<11> D<12> D<13> D<14> D<15> D<1> D<2> D<3> D<4> D<5> D<6> D<7> D<8> D<9> DQ<0> DQ<10> DQ<11> DQ<12> DQ<13> DQ<14> DQ<15> 6.5 DQ<1> 10.0 DQ<2> 10.0 DQ<3> 10.0 DQ<4> 10.0 DQ<5> 10.0 DQ<6> 10.0 DQ<7> 10.0 DQ<8> 6.5 DQ<9> 6.5 DTACK IDE_A<0> IDE_A<1> IDE_A<2> IDE_CS<0> IDE_CS<1> IDE_R IDE_W INT_OUT LAN_RD LAN_WRH LAN_WRL OVR OWN ROM_OE SLAVE -------------------------------------------------------------------------------- Pad to Pad (tPD) (nsec) \ From D D D D D D D D D D D \ Q Q Q Q Q Q Q Q Q Q Q \ < < < < < < < < < < < \ 1 1 1 1 1 1 1 2 3 4 5 \ 0 1 2 3 4 5 > > > > > \ > > > > > > \ \ \ To \------------------------------------------------------------------ A_LAN<0> A_LAN<10> A_LAN<11> A_LAN<12> A_LAN<13> A_LAN<1> A_LAN<2> A_LAN<3> A_LAN<4> A_LAN<5> A_LAN<6> A_LAN<7> A_LAN<8> A_LAN<9> CP_RD CP_WE D<0> D<10> 10.0 D<11> 10.0 D<12> 11.0 D<13> 11.0 D<14> 11.0 D<15> 11.0 D<1> 10.0 D<2> 10.0 D<3> 10.0 D<4> 10.0 D<5> 10.0 D<6> D<7> D<8> D<9> DQ<0> DQ<10> DQ<11> DQ<12> DQ<13> DQ<14> DQ<15> DQ<1> DQ<2> DQ<3> DQ<4> DQ<5> DQ<6> DQ<7> DQ<8> DQ<9> DTACK IDE_A<0> IDE_A<1> IDE_A<2> IDE_CS<0> IDE_CS<1> IDE_R IDE_W INT_OUT LAN_RD LAN_WRH LAN_WRL OVR OWN ROM_OE SLAVE -------------------------------------------------------------------------------- Pad to Pad (tPD) (nsec) \ From D D D D I L L R U \ Q Q Q Q D A D W D \ < < < < E N S S \ 6 7 8 9 _ _ \ > > > > W I \ A N \ I T \ T \ To \------------------------------------------------------ A_LAN<0> A_LAN<10> A_LAN<11> A_LAN<12> A_LAN<13> A_LAN<1> A_LAN<2> A_LAN<3> A_LAN<4> A_LAN<5> A_LAN<6> A_LAN<7> A_LAN<8> A_LAN<9> CP_RD CP_WE D<0> 18.7 18.7 18.7 D<10> 18.7 18.7 18.7 D<11> 18.7 18.7 18.7 D<12> 18.7 18.7 18.7 D<13> 18.7 18.7 18.7 D<14> 18.7 18.7 18.7 D<15> 18.7 18.7 18.7 D<1> 18.7 18.7 18.7 D<2> 18.7 18.7 18.7 D<3> 18.7 18.7 18.7 D<4> 18.7 18.7 18.7 D<5> 18.7 18.7 18.7 D<6> 10.0 18.7 18.7 18.7 D<7> 10.0 18.7 18.7 18.7 D<8> 10.0 18.7 18.7 18.7 D<9> 10.0 18.7 18.7 18.7 DQ<0> 18.7 18.7 18.7 DQ<10> 18.7 18.7 18.7 DQ<11> 18.7 18.7 18.7 DQ<12> 18.7 18.7 18.7 DQ<13> 18.7 18.7 18.7 DQ<14> 18.7 18.7 18.7 DQ<15> 18.7 18.7 18.7 DQ<1> 18.7 18.7 18.7 DQ<2> 18.7 18.7 18.7 DQ<3> 18.7 18.7 18.7 DQ<4> 18.7 18.7 18.7 DQ<5> 18.7 18.7 18.7 DQ<6> 18.7 18.7 18.7 DQ<7> 18.7 18.7 18.7 DQ<8> 18.7 18.7 18.7 DQ<9> 18.7 18.7 18.7 DTACK 11.0 IDE_A<0> IDE_A<1> IDE_A<2> IDE_CS<0> IDE_CS<1> IDE_R IDE_W INT_OUT 18.7 LAN_RD LAN_WRH LAN_WRL OVR OWN ROM_OE SLAVE -------------------------------------------------------------------------------- Clock Pad to Output Pad (tCO) (nsec) \ From A C C \ S 1 3 \ \ \ \ \ To \------------------ CP_CS 10.2 CP_RD 25.6 25.6 CP_WE 25.6 25.6 D<0> 26.6 D<10> 26.6 D<11> 26.6 D<12> 26.6 25.6 25.6 D<13> 26.6 26.6 26.6 D<14> 26.6 25.6 25.6 D<15> 26.6 25.6 25.6 D<1> 26.6 D<2> 26.6 D<3> 26.6 D<4> 26.6 D<5> 26.6 D<6> 26.6 D<7> 26.6 D<8> 26.6 D<9> 26.6 DQ<0> 26.6 DQ<10> 26.6 DQ<11> 26.6 DQ<12> 26.6 DQ<13> 26.6 DQ<14> 26.6 DQ<15> 26.6 DQ<1> 26.6 DQ<2> 26.6 DQ<3> 26.6 DQ<4> 26.6 DQ<5> 26.6 DQ<6> 26.6 DQ<7> 26.6 DQ<8> 26.6 DQ<9> 26.6 DTACK 18.9 IDE_R 25.6 25.6 IDE_W 25.6 25.6 INT_OUT 34.3 34.3 LAN_CS 10.2 LAN_RD 25.6 25.6 LAN_WRH 25.6 25.6 LAN_WRL 25.6 25.6 OVR 18.9 OWN 26.6 ROM_OE 25.6 25.6 SLAVE 17.9 -------------------------------------------------------------------------------- Setup to Clock at Pad (tSU or tSUF) (nsec) \ From A C C \ S 1 3 \ \ \ \ \ \ \ \ \ \ To \------------------ A<15> -5.6 -5.6 A<16> 3.1 A<17> 3.1 A<18> 3.1 A<19> 3.1 A<1> -4.2 -4.2 A<20> 3.5 A<21> 3.1 A<22> 3.5 A<23> 3.5 A<2> -4.2 -4.2 A<3> -4.2 -4.2 A<4> -4.2 -4.2 A<5> -4.2 -4.2 A<6> -4.2 -4.2 AS -4.2 -4.2 AUTOBOOT_OFF -4.2 -4.2 CFIN 2.1 D<10> -4.6 -4.6 D<11> -4.6 -4.6 D<12> -4.6 -4.6 D<13> -4.6 -4.6 D<14> -4.6 -4.6 D<15> -4.6 -4.6 D<8> -4.6 -4.6 D<9> -4.6 -4.6 LDS -4.2 -4.2 RESET -4.2 -4.2 RW -4.2 -4.2 UDS -4.2 -4.2 -------------------------------------------------------------------------------- Clock to Setup (tCYC) (nsec) (Clock: C1) \ From A A A A C C C C \ U U U U P P P P \ T T T T _ _ _ _ \ O O O O B B B B \ _ _ _ _ A A A A \ C C C C S S S S \ O O O O E E E E \ N N N N A A A A \ F F F F D D D D \ I I I I R R R R \ G G G G < < < < \ _ _ _ _ 0 1 2 3 \ D D D D > > > > \ O O O O . . . . \ N N N N Q Q Q Q \ E E E E \ < < _ _ \ 0 1 C C \ > > Y Y \ . . C C \ Q Q L L \ E E \ < < \ 0 1 \ > > \ . . \ Q Q To \------------------------------------------------ AUTO_CONFIG_DONE<0>.D 10.0 10.0 AUTO_CONFIG_DONE<1>.D 10.0 10.0 AUTO_CONFIG_DONE_CYCLE<0>.D 11.0 11.0 11.0 AUTO_CONFIG_DONE_CYCLE<1>.D 11.0 11.0 11.4 11.4 CP_BASEADR<0>.D 11.0 11.0 11.0 CP_BASEADR<1>.D 11.0 11.0 11.0 CP_BASEADR<2>.D 11.0 11.0 11.0 CP_BASEADR<3>.D 11.0 11.0 11.0 CP_BASEADR<4>.D 11.0 11.0 CP_BASEADR<5>.D 11.0 11.0 CP_BASEADR<6>.D 11.0 11.0 CP_BASEADR<7>.D 11.0 11.0 Dout1<0>.D 11.4 11.4 Dout1<1>.D 11.4 11.4 Dout1<2>.D 11.0 11.4 Dout1<3>.D 11.0 IDE_BASEADR<0>.D 11.0 11.0 IDE_BASEADR<1>.D 11.0 11.0 IDE_BASEADR<2>.D 11.0 11.0 IDE_BASEADR<3>.D 11.0 11.0 IDE_BASEADR<4>.D 11.0 11.0 IDE_BASEADR<5>.D 11.0 11.0 IDE_BASEADR<6>.D 11.0 11.0 IDE_BASEADR<7>.D 11.0 11.0 IDE_ENABLE.D IDE_R_S.D LAN_BASEADR<0>.D 11.0 11.0 LAN_BASEADR<1>.D 11.0 11.0 LAN_BASEADR<2>.D 11.0 11.0 LAN_BASEADR<3>.D 11.0 11.0 LAN_BASEADR<4>.D 11.0 11.0 LAN_BASEADR<5>.D 11.0 11.0 LAN_BASEADR<6>.D 11.0 11.0 LAN_BASEADR<7>.D 11.0 11.0 ROM_OE_S.D SHUT_UP<0>.D 10.0 10.0 SHUT_UP<1>.D 10.0 10.0 SHUT_UP<2>.D 10.0 10.0 -------------------------------------------------------------------------------- Clock to Setup (tCYC) (nsec) (Clock: C1) \ From C C C C D D D D \ P P P P S o o o \ _ _ _ _ _ u u u \ B B B B D t t t \ A A A A . 1 1 1 \ S S S S Q < < < \ E E E E 0 1 2 \ A A A A > > > \ D D D D . . . \ R R R R Q Q Q \ < < < < \ 4 5 6 7 \ > > > > \ . . . . \ Q Q Q Q \ \ \ \ \ \ \ \ \ \ \ \ To \------------------------------------------------ AUTO_CONFIG_DONE<0>.D AUTO_CONFIG_DONE<1>.D AUTO_CONFIG_DONE_CYCLE<0>.D 11.0 AUTO_CONFIG_DONE_CYCLE<1>.D 11.4 CP_BASEADR<0>.D CP_BASEADR<1>.D CP_BASEADR<2>.D CP_BASEADR<3>.D CP_BASEADR<4>.D 11.0 CP_BASEADR<5>.D 11.0 CP_BASEADR<6>.D 11.0 CP_BASEADR<7>.D 11.0 Dout1<0>.D 11.0 Dout1<1>.D 10.0 Dout1<2>.D 10.0 Dout1<3>.D IDE_BASEADR<0>.D IDE_BASEADR<1>.D IDE_BASEADR<2>.D IDE_BASEADR<3>.D IDE_BASEADR<4>.D IDE_BASEADR<5>.D IDE_BASEADR<6>.D IDE_BASEADR<7>.D IDE_ENABLE.D IDE_R_S.D LAN_BASEADR<0>.D LAN_BASEADR<1>.D LAN_BASEADR<2>.D LAN_BASEADR<3>.D LAN_BASEADR<4>.D LAN_BASEADR<5>.D LAN_BASEADR<6>.D LAN_BASEADR<7>.D ROM_OE_S.D SHUT_UP<0>.D SHUT_UP<1>.D SHUT_UP<2>.D -------------------------------------------------------------------------------- Clock to Setup (tCYC) (nsec) (Clock: C1) \ From D I I I I I I I \ o D D D D D D D \ u E E E E E E E \ t _ _ _ _ _ _ _ \ 1 B B B B B B B \ < A A A A A A A \ 3 S S S S S S S \ > E E E E E E E \ . A A A A A A A \ Q D D D D D D D \ R R R R R R R \ < < < < < < < \ 0 1 2 3 4 5 6 \ > > > > > > > \ . . . . . . . \ Q Q Q Q Q Q Q \ \ \ \ \ \ \ \ \ \ \ To \------------------------------------------------ AUTO_CONFIG_DONE<0>.D AUTO_CONFIG_DONE<1>.D AUTO_CONFIG_DONE_CYCLE<0>.D AUTO_CONFIG_DONE_CYCLE<1>.D CP_BASEADR<0>.D CP_BASEADR<1>.D CP_BASEADR<2>.D CP_BASEADR<3>.D CP_BASEADR<4>.D CP_BASEADR<5>.D CP_BASEADR<6>.D CP_BASEADR<7>.D Dout1<0>.D Dout1<1>.D Dout1<2>.D Dout1<3>.D 11.0 IDE_BASEADR<0>.D 11.0 IDE_BASEADR<1>.D 11.0 IDE_BASEADR<2>.D 11.0 IDE_BASEADR<3>.D 11.0 IDE_BASEADR<4>.D 11.0 IDE_BASEADR<5>.D 11.0 IDE_BASEADR<6>.D 11.0 IDE_BASEADR<7>.D IDE_ENABLE.D IDE_R_S.D LAN_BASEADR<0>.D LAN_BASEADR<1>.D LAN_BASEADR<2>.D LAN_BASEADR<3>.D LAN_BASEADR<4>.D LAN_BASEADR<5>.D LAN_BASEADR<6>.D LAN_BASEADR<7>.D ROM_OE_S.D SHUT_UP<0>.D SHUT_UP<1>.D SHUT_UP<2>.D -------------------------------------------------------------------------------- Clock to Setup (tCYC) (nsec) (Clock: C1) \ From I I L L L L L L \ D D A A A A A A \ E E N N N N N N \ _ _ _ _ _ _ _ _ \ B E B B B B B B \ A N A A A A A A \ S A S S S S S S \ E B E E E E E E \ A L A A A A A A \ D E D D D D D D \ R . R R R R R R \ < Q < < < < < < \ 7 0 1 2 3 4 5 \ > > > > > > > \ . . . . . . . \ Q Q Q Q Q Q Q \ \ \ \ \ \ \ \ \ \ \ To \------------------------------------------------ AUTO_CONFIG_DONE<0>.D AUTO_CONFIG_DONE<1>.D AUTO_CONFIG_DONE_CYCLE<0>.D AUTO_CONFIG_DONE_CYCLE<1>.D CP_BASEADR<0>.D CP_BASEADR<1>.D CP_BASEADR<2>.D CP_BASEADR<3>.D CP_BASEADR<4>.D CP_BASEADR<5>.D CP_BASEADR<6>.D CP_BASEADR<7>.D Dout1<0>.D Dout1<1>.D Dout1<2>.D Dout1<3>.D IDE_BASEADR<0>.D IDE_BASEADR<1>.D IDE_BASEADR<2>.D IDE_BASEADR<3>.D IDE_BASEADR<4>.D IDE_BASEADR<5>.D IDE_BASEADR<6>.D IDE_BASEADR<7>.D 11.0 IDE_ENABLE.D 10.0 IDE_R_S.D 10.0 LAN_BASEADR<0>.D 11.0 LAN_BASEADR<1>.D 11.0 LAN_BASEADR<2>.D 11.0 LAN_BASEADR<3>.D 11.0 LAN_BASEADR<4>.D 11.0 LAN_BASEADR<5>.D 11.0 LAN_BASEADR<6>.D LAN_BASEADR<7>.D ROM_OE_S.D 10.0 SHUT_UP<0>.D SHUT_UP<1>.D SHUT_UP<2>.D -------------------------------------------------------------------------------- Clock to Setup (tCYC) (nsec) (Clock: C1) \ From L L S S S \ A A H H H \ N N U U U \ _ _ T T T \ B B _ _ _ \ A A U U U \ S S P P P \ E E < < < \ A A 0 1 2 \ D D > > > \ R R . . . \ < < Q Q Q \ 6 7 \ > > \ . . \ Q Q \ \ \ \ \ \ \ \ \ \ \ To \------------------------------ AUTO_CONFIG_DONE<0>.D AUTO_CONFIG_DONE<1>.D AUTO_CONFIG_DONE_CYCLE<0>.D 11.0 11.0 10.0 AUTO_CONFIG_DONE_CYCLE<1>.D 11.0 11.0 11.0 CP_BASEADR<0>.D 11.0 CP_BASEADR<1>.D 11.0 CP_BASEADR<2>.D 11.0 CP_BASEADR<3>.D 11.0 CP_BASEADR<4>.D 11.0 CP_BASEADR<5>.D 11.0 CP_BASEADR<6>.D 11.0 CP_BASEADR<7>.D 11.0 Dout1<0>.D Dout1<1>.D Dout1<2>.D Dout1<3>.D IDE_BASEADR<0>.D 11.0 IDE_BASEADR<1>.D 11.0 IDE_BASEADR<2>.D 11.0 IDE_BASEADR<3>.D 11.0 IDE_BASEADR<4>.D 11.0 IDE_BASEADR<5>.D 11.0 IDE_BASEADR<6>.D 11.0 IDE_BASEADR<7>.D 11.0 IDE_ENABLE.D IDE_R_S.D LAN_BASEADR<0>.D 11.0 LAN_BASEADR<1>.D 11.0 LAN_BASEADR<2>.D 11.0 LAN_BASEADR<3>.D 11.0 LAN_BASEADR<4>.D 11.0 LAN_BASEADR<5>.D 11.0 LAN_BASEADR<6>.D 11.0 11.0 LAN_BASEADR<7>.D 11.0 11.0 ROM_OE_S.D SHUT_UP<0>.D 10.0 SHUT_UP<1>.D 10.0 SHUT_UP<2>.D 10.0 -------------------------------------------------------------------------------- Clock to Setup (tCYC) (nsec) (Clock: C3) \ From A A A A C C C C \ U U U U P P P P \ T T T T _ _ _ _ \ O O O O B B B B \ _ _ _ _ A A A A \ C C C C S S S S \ O O O O E E E E \ N N N N A A A A \ F F F F D D D D \ I I I I R R R R \ G G G G < < < < \ _ _ _ _ 0 1 2 3 \ D D D D > > > > \ O O O O . . . . \ N N N N Q Q Q Q \ E E E E \ < < _ _ \ 0 1 C C \ > > Y Y \ . . C C \ Q Q L L \ E E \ < < \ 0 1 \ > > \ . . \ Q Q To \------------------------------------------------ AUTO_CONFIG_DONE<0>.D 10.0 10.0 AUTO_CONFIG_DONE<1>.D 10.0 10.0 AUTO_CONFIG_DONE_CYCLE<0>.D 11.0 11.0 11.0 AUTO_CONFIG_DONE_CYCLE<1>.D 11.0 11.0 11.4 11.4 CP_BASEADR<0>.D 11.0 11.0 11.0 CP_BASEADR<1>.D 11.0 11.0 11.0 CP_BASEADR<2>.D 11.0 11.0 11.0 CP_BASEADR<3>.D 11.0 11.0 11.0 CP_BASEADR<4>.D 11.0 11.0 CP_BASEADR<5>.D 11.0 11.0 CP_BASEADR<6>.D 11.0 11.0 CP_BASEADR<7>.D 11.0 11.0 Dout1<0>.D 11.4 11.4 Dout1<1>.D 11.4 11.4 Dout1<2>.D 11.0 11.4 Dout1<3>.D 11.0 IDE_BASEADR<0>.D 11.0 11.0 IDE_BASEADR<1>.D 11.0 11.0 IDE_BASEADR<2>.D 11.0 11.0 IDE_BASEADR<3>.D 11.0 11.0 IDE_BASEADR<4>.D 11.0 11.0 IDE_BASEADR<5>.D 11.0 11.0 IDE_BASEADR<6>.D 11.0 11.0 IDE_BASEADR<7>.D 11.0 11.0 IDE_ENABLE.D IDE_R_S.D LAN_BASEADR<0>.D 11.0 11.0 LAN_BASEADR<1>.D 11.0 11.0 LAN_BASEADR<2>.D 11.0 11.0 LAN_BASEADR<3>.D 11.0 11.0 LAN_BASEADR<4>.D 11.0 11.0 LAN_BASEADR<5>.D 11.0 11.0 LAN_BASEADR<6>.D 11.0 11.0 LAN_BASEADR<7>.D 11.0 11.0 ROM_OE_S.D SHUT_UP<0>.D 10.0 10.0 SHUT_UP<1>.D 10.0 10.0 SHUT_UP<2>.D 10.0 10.0 -------------------------------------------------------------------------------- Clock to Setup (tCYC) (nsec) (Clock: C3) \ From C C C C D D D D \ P P P P S o o o \ _ _ _ _ _ u u u \ B B B B D t t t \ A A A A . 1 1 1 \ S S S S Q < < < \ E E E E 0 1 2 \ A A A A > > > \ D D D D . . . \ R R R R Q Q Q \ < < < < \ 4 5 6 7 \ > > > > \ . . . . \ Q Q Q Q \ \ \ \ \ \ \ \ \ \ \ \ To \------------------------------------------------ AUTO_CONFIG_DONE<0>.D AUTO_CONFIG_DONE<1>.D AUTO_CONFIG_DONE_CYCLE<0>.D 11.0 AUTO_CONFIG_DONE_CYCLE<1>.D 11.4 CP_BASEADR<0>.D CP_BASEADR<1>.D CP_BASEADR<2>.D CP_BASEADR<3>.D CP_BASEADR<4>.D 11.0 CP_BASEADR<5>.D 11.0 CP_BASEADR<6>.D 11.0 CP_BASEADR<7>.D 11.0 Dout1<0>.D 11.0 Dout1<1>.D 10.0 Dout1<2>.D 10.0 Dout1<3>.D IDE_BASEADR<0>.D IDE_BASEADR<1>.D IDE_BASEADR<2>.D IDE_BASEADR<3>.D IDE_BASEADR<4>.D IDE_BASEADR<5>.D IDE_BASEADR<6>.D IDE_BASEADR<7>.D IDE_ENABLE.D IDE_R_S.D LAN_BASEADR<0>.D LAN_BASEADR<1>.D LAN_BASEADR<2>.D LAN_BASEADR<3>.D LAN_BASEADR<4>.D LAN_BASEADR<5>.D LAN_BASEADR<6>.D LAN_BASEADR<7>.D ROM_OE_S.D SHUT_UP<0>.D SHUT_UP<1>.D SHUT_UP<2>.D -------------------------------------------------------------------------------- Clock to Setup (tCYC) (nsec) (Clock: C3) \ From D I I I I I I I \ o D D D D D D D \ u E E E E E E E \ t _ _ _ _ _ _ _ \ 1 B B B B B B B \ < A A A A A A A \ 3 S S S S S S S \ > E E E E E E E \ . A A A A A A A \ Q D D D D D D D \ R R R R R R R \ < < < < < < < \ 0 1 2 3 4 5 6 \ > > > > > > > \ . . . . . . . \ Q Q Q Q Q Q Q \ \ \ \ \ \ \ \ \ \ \ To \------------------------------------------------ AUTO_CONFIG_DONE<0>.D AUTO_CONFIG_DONE<1>.D AUTO_CONFIG_DONE_CYCLE<0>.D AUTO_CONFIG_DONE_CYCLE<1>.D CP_BASEADR<0>.D CP_BASEADR<1>.D CP_BASEADR<2>.D CP_BASEADR<3>.D CP_BASEADR<4>.D CP_BASEADR<5>.D CP_BASEADR<6>.D CP_BASEADR<7>.D Dout1<0>.D Dout1<1>.D Dout1<2>.D Dout1<3>.D 11.0 IDE_BASEADR<0>.D 11.0 IDE_BASEADR<1>.D 11.0 IDE_BASEADR<2>.D 11.0 IDE_BASEADR<3>.D 11.0 IDE_BASEADR<4>.D 11.0 IDE_BASEADR<5>.D 11.0 IDE_BASEADR<6>.D 11.0 IDE_BASEADR<7>.D IDE_ENABLE.D IDE_R_S.D LAN_BASEADR<0>.D LAN_BASEADR<1>.D LAN_BASEADR<2>.D LAN_BASEADR<3>.D LAN_BASEADR<4>.D LAN_BASEADR<5>.D LAN_BASEADR<6>.D LAN_BASEADR<7>.D ROM_OE_S.D SHUT_UP<0>.D SHUT_UP<1>.D SHUT_UP<2>.D -------------------------------------------------------------------------------- Clock to Setup (tCYC) (nsec) (Clock: C3) \ From I I L L L L L L \ D D A A A A A A \ E E N N N N N N \ _ _ _ _ _ _ _ _ \ B E B B B B B B \ A N A A A A A A \ S A S S S S S S \ E B E E E E E E \ A L A A A A A A \ D E D D D D D D \ R . R R R R R R \ < Q < < < < < < \ 7 0 1 2 3 4 5 \ > > > > > > > \ . . . . . . . \ Q Q Q Q Q Q Q \ \ \ \ \ \ \ \ \ \ \ To \------------------------------------------------ AUTO_CONFIG_DONE<0>.D AUTO_CONFIG_DONE<1>.D AUTO_CONFIG_DONE_CYCLE<0>.D AUTO_CONFIG_DONE_CYCLE<1>.D CP_BASEADR<0>.D CP_BASEADR<1>.D CP_BASEADR<2>.D CP_BASEADR<3>.D CP_BASEADR<4>.D CP_BASEADR<5>.D CP_BASEADR<6>.D CP_BASEADR<7>.D Dout1<0>.D Dout1<1>.D Dout1<2>.D Dout1<3>.D IDE_BASEADR<0>.D IDE_BASEADR<1>.D IDE_BASEADR<2>.D IDE_BASEADR<3>.D IDE_BASEADR<4>.D IDE_BASEADR<5>.D IDE_BASEADR<6>.D IDE_BASEADR<7>.D 11.0 IDE_ENABLE.D 10.0 IDE_R_S.D 10.0 LAN_BASEADR<0>.D 11.0 LAN_BASEADR<1>.D 11.0 LAN_BASEADR<2>.D 11.0 LAN_BASEADR<3>.D 11.0 LAN_BASEADR<4>.D 11.0 LAN_BASEADR<5>.D 11.0 LAN_BASEADR<6>.D LAN_BASEADR<7>.D ROM_OE_S.D 10.0 SHUT_UP<0>.D SHUT_UP<1>.D SHUT_UP<2>.D -------------------------------------------------------------------------------- Clock to Setup (tCYC) (nsec) (Clock: C3) \ From L L S S S \ A A H H H \ N N U U U \ _ _ T T T \ B B _ _ _ \ A A U U U \ S S P P P \ E E < < < \ A A 0 1 2 \ D D > > > \ R R . . . \ < < Q Q Q \ 6 7 \ > > \ . . \ Q Q \ \ \ \ \ \ \ \ \ \ \ To \------------------------------ AUTO_CONFIG_DONE<0>.D AUTO_CONFIG_DONE<1>.D AUTO_CONFIG_DONE_CYCLE<0>.D 11.0 11.0 10.0 AUTO_CONFIG_DONE_CYCLE<1>.D 11.0 11.0 11.0 CP_BASEADR<0>.D 11.0 CP_BASEADR<1>.D 11.0 CP_BASEADR<2>.D 11.0 CP_BASEADR<3>.D 11.0 CP_BASEADR<4>.D 11.0 CP_BASEADR<5>.D 11.0 CP_BASEADR<6>.D 11.0 CP_BASEADR<7>.D 11.0 Dout1<0>.D Dout1<1>.D Dout1<2>.D Dout1<3>.D IDE_BASEADR<0>.D 11.0 IDE_BASEADR<1>.D 11.0 IDE_BASEADR<2>.D 11.0 IDE_BASEADR<3>.D 11.0 IDE_BASEADR<4>.D 11.0 IDE_BASEADR<5>.D 11.0 IDE_BASEADR<6>.D 11.0 IDE_BASEADR<7>.D 11.0 IDE_ENABLE.D IDE_R_S.D LAN_BASEADR<0>.D 11.0 LAN_BASEADR<1>.D 11.0 LAN_BASEADR<2>.D 11.0 LAN_BASEADR<3>.D 11.0 LAN_BASEADR<4>.D 11.0 LAN_BASEADR<5>.D 11.0 LAN_BASEADR<6>.D 11.0 11.0 LAN_BASEADR<7>.D 11.0 11.0 ROM_OE_S.D SHUT_UP<0>.D 10.0 SHUT_UP<1>.D 10.0 SHUT_UP<2>.D 10.0 Path Type Definition: Pad to Pad (tPD) - Reports pad to pad paths that start at input pads and end at output pads. Paths are not traced through registers. Clock Pad to Output Pad (tCO) - Reports paths that start at input pads trace through clock inputs of registers and end at output pads. Paths are not traced through PRE/CLR inputs of registers. Setup to Clock at Pad (tSU or tSUF) - Reports external setup time of data to clock at pad. Data path starts at an input pad and ends at register (Fast Input Register for tSUF) D/T input. Clock path starts at input pad and ends at the register clock input. Paths are not traced through registers. Pin-to-pin setup requirement is not reported or guaranteed for product-term clocks derived from macrocell feedback signals. Clock to Setup (tCYC) - Register to register cycle time. Include source register tCO and destination register tSU. Note that when the computed Maximum Clock Speed is limited by tCYC it is computed assuming that all registers are rising-edge sensitive.