MDF Database: version 1.0 MDF_INFO | LAN_IDE_CP | XC95288XL-10-TQ144 MACROCELL | 8 | 10 | Z3_DATA<0> ATTRIBUTES | 8685506 | 0 OUTPUTMC | 1 | 8 | 9 INPUTS | 11 | LAN_BASEADR<6> | A<22>.PIN | IDE_W_S.EXP | LAN_SM_RST | FCS | RW | $OpTx$FX_DC$107 | LAN_SM_FSM_FFd3 | LAN_SM_FSM_FFd4 | LAN_SM_FSM_FFd2 | LAN_SM_FSM_FFd1 INPUTMC | 8 | 6 | 13 | 8 | 11 | 6 | 0 | 4 | 3 | 0 | 10 | 14 | 3 | 0 | 1 | 12 | 4 INPUTP | 3 | 162 | 147 | 158 EXPORTS | 1 | 8 | 9 IMPORTS | 1 | 8 | 11 EQ | 10 | A<8>.D = ;Imported pterms FB9_12 DQ_SWAP & DQ<8>.PIN # !DQ_SWAP & DQ<0>.PIN; A<8>.CLK = CLK_EXT; // GCK A<8>.AP = LAN_SM_RST; A<8>.OE = !FCS & RW & !$OpTx$FX_DC$107; A<8>.CE = LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 & !LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1; Z3_DATA<0>.EXP = LAN_BASEADR<6> & !A<22>.PIN # !LAN_BASEADR<6> & A<22>.PIN GLOBALS | 1 | 2 | CLK_EXT MACROCELL | 15 | 5 | Z3_DATA<10> ATTRIBUTES | 8685506 | 0 INPUTS | 11 | DQ_SWAP | DQ<10>.PIN | DQ<2>.PIN | LAN_SM_RST | FCS | RW | $OpTx$FX_DC$107 | LAN_SM_FSM_FFd3 | LAN_SM_FSM_FFd4 | LAN_SM_FSM_FFd2 | LAN_SM_FSM_FFd1 INPUTMC | 7 | 8 | 1 | 6 | 0 | 4 | 3 | 0 | 10 | 14 | 3 | 0 | 1 | 12 | 4 INPUTP | 4 | 234 | 220 | 147 | 158 EQ | 7 | A<18>.D = DQ_SWAP & DQ<2>.PIN # !DQ_SWAP & DQ<10>.PIN; A<18>.CLK = CLK_EXT; // GCK A<18>.AP = LAN_SM_RST; A<18>.OE = !FCS & RW & !$OpTx$FX_DC$107; A<18>.CE = LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 & !LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1; GLOBALS | 1 | 2 | CLK_EXT MACROCELL | 15 | 2 | Z3_DATA<11> ATTRIBUTES | 8685506 | 0 INPUTS | 11 | DQ_SWAP | DQ<11>.PIN | DQ<3>.PIN | LAN_SM_RST | FCS | RW | $OpTx$FX_DC$107 | LAN_SM_FSM_FFd3 | LAN_SM_FSM_FFd4 | LAN_SM_FSM_FFd2 | LAN_SM_FSM_FFd1 INPUTMC | 7 | 8 | 1 | 6 | 0 | 4 | 3 | 0 | 10 | 14 | 3 | 0 | 1 | 12 | 4 INPUTP | 4 | 207 | 219 | 147 | 158 EQ | 7 | A<19>.D = DQ_SWAP & DQ<3>.PIN # !DQ_SWAP & DQ<11>.PIN; A<19>.CLK = CLK_EXT; // GCK A<19>.AP = LAN_SM_RST; A<19>.OE = !FCS & RW & !$OpTx$FX_DC$107; A<19>.CE = LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 & !LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1; GLOBALS | 1 | 2 | CLK_EXT MACROCELL | 15 | 1 | Z3_DATA<12> ATTRIBUTES | 8685506 | 0 INPUTS | 11 | DQ_SWAP | DQ<12>.PIN | DQ<4>.PIN | LAN_SM_RST | FCS | RW | $OpTx$FX_DC$107 | LAN_SM_FSM_FFd3 | LAN_SM_FSM_FFd4 | LAN_SM_FSM_FFd2 | LAN_SM_FSM_FFd1 INPUTMC | 7 | 8 | 1 | 6 | 0 | 4 | 3 | 0 | 10 | 14 | 3 | 0 | 1 | 12 | 4 INPUTP | 4 | 235 | 225 | 147 | 158 EQ | 7 | A<20>.D = DQ_SWAP & DQ<4>.PIN # !DQ_SWAP & DQ<12>.PIN; A<20>.CLK = CLK_EXT; // GCK A<20>.AP = LAN_SM_RST; A<20>.OE = !FCS & RW & !$OpTx$FX_DC$107; A<20>.CE = LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 & !LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1; GLOBALS | 1 | 2 | CLK_EXT MACROCELL | 14 | 16 | Z3_DATA<13> ATTRIBUTES | 8685506 | 0 OUTPUTMC | 1 | 14 | 17 INPUTS | 12 | DQ_SWAP | DQ<13>.PIN | UDS | LAN_SM_RST | FCS | RW | $OpTx$FX_DC$107 | LAN_SM_FSM_FFd3 | LAN_SM_FSM_FFd4 | LAN_SM_FSM_FFd2 | LAN_SM_FSM_FFd1 | LAN_READY.EXP INPUTMC | 8 | 8 | 1 | 6 | 0 | 4 | 3 | 0 | 10 | 14 | 3 | 0 | 1 | 12 | 4 | 14 | 15 INPUTP | 4 | 204 | 155 | 147 | 158 EXPORTS | 1 | 14 | 17 IMPORTS | 1 | 14 | 15 EQ | 10 | A<21>.D = !DQ_SWAP & DQ<13>.PIN ;Imported pterms FB15_16 # DQ_SWAP & DQ<5>.PIN; A<21>.CLK = CLK_EXT; // GCK A<21>.AP = LAN_SM_RST; A<21>.OE = !FCS & RW & !$OpTx$FX_DC$107; A<21>.CE = LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 & !LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1; Z3_DATA<13>.EXP = !UDS & LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 & LAN_SM_FSM_FFd1 GLOBALS | 1 | 2 | CLK_EXT MACROCELL | 14 | 14 | Z3_DATA<14> ATTRIBUTES | 8685506 | 0 OUTPUTMC | 1 | 14 | 15 INPUTS | 13 | DQ_SWAP | DQ<14>.PIN | DS1 | LAN_SM_RST | FCS | RW | $OpTx$FX_DC$107 | LAN_SM_FSM_FFd3 | LAN_SM_FSM_FFd4 | LAN_SM_FSM_FFd2 | LAN_SM_FSM_FFd1 | DS0 | Z3_DATA<15>.EXP INPUTMC | 8 | 8 | 1 | 6 | 0 | 4 | 3 | 0 | 10 | 14 | 3 | 0 | 1 | 12 | 4 | 14 | 13 INPUTP | 5 | 236 | 148 | 147 | 158 | 170 EXPORTS | 1 | 14 | 15 IMPORTS | 1 | 14 | 13 EQ | 9 | A<22>.D = !DQ_SWAP & DQ<14>.PIN ;Imported pterms FB15_14 # DQ_SWAP & DQ<6>.PIN; A<22>.CLK = CLK_EXT; // GCK A<22>.AP = LAN_SM_RST; A<22>.OE = !FCS & RW & !$OpTx$FX_DC$107; A<22>.CE = LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 & !LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1; Z3_DATA<14>.EXP = DS1 & DS0 & !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 GLOBALS | 1 | 2 | CLK_EXT MACROCELL | 14 | 13 | Z3_DATA<15> ATTRIBUTES | 8685506 | 0 OUTPUTMC | 1 | 14 | 14 INPUTS | 12 | DQ_SWAP | DQ<15>.PIN | DQ<6>.PIN | LAN_SM_RST | FCS | RW | $OpTx$FX_DC$107 | LAN_SM_FSM_FFd3 | LAN_SM_FSM_FFd4 | LAN_SM_FSM_FFd2 | LAN_SM_FSM_FFd1 | LAN_RD_S.EXP INPUTMC | 8 | 8 | 1 | 6 | 0 | 4 | 3 | 0 | 10 | 14 | 3 | 0 | 1 | 12 | 4 | 14 | 12 INPUTP | 4 | 202 | 227 | 147 | 158 EXPORTS | 1 | 14 | 14 IMPORTS | 1 | 14 | 12 EQ | 9 | A<23>.D = !DQ_SWAP & DQ<15>.PIN ;Imported pterms FB15_13 # DQ_SWAP & DQ<7>.PIN; A<23>.CLK = CLK_EXT; // GCK A<23>.AP = LAN_SM_RST; A<23>.OE = !FCS & RW & !$OpTx$FX_DC$107; A<23>.CE = LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 & !LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1; Z3_DATA<15>.EXP = DQ_SWAP & DQ<6>.PIN GLOBALS | 1 | 2 | CLK_EXT MACROCELL | 8 | 13 | Z3_DATA<1> ATTRIBUTES | 8685506 | 0 INPUTS | 11 | DQ_SWAP | DQ<1>.PIN | DQ<9>.PIN | LAN_SM_RST | FCS | RW | $OpTx$FX_DC$107 | LAN_SM_FSM_FFd3 | LAN_SM_FSM_FFd4 | LAN_SM_FSM_FFd2 | LAN_SM_FSM_FFd1 INPUTMC | 7 | 8 | 1 | 6 | 0 | 4 | 3 | 0 | 10 | 14 | 3 | 0 | 1 | 12 | 4 INPUTP | 4 | 216 | 209 | 147 | 158 EQ | 7 | A<9>.D = DQ_SWAP & DQ<9>.PIN # !DQ_SWAP & DQ<1>.PIN; A<9>.CLK = CLK_EXT; // GCK A<9>.AP = LAN_SM_RST; A<9>.OE = !FCS & RW & !$OpTx$FX_DC$107; A<9>.CE = LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 & !LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1; GLOBALS | 1 | 2 | CLK_EXT MACROCELL | 8 | 16 | Z3_DATA<2> ATTRIBUTES | 8685506 | 0 INPUTS | 11 | DQ_SWAP | DQ<10>.PIN | DQ<2>.PIN | LAN_SM_RST | FCS | RW | $OpTx$FX_DC$107 | LAN_SM_FSM_FFd3 | LAN_SM_FSM_FFd4 | LAN_SM_FSM_FFd2 | LAN_SM_FSM_FFd1 INPUTMC | 7 | 8 | 1 | 6 | 0 | 4 | 3 | 0 | 10 | 14 | 3 | 0 | 1 | 12 | 4 INPUTP | 4 | 234 | 220 | 147 | 158 EQ | 7 | A<10>.D = DQ_SWAP & DQ<10>.PIN # !DQ_SWAP & DQ<2>.PIN; A<10>.CLK = CLK_EXT; // GCK A<10>.AP = LAN_SM_RST; A<10>.OE = !FCS & RW & !$OpTx$FX_DC$107; A<10>.CE = LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 & !LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1; GLOBALS | 1 | 2 | CLK_EXT MACROCELL | 10 | 2 | Z3_DATA<3> ATTRIBUTES | 8685506 | 0 OUTPUTMC | 1 | 10 | 1 INPUTS | 12 | DQ_SWAP | DQ<11>.PIN | DQ<5>.PIN | LAN_SM_RST | FCS | RW | $OpTx$FX_DC$107 | LAN_SM_FSM_FFd3 | LAN_SM_FSM_FFd4 | LAN_SM_FSM_FFd2 | LAN_SM_FSM_FFd1 | Z3_DATA<28>.EXP INPUTMC | 8 | 8 | 1 | 6 | 0 | 4 | 3 | 0 | 10 | 14 | 3 | 0 | 1 | 12 | 4 | 10 | 3 INPUTP | 4 | 207 | 221 | 147 | 158 EXPORTS | 1 | 10 | 1 IMPORTS | 1 | 10 | 3 EQ | 9 | A<11>.D = DQ_SWAP & DQ<11>.PIN ;Imported pterms FB11_4 # !DQ_SWAP & DQ<3>.PIN; A<11>.CLK = CLK_EXT; // GCK A<11>.AP = LAN_SM_RST; A<11>.OE = !FCS & RW & !$OpTx$FX_DC$107; A<11>.CE = LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 & !LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1; Z3_DATA<3>.EXP = DQ_SWAP & DQ<5>.PIN GLOBALS | 1 | 2 | CLK_EXT MACROCELL | 10 | 4 | Z3_DATA<4> ATTRIBUTES | 8685506 | 0 INPUTS | 11 | DQ_SWAP | DQ<12>.PIN | DQ<4>.PIN | LAN_SM_RST | FCS | RW | $OpTx$FX_DC$107 | LAN_SM_FSM_FFd3 | LAN_SM_FSM_FFd4 | LAN_SM_FSM_FFd2 | LAN_SM_FSM_FFd1 INPUTMC | 7 | 8 | 1 | 6 | 0 | 4 | 3 | 0 | 10 | 14 | 3 | 0 | 1 | 12 | 4 INPUTP | 4 | 235 | 225 | 147 | 158 EQ | 7 | A<12>.D = DQ_SWAP & DQ<12>.PIN # !DQ_SWAP & DQ<4>.PIN; A<12>.CLK = CLK_EXT; // GCK A<12>.AP = LAN_SM_RST; A<12>.OE = !FCS & RW & !$OpTx$FX_DC$107; A<12>.CE = LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 & !LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1; GLOBALS | 1 | 2 | CLK_EXT MACROCELL | 10 | 9 | Z3_DATA<5> ATTRIBUTES | 8685506 | 0 INPUTS | 11 | DQ_SWAP | DQ<13>.PIN | DQ<5>.PIN | LAN_SM_RST | FCS | RW | $OpTx$FX_DC$107 | LAN_SM_FSM_FFd3 | LAN_SM_FSM_FFd4 | LAN_SM_FSM_FFd2 | LAN_SM_FSM_FFd1 INPUTMC | 7 | 8 | 1 | 6 | 0 | 4 | 3 | 0 | 10 | 14 | 3 | 0 | 1 | 12 | 4 INPUTP | 4 | 204 | 221 | 147 | 158 EQ | 7 | A<13>.D = DQ_SWAP & DQ<13>.PIN # !DQ_SWAP & DQ<5>.PIN; A<13>.CLK = CLK_EXT; // GCK A<13>.AP = LAN_SM_RST; A<13>.OE = !FCS & RW & !$OpTx$FX_DC$107; A<13>.CE = LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 & !LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1; GLOBALS | 1 | 2 | CLK_EXT MACROCELL | 10 | 10 | Z3_DATA<6> ATTRIBUTES | 8685506 | 0 INPUTS | 11 | DQ_SWAP | DQ<14>.PIN | DQ<6>.PIN | LAN_SM_RST | FCS | RW | $OpTx$FX_DC$107 | LAN_SM_FSM_FFd3 | LAN_SM_FSM_FFd4 | LAN_SM_FSM_FFd2 | LAN_SM_FSM_FFd1 INPUTMC | 7 | 8 | 1 | 6 | 0 | 4 | 3 | 0 | 10 | 14 | 3 | 0 | 1 | 12 | 4 INPUTP | 4 | 236 | 227 | 147 | 158 EQ | 7 | A<14>.D = DQ_SWAP & DQ<14>.PIN # !DQ_SWAP & DQ<6>.PIN; A<14>.CLK = CLK_EXT; // GCK A<14>.AP = LAN_SM_RST; A<14>.OE = !FCS & RW & !$OpTx$FX_DC$107; A<14>.CE = LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 & !LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1; GLOBALS | 1 | 2 | CLK_EXT MACROCELL | 12 | 7 | Z3_DATA<7> ATTRIBUTES | 8685506 | 0 INPUTS | 11 | DQ_SWAP | DQ<15>.PIN | DQ<7>.PIN | LAN_SM_RST | FCS | RW | $OpTx$FX_DC$107 | LAN_SM_FSM_FFd3 | LAN_SM_FSM_FFd4 | LAN_SM_FSM_FFd2 | LAN_SM_FSM_FFd1 INPUTMC | 7 | 8 | 1 | 6 | 0 | 4 | 3 | 0 | 10 | 14 | 3 | 0 | 1 | 12 | 4 INPUTP | 4 | 202 | 226 | 147 | 158 EQ | 7 | A<15>.D = DQ_SWAP & DQ<15>.PIN # !DQ_SWAP & DQ<7>.PIN; A<15>.CLK = CLK_EXT; // GCK A<15>.AP = LAN_SM_RST; A<15>.OE = !FCS & RW & !$OpTx$FX_DC$107; A<15>.CE = LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 & !LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1; GLOBALS | 1 | 2 | CLK_EXT MACROCELL | 15 | 10 | Z3_DATA<8> ATTRIBUTES | 8685506 | 0 INPUTS | 11 | DQ_SWAP | DQ<0>.PIN | DQ<8>.PIN | LAN_SM_RST | FCS | RW | $OpTx$FX_DC$107 | LAN_SM_FSM_FFd3 | LAN_SM_FSM_FFd4 | LAN_SM_FSM_FFd2 | LAN_SM_FSM_FFd1 INPUTMC | 7 | 8 | 1 | 6 | 0 | 4 | 3 | 0 | 10 | 14 | 3 | 0 | 1 | 12 | 4 INPUTP | 4 | 217 | 231 | 147 | 158 EQ | 7 | A<16>.D = DQ_SWAP & DQ<0>.PIN # !DQ_SWAP & DQ<8>.PIN; A<16>.CLK = CLK_EXT; // GCK A<16>.AP = LAN_SM_RST; A<16>.OE = !FCS & RW & !$OpTx$FX_DC$107; A<16>.CE = LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 & !LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1; GLOBALS | 1 | 2 | CLK_EXT MACROCELL | 15 | 7 | Z3_DATA<9> ATTRIBUTES | 8685506 | 0 INPUTS | 11 | DQ_SWAP | DQ<1>.PIN | DQ<9>.PIN | LAN_SM_RST | FCS | RW | $OpTx$FX_DC$107 | LAN_SM_FSM_FFd3 | LAN_SM_FSM_FFd4 | LAN_SM_FSM_FFd2 | LAN_SM_FSM_FFd1 INPUTMC | 7 | 8 | 1 | 6 | 0 | 4 | 3 | 0 | 10 | 14 | 3 | 0 | 1 | 12 | 4 INPUTP | 4 | 216 | 209 | 147 | 158 EQ | 7 | A<17>.D = DQ_SWAP & DQ<1>.PIN # !DQ_SWAP & DQ<9>.PIN; A<17>.CLK = CLK_EXT; // GCK A<17>.AP = LAN_SM_RST; A<17>.OE = !FCS & RW & !$OpTx$FX_DC$107; A<17>.CE = LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 & !LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1; GLOBALS | 1 | 2 | CLK_EXT MACROCELL | 7 | 15 | AUTO_CONFIG_Z2_DONE<0> ATTRIBUTES | 8520560 | 0 OUTPUTMC | 44 | 7 | 15 | 13 | 4 | 13 | 3 | 13 | 9 | 13 | 8 | 13 | 7 | 13 | 0 | 9 | 17 | 9 | 15 | 9 | 14 | 13 | 5 | 3 | 17 | 3 | 16 | 3 | 15 | 3 | 14 | 9 | 12 | 9 | 8 | 9 | 6 | 9 | 3 | 4 | 6 | 13 | 1 | 13 | 15 | 13 | 6 | 11 | 14 | 9 | 16 | 11 | 4 | 13 | 10 | 3 | 0 | 3 | 13 | 9 | 0 | 9 | 2 | 9 | 5 | 9 | 7 | 9 | 11 | 9 | 13 | 11 | 3 | 11 | 6 | 11 | 13 | 11 | 16 | 11 | 17 | 13 | 12 | 13 | 13 | 13 | 17 | 7 | 16 INPUTS | 7 | AUTO_CONFIG_Z2_DONE<0> | AUTO_CONFIG_Z2_DONE_CYCLE<0> | SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF | RESET | AS | IDE_BASEADR<7> | A<23>.PIN INPUTMC | 4 | 7 | 15 | 13 | 4 | 2 | 8 | 9 | 3 INPUTP | 3 | 263 | 152 | 161 EXPORTS | 1 | 7 | 16 EQ | 6 | !AUTO_CONFIG_Z2_DONE<0>.D = !AUTO_CONFIG_Z2_DONE<0> & !AUTO_CONFIG_Z2_DONE_CYCLE<0>; AUTO_CONFIG_Z2_DONE<0>.CLK = SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF; AUTO_CONFIG_Z2_DONE<0>.AR = !RESET; AUTO_CONFIG_Z2_DONE<0>.CE = AS; AUTO_CONFIG_Z2_DONE<0>.EXP = !IDE_BASEADR<7> & A<23>.PIN MACROCELL | 7 | 14 | AUTO_CONFIG_Z2_DONE<1> ATTRIBUTES | 8520560 | 0 OUTPUTMC | 20 | 7 | 14 | 13 | 3 | 3 | 17 | 3 | 16 | 3 | 15 | 3 | 14 | 9 | 12 | 9 | 8 | 9 | 6 | 9 | 3 | 4 | 6 | 13 | 15 | 9 | 11 | 13 | 10 | 3 | 0 | 3 | 13 | 9 | 2 | 9 | 5 | 9 | 7 | 13 | 13 INPUTS | 5 | AUTO_CONFIG_Z2_DONE<1> | AUTO_CONFIG_Z2_DONE_CYCLE<1> | SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF | RESET | AS INPUTMC | 3 | 7 | 14 | 13 | 3 | 2 | 8 INPUTP | 2 | 263 | 152 EQ | 5 | !AUTO_CONFIG_Z2_DONE<1>.D = !AUTO_CONFIG_Z2_DONE<1> & !AUTO_CONFIG_Z2_DONE_CYCLE<1>; AUTO_CONFIG_Z2_DONE<1>.CLK = SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF; AUTO_CONFIG_Z2_DONE<1>.AR = !RESET; AUTO_CONFIG_Z2_DONE<1>.CE = AS; MACROCELL | 13 | 4 | AUTO_CONFIG_Z2_DONE_CYCLE<0> ATTRIBUTES | 4326192 | 0 OUTPUTMC | 3 | 7 | 15 | 13 | 4 | 13 | 5 INPUTS | 17 | AS | AUTO_CONFIG_Z2_DONE<0> | UDS | AUTO_CONFIG_Z2_DONE_CYCLE<0> | A<5> | A<4> | A<1> | RW | A<6> | A<3> | AUTOCONFIG_Z2_ACCESS | LDS | SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF | RESET | D<15>.PIN | CP_BASEADR<7> | A<2> INPUTMC | 5 | 7 | 15 | 13 | 4 | 4 | 6 | 2 | 8 | 13 | 5 INPUTP | 12 | 152 | 155 | 91 | 97 | 107 | 158 | 98 | 99 | 157 | 263 | 89 | 101 EXPORTS | 1 | 13 | 5 EQ | 11 | AUTO_CONFIG_Z2_DONE_CYCLE<0>.T = !AS & !AUTO_CONFIG_Z2_DONE<0> & !UDS & !AUTO_CONFIG_Z2_DONE_CYCLE<0> & !A<5> & !A<4> & !A<1> & !RW & A<6> & A<3> & AUTOCONFIG_Z2_ACCESS # !AS & !AUTO_CONFIG_Z2_DONE<0> & !LDS & !AUTO_CONFIG_Z2_DONE_CYCLE<0> & !A<5> & !A<4> & !A<1> & !RW & A<6> & A<3> & AUTOCONFIG_Z2_ACCESS; AUTO_CONFIG_Z2_DONE_CYCLE<0>.CLK = SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF; AUTO_CONFIG_Z2_DONE_CYCLE<0>.AR = !RESET; AUTO_CONFIG_Z2_DONE_CYCLE<0>.EXP = D<15>.PIN & !AS & !AUTO_CONFIG_Z2_DONE<0> & !LDS & !CP_BASEADR<7> & !A<5> & !A<4> & !A<1> & !RW & A<6> & A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS MACROCELL | 13 | 3 | AUTO_CONFIG_Z2_DONE_CYCLE<1> ATTRIBUTES | 4326192 | 0 OUTPUTMC | 2 | 7 | 14 | 13 | 3 INPUTS | 15 | AS | AUTO_CONFIG_Z2_DONE<0> | AUTO_CONFIG_Z2_DONE<1> | UDS | AUTO_CONFIG_Z2_DONE_CYCLE<1> | A<5> | A<4> | A<1> | RW | A<6> | A<3> | AUTOCONFIG_Z2_ACCESS | LDS | SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF | RESET INPUTMC | 5 | 7 | 15 | 7 | 14 | 13 | 3 | 4 | 6 | 2 | 8 INPUTP | 10 | 152 | 155 | 91 | 97 | 107 | 158 | 98 | 99 | 157 | 263 EQ | 8 | AUTO_CONFIG_Z2_DONE_CYCLE<1>.T = !AS & AUTO_CONFIG_Z2_DONE<0> & !AUTO_CONFIG_Z2_DONE<1> & !UDS & !AUTO_CONFIG_Z2_DONE_CYCLE<1> & !A<5> & !A<4> & !A<1> & !RW & A<6> & A<3> & AUTOCONFIG_Z2_ACCESS # !AS & AUTO_CONFIG_Z2_DONE<0> & !AUTO_CONFIG_Z2_DONE<1> & !LDS & !AUTO_CONFIG_Z2_DONE_CYCLE<1> & !A<5> & !A<4> & !A<1> & !RW & A<6> & A<3> & AUTOCONFIG_Z2_ACCESS; AUTO_CONFIG_Z2_DONE_CYCLE<1>.CLK = SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF; AUTO_CONFIG_Z2_DONE_CYCLE<1>.AR = !RESET; MACROCELL | 8 | 15 | AUTO_CONFIG_DONE ATTRIBUTES | 8553296 | 0 OUTPUTMC | 2 | 7 | 13 | 13 | 10 INPUTS | 3 | AUTO_CONFIG_DONE_CYCLE | RESET | FCS INPUTMC | 1 | 6 | 3 INPUTP | 2 | 263 | 147 EQ | 4 | AUTO_CONFIG_DONE.D = AUTO_CONFIG_DONE_CYCLE; AUTO_CONFIG_DONE.CLK = CLK_EXT; // GCK AUTO_CONFIG_DONE.AR = !RESET; AUTO_CONFIG_DONE.CE = FCS; GLOBALS | 1 | 2 | CLK_EXT MACROCELL | 6 | 3 | AUTO_CONFIG_DONE_CYCLE ATTRIBUTES | 4358992 | 0 OUTPUTMC | 3 | 8 | 15 | 6 | 3 | 6 | 2 INPUTS | 16 | AUTO_CONFIG_DONE_CYCLE | RW | Z3_ADR<2> | Z3_ADR_0 | Z3_ADR<6> | Z3_ADR<3> | Z3_ADR<4> | Z3_ADR<5> | RESET | UDS | FCS | AUTOCONFIG_Z3_ACCESS | DS1 | LAN_ACCESS | D_OUT<5> | DS0 INPUTMC | 10 | 6 | 3 | 9 | 0 | 11 | 17 | 2 | 16 | 11 | 10 | 11 | 12 | 11 | 13 | 7 | 13 | 8 | 8 | 3 | 9 INPUTP | 6 | 158 | 263 | 155 | 147 | 148 | 170 EXPORTS | 1 | 6 | 2 EQ | 9 | AUTO_CONFIG_DONE_CYCLE.T = !AUTO_CONFIG_DONE_CYCLE & !RW & !Z3_ADR<2> & Z3_ADR_0 & !Z3_ADR<6> & !Z3_ADR<3> & Z3_ADR<4> & !Z3_ADR<5>; AUTO_CONFIG_DONE_CYCLE.CLK = CLK_EXT; // GCK AUTO_CONFIG_DONE_CYCLE.AR = !RESET; AUTO_CONFIG_DONE_CYCLE.CE = !UDS & !FCS & AUTOCONFIG_Z3_ACCESS; AUTO_CONFIG_DONE_CYCLE.EXP = !DS1 & !FCS & RW & !LAN_ACCESS & AUTOCONFIG_Z3_ACCESS & D_OUT<5> # !DS0 & !FCS & RW & !LAN_ACCESS & AUTOCONFIG_Z3_ACCESS & D_OUT<5> GLOBALS | 1 | 2 | CLK_EXT MACROCELL | 13 | 9 | CP_BASEADR<0> ATTRIBUTES | 4326304 | 0 OUTPUTMC | 3 | 13 | 9 | 4 | 1 | 13 | 8 INPUTS | 17 | D<8>.PIN | AS | AUTO_CONFIG_Z2_DONE<0> | UDS | CP_BASEADR<0> | A<5> | A<4> | A<1> | RW | A<6> | A<3> | A<2> | AUTOCONFIG_Z2_ACCESS | LDS | SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF | RESET | CP_BASEADR<1>.EXP INPUTMC | 5 | 7 | 15 | 13 | 9 | 4 | 6 | 2 | 8 | 13 | 8 INPUTP | 12 | 32 | 152 | 155 | 91 | 97 | 107 | 158 | 98 | 99 | 101 | 157 | 263 IMPORTS | 1 | 13 | 8 EQ | 15 | CP_BASEADR<0>.T = D<8>.PIN & !AS & !AUTO_CONFIG_Z2_DONE<0> & !UDS & !CP_BASEADR<0> & !A<5> & !A<4> & !A<1> & !RW & A<6> & A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS # !D<8>.PIN & !AS & !AUTO_CONFIG_Z2_DONE<0> & !UDS & CP_BASEADR<0> & !A<5> & !A<4> & !A<1> & !RW & A<6> & A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS # !D<8>.PIN & !AS & !AUTO_CONFIG_Z2_DONE<0> & !LDS & CP_BASEADR<0> & !A<5> & !A<4> & !A<1> & !RW & A<6> & A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS ;Imported pterms FB14_9 # D<8>.PIN & !AS & !AUTO_CONFIG_Z2_DONE<0> & !LDS & !CP_BASEADR<0> & !A<5> & !A<4> & !A<1> & !RW & A<6> & A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS; CP_BASEADR<0>.CLK = SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF; CP_BASEADR<0>.AP = !RESET; MACROCELL | 13 | 8 | CP_BASEADR<1> ATTRIBUTES | 4326304 | 0 OUTPUTMC | 4 | 13 | 8 | 4 | 0 | 13 | 7 | 13 | 9 INPUTS | 19 | D<9>.PIN | AS | AUTO_CONFIG_Z2_DONE<0> | UDS | CP_BASEADR<1> | A<5> | A<4> | A<1> | RW | A<6> | A<3> | A<2> | AUTOCONFIG_Z2_ACCESS | LDS | SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF | RESET | D<8>.PIN | CP_BASEADR<0> | CP_BASEADR<2>.EXP INPUTMC | 6 | 7 | 15 | 13 | 8 | 4 | 6 | 2 | 8 | 13 | 9 | 13 | 7 INPUTP | 13 | 73 | 152 | 155 | 91 | 97 | 107 | 158 | 98 | 99 | 101 | 157 | 263 | 32 EXPORTS | 1 | 13 | 9 IMPORTS | 1 | 13 | 7 EQ | 18 | CP_BASEADR<1>.T = !D<9>.PIN & !AS & !AUTO_CONFIG_Z2_DONE<0> & !UDS & CP_BASEADR<1> & !A<5> & !A<4> & !A<1> & !RW & A<6> & A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS # !D<9>.PIN & !AS & !AUTO_CONFIG_Z2_DONE<0> & !LDS & CP_BASEADR<1> & !A<5> & !A<4> & !A<1> & !RW & A<6> & A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS ;Imported pterms FB14_8 # D<9>.PIN & !AS & !AUTO_CONFIG_Z2_DONE<0> & !UDS & !CP_BASEADR<1> & !A<5> & !A<4> & !A<1> & !RW & A<6> & A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS # D<9>.PIN & !AS & !AUTO_CONFIG_Z2_DONE<0> & !LDS & !CP_BASEADR<1> & !A<5> & !A<4> & !A<1> & !RW & A<6> & A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS; CP_BASEADR<1>.CLK = SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF; CP_BASEADR<1>.AP = !RESET; CP_BASEADR<1>.EXP = D<8>.PIN & !AS & !AUTO_CONFIG_Z2_DONE<0> & !LDS & !CP_BASEADR<0> & !A<5> & !A<4> & !A<1> & !RW & A<6> & A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS MACROCELL | 13 | 7 | CP_BASEADR<2> ATTRIBUTES | 4326304 | 0 OUTPUTMC | 4 | 13 | 7 | 4 | 0 | 13 | 6 | 13 | 8 INPUTS | 19 | D<10>.PIN | AS | AUTO_CONFIG_Z2_DONE<0> | UDS | CP_BASEADR<2> | A<5> | A<4> | A<1> | RW | A<6> | A<3> | A<2> | AUTOCONFIG_Z2_ACCESS | D<9>.PIN | SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF | RESET | CP_BASEADR<1> | LDS | EXP53_.EXP INPUTMC | 6 | 7 | 15 | 13 | 7 | 4 | 6 | 2 | 8 | 13 | 8 | 13 | 6 INPUTP | 13 | 74 | 152 | 155 | 91 | 97 | 107 | 158 | 98 | 99 | 101 | 73 | 263 | 157 EXPORTS | 1 | 13 | 8 IMPORTS | 1 | 13 | 6 EQ | 21 | CP_BASEADR<2>.T = !D<10>.PIN & !AS & !AUTO_CONFIG_Z2_DONE<0> & !UDS & CP_BASEADR<2> & !A<5> & !A<4> & !A<1> & !RW & A<6> & A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS ;Imported pterms FB14_7 # D<10>.PIN & !AS & !AUTO_CONFIG_Z2_DONE<0> & !UDS & !CP_BASEADR<2> & !A<5> & !A<4> & !A<1> & !RW & A<6> & A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS # D<10>.PIN & !AS & !AUTO_CONFIG_Z2_DONE<0> & !LDS & !CP_BASEADR<2> & !A<5> & !A<4> & !A<1> & !RW & A<6> & A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS # !D<10>.PIN & !AS & !AUTO_CONFIG_Z2_DONE<0> & !LDS & CP_BASEADR<2> & !A<5> & !A<4> & !A<1> & !RW & A<6> & A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS; CP_BASEADR<2>.CLK = SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF; CP_BASEADR<2>.AP = !RESET; CP_BASEADR<2>.EXP = D<9>.PIN & !AS & !AUTO_CONFIG_Z2_DONE<0> & !UDS & !CP_BASEADR<1> & !A<5> & !A<4> & !A<1> & !RW & A<6> & A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS # D<9>.PIN & !AS & !AUTO_CONFIG_Z2_DONE<0> & !LDS & !CP_BASEADR<1> & !A<5> & !A<4> & !A<1> & !RW & A<6> & A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS MACROCELL | 13 | 0 | CP_BASEADR<3> ATTRIBUTES | 4326304 | 0 OUTPUTMC | 4 | 13 | 0 | 4 | 0 | 4 | 2 | 13 | 17 INPUTS | 17 | D<11>.PIN | AS | AUTO_CONFIG_Z2_DONE<0> | UDS | CP_BASEADR<3> | A<5> | A<4> | A<1> | RW | A<6> | A<3> | A<2> | AUTOCONFIG_Z2_ACCESS | LDS | SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF | RESET | EXP55_.EXP INPUTMC | 5 | 7 | 15 | 13 | 0 | 4 | 6 | 2 | 8 | 13 | 17 INPUTP | 12 | 77 | 152 | 155 | 91 | 97 | 107 | 158 | 98 | 99 | 101 | 157 | 263 IMPORTS | 1 | 13 | 17 EQ | 15 | CP_BASEADR<3>.T = D<11>.PIN & !AS & !AUTO_CONFIG_Z2_DONE<0> & !UDS & !CP_BASEADR<3> & !A<5> & !A<4> & !A<1> & !RW & A<6> & A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS # !D<11>.PIN & !AS & !AUTO_CONFIG_Z2_DONE<0> & !UDS & CP_BASEADR<3> & !A<5> & !A<4> & !A<1> & !RW & A<6> & A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS # !D<11>.PIN & !AS & !AUTO_CONFIG_Z2_DONE<0> & !LDS & CP_BASEADR<3> & !A<5> & !A<4> & !A<1> & !RW & A<6> & A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS ;Imported pterms FB14_18 # D<11>.PIN & !AS & !AUTO_CONFIG_Z2_DONE<0> & !LDS & !CP_BASEADR<3> & !A<5> & !A<4> & !A<1> & !RW & A<6> & A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS; CP_BASEADR<3>.CLK = SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF; CP_BASEADR<3>.AP = !RESET; MACROCELL | 9 | 17 | CP_BASEADR<4> ATTRIBUTES | 4326304 | 0 OUTPUTMC | 3 | 9 | 17 | 4 | 2 | 9 | 0 INPUTS | 17 | D<12>.PIN | AS | AUTO_CONFIG_Z2_DONE<0> | UDS | CP_BASEADR<4> | A<5> | A<4> | A<1> | RW | A<6> | A<3> | A<2> | AUTOCONFIG_Z2_ACCESS | LDS | SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF | RESET | Z3_ADR<2>.EXP INPUTMC | 5 | 7 | 15 | 9 | 17 | 4 | 6 | 2 | 8 | 9 | 0 INPUTP | 12 | 78 | 152 | 155 | 91 | 97 | 107 | 158 | 98 | 99 | 101 | 157 | 263 IMPORTS | 1 | 9 | 0 EQ | 15 | CP_BASEADR<4>.T = D<12>.PIN & !AS & !AUTO_CONFIG_Z2_DONE<0> & !UDS & !CP_BASEADR<4> & !A<5> & !A<4> & !A<1> & !RW & A<6> & A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS # !D<12>.PIN & !AS & !AUTO_CONFIG_Z2_DONE<0> & !UDS & CP_BASEADR<4> & !A<5> & !A<4> & !A<1> & !RW & A<6> & A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS # !D<12>.PIN & !AS & !AUTO_CONFIG_Z2_DONE<0> & !LDS & CP_BASEADR<4> & !A<5> & !A<4> & !A<1> & !RW & A<6> & A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS ;Imported pterms FB10_1 # D<12>.PIN & !AS & !AUTO_CONFIG_Z2_DONE<0> & !LDS & !CP_BASEADR<4> & !A<5> & !A<4> & !A<1> & !RW & A<6> & A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS; CP_BASEADR<4>.CLK = SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF; CP_BASEADR<4>.AP = !RESET; MACROCELL | 9 | 15 | CP_BASEADR<5> ATTRIBUTES | 4326304 | 0 OUTPUTMC | 3 | 9 | 15 | 4 | 2 | 9 | 16 INPUTS | 17 | D<13>.PIN | AS | AUTO_CONFIG_Z2_DONE<0> | UDS | CP_BASEADR<5> | A<5> | A<4> | A<1> | RW | A<6> | A<3> | A<2> | AUTOCONFIG_Z2_ACCESS | LDS | SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF | RESET | DQ_10_IOBUFE.EXP INPUTMC | 5 | 7 | 15 | 9 | 15 | 4 | 6 | 2 | 8 | 9 | 16 INPUTP | 12 | 80 | 152 | 155 | 91 | 97 | 107 | 158 | 98 | 99 | 101 | 157 | 263 IMPORTS | 1 | 9 | 16 EQ | 15 | CP_BASEADR<5>.T = D<13>.PIN & !AS & !AUTO_CONFIG_Z2_DONE<0> & !UDS & !CP_BASEADR<5> & !A<5> & !A<4> & !A<1> & !RW & A<6> & A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS # !D<13>.PIN & !AS & !AUTO_CONFIG_Z2_DONE<0> & !UDS & CP_BASEADR<5> & !A<5> & !A<4> & !A<1> & !RW & A<6> & A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS # !D<13>.PIN & !AS & !AUTO_CONFIG_Z2_DONE<0> & !LDS & CP_BASEADR<5> & !A<5> & !A<4> & !A<1> & !RW & A<6> & A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS ;Imported pterms FB10_17 # D<13>.PIN & !AS & !AUTO_CONFIG_Z2_DONE<0> & !LDS & !CP_BASEADR<5> & !A<5> & !A<4> & !A<1> & !RW & A<6> & A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS; CP_BASEADR<5>.CLK = SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF; CP_BASEADR<5>.AP = !RESET; MACROCELL | 9 | 14 | CP_BASEADR<6> ATTRIBUTES | 4326304 | 0 OUTPUTMC | 3 | 9 | 14 | 4 | 3 | 9 | 13 INPUTS | 17 | D<14>.PIN | AS | AUTO_CONFIG_Z2_DONE<0> | UDS | CP_BASEADR<6> | A<5> | A<4> | A<1> | RW | A<6> | A<3> | A<2> | AUTOCONFIG_Z2_ACCESS | LDS | SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF | RESET | DQ_8_IOBUFE.EXP INPUTMC | 5 | 7 | 15 | 9 | 14 | 4 | 6 | 2 | 8 | 9 | 13 INPUTP | 12 | 81 | 152 | 155 | 91 | 97 | 107 | 158 | 98 | 99 | 101 | 157 | 263 IMPORTS | 1 | 9 | 13 EQ | 15 | CP_BASEADR<6>.T = D<14>.PIN & !AS & !AUTO_CONFIG_Z2_DONE<0> & !UDS & !CP_BASEADR<6> & !A<5> & !A<4> & !A<1> & !RW & A<6> & A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS # !D<14>.PIN & !AS & !AUTO_CONFIG_Z2_DONE<0> & !UDS & CP_BASEADR<6> & !A<5> & !A<4> & !A<1> & !RW & A<6> & A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS # !D<14>.PIN & !AS & !AUTO_CONFIG_Z2_DONE<0> & !LDS & CP_BASEADR<6> & !A<5> & !A<4> & !A<1> & !RW & A<6> & A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS ;Imported pterms FB10_14 # D<14>.PIN & !AS & !AUTO_CONFIG_Z2_DONE<0> & !LDS & !CP_BASEADR<6> & !A<5> & !A<4> & !A<1> & !RW & A<6> & A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS; CP_BASEADR<6>.CLK = SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF; CP_BASEADR<6>.AP = !RESET; MACROCELL | 13 | 5 | CP_BASEADR<7> ATTRIBUTES | 4326304 | 0 OUTPUTMC | 3 | 13 | 5 | 4 | 3 | 13 | 4 INPUTS | 17 | D<15>.PIN | AS | AUTO_CONFIG_Z2_DONE<0> | UDS | CP_BASEADR<7> | A<5> | A<4> | A<1> | RW | A<6> | A<3> | A<2> | AUTOCONFIG_Z2_ACCESS | LDS | SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF | RESET | AUTO_CONFIG_Z2_DONE_CYCLE<0>.EXP INPUTMC | 5 | 7 | 15 | 13 | 5 | 4 | 6 | 2 | 8 | 13 | 4 INPUTP | 12 | 89 | 152 | 155 | 91 | 97 | 107 | 158 | 98 | 99 | 101 | 157 | 263 IMPORTS | 1 | 13 | 4 EQ | 15 | CP_BASEADR<7>.T = D<15>.PIN & !AS & !AUTO_CONFIG_Z2_DONE<0> & !UDS & !CP_BASEADR<7> & !A<5> & !A<4> & !A<1> & !RW & A<6> & A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS # !D<15>.PIN & !AS & !AUTO_CONFIG_Z2_DONE<0> & !UDS & CP_BASEADR<7> & !A<5> & !A<4> & !A<1> & !RW & A<6> & A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS # !D<15>.PIN & !AS & !AUTO_CONFIG_Z2_DONE<0> & !LDS & CP_BASEADR<7> & !A<5> & !A<4> & !A<1> & !RW & A<6> & A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS ;Imported pterms FB14_5 # D<15>.PIN & !AS & !AUTO_CONFIG_Z2_DONE<0> & !LDS & !CP_BASEADR<7> & !A<5> & !A<4> & !A<1> & !RW & A<6> & A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS; CP_BASEADR<7>.CLK = SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF; CP_BASEADR<7>.AP = !RESET; MACROCELL | 3 | 17 | IDE_BASEADR<0> ATTRIBUTES | 4326304 | 0 OUTPUTMC | 4 | 3 | 17 | 7 | 17 | 3 | 0 | 3 | 16 INPUTS | 20 | D<8>.PIN | AS | AUTO_CONFIG_Z2_DONE<0> | AUTO_CONFIG_Z2_DONE<1> | UDS | IDE_BASEADR<0> | A<5> | A<4> | A<1> | RW | A<6> | A<3> | A<2> | AUTOCONFIG_Z2_ACCESS | LDS | SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF | RESET | D<9>.PIN | IDE_BASEADR<1> | D_OUT<7>.EXP INPUTMC | 7 | 7 | 15 | 7 | 14 | 3 | 17 | 4 | 6 | 2 | 8 | 3 | 16 | 3 | 0 INPUTP | 13 | 32 | 152 | 155 | 91 | 97 | 107 | 158 | 98 | 99 | 101 | 157 | 263 | 73 EXPORTS | 1 | 3 | 16 IMPORTS | 1 | 3 | 0 EQ | 18 | IDE_BASEADR<0>.T = !D<8>.PIN & !AS & AUTO_CONFIG_Z2_DONE<0> & !AUTO_CONFIG_Z2_DONE<1> & !UDS & IDE_BASEADR<0> & !A<5> & !A<4> & !A<1> & !RW & A<6> & A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS # !D<8>.PIN & !AS & AUTO_CONFIG_Z2_DONE<0> & !AUTO_CONFIG_Z2_DONE<1> & !LDS & IDE_BASEADR<0> & !A<5> & !A<4> & !A<1> & !RW & A<6> & A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS ;Imported pterms FB4_1 # D<8>.PIN & !AS & AUTO_CONFIG_Z2_DONE<0> & !AUTO_CONFIG_Z2_DONE<1> & !UDS & !IDE_BASEADR<0> & !A<5> & !A<4> & !A<1> & !RW & A<6> & A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS # D<8>.PIN & !AS & AUTO_CONFIG_Z2_DONE<0> & !AUTO_CONFIG_Z2_DONE<1> & !LDS & !IDE_BASEADR<0> & !A<5> & !A<4> & !A<1> & !RW & A<6> & A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS; IDE_BASEADR<0>.CLK = SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF; IDE_BASEADR<0>.AP = !RESET; IDE_BASEADR<0>.EXP = D<9>.PIN & !AS & AUTO_CONFIG_Z2_DONE<0> & !AUTO_CONFIG_Z2_DONE<1> & !LDS & !IDE_BASEADR<1> & !A<5> & !A<4> & !A<1> & !RW & A<6> & A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS MACROCELL | 3 | 16 | IDE_BASEADR<1> ATTRIBUTES | 4326304 | 0 OUTPUTMC | 3 | 3 | 16 | 7 | 16 | 3 | 17 INPUTS | 18 | D<9>.PIN | AS | AUTO_CONFIG_Z2_DONE<0> | AUTO_CONFIG_Z2_DONE<1> | UDS | IDE_BASEADR<1> | A<5> | A<4> | A<1> | RW | A<6> | A<3> | A<2> | AUTOCONFIG_Z2_ACCESS | LDS | SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF | RESET | IDE_BASEADR<0>.EXP INPUTMC | 6 | 7 | 15 | 7 | 14 | 3 | 16 | 4 | 6 | 2 | 8 | 3 | 17 INPUTP | 12 | 73 | 152 | 155 | 91 | 97 | 107 | 158 | 98 | 99 | 101 | 157 | 263 IMPORTS | 1 | 3 | 17 EQ | 15 | IDE_BASEADR<1>.T = D<9>.PIN & !AS & AUTO_CONFIG_Z2_DONE<0> & !AUTO_CONFIG_Z2_DONE<1> & !UDS & !IDE_BASEADR<1> & !A<5> & !A<4> & !A<1> & !RW & A<6> & A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS # !D<9>.PIN & !AS & AUTO_CONFIG_Z2_DONE<0> & !AUTO_CONFIG_Z2_DONE<1> & !UDS & IDE_BASEADR<1> & !A<5> & !A<4> & !A<1> & !RW & A<6> & A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS # !D<9>.PIN & !AS & AUTO_CONFIG_Z2_DONE<0> & !AUTO_CONFIG_Z2_DONE<1> & !LDS & IDE_BASEADR<1> & !A<5> & !A<4> & !A<1> & !RW & A<6> & A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS ;Imported pterms FB4_18 # D<9>.PIN & !AS & AUTO_CONFIG_Z2_DONE<0> & !AUTO_CONFIG_Z2_DONE<1> & !LDS & !IDE_BASEADR<1> & !A<5> & !A<4> & !A<1> & !RW & A<6> & A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS; IDE_BASEADR<1>.CLK = SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF; IDE_BASEADR<1>.AP = !RESET; MACROCELL | 3 | 15 | IDE_BASEADR<2> ATTRIBUTES | 4326304 | 0 OUTPUTMC | 3 | 3 | 15 | 7 | 16 | 3 | 14 INPUTS | 18 | D<10>.PIN | AS | AUTO_CONFIG_Z2_DONE<0> | AUTO_CONFIG_Z2_DONE<1> | UDS | IDE_BASEADR<2> | A<5> | A<4> | A<1> | RW | A<6> | A<3> | A<2> | AUTOCONFIG_Z2_ACCESS | LDS | SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF | RESET | IDE_BASEADR<3>.EXP INPUTMC | 6 | 7 | 15 | 7 | 14 | 3 | 15 | 4 | 6 | 2 | 8 | 3 | 14 INPUTP | 12 | 74 | 152 | 155 | 91 | 97 | 107 | 158 | 98 | 99 | 101 | 157 | 263 IMPORTS | 1 | 3 | 14 EQ | 15 | IDE_BASEADR<2>.T = D<10>.PIN & !AS & AUTO_CONFIG_Z2_DONE<0> & !AUTO_CONFIG_Z2_DONE<1> & !UDS & !IDE_BASEADR<2> & !A<5> & !A<4> & !A<1> & !RW & A<6> & A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS # !D<10>.PIN & !AS & AUTO_CONFIG_Z2_DONE<0> & !AUTO_CONFIG_Z2_DONE<1> & !UDS & IDE_BASEADR<2> & !A<5> & !A<4> & !A<1> & !RW & A<6> & A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS # !D<10>.PIN & !AS & AUTO_CONFIG_Z2_DONE<0> & !AUTO_CONFIG_Z2_DONE<1> & !LDS & IDE_BASEADR<2> & !A<5> & !A<4> & !A<1> & !RW & A<6> & A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS ;Imported pterms FB4_15 # D<10>.PIN & !AS & AUTO_CONFIG_Z2_DONE<0> & !AUTO_CONFIG_Z2_DONE<1> & !LDS & !IDE_BASEADR<2> & !A<5> & !A<4> & !A<1> & !RW & A<6> & A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS; IDE_BASEADR<2>.CLK = SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF; IDE_BASEADR<2>.AP = !RESET; MACROCELL | 3 | 14 | IDE_BASEADR<3> ATTRIBUTES | 4326304 | 0 OUTPUTMC | 5 | 3 | 14 | 7 | 16 | 3 | 13 | 7 | 0 | 3 | 15 INPUTS | 20 | D<11>.PIN | AS | AUTO_CONFIG_Z2_DONE<0> | AUTO_CONFIG_Z2_DONE<1> | UDS | IDE_BASEADR<3> | A<5> | A<4> | A<1> | RW | A<6> | A<3> | A<2> | AUTOCONFIG_Z2_ACCESS | LDS | SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF | RESET | D<10>.PIN | IDE_BASEADR<2> | A_LAN_5_OBUF.EXP INPUTMC | 7 | 7 | 15 | 7 | 14 | 3 | 14 | 4 | 6 | 2 | 8 | 3 | 15 | 3 | 13 INPUTP | 13 | 77 | 152 | 155 | 91 | 97 | 107 | 158 | 98 | 99 | 101 | 157 | 263 | 74 EXPORTS | 1 | 3 | 15 IMPORTS | 1 | 3 | 13 EQ | 18 | IDE_BASEADR<3>.T = !D<11>.PIN & !AS & AUTO_CONFIG_Z2_DONE<0> & !AUTO_CONFIG_Z2_DONE<1> & !UDS & IDE_BASEADR<3> & !A<5> & !A<4> & !A<1> & !RW & A<6> & A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS # !D<11>.PIN & !AS & AUTO_CONFIG_Z2_DONE<0> & !AUTO_CONFIG_Z2_DONE<1> & !LDS & IDE_BASEADR<3> & !A<5> & !A<4> & !A<1> & !RW & A<6> & A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS ;Imported pterms FB4_14 # D<11>.PIN & !AS & AUTO_CONFIG_Z2_DONE<0> & !AUTO_CONFIG_Z2_DONE<1> & !UDS & !IDE_BASEADR<3> & !A<5> & !A<4> & !A<1> & !RW & A<6> & A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS # D<11>.PIN & !AS & AUTO_CONFIG_Z2_DONE<0> & !AUTO_CONFIG_Z2_DONE<1> & !LDS & !IDE_BASEADR<3> & !A<5> & !A<4> & !A<1> & !RW & A<6> & A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS; IDE_BASEADR<3>.CLK = SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF; IDE_BASEADR<3>.AP = !RESET; IDE_BASEADR<3>.EXP = D<10>.PIN & !AS & AUTO_CONFIG_Z2_DONE<0> & !AUTO_CONFIG_Z2_DONE<1> & !LDS & !IDE_BASEADR<2> & !A<5> & !A<4> & !A<1> & !RW & A<6> & A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS MACROCELL | 9 | 12 | IDE_BASEADR<4> ATTRIBUTES | 4326304 | 0 OUTPUTMC | 3 | 9 | 12 | 7 | 0 | 9 | 11 INPUTS | 18 | D<12>.PIN | AS | AUTO_CONFIG_Z2_DONE<0> | AUTO_CONFIG_Z2_DONE<1> | UDS | IDE_BASEADR<4> | A<5> | A<4> | A<1> | RW | A<6> | A<3> | A<2> | AUTOCONFIG_Z2_ACCESS | LDS | SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF | RESET | DQ_6_IOBUFE.EXP INPUTMC | 6 | 7 | 15 | 7 | 14 | 9 | 12 | 4 | 6 | 2 | 8 | 9 | 11 INPUTP | 12 | 78 | 152 | 155 | 91 | 97 | 107 | 158 | 98 | 99 | 101 | 157 | 263 IMPORTS | 1 | 9 | 11 EQ | 15 | IDE_BASEADR<4>.T = D<12>.PIN & !AS & AUTO_CONFIG_Z2_DONE<0> & !AUTO_CONFIG_Z2_DONE<1> & !UDS & !IDE_BASEADR<4> & !A<5> & !A<4> & !A<1> & !RW & A<6> & A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS # !D<12>.PIN & !AS & AUTO_CONFIG_Z2_DONE<0> & !AUTO_CONFIG_Z2_DONE<1> & !UDS & IDE_BASEADR<4> & !A<5> & !A<4> & !A<1> & !RW & A<6> & A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS # !D<12>.PIN & !AS & AUTO_CONFIG_Z2_DONE<0> & !AUTO_CONFIG_Z2_DONE<1> & !LDS & IDE_BASEADR<4> & !A<5> & !A<4> & !A<1> & !RW & A<6> & A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS ;Imported pterms FB10_12 # D<12>.PIN & !AS & AUTO_CONFIG_Z2_DONE<0> & !AUTO_CONFIG_Z2_DONE<1> & !LDS & !IDE_BASEADR<4> & !A<5> & !A<4> & !A<1> & !RW & A<6> & A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS; IDE_BASEADR<4>.CLK = SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF; IDE_BASEADR<4>.AP = !RESET; MACROCELL | 9 | 8 | IDE_BASEADR<5> ATTRIBUTES | 4326304 | 0 OUTPUTMC | 3 | 9 | 8 | 7 | 0 | 9 | 7 INPUTS | 18 | D<13>.PIN | AS | AUTO_CONFIG_Z2_DONE<0> | AUTO_CONFIG_Z2_DONE<1> | UDS | IDE_BASEADR<5> | A<5> | A<4> | A<1> | RW | A<6> | A<3> | A<2> | AUTOCONFIG_Z2_ACCESS | LDS | SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF | RESET | DQ_5_IOBUFE.EXP INPUTMC | 6 | 7 | 15 | 7 | 14 | 9 | 8 | 4 | 6 | 2 | 8 | 9 | 7 INPUTP | 12 | 80 | 152 | 155 | 91 | 97 | 107 | 158 | 98 | 99 | 101 | 157 | 263 IMPORTS | 1 | 9 | 7 EQ | 15 | IDE_BASEADR<5>.T = D<13>.PIN & !AS & AUTO_CONFIG_Z2_DONE<0> & !AUTO_CONFIG_Z2_DONE<1> & !UDS & !IDE_BASEADR<5> & !A<5> & !A<4> & !A<1> & !RW & A<6> & A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS # !D<13>.PIN & !AS & AUTO_CONFIG_Z2_DONE<0> & !AUTO_CONFIG_Z2_DONE<1> & !UDS & IDE_BASEADR<5> & !A<5> & !A<4> & !A<1> & !RW & A<6> & A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS # !D<13>.PIN & !AS & AUTO_CONFIG_Z2_DONE<0> & !AUTO_CONFIG_Z2_DONE<1> & !LDS & IDE_BASEADR<5> & !A<5> & !A<4> & !A<1> & !RW & A<6> & A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS ;Imported pterms FB10_8 # D<13>.PIN & !AS & AUTO_CONFIG_Z2_DONE<0> & !AUTO_CONFIG_Z2_DONE<1> & !LDS & !IDE_BASEADR<5> & !A<5> & !A<4> & !A<1> & !RW & A<6> & A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS; IDE_BASEADR<5>.CLK = SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF; IDE_BASEADR<5>.AP = !RESET; MACROCELL | 9 | 6 | IDE_BASEADR<6> ATTRIBUTES | 4326304 | 0 OUTPUTMC | 3 | 9 | 6 | 7 | 1 | 9 | 5 INPUTS | 18 | D<14>.PIN | AS | AUTO_CONFIG_Z2_DONE<0> | AUTO_CONFIG_Z2_DONE<1> | UDS | IDE_BASEADR<6> | A<5> | A<4> | A<1> | RW | A<6> | A<3> | A<2> | AUTOCONFIG_Z2_ACCESS | LDS | SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF | RESET | DQ_2_IOBUFE.EXP INPUTMC | 6 | 7 | 15 | 7 | 14 | 9 | 6 | 4 | 6 | 2 | 8 | 9 | 5 INPUTP | 12 | 81 | 152 | 155 | 91 | 97 | 107 | 158 | 98 | 99 | 101 | 157 | 263 IMPORTS | 1 | 9 | 5 EQ | 15 | IDE_BASEADR<6>.T = D<14>.PIN & !AS & AUTO_CONFIG_Z2_DONE<0> & !AUTO_CONFIG_Z2_DONE<1> & !UDS & !IDE_BASEADR<6> & !A<5> & !A<4> & !A<1> & !RW & A<6> & A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS # !D<14>.PIN & !AS & AUTO_CONFIG_Z2_DONE<0> & !AUTO_CONFIG_Z2_DONE<1> & !UDS & IDE_BASEADR<6> & !A<5> & !A<4> & !A<1> & !RW & A<6> & A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS # !D<14>.PIN & !AS & AUTO_CONFIG_Z2_DONE<0> & !AUTO_CONFIG_Z2_DONE<1> & !LDS & IDE_BASEADR<6> & !A<5> & !A<4> & !A<1> & !RW & A<6> & A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS ;Imported pterms FB10_6 # D<14>.PIN & !AS & AUTO_CONFIG_Z2_DONE<0> & !AUTO_CONFIG_Z2_DONE<1> & !LDS & !IDE_BASEADR<6> & !A<5> & !A<4> & !A<1> & !RW & A<6> & A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS; IDE_BASEADR<6>.CLK = SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF; IDE_BASEADR<6>.AP = !RESET; MACROCELL | 9 | 3 | IDE_BASEADR<7> ATTRIBUTES | 4326304 | 0 OUTPUTMC | 4 | 9 | 3 | 7 | 15 | 7 | 1 | 9 | 2 INPUTS | 18 | D<15>.PIN | AS | AUTO_CONFIG_Z2_DONE<0> | AUTO_CONFIG_Z2_DONE<1> | UDS | IDE_BASEADR<7> | A<5> | A<4> | A<1> | RW | A<6> | A<3> | A<2> | AUTOCONFIG_Z2_ACCESS | LDS | SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF | RESET | DQ_0_IOBUFE.EXP INPUTMC | 6 | 7 | 15 | 7 | 14 | 9 | 3 | 4 | 6 | 2 | 8 | 9 | 2 INPUTP | 12 | 89 | 152 | 155 | 91 | 97 | 107 | 158 | 98 | 99 | 101 | 157 | 263 IMPORTS | 1 | 9 | 2 EQ | 15 | IDE_BASEADR<7>.T = D<15>.PIN & !AS & AUTO_CONFIG_Z2_DONE<0> & !AUTO_CONFIG_Z2_DONE<1> & !UDS & !IDE_BASEADR<7> & !A<5> & !A<4> & !A<1> & !RW & A<6> & A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS # !D<15>.PIN & !AS & AUTO_CONFIG_Z2_DONE<0> & !AUTO_CONFIG_Z2_DONE<1> & !UDS & IDE_BASEADR<7> & !A<5> & !A<4> & !A<1> & !RW & A<6> & A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS # !D<15>.PIN & !AS & AUTO_CONFIG_Z2_DONE<0> & !AUTO_CONFIG_Z2_DONE<1> & !LDS & IDE_BASEADR<7> & !A<5> & !A<4> & !A<1> & !RW & A<6> & A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS ;Imported pterms FB10_3 # D<15>.PIN & !AS & AUTO_CONFIG_Z2_DONE<0> & !AUTO_CONFIG_Z2_DONE<1> & !LDS & !IDE_BASEADR<7> & !A<5> & !A<4> & !A<1> & !RW & A<6> & A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS; IDE_BASEADR<7>.CLK = SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF; IDE_BASEADR<7>.AP = !RESET; MACROCELL | 1 | 17 | LAN_BASEADR<0> ATTRIBUTES | 8553408 | 0 OUTPUTMC | 2 | 2 | 1 | 1 | 16 INPUTS | 16 | D<0>.PIN | RESET | UDS | FCS | RW | Z3_ADR<2> | Z3_ADR_1 | Z3_ADR_0 | Z3_ADR<6> | AUTOCONFIG_Z3_ACCESS | Z3_ADR<3> | Z3_ADR<4> | Z3_ADR<5> | LDS | DS1 | DS0 INPUTMC | 8 | 9 | 0 | 11 | 0 | 11 | 17 | 2 | 16 | 7 | 13 | 11 | 10 | 11 | 12 | 11 | 13 INPUTP | 8 | 4 | 263 | 155 | 147 | 158 | 157 | 148 | 170 EXPORTS | 1 | 1 | 16 EQ | 7 | LAN_BASEADR<0>.D = D<0>.PIN; LAN_BASEADR<0>.CLK = CLK_EXT; // GCK LAN_BASEADR<0>.AP = !RESET; LAN_BASEADR<0>.CE = !UDS & !FCS & !RW & !Z3_ADR<2> & !Z3_ADR_1 & Z3_ADR_0 & !Z3_ADR<6> & AUTOCONFIG_Z3_ACCESS & !Z3_ADR<3> & Z3_ADR<4> & !Z3_ADR<5>; LAN_BASEADR<0>.EXP = UDS & LDS & DS1 & DS0 GLOBALS | 1 | 2 | CLK_EXT MACROCELL | 1 | 15 | LAN_BASEADR<10> ATTRIBUTES | 8553408 | 0 OUTPUTMC | 3 | 8 | 2 | 8 | 9 | 1 | 16 INPUTS | 15 | D<10>.PIN | RESET | UDS | FCS | RW | Z3_ADR<2> | Z3_ADR_1 | Z3_ADR_0 | Z3_ADR<6> | AUTOCONFIG_Z3_ACCESS | Z3_ADR<3> | Z3_ADR<4> | Z3_ADR<5> | Z3_DATA<24> | LAN_ACCESS INPUTMC | 10 | 9 | 0 | 11 | 0 | 11 | 17 | 2 | 16 | 7 | 13 | 11 | 10 | 11 | 12 | 11 | 13 | 15 | 8 | 8 | 8 INPUTP | 5 | 74 | 263 | 155 | 147 | 158 EXPORTS | 1 | 1 | 16 EQ | 7 | LAN_BASEADR<10>.D = D<10>.PIN; LAN_BASEADR<10>.CLK = CLK_EXT; // GCK LAN_BASEADR<10>.AP = !RESET; LAN_BASEADR<10>.CE = !UDS & !FCS & !RW & !Z3_ADR<2> & !Z3_ADR_1 & Z3_ADR_0 & !Z3_ADR<6> & AUTOCONFIG_Z3_ACCESS & !Z3_ADR<3> & Z3_ADR<4> & !Z3_ADR<5>; LAN_BASEADR<10>.EXP = Z3_DATA<24> & LAN_ACCESS GLOBALS | 1 | 2 | CLK_EXT MACROCELL | 1 | 12 | LAN_BASEADR<11> ATTRIBUTES | 8553408 | 0 OUTPUTMC | 3 | 8 | 0 | 8 | 7 | 8 | 2 INPUTS | 13 | D<11>.PIN | RESET | UDS | FCS | RW | Z3_ADR<2> | Z3_ADR_1 | Z3_ADR_0 | Z3_ADR<6> | AUTOCONFIG_Z3_ACCESS | Z3_ADR<3> | Z3_ADR<4> | Z3_ADR<5> INPUTMC | 8 | 9 | 0 | 11 | 0 | 11 | 17 | 2 | 16 | 7 | 13 | 11 | 10 | 11 | 12 | 11 | 13 INPUTP | 5 | 77 | 263 | 155 | 147 | 158 EQ | 6 | LAN_BASEADR<11>.D = D<11>.PIN; LAN_BASEADR<11>.CLK = CLK_EXT; // GCK LAN_BASEADR<11>.AP = !RESET; LAN_BASEADR<11>.CE = !UDS & !FCS & !RW & !Z3_ADR<2> & !Z3_ADR_1 & Z3_ADR_0 & !Z3_ADR<6> & AUTOCONFIG_Z3_ACCESS & !Z3_ADR<3> & Z3_ADR<4> & !Z3_ADR<5>; GLOBALS | 1 | 2 | CLK_EXT MACROCELL | 1 | 10 | LAN_BASEADR<12> ATTRIBUTES | 8553408 | 0 OUTPUTMC | 2 | 8 | 9 | 8 | 17 INPUTS | 13 | D<12>.PIN | RESET | UDS | FCS | RW | Z3_ADR<2> | Z3_ADR_1 | Z3_ADR_0 | Z3_ADR<6> | AUTOCONFIG_Z3_ACCESS | Z3_ADR<3> | Z3_ADR<4> | Z3_ADR<5> INPUTMC | 8 | 9 | 0 | 11 | 0 | 11 | 17 | 2 | 16 | 7 | 13 | 11 | 10 | 11 | 12 | 11 | 13 INPUTP | 5 | 78 | 263 | 155 | 147 | 158 EQ | 6 | LAN_BASEADR<12>.D = D<12>.PIN; LAN_BASEADR<12>.CLK = CLK_EXT; // GCK LAN_BASEADR<12>.AP = !RESET; LAN_BASEADR<12>.CE = !UDS & !FCS & !RW & !Z3_ADR<2> & !Z3_ADR_1 & Z3_ADR_0 & !Z3_ADR<6> & AUTOCONFIG_Z3_ACCESS & !Z3_ADR<3> & Z3_ADR<4> & !Z3_ADR<5>; GLOBALS | 1 | 2 | CLK_EXT MACROCELL | 1 | 8 | LAN_BASEADR<13> ATTRIBUTES | 8553408 | 0 OUTPUTMC | 3 | 8 | 6 | 8 | 3 | 8 | 17 INPUTS | 13 | D<13>.PIN | RESET | UDS | FCS | RW | Z3_ADR<2> | Z3_ADR_1 | Z3_ADR_0 | Z3_ADR<6> | AUTOCONFIG_Z3_ACCESS | Z3_ADR<3> | Z3_ADR<4> | Z3_ADR<5> INPUTMC | 8 | 9 | 0 | 11 | 0 | 11 | 17 | 2 | 16 | 7 | 13 | 11 | 10 | 11 | 12 | 11 | 13 INPUTP | 5 | 80 | 263 | 155 | 147 | 158 EQ | 6 | LAN_BASEADR<13>.D = D<13>.PIN; LAN_BASEADR<13>.CLK = CLK_EXT; // GCK LAN_BASEADR<13>.AP = !RESET; LAN_BASEADR<13>.CE = !UDS & !FCS & !RW & !Z3_ADR<2> & !Z3_ADR_1 & Z3_ADR_0 & !Z3_ADR<6> & AUTOCONFIG_Z3_ACCESS & !Z3_ADR<3> & Z3_ADR<4> & !Z3_ADR<5>; GLOBALS | 1 | 2 | CLK_EXT MACROCELL | 1 | 6 | LAN_BASEADR<14> ATTRIBUTES | 8553408 | 0 OUTPUTMC | 1 | 2 | 17 INPUTS | 13 | D<14>.PIN | RESET | UDS | FCS | RW | Z3_ADR<2> | Z3_ADR_1 | Z3_ADR_0 | Z3_ADR<6> | AUTOCONFIG_Z3_ACCESS | Z3_ADR<3> | Z3_ADR<4> | Z3_ADR<5> INPUTMC | 8 | 9 | 0 | 11 | 0 | 11 | 17 | 2 | 16 | 7 | 13 | 11 | 10 | 11 | 12 | 11 | 13 INPUTP | 5 | 81 | 263 | 155 | 147 | 158 EQ | 6 | LAN_BASEADR<14>.D = D<14>.PIN; LAN_BASEADR<14>.CLK = CLK_EXT; // GCK LAN_BASEADR<14>.AP = !RESET; LAN_BASEADR<14>.CE = !UDS & !FCS & !RW & !Z3_ADR<2> & !Z3_ADR_1 & Z3_ADR_0 & !Z3_ADR<6> & AUTOCONFIG_Z3_ACCESS & !Z3_ADR<3> & Z3_ADR<4> & !Z3_ADR<5>; GLOBALS | 1 | 2 | CLK_EXT MACROCELL | 1 | 3 | LAN_BASEADR<15> ATTRIBUTES | 8553408 | 0 OUTPUTMC | 3 | 8 | 7 | 8 | 2 | 8 | 9 INPUTS | 13 | D<15>.PIN | RESET | UDS | FCS | RW | Z3_ADR<2> | Z3_ADR_1 | Z3_ADR_0 | Z3_ADR<6> | AUTOCONFIG_Z3_ACCESS | Z3_ADR<3> | Z3_ADR<4> | Z3_ADR<5> INPUTMC | 8 | 9 | 0 | 11 | 0 | 11 | 17 | 2 | 16 | 7 | 13 | 11 | 10 | 11 | 12 | 11 | 13 INPUTP | 5 | 89 | 263 | 155 | 147 | 158 EQ | 6 | LAN_BASEADR<15>.D = D<15>.PIN; LAN_BASEADR<15>.CLK = CLK_EXT; // GCK LAN_BASEADR<15>.AP = !RESET; LAN_BASEADR<15>.CE = !UDS & !FCS & !RW & !Z3_ADR<2> & !Z3_ADR_1 & Z3_ADR_0 & !Z3_ADR<6> & AUTOCONFIG_Z3_ACCESS & !Z3_ADR<3> & Z3_ADR<4> & !Z3_ADR<5>; GLOBALS | 1 | 2 | CLK_EXT MACROCELL | 1 | 0 | LAN_BASEADR<1> ATTRIBUTES | 8553408 | 0 OUTPUTMC | 1 | 2 | 0 INPUTS | 13 | D<1>.PIN | RESET | UDS | FCS | RW | Z3_ADR<2> | Z3_ADR_1 | Z3_ADR_0 | Z3_ADR<6> | AUTOCONFIG_Z3_ACCESS | Z3_ADR<3> | Z3_ADR<4> | Z3_ADR<5> INPUTMC | 8 | 9 | 0 | 11 | 0 | 11 | 17 | 2 | 16 | 7 | 13 | 11 | 10 | 11 | 12 | 11 | 13 INPUTP | 5 | 30 | 263 | 155 | 147 | 158 EQ | 6 | LAN_BASEADR<1>.D = D<1>.PIN; LAN_BASEADR<1>.CLK = CLK_EXT; // GCK LAN_BASEADR<1>.AP = !RESET; LAN_BASEADR<1>.CE = !UDS & !FCS & !RW & !Z3_ADR<2> & !Z3_ADR_1 & Z3_ADR_0 & !Z3_ADR<6> & AUTOCONFIG_Z3_ACCESS & !Z3_ADR<3> & Z3_ADR<4> & !Z3_ADR<5>; GLOBALS | 1 | 2 | CLK_EXT MACROCELL | 6 | 7 | LAN_BASEADR<2> ATTRIBUTES | 8553408 | 0 OUTPUTMC | 1 | 2 | 17 INPUTS | 13 | D<2>.PIN | RESET | UDS | FCS | RW | Z3_ADR<2> | Z3_ADR_1 | Z3_ADR_0 | Z3_ADR<6> | AUTOCONFIG_Z3_ACCESS | Z3_ADR<3> | Z3_ADR<4> | Z3_ADR<5> INPUTMC | 8 | 9 | 0 | 11 | 0 | 11 | 17 | 2 | 16 | 7 | 13 | 11 | 10 | 11 | 12 | 11 | 13 INPUTP | 5 | 71 | 263 | 155 | 147 | 158 EQ | 6 | LAN_BASEADR<2>.D = D<2>.PIN; LAN_BASEADR<2>.CLK = CLK_EXT; // GCK LAN_BASEADR<2>.AP = !RESET; LAN_BASEADR<2>.CE = !UDS & !FCS & !RW & !Z3_ADR<2> & !Z3_ADR_1 & Z3_ADR_0 & !Z3_ADR<6> & AUTOCONFIG_Z3_ACCESS & !Z3_ADR<3> & Z3_ADR<4> & !Z3_ADR<5>; GLOBALS | 1 | 2 | CLK_EXT MACROCELL | 6 | 8 | LAN_BASEADR<3> ATTRIBUTES | 8553408 | 0 OUTPUTMC | 2 | 2 | 1 | 2 | 16 INPUTS | 13 | D<3>.PIN | RESET | UDS | FCS | RW | Z3_ADR<2> | Z3_ADR_1 | Z3_ADR_0 | Z3_ADR<6> | AUTOCONFIG_Z3_ACCESS | Z3_ADR<3> | Z3_ADR<4> | Z3_ADR<5> INPUTMC | 8 | 9 | 0 | 11 | 0 | 11 | 17 | 2 | 16 | 7 | 13 | 11 | 10 | 11 | 12 | 11 | 13 INPUTP | 5 | 28 | 263 | 155 | 147 | 158 EQ | 6 | LAN_BASEADR<3>.D = D<3>.PIN; LAN_BASEADR<3>.CLK = CLK_EXT; // GCK LAN_BASEADR<3>.AP = !RESET; LAN_BASEADR<3>.CE = !UDS & !FCS & !RW & !Z3_ADR<2> & !Z3_ADR_1 & Z3_ADR_0 & !Z3_ADR<6> & AUTOCONFIG_Z3_ACCESS & !Z3_ADR<3> & Z3_ADR<4> & !Z3_ADR<5>; GLOBALS | 1 | 2 | CLK_EXT MACROCELL | 6 | 9 | LAN_BASEADR<4> ATTRIBUTES | 8553408 | 0 OUTPUTMC | 1 | 2 | 1 INPUTS | 13 | D<4>.PIN | RESET | UDS | FCS | RW | Z3_ADR<2> | Z3_ADR_1 | Z3_ADR_0 | Z3_ADR<6> | AUTOCONFIG_Z3_ACCESS | Z3_ADR<3> | Z3_ADR<4> | Z3_ADR<5> INPUTMC | 8 | 9 | 0 | 11 | 0 | 11 | 17 | 2 | 16 | 7 | 13 | 11 | 10 | 11 | 12 | 11 | 13 INPUTP | 5 | 38 | 263 | 155 | 147 | 158 EQ | 6 | LAN_BASEADR<4>.D = D<4>.PIN; LAN_BASEADR<4>.CLK = CLK_EXT; // GCK LAN_BASEADR<4>.AP = !RESET; LAN_BASEADR<4>.CE = !UDS & !FCS & !RW & !Z3_ADR<2> & !Z3_ADR_1 & Z3_ADR_0 & !Z3_ADR<6> & AUTOCONFIG_Z3_ACCESS & !Z3_ADR<3> & Z3_ADR<4> & !Z3_ADR<5>; GLOBALS | 1 | 2 | CLK_EXT MACROCELL | 6 | 10 | LAN_BASEADR<5> ATTRIBUTES | 8553408 | 0 OUTPUTMC | 2 | 2 | 0 | 6 | 11 INPUTS | 16 | D<5>.PIN | RESET | UDS | FCS | RW | Z3_ADR<2> | Z3_ADR_1 | Z3_ADR_0 | Z3_ADR<6> | AUTOCONFIG_Z3_ACCESS | Z3_ADR<3> | Z3_ADR<4> | Z3_ADR<5> | Z3_DATA<31> | LAN_ACCESS | DS0 INPUTMC | 10 | 9 | 0 | 11 | 0 | 11 | 17 | 2 | 16 | 7 | 13 | 11 | 10 | 11 | 12 | 11 | 13 | 12 | 2 | 8 | 8 INPUTP | 6 | 37 | 263 | 155 | 147 | 158 | 170 EXPORTS | 1 | 6 | 11 EQ | 8 | LAN_BASEADR<5>.D = D<5>.PIN; LAN_BASEADR<5>.CLK = CLK_EXT; // GCK LAN_BASEADR<5>.AP = !RESET; LAN_BASEADR<5>.CE = !UDS & !FCS & !RW & !Z3_ADR<2> & !Z3_ADR_1 & Z3_ADR_0 & !Z3_ADR<6> & AUTOCONFIG_Z3_ACCESS & !Z3_ADR<3> & Z3_ADR<4> & !Z3_ADR<5>; LAN_BASEADR<5>.EXP = !UDS & !FCS & Z3_DATA<31> & RW & LAN_ACCESS # !DS0 & !FCS & Z3_DATA<31> & RW & LAN_ACCESS GLOBALS | 1 | 2 | CLK_EXT MACROCELL | 6 | 13 | LAN_BASEADR<6> ATTRIBUTES | 8553408 | 0 OUTPUTMC | 3 | 8 | 3 | 8 | 10 | 6 | 12 INPUTS | 16 | D<6>.PIN | RESET | UDS | FCS | RW | Z3_ADR<2> | Z3_ADR_1 | Z3_ADR_0 | Z3_ADR<6> | AUTOCONFIG_Z3_ACCESS | Z3_ADR<3> | Z3_ADR<4> | Z3_ADR<5> | LDS | LAN_ACCESS | D_OUT<7> INPUTMC | 10 | 9 | 0 | 11 | 0 | 11 | 17 | 2 | 16 | 7 | 13 | 11 | 10 | 11 | 12 | 11 | 13 | 8 | 8 | 3 | 0 INPUTP | 6 | 26 | 263 | 155 | 147 | 158 | 157 EXPORTS | 1 | 6 | 12 EQ | 8 | LAN_BASEADR<6>.D = D<6>.PIN; LAN_BASEADR<6>.CLK = CLK_EXT; // GCK LAN_BASEADR<6>.AP = !RESET; LAN_BASEADR<6>.CE = !UDS & !FCS & !RW & !Z3_ADR<2> & !Z3_ADR_1 & Z3_ADR_0 & !Z3_ADR<6> & AUTOCONFIG_Z3_ACCESS & !Z3_ADR<3> & Z3_ADR<4> & !Z3_ADR<5>; LAN_BASEADR<6>.EXP = !LDS & !FCS & RW & !LAN_ACCESS & AUTOCONFIG_Z3_ACCESS & D_OUT<7> GLOBALS | 1 | 2 | CLK_EXT MACROCELL | 6 | 14 | LAN_BASEADR<7> ATTRIBUTES | 8553408 | 0 OUTPUTMC | 2 | 2 | 0 | 2 | 17 INPUTS | 13 | D<7>.PIN | RESET | UDS | FCS | RW | Z3_ADR<2> | Z3_ADR_1 | Z3_ADR_0 | Z3_ADR<6> | AUTOCONFIG_Z3_ACCESS | Z3_ADR<3> | Z3_ADR<4> | Z3_ADR<5> INPUTMC | 8 | 9 | 0 | 11 | 0 | 11 | 17 | 2 | 16 | 7 | 13 | 11 | 10 | 11 | 12 | 11 | 13 INPUTP | 5 | 29 | 263 | 155 | 147 | 158 EQ | 6 | LAN_BASEADR<7>.D = D<7>.PIN; LAN_BASEADR<7>.CLK = CLK_EXT; // GCK LAN_BASEADR<7>.AP = !RESET; LAN_BASEADR<7>.CE = !UDS & !FCS & !RW & !Z3_ADR<2> & !Z3_ADR_1 & Z3_ADR_0 & !Z3_ADR<6> & AUTOCONFIG_Z3_ACCESS & !Z3_ADR<3> & Z3_ADR<4> & !Z3_ADR<5>; GLOBALS | 1 | 2 | CLK_EXT MACROCELL | 6 | 16 | LAN_BASEADR<8> ATTRIBUTES | 8553408 | 0 OUTPUTMC | 2 | 8 | 6 | 8 | 17 INPUTS | 13 | D<8>.PIN | RESET | UDS | FCS | RW | Z3_ADR<2> | Z3_ADR_1 | Z3_ADR_0 | Z3_ADR<6> | AUTOCONFIG_Z3_ACCESS | Z3_ADR<3> | Z3_ADR<4> | Z3_ADR<5> INPUTMC | 8 | 9 | 0 | 11 | 0 | 11 | 17 | 2 | 16 | 7 | 13 | 11 | 10 | 11 | 12 | 11 | 13 INPUTP | 5 | 32 | 263 | 155 | 147 | 158 EQ | 6 | LAN_BASEADR<8>.D = D<8>.PIN; LAN_BASEADR<8>.CLK = CLK_EXT; // GCK LAN_BASEADR<8>.AP = !RESET; LAN_BASEADR<8>.CE = !UDS & !FCS & !RW & !Z3_ADR<2> & !Z3_ADR_1 & Z3_ADR_0 & !Z3_ADR<6> & AUTOCONFIG_Z3_ACCESS & !Z3_ADR<3> & Z3_ADR<4> & !Z3_ADR<5>; GLOBALS | 1 | 2 | CLK_EXT MACROCELL | 6 | 17 | LAN_BASEADR<9> ATTRIBUTES | 8553408 | 0 OUTPUTMC | 2 | 8 | 0 | 8 | 7 INPUTS | 13 | D<9>.PIN | RESET | UDS | FCS | RW | Z3_ADR<2> | Z3_ADR_1 | Z3_ADR_0 | Z3_ADR<6> | AUTOCONFIG_Z3_ACCESS | Z3_ADR<3> | Z3_ADR<4> | Z3_ADR<5> INPUTMC | 8 | 9 | 0 | 11 | 0 | 11 | 17 | 2 | 16 | 7 | 13 | 11 | 10 | 11 | 12 | 11 | 13 INPUTP | 5 | 73 | 263 | 155 | 147 | 158 EQ | 6 | LAN_BASEADR<9>.D = D<9>.PIN; LAN_BASEADR<9>.CLK = CLK_EXT; // GCK LAN_BASEADR<9>.AP = !RESET; LAN_BASEADR<9>.CE = !UDS & !FCS & !RW & !Z3_ADR<2> & !Z3_ADR_1 & Z3_ADR_0 & !Z3_ADR<6> & AUTOCONFIG_Z3_ACCESS & !Z3_ADR<3> & Z3_ADR<4> & !Z3_ADR<5>; GLOBALS | 1 | 2 | CLK_EXT MACROCELL | 6 | 15 | LAN_INT_ENABLE ATTRIBUTES | 4358928 | 0 OUTPUTMC | 2 | 6 | 15 | 2 | 10 INPUTS | 10 | D<15>.PIN | UDS | FCS | LAN_INT_ENABLE | RW | LAN_ACCESS | Z3_ADR<13> | LDS | A<23>.PIN | RESET INPUTMC | 3 | 6 | 15 | 8 | 8 | 7 | 12 INPUTP | 7 | 89 | 155 | 147 | 158 | 157 | 161 | 263 EQ | 10 | LAN_INT_ENABLE.T = D<15>.PIN & !UDS & !FCS & !LAN_INT_ENABLE & !RW & LAN_ACCESS & Z3_ADR<13> # !D<15>.PIN & !UDS & !FCS & LAN_INT_ENABLE & !RW & LAN_ACCESS & Z3_ADR<13> # UDS & !LDS & !FCS & LAN_INT_ENABLE & !A<23>.PIN & !RW & LAN_ACCESS & Z3_ADR<13> # UDS & !LDS & !FCS & !LAN_INT_ENABLE & A<23>.PIN & !RW & LAN_ACCESS & Z3_ADR<13>; LAN_INT_ENABLE.CLK = CLK_EXT; // GCK LAN_INT_ENABLE.AR = !RESET; GLOBALS | 1 | 2 | CLK_EXT MACROCELL | 5 | 12 | LAN_IRQ_OUT ATTRIBUTES | 8553344 | 0 OUTPUTMC | 2 | 5 | 12 | 2 | 10 INPUTS | 4 | LAN_IRQ_OUT | LAN_IRQ_D0 | LAN_INT | RESET INPUTMC | 2 | 5 | 12 | 5 | 3 INPUTP | 2 | 201 | 263 EQ | 4 | LAN_IRQ_OUT.D = LAN_INT # LAN_IRQ_OUT & !LAN_IRQ_D0; LAN_IRQ_OUT.CLK = CLK_EXT; // GCK LAN_IRQ_OUT.AP = !RESET; GLOBALS | 1 | 2 | CLK_EXT MACROCELL | 15 | 13 | Z3_DATA<16> ATTRIBUTES | 8553408 | 0 OUTPUTMC | 2 | 3 | 1 | 15 | 14 INPUTS | 11 | DQ_SWAP | DQ<0>.PIN | DQ<8>.PIN | LAN_SM_RST | LAN_SM_FSM_FFd4 | LAN_SM_FSM_FFd2 | LAN_SM_FSM_FFd1 | UDS | LDS | LAN_SM_FSM_FFd3 | A<10>.PIN INPUTMC | 6 | 8 | 1 | 6 | 0 | 14 | 3 | 0 | 1 | 12 | 4 | 0 | 10 INPUTP | 5 | 217 | 231 | 155 | 157 | 112 EXPORTS | 1 | 15 | 14 EQ | 8 | Z3_DATA<16>.D = DQ_SWAP & DQ<8>.PIN # !DQ_SWAP & DQ<0>.PIN; Z3_DATA<16>.CLK = CLK_EXT; // GCK Z3_DATA<16>.AP = LAN_SM_RST; Z3_DATA<16>.CE = !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 & LAN_SM_FSM_FFd1; Z3_DATA<16>.EXP = UDS & LDS & DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 & A<10>.PIN GLOBALS | 1 | 2 | CLK_EXT MACROCELL | 15 | 12 | Z3_DATA<17> ATTRIBUTES | 8553408 | 0 OUTPUTMC | 1 | 1 | 14 INPUTS | 7 | DQ_SWAP | DQ<1>.PIN | DQ<9>.PIN | LAN_SM_RST | LAN_SM_FSM_FFd4 | LAN_SM_FSM_FFd2 | LAN_SM_FSM_FFd1 INPUTMC | 5 | 8 | 1 | 6 | 0 | 14 | 3 | 0 | 1 | 12 | 4 INPUTP | 2 | 216 | 209 EQ | 6 | Z3_DATA<17>.D = DQ_SWAP & DQ<9>.PIN # !DQ_SWAP & DQ<1>.PIN; Z3_DATA<17>.CLK = CLK_EXT; // GCK Z3_DATA<17>.AP = LAN_SM_RST; Z3_DATA<17>.CE = !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 & LAN_SM_FSM_FFd1; GLOBALS | 1 | 2 | CLK_EXT MACROCELL | 15 | 11 | Z3_DATA<18> ATTRIBUTES | 8553408 | 0 OUTPUTMC | 1 | 4 | 9 INPUTS | 7 | DQ_SWAP | DQ<10>.PIN | DQ<2>.PIN | LAN_SM_RST | LAN_SM_FSM_FFd4 | LAN_SM_FSM_FFd2 | LAN_SM_FSM_FFd1 INPUTMC | 5 | 8 | 1 | 6 | 0 | 14 | 3 | 0 | 1 | 12 | 4 INPUTP | 2 | 234 | 220 EQ | 6 | Z3_DATA<18>.D = DQ_SWAP & DQ<10>.PIN # !DQ_SWAP & DQ<2>.PIN; Z3_DATA<18>.CLK = CLK_EXT; // GCK Z3_DATA<18>.AP = LAN_SM_RST; Z3_DATA<18>.CE = !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 & LAN_SM_FSM_FFd1; GLOBALS | 1 | 2 | CLK_EXT MACROCELL | 10 | 12 | Z3_DATA<19> ATTRIBUTES | 8553408 | 0 OUTPUTMC | 1 | 1 | 11 INPUTS | 7 | DQ_SWAP | DQ<11>.PIN | DQ<3>.PIN | LAN_SM_RST | LAN_SM_FSM_FFd4 | LAN_SM_FSM_FFd2 | LAN_SM_FSM_FFd1 INPUTMC | 5 | 8 | 1 | 6 | 0 | 14 | 3 | 0 | 1 | 12 | 4 INPUTP | 2 | 207 | 219 EQ | 6 | Z3_DATA<19>.D = DQ_SWAP & DQ<11>.PIN # !DQ_SWAP & DQ<3>.PIN; Z3_DATA<19>.CLK = CLK_EXT; // GCK Z3_DATA<19>.AP = LAN_SM_RST; Z3_DATA<19>.CE = !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 & LAN_SM_FSM_FFd1; GLOBALS | 1 | 2 | CLK_EXT MACROCELL | 10 | 8 | Z3_DATA<20> ATTRIBUTES | 8553408 | 0 OUTPUTMC | 1 | 0 | 5 INPUTS | 7 | DQ_SWAP | DQ<12>.PIN | DQ<4>.PIN | LAN_SM_RST | LAN_SM_FSM_FFd4 | LAN_SM_FSM_FFd2 | LAN_SM_FSM_FFd1 INPUTMC | 5 | 8 | 1 | 6 | 0 | 14 | 3 | 0 | 1 | 12 | 4 INPUTP | 2 | 235 | 225 EQ | 6 | Z3_DATA<20>.D = DQ_SWAP & DQ<12>.PIN # !DQ_SWAP & DQ<4>.PIN; Z3_DATA<20>.CLK = CLK_EXT; // GCK Z3_DATA<20>.AP = LAN_SM_RST; Z3_DATA<20>.CE = !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 & LAN_SM_FSM_FFd1; GLOBALS | 1 | 2 | CLK_EXT MACROCELL | 10 | 7 | Z3_DATA<21> ATTRIBUTES | 8553408 | 0 OUTPUTMC | 1 | 0 | 4 INPUTS | 7 | DQ_SWAP | DQ<13>.PIN | DQ<5>.PIN | LAN_SM_RST | LAN_SM_FSM_FFd4 | LAN_SM_FSM_FFd2 | LAN_SM_FSM_FFd1 INPUTMC | 5 | 8 | 1 | 6 | 0 | 14 | 3 | 0 | 1 | 12 | 4 INPUTP | 2 | 204 | 221 EQ | 6 | Z3_DATA<21>.D = DQ_SWAP & DQ<13>.PIN # !DQ_SWAP & DQ<5>.PIN; Z3_DATA<21>.CLK = CLK_EXT; // GCK Z3_DATA<21>.AP = LAN_SM_RST; Z3_DATA<21>.CE = !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 & LAN_SM_FSM_FFd1; GLOBALS | 1 | 2 | CLK_EXT MACROCELL | 10 | 6 | Z3_DATA<22> ATTRIBUTES | 8553408 | 0 OUTPUTMC | 1 | 1 | 9 INPUTS | 7 | DQ_SWAP | DQ<14>.PIN | DQ<6>.PIN | LAN_SM_RST | LAN_SM_FSM_FFd4 | LAN_SM_FSM_FFd2 | LAN_SM_FSM_FFd1 INPUTMC | 5 | 8 | 1 | 6 | 0 | 14 | 3 | 0 | 1 | 12 | 4 INPUTP | 2 | 236 | 227 EQ | 6 | Z3_DATA<22>.D = DQ_SWAP & DQ<14>.PIN # !DQ_SWAP & DQ<6>.PIN; Z3_DATA<22>.CLK = CLK_EXT; // GCK Z3_DATA<22>.AP = LAN_SM_RST; Z3_DATA<22>.CE = !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 & LAN_SM_FSM_FFd1; GLOBALS | 1 | 2 | CLK_EXT MACROCELL | 12 | 8 | Z3_DATA<23> ATTRIBUTES | 8553408 | 0 OUTPUTMC | 2 | 1 | 13 | 12 | 9 INPUTS | 11 | DQ_SWAP | DQ<15>.PIN | DQ<7>.PIN | LAN_SM_RST | LAN_SM_FSM_FFd4 | LAN_SM_FSM_FFd2 | LAN_SM_FSM_FFd1 | UDS | LDS | A<21>.PIN | LAN_SM_FSM_FFd3 INPUTMC | 6 | 8 | 1 | 6 | 0 | 14 | 3 | 0 | 1 | 12 | 4 | 0 | 10 INPUTP | 5 | 202 | 226 | 155 | 157 | 163 EXPORTS | 1 | 12 | 9 EQ | 8 | Z3_DATA<23>.D = DQ_SWAP & DQ<15>.PIN # !DQ_SWAP & DQ<7>.PIN; Z3_DATA<23>.CLK = CLK_EXT; // GCK Z3_DATA<23>.AP = LAN_SM_RST; Z3_DATA<23>.CE = !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 & LAN_SM_FSM_FFd1; Z3_DATA<23>.EXP = UDS & LDS & A<21>.PIN & DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 GLOBALS | 1 | 2 | CLK_EXT MACROCELL | 15 | 8 | Z3_DATA<24> ATTRIBUTES | 8553408 | 0 OUTPUTMC | 1 | 1 | 15 INPUTS | 7 | DQ_SWAP | DQ<0>.PIN | DQ<8>.PIN | LAN_SM_RST | LAN_SM_FSM_FFd4 | LAN_SM_FSM_FFd2 | LAN_SM_FSM_FFd1 INPUTMC | 5 | 8 | 1 | 6 | 0 | 14 | 3 | 0 | 1 | 12 | 4 INPUTP | 2 | 217 | 231 EQ | 6 | Z3_DATA<24>.D = DQ_SWAP & DQ<0>.PIN # !DQ_SWAP & DQ<8>.PIN; Z3_DATA<24>.CLK = CLK_EXT; // GCK Z3_DATA<24>.AP = LAN_SM_RST; Z3_DATA<24>.CE = !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 & LAN_SM_FSM_FFd1; GLOBALS | 1 | 2 | CLK_EXT MACROCELL | 15 | 6 | Z3_DATA<25> ATTRIBUTES | 8553408 | 0 OUTPUTMC | 1 | 4 | 10 INPUTS | 7 | DQ_SWAP | DQ<1>.PIN | DQ<9>.PIN | LAN_SM_RST | LAN_SM_FSM_FFd4 | LAN_SM_FSM_FFd2 | LAN_SM_FSM_FFd1 INPUTMC | 5 | 8 | 1 | 6 | 0 | 14 | 3 | 0 | 1 | 12 | 4 INPUTP | 2 | 216 | 209 EQ | 6 | Z3_DATA<25>.D = DQ_SWAP & DQ<1>.PIN # !DQ_SWAP & DQ<9>.PIN; Z3_DATA<25>.CLK = CLK_EXT; // GCK Z3_DATA<25>.AP = LAN_SM_RST; Z3_DATA<25>.CE = !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 & LAN_SM_FSM_FFd1; GLOBALS | 1 | 2 | CLK_EXT MACROCELL | 15 | 4 | Z3_DATA<26> ATTRIBUTES | 8553408 | 0 OUTPUTMC | 1 | 4 | 12 INPUTS | 7 | DQ_SWAP | DQ<10>.PIN | DQ<2>.PIN | LAN_SM_RST | LAN_SM_FSM_FFd4 | LAN_SM_FSM_FFd2 | LAN_SM_FSM_FFd1 INPUTMC | 5 | 8 | 1 | 6 | 0 | 14 | 3 | 0 | 1 | 12 | 4 INPUTP | 2 | 234 | 220 EQ | 6 | Z3_DATA<26>.D = DQ_SWAP & DQ<2>.PIN # !DQ_SWAP & DQ<10>.PIN; Z3_DATA<26>.CLK = CLK_EXT; // GCK Z3_DATA<26>.AP = LAN_SM_RST; Z3_DATA<26>.CE = !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 & LAN_SM_FSM_FFd1; GLOBALS | 1 | 2 | CLK_EXT MACROCELL | 10 | 5 | Z3_DATA<27> ATTRIBUTES | 8553408 | 0 OUTPUTMC | 1 | 4 | 13 INPUTS | 7 | DQ_SWAP | DQ<11>.PIN | DQ<3>.PIN | LAN_SM_RST | LAN_SM_FSM_FFd4 | LAN_SM_FSM_FFd2 | LAN_SM_FSM_FFd1 INPUTMC | 5 | 8 | 1 | 6 | 0 | 14 | 3 | 0 | 1 | 12 | 4 INPUTP | 2 | 207 | 219 EQ | 6 | Z3_DATA<27>.D = DQ_SWAP & DQ<3>.PIN # !DQ_SWAP & DQ<11>.PIN; Z3_DATA<27>.CLK = CLK_EXT; // GCK Z3_DATA<27>.AP = LAN_SM_RST; Z3_DATA<27>.CE = !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 & LAN_SM_FSM_FFd1; GLOBALS | 1 | 2 | CLK_EXT MACROCELL | 10 | 3 | Z3_DATA<28> ATTRIBUTES | 8553408 | 0 OUTPUTMC | 2 | 4 | 15 | 10 | 2 INPUTS | 8 | DQ_SWAP | DQ<12>.PIN | DQ<4>.PIN | LAN_SM_RST | LAN_SM_FSM_FFd4 | LAN_SM_FSM_FFd2 | LAN_SM_FSM_FFd1 | DQ<3>.PIN INPUTMC | 5 | 8 | 1 | 6 | 0 | 14 | 3 | 0 | 1 | 12 | 4 INPUTP | 3 | 235 | 225 | 219 EXPORTS | 1 | 10 | 2 EQ | 7 | Z3_DATA<28>.D = DQ_SWAP & DQ<4>.PIN # !DQ_SWAP & DQ<12>.PIN; Z3_DATA<28>.CLK = CLK_EXT; // GCK Z3_DATA<28>.AP = LAN_SM_RST; Z3_DATA<28>.CE = !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 & LAN_SM_FSM_FFd1; Z3_DATA<28>.EXP = !DQ_SWAP & DQ<3>.PIN GLOBALS | 1 | 2 | CLK_EXT MACROCELL | 10 | 1 | Z3_DATA<29> ATTRIBUTES | 8553408 | 0 OUTPUTMC | 2 | 6 | 1 | 10 | 0 INPUTS | 9 | DQ_SWAP | DQ<13>.PIN | DQ<6>.PIN | LAN_SM_RST | LAN_SM_FSM_FFd4 | LAN_SM_FSM_FFd2 | LAN_SM_FSM_FFd1 | DQ<14>.PIN | Z3_DATA<3>.EXP INPUTMC | 6 | 8 | 1 | 6 | 0 | 14 | 3 | 0 | 1 | 12 | 4 | 10 | 2 INPUTP | 3 | 204 | 227 | 236 EXPORTS | 1 | 10 | 0 IMPORTS | 1 | 10 | 2 EQ | 9 | Z3_DATA<29>.D = !DQ_SWAP & DQ<13>.PIN ;Imported pterms FB11_3 # DQ_SWAP & DQ<5>.PIN; Z3_DATA<29>.CLK = CLK_EXT; // GCK Z3_DATA<29>.AP = LAN_SM_RST; Z3_DATA<29>.CE = !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 & LAN_SM_FSM_FFd1; Z3_DATA<29>.EXP = DQ_SWAP & DQ<6>.PIN # !DQ_SWAP & DQ<14>.PIN GLOBALS | 1 | 2 | CLK_EXT MACROCELL | 10 | 0 | Z3_DATA<30> ATTRIBUTES | 8553408 | 0 OUTPUTMC | 2 | 6 | 5 | 10 | 17 INPUTS | 12 | D<8>.PIN | LDS | DQ_SWAP | LAN_SM_RST | LAN_SM_FSM_FFd4 | LAN_SM_FSM_FFd2 | LAN_SM_FSM_FFd1 | LAN_SM_FSM_FFd3 | A<16>.PIN | UDS | A<8>.PIN | Z3_DATA<29>.EXP INPUTMC | 7 | 8 | 1 | 6 | 0 | 14 | 3 | 0 | 1 | 12 | 4 | 0 | 10 | 10 | 1 INPUTP | 5 | 32 | 157 | 175 | 155 | 106 EXPORTS | 1 | 10 | 17 IMPORTS | 1 | 10 | 1 EQ | 13 | Z3_DATA<30>.D = ;Imported pterms FB11_2 DQ_SWAP & DQ<6>.PIN # !DQ_SWAP & DQ<14>.PIN; Z3_DATA<30>.CLK = CLK_EXT; // GCK Z3_DATA<30>.AP = LAN_SM_RST; Z3_DATA<30>.CE = !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 & LAN_SM_FSM_FFd1; Z3_DATA<30>.EXP = D<8>.PIN & !LDS & DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # A<16>.PIN & UDS & LDS & DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # UDS & LDS & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 & A<8>.PIN GLOBALS | 1 | 2 | CLK_EXT MACROCELL | 12 | 2 | Z3_DATA<31> ATTRIBUTES | 8553408 | 0 OUTPUTMC | 3 | 6 | 10 | 6 | 12 | 12 | 3 INPUTS | 8 | DQ_SWAP | DQ<15>.PIN | DQ<7>.PIN | LAN_SM_RST | LAN_SM_FSM_FFd4 | LAN_SM_FSM_FFd2 | LAN_SM_FSM_FFd1 | DS1 INPUTMC | 5 | 8 | 1 | 6 | 0 | 14 | 3 | 0 | 1 | 12 | 4 INPUTP | 3 | 202 | 226 | 148 EXPORTS | 1 | 12 | 3 EQ | 8 | Z3_DATA<31>.D = DQ_SWAP & DQ<7>.PIN # !DQ_SWAP & DQ<15>.PIN; Z3_DATA<31>.CLK = CLK_EXT; // GCK Z3_DATA<31>.AP = LAN_SM_RST; Z3_DATA<31>.CE = !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 & LAN_SM_FSM_FFd1; Z3_DATA<31>.EXP = !DS1 & !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1 GLOBALS | 1 | 2 | CLK_EXT MACROCELL | 9 | 16 | DQ_10_IOBUFE ATTRIBUTES | 265986 | 0 OUTPUTMC | 1 | 9 | 15 INPUTS | 17 | RESET | LAN_D_INIT<8> | DQ_DATA<10> | $OpTx$FX_DC$117__$INT | D<13>.PIN | AS | AUTO_CONFIG_Z2_DONE<0> | LDS | CP_BASEADR<5> | A<5> | A<4> | A<1> | RW | A<6> | A<3> | A<2> | AUTOCONFIG_Z2_ACCESS INPUTMC | 6 | 5 | 14 | 15 | 15 | 4 | 7 | 7 | 15 | 9 | 15 | 4 | 6 INPUTP | 11 | 263 | 80 | 152 | 157 | 91 | 97 | 107 | 158 | 98 | 99 | 101 EXPORTS | 1 | 9 | 15 EQ | 6 | DQ<10> = RESET & DQ_DATA<10> # !RESET & LAN_D_INIT<8>; DQ<10>.OE = !$OpTx$FX_DC$117__$INT; DQ_10_IOBUFE.EXP = D<13>.PIN & !AS & !AUTO_CONFIG_Z2_DONE<0> & !LDS & !CP_BASEADR<5> & !A<5> & !A<4> & !A<1> & !RW & A<6> & A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS MACROCELL | 11 | 9 | DQ_11_IOBUFE ATTRIBUTES | 265986 | 0 INPUTS | 4 | RESET | LAN_D_INIT<8> | DQ_DATA<11> | $OpTx$FX_DC$117__$INT INPUTMC | 3 | 5 | 14 | 0 | 0 | 4 | 7 INPUTP | 1 | 263 EQ | 3 | DQ<11> = RESET & DQ_DATA<11> # !RESET & LAN_D_INIT<8>; DQ<11>.OE = !$OpTx$FX_DC$117__$INT; MACROCELL | 9 | 1 | DQ_1_IOBUFE ATTRIBUTES | 265986 | 0 INPUTS | 4 | RESET | LAN_D_INIT<1> | DQ_DATA<1> | $OpTx$FX_DC$117__$INT INPUTMC | 3 | 5 | 15 | 14 | 0 | 4 | 7 INPUTP | 1 | 263 EQ | 3 | DQ<1> = RESET & DQ_DATA<1> # !RESET & LAN_D_INIT<1>; DQ<1>.OE = !$OpTx$FX_DC$117__$INT; MACROCELL | 9 | 9 | DQ_4_IOBUFE ATTRIBUTES | 265986 | 0 INPUTS | 4 | RESET | LAN_D_INIT<1> | DQ_DATA<4> | $OpTx$FX_DC$117__$INT INPUTMC | 3 | 5 | 15 | 14 | 10 | 4 | 7 INPUTP | 1 | 263 EQ | 3 | DQ<4> = RESET & DQ_DATA<4> # !RESET & LAN_D_INIT<1>; DQ<4>.OE = !$OpTx$FX_DC$117__$INT; MACROCELL | 9 | 13 | DQ_8_IOBUFE ATTRIBUTES | 265986 | 0 OUTPUTMC | 1 | 9 | 14 INPUTS | 17 | RESET | LAN_D_INIT<8> | DQ_DATA<8> | $OpTx$FX_DC$117__$INT | D<14>.PIN | AS | AUTO_CONFIG_Z2_DONE<0> | LDS | CP_BASEADR<6> | A<5> | A<4> | A<1> | RW | A<6> | A<3> | A<2> | AUTOCONFIG_Z2_ACCESS INPUTMC | 6 | 5 | 14 | 10 | 15 | 4 | 7 | 7 | 15 | 9 | 14 | 4 | 6 INPUTP | 11 | 263 | 81 | 152 | 157 | 91 | 97 | 107 | 158 | 98 | 99 | 101 EXPORTS | 1 | 9 | 14 EQ | 6 | DQ<8> = RESET & DQ_DATA<8> # !RESET & LAN_D_INIT<8>; DQ<8>.OE = !$OpTx$FX_DC$117__$INT; DQ_8_IOBUFE.EXP = D<14>.PIN & !AS & !AUTO_CONFIG_Z2_DONE<0> & !LDS & !CP_BASEADR<6> & !A<5> & !A<4> & !A<1> & !RW & A<6> & A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS MACROCELL | 11 | 11 | DQ_9_IOBUFE ATTRIBUTES | 265986 | 0 INPUTS | 4 | RESET | LAN_D_INIT<1> | DQ_DATA<9> | $OpTx$FX_DC$117__$INT INPUTMC | 3 | 5 | 15 | 14 | 4 | 4 | 7 INPUTP | 1 | 263 EQ | 3 | DQ<9> = RESET & DQ_DATA<9> # !RESET & LAN_D_INIT<1>; DQ<9>.OE = !$OpTx$FX_DC$117__$INT; MACROCELL | 3 | 1 | D_0_IOBUFE ATTRIBUTES | 265986 | 0 INPUTS | 9 | UDS | FCS | Z3_DATA<16> | RW | LAN_ACCESS | DS0 | DS1 | LDS | D_9_IOBUFE/D_9_IOBUFE_TRST__$INT INPUTMC | 3 | 15 | 13 | 8 | 8 | 4 | 8 INPUTP | 6 | 155 | 147 | 158 | 170 | 148 | 157 EQ | 5 | !D<0> = !UDS & !FCS & !Z3_DATA<16> & RW & LAN_ACCESS # !LDS & !FCS & !Z3_DATA<16> & RW & LAN_ACCESS # !DS1 & !FCS & !Z3_DATA<16> & RW & LAN_ACCESS # !DS0 & !FCS & !Z3_DATA<16> & RW & LAN_ACCESS; D<0>.OE = !D_9_IOBUFE/D_9_IOBUFE_TRST__$INT; MACROCELL | 4 | 13 | D_10_IOBUFE ATTRIBUTES | 265986 | 0 OUTPUTMC | 1 | 4 | 14 INPUTS | 10 | FCS | RW | Z3_DATA<27> | LAN_ACCESS | UDS | LDS | DS1 | DS0 | EXP29_.EXP | D_9_IOBUFE/D_9_IOBUFE_TRST__$INT INPUTMC | 4 | 10 | 5 | 8 | 8 | 4 | 12 | 4 | 8 INPUTP | 6 | 147 | 158 | 155 | 157 | 148 | 170 EXPORTS | 1 | 4 | 14 IMPORTS | 1 | 4 | 12 EQ | 10 | D<10> = FCS # !RW ;Imported pterms FB5_13 # Z3_DATA<26> & LAN_ACCESS # !LAN_ACCESS & !AUTOCONFIG_Z3_ACCESS # !LAN_ACCESS & D_OUT<2> # UDS & LDS & DS1 & DS0; D<10>.OE = !D_9_IOBUFE/D_9_IOBUFE_TRST__$INT; D_10_IOBUFE.EXP = Z3_DATA<27> & LAN_ACCESS # UDS & LDS & DS1 & DS0 MACROCELL | 4 | 14 | D_11_IOBUFE ATTRIBUTES | 265986 | 0 INPUTS | 7 | FCS | RW | LAN_ACCESS | AUTOCONFIG_Z3_ACCESS | D_OUT<3> | D_10_IOBUFE.EXP | D_9_IOBUFE/D_9_IOBUFE_TRST__$INT INPUTMC | 5 | 8 | 8 | 7 | 13 | 3 | 2 | 4 | 13 | 4 | 8 INPUTP | 2 | 147 | 158 IMPORTS | 1 | 4 | 13 EQ | 8 | D<11> = FCS # !RW # !LAN_ACCESS & !AUTOCONFIG_Z3_ACCESS # !LAN_ACCESS & D_OUT<3> ;Imported pterms FB5_14 # Z3_DATA<27> & LAN_ACCESS # UDS & LDS & DS1 & DS0; D<11>.OE = !D_9_IOBUFE/D_9_IOBUFE_TRST__$INT; MACROCELL | 4 | 16 | D_12_IOBUFE ATTRIBUTES | 265986 | 0 INPUTS | 12 | FCS | D_Z2_OUT<0> | RW | LAN_ACCESS | AUTOCONFIG_Z3_ACCESS | UDS | LDS | DS1 | DS0 | EXP30_.EXP | ROM_B_0_OBUF$BUF2/ROM_B_0_OBUF$BUF2_TRST.EXP | D_9_IOBUFE/D_9_IOBUFE_TRST__$INT INPUTMC | 6 | 13 | 11 | 8 | 8 | 7 | 13 | 4 | 15 | 4 | 17 | 4 | 8 INPUTP | 6 | 147 | 158 | 155 | 157 | 148 | 170 IMPORTS | 2 | 4 | 15 | 4 | 17 EQ | 19 | D<12> = FCS & D_Z2_OUT<0> # !RW & D_Z2_OUT<0> # !LAN_ACCESS & !AUTOCONFIG_Z3_ACCESS & D_Z2_OUT<0> # UDS & LDS & DS1 & DS0 & D_Z2_OUT<0> ;Imported pterms FB5_16 # !UDS & !FCS & Z3_DATA<28> & RW & LAN_ACCESS # !LDS & !FCS & Z3_DATA<28> & RW & LAN_ACCESS # !DS1 & !FCS & Z3_DATA<28> & RW & LAN_ACCESS # !DS0 & !FCS & Z3_DATA<28> & RW & LAN_ACCESS # !UDS & !FCS & RW & !LAN_ACCESS & AUTOCONFIG_Z3_ACCESS & D_OUT<4> ;Imported pterms FB5_18 # !LDS & !FCS & RW & !LAN_ACCESS & AUTOCONFIG_Z3_ACCESS & D_OUT<4> # !DS1 & !FCS & RW & !LAN_ACCESS & AUTOCONFIG_Z3_ACCESS & D_OUT<4> # !DS0 & !FCS & RW & !LAN_ACCESS & AUTOCONFIG_Z3_ACCESS & D_OUT<4>; D<12>.OE = !D_9_IOBUFE/D_9_IOBUFE_TRST__$INT; MACROCELL | 6 | 2 | D_13_IOBUFE ATTRIBUTES | 265986 | 0 INPUTS | 12 | FCS | D_Z2_OUT<1> | RW | LAN_ACCESS | AUTOCONFIG_Z3_ACCESS | UDS | LDS | DS1 | DS0 | EXP31_.EXP | AUTO_CONFIG_DONE_CYCLE.EXP | D_9_IOBUFE/D_9_IOBUFE_TRST__$INT INPUTMC | 6 | 11 | 15 | 8 | 8 | 7 | 13 | 6 | 1 | 6 | 3 | 4 | 8 INPUTP | 6 | 147 | 158 | 155 | 157 | 148 | 170 IMPORTS | 2 | 6 | 1 | 6 | 3 EQ | 20 | D<13> = FCS & D_Z2_OUT<1> # !RW & D_Z2_OUT<1> # !LAN_ACCESS & !AUTOCONFIG_Z3_ACCESS & D_Z2_OUT<1> # UDS & LDS & DS1 & DS0 & D_Z2_OUT<1> ;Imported pterms FB7_2 # !UDS & !FCS & Z3_DATA<29> & RW & LAN_ACCESS # !LDS & !FCS & Z3_DATA<29> & RW & LAN_ACCESS # !DS1 & !FCS & Z3_DATA<29> & RW & LAN_ACCESS # !DS0 & !FCS & Z3_DATA<29> & RW & LAN_ACCESS # !UDS & !FCS & RW & !LAN_ACCESS & AUTOCONFIG_Z3_ACCESS & D_OUT<5> ;Imported pterms FB7_1 # !LDS & !FCS & RW & !LAN_ACCESS & AUTOCONFIG_Z3_ACCESS & D_OUT<5> ;Imported pterms FB7_4 # !DS1 & !FCS & RW & !LAN_ACCESS & AUTOCONFIG_Z3_ACCESS & D_OUT<5> # !DS0 & !FCS & RW & !LAN_ACCESS & AUTOCONFIG_Z3_ACCESS & D_OUT<5>; D<13>.OE = !D_9_IOBUFE/D_9_IOBUFE_TRST__$INT; MACROCELL | 6 | 4 | D_14_IOBUFE ATTRIBUTES | 265986 | 0 INPUTS | 11 | FCS | D_Z2_OUT<2> | RW | LAN_ACCESS | AUTOCONFIG_Z3_ACCESS | UDS | LDS | DS1 | DS0 | EXP32_.EXP | D_9_IOBUFE/D_9_IOBUFE_TRST__$INT INPUTMC | 5 | 11 | 2 | 8 | 8 | 7 | 13 | 6 | 5 | 4 | 8 INPUTP | 6 | 147 | 158 | 155 | 157 | 148 | 170 IMPORTS | 1 | 6 | 5 EQ | 19 | D<14> = FCS & D_Z2_OUT<2> # !RW & D_Z2_OUT<2> # !LAN_ACCESS & !AUTOCONFIG_Z3_ACCESS & D_Z2_OUT<2> # UDS & LDS & DS1 & DS0 & D_Z2_OUT<2> ;Imported pterms FB7_6 # !UDS & !FCS & Z3_DATA<30> & RW & LAN_ACCESS # !LDS & !FCS & Z3_DATA<30> & RW & LAN_ACCESS # !DS1 & !FCS & Z3_DATA<30> & RW & LAN_ACCESS # !DS0 & !FCS & Z3_DATA<30> & RW & LAN_ACCESS # !UDS & !FCS & RW & !LAN_ACCESS & AUTOCONFIG_Z3_ACCESS & D_OUT<6> ;Imported pterms FB7_7 # !LDS & !FCS & RW & !LAN_ACCESS & AUTOCONFIG_Z3_ACCESS & D_OUT<6> # !DS1 & !FCS & RW & !LAN_ACCESS & AUTOCONFIG_Z3_ACCESS & D_OUT<6> # !DS0 & !FCS & RW & !LAN_ACCESS & AUTOCONFIG_Z3_ACCESS & D_OUT<6>; D<14>.OE = !D_9_IOBUFE/D_9_IOBUFE_TRST__$INT; MACROCELL | 6 | 11 | D_15_IOBUFE ATTRIBUTES | 265986 | 0 INPUTS | 12 | FCS | D_Z2_OUT<3> | RW | LAN_ACCESS | AUTOCONFIG_Z3_ACCESS | UDS | LDS | DS1 | DS0 | LAN_BASEADR<5>.EXP | EXP33_.EXP | D_9_IOBUFE/D_9_IOBUFE_TRST__$INT INPUTMC | 6 | 11 | 5 | 8 | 8 | 7 | 13 | 6 | 10 | 6 | 12 | 4 | 8 INPUTP | 6 | 147 | 158 | 155 | 157 | 148 | 170 IMPORTS | 2 | 6 | 10 | 6 | 12 EQ | 20 | D<15> = FCS & D_Z2_OUT<3> # !RW & D_Z2_OUT<3> # !LAN_ACCESS & !AUTOCONFIG_Z3_ACCESS & D_Z2_OUT<3> # UDS & LDS & DS1 & DS0 & D_Z2_OUT<3> ;Imported pterms FB7_11 # !UDS & !FCS & Z3_DATA<31> & RW & LAN_ACCESS # !DS0 & !FCS & Z3_DATA<31> & RW & LAN_ACCESS ;Imported pterms FB7_13 # !LDS & !FCS & Z3_DATA<31> & RW & LAN_ACCESS # !DS1 & !FCS & Z3_DATA<31> & RW & LAN_ACCESS # !UDS & !FCS & RW & !LAN_ACCESS & AUTOCONFIG_Z3_ACCESS & D_OUT<7> # !DS1 & !FCS & RW & !LAN_ACCESS & AUTOCONFIG_Z3_ACCESS & D_OUT<7> # !DS0 & !FCS & RW & !LAN_ACCESS & AUTOCONFIG_Z3_ACCESS & D_OUT<7> ;Imported pterms FB7_14 # !LDS & !FCS & RW & !LAN_ACCESS & AUTOCONFIG_Z3_ACCESS & D_OUT<7>; D<15>.OE = !D_9_IOBUFE/D_9_IOBUFE_TRST__$INT; MACROCELL | 1 | 14 | D_1_IOBUFE ATTRIBUTES | 265986 | 0 INPUTS | 9 | UDS | FCS | Z3_DATA<17> | RW | LAN_ACCESS | DS0 | DS1 | LDS | D_9_IOBUFE/D_9_IOBUFE_TRST__$INT INPUTMC | 3 | 15 | 12 | 8 | 8 | 4 | 8 INPUTP | 6 | 155 | 147 | 158 | 170 | 148 | 157 EQ | 5 | !D<1> = !UDS & !FCS & !Z3_DATA<17> & RW & LAN_ACCESS # !LDS & !FCS & !Z3_DATA<17> & RW & LAN_ACCESS # !DS1 & !FCS & !Z3_DATA<17> & RW & LAN_ACCESS # !DS0 & !FCS & !Z3_DATA<17> & RW & LAN_ACCESS; D<1>.OE = !D_9_IOBUFE/D_9_IOBUFE_TRST__$INT; MACROCELL | 4 | 9 | D_2_IOBUFE ATTRIBUTES | 265986 | 0 INPUTS | 9 | UDS | FCS | Z3_DATA<18> | RW | LAN_ACCESS | DS0 | DS1 | LDS | D_9_IOBUFE/D_9_IOBUFE_TRST__$INT INPUTMC | 3 | 15 | 11 | 8 | 8 | 4 | 8 INPUTP | 6 | 155 | 147 | 158 | 170 | 148 | 157 EQ | 5 | !D<2> = !UDS & !FCS & !Z3_DATA<18> & RW & LAN_ACCESS # !LDS & !FCS & !Z3_DATA<18> & RW & LAN_ACCESS # !DS1 & !FCS & !Z3_DATA<18> & RW & LAN_ACCESS # !DS0 & !FCS & !Z3_DATA<18> & RW & LAN_ACCESS; D<2>.OE = !D_9_IOBUFE/D_9_IOBUFE_TRST__$INT; MACROCELL | 1 | 11 | D_3_IOBUFE ATTRIBUTES | 265986 | 0 INPUTS | 9 | UDS | FCS | Z3_DATA<19> | RW | LAN_ACCESS | DS0 | DS1 | LDS | D_9_IOBUFE/D_9_IOBUFE_TRST__$INT INPUTMC | 3 | 10 | 12 | 8 | 8 | 4 | 8 INPUTP | 6 | 155 | 147 | 158 | 170 | 148 | 157 EQ | 5 | !D<3> = !UDS & !FCS & !Z3_DATA<19> & RW & LAN_ACCESS # !LDS & !FCS & !Z3_DATA<19> & RW & LAN_ACCESS # !DS1 & !FCS & !Z3_DATA<19> & RW & LAN_ACCESS # !DS0 & !FCS & !Z3_DATA<19> & RW & LAN_ACCESS; D<3>.OE = !D_9_IOBUFE/D_9_IOBUFE_TRST__$INT; MACROCELL | 0 | 5 | D_4_IOBUFE ATTRIBUTES | 265986 | 0 INPUTS | 9 | UDS | FCS | Z3_DATA<20> | RW | LAN_ACCESS | DS0 | DS1 | LDS | D_9_IOBUFE/D_9_IOBUFE_TRST__$INT INPUTMC | 3 | 10 | 8 | 8 | 8 | 4 | 8 INPUTP | 6 | 155 | 147 | 158 | 170 | 148 | 157 EQ | 5 | !D<4> = !UDS & !FCS & !Z3_DATA<20> & RW & LAN_ACCESS # !LDS & !FCS & !Z3_DATA<20> & RW & LAN_ACCESS # !DS1 & !FCS & !Z3_DATA<20> & RW & LAN_ACCESS # !DS0 & !FCS & !Z3_DATA<20> & RW & LAN_ACCESS; D<4>.OE = !D_9_IOBUFE/D_9_IOBUFE_TRST__$INT; MACROCELL | 0 | 4 | D_5_IOBUFE ATTRIBUTES | 265986 | 0 INPUTS | 9 | UDS | FCS | Z3_DATA<21> | RW | LAN_ACCESS | DS0 | DS1 | LDS | D_9_IOBUFE/D_9_IOBUFE_TRST__$INT INPUTMC | 3 | 10 | 7 | 8 | 8 | 4 | 8 INPUTP | 6 | 155 | 147 | 158 | 170 | 148 | 157 EQ | 5 | !D<5> = !UDS & !FCS & !Z3_DATA<21> & RW & LAN_ACCESS # !LDS & !FCS & !Z3_DATA<21> & RW & LAN_ACCESS # !DS1 & !FCS & !Z3_DATA<21> & RW & LAN_ACCESS # !DS0 & !FCS & !Z3_DATA<21> & RW & LAN_ACCESS; D<5>.OE = !D_9_IOBUFE/D_9_IOBUFE_TRST__$INT; MACROCELL | 1 | 9 | D_6_IOBUFE ATTRIBUTES | 265986 | 0 INPUTS | 9 | UDS | FCS | Z3_DATA<22> | RW | LAN_ACCESS | DS0 | DS1 | LDS | D_9_IOBUFE/D_9_IOBUFE_TRST__$INT INPUTMC | 3 | 10 | 6 | 8 | 8 | 4 | 8 INPUTP | 6 | 155 | 147 | 158 | 170 | 148 | 157 EQ | 5 | !D<6> = !UDS & !FCS & !Z3_DATA<22> & RW & LAN_ACCESS # !LDS & !FCS & !Z3_DATA<22> & RW & LAN_ACCESS # !DS1 & !FCS & !Z3_DATA<22> & RW & LAN_ACCESS # !DS0 & !FCS & !Z3_DATA<22> & RW & LAN_ACCESS; D<6>.OE = !D_9_IOBUFE/D_9_IOBUFE_TRST__$INT; MACROCELL | 1 | 13 | D_7_IOBUFE ATTRIBUTES | 265986 | 0 INPUTS | 9 | UDS | FCS | Z3_DATA<23> | RW | LAN_ACCESS | DS0 | DS1 | LDS | D_9_IOBUFE/D_9_IOBUFE_TRST__$INT INPUTMC | 3 | 12 | 8 | 8 | 8 | 4 | 8 INPUTP | 6 | 155 | 147 | 158 | 170 | 148 | 157 EQ | 5 | !D<7> = !UDS & !FCS & !Z3_DATA<23> & RW & LAN_ACCESS # !LDS & !FCS & !Z3_DATA<23> & RW & LAN_ACCESS # !DS1 & !FCS & !Z3_DATA<23> & RW & LAN_ACCESS # !DS0 & !FCS & !Z3_DATA<23> & RW & LAN_ACCESS; D<7>.OE = !D_9_IOBUFE/D_9_IOBUFE_TRST__$INT; MACROCELL | 1 | 16 | D_8_IOBUFE ATTRIBUTES | 265986 | 0 INPUTS | 8 | FCS | RW | LAN_ACCESS | AUTOCONFIG_Z3_ACCESS | D_OUT<0> | LAN_BASEADR<10>.EXP | LAN_BASEADR<0>.EXP | D_9_IOBUFE/D_9_IOBUFE_TRST__$INT INPUTMC | 6 | 8 | 8 | 7 | 13 | 3 | 3 | 1 | 15 | 1 | 17 | 4 | 8 INPUTP | 2 | 147 | 158 IMPORTS | 2 | 1 | 15 | 1 | 17 EQ | 9 | D<8> = FCS # !RW # !LAN_ACCESS & !AUTOCONFIG_Z3_ACCESS # !LAN_ACCESS & D_OUT<0> ;Imported pterms FB2_16 # Z3_DATA<24> & LAN_ACCESS ;Imported pterms FB2_18 # UDS & LDS & DS1 & DS0; D<8>.OE = !D_9_IOBUFE/D_9_IOBUFE_TRST__$INT; MACROCELL | 4 | 11 | D_9_IOBUFE ATTRIBUTES | 265986 | 0 INPUTS | 7 | FCS | RW | LAN_ACCESS | AUTOCONFIG_Z3_ACCESS | D_OUT<1> | EXP28_.EXP | D_9_IOBUFE/D_9_IOBUFE_TRST__$INT INPUTMC | 5 | 8 | 8 | 7 | 13 | 3 | 12 | 4 | 10 | 4 | 8 INPUTP | 2 | 147 | 158 IMPORTS | 1 | 4 | 10 EQ | 8 | D<9> = FCS # !RW # !LAN_ACCESS & !AUTOCONFIG_Z3_ACCESS # !LAN_ACCESS & D_OUT<1> ;Imported pterms FB5_11 # Z3_DATA<25> & LAN_ACCESS # UDS & LDS & DS1 & DS0; D<9>.OE = !D_9_IOBUFE/D_9_IOBUFE_TRST__$INT; MACROCELL | 9 | 2 | DQ_0_IOBUFE ATTRIBUTES | 265986 | 0 OUTPUTMC | 1 | 9 | 3 INPUTS | 17 | RESET | DQ_DATA<0> | $OpTx$FX_DC$117__$INT | D<15>.PIN | AS | AUTO_CONFIG_Z2_DONE<0> | AUTO_CONFIG_Z2_DONE<1> | LDS | IDE_BASEADR<7> | A<5> | A<4> | A<1> | RW | A<6> | A<3> | A<2> | AUTOCONFIG_Z2_ACCESS INPUTMC | 6 | 10 | 17 | 4 | 7 | 7 | 15 | 7 | 14 | 9 | 3 | 4 | 6 INPUTP | 11 | 263 | 89 | 152 | 157 | 91 | 97 | 107 | 158 | 98 | 99 | 101 EXPORTS | 1 | 9 | 3 EQ | 5 | DQ<0> = RESET & DQ_DATA<0>; DQ<0>.OE = !$OpTx$FX_DC$117__$INT; DQ_0_IOBUFE.EXP = D<15>.PIN & !AS & AUTO_CONFIG_Z2_DONE<0> & !AUTO_CONFIG_Z2_DONE<1> & !LDS & !IDE_BASEADR<7> & !A<5> & !A<4> & !A<1> & !RW & A<6> & A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS MACROCELL | 7 | 1 | DQ_12_IOBUFE ATTRIBUTES | 265986 | 0 OUTPUTMC | 1 | 7 | 0 INPUTS | 7 | RESET | DQ_DATA<12> | $OpTx$FX_DC$117__$INT | IDE_BASEADR<6> | A<22>.PIN | IDE_BASEADR<7> | A<23>.PIN INPUTMC | 4 | 0 | 15 | 4 | 7 | 9 | 6 | 9 | 3 INPUTP | 3 | 263 | 162 | 161 EXPORTS | 1 | 7 | 0 EQ | 5 | DQ<12> = RESET & DQ_DATA<12>; DQ<12>.OE = !$OpTx$FX_DC$117__$INT; DQ_12_IOBUFE.EXP = IDE_BASEADR<6> & !A<22>.PIN # !IDE_BASEADR<6> & A<22>.PIN # IDE_BASEADR<7> & !A<23>.PIN MACROCELL | 11 | 7 | DQ_13_IOBUFE ATTRIBUTES | 265986 | 0 OUTPUTMC | 1 | 11 | 6 INPUTS | 12 | RESET | DQ_DATA<13> | $OpTx$FX_DC$117__$INT | AS | LDS | A<5> | A<4> | A<1> | A<6> | A<3> | A<2> | AUTOCONFIG_Z2_ACCESS INPUTMC | 3 | 12 | 17 | 4 | 7 | 4 | 6 INPUTP | 9 | 263 | 152 | 157 | 91 | 97 | 107 | 98 | 99 | 101 EXPORTS | 1 | 11 | 6 EQ | 4 | DQ<13> = RESET & DQ_DATA<13>; DQ<13>.OE = !$OpTx$FX_DC$117__$INT; DQ_13_IOBUFE.EXP = !AS & !LDS & !A<5> & A<4> & !A<1> & !A<6> & A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS MACROCELL | 7 | 2 | DQ_14_IOBUFE ATTRIBUTES | 265986 | 0 INPUTS | 3 | RESET | DQ_DATA<14> | $OpTx$FX_DC$117__$INT INPUTMC | 2 | 12 | 14 | 4 | 7 INPUTP | 1 | 263 EQ | 2 | DQ<14> = RESET & DQ_DATA<14>; DQ<14>.OE = !$OpTx$FX_DC$117__$INT; MACROCELL | 11 | 4 | DQ_15_IOBUFE ATTRIBUTES | 265986 | 0 OUTPUTMC | 1 | 11 | 5 INPUTS | 14 | RESET | DQ_DATA<15> | $OpTx$FX_DC$117__$INT | AS | AUTO_CONFIG_Z2_DONE<0> | UDS | A<5> | A<1> | A<6> | A<3> | AUTOCONFIG_Z2_ACCESS | A<4> | A<2> | LDS INPUTMC | 4 | 12 | 12 | 4 | 7 | 7 | 15 | 4 | 6 INPUTP | 10 | 263 | 152 | 155 | 91 | 107 | 98 | 99 | 97 | 101 | 157 EXPORTS | 1 | 11 | 5 EQ | 8 | DQ<15> = RESET & DQ_DATA<15>; DQ<15>.OE = !$OpTx$FX_DC$117__$INT; DQ_15_IOBUFE.EXP = !AS & !AUTO_CONFIG_Z2_DONE<0> & !UDS & !A<5> & A<1> & !A<6> & !A<3> & AUTOCONFIG_Z2_ACCESS # !AS & !UDS & !A<5> & A<4> & A<1> & !A<6> & A<2> & AUTOCONFIG_Z2_ACCESS # !AS & !LDS & !A<5> & !A<4> & A<6> & !A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS MACROCELL | 9 | 5 | DQ_2_IOBUFE ATTRIBUTES | 265986 | 0 OUTPUTMC | 1 | 9 | 6 INPUTS | 17 | RESET | DQ_DATA<2> | $OpTx$FX_DC$117__$INT | D<14>.PIN | AS | AUTO_CONFIG_Z2_DONE<0> | AUTO_CONFIG_Z2_DONE<1> | LDS | IDE_BASEADR<6> | A<5> | A<4> | A<1> | RW | A<6> | A<3> | A<2> | AUTOCONFIG_Z2_ACCESS INPUTMC | 6 | 15 | 16 | 4 | 7 | 7 | 15 | 7 | 14 | 9 | 6 | 4 | 6 INPUTP | 11 | 263 | 81 | 152 | 157 | 91 | 97 | 107 | 158 | 98 | 99 | 101 EXPORTS | 1 | 9 | 6 EQ | 5 | DQ<2> = RESET & DQ_DATA<2>; DQ<2>.OE = !$OpTx$FX_DC$117__$INT; DQ_2_IOBUFE.EXP = D<14>.PIN & !AS & AUTO_CONFIG_Z2_DONE<0> & !AUTO_CONFIG_Z2_DONE<1> & !LDS & !IDE_BASEADR<6> & !A<5> & !A<4> & !A<1> & !RW & A<6> & A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS MACROCELL | 9 | 4 | DQ_3_IOBUFE ATTRIBUTES | 265986 | 0 INPUTS | 3 | RESET | DQ_DATA<3> | $OpTx$FX_DC$117__$INT INPUTMC | 2 | 0 | 12 | 4 | 7 INPUTP | 1 | 263 EQ | 2 | DQ<3> = RESET & DQ_DATA<3>; DQ<3>.OE = !$OpTx$FX_DC$117__$INT; MACROCELL | 9 | 7 | DQ_5_IOBUFE ATTRIBUTES | 265986 | 0 OUTPUTMC | 1 | 9 | 8 INPUTS | 17 | RESET | DQ_DATA<5> | $OpTx$FX_DC$117__$INT | D<13>.PIN | AS | AUTO_CONFIG_Z2_DONE<0> | AUTO_CONFIG_Z2_DONE<1> | LDS | IDE_BASEADR<5> | A<5> | A<4> | A<1> | RW | A<6> | A<3> | A<2> | AUTOCONFIG_Z2_ACCESS INPUTMC | 6 | 12 | 11 | 4 | 7 | 7 | 15 | 7 | 14 | 9 | 8 | 4 | 6 INPUTP | 11 | 263 | 80 | 152 | 157 | 91 | 97 | 107 | 158 | 98 | 99 | 101 EXPORTS | 1 | 9 | 8 EQ | 5 | DQ<5> = RESET & DQ_DATA<5>; DQ<5>.OE = !$OpTx$FX_DC$117__$INT; DQ_5_IOBUFE.EXP = D<13>.PIN & !AS & AUTO_CONFIG_Z2_DONE<0> & !AUTO_CONFIG_Z2_DONE<1> & !LDS & !IDE_BASEADR<5> & !A<5> & !A<4> & !A<1> & !RW & A<6> & A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS MACROCELL | 9 | 11 | DQ_6_IOBUFE ATTRIBUTES | 265986 | 0 OUTPUTMC | 1 | 9 | 12 INPUTS | 17 | RESET | DQ_DATA<6> | $OpTx$FX_DC$117__$INT | D<12>.PIN | AS | AUTO_CONFIG_Z2_DONE<0> | AUTO_CONFIG_Z2_DONE<1> | LDS | IDE_BASEADR<4> | A<5> | A<4> | A<1> | RW | A<6> | A<3> | A<2> | AUTOCONFIG_Z2_ACCESS INPUTMC | 6 | 12 | 6 | 4 | 7 | 7 | 15 | 7 | 14 | 9 | 12 | 4 | 6 INPUTP | 11 | 263 | 78 | 152 | 157 | 91 | 97 | 107 | 158 | 98 | 99 | 101 EXPORTS | 1 | 9 | 12 EQ | 5 | DQ<6> = RESET & DQ_DATA<6>; DQ<6>.OE = !$OpTx$FX_DC$117__$INT; DQ_6_IOBUFE.EXP = D<12>.PIN & !AS & AUTO_CONFIG_Z2_DONE<0> & !AUTO_CONFIG_Z2_DONE<1> & !LDS & !IDE_BASEADR<4> & !A<5> & !A<4> & !A<1> & !RW & A<6> & A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS MACROCELL | 9 | 10 | DQ_7_IOBUFE ATTRIBUTES | 265986 | 0 INPUTS | 3 | RESET | DQ_DATA<7> | $OpTx$FX_DC$117__$INT INPUTMC | 2 | 14 | 9 | 4 | 7 INPUTP | 1 | 263 EQ | 2 | DQ<7> = RESET & DQ_DATA<7>; DQ<7>.OE = !$OpTx$FX_DC$117__$INT; MACROCELL | 8 | 1 | DQ_SWAP ATTRIBUTES | 8520608 | 0 OUTPUTMC | 67 | 0 | 17 | 15 | 5 | 15 | 2 | 15 | 1 | 14 | 16 | 14 | 14 | 14 | 13 | 8 | 13 | 8 | 16 | 10 | 2 | 10 | 4 | 10 | 9 | 10 | 10 | 12 | 7 | 15 | 10 | 15 | 7 | 15 | 13 | 15 | 12 | 15 | 11 | 10 | 12 | 10 | 8 | 10 | 7 | 10 | 6 | 12 | 8 | 15 | 8 | 15 | 6 | 15 | 4 | 10 | 5 | 10 | 3 | 10 | 1 | 8 | 11 | 12 | 2 | 10 | 16 | 15 | 14 | 14 | 3 | 0 | 14 | 12 | 16 | 12 | 13 | 12 | 11 | 12 | 17 | 15 | 0 | 0 | 11 | 14 | 9 | 12 | 10 | 12 | 5 | 14 | 8 | 10 | 14 | 0 | 1 | 0 | 13 | 0 | 16 | 10 | 0 | 10 | 13 | 12 | 0 | 12 | 1 | 12 | 4 | 12 | 9 | 12 | 15 | 14 | 1 | 14 | 5 | 14 | 6 | 14 | 7 | 14 | 11 | 14 | 12 | 14 | 15 | 14 | 17 | 15 | 16 | 15 | 17 INPUTS | 7 | SHUT_UP | Z3 | $OpTx$INV$215 | EXP36_.EXP | EXP37_.EXP | FCS | RESET INPUTMC | 4 | 6 | 6 | 2 | 0 | 8 | 0 | 8 | 2 INPUTP | 3 | 151 | 147 | 263 IMPORTS | 2 | 8 | 0 | 8 | 2 EQ | 27 | DQ_SWAP.D = !Z3 # SHUT_UP # $OpTx$INV$215 ;Imported pterms FB9_1 # !A<13>.PIN # !A<14>.PIN # D<9>.PIN & !LAN_BASEADR<9> # !D<9>.PIN & LAN_BASEADR<9> # D<11>.PIN & !LAN_BASEADR<11> ;Imported pterms FB9_18 # D<8>.PIN & !LAN_BASEADR<8> # !D<8>.PIN & LAN_BASEADR<8> # D<13>.PIN & !LAN_BASEADR<13> # D<12>.PIN & !LAN_BASEADR<12> # !D<12>.PIN & LAN_BASEADR<12> ;Imported pterms FB9_3 # !D<11>.PIN & LAN_BASEADR<11> # D<10>.PIN & !LAN_BASEADR<10> # !D<10>.PIN & LAN_BASEADR<10> # D<15>.PIN & !LAN_BASEADR<15> # !D<15>.PIN & LAN_BASEADR<15> ;Imported pterms FB9_4 # !D<13>.PIN & LAN_BASEADR<13> # LAN_BASEADR<6> & !A<22>.PIN # !LAN_BASEADR<6> & A<22>.PIN; DQ_SWAP.CLK = !FCS; DQ_SWAP.AP = !RESET; MACROCELL | 0 | 10 | LAN_SM_FSM_FFd3 ATTRIBUTES | 8553232 | 0 OUTPUTMC | 72 | 8 | 10 | 15 | 5 | 15 | 2 | 15 | 1 | 14 | 16 | 14 | 14 | 14 | 13 | 8 | 13 | 8 | 16 | 10 | 2 | 10 | 4 | 10 | 9 | 10 | 10 | 12 | 7 | 15 | 10 | 15 | 7 | 0 | 10 | 14 | 3 | 0 | 8 | 12 | 3 | 10 | 17 | 15 | 15 | 0 | 0 | 0 | 15 | 12 | 17 | 12 | 13 | 12 | 12 | 14 | 0 | 15 | 14 | 0 | 12 | 14 | 10 | 12 | 10 | 12 | 6 | 14 | 8 | 10 | 15 | 14 | 4 | 14 | 12 | 14 | 15 | 14 | 6 | 14 | 17 | 0 | 1 | 0 | 2 | 0 | 7 | 0 | 9 | 0 | 11 | 0 | 13 | 0 | 14 | 0 | 16 | 0 | 17 | 10 | 0 | 10 | 13 | 10 | 14 | 10 | 16 | 12 | 0 | 12 | 1 | 12 | 4 | 12 | 5 | 12 | 8 | 12 | 9 | 12 | 11 | 12 | 15 | 12 | 16 | 14 | 1 | 14 | 2 | 14 | 5 | 14 | 7 | 14 | 9 | 14 | 11 | 15 | 0 | 15 | 13 | 15 | 16 | 15 | 17 INPUTS | 8 | LAN_SM_FSM_FFd4 | LAN_SM_FSM_FFd3 | LAN_SM_FSM_FFd2 | LAN_SM_FSM_FFd1 | DS1 | DS0 | IDE_CS_1_OBUF.EXP | LAN_SM_RST INPUTMC | 6 | 14 | 3 | 0 | 10 | 0 | 1 | 12 | 4 | 0 | 9 | 6 | 0 INPUTP | 2 | 148 | 170 IMPORTS | 1 | 0 | 9 EQ | 10 | LAN_SM_FSM_FFd3.D = LAN_SM_FSM_FFd4 # LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd2 # !LAN_SM_FSM_FFd2 & LAN_SM_FSM_FFd1 # DS1 & DS0 & LAN_SM_FSM_FFd2 ;Imported pterms FB1_10 # !LAN_SM_FSM_FFd3 & LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1 # UDS & LDS & RW & !LAN_SM_FSM_FFd3; LAN_SM_FSM_FFd3.CLK = CLK_EXT; // GCK LAN_SM_FSM_FFd3.AR = LAN_SM_RST; GLOBALS | 1 | 2 | CLK_EXT MACROCELL | 14 | 3 | LAN_SM_FSM_FFd4 ATTRIBUTES | 8553232 | 0 OUTPUTMC | 84 | 8 | 10 | 15 | 5 | 15 | 2 | 15 | 1 | 14 | 16 | 14 | 14 | 14 | 13 | 8 | 13 | 8 | 16 | 10 | 2 | 10 | 4 | 10 | 9 | 10 | 10 | 12 | 7 | 15 | 10 | 15 | 7 | 15 | 13 | 15 | 12 | 15 | 11 | 10 | 12 | 10 | 8 | 10 | 7 | 10 | 6 | 12 | 8 | 15 | 8 | 15 | 6 | 15 | 4 | 10 | 5 | 10 | 3 | 10 | 1 | 10 | 0 | 12 | 2 | 0 | 10 | 14 | 2 | 0 | 1 | 12 | 3 | 10 | 17 | 15 | 15 | 0 | 0 | 0 | 15 | 12 | 17 | 12 | 13 | 12 | 12 | 14 | 0 | 15 | 16 | 0 | 12 | 14 | 10 | 12 | 10 | 12 | 6 | 14 | 8 | 10 | 15 | 14 | 4 | 14 | 12 | 14 | 15 | 14 | 6 | 14 | 11 | 0 | 8 | 0 | 2 | 0 | 7 | 0 | 11 | 0 | 13 | 0 | 14 | 0 | 16 | 0 | 17 | 10 | 13 | 10 | 14 | 10 | 16 | 12 | 0 | 12 | 1 | 12 | 4 | 12 | 5 | 12 | 9 | 12 | 11 | 12 | 15 | 12 | 16 | 14 | 1 | 14 | 3 | 14 | 5 | 14 | 7 | 14 | 9 | 14 | 17 | 15 | 0 | 15 | 14 | 15 | 17 INPUTS | 11 | LAN_SM_FSM_FFd3 | LAN_SM_FSM_FFd2 | A<17>.PIN | DQ_SWAP | LAN_SM_FSM_FFd4 | LAN_SM_FSM_FFd1 | LAN_SM_RST | UDS | D<1>.PIN | A<9>.PIN | CP_RD_S.EXP INPUTMC | 7 | 0 | 10 | 0 | 1 | 8 | 1 | 14 | 3 | 12 | 4 | 6 | 0 | 14 | 2 INPUTP | 4 | 172 | 155 | 30 | 108 EXPORTS | 1 | 14 | 4 IMPORTS | 1 | 14 | 2 EQ | 13 | !LAN_SM_FSM_FFd4.D = LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd2 ;Imported pterms FB15_3 # LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1 # DS1 & DS0 & LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4; LAN_SM_FSM_FFd4.CLK = CLK_EXT; // GCK LAN_SM_FSM_FFd4.AR = LAN_SM_RST; LAN_SM_FSM_FFd4.EXP = A<17>.PIN & !DQ_SWAP & !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1 # !UDS & D<1>.PIN & DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # DQ_SWAP & !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1 & A<9>.PIN GLOBALS | 1 | 2 | CLK_EXT MACROCELL | 0 | 1 | LAN_SM_FSM_FFd2 ATTRIBUTES | 8553232 | 0 OUTPUTMC | 72 | 8 | 10 | 15 | 5 | 15 | 2 | 15 | 1 | 14 | 16 | 14 | 14 | 14 | 13 | 8 | 13 | 8 | 16 | 10 | 2 | 10 | 4 | 10 | 9 | 10 | 10 | 12 | 7 | 15 | 10 | 15 | 7 | 15 | 13 | 15 | 12 | 15 | 11 | 10 | 12 | 10 | 8 | 10 | 7 | 10 | 6 | 12 | 8 | 15 | 8 | 15 | 6 | 15 | 4 | 10 | 5 | 10 | 3 | 10 | 1 | 10 | 0 | 12 | 2 | 0 | 10 | 14 | 3 | 0 | 1 | 12 | 4 | 10 | 17 | 15 | 15 | 0 | 0 | 0 | 15 | 12 | 17 | 12 | 11 | 12 | 12 | 14 | 0 | 15 | 14 | 0 | 12 | 14 | 10 | 12 | 10 | 12 | 6 | 14 | 8 | 10 | 15 | 14 | 4 | 14 | 12 | 14 | 15 | 14 | 6 | 14 | 17 | 0 | 8 | 0 | 2 | 0 | 9 | 0 | 11 | 0 | 14 | 0 | 17 | 10 | 14 | 10 | 16 | 12 | 0 | 12 | 3 | 12 | 5 | 12 | 15 | 14 | 2 | 14 | 7 | 14 | 9 | 15 | 17 INPUTS | 11 | LAN_SM_FSM_FFd4 | LAN_SM_FSM_FFd2 | LDS | D<3>.PIN | DQ_SWAP | LAN_SM_FSM_FFd3 | A<19>.PIN | UDS | LAN_SM_RST | A<11>.PIN | EXP22_.EXP INPUTMC | 6 | 14 | 3 | 0 | 1 | 8 | 1 | 0 | 10 | 6 | 0 | 0 | 2 INPUTP | 5 | 157 | 28 | 169 | 155 | 114 EXPORTS | 1 | 0 | 0 IMPORTS | 1 | 0 | 2 EQ | 15 | LAN_SM_FSM_FFd2.D = LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 ;Imported pterms FB1_3 # !UDS & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # !LDS & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # DS1 & DS0 & LAN_SM_FSM_FFd2 # !LAN_SM_FSM_FFd3 & LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1; LAN_SM_FSM_FFd2.CLK = CLK_EXT; // GCK LAN_SM_FSM_FFd2.AR = LAN_SM_RST; LAN_SM_FSM_FFd2.EXP = !LDS & D<3>.PIN & DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # A<19>.PIN & UDS & LDS & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # UDS & LDS & DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 & A<11>.PIN GLOBALS | 1 | 2 | CLK_EXT MACROCELL | 12 | 4 | LAN_SM_FSM_FFd1 ATTRIBUTES | 8553232 | 0 OUTPUTMC | 74 | 8 | 10 | 15 | 5 | 15 | 2 | 15 | 1 | 14 | 16 | 14 | 14 | 14 | 13 | 8 | 13 | 8 | 16 | 10 | 2 | 10 | 4 | 10 | 9 | 10 | 10 | 12 | 7 | 15 | 10 | 15 | 7 | 15 | 13 | 15 | 12 | 15 | 11 | 10 | 12 | 10 | 8 | 10 | 7 | 10 | 6 | 12 | 8 | 15 | 8 | 15 | 6 | 15 | 4 | 10 | 5 | 10 | 3 | 10 | 1 | 10 | 0 | 12 | 2 | 0 | 10 | 14 | 2 | 0 | 8 | 12 | 4 | 10 | 17 | 15 | 15 | 0 | 0 | 0 | 15 | 12 | 17 | 12 | 14 | 12 | 12 | 14 | 0 | 15 | 16 | 0 | 12 | 14 | 10 | 12 | 11 | 12 | 6 | 14 | 8 | 10 | 15 | 14 | 4 | 14 | 12 | 14 | 15 | 14 | 6 | 14 | 17 | 0 | 2 | 0 | 7 | 0 | 9 | 0 | 11 | 0 | 14 | 0 | 17 | 10 | 14 | 10 | 16 | 12 | 0 | 12 | 3 | 12 | 5 | 12 | 10 | 12 | 15 | 14 | 3 | 14 | 7 | 14 | 9 | 15 | 14 | 15 | 17 INPUTS | 12 | LAN_SM_FSM_FFd2 | LAN_SM_FSM_FFd1 | LDS | D<6>.PIN | DQ_SWAP | LAN_SM_FSM_FFd3 | LAN_SM_FSM_FFd4 | LAN_SM_RST | UDS | A<22>.PIN | A<14>.PIN | EXP47_.EXP INPUTMC | 7 | 0 | 1 | 12 | 4 | 8 | 1 | 0 | 10 | 14 | 3 | 6 | 0 | 12 | 3 INPUTP | 5 | 157 | 26 | 155 | 162 | 125 EXPORTS | 1 | 12 | 5 IMPORTS | 1 | 12 | 3 EQ | 21 | LAN_SM_FSM_FFd1.D = !LAN_SM_FSM_FFd2 & LAN_SM_FSM_FFd1 ;Imported pterms FB13_4 # !RW & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # LAN_SM_FSM_FFd3 & LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd1 # !LAN_SM_FSM_FFd3 & LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1 # DS1 & DS0 & !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd1 # !DS0 & !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1 ;Imported pterms FB13_3 # !DS1 & !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1; LAN_SM_FSM_FFd1.CLK = CLK_EXT; // GCK LAN_SM_FSM_FFd1.AR = LAN_SM_RST; LAN_SM_FSM_FFd1.EXP = !LDS & D<6>.PIN & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # UDS & LDS & A<22>.PIN & DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # UDS & LDS & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 & A<14>.PIN GLOBALS | 1 | 2 | CLK_EXT MACROCELL | 9 | 0 | Z3_ADR<2> ATTRIBUTES | 8520608 | 0 OUTPUTMC | 26 | 6 | 3 | 1 | 17 | 1 | 15 | 1 | 12 | 1 | 10 | 1 | 8 | 1 | 6 | 1 | 3 | 1 | 0 | 6 | 7 | 6 | 8 | 6 | 9 | 6 | 10 | 6 | 13 | 6 | 14 | 6 | 16 | 6 | 17 | 6 | 6 | 3 | 3 | 3 | 12 | 3 | 6 | 3 | 10 | 3 | 9 | 3 | 8 | 3 | 7 | 9 | 17 INPUTS | 15 | A<4> | FCS | RESET | D<12>.PIN | AS | AUTO_CONFIG_Z2_DONE<0> | LDS | CP_BASEADR<4> | A<5> | A<1> | RW | A<6> | A<3> | A<2> | AUTOCONFIG_Z2_ACCESS INPUTMC | 3 | 7 | 15 | 9 | 17 | 4 | 6 INPUTP | 12 | 97 | 147 | 263 | 78 | 152 | 157 | 91 | 107 | 158 | 98 | 99 | 101 EXPORTS | 1 | 9 | 17 EQ | 6 | Z3_ADR<2>.D = A<4>; Z3_ADR<2>.CLK = !FCS; Z3_ADR<2>.AP = !RESET; Z3_ADR<2>.EXP = D<12>.PIN & !AS & !AUTO_CONFIG_Z2_DONE<0> & !LDS & !CP_BASEADR<4> & !A<5> & !A<4> & !A<1> & !RW & A<6> & A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS MACROCELL | 11 | 0 | Z3_ADR_1 ATTRIBUTES | 8520608 | 0 OUTPUTMC | 26 | 1 | 17 | 1 | 15 | 1 | 12 | 1 | 10 | 1 | 8 | 1 | 6 | 1 | 3 | 1 | 0 | 6 | 7 | 6 | 8 | 6 | 9 | 6 | 10 | 6 | 13 | 6 | 14 | 6 | 16 | 6 | 17 | 6 | 6 | 3 | 3 | 3 | 12 | 3 | 6 | 3 | 2 | 3 | 10 | 3 | 9 | 3 | 8 | 3 | 0 | 3 | 11 INPUTS | 3 | A<3> | FCS | RESET INPUTP | 3 | 99 | 147 | 263 EQ | 3 | Z3_ADR_1.D = A<3>; Z3_ADR_1.CLK = !FCS; Z3_ADR_1.AP = !RESET; MACROCELL | 11 | 17 | Z3_ADR_0 ATTRIBUTES | 8520608 | 0 OUTPUTMC | 26 | 6 | 3 | 1 | 17 | 1 | 15 | 1 | 12 | 1 | 10 | 1 | 8 | 1 | 6 | 1 | 3 | 1 | 0 | 6 | 7 | 6 | 8 | 6 | 9 | 6 | 10 | 6 | 13 | 6 | 14 | 6 | 16 | 6 | 17 | 6 | 6 | 3 | 3 | 3 | 12 | 3 | 6 | 3 | 10 | 3 | 9 | 3 | 8 | 3 | 4 | 11 | 16 INPUTS | 12 | A<2> | FCS | RESET | AS | AUTO_CONFIG_Z2_DONE<0> | LDS | A<5> | A<1> | A<6> | A<3> | AUTOCONFIG_Z2_ACCESS | A<4> INPUTMC | 2 | 7 | 15 | 4 | 6 INPUTP | 10 | 101 | 147 | 263 | 152 | 157 | 91 | 107 | 98 | 99 | 97 EXPORTS | 1 | 11 | 16 EQ | 7 | Z3_ADR_0.D = A<2>; Z3_ADR_0.CLK = !FCS; Z3_ADR_0.AP = !RESET; Z3_ADR_0.EXP = !AS & !AUTO_CONFIG_Z2_DONE<0> & !LDS & !A<5> & A<1> & !A<6> & !A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS # !AS & !LDS & A<5> & !A<4> & !A<1> & !A<6> & !A<3> & A<2> & AUTOCONFIG_Z2_ACCESS MACROCELL | 5 | 8 | LAN_RST_SM_FSM_FFd3 ATTRIBUTES | 4358928 | 0 OUTPUTMC | 8 | 5 | 8 | 5 | 10 | 5 | 11 | 5 | 15 | 5 | 14 | 5 | 6 | 5 | 17 | 5 | 16 INPUTS | 4 | LAN_RST_SM_FSM_FFd3 | LAN_RST_SM_FSM_FFd2 | LAN_RST_SM_FSM_FFd1 | RESET INPUTMC | 3 | 5 | 8 | 5 | 10 | 5 | 11 INPUTP | 1 | 263 EQ | 6 | LAN_RST_SM_FSM_FFd3.T = LAN_RST_SM_FSM_FFd3 & LAN_RST_SM_FSM_FFd2 & !LAN_RST_SM_FSM_FFd1 # !LAN_RST_SM_FSM_FFd3 & !LAN_RST_SM_FSM_FFd2 & LAN_RST_SM_FSM_FFd1; LAN_RST_SM_FSM_FFd3.CLK = CLK_EXT; // GCK LAN_RST_SM_FSM_FFd3.AR = RESET; GLOBALS | 1 | 2 | CLK_EXT MACROCELL | 5 | 10 | LAN_RST_SM_FSM_FFd2 ATTRIBUTES | 8553232 | 0 OUTPUTMC | 8 | 5 | 8 | 5 | 10 | 5 | 11 | 5 | 15 | 5 | 14 | 5 | 6 | 5 | 17 | 5 | 16 INPUTS | 4 | LAN_RST_SM_FSM_FFd3 | LAN_RST_SM_FSM_FFd2 | LAN_RST_SM_FSM_FFd1 | RESET INPUTMC | 3 | 5 | 8 | 5 | 10 | 5 | 11 INPUTP | 1 | 263 EQ | 5 | !LAN_RST_SM_FSM_FFd2.D = !LAN_RST_SM_FSM_FFd3 & !LAN_RST_SM_FSM_FFd2 # LAN_RST_SM_FSM_FFd3 & LAN_RST_SM_FSM_FFd2 & LAN_RST_SM_FSM_FFd1; LAN_RST_SM_FSM_FFd2.CLK = CLK_EXT; // GCK LAN_RST_SM_FSM_FFd2.AR = RESET; GLOBALS | 1 | 2 | CLK_EXT MACROCELL | 2 | 16 | Z3_ADR<6> ATTRIBUTES | 8520608 | 0 OUTPUTMC | 24 | 6 | 3 | 1 | 17 | 1 | 15 | 1 | 12 | 1 | 10 | 1 | 8 | 1 | 6 | 1 | 3 | 1 | 0 | 6 | 7 | 6 | 8 | 6 | 9 | 6 | 10 | 6 | 13 | 6 | 14 | 6 | 16 | 6 | 17 | 6 | 6 | 3 | 10 | 3 | 9 | 3 | 8 | 3 | 0 | 1 | 2 | 2 | 17 INPUTS | 5 | A<8>.PIN | FCS | RESET | A<19>.PIN | LAN_BASEADR<3> INPUTMC | 1 | 6 | 8 INPUTP | 4 | 106 | 147 | 263 | 169 EXPORTS | 1 | 2 | 17 EQ | 4 | Z3_ADR<6>.D = A<8>.PIN; Z3_ADR<6>.CLK = !FCS; Z3_ADR<6>.AP = !RESET; Z3_ADR<6>.EXP = !A<19>.PIN & LAN_BASEADR<3> MACROCELL | 5 | 11 | LAN_RST_SM_FSM_FFd1 ATTRIBUTES | 8553232 | 0 OUTPUTMC | 8 | 5 | 8 | 5 | 10 | 5 | 11 | 5 | 15 | 5 | 14 | 5 | 6 | 5 | 17 | 5 | 16 INPUTS | 4 | LAN_RST_SM_FSM_FFd3 | LAN_RST_SM_FSM_FFd2 | LAN_RST_SM_FSM_FFd1 | RESET INPUTMC | 3 | 5 | 8 | 5 | 10 | 5 | 11 INPUTP | 1 | 263 EQ | 4 | LAN_RST_SM_FSM_FFd1.D = !LAN_RST_SM_FSM_FFd3 # !LAN_RST_SM_FSM_FFd2 & LAN_RST_SM_FSM_FFd1; LAN_RST_SM_FSM_FFd1.CLK = CLK_EXT; // GCK LAN_RST_SM_FSM_FFd1.AR = RESET; GLOBALS | 1 | 2 | CLK_EXT MACROCELL | 8 | 8 | LAN_ACCESS ATTRIBUTES | 8520496 | 0 OUTPUTMC | 37 | 6 | 15 | 3 | 1 | 4 | 12 | 4 | 14 | 4 | 16 | 6 | 2 | 6 | 4 | 6 | 11 | 1 | 14 | 4 | 9 | 1 | 11 | 0 | 5 | 0 | 4 | 1 | 9 | 1 | 13 | 1 | 16 | 4 | 11 | 8 | 5 | 6 | 0 | 7 | 7 | 13 | 13 | 4 | 3 | 4 | 7 | 4 | 8 | 4 | 17 | 1 | 15 | 4 | 10 | 4 | 13 | 4 | 15 | 6 | 1 | 6 | 3 | 6 | 5 | 6 | 6 | 6 | 10 | 6 | 12 | 6 | 13 | 13 | 14 INPUTS | 7 | SHUT_UP | Z3 | $OpTx$INV$215 | EXP38_.EXP | EXP39_.EXP | FCS | RESET INPUTMC | 4 | 6 | 6 | 2 | 0 | 8 | 7 | 8 | 9 INPUTP | 3 | 151 | 147 | 263 IMPORTS | 2 | 8 | 7 | 8 | 9 EQ | 25 | !LAN_ACCESS.D = !Z3 # SHUT_UP # $OpTx$INV$215 ;Imported pterms FB9_8 # D<9>.PIN & !LAN_BASEADR<9> # !D<9>.PIN & LAN_BASEADR<9> # D<11>.PIN & !LAN_BASEADR<11> # !D<11>.PIN & LAN_BASEADR<11> # D<15>.PIN & !LAN_BASEADR<15> ;Imported pterms FB9_7 # D<8>.PIN & !LAN_BASEADR<8> # !D<8>.PIN & LAN_BASEADR<8> # D<13>.PIN & !LAN_BASEADR<13> # !D<13>.PIN & LAN_BASEADR<13> ;Imported pterms FB9_10 # D<12>.PIN & !LAN_BASEADR<12> # !D<12>.PIN & LAN_BASEADR<12> # D<10>.PIN & !LAN_BASEADR<10> # !D<10>.PIN & LAN_BASEADR<10> # !D<15>.PIN & LAN_BASEADR<15> ;Imported pterms FB9_11 # LAN_BASEADR<6> & !A<22>.PIN # !LAN_BASEADR<6> & A<22>.PIN; LAN_ACCESS.CLK = !FCS; LAN_ACCESS.AR = !RESET; MACROCELL | 4 | 6 | AUTOCONFIG_Z2_ACCESS ATTRIBUTES | 8520496 | 0 OUTPUTMC | 50 | 13 | 4 | 13 | 3 | 13 | 9 | 13 | 8 | 13 | 7 | 13 | 0 | 9 | 17 | 9 | 15 | 9 | 14 | 13 | 5 | 3 | 17 | 3 | 16 | 3 | 15 | 3 | 14 | 9 | 12 | 9 | 8 | 9 | 6 | 9 | 3 | 13 | 1 | 13 | 15 | 13 | 11 | 11 | 15 | 11 | 2 | 11 | 5 | 13 | 13 | 4 | 8 | 3 | 0 | 3 | 13 | 4 | 7 | 9 | 0 | 9 | 2 | 9 | 5 | 9 | 7 | 9 | 11 | 9 | 13 | 9 | 16 | 11 | 1 | 11 | 3 | 11 | 4 | 11 | 6 | 11 | 7 | 11 | 13 | 11 | 14 | 11 | 16 | 11 | 17 | 13 | 6 | 13 | 10 | 13 | 12 | 13 | 14 | 13 | 17 INPUTS | 17 | CFIN | A<20>.PIN | A<19>.PIN | A<18>.PIN | A<17>.PIN | A<16>.PIN | AUTO_CONFIG_Z2_DONE<0> | A<23>.PIN | A<22>.PIN | A<21>.PIN | AUTO_CONFIG_Z2_DONE<1> | AS | RESET | UDS | LDS | DS1 | DS0 INPUTMC | 2 | 7 | 15 | 7 | 14 INPUTP | 15 | 190 | 167 | 169 | 171 | 172 | 175 | 161 | 162 | 163 | 152 | 263 | 155 | 157 | 148 | 170 EXPORTS | 1 | 4 | 7 EQ | 9 | AUTOCONFIG_Z2_ACCESS.D = !CFIN & !A<20>.PIN & A<19>.PIN & !A<18>.PIN & !A<17>.PIN & !A<16>.PIN & !AUTO_CONFIG_Z2_DONE<0> & A<23>.PIN & A<22>.PIN & A<21>.PIN # !CFIN & !A<20>.PIN & A<19>.PIN & !A<18>.PIN & !A<17>.PIN & !A<16>.PIN & !AUTO_CONFIG_Z2_DONE<1> & A<23>.PIN & A<22>.PIN & A<21>.PIN; AUTOCONFIG_Z2_ACCESS.CLK = !AS; AUTOCONFIG_Z2_ACCESS.AR = !RESET; AUTOCONFIG_Z2_ACCESS.EXP = RESET & UDS & LDS & DS1 & DS0 MACROCELL | 7 | 13 | AUTOCONFIG_Z3_ACCESS ATTRIBUTES | 8520496 | 0 OUTPUTMC | 44 | 6 | 3 | 1 | 17 | 1 | 15 | 1 | 12 | 1 | 10 | 1 | 8 | 1 | 6 | 1 | 3 | 1 | 0 | 6 | 7 | 6 | 8 | 6 | 9 | 6 | 10 | 6 | 13 | 6 | 14 | 6 | 16 | 6 | 17 | 4 | 12 | 4 | 14 | 4 | 16 | 6 | 2 | 6 | 4 | 6 | 11 | 1 | 16 | 4 | 11 | 6 | 6 | 3 | 3 | 3 | 12 | 3 | 6 | 3 | 2 | 3 | 10 | 3 | 9 | 3 | 8 | 3 | 0 | 13 | 13 | 4 | 8 | 4 | 17 | 2 | 9 | 4 | 15 | 6 | 0 | 6 | 1 | 6 | 5 | 6 | 12 | 13 | 14 INPUTS | 21 | Z3 | D<9>.PIN | D<8>.PIN | D<14>.PIN | D<13>.PIN | D<12>.PIN | D<11>.PIN | D<10>.PIN | D<15>.PIN | CFIN | A<20>.PIN | A<19>.PIN | A<18>.PIN | A<17>.PIN | A<16>.PIN | AUTO_CONFIG_DONE | A<23>.PIN | A<22>.PIN | A<21>.PIN | FCS | RESET INPUTMC | 1 | 8 | 15 INPUTP | 20 | 151 | 73 | 32 | 81 | 80 | 78 | 77 | 74 | 89 | 190 | 167 | 169 | 171 | 172 | 175 | 161 | 162 | 163 | 147 | 263 EQ | 7 | AUTOCONFIG_Z3_ACCESS.D = Z3 & D<9>.PIN & D<8>.PIN & D<14>.PIN & D<13>.PIN & D<12>.PIN & D<11>.PIN & D<10>.PIN & D<15>.PIN & !CFIN & !A<20>.PIN & !A<19>.PIN & !A<18>.PIN & !A<17>.PIN & !A<16>.PIN & !AUTO_CONFIG_DONE & !A<23>.PIN & !A<22>.PIN & !A<21>.PIN; AUTOCONFIG_Z3_ACCESS.CLK = !FCS; AUTOCONFIG_Z3_ACCESS.AR = !RESET; MACROCELL | 11 | 10 | Z3_ADR<3> ATTRIBUTES | 8520608 | 0 OUTPUTMC | 27 | 6 | 3 | 1 | 17 | 1 | 15 | 1 | 12 | 1 | 10 | 1 | 8 | 1 | 6 | 1 | 3 | 1 | 0 | 6 | 7 | 6 | 8 | 6 | 9 | 6 | 10 | 6 | 13 | 6 | 14 | 6 | 16 | 6 | 17 | 6 | 6 | 3 | 3 | 3 | 12 | 3 | 6 | 3 | 2 | 3 | 10 | 3 | 9 | 3 | 8 | 3 | 0 | 1 | 1 INPUTS | 3 | A<5> | FCS | RESET INPUTP | 3 | 91 | 147 | 263 EQ | 3 | Z3_ADR<3>.D = A<5>; Z3_ADR<3>.CLK = !FCS; Z3_ADR<3>.AP = !RESET; MACROCELL | 11 | 12 | Z3_ADR<4> ATTRIBUTES | 8520608 | 0 OUTPUTMC | 27 | 6 | 3 | 1 | 17 | 1 | 15 | 1 | 12 | 1 | 10 | 1 | 8 | 1 | 6 | 1 | 3 | 1 | 0 | 6 | 7 | 6 | 8 | 6 | 9 | 6 | 10 | 6 | 13 | 6 | 14 | 6 | 16 | 6 | 17 | 6 | 6 | 3 | 3 | 3 | 12 | 3 | 6 | 3 | 2 | 3 | 10 | 3 | 9 | 3 | 8 | 3 | 0 | 3 | 13 INPUTS | 3 | A<6> | FCS | RESET INPUTP | 3 | 98 | 147 | 263 EQ | 3 | Z3_ADR<4>.D = A<6>; Z3_ADR<4>.CLK = !FCS; Z3_ADR<4>.AP = !RESET; MACROCELL | 11 | 13 | Z3_ADR<5> ATTRIBUTES | 8520608 | 0 OUTPUTMC | 28 | 6 | 3 | 1 | 17 | 1 | 15 | 1 | 12 | 1 | 10 | 1 | 8 | 1 | 6 | 1 | 3 | 1 | 0 | 6 | 7 | 6 | 8 | 6 | 9 | 6 | 10 | 6 | 13 | 6 | 14 | 6 | 16 | 6 | 17 | 6 | 6 | 3 | 3 | 3 | 12 | 3 | 6 | 3 | 2 | 3 | 10 | 3 | 9 | 3 | 8 | 3 | 0 | 1 | 4 | 11 | 14 INPUTS | 12 | A<7> | FCS | RESET | AS | AUTO_CONFIG_Z2_DONE<0> | LDS | A<5> | A<4> | A<1> | A<6> | A<2> | AUTOCONFIG_Z2_ACCESS INPUTMC | 2 | 7 | 15 | 4 | 6 INPUTP | 10 | 100 | 147 | 263 | 152 | 157 | 91 | 97 | 107 | 98 | 101 EXPORTS | 1 | 11 | 14 EQ | 5 | Z3_ADR<5>.D = A<7>; Z3_ADR<5>.CLK = !FCS; Z3_ADR<5>.AP = !RESET; Z3_ADR<5>.EXP = !AS & AUTO_CONFIG_Z2_DONE<0> & !LDS & !A<5> & A<4> & !A<1> & !A<6> & A<2> & AUTOCONFIG_Z2_ACCESS MACROCELL | 7 | 17 | IDE_ACCESS ATTRIBUTES | 8520496 | 0 OUTPUTMC | 6 | 8 | 14 | 8 | 12 | 8 | 11 | 8 | 5 | 13 | 13 | 13 | 14 INPUTS | 7 | SHUT_UP_Z2<1> | A<16>.PIN | IDE_BASEADR<0> | EXP34_.EXP | EXP35_.EXP | AS | RESET INPUTMC | 4 | 13 | 15 | 3 | 17 | 7 | 0 | 7 | 16 INPUTP | 3 | 175 | 152 | 263 IMPORTS | 2 | 7 | 0 | 7 | 16 EQ | 23 | !IDE_ACCESS.D = SHUT_UP_Z2<1> # A<16>.PIN & !IDE_BASEADR<0> # !A<16>.PIN & IDE_BASEADR<0> ;Imported pterms FB8_1 # A<20>.PIN & !IDE_BASEADR<4> # !A<20>.PIN & IDE_BASEADR<4> # !A<19>.PIN & IDE_BASEADR<3> # IDE_BASEADR<5> & !A<21>.PIN # !IDE_BASEADR<5> & A<21>.PIN ;Imported pterms FB8_2 # IDE_BASEADR<6> & !A<22>.PIN # !IDE_BASEADR<6> & A<22>.PIN # IDE_BASEADR<7> & !A<23>.PIN ;Imported pterms FB8_17 # A<19>.PIN & !IDE_BASEADR<3> # A<18>.PIN & !IDE_BASEADR<2> # !A<18>.PIN & IDE_BASEADR<2> # A<17>.PIN & !IDE_BASEADR<1> # !A<17>.PIN & IDE_BASEADR<1> ;Imported pterms FB8_16 # !IDE_BASEADR<7> & A<23>.PIN; IDE_ACCESS.CLK = !AS; IDE_ACCESS.AR = !RESET; MACROCELL | 7 | 12 | Z3_ADR<13> ATTRIBUTES | 8520608 | 0 OUTPUTMC | 3 | 6 | 15 | 8 | 5 | 6 | 0 INPUTS | 3 | A<15>.PIN | FCS | RESET INPUTP | 3 | 139 | 147 | 263 EQ | 3 | Z3_ADR<13>.D = A<15>.PIN; Z3_ADR<13>.CLK = !FCS; Z3_ADR<13>.AP = !RESET; MACROCELL | 5 | 15 | LAN_D_INIT<1> ATTRIBUTES | 8553232 | 0 OUTPUTMC | 3 | 9 | 1 | 9 | 9 | 11 | 11 INPUTS | 4 | LAN_RST_SM_FSM_FFd3 | LAN_RST_SM_FSM_FFd1 | LAN_RST_SM_FSM_FFd2 | RESET INPUTMC | 3 | 5 | 8 | 5 | 11 | 5 | 10 INPUTP | 1 | 263 EQ | 4 | LAN_D_INIT<1>.D = LAN_RST_SM_FSM_FFd3 & !LAN_RST_SM_FSM_FFd1 # !LAN_RST_SM_FSM_FFd3 & LAN_RST_SM_FSM_FFd2; LAN_D_INIT<1>.CLK = CLK_EXT; // GCK LAN_D_INIT<1>.AR = RESET; GLOBALS | 1 | 2 | CLK_EXT MACROCELL | 5 | 14 | LAN_D_INIT<8> ATTRIBUTES | 8553232 | 0 OUTPUTMC | 3 | 9 | 16 | 11 | 9 | 9 | 13 INPUTS | 4 | LAN_RST_SM_FSM_FFd3 | LAN_RST_SM_FSM_FFd2 | LAN_RST_SM_FSM_FFd1 | RESET INPUTMC | 3 | 5 | 8 | 5 | 10 | 5 | 11 INPUTP | 1 | 263 EQ | 4 | LAN_D_INIT<8>.D = LAN_RST_SM_FSM_FFd3 & LAN_RST_SM_FSM_FFd1 # !LAN_RST_SM_FSM_FFd3 & !LAN_RST_SM_FSM_FFd2; LAN_D_INIT<8>.CLK = CLK_EXT; // GCK LAN_D_INIT<8>.AR = RESET; GLOBALS | 1 | 2 | CLK_EXT MACROCELL | 8 | 14 | IDE_ENABLE ATTRIBUTES | 8520672 | 0 OUTPUTMC | 2 | 8 | 12 | 8 | 5 INPUTS | 5 | SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF | RESET | AS | RW | IDE_ACCESS INPUTMC | 2 | 2 | 8 | 7 | 17 INPUTP | 3 | 263 | 152 | 158 EQ | 4 | IDE_ENABLE.D = Gnd; IDE_ENABLE.CLK = SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF; IDE_ENABLE.AP = !RESET; IDE_ENABLE.CE = !AS & !RW & IDE_ACCESS; MACROCELL | 10 | 17 | DQ_DATA<0> ATTRIBUTES | 8553344 | 0 OUTPUTMC | 2 | 9 | 2 | 10 | 17 INPUTS | 8 | LAN_SM_FSM_FFd1 | DQ_DATA<0> | LAN_SM_FSM_FFd4 | LAN_SM_FSM_FFd3 | LAN_SM_FSM_FFd2 | Z3_DATA<30>.EXP | CP_WE_OBUF.EXP | LAN_SM_RST INPUTMC | 8 | 12 | 4 | 10 | 17 | 14 | 3 | 0 | 10 | 0 | 1 | 10 | 0 | 10 | 16 | 6 | 0 IMPORTS | 2 | 10 | 0 | 10 | 16 EQ | 24 | DQ_DATA<0>.D = LAN_SM_FSM_FFd4 & DQ_DATA<0> # LAN_SM_FSM_FFd1 & DQ_DATA<0> # LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd2 & DQ_DATA<0> # !LAN_SM_FSM_FFd3 & LAN_SM_FSM_FFd2 & DQ_DATA<0> ;Imported pterms FB11_1 # D<8>.PIN & !LDS & DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # A<16>.PIN & UDS & LDS & DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # UDS & LDS & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 & A<8>.PIN ;Imported pterms FB11_17 # D<8>.PIN & !UDS & DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # A<16>.PIN & DQ_SWAP & !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1 # !UDS & D<0>.PIN & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # !LDS & D<0>.PIN & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # !DQ_SWAP & !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1 & A<8>.PIN; DQ_DATA<0>.CLK = CLK_EXT; // GCK DQ_DATA<0>.AP = LAN_SM_RST; GLOBALS | 1 | 2 | CLK_EXT MACROCELL | 15 | 15 | DQ_DATA<10> ATTRIBUTES | 8553344 | 0 OUTPUTMC | 2 | 9 | 16 | 15 | 15 INPUTS | 8 | LAN_SM_FSM_FFd1 | DQ_DATA<10> | LAN_SM_FSM_FFd4 | LAN_SM_FSM_FFd3 | LAN_SM_FSM_FFd2 | EXP61_.EXP | DQ_DATA<2>.EXP | LAN_SM_RST INPUTMC | 8 | 12 | 4 | 15 | 15 | 14 | 3 | 0 | 10 | 0 | 1 | 15 | 14 | 15 | 16 | 6 | 0 IMPORTS | 2 | 15 | 14 | 15 | 16 EQ | 25 | DQ_DATA<10>.D = LAN_SM_FSM_FFd4 & DQ_DATA<10> # LAN_SM_FSM_FFd1 & DQ_DATA<10> # LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd2 & DQ_DATA<10> # !LAN_SM_FSM_FFd3 & LAN_SM_FSM_FFd2 & DQ_DATA<10> ;Imported pterms FB16_15 # D<10>.PIN & !UDS & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # D<10>.PIN & !LDS & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # A<18>.PIN & !DQ_SWAP & !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1 # !UDS & D<2>.PIN & DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # DQ_SWAP & !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1 & A<10>.PIN ;Imported pterms FB16_14 # UDS & LDS & DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 & A<10>.PIN ;Imported pterms FB16_17 # !LDS & D<2>.PIN & DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # A<18>.PIN & UDS & LDS & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4; DQ_DATA<10>.CLK = CLK_EXT; // GCK DQ_DATA<10>.AP = LAN_SM_RST; GLOBALS | 1 | 2 | CLK_EXT MACROCELL | 0 | 0 | DQ_DATA<11> ATTRIBUTES | 8553344 | 0 OUTPUTMC | 2 | 11 | 9 | 0 | 0 INPUTS | 8 | LAN_SM_FSM_FFd1 | DQ_DATA<11> | LAN_SM_FSM_FFd4 | LAN_SM_FSM_FFd3 | LAN_SM_FSM_FFd2 | LAN_SM_FSM_FFd2.EXP | EXP23_.EXP | LAN_SM_RST INPUTMC | 8 | 12 | 4 | 0 | 0 | 14 | 3 | 0 | 10 | 0 | 1 | 0 | 1 | 0 | 17 | 6 | 0 IMPORTS | 2 | 0 | 1 | 0 | 17 EQ | 24 | DQ_DATA<11>.D = LAN_SM_FSM_FFd4 & DQ_DATA<11> # LAN_SM_FSM_FFd1 & DQ_DATA<11> # LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd2 & DQ_DATA<11> # !LAN_SM_FSM_FFd3 & LAN_SM_FSM_FFd2 & DQ_DATA<11> ;Imported pterms FB1_2 # !LDS & D<3>.PIN & DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # A<19>.PIN & UDS & LDS & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # UDS & LDS & DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 & A<11>.PIN ;Imported pterms FB1_18 # D<11>.PIN & !UDS & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # D<11>.PIN & !LDS & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # A<19>.PIN & !DQ_SWAP & !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1 # !UDS & D<3>.PIN & DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # DQ_SWAP & !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1 & A<11>.PIN; DQ_DATA<11>.CLK = CLK_EXT; // GCK DQ_DATA<11>.AP = LAN_SM_RST; GLOBALS | 1 | 2 | CLK_EXT MACROCELL | 0 | 15 | DQ_DATA<12> ATTRIBUTES | 8553344 | 0 OUTPUTMC | 2 | 7 | 1 | 0 | 15 INPUTS | 8 | LAN_SM_FSM_FFd1 | DQ_DATA<12> | LAN_SM_FSM_FFd4 | LAN_SM_FSM_FFd3 | LAN_SM_FSM_FFd2 | IDE_A_1_OBUF$BUF0.EXP | IDE_R_OBUF.EXP | LAN_SM_RST INPUTMC | 8 | 12 | 4 | 0 | 15 | 14 | 3 | 0 | 10 | 0 | 1 | 0 | 14 | 0 | 16 | 6 | 0 IMPORTS | 2 | 0 | 14 | 0 | 16 EQ | 24 | DQ_DATA<12>.D = LAN_SM_FSM_FFd4 & DQ_DATA<12> # LAN_SM_FSM_FFd1 & DQ_DATA<12> # LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd2 & DQ_DATA<12> # !LAN_SM_FSM_FFd3 & LAN_SM_FSM_FFd2 & DQ_DATA<12> ;Imported pterms FB1_15 # D<12>.PIN & !UDS & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # D<12>.PIN & !LDS & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # A<20>.PIN & !DQ_SWAP & !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1 # DQ_SWAP & !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1 & A<12>.PIN ;Imported pterms FB1_17 # !UDS & D<4>.PIN & DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # !LDS & D<4>.PIN & DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # A<20>.PIN & UDS & LDS & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # UDS & LDS & DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 & A<12>.PIN; DQ_DATA<12>.CLK = CLK_EXT; // GCK DQ_DATA<12>.AP = LAN_SM_RST; GLOBALS | 1 | 2 | CLK_EXT MACROCELL | 12 | 17 | DQ_DATA<13> ATTRIBUTES | 8553344 | 0 OUTPUTMC | 4 | 11 | 7 | 12 | 17 | 12 | 0 | 12 | 16 INPUTS | 11 | LAN_SM_FSM_FFd1 | DQ_DATA<13> | LAN_SM_FSM_FFd4 | LAN_SM_FSM_FFd3 | LAN_SM_FSM_FFd2 | UDS | LDS | A<22>.PIN | DQ_SWAP | EXP46_.EXP | LAN_SM_RST INPUTMC | 8 | 12 | 4 | 12 | 17 | 14 | 3 | 0 | 10 | 0 | 1 | 8 | 1 | 12 | 0 | 6 | 0 INPUTP | 3 | 155 | 157 | 162 EXPORTS | 1 | 12 | 16 IMPORTS | 1 | 12 | 0 EQ | 26 | DQ_DATA<13>.D = LAN_SM_FSM_FFd4 & DQ_DATA<13> # LAN_SM_FSM_FFd1 & DQ_DATA<13> # !LAN_SM_FSM_FFd3 & LAN_SM_FSM_FFd2 & DQ_DATA<13> ;Imported pterms FB13_1 # LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd2 & DQ_DATA<13> # D<13>.PIN & !UDS & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # D<13>.PIN & !LDS & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # A<21>.PIN & !DQ_SWAP & !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1 # DQ_SWAP & !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1 & A<13>.PIN ;Imported pterms FB13_2 # !UDS & D<5>.PIN & DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # !LDS & D<5>.PIN & DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # UDS & LDS & A<21>.PIN & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # UDS & LDS & DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 & A<13>.PIN; DQ_DATA<13>.CLK = CLK_EXT; // GCK DQ_DATA<13>.AP = LAN_SM_RST; DQ_DATA<13>.EXP = UDS & LDS & A<22>.PIN & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 GLOBALS | 1 | 2 | CLK_EXT MACROCELL | 12 | 14 | DQ_DATA<14> ATTRIBUTES | 8553344 | 0 OUTPUTMC | 4 | 7 | 2 | 12 | 14 | 12 | 15 | 12 | 13 INPUTS | 8 | LAN_SM_FSM_FFd1 | DQ_DATA<14> | RESET | LAN_WR_RST | FCS | LAN_WRL_S | EXP51_.EXP | LAN_SM_RST INPUTMC | 6 | 12 | 4 | 12 | 14 | 5 | 6 | 14 | 17 | 12 | 15 | 6 | 0 INPUTP | 2 | 263 | 147 EXPORTS | 1 | 12 | 13 IMPORTS | 1 | 12 | 15 EQ | 28 | DQ_DATA<14>.D = LAN_SM_FSM_FFd1 & DQ_DATA<14> ;Imported pterms FB13_16 # LAN_SM_FSM_FFd4 & DQ_DATA<14> # LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd2 & DQ_DATA<14> # !LAN_SM_FSM_FFd3 & LAN_SM_FSM_FFd2 & DQ_DATA<14> # A<22>.PIN & !DQ_SWAP & !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1 # DQ_SWAP & !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1 & A<14>.PIN ;Imported pterms FB13_17 # D<14>.PIN & !UDS & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # D<14>.PIN & !LDS & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # !UDS & D<6>.PIN & DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # !LDS & D<6>.PIN & DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # UDS & LDS & DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 & A<14>.PIN ;Imported pterms FB13_18 # UDS & LDS & A<22>.PIN & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4; DQ_DATA<14>.CLK = CLK_EXT; // GCK DQ_DATA<14>.AP = LAN_SM_RST; DQ_DATA<14>.EXP = !RESET & LAN_WR_RST # FCS & LAN_WR_RST # RESET & !FCS & LAN_WRL_S GLOBALS | 1 | 2 | CLK_EXT MACROCELL | 12 | 12 | DQ_DATA<15> ATTRIBUTES | 8553344 | 0 OUTPUTMC | 2 | 11 | 4 | 12 | 12 INPUTS | 8 | LAN_SM_FSM_FFd1 | DQ_DATA<15> | LAN_SM_FSM_FFd4 | LAN_SM_FSM_FFd3 | LAN_SM_FSM_FFd2 | DQ_DATA<5>.EXP | LAN_WRL_OBUF.EXP | LAN_SM_RST INPUTMC | 8 | 12 | 4 | 12 | 12 | 14 | 3 | 0 | 10 | 0 | 1 | 12 | 11 | 12 | 13 | 6 | 0 IMPORTS | 2 | 12 | 11 | 12 | 13 EQ | 24 | DQ_DATA<15>.D = LAN_SM_FSM_FFd4 & DQ_DATA<15> # LAN_SM_FSM_FFd1 & DQ_DATA<15> # LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd2 & DQ_DATA<15> # !LAN_SM_FSM_FFd3 & LAN_SM_FSM_FFd2 & DQ_DATA<15> ;Imported pterms FB13_12 # D<15>.PIN & !UDS & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # A<23>.PIN & !DQ_SWAP & !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1 # DQ_SWAP & !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1 & A<15>.PIN ;Imported pterms FB13_14 # D<15>.PIN & !LDS & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # !UDS & D<7>.PIN & DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # !LDS & D<7>.PIN & DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # UDS & LDS & A<23>.PIN & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # UDS & LDS & DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 & A<15>.PIN; DQ_DATA<15>.CLK = CLK_EXT; // GCK DQ_DATA<15>.AP = LAN_SM_RST; GLOBALS | 1 | 2 | CLK_EXT MACROCELL | 14 | 0 | DQ_DATA<1> ATTRIBUTES | 8553344 | 0 OUTPUTMC | 2 | 9 | 1 | 14 | 0 INPUTS | 8 | LAN_SM_FSM_FFd1 | DQ_DATA<1> | LAN_SM_FSM_FFd4 | LAN_SM_FSM_FFd3 | LAN_SM_FSM_FFd2 | EXP56_.EXP | LAN_WRL_S.EXP | LAN_SM_RST INPUTMC | 8 | 12 | 4 | 14 | 0 | 14 | 3 | 0 | 10 | 0 | 1 | 14 | 1 | 14 | 17 | 6 | 0 IMPORTS | 2 | 14 | 1 | 14 | 17 EQ | 24 | DQ_DATA<1>.D = LAN_SM_FSM_FFd4 & DQ_DATA<1> # LAN_SM_FSM_FFd1 & DQ_DATA<1> # LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd2 & DQ_DATA<1> # !LAN_SM_FSM_FFd3 & LAN_SM_FSM_FFd2 & DQ_DATA<1> ;Imported pterms FB15_2 # D<9>.PIN & !UDS & DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # D<9>.PIN & !LDS & DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # !LDS & D<1>.PIN & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # A<17>.PIN & UDS & LDS & DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # UDS & LDS & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 & A<9>.PIN ;Imported pterms FB15_18 # A<17>.PIN & DQ_SWAP & !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1 # !UDS & D<1>.PIN & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # !DQ_SWAP & !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1 & A<9>.PIN; DQ_DATA<1>.CLK = CLK_EXT; // GCK DQ_DATA<1>.AP = LAN_SM_RST; GLOBALS | 1 | 2 | CLK_EXT MACROCELL | 15 | 16 | DQ_DATA<2> ATTRIBUTES | 8553344 | 0 OUTPUTMC | 4 | 9 | 5 | 15 | 16 | 15 | 17 | 15 | 15 INPUTS | 11 | LAN_SM_FSM_FFd1 | DQ_DATA<2> | LAN_SM_FSM_FFd4 | LDS | D<2>.PIN | DQ_SWAP | LAN_SM_FSM_FFd3 | A<18>.PIN | UDS | EXP62_.EXP | LAN_SM_RST INPUTMC | 7 | 12 | 4 | 15 | 16 | 14 | 3 | 8 | 1 | 0 | 10 | 15 | 17 | 6 | 0 INPUTP | 4 | 157 | 71 | 171 | 155 EXPORTS | 1 | 15 | 15 IMPORTS | 1 | 15 | 17 EQ | 28 | DQ_DATA<2>.D = LAN_SM_FSM_FFd4 & DQ_DATA<2> # LAN_SM_FSM_FFd1 & DQ_DATA<2> ;Imported pterms FB16_18 # LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd2 & DQ_DATA<2> # !LAN_SM_FSM_FFd3 & LAN_SM_FSM_FFd2 & DQ_DATA<2> # D<10>.PIN & !UDS & DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # A<18>.PIN & DQ_SWAP & !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1 # !DQ_SWAP & !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1 & A<10>.PIN ;Imported pterms FB16_1 # D<10>.PIN & !LDS & DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # !UDS & D<2>.PIN & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # !LDS & D<2>.PIN & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # A<18>.PIN & UDS & LDS & DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # UDS & LDS & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 & A<10>.PIN; DQ_DATA<2>.CLK = CLK_EXT; // GCK DQ_DATA<2>.AP = LAN_SM_RST; DQ_DATA<2>.EXP = !LDS & D<2>.PIN & DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # A<18>.PIN & UDS & LDS & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 GLOBALS | 1 | 2 | CLK_EXT MACROCELL | 0 | 12 | DQ_DATA<3> ATTRIBUTES | 8553344 | 0 OUTPUTMC | 2 | 9 | 4 | 0 | 12 INPUTS | 8 | LAN_SM_FSM_FFd1 | DQ_DATA<3> | LAN_SM_FSM_FFd4 | LAN_SM_FSM_FFd3 | LAN_SM_FSM_FFd2 | IDE_A_0_OBUF$BUF0.EXP | IDE_A_2_OBUF$BUF0.EXP | LAN_SM_RST INPUTMC | 8 | 12 | 4 | 0 | 12 | 14 | 3 | 0 | 10 | 0 | 1 | 0 | 11 | 0 | 13 | 6 | 0 IMPORTS | 2 | 0 | 11 | 0 | 13 EQ | 24 | DQ_DATA<3>.D = LAN_SM_FSM_FFd4 & DQ_DATA<3> # LAN_SM_FSM_FFd1 & DQ_DATA<3> # LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd2 & DQ_DATA<3> # !LAN_SM_FSM_FFd3 & LAN_SM_FSM_FFd2 & DQ_DATA<3> ;Imported pterms FB1_12 # D<11>.PIN & !UDS & DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # D<11>.PIN & !LDS & DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # A<19>.PIN & DQ_SWAP & !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1 # !DQ_SWAP & !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1 & A<11>.PIN ;Imported pterms FB1_14 # !UDS & D<3>.PIN & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # !LDS & D<3>.PIN & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # A<19>.PIN & UDS & LDS & DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # UDS & LDS & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 & A<11>.PIN; DQ_DATA<3>.CLK = CLK_EXT; // GCK DQ_DATA<3>.AP = LAN_SM_RST; GLOBALS | 1 | 2 | CLK_EXT MACROCELL | 14 | 10 | DQ_DATA<4> ATTRIBUTES | 8553344 | 0 OUTPUTMC | 2 | 9 | 9 | 14 | 10 INPUTS | 8 | LAN_SM_FSM_FFd1 | DQ_DATA<4> | LAN_SM_FSM_FFd4 | LAN_SM_FSM_FFd3 | LAN_SM_FSM_FFd2 | DQ_DATA<7>.EXP | ROM_B_0_OBUF$BUF9.EXP | LAN_SM_RST INPUTMC | 8 | 12 | 4 | 14 | 10 | 14 | 3 | 0 | 10 | 0 | 1 | 14 | 9 | 14 | 11 | 6 | 0 IMPORTS | 2 | 14 | 9 | 14 | 11 EQ | 24 | DQ_DATA<4>.D = LAN_SM_FSM_FFd4 & DQ_DATA<4> # LAN_SM_FSM_FFd1 & DQ_DATA<4> # LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd2 & DQ_DATA<4> # !LAN_SM_FSM_FFd3 & LAN_SM_FSM_FFd2 & DQ_DATA<4> ;Imported pterms FB15_10 # D<12>.PIN & !UDS & DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # D<12>.PIN & !LDS & DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # A<20>.PIN & DQ_SWAP & !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1 # !DQ_SWAP & !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1 & A<12>.PIN ;Imported pterms FB15_12 # !UDS & D<4>.PIN & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # !LDS & D<4>.PIN & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # A<20>.PIN & UDS & LDS & DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # UDS & LDS & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 & A<12>.PIN; DQ_DATA<4>.CLK = CLK_EXT; // GCK DQ_DATA<4>.AP = LAN_SM_RST; GLOBALS | 1 | 2 | CLK_EXT MACROCELL | 12 | 11 | DQ_DATA<5> ATTRIBUTES | 8553344 | 0 OUTPUTMC | 4 | 9 | 7 | 12 | 11 | 12 | 10 | 12 | 12 INPUTS | 12 | LAN_SM_FSM_FFd1 | DQ_DATA<5> | D<15>.PIN | UDS | DQ_SWAP | LAN_SM_FSM_FFd3 | LAN_SM_FSM_FFd4 | A<23>.PIN | LAN_SM_FSM_FFd2 | A<15>.PIN | EXP50_.EXP | LAN_SM_RST INPUTMC | 8 | 12 | 4 | 12 | 11 | 8 | 1 | 0 | 10 | 14 | 3 | 0 | 1 | 12 | 10 | 6 | 0 INPUTP | 4 | 89 | 155 | 161 | 139 EXPORTS | 1 | 12 | 12 IMPORTS | 1 | 12 | 10 EQ | 31 | DQ_DATA<5>.D = LAN_SM_FSM_FFd1 & DQ_DATA<5> ;Imported pterms FB13_11 # LAN_SM_FSM_FFd4 & DQ_DATA<5> # LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd2 & DQ_DATA<5> # !LAN_SM_FSM_FFd3 & LAN_SM_FSM_FFd2 & DQ_DATA<5> # A<21>.PIN & DQ_SWAP & !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1 # !DQ_SWAP & !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1 & A<13>.PIN ;Imported pterms FB13_10 # D<13>.PIN & !UDS & DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # D<13>.PIN & !LDS & DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # !UDS & D<5>.PIN & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # !LDS & D<5>.PIN & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # UDS & LDS & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 & A<13>.PIN ;Imported pterms FB13_9 # UDS & LDS & A<21>.PIN & DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4; DQ_DATA<5>.CLK = CLK_EXT; // GCK DQ_DATA<5>.AP = LAN_SM_RST; DQ_DATA<5>.EXP = D<15>.PIN & !UDS & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # A<23>.PIN & !DQ_SWAP & !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1 # DQ_SWAP & !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1 & A<15>.PIN GLOBALS | 1 | 2 | CLK_EXT MACROCELL | 12 | 6 | DQ_DATA<6> ATTRIBUTES | 8553344 | 0 OUTPUTMC | 2 | 9 | 11 | 12 | 6 INPUTS | 7 | LAN_SM_FSM_FFd1 | DQ_DATA<6> | LAN_SM_FSM_FFd4 | LAN_SM_FSM_FFd3 | LAN_SM_FSM_FFd2 | EXP48_.EXP | LAN_SM_RST INPUTMC | 7 | 12 | 4 | 12 | 6 | 14 | 3 | 0 | 10 | 0 | 1 | 12 | 5 | 6 | 0 IMPORTS | 1 | 12 | 5 EQ | 24 | DQ_DATA<6>.D = LAN_SM_FSM_FFd4 & DQ_DATA<6> # LAN_SM_FSM_FFd1 & DQ_DATA<6> # LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd2 & DQ_DATA<6> # !LAN_SM_FSM_FFd3 & LAN_SM_FSM_FFd2 & DQ_DATA<6> ;Imported pterms FB13_6 # D<14>.PIN & !UDS & DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # D<14>.PIN & !LDS & DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # !UDS & D<6>.PIN & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # A<22>.PIN & DQ_SWAP & !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1 # !DQ_SWAP & !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1 & A<14>.PIN ;Imported pterms FB13_5 # !LDS & D<6>.PIN & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # UDS & LDS & A<22>.PIN & DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # UDS & LDS & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 & A<14>.PIN; DQ_DATA<6>.CLK = CLK_EXT; // GCK DQ_DATA<6>.AP = LAN_SM_RST; GLOBALS | 1 | 2 | CLK_EXT MACROCELL | 14 | 9 | DQ_DATA<7> ATTRIBUTES | 8553344 | 0 OUTPUTMC | 3 | 9 | 10 | 14 | 8 | 14 | 10 INPUTS | 12 | D<12>.PIN | UDS | DQ_SWAP | LAN_SM_FSM_FFd3 | LAN_SM_FSM_FFd4 | LDS | A<20>.PIN | LAN_SM_FSM_FFd2 | LAN_SM_FSM_FFd1 | A<12>.PIN | EXP59_.EXP | LAN_SM_RST INPUTMC | 7 | 8 | 1 | 0 | 10 | 14 | 3 | 0 | 1 | 12 | 4 | 14 | 8 | 6 | 0 INPUTP | 5 | 78 | 155 | 157 | 167 | 115 EXPORTS | 1 | 14 | 10 IMPORTS | 1 | 14 | 8 EQ | 33 | DQ_DATA<7>.D = ;Imported pterms FB15_9 LAN_SM_FSM_FFd4 & DQ_DATA<7> # LAN_SM_FSM_FFd1 & DQ_DATA<7> # LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd2 & DQ_DATA<7> # !LAN_SM_FSM_FFd3 & LAN_SM_FSM_FFd2 & DQ_DATA<7> # !DQ_SWAP & !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1 & A<15>.PIN ;Imported pterms FB15_8 # D<15>.PIN & !UDS & DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # D<15>.PIN & !LDS & DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # !UDS & D<7>.PIN & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # !LDS & D<7>.PIN & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # A<23>.PIN & DQ_SWAP & !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1 ;Imported pterms FB15_7 # UDS & LDS & A<23>.PIN & DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # UDS & LDS & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 & A<15>.PIN; DQ_DATA<7>.CLK = CLK_EXT; // GCK DQ_DATA<7>.AP = LAN_SM_RST; DQ_DATA<7>.EXP = D<12>.PIN & !UDS & DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # D<12>.PIN & !LDS & DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # A<20>.PIN & DQ_SWAP & !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1 # !DQ_SWAP & !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1 & A<12>.PIN GLOBALS | 1 | 2 | CLK_EXT MACROCELL | 10 | 15 | DQ_DATA<8> ATTRIBUTES | 8553344 | 0 OUTPUTMC | 4 | 9 | 13 | 10 | 15 | 10 | 14 | 10 | 16 INPUTS | 10 | LAN_SM_FSM_FFd1 | DQ_DATA<8> | LAN_SM_FSM_FFd4 | LAN_SM_FSM_FFd3 | LAN_SM_FSM_FFd2 | AS | CP_WE_S | CP_WE_QUIRK | EXP41_.EXP | LAN_SM_RST INPUTMC | 9 | 12 | 4 | 10 | 15 | 14 | 3 | 0 | 10 | 0 | 1 | 11 | 8 | 2 | 11 | 10 | 14 | 6 | 0 INPUTP | 1 | 152 EXPORTS | 1 | 10 | 16 IMPORTS | 1 | 10 | 14 EQ | 25 | DQ_DATA<8>.D = LAN_SM_FSM_FFd4 & DQ_DATA<8> # LAN_SM_FSM_FFd1 & DQ_DATA<8> # !LAN_SM_FSM_FFd3 & LAN_SM_FSM_FFd2 & DQ_DATA<8> ;Imported pterms FB11_15 # LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd2 & DQ_DATA<8> # A<16>.PIN & !DQ_SWAP & !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1 # !UDS & D<0>.PIN & DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # !LDS & D<0>.PIN & DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # DQ_SWAP & !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1 & A<8>.PIN ;Imported pterms FB11_14 # D<8>.PIN & !UDS & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # D<8>.PIN & !LDS & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # A<16>.PIN & UDS & LDS & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # UDS & LDS & DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 & A<8>.PIN; DQ_DATA<8>.CLK = CLK_EXT; // GCK DQ_DATA<8>.AP = LAN_SM_RST; DQ_DATA<8>.EXP = !AS & !CP_WE_S & CP_WE_QUIRK GLOBALS | 1 | 2 | CLK_EXT MACROCELL | 14 | 4 | DQ_DATA<9> ATTRIBUTES | 8553344 | 0 OUTPUTMC | 2 | 11 | 11 | 14 | 4 INPUTS | 8 | LAN_SM_FSM_FFd1 | DQ_DATA<9> | LAN_SM_FSM_FFd4 | LAN_SM_FSM_FFd3 | LAN_SM_FSM_FFd2 | LAN_SM_FSM_FFd4.EXP | EXP57_.EXP | LAN_SM_RST INPUTMC | 8 | 12 | 4 | 14 | 4 | 14 | 3 | 0 | 10 | 0 | 1 | 14 | 3 | 14 | 5 | 6 | 0 IMPORTS | 2 | 14 | 3 | 14 | 5 EQ | 24 | DQ_DATA<9>.D = LAN_SM_FSM_FFd4 & DQ_DATA<9> # LAN_SM_FSM_FFd1 & DQ_DATA<9> # LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd2 & DQ_DATA<9> # !LAN_SM_FSM_FFd3 & LAN_SM_FSM_FFd2 & DQ_DATA<9> ;Imported pterms FB15_4 # A<17>.PIN & !DQ_SWAP & !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1 # !UDS & D<1>.PIN & DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # DQ_SWAP & !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1 & A<9>.PIN ;Imported pterms FB15_6 # D<9>.PIN & !UDS & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # D<9>.PIN & !LDS & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # !LDS & D<1>.PIN & DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # A<17>.PIN & UDS & LDS & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # UDS & LDS & DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 & A<9>.PIN; DQ_DATA<9>.CLK = CLK_EXT; // GCK DQ_DATA<9>.AP = LAN_SM_RST; GLOBALS | 1 | 2 | CLK_EXT MACROCELL | 5 | 6 | LAN_WR_RST ATTRIBUTES | 8553232 | 0 OUTPUTMC | 2 | 7 | 4 | 12 | 14 INPUTS | 4 | LAN_RST_SM_FSM_FFd3 | LAN_RST_SM_FSM_FFd2 | LAN_RST_SM_FSM_FFd1 | RESET INPUTMC | 3 | 5 | 8 | 5 | 10 | 5 | 11 INPUTP | 1 | 263 EQ | 6 | LAN_WR_RST.D = LAN_RST_SM_FSM_FFd3 & LAN_RST_SM_FSM_FFd2 & !LAN_RST_SM_FSM_FFd1 # LAN_RST_SM_FSM_FFd3 & !LAN_RST_SM_FSM_FFd2 & LAN_RST_SM_FSM_FFd1; LAN_WR_RST.CLK = CLK_EXT; // GCK LAN_WR_RST.AR = RESET; GLOBALS | 1 | 2 | CLK_EXT MACROCELL | 13 | 1 | SHUT_UP_Z2<0> ATTRIBUTES | 4326308 | 0 OUTPUTMC | 2 | 13 | 1 | 4 | 1 INPUTS | 15 | AS | AUTO_CONFIG_Z2_DONE<0> | UDS | A<5> | A<4> | A<1> | RW | A<6> | A<3> | A<2> | AUTOCONFIG_Z2_ACCESS | SHUT_UP_Z2<0> | LDS | SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF | RESET INPUTMC | 4 | 7 | 15 | 4 | 6 | 13 | 1 | 2 | 8 INPUTP | 11 | 152 | 155 | 91 | 97 | 107 | 158 | 98 | 99 | 101 | 157 | 263 EQ | 8 | SHUT_UP_Z2<0>.T = !AS & !AUTO_CONFIG_Z2_DONE<0> & !UDS & !A<5> & !A<4> & !A<1> & !RW & A<6> & A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS & SHUT_UP_Z2<0> # !AS & !AUTO_CONFIG_Z2_DONE<0> & !LDS & !A<5> & !A<4> & !A<1> & !RW & A<6> & A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS & SHUT_UP_Z2<0>; SHUT_UP_Z2<0>.CLK = SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF; SHUT_UP_Z2<0>.AP = !RESET; MACROCELL | 13 | 15 | SHUT_UP_Z2<1> ATTRIBUTES | 4326308 | 0 OUTPUTMC | 2 | 7 | 17 | 13 | 15 INPUTS | 16 | AS | AUTO_CONFIG_Z2_DONE<0> | AUTO_CONFIG_Z2_DONE<1> | UDS | A<5> | A<4> | A<1> | RW | A<6> | A<3> | A<2> | AUTOCONFIG_Z2_ACCESS | SHUT_UP_Z2<1> | LDS | SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF | RESET INPUTMC | 5 | 7 | 15 | 7 | 14 | 4 | 6 | 13 | 15 | 2 | 8 INPUTP | 11 | 152 | 155 | 91 | 97 | 107 | 158 | 98 | 99 | 101 | 157 | 263 EQ | 8 | SHUT_UP_Z2<1>.T = !AS & AUTO_CONFIG_Z2_DONE<0> & !AUTO_CONFIG_Z2_DONE<1> & !UDS & !A<5> & !A<4> & !A<1> & !RW & A<6> & A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS & SHUT_UP_Z2<1> # !AS & AUTO_CONFIG_Z2_DONE<0> & !AUTO_CONFIG_Z2_DONE<1> & !LDS & !A<5> & !A<4> & !A<1> & !RW & A<6> & A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS & SHUT_UP_Z2<1>; SHUT_UP_Z2<1>.CLK = SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF; SHUT_UP_Z2<1>.AP = !RESET; MACROCELL | 13 | 11 | D_Z2_OUT<0> ATTRIBUTES | 8520612 | 0 OUTPUTMC | 1 | 4 | 16 INPUTS | 13 | AS | UDS | A<5> | A<4> | A<6> | A<3> | A<2> | AUTOCONFIG_Z2_ACCESS | A<1> | CFOUT_OBUF.EXP | EXP54_.EXP | SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF | RESET INPUTMC | 4 | 4 | 6 | 13 | 10 | 13 | 12 | 2 | 8 INPUTP | 9 | 152 | 155 | 91 | 97 | 98 | 99 | 101 | 107 | 263 IMPORTS | 2 | 13 | 10 | 13 | 12 EQ | 35 | !D_Z2_OUT<0>.D = !AS & !UDS & A<5> & !A<4> & !A<6> & !A<3> & A<2> & AUTOCONFIG_Z2_ACCESS # !AS & !UDS & !A<5> & A<4> & A<1> & !A<6> & A<3> & AUTOCONFIG_Z2_ACCESS # !AS & !UDS & !A<5> & !A<4> & A<6> & !A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS ;Imported pterms FB14_11 # !AS & !UDS & !A<5> & A<4> & !A<6> & A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS # !AS & !LDS & A<5> & !A<4> & !A<6> & !A<3> & A<2> & AUTOCONFIG_Z2_ACCESS # !AS & !LDS & !A<5> & A<4> & A<1> & !A<6> & A<3> & AUTOCONFIG_Z2_ACCESS # !AS & !LDS & !A<5> & !A<4> & A<6> & !A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS ;Imported pterms FB14_13 # !AS & !LDS & !A<5> & A<4> & !A<6> & A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS # !AS & !AUTO_CONFIG_Z2_DONE<0> & !UDS & !A<5> & !A<4> & !A<1> & !A<6> & !A<3> & AUTOCONFIG_Z2_ACCESS # !AS & !AUTO_CONFIG_Z2_DONE<0> & !UDS & !A<5> & !A<1> & !A<6> & !A<3> & A<2> & AUTOCONFIG_Z2_ACCESS # !AS & !AUTO_CONFIG_Z2_DONE<0> & !LDS & !A<5> & !A<4> & !A<1> & !A<6> & !A<3> & AUTOCONFIG_Z2_ACCESS # !AS & !AUTO_CONFIG_Z2_DONE<0> & !LDS & !A<5> & !A<1> & !A<6> & !A<3> & A<2> & AUTOCONFIG_Z2_ACCESS ;Imported pterms FB14_14 # !AS & AUTO_CONFIG_Z2_DONE<0> & !AUTO_CONFIG_Z2_DONE<1> & !UDS & A<5> & !A<4> & A<1> & !A<6> & A<2> & AUTOCONFIG_Z2_ACCESS # !AS & AUTO_CONFIG_Z2_DONE<0> & !AUTO_CONFIG_Z2_DONE<1> & !LDS & A<5> & !A<4> & A<1> & !A<6> & A<2> & AUTOCONFIG_Z2_ACCESS; D_Z2_OUT<0>.CLK = SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF; D_Z2_OUT<0>.AP = !RESET; MACROCELL | 11 | 15 | D_Z2_OUT<1> ATTRIBUTES | 8520612 | 0 OUTPUTMC | 1 | 6 | 2 INPUTS | 14 | AS | UDS | A<5> | A<4> | A<3> | A<2> | AUTOCONFIG_Z2_ACCESS | LDS | A<1> | A<6> | EXP44_.EXP | SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF | RESET | EXP45_.EXP INPUTMC | 4 | 4 | 6 | 11 | 14 | 2 | 8 | 11 | 16 INPUTP | 10 | 152 | 155 | 91 | 97 | 99 | 101 | 157 | 107 | 98 | 263 IMPORTS | 2 | 11 | 14 | 11 | 16 EQ | 38 | !D_Z2_OUT<1>.D = !AS & !UDS & !A<5> & !A<4> & !A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS # !AS & !LDS & !A<5> & !A<4> & !A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS # !AS & !UDS & !A<5> & A<4> & !A<1> & !A<6> & A<3> & AUTOCONFIG_Z2_ACCESS ;Imported pterms FB12_15 # !AS & !UDS & !A<5> & A<4> & !A<6> & A<3> & A<2> & AUTOCONFIG_Z2_ACCESS # !AS & !LDS & !A<5> & A<4> & !A<1> & !A<6> & A<3> & AUTOCONFIG_Z2_ACCESS # !AS & !LDS & !A<5> & A<4> & !A<6> & A<3> & A<2> & AUTOCONFIG_Z2_ACCESS # !AS & AUTO_CONFIG_Z2_DONE<0> & !UDS & !A<5> & !A<4> & A<1> & !A<6> & !A<3> & AUTOCONFIG_Z2_ACCESS # !AS & !AUTO_CONFIG_Z2_DONE<0> & !UDS & !A<5> & !A<4> & !A<1> & !A<6> & !A<3> & AUTOCONFIG_Z2_ACCESS ;Imported pterms FB12_14 # !AS & AUTO_CONFIG_Z2_DONE<0> & !LDS & !A<5> & A<4> & !A<1> & !A<6> & A<2> & AUTOCONFIG_Z2_ACCESS ;Imported pterms FB12_17 # !AS & AUTO_CONFIG_Z2_DONE<0> & !UDS & !A<5> & A<4> & !A<1> & !A<6> & A<2> & AUTOCONFIG_Z2_ACCESS # !AS & AUTO_CONFIG_Z2_DONE<0> & !LDS & !A<5> & !A<4> & A<1> & !A<6> & !A<3> & AUTOCONFIG_Z2_ACCESS # !AS & !AUTO_CONFIG_Z2_DONE<0> & !UDS & !A<5> & A<1> & !A<6> & !A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS # !AS & !AUTO_CONFIG_Z2_DONE<0> & !LDS & !A<5> & !A<4> & !A<1> & !A<6> & !A<3> & AUTOCONFIG_Z2_ACCESS # !AS & !UDS & A<5> & !A<4> & !A<1> & !A<6> & !A<3> & A<2> & AUTOCONFIG_Z2_ACCESS ;Imported pterms FB12_18 # !AS & !AUTO_CONFIG_Z2_DONE<0> & !LDS & !A<5> & A<1> & !A<6> & !A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS # !AS & !LDS & A<5> & !A<4> & !A<1> & !A<6> & !A<3> & A<2> & AUTOCONFIG_Z2_ACCESS; D_Z2_OUT<1>.CLK = SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF; D_Z2_OUT<1>.AP = !RESET; MACROCELL | 11 | 2 | D_Z2_OUT<2> ATTRIBUTES | 8520612 | 0 OUTPUTMC | 1 | 6 | 4 INPUTS | 13 | AS | UDS | A<5> | A<4> | A<6> | A<3> | A<2> | AUTOCONFIG_Z2_ACCESS | A<1> | ROM_B_0_OBUF$BUF4.EXP | EXP42_.EXP | SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF | RESET INPUTMC | 4 | 4 | 6 | 11 | 1 | 11 | 3 | 2 | 8 INPUTP | 9 | 152 | 155 | 91 | 97 | 98 | 99 | 101 | 107 | 263 IMPORTS | 2 | 11 | 1 | 11 | 3 EQ | 28 | !D_Z2_OUT<2>.D = !AS & !UDS & !A<5> & !A<4> & A<1> & !A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS # !AS & !UDS & !A<5> & !A<4> & A<6> & !A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS # !AS & !UDS & !A<4> & A<1> & !A<6> & !A<3> & A<2> & AUTOCONFIG_Z2_ACCESS ;Imported pterms FB12_2 # !AS & !UDS & !A<5> & A<1> & !A<6> & !A<3> & A<2> & AUTOCONFIG_Z2_ACCESS # !AS & !LDS & !A<5> & !A<4> & A<1> & !A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS # !AS & !LDS & !A<5> & !A<4> & A<6> & !A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS # !AS & !LDS & !A<4> & A<1> & !A<6> & !A<3> & A<2> & AUTOCONFIG_Z2_ACCESS ;Imported pterms FB12_4 # !AS & !LDS & !A<5> & A<1> & !A<6> & !A<3> & A<2> & AUTOCONFIG_Z2_ACCESS # !AS & !AUTO_CONFIG_Z2_DONE<0> & !UDS & !A<5> & !A<4> & !A<6> & !A<3> & A<2> & AUTOCONFIG_Z2_ACCESS # !AS & !AUTO_CONFIG_Z2_DONE<0> & !LDS & !A<5> & !A<4> & !A<6> & !A<3> & A<2> & AUTOCONFIG_Z2_ACCESS # !AS & !UDS & !A<5> & A<4> & !A<1> & !A<6> & A<3> & A<2> & AUTOCONFIG_Z2_ACCESS # !AS & !LDS & !A<5> & A<4> & !A<1> & !A<6> & A<3> & A<2> & AUTOCONFIG_Z2_ACCESS; D_Z2_OUT<2>.CLK = SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF; D_Z2_OUT<2>.AP = !RESET; MACROCELL | 11 | 5 | D_Z2_OUT<3> ATTRIBUTES | 8520612 | 0 OUTPUTMC | 1 | 6 | 11 INPUTS | 14 | AS | UDS | A<5> | A<1> | A<6> | A<3> | A<2> | AUTOCONFIG_Z2_ACCESS | LDS | A<4> | DQ_15_IOBUFE.EXP | SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF | RESET | EXP43_.EXP INPUTMC | 4 | 4 | 6 | 11 | 4 | 2 | 8 | 11 | 6 INPUTP | 10 | 152 | 155 | 91 | 107 | 98 | 99 | 101 | 157 | 97 | 263 IMPORTS | 2 | 11 | 4 | 11 | 6 EQ | 29 | !D_Z2_OUT<3>.D = !AS & !UDS & !A<5> & !A<4> & A<6> & !A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS # !AS & !UDS & !A<5> & A<1> & !A<6> & !A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS # !AS & !LDS & !A<5> & A<1> & !A<6> & !A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS ;Imported pterms FB12_5 # !AS & !AUTO_CONFIG_Z2_DONE<0> & !UDS & !A<5> & A<1> & !A<6> & !A<3> & AUTOCONFIG_Z2_ACCESS # !AS & !UDS & !A<5> & A<4> & A<1> & !A<6> & A<2> & AUTOCONFIG_Z2_ACCESS # !AS & !LDS & !A<5> & !A<4> & A<6> & !A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS ;Imported pterms FB12_7 # !AS & !AUTO_CONFIG_Z2_DONE<0> & !LDS & !A<5> & A<1> & !A<6> & !A<3> & AUTOCONFIG_Z2_ACCESS # !AS & !LDS & !A<5> & A<4> & A<1> & !A<6> & A<2> & AUTOCONFIG_Z2_ACCESS # !AS & !UDS & A<5> & !A<4> & !A<1> & !A<6> & !A<3> & A<2> & AUTOCONFIG_Z2_ACCESS # !AS & !UDS & !A<5> & A<4> & !A<1> & !A<6> & A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS # !AS & !LDS & A<5> & !A<4> & !A<1> & !A<6> & !A<3> & A<2> & AUTOCONFIG_Z2_ACCESS ;Imported pterms FB12_8 # !AS & !LDS & !A<5> & A<4> & !A<1> & !A<6> & A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS; D_Z2_OUT<3>.CLK = SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF; D_Z2_OUT<3>.AP = !RESET; MACROCELL | 8 | 12 | IDE_R_S ATTRIBUTES | 8520608 | 0 OUTPUTMC | 1 | 0 | 16 INPUTS | 6 | AS | RW | IDE_ACCESS | IDE_ENABLE | SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF | RESET INPUTMC | 3 | 7 | 17 | 8 | 14 | 2 | 8 INPUTP | 3 | 152 | 158 | 263 EQ | 3 | !IDE_R_S.D = !AS & RW & IDE_ACCESS & !IDE_ENABLE; IDE_R_S.CLK = SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF; IDE_R_S.AP = !RESET; MACROCELL | 8 | 11 | IDE_W_S ATTRIBUTES | 8520608 | 0 OUTPUTMC | 2 | 2 | 2 | 8 | 10 INPUTS | 8 | AS | RW | IDE_ACCESS | SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF | RESET | DQ_SWAP | DQ<8>.PIN | DQ<0>.PIN INPUTMC | 3 | 7 | 17 | 2 | 8 | 8 | 1 INPUTP | 5 | 152 | 158 | 263 | 231 | 217 EXPORTS | 1 | 8 | 10 EQ | 5 | !IDE_W_S.D = !AS & !RW & IDE_ACCESS; IDE_W_S.CLK = SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF; IDE_W_S.AP = !RESET; IDE_W_S.EXP = DQ_SWAP & DQ<8>.PIN # !DQ_SWAP & DQ<0>.PIN MACROCELL | 8 | 5 | ROM_OE_S ATTRIBUTES | 8520608 | 0 OUTPUTMC | 2 | 4 | 4 | 8 | 6 INPUTS | 9 | AS | RW | IDE_ACCESS | IDE_ENABLE | SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF | RESET | FCS | LAN_ACCESS | Z3_ADR<13> INPUTMC | 5 | 7 | 17 | 8 | 14 | 2 | 8 | 8 | 8 | 7 | 12 INPUTP | 4 | 152 | 158 | 263 | 147 EXPORTS | 1 | 8 | 6 EQ | 4 | !ROM_OE_S.D = !AS & RW & IDE_ACCESS & IDE_ENABLE; ROM_OE_S.CLK = SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF; ROM_OE_S.AP = !RESET; ROM_OE_S.EXP = !FCS & LAN_ACCESS & Z3_ADR<13> MACROCELL | 6 | 6 | SHUT_UP ATTRIBUTES | 8553408 | 0 OUTPUTMC | 3 | 8 | 1 | 8 | 8 | 6 | 5 INPUTS | 17 | RESET | UDS | FCS | RW | Z3_ADR<2> | Z3_ADR_1 | Z3_ADR_0 | Z3_ADR<6> | AUTOCONFIG_Z3_ACCESS | Z3_ADR<3> | Z3_ADR<4> | Z3_ADR<5> | LDS | LAN_ACCESS | D_OUT<6> | DS1 | DS0 INPUTMC | 10 | 9 | 0 | 11 | 0 | 11 | 17 | 2 | 16 | 7 | 13 | 11 | 10 | 11 | 12 | 11 | 13 | 8 | 8 | 3 | 8 INPUTP | 7 | 263 | 155 | 147 | 158 | 157 | 148 | 170 EXPORTS | 1 | 6 | 5 EQ | 12 | SHUT_UP.D = Gnd; SHUT_UP.CLK = CLK_EXT; // GCK SHUT_UP.AP = !RESET; SHUT_UP.CE = !UDS & !FCS & !RW & !Z3_ADR<2> & !Z3_ADR_1 & Z3_ADR_0 & !Z3_ADR<6> & AUTOCONFIG_Z3_ACCESS & !Z3_ADR<3> & Z3_ADR<4> & !Z3_ADR<5>; SHUT_UP.EXP = !LDS & !FCS & RW & !LAN_ACCESS & AUTOCONFIG_Z3_ACCESS & D_OUT<6> # !DS1 & !FCS & RW & !LAN_ACCESS & AUTOCONFIG_Z3_ACCESS & D_OUT<6> # !DS0 & !FCS & RW & !LAN_ACCESS & AUTOCONFIG_Z3_ACCESS & D_OUT<6> GLOBALS | 1 | 2 | CLK_EXT MACROCELL | 4 | 5 | Z3_ADR<10> ATTRIBUTES | 8520608 | 0 OUTPUTMC | 1 | 5 | 7 INPUTS | 3 | A<12>.PIN | FCS | RESET INPUTP | 3 | 115 | 147 | 263 EQ | 3 | Z3_ADR<10>.D = A<12>.PIN; Z3_ADR<10>.CLK = !FCS; Z3_ADR<10>.AP = !RESET; MACROCELL | 8 | 4 | Z3_ADR<11> ATTRIBUTES | 8520608 | 0 OUTPUTMC | 2 | 5 | 2 | 8 | 3 INPUTS | 4 | A<13>.PIN | FCS | RESET | A<14>.PIN INPUTP | 4 | 123 | 147 | 263 | 125 EXPORTS | 1 | 8 | 3 EQ | 4 | Z3_ADR<11>.D = A<13>.PIN; Z3_ADR<11>.CLK = !FCS; Z3_ADR<11>.AP = !RESET; Z3_ADR<11>.EXP = A<14>.PIN MACROCELL | 8 | 3 | Z3_ADR<12> ATTRIBUTES | 8520608 | 0 OUTPUTMC | 2 | 5 | 4 | 8 | 2 INPUTS | 7 | D<13>.PIN | FCS | RESET | LAN_BASEADR<13> | LAN_BASEADR<6> | A<22>.PIN | Z3_ADR<11>.EXP INPUTMC | 3 | 1 | 8 | 6 | 13 | 8 | 4 INPUTP | 4 | 80 | 147 | 263 | 162 EXPORTS | 1 | 8 | 2 IMPORTS | 1 | 8 | 4 EQ | 7 | Z3_ADR<12>.D = ;Imported pterms FB9_5 A<14>.PIN; Z3_ADR<12>.CLK = !FCS; Z3_ADR<12>.AP = !RESET; Z3_ADR<12>.EXP = !D<13>.PIN & LAN_BASEADR<13> # LAN_BASEADR<6> & !A<22>.PIN # !LAN_BASEADR<6> & A<22>.PIN MACROCELL | 2 | 15 | Z3_ADR<7> ATTRIBUTES | 8520608 | 0 OUTPUTMC | 1 | 5 | 9 INPUTS | 3 | A<9>.PIN | FCS | RESET INPUTP | 3 | 108 | 147 | 263 EQ | 3 | Z3_ADR<7>.D = A<9>.PIN; Z3_ADR<7>.CLK = !FCS; Z3_ADR<7>.AP = !RESET; MACROCELL | 2 | 14 | Z3_ADR<8> ATTRIBUTES | 8520608 | 0 OUTPUTMC | 1 | 5 | 13 INPUTS | 3 | A<10>.PIN | FCS | RESET INPUTP | 3 | 112 | 147 | 263 EQ | 3 | Z3_ADR<8>.D = A<10>.PIN; Z3_ADR<8>.CLK = !FCS; Z3_ADR<8>.AP = !RESET; MACROCELL | 2 | 12 | Z3_ADR<9> ATTRIBUTES | 8520608 | 0 OUTPUTMC | 1 | 5 | 5 INPUTS | 3 | A<11>.PIN | FCS | RESET INPUTP | 3 | 114 | 147 | 263 EQ | 3 | Z3_ADR<9>.D = A<11>.PIN; Z3_ADR<9>.CLK = !FCS; Z3_ADR<9>.AP = !RESET; MACROCELL | 8 | 6 | CONFIG_READY ATTRIBUTES | 8553232 | 0 OUTPUTMC | 2 | 2 | 9 | 8 | 7 INPUTS | 6 | D<8>.PIN | LAN_BASEADR<8> | D<13>.PIN | RESET | LAN_BASEADR<13> | ROM_OE_S.EXP INPUTMC | 3 | 6 | 16 | 1 | 8 | 8 | 5 INPUTP | 3 | 32 | 80 | 263 EXPORTS | 1 | 8 | 7 IMPORTS | 1 | 8 | 5 EQ | 8 | CONFIG_READY.D = ;Imported pterms FB9_6 !FCS & LAN_ACCESS & Z3_ADR<13>; CONFIG_READY.CLK = CLK_EXT; // GCK CONFIG_READY.AR = !RESET; CONFIG_READY.EXP = D<8>.PIN & !LAN_BASEADR<8> # !D<8>.PIN & LAN_BASEADR<8> # D<13>.PIN & !LAN_BASEADR<13> # !D<13>.PIN & LAN_BASEADR<13> GLOBALS | 1 | 2 | CLK_EXT MACROCELL | 3 | 3 | D_OUT<0> ATTRIBUTES | 8553348 | 0 OUTPUTMC | 1 | 1 | 16 INPUTS | 10 | UDS | FCS | Z3_ADR<2> | Z3_ADR_1 | Z3_ADR_0 | AUTOCONFIG_Z3_ACCESS | Z3_ADR<3> | Z3_ADR<4> | Z3_ADR<5> | RESET INPUTMC | 7 | 9 | 0 | 11 | 0 | 11 | 17 | 7 | 13 | 11 | 10 | 11 | 12 | 11 | 13 INPUTP | 3 | 155 | 147 | 263 EQ | 4 | !D_OUT<0>.D = !UDS & !FCS & !Z3_ADR<2> & !Z3_ADR_1 & Z3_ADR_0 & AUTOCONFIG_Z3_ACCESS & !Z3_ADR<3> & !Z3_ADR<4> & !Z3_ADR<5>; D_OUT<0>.CLK = CLK_EXT; // GCK D_OUT<0>.AP = !RESET; GLOBALS | 1 | 2 | CLK_EXT MACROCELL | 3 | 12 | D_OUT<1> ATTRIBUTES | 8553348 | 0 OUTPUTMC | 1 | 4 | 11 INPUTS | 10 | UDS | FCS | Z3_ADR<2> | Z3_ADR_1 | AUTOCONFIG_Z3_ACCESS | Z3_ADR<3> | Z3_ADR<4> | Z3_ADR<5> | Z3_ADR_0 | RESET INPUTMC | 7 | 9 | 0 | 11 | 0 | 7 | 13 | 11 | 10 | 11 | 12 | 11 | 13 | 11 | 17 INPUTP | 3 | 155 | 147 | 263 EQ | 8 | !D_OUT<1>.D = !UDS & !FCS & !Z3_ADR<2> & !Z3_ADR_1 & AUTOCONFIG_Z3_ACCESS & !Z3_ADR<3> & !Z3_ADR<4> & !Z3_ADR<5> # !UDS & !FCS & !Z3_ADR<2> & !Z3_ADR_0 & AUTOCONFIG_Z3_ACCESS & !Z3_ADR<3> & !Z3_ADR<4> & !Z3_ADR<5> # !UDS & !FCS & !Z3_ADR_1 & !Z3_ADR_0 & AUTOCONFIG_Z3_ACCESS & !Z3_ADR<3> & !Z3_ADR<4> & !Z3_ADR<5>; D_OUT<1>.CLK = CLK_EXT; // GCK D_OUT<1>.AP = !RESET; GLOBALS | 1 | 2 | CLK_EXT MACROCELL | 3 | 6 | D_OUT<2> ATTRIBUTES | 8553348 | 0 OUTPUTMC | 1 | 4 | 12 INPUTS | 10 | UDS | FCS | Z3_ADR<2> | Z3_ADR_1 | Z3_ADR_0 | AUTOCONFIG_Z3_ACCESS | Z3_ADR<3> | Z3_ADR<4> | Z3_ADR<5> | RESET INPUTMC | 7 | 9 | 0 | 11 | 0 | 11 | 17 | 7 | 13 | 11 | 10 | 11 | 12 | 11 | 13 INPUTP | 3 | 155 | 147 | 263 EQ | 6 | !D_OUT<2>.D = !UDS & !FCS & Z3_ADR<2> & !Z3_ADR_1 & Z3_ADR_0 & AUTOCONFIG_Z3_ACCESS & !Z3_ADR<3> & !Z3_ADR<4> & !Z3_ADR<5> # !UDS & !FCS & !Z3_ADR<2> & !Z3_ADR_1 & !Z3_ADR_0 & AUTOCONFIG_Z3_ACCESS & !Z3_ADR<3> & !Z3_ADR<4> & !Z3_ADR<5>; D_OUT<2>.CLK = CLK_EXT; // GCK D_OUT<2>.AP = !RESET; GLOBALS | 1 | 2 | CLK_EXT MACROCELL | 3 | 2 | D_OUT<3> ATTRIBUTES | 8553348 | 0 OUTPUTMC | 1 | 4 | 14 INPUTS | 8 | UDS | FCS | Z3_ADR_1 | AUTOCONFIG_Z3_ACCESS | Z3_ADR<3> | Z3_ADR<4> | Z3_ADR<5> | RESET INPUTMC | 5 | 11 | 0 | 7 | 13 | 11 | 10 | 11 | 12 | 11 | 13 INPUTP | 3 | 155 | 147 | 263 EQ | 4 | !D_OUT<3>.D = !UDS & !FCS & !Z3_ADR_1 & AUTOCONFIG_Z3_ACCESS & !Z3_ADR<3> & !Z3_ADR<4> & !Z3_ADR<5>; D_OUT<3>.CLK = CLK_EXT; // GCK D_OUT<3>.AP = !RESET; GLOBALS | 1 | 2 | CLK_EXT MACROCELL | 3 | 10 | D_OUT<4> ATTRIBUTES | 8553348 | 0 OUTPUTMC | 2 | 4 | 15 | 4 | 17 INPUTS | 11 | UDS | FCS | Z3_ADR<2> | Z3_ADR_0 | Z3_ADR<6> | AUTOCONFIG_Z3_ACCESS | Z3_ADR<3> | Z3_ADR<4> | Z3_ADR<5> | Z3_ADR_1 | RESET INPUTMC | 8 | 9 | 0 | 11 | 17 | 2 | 16 | 7 | 13 | 11 | 10 | 11 | 12 | 11 | 13 | 11 | 0 INPUTP | 3 | 155 | 147 | 263 EQ | 8 | !D_OUT<4>.D = !UDS & !FCS & !Z3_ADR<2> & !Z3_ADR_1 & Z3_ADR_0 & AUTOCONFIG_Z3_ACCESS & !Z3_ADR<3> & !Z3_ADR<4> & !Z3_ADR<5> # !UDS & !FCS & !Z3_ADR<2> & !Z3_ADR_0 & !Z3_ADR<6> & AUTOCONFIG_Z3_ACCESS & !Z3_ADR<3> & !Z3_ADR<4> & !Z3_ADR<5> # !UDS & !FCS & !Z3_ADR_1 & Z3_ADR_0 & !Z3_ADR<6> & AUTOCONFIG_Z3_ACCESS & !Z3_ADR<3> & !Z3_ADR<4> & !Z3_ADR<5>; D_OUT<4>.CLK = CLK_EXT; // GCK D_OUT<4>.AP = !RESET; GLOBALS | 1 | 2 | CLK_EXT MACROCELL | 3 | 9 | D_OUT<5> ATTRIBUTES | 8553348 | 0 OUTPUTMC | 3 | 6 | 1 | 6 | 0 | 6 | 3 INPUTS | 11 | UDS | FCS | Z3_ADR<2> | Z3_ADR_1 | AUTOCONFIG_Z3_ACCESS | Z3_ADR<3> | Z3_ADR<4> | Z3_ADR<5> | Z3_ADR_0 | Z3_ADR<6> | RESET INPUTMC | 8 | 9 | 0 | 11 | 0 | 7 | 13 | 11 | 10 | 11 | 12 | 11 | 13 | 11 | 17 | 2 | 16 INPUTP | 3 | 155 | 147 | 263 EQ | 8 | !D_OUT<5>.D = !UDS & !FCS & !Z3_ADR<2> & !Z3_ADR_1 & AUTOCONFIG_Z3_ACCESS & !Z3_ADR<3> & !Z3_ADR<4> & !Z3_ADR<5> # !UDS & !FCS & !Z3_ADR<2> & !Z3_ADR_0 & Z3_ADR<6> & AUTOCONFIG_Z3_ACCESS & !Z3_ADR<3> & !Z3_ADR<4> & !Z3_ADR<5> # !UDS & !FCS & !Z3_ADR_1 & !Z3_ADR_0 & Z3_ADR<6> & AUTOCONFIG_Z3_ACCESS & !Z3_ADR<3> & !Z3_ADR<4> & !Z3_ADR<5>; D_OUT<5>.CLK = CLK_EXT; // GCK D_OUT<5>.AP = !RESET; GLOBALS | 1 | 2 | CLK_EXT MACROCELL | 3 | 8 | D_OUT<6> ATTRIBUTES | 8553348 | 0 OUTPUTMC | 2 | 6 | 5 | 6 | 6 INPUTS | 11 | UDS | FCS | Z3_ADR<2> | Z3_ADR_1 | Z3_ADR_0 | AUTOCONFIG_Z3_ACCESS | Z3_ADR<3> | Z3_ADR<4> | Z3_ADR<5> | Z3_ADR<6> | RESET INPUTMC | 8 | 9 | 0 | 11 | 0 | 11 | 17 | 7 | 13 | 11 | 10 | 11 | 12 | 11 | 13 | 2 | 16 INPUTP | 3 | 155 | 147 | 263 EQ | 9 | !D_OUT<6>.D = !UDS & !FCS & !Z3_ADR<2> & !Z3_ADR_1 & !Z3_ADR_0 & AUTOCONFIG_Z3_ACCESS & !Z3_ADR<3> & !Z3_ADR<4> & !Z3_ADR<5> # !UDS & !FCS & !Z3_ADR<2> & !Z3_ADR_1 & !Z3_ADR<6> & AUTOCONFIG_Z3_ACCESS & !Z3_ADR<3> & !Z3_ADR<4> & !Z3_ADR<5> # !UDS & !FCS & Z3_ADR<2> & !Z3_ADR_1 & Z3_ADR_0 & Z3_ADR<6> & AUTOCONFIG_Z3_ACCESS & !Z3_ADR<3> & !Z3_ADR<4> & !Z3_ADR<5>; D_OUT<6>.CLK = CLK_EXT; // GCK D_OUT<6>.AP = !RESET; GLOBALS | 1 | 2 | CLK_EXT MACROCELL | 3 | 0 | D_OUT<7> ATTRIBUTES | 8553348 | 0 OUTPUTMC | 3 | 6 | 12 | 6 | 13 | 3 | 17 INPUTS | 23 | UDS | FCS | Z3_ADR_1 | Z3_ADR<6> | AUTOCONFIG_Z3_ACCESS | Z3_ADR<3> | Z3_ADR<4> | Z3_ADR<5> | RESET | D<8>.PIN | AS | AUTO_CONFIG_Z2_DONE<0> | AUTO_CONFIG_Z2_DONE<1> | IDE_BASEADR<0> | A<5> | A<4> | A<1> | RW | A<6> | A<3> | A<2> | AUTOCONFIG_Z2_ACCESS | LDS INPUTMC | 10 | 11 | 0 | 2 | 16 | 7 | 13 | 11 | 10 | 11 | 12 | 11 | 13 | 7 | 15 | 7 | 14 | 3 | 17 | 4 | 6 INPUTP | 13 | 155 | 147 | 263 | 32 | 152 | 91 | 97 | 107 | 158 | 98 | 99 | 101 | 157 EXPORTS | 1 | 3 | 17 EQ | 10 | !D_OUT<7>.D = !UDS & !FCS & !Z3_ADR_1 & Z3_ADR<6> & AUTOCONFIG_Z3_ACCESS & !Z3_ADR<3> & !Z3_ADR<4> & !Z3_ADR<5>; D_OUT<7>.CLK = CLK_EXT; // GCK D_OUT<7>.AP = !RESET; D_OUT<7>.EXP = D<8>.PIN & !AS & AUTO_CONFIG_Z2_DONE<0> & !AUTO_CONFIG_Z2_DONE<1> & !UDS & !IDE_BASEADR<0> & !A<5> & !A<4> & !A<1> & !RW & A<6> & A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS # D<8>.PIN & !AS & AUTO_CONFIG_Z2_DONE<0> & !AUTO_CONFIG_Z2_DONE<1> & !LDS & !IDE_BASEADR<0> & !A<5> & !A<4> & !A<1> & !RW & A<6> & A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS GLOBALS | 1 | 2 | CLK_EXT MACROCELL | 5 | 17 | LAN_A_INIT<6> ATTRIBUTES | 8553348 | 0 OUTPUTMC | 1 | 1 | 4 INPUTS | 4 | LAN_RST_SM_FSM_FFd3 | LAN_RST_SM_FSM_FFd2 | LAN_RST_SM_FSM_FFd1 | RESET INPUTMC | 3 | 5 | 8 | 5 | 10 | 5 | 11 INPUTP | 1 | 263 EQ | 4 | LAN_A_INIT<6>.D = LAN_RST_SM_FSM_FFd3 & LAN_RST_SM_FSM_FFd1 # !LAN_RST_SM_FSM_FFd3 & !LAN_RST_SM_FSM_FFd2; LAN_A_INIT<6>.CLK = CLK_EXT; // GCK LAN_A_INIT<6>.AP = RESET; GLOBALS | 1 | 2 | CLK_EXT MACROCELL | 5 | 16 | LAN_CS_RST ATTRIBUTES | 8553232 | 0 OUTPUTMC | 1 | 7 | 7 INPUTS | 4 | LAN_RST_SM_FSM_FFd3 | LAN_RST_SM_FSM_FFd2 | LAN_RST_SM_FSM_FFd1 | RESET INPUTMC | 3 | 5 | 8 | 5 | 10 | 5 | 11 INPUTP | 1 | 263 EQ | 6 | !LAN_CS_RST.D = !LAN_RST_SM_FSM_FFd3 & LAN_RST_SM_FSM_FFd2 & LAN_RST_SM_FSM_FFd1 # !LAN_RST_SM_FSM_FFd3 & !LAN_RST_SM_FSM_FFd2 & !LAN_RST_SM_FSM_FFd1; LAN_CS_RST.CLK = CLK_EXT; // GCK LAN_CS_RST.AR = RESET; GLOBALS | 1 | 2 | CLK_EXT MACROCELL | 5 | 3 | LAN_IRQ_D0 ATTRIBUTES | 8553344 | 0 OUTPUTMC | 1 | 5 | 12 INPUTS | 2 | LAN_INT | RESET INPUTP | 2 | 201 | 263 EQ | 3 | LAN_IRQ_D0.D = LAN_INT; LAN_IRQ_D0.CLK = CLK_EXT; // GCK LAN_IRQ_D0.AP = !RESET; GLOBALS | 1 | 2 | CLK_EXT MACROCELL | 14 | 12 | LAN_RD_S ATTRIBUTES | 8553232 | 0 OUTPUTMC | 2 | 7 | 9 | 14 | 13 INPUTS | 8 | LAN_SM_FSM_FFd4 | LAN_SM_FSM_FFd2 | LAN_SM_FSM_FFd1 | LAN_SM_FSM_FFd3 | RW | LAN_SM_RST | DQ_SWAP | DQ<7>.PIN INPUTMC | 6 | 14 | 3 | 0 | 1 | 12 | 4 | 0 | 10 | 6 | 0 | 8 | 1 INPUTP | 2 | 158 | 226 EXPORTS | 1 | 14 | 13 EQ | 8 | LAN_RD_S.D = RW & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # !LAN_SM_FSM_FFd3 & LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1 # LAN_SM_FSM_FFd4 & !LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1; LAN_RD_S.CLK = CLK_EXT; // GCK LAN_RD_S.AR = LAN_SM_RST; LAN_RD_S.EXP = DQ_SWAP & DQ<7>.PIN GLOBALS | 1 | 2 | CLK_EXT MACROCELL | 14 | 15 | LAN_READY ATTRIBUTES | 8553232 | 0 OUTPUTMC | 2 | 2 | 9 | 14 | 16 INPUTS | 8 | LAN_SM_FSM_FFd3 | LAN_SM_FSM_FFd2 | LAN_SM_FSM_FFd4 | LAN_SM_FSM_FFd1 | DQ_SWAP | DQ<5>.PIN | LAN_SM_RST | Z3_DATA<14>.EXP INPUTMC | 7 | 0 | 10 | 0 | 1 | 14 | 3 | 12 | 4 | 8 | 1 | 6 | 0 | 14 | 14 INPUTP | 1 | 221 EXPORTS | 1 | 14 | 16 IMPORTS | 1 | 14 | 14 EQ | 10 | LAN_READY.D = LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd2 # LAN_SM_FSM_FFd3 & LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd1 # !LAN_SM_FSM_FFd4 & !LAN_SM_FSM_FFd2 & LAN_SM_FSM_FFd1 ;Imported pterms FB15_15 # DS1 & DS0 & !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2; LAN_READY.CLK = CLK_EXT; // GCK LAN_READY.AR = LAN_SM_RST; LAN_READY.EXP = DQ_SWAP & DQ<5>.PIN GLOBALS | 1 | 2 | CLK_EXT MACROCELL | 14 | 6 | LAN_WRH_S ATTRIBUTES | 8553232 | 0 OUTPUTMC | 2 | 7 | 4 | 14 | 7 INPUTS | 11 | DS0 | LAN_SM_FSM_FFd3 | LAN_SM_FSM_FFd2 | LAN_SM_FSM_FFd1 | LDS | LAN_SM_FSM_FFd4 | LAN_SM_RST | UDS | A<23>.PIN | DQ_SWAP | A<15>.PIN INPUTMC | 6 | 0 | 10 | 0 | 1 | 12 | 4 | 14 | 3 | 6 | 0 | 8 | 1 INPUTP | 5 | 170 | 157 | 155 | 161 | 139 EXPORTS | 1 | 14 | 7 EQ | 10 | LAN_WRH_S.D = !LDS & LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 & LAN_SM_FSM_FFd1 # !DS0 & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd2 & LAN_SM_FSM_FFd1; LAN_WRH_S.CLK = CLK_EXT; // GCK LAN_WRH_S.AR = LAN_SM_RST; LAN_WRH_S.EXP = UDS & LDS & A<23>.PIN & DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # UDS & LDS & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 & A<15>.PIN GLOBALS | 1 | 2 | CLK_EXT MACROCELL | 14 | 17 | LAN_WRL_S ATTRIBUTES | 8553232 | 0 OUTPUTMC | 2 | 12 | 14 | 14 | 0 INPUTS | 12 | DS1 | LAN_SM_FSM_FFd3 | LAN_SM_FSM_FFd2 | LAN_SM_FSM_FFd1 | A<17>.PIN | DQ_SWAP | LAN_SM_RST | LAN_SM_FSM_FFd4 | UDS | D<1>.PIN | A<9>.PIN | Z3_DATA<13>.EXP INPUTMC | 7 | 0 | 10 | 0 | 1 | 12 | 4 | 8 | 1 | 6 | 0 | 14 | 3 | 14 | 16 INPUTP | 5 | 148 | 172 | 155 | 30 | 108 EXPORTS | 1 | 14 | 0 IMPORTS | 1 | 14 | 16 EQ | 13 | LAN_WRL_S.D = !DS1 & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd2 & LAN_SM_FSM_FFd1 ;Imported pterms FB15_17 # !UDS & LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 & LAN_SM_FSM_FFd1; LAN_WRL_S.CLK = CLK_EXT; // GCK LAN_WRL_S.AR = LAN_SM_RST; LAN_WRL_S.EXP = A<17>.PIN & DQ_SWAP & !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1 # !UDS & D<1>.PIN & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # !DQ_SWAP & !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1 & A<9>.PIN GLOBALS | 1 | 2 | CLK_EXT MACROCELL | 0 | 8 | Z3_A_LOW ATTRIBUTES | 8553232 | 0 OUTPUTMC | 1 | 3 | 5 INPUTS | 8 | LAN_SM_FSM_FFd4 | LAN_SM_FSM_FFd2 | DS0 | DS1 | LAN_SM_FSM_FFd3 | LAN_SM_FSM_FFd1 | IDE_CS_0_OBUF.EXP | LAN_SM_RST INPUTMC | 6 | 14 | 3 | 0 | 1 | 0 | 10 | 12 | 4 | 0 | 7 | 6 | 0 INPUTP | 2 | 170 | 148 IMPORTS | 1 | 0 | 7 EQ | 11 | Z3_A_LOW.D = LAN_SM_FSM_FFd4 & !LAN_SM_FSM_FFd2 # !DS1 & !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 # !DS0 & !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 # !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd2 & LAN_SM_FSM_FFd1 ;Imported pterms FB1_8 # LAN_SM_FSM_FFd3 & LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd1 # UDS & LDS & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4; Z3_A_LOW.CLK = CLK_EXT; // GCK Z3_A_LOW.AR = LAN_SM_RST; GLOBALS | 1 | 2 | CLK_EXT MACROCELL | 4 | 4 | ROM_OE_OBUF ATTRIBUTES | 264962 | 0 OUTPUTMC | 1 | 4 | 3 INPUTS | 7 | AS | ROM_OE_S | AUTOBOOT_OFF | UDS | LDS | DS1 | DS0 INPUTMC | 1 | 8 | 5 INPUTP | 6 | 152 | 142 | 155 | 157 | 148 | 170 EXPORTS | 1 | 4 | 3 EQ | 2 | !ROM_OE = !AS & !ROM_OE_S & !AUTOBOOT_OFF; ROM_OE_OBUF.EXP = UDS & LDS & DS1 & DS0 MACROCELL | 6 | 0 | LAN_SM_RST ATTRIBUTES | 8553216 | 0 OUTPUTMC | 58 | 8 | 10 | 15 | 5 | 15 | 2 | 15 | 1 | 14 | 16 | 14 | 14 | 14 | 13 | 8 | 13 | 8 | 16 | 10 | 2 | 10 | 4 | 10 | 9 | 10 | 10 | 12 | 7 | 15 | 10 | 15 | 7 | 15 | 13 | 15 | 12 | 15 | 11 | 10 | 12 | 10 | 8 | 10 | 7 | 10 | 6 | 12 | 8 | 15 | 8 | 15 | 6 | 15 | 4 | 10 | 5 | 10 | 3 | 10 | 1 | 10 | 0 | 12 | 2 | 0 | 10 | 14 | 3 | 0 | 1 | 12 | 4 | 10 | 17 | 15 | 15 | 0 | 0 | 0 | 15 | 12 | 17 | 12 | 14 | 12 | 12 | 14 | 0 | 15 | 16 | 0 | 12 | 14 | 10 | 12 | 11 | 12 | 6 | 14 | 9 | 10 | 15 | 14 | 4 | 14 | 12 | 14 | 15 | 14 | 6 | 14 | 17 | 0 | 8 | 6 | 1 INPUTS | 12 | RESET | UDS | FCS | LAN_ACCESS | Z3_ADR<13> | BERR | DS0 | DS1 | LDS | RW | AUTOCONFIG_Z3_ACCESS | D_OUT<5> INPUTMC | 4 | 8 | 8 | 7 | 12 | 7 | 13 | 3 | 9 INPUTP | 8 | 263 | 155 | 147 | 176 | 170 | 148 | 157 | 158 EXPORTS | 1 | 6 | 1 EQ | 11 | !LAN_SM_RST.D = RESET & !UDS & !FCS & LAN_ACCESS & !Z3_ADR<13> & BERR # RESET & !LDS & !FCS & LAN_ACCESS & !Z3_ADR<13> & BERR # RESET & !DS1 & !FCS & LAN_ACCESS & !Z3_ADR<13> & BERR # RESET & !DS0 & !FCS & LAN_ACCESS & !Z3_ADR<13> & BERR; !LAN_SM_RST.CLK = CLK_EXT; // GCK LAN_SM_RST.EXP = !LDS & !FCS & RW & !LAN_ACCESS & AUTOCONFIG_Z3_ACCESS & D_OUT<5> GLOBALS | 1 | 2 | CLK_EXT MACROCELL | 11 | 8 | CP_WE_S ATTRIBUTES | 8520480 | 0 OUTPUTMC | 2 | 2 | 11 | 10 | 15 INPUTS | 5 | UDS | RW | CP_CS | LDS | SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF INPUTMC | 2 | 4 | 1 | 2 | 8 INPUTP | 3 | 155 | 158 | 157 EQ | 3 | !CP_WE_S.D = !UDS & !RW & !CP_CS # !LDS & !RW & !CP_CS; CP_WE_S.CLK = SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF; MACROCELL | 14 | 2 | CP_RD_S ATTRIBUTES | 8520480 | 0 OUTPUTMC | 2 | 12 | 1 | 14 | 3 INPUTS | 11 | UDS | RW | CP_CS | LDS | SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF | LAN_SM_FSM_FFd4 | LAN_SM_FSM_FFd2 | LAN_SM_FSM_FFd1 | DS1 | DS0 | LAN_SM_FSM_FFd3 INPUTMC | 6 | 4 | 1 | 2 | 8 | 14 | 3 | 0 | 1 | 12 | 4 | 0 | 10 INPUTP | 5 | 155 | 158 | 157 | 148 | 170 EXPORTS | 1 | 14 | 3 EQ | 6 | !CP_RD_S.D = !UDS & RW & !CP_CS # !LDS & RW & !CP_CS; CP_RD_S.CLK = SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF; CP_RD_S.EXP = LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1 # DS1 & DS0 & LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 MACROCELL | 2 | 11 | CP_WE_QUIRK ATTRIBUTES | 8520480 | 0 OUTPUTMC | 1 | 10 | 15 INPUTS | 2 | CP_WE_S | SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF INPUTMC | 2 | 11 | 8 | 2 | 8 EQ | 2 | CP_WE_QUIRK.D = CP_WE_S; CP_WE_QUIRK.CLK = SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF; MACROCELL | 5 | 0 | LAN_A_INIT<3> ATTRIBUTES | 8553348 | 0 OUTPUTMC | 1 | 3 | 7 INPUTS | 1 | RESET INPUTP | 1 | 263 EQ | 3 | LAN_A_INIT<3>.D = Gnd; LAN_A_INIT<3>.CLK = CLK_EXT; // GCK LAN_A_INIT<3>.AP = RESET; GLOBALS | 1 | 2 | CLK_EXT MACROCELL | 3 | 5 | A_LAN_0_OBUF ATTRIBUTES | 264962 | 0 INPUTS | 2 | RESET | Z3_A_LOW INPUTMC | 1 | 0 | 8 INPUTP | 1 | 263 EQ | 1 | !A_LAN<0> = RESET & !Z3_A_LOW; MACROCELL | 5 | 5 | A_LAN_10_OBUF ATTRIBUTES | 264962 | 0 INPUTS | 2 | RESET | Z3_ADR<9> INPUTMC | 1 | 2 | 12 INPUTP | 1 | 263 EQ | 1 | !A_LAN<10> = RESET & !Z3_ADR<9>; MACROCELL | 5 | 7 | A_LAN_11_OBUF ATTRIBUTES | 264962 | 0 INPUTS | 2 | RESET | Z3_ADR<10> INPUTMC | 1 | 4 | 5 INPUTP | 1 | 263 EQ | 1 | !A_LAN<11> = RESET & !Z3_ADR<10>; MACROCELL | 5 | 2 | A_LAN_12_OBUF ATTRIBUTES | 264962 | 0 INPUTS | 2 | RESET | Z3_ADR<11> INPUTMC | 1 | 8 | 4 INPUTP | 1 | 263 EQ | 1 | !A_LAN<12> = RESET & !Z3_ADR<11>; MACROCELL | 5 | 4 | A_LAN_13_OBUF ATTRIBUTES | 264962 | 0 INPUTS | 2 | RESET | Z3_ADR<12> INPUTMC | 1 | 8 | 3 INPUTP | 1 | 263 EQ | 1 | !A_LAN<13> = RESET & !Z3_ADR<12>; MACROCELL | 3 | 4 | A_LAN_1_OBUF ATTRIBUTES | 264962 | 0 INPUTS | 2 | RESET | Z3_ADR_0 INPUTMC | 1 | 11 | 17 INPUTP | 1 | 263 EQ | 1 | !A_LAN<1> = RESET & !Z3_ADR_0; MACROCELL | 3 | 11 | A_LAN_2_OBUF ATTRIBUTES | 264962 | 0 INPUTS | 2 | RESET | Z3_ADR_1 INPUTMC | 1 | 11 | 0 INPUTP | 1 | 263 EQ | 1 | !A_LAN<2> = RESET & !Z3_ADR_1; MACROCELL | 3 | 7 | A_LAN_3_OBUF ATTRIBUTES | 264962 | 0 INPUTS | 3 | RESET | LAN_A_INIT<3> | Z3_ADR<2> INPUTMC | 2 | 5 | 0 | 9 | 0 INPUTP | 1 | 263 EQ | 2 | A_LAN<3> = RESET & Z3_ADR<2> # !RESET & LAN_A_INIT<3>; MACROCELL | 1 | 1 | A_LAN_4_OBUF ATTRIBUTES | 264962 | 0 INPUTS | 2 | RESET | Z3_ADR<3> INPUTMC | 1 | 11 | 10 INPUTP | 1 | 263 EQ | 1 | !A_LAN<4> = RESET & !Z3_ADR<3>; MACROCELL | 3 | 13 | A_LAN_5_OBUF ATTRIBUTES | 264962 | 0 OUTPUTMC | 1 | 3 | 14 INPUTS | 17 | RESET | Z3_ADR<4> | D<11>.PIN | AS | AUTO_CONFIG_Z2_DONE<0> | AUTO_CONFIG_Z2_DONE<1> | UDS | IDE_BASEADR<3> | A<5> | A<4> | A<1> | RW | A<6> | A<3> | A<2> | AUTOCONFIG_Z2_ACCESS | LDS INPUTMC | 5 | 11 | 12 | 7 | 15 | 7 | 14 | 3 | 14 | 4 | 6 INPUTP | 12 | 263 | 77 | 152 | 155 | 91 | 97 | 107 | 158 | 98 | 99 | 101 | 157 EXPORTS | 1 | 3 | 14 EQ | 7 | !A_LAN<5> = RESET & !Z3_ADR<4>; A_LAN_5_OBUF.EXP = D<11>.PIN & !AS & AUTO_CONFIG_Z2_DONE<0> & !AUTO_CONFIG_Z2_DONE<1> & !UDS & !IDE_BASEADR<3> & !A<5> & !A<4> & !A<1> & !RW & A<6> & A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS # D<11>.PIN & !AS & AUTO_CONFIG_Z2_DONE<0> & !AUTO_CONFIG_Z2_DONE<1> & !LDS & !IDE_BASEADR<3> & !A<5> & !A<4> & !A<1> & !RW & A<6> & A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS MACROCELL | 1 | 4 | A_LAN_6_OBUF ATTRIBUTES | 264962 | 0 INPUTS | 3 | RESET | LAN_A_INIT<6> | Z3_ADR<5> INPUTMC | 2 | 5 | 17 | 11 | 13 INPUTP | 1 | 263 EQ | 2 | A_LAN<6> = RESET & Z3_ADR<5> # !RESET & LAN_A_INIT<6>; MACROCELL | 1 | 2 | A_LAN_7_OBUF ATTRIBUTES | 264962 | 0 INPUTS | 2 | RESET | Z3_ADR<6> INPUTMC | 1 | 2 | 16 INPUTP | 1 | 263 EQ | 1 | !A_LAN<7> = RESET & !Z3_ADR<6>; MACROCELL | 5 | 9 | A_LAN_8_OBUF ATTRIBUTES | 264962 | 0 INPUTS | 2 | RESET | Z3_ADR<7> INPUTMC | 1 | 2 | 15 INPUTP | 1 | 263 EQ | 1 | !A_LAN<8> = RESET & !Z3_ADR<7>; MACROCELL | 5 | 13 | A_LAN_9_OBUF ATTRIBUTES | 264962 | 0 INPUTS | 2 | RESET | Z3_ADR<8> INPUTMC | 1 | 2 | 14 INPUTP | 1 | 263 EQ | 1 | !A_LAN<9> = RESET & !Z3_ADR<8>; MACROCELL | 12 | 1 | CP_RD_OBUF ATTRIBUTES | 264962 | 0 OUTPUTMC | 1 | 12 | 0 INPUTS | 10 | AS | CP_RD_S | UDS | D<5>.PIN | DQ_SWAP | LAN_SM_FSM_FFd3 | LAN_SM_FSM_FFd4 | LDS | A<21>.PIN | A<13>.PIN INPUTMC | 4 | 14 | 2 | 8 | 1 | 0 | 10 | 14 | 3 INPUTP | 6 | 152 | 155 | 37 | 157 | 163 | 123 EXPORTS | 1 | 12 | 0 EQ | 9 | !CP_RD = !AS & !CP_RD_S; CP_RD_OBUF.EXP = !UDS & D<5>.PIN & DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # !LDS & D<5>.PIN & DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # UDS & LDS & A<21>.PIN & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # UDS & LDS & DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 & A<13>.PIN MACROCELL | 10 | 16 | CP_WE_OBUF ATTRIBUTES | 264962 | 0 OUTPUTMC | 1 | 10 | 17 INPUTS | 12 | D<8>.PIN | UDS | DQ_SWAP | LAN_SM_FSM_FFd3 | LAN_SM_FSM_FFd4 | A<16>.PIN | LAN_SM_FSM_FFd2 | LAN_SM_FSM_FFd1 | D<0>.PIN | LDS | A<8>.PIN | DQ_DATA<8>.EXP INPUTMC | 6 | 8 | 1 | 0 | 10 | 14 | 3 | 0 | 1 | 12 | 4 | 10 | 15 INPUTP | 6 | 32 | 155 | 175 | 4 | 157 | 106 EXPORTS | 1 | 10 | 17 IMPORTS | 1 | 10 | 15 EQ | 12 | !CP_WE = ;Imported pterms FB11_16 !AS & !CP_WE_S & CP_WE_QUIRK; CP_WE_OBUF.EXP = D<8>.PIN & !UDS & DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # A<16>.PIN & DQ_SWAP & !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1 # !UDS & D<0>.PIN & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # !LDS & D<0>.PIN & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # !DQ_SWAP & !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1 & A<8>.PIN MACROCELL | 0 | 16 | IDE_R_OBUF ATTRIBUTES | 264962 | 0 OUTPUTMC | 1 | 0 | 15 INPUTS | 10 | AS | IDE_R_S | UDS | D<4>.PIN | DQ_SWAP | LAN_SM_FSM_FFd3 | LAN_SM_FSM_FFd4 | LDS | A<20>.PIN | A<12>.PIN INPUTMC | 4 | 8 | 12 | 8 | 1 | 0 | 10 | 14 | 3 INPUTP | 6 | 152 | 155 | 38 | 157 | 167 | 115 EXPORTS | 1 | 0 | 15 EQ | 9 | !IDE_R = !AS & !IDE_R_S; IDE_R_OBUF.EXP = !UDS & D<4>.PIN & DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # !LDS & D<4>.PIN & DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # A<20>.PIN & UDS & LDS & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # UDS & LDS & DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 & A<12>.PIN MACROCELL | 2 | 1 | IDE_W_OBUF ATTRIBUTES | 264962 | 0 OUTPUTMC | 1 | 2 | 0 INPUTS | 7 | A<20>.PIN | LAN_BASEADR<4> | A<19>.PIN | LAN_BASEADR<3> | A<16>.PIN | LAN_BASEADR<0> | EXP24_.EXP INPUTMC | 4 | 6 | 9 | 6 | 8 | 1 | 17 | 2 | 2 INPUTP | 3 | 167 | 169 | 175 EXPORTS | 1 | 2 | 0 IMPORTS | 1 | 2 | 2 EQ | 7 | !IDE_W = ;Imported pterms FB3_3 !AS & !IDE_W_S; IDE_W_OBUF.EXP = A<20>.PIN & !LAN_BASEADR<4> # !A<20>.PIN & LAN_BASEADR<4> # A<19>.PIN & !LAN_BASEADR<3> # A<16>.PIN & !LAN_BASEADR<0> # !A<16>.PIN & LAN_BASEADR<0> MACROCELL | 7 | 7 | LAN_CS_OBUF ATTRIBUTES | 264962 | 0 INPUTS | 3 | RESET | LAN_CS_RST | LAN_ACCESS INPUTMC | 2 | 5 | 16 | 8 | 8 INPUTP | 1 | 263 EQ | 2 | LAN_CS = RESET & LAN_ACCESS # !RESET & LAN_CS_RST; MACROCELL | 7 | 4 | LAN_WRH_OBUF ATTRIBUTES | 264962 | 0 INPUTS | 4 | RESET | LAN_WR_RST | FCS | LAN_WRH_S INPUTMC | 2 | 5 | 6 | 14 | 6 INPUTP | 2 | 263 | 147 EQ | 3 | LAN_WRH = !RESET & LAN_WR_RST # FCS & LAN_WR_RST # RESET & !FCS & LAN_WRH_S; MACROCELL | 12 | 13 | LAN_WRL_OBUF ATTRIBUTES | 264962 | 0 OUTPUTMC | 1 | 12 | 12 INPUTS | 10 | D<15>.PIN | LDS | DQ_SWAP | LAN_SM_FSM_FFd3 | LAN_SM_FSM_FFd4 | UDS | D<7>.PIN | A<23>.PIN | A<15>.PIN | DQ_DATA<14>.EXP INPUTMC | 4 | 8 | 1 | 0 | 10 | 14 | 3 | 12 | 14 INPUTP | 6 | 89 | 157 | 155 | 29 | 161 | 139 EXPORTS | 1 | 12 | 12 IMPORTS | 1 | 12 | 14 EQ | 14 | LAN_WRL = ;Imported pterms FB13_15 !RESET & LAN_WR_RST # FCS & LAN_WR_RST # RESET & !FCS & LAN_WRL_S; LAN_WRL_OBUF.EXP = D<15>.PIN & !LDS & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # !UDS & D<7>.PIN & DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # !LDS & D<7>.PIN & DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # UDS & LDS & A<23>.PIN & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # UDS & LDS & DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 & A<15>.PIN MACROCELL | 7 | 9 | LAN_RD_OBUF ATTRIBUTES | 264962 | 0 INPUTS | 3 | RESET | FCS | LAN_RD_S INPUTMC | 1 | 14 | 12 INPUTP | 2 | 263 | 147 EQ | 1 | LAN_RD = RESET & !FCS & LAN_RD_S; MACROCELL | 13 | 13 | SLAVE_OBUF ATTRIBUTES | 264962 | 0 OUTPUTMC | 1 | 13 | 12 INPUTS | 17 | AS | FCS | LAN_ACCESS | AUTOCONFIG_Z3_ACCESS | AUTOCONFIG_Z2_ACCESS | IDE_ACCESS | CP_CS | AUTO_CONFIG_Z2_DONE<0> | AUTO_CONFIG_Z2_DONE<1> | UDS | A<5> | A<4> | A<1> | A<6> | A<2> | LDS | ROM_B_0_OBUF$BUF1.EXP INPUTMC | 8 | 8 | 8 | 7 | 13 | 4 | 6 | 7 | 17 | 4 | 1 | 7 | 15 | 7 | 14 | 13 | 14 INPUTP | 9 | 152 | 147 | 155 | 91 | 97 | 107 | 98 | 101 | 157 EXPORTS | 1 | 13 | 12 IMPORTS | 1 | 13 | 14 EQ | 12 | SLAVE = AS & FCS # AS & !LAN_ACCESS & !AUTOCONFIG_Z3_ACCESS # FCS & !AUTOCONFIG_Z2_ACCESS & !IDE_ACCESS & CP_CS ;Imported pterms FB14_15 # !LAN_ACCESS & !AUTOCONFIG_Z2_ACCESS & !AUTOCONFIG_Z3_ACCESS & !IDE_ACCESS & CP_CS; SLAVE_OBUF.EXP = !AS & AUTO_CONFIG_Z2_DONE<0> & !AUTO_CONFIG_Z2_DONE<1> & !UDS & A<5> & !A<4> & A<1> & !A<6> & A<2> & AUTOCONFIG_Z2_ACCESS # !AS & AUTO_CONFIG_Z2_DONE<0> & !AUTO_CONFIG_Z2_DONE<1> & !LDS & A<5> & !A<4> & A<1> & !A<6> & A<2> & AUTOCONFIG_Z2_ACCESS MACROCELL | 13 | 2 | ROM_B_0_OBUF$BUF2 ATTRIBUTES | 265986 | 0 INPUTS | 1 | ROM_B_0_OBUF$BUF2/ROM_B_0_OBUF$BUF2_TRST INPUTMC | 1 | 4 | 17 EQ | 2 | OVR = Gnd; OVR.OE = ROM_B_0_OBUF$BUF2/ROM_B_0_OBUF$BUF2_TRST; MACROCELL | 2 | 13 | ROM_B_0_OBUF$BUF8 ATTRIBUTES | 265986 | 0 INPUTS | 1 | ROM_B_0_OBUF$BUF8/ROM_B_0_OBUF$BUF8_TRST INPUTMC | 1 | 2 | 10 EQ | 2 | INT_OUT = Gnd; INT_OUT.OE = ROM_B_0_OBUF$BUF8/ROM_B_0_OBUF$BUF8_TRST; MACROCELL | 14 | 11 | ROM_B_0_OBUF$BUF9 ATTRIBUTES | 265986 | 0 OUTPUTMC | 1 | 14 | 10 INPUTS | 9 | ROM_B_0_OBUF$BUF9/ROM_B_0_OBUF$BUF9_TRST__$INT | UDS | D<4>.PIN | DQ_SWAP | LAN_SM_FSM_FFd3 | LAN_SM_FSM_FFd4 | LDS | A<20>.PIN | A<12>.PIN INPUTMC | 4 | 2 | 9 | 8 | 1 | 0 | 10 | 14 | 3 INPUTP | 5 | 155 | 38 | 157 | 167 | 115 EXPORTS | 1 | 14 | 10 EQ | 10 | DTACK = Gnd; DTACK.OE = !ROM_B_0_OBUF$BUF9/ROM_B_0_OBUF$BUF9_TRST__$INT; ROM_B_0_OBUF$BUF9.EXP = !UDS & D<4>.PIN & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # !LDS & D<4>.PIN & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # A<20>.PIN & UDS & LDS & DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # UDS & LDS & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 & A<12>.PIN MACROCELL | 13 | 10 | CFOUT_OBUF ATTRIBUTES | 264962 | 0 OUTPUTMC | 1 | 13 | 11 INPUTS | 13 | AUTO_CONFIG_Z2_DONE<0> | AUTO_CONFIG_Z2_DONE<1> | AUTO_CONFIG_DONE | AS | UDS | A<5> | A<4> | A<6> | A<3> | A<2> | AUTOCONFIG_Z2_ACCESS | LDS | A<1> INPUTMC | 4 | 7 | 15 | 7 | 14 | 8 | 15 | 4 | 6 INPUTP | 9 | 152 | 155 | 91 | 97 | 98 | 99 | 101 | 157 | 107 EXPORTS | 1 | 13 | 11 EQ | 10 | !CFOUT = AUTO_CONFIG_Z2_DONE<0> & AUTO_CONFIG_Z2_DONE<1> & AUTO_CONFIG_DONE; CFOUT_OBUF.EXP = !AS & !UDS & !A<5> & A<4> & !A<6> & A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS # !AS & !LDS & A<5> & !A<4> & !A<6> & !A<3> & A<2> & AUTOCONFIG_Z2_ACCESS # !AS & !LDS & !A<5> & A<4> & A<1> & !A<6> & A<3> & AUTOCONFIG_Z2_ACCESS # !AS & !LDS & !A<5> & !A<4> & A<6> & !A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS MACROCELL | 4 | 1 | CP_CS_OBUF ATTRIBUTES | 8782758 | 0 OUTPUTMC | 4 | 11 | 8 | 14 | 2 | 13 | 13 | 13 | 14 INPUTS | 7 | SHUT_UP_Z2<0> | A<16>.PIN | CP_BASEADR<0> | EXP26_.EXP | EXP27_.EXP | AS | RESET INPUTMC | 4 | 13 | 1 | 13 | 9 | 4 | 0 | 4 | 2 INPUTP | 3 | 175 | 152 | 263 IMPORTS | 2 | 4 | 0 | 4 | 2 EQ | 22 | CP_CS.D = SHUT_UP_Z2<0> # A<16>.PIN & !CP_BASEADR<0> # !A<16>.PIN & CP_BASEADR<0> ;Imported pterms FB5_1 # A<19>.PIN & !CP_BASEADR<3> # A<18>.PIN & !CP_BASEADR<2> # !A<18>.PIN & CP_BASEADR<2> # A<17>.PIN & !CP_BASEADR<1> # !A<17>.PIN & CP_BASEADR<1> ;Imported pterms FB5_3 # A<20>.PIN & !CP_BASEADR<4> # !A<20>.PIN & CP_BASEADR<4> # !A<19>.PIN & CP_BASEADR<3> # CP_BASEADR<5> & !A<21>.PIN # !CP_BASEADR<5> & A<21>.PIN ;Imported pterms FB5_4 # CP_BASEADR<6> & !A<22>.PIN # !CP_BASEADR<6> & A<22>.PIN # CP_BASEADR<7> & !A<23>.PIN # !CP_BASEADR<7> & A<23>.PIN; CP_CS.CLK = !AS; CP_CS.AP = !RESET; MACROCELL | 0 | 11 | IDE_A_0_OBUF$BUF0 ATTRIBUTES | 264962 | 0 OUTPUTMC | 1 | 0 | 12 INPUTS | 11 | A<9>.PIN | D<11>.PIN | UDS | DQ_SWAP | LAN_SM_FSM_FFd3 | LAN_SM_FSM_FFd4 | LDS | A<19>.PIN | LAN_SM_FSM_FFd2 | LAN_SM_FSM_FFd1 | A<11>.PIN INPUTMC | 5 | 8 | 1 | 0 | 10 | 14 | 3 | 0 | 1 | 12 | 4 INPUTP | 6 | 108 | 77 | 155 | 157 | 169 | 114 EXPORTS | 1 | 0 | 12 EQ | 9 | IDE_A<0> = A<9>.PIN; IDE_A_0_OBUF$BUF0.EXP = D<11>.PIN & !UDS & DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # D<11>.PIN & !LDS & DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # A<19>.PIN & DQ_SWAP & !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1 # !DQ_SWAP & !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1 & A<11>.PIN MACROCELL | 0 | 14 | IDE_A_1_OBUF$BUF0 ATTRIBUTES | 264962 | 0 OUTPUTMC | 1 | 0 | 15 INPUTS | 11 | A<10>.PIN | D<12>.PIN | UDS | DQ_SWAP | LAN_SM_FSM_FFd3 | LAN_SM_FSM_FFd4 | LDS | A<20>.PIN | LAN_SM_FSM_FFd2 | LAN_SM_FSM_FFd1 | A<12>.PIN INPUTMC | 5 | 8 | 1 | 0 | 10 | 14 | 3 | 0 | 1 | 12 | 4 INPUTP | 6 | 112 | 78 | 155 | 157 | 167 | 115 EXPORTS | 1 | 0 | 15 EQ | 9 | IDE_A<1> = A<10>.PIN; IDE_A_1_OBUF$BUF0.EXP = D<12>.PIN & !UDS & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # D<12>.PIN & !LDS & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # A<20>.PIN & !DQ_SWAP & !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1 # DQ_SWAP & !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1 & A<12>.PIN MACROCELL | 0 | 13 | IDE_A_2_OBUF$BUF0 ATTRIBUTES | 264962 | 0 OUTPUTMC | 1 | 0 | 12 INPUTS | 8 | A<11>.PIN | UDS | D<3>.PIN | DQ_SWAP | LAN_SM_FSM_FFd3 | LAN_SM_FSM_FFd4 | LDS | A<19>.PIN INPUTMC | 3 | 8 | 1 | 0 | 10 | 14 | 3 INPUTP | 5 | 114 | 155 | 28 | 157 | 169 EXPORTS | 1 | 0 | 12 EQ | 9 | IDE_A<2> = A<11>.PIN; IDE_A_2_OBUF$BUF0.EXP = !UDS & D<3>.PIN & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # !LDS & D<3>.PIN & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # A<19>.PIN & UDS & LDS & DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # UDS & LDS & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 & A<11>.PIN MACROCELL | 0 | 7 | IDE_CS_0_OBUF ATTRIBUTES | 264962 | 0 OUTPUTMC | 1 | 0 | 8 INPUTS | 6 | A<12>.PIN | LAN_SM_FSM_FFd3 | LAN_SM_FSM_FFd4 | LAN_SM_FSM_FFd1 | UDS | LDS INPUTMC | 3 | 0 | 10 | 14 | 3 | 12 | 4 INPUTP | 3 | 115 | 155 | 157 EXPORTS | 1 | 0 | 8 EQ | 4 | IDE_CS<0> = !A<12>.PIN; IDE_CS_0_OBUF.EXP = LAN_SM_FSM_FFd3 & LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd1 # UDS & LDS & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 MACROCELL | 0 | 9 | IDE_CS_1_OBUF ATTRIBUTES | 264962 | 0 OUTPUTMC | 1 | 0 | 10 INPUTS | 7 | A<13>.PIN | LAN_SM_FSM_FFd3 | LAN_SM_FSM_FFd2 | LAN_SM_FSM_FFd1 | UDS | LDS | RW INPUTMC | 3 | 0 | 10 | 0 | 1 | 12 | 4 INPUTP | 4 | 123 | 155 | 157 | 158 EXPORTS | 1 | 0 | 10 EQ | 4 | IDE_CS<1> = !A<13>.PIN; IDE_CS_1_OBUF.EXP = !LAN_SM_FSM_FFd3 & LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1 # UDS & LDS & RW & !LAN_SM_FSM_FFd3 MACROCELL | 13 | 14 | ROM_B_0_OBUF$BUF1 ATTRIBUTES | 265986 | 0 OUTPUTMC | 1 | 13 | 13 INPUTS | 5 | LAN_ACCESS | AUTOCONFIG_Z2_ACCESS | AUTOCONFIG_Z3_ACCESS | IDE_ACCESS | CP_CS INPUTMC | 5 | 8 | 8 | 4 | 6 | 7 | 13 | 7 | 17 | 4 | 1 EXPORTS | 1 | 13 | 13 EQ | 4 | OWN = Gnd; OWN.OE = Gnd; ROM_B_0_OBUF$BUF1.EXP = !LAN_ACCESS & !AUTOCONFIG_Z2_ACCESS & !AUTOCONFIG_Z3_ACCESS & !IDE_ACCESS & CP_CS MACROCELL | 15 | 9 | ROM_B_0_OBUF$BUF3 ATTRIBUTES | 265986 | 0 INPUTS | 0 EQ | 2 | MTACK = Gnd; MTACK.OE = Gnd; MACROCELL | 11 | 1 | ROM_B_0_OBUF$BUF4 ATTRIBUTES | 265986 | 0 OUTPUTMC | 1 | 11 | 2 INPUTS | 10 | AS | UDS | A<5> | A<1> | A<6> | A<3> | A<2> | AUTOCONFIG_Z2_ACCESS | LDS | A<4> INPUTMC | 1 | 4 | 6 INPUTP | 9 | 152 | 155 | 91 | 107 | 98 | 99 | 101 | 157 | 97 EXPORTS | 1 | 11 | 2 EQ | 10 | LAN_CFG<4> = Gnd; LAN_CFG<4>.OE = Gnd; ROM_B_0_OBUF$BUF4.EXP = !AS & !UDS & !A<5> & A<1> & !A<6> & !A<3> & A<2> & AUTOCONFIG_Z2_ACCESS # !AS & !LDS & !A<5> & !A<4> & A<1> & !A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS # !AS & !LDS & !A<5> & !A<4> & A<6> & !A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS # !AS & !LDS & !A<4> & A<1> & !A<6> & !A<3> & A<2> & AUTOCONFIG_Z2_ACCESS MACROCELL | 1 | 7 | ROM_B_0_OBUF$BUF5 ATTRIBUTES | 265986 | 0 INPUTS | 0 EQ | 2 | LAN_CFG<3> = Gnd; LAN_CFG<3>.OE = Gnd; MACROCELL | 5 | 1 | ROM_B_0_OBUF$BUF6 ATTRIBUTES | 265986 | 0 INPUTS | 0 EQ | 2 | LAN_CFG<2> = Gnd; LAN_CFG<2>.OE = Gnd; MACROCELL | 1 | 5 | ROM_B_0_OBUF$BUF7 ATTRIBUTES | 265986 | 0 INPUTS | 0 EQ | 2 | LAN_CFG<1> = Gnd; LAN_CFG<1>.OE = Gnd; MACROCELL | 10 | 13 | ROM_B_0_OBUF ATTRIBUTES | 264962 | 0 OUTPUTMC | 1 | 10 | 14 INPUTS | 8 | D<8>.PIN | UDS | DQ_SWAP | LAN_SM_FSM_FFd3 | LAN_SM_FSM_FFd4 | LDS | A<16>.PIN | A<8>.PIN INPUTMC | 3 | 8 | 1 | 0 | 10 | 14 | 3 INPUTP | 5 | 32 | 155 | 157 | 175 | 106 EXPORTS | 1 | 10 | 14 EQ | 9 | ROM_B<1> = Gnd; ROM_B_0_OBUF.EXP = D<8>.PIN & !UDS & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # D<8>.PIN & !LDS & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # A<16>.PIN & UDS & LDS & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # UDS & LDS & DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 & A<8>.PIN MACROCELL | 10 | 11 | ROM_B_0_OBUF$BUF0 ATTRIBUTES | 264962 | 0 INPUTS | 0 EQ | 1 | ROM_B<0> = Gnd; MACROCELL | 4 | 3 | $OpTx$FX_DC$107 ATTRIBUTES | 133888 | 0 OUTPUTMC | 17 | 8 | 10 | 15 | 5 | 15 | 2 | 15 | 1 | 14 | 16 | 14 | 14 | 14 | 13 | 8 | 13 | 8 | 16 | 10 | 2 | 10 | 4 | 10 | 9 | 10 | 10 | 12 | 7 | 15 | 10 | 15 | 7 | 4 | 2 INPUTS | 6 | LAN_ACCESS | CP_BASEADR<6> | A<22>.PIN | CP_BASEADR<7> | A<23>.PIN | ROM_OE_OBUF.EXP INPUTMC | 4 | 8 | 8 | 9 | 14 | 13 | 5 | 4 | 4 INPUTP | 2 | 162 | 161 EXPORTS | 1 | 4 | 2 IMPORTS | 1 | 4 | 4 EQ | 7 | $OpTx$FX_DC$107 = !LAN_ACCESS ;Imported pterms FB5_5 # UDS & LDS & DS1 & DS0; $OpTx$FX_DC$107.EXP = CP_BASEADR<6> & !A<22>.PIN # !CP_BASEADR<6> & A<22>.PIN # CP_BASEADR<7> & !A<23>.PIN # !CP_BASEADR<7> & A<23>.PIN MACROCELL | 2 | 8 | SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF ATTRIBUTES | 133888 | 0 OUTPUTMC | 33 | 7 | 15 | 7 | 14 | 13 | 4 | 13 | 3 | 13 | 9 | 13 | 8 | 13 | 7 | 13 | 0 | 9 | 17 | 9 | 15 | 9 | 14 | 13 | 5 | 3 | 17 | 3 | 16 | 3 | 15 | 3 | 14 | 9 | 12 | 9 | 8 | 9 | 6 | 9 | 3 | 8 | 14 | 13 | 1 | 13 | 15 | 13 | 11 | 11 | 15 | 11 | 2 | 11 | 5 | 8 | 12 | 8 | 11 | 8 | 5 | 11 | 8 | 14 | 2 | 2 | 11 INPUTS | 2 | C1 | C3 INPUTP | 2 | 188 | 187 EQ | 2 | SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF = C1 $ C3; MACROCELL | 4 | 7 | $OpTx$FX_DC$117__$INT ATTRIBUTES | 133888 | 0 OUTPUTMC | 17 | 9 | 16 | 11 | 9 | 9 | 1 | 9 | 9 | 9 | 13 | 11 | 11 | 9 | 2 | 7 | 1 | 11 | 7 | 7 | 2 | 11 | 4 | 9 | 5 | 9 | 4 | 9 | 7 | 9 | 11 | 9 | 10 | 4 | 8 INPUTS | 11 | RESET | LAN_ACCESS | FCS | RW | AS | UDS | LDS | DS1 | DS0 | AUTOCONFIG_Z2_ACCESS | AUTOCONFIG_Z2_ACCESS.EXP INPUTMC | 3 | 8 | 8 | 4 | 6 | 4 | 6 INPUTP | 8 | 263 | 147 | 158 | 152 | 155 | 157 | 148 | 170 EXPORTS | 1 | 4 | 8 IMPORTS | 1 | 4 | 6 EQ | 7 | $OpTx$FX_DC$117__$INT = RESET & FCS # RESET & RW # RESET & !LAN_ACCESS ;Imported pterms FB5_7 # RESET & UDS & LDS & DS1 & DS0; $OpTx$FX_DC$117__$INT.EXP = AS & UDS & LDS & DS1 & DS0 # UDS & LDS & DS1 & DS0 & !AUTOCONFIG_Z2_ACCESS MACROCELL | 4 | 8 | D_9_IOBUFE/D_9_IOBUFE_TRST__$INT ATTRIBUTES | 133888 | 0 OUTPUTMC | 16 | 3 | 1 | 4 | 13 | 4 | 14 | 4 | 16 | 6 | 2 | 6 | 4 | 6 | 11 | 1 | 14 | 4 | 9 | 1 | 11 | 0 | 5 | 0 | 4 | 1 | 9 | 1 | 13 | 1 | 16 | 4 | 11 INPUTS | 7 | RW | FCS | AUTOCONFIG_Z2_ACCESS | AS | LAN_ACCESS | AUTOCONFIG_Z3_ACCESS | $OpTx$FX_DC$117__$INT.EXP INPUTMC | 4 | 4 | 6 | 8 | 8 | 7 | 13 | 4 | 7 INPUTP | 3 | 158 | 147 | 152 IMPORTS | 1 | 4 | 7 EQ | 9 | D_9_IOBUFE/D_9_IOBUFE_TRST__$INT = !RW # AS & FCS # FCS & !AUTOCONFIG_Z2_ACCESS # AS & !LAN_ACCESS & !AUTOCONFIG_Z3_ACCESS # !LAN_ACCESS & !AUTOCONFIG_Z2_ACCESS & !AUTOCONFIG_Z3_ACCESS ;Imported pterms FB5_8 # AS & UDS & LDS & DS1 & DS0 # UDS & LDS & DS1 & DS0 & !AUTOCONFIG_Z2_ACCESS; MACROCELL | 2 | 0 | $OpTx$INV$215 ATTRIBUTES | 133888 | 0 OUTPUTMC | 2 | 8 | 1 | 8 | 8 INPUTS | 8 | LAN_BASEADR<5> | A<21>.PIN | A<17>.PIN | LAN_BASEADR<1> | LAN_BASEADR<7> | A<23>.PIN | IDE_W_OBUF.EXP | EXP25_.EXP INPUTMC | 5 | 6 | 10 | 1 | 0 | 6 | 14 | 2 | 1 | 2 | 17 INPUTP | 3 | 163 | 172 | 161 IMPORTS | 2 | 2 | 1 | 2 | 17 EQ | 19 | $OpTx$INV$215 = A<17>.PIN & !LAN_BASEADR<1> # !A<17>.PIN & LAN_BASEADR<1> # LAN_BASEADR<5> & !A<21>.PIN # !LAN_BASEADR<5> & A<21>.PIN # !LAN_BASEADR<7> & A<23>.PIN ;Imported pterms FB3_2 # A<20>.PIN & !LAN_BASEADR<4> # !A<20>.PIN & LAN_BASEADR<4> # A<19>.PIN & !LAN_BASEADR<3> # A<16>.PIN & !LAN_BASEADR<0> # !A<16>.PIN & LAN_BASEADR<0> ;Imported pterms FB3_18 # D<14>.PIN & !LAN_BASEADR<14> # !D<14>.PIN & LAN_BASEADR<14> # A<18>.PIN & !LAN_BASEADR<2> # !A<18>.PIN & LAN_BASEADR<2> # LAN_BASEADR<7> & !A<23>.PIN ;Imported pterms FB3_17 # !A<19>.PIN & LAN_BASEADR<3>; MACROCELL | 4 | 17 | ROM_B_0_OBUF$BUF2/ROM_B_0_OBUF$BUF2_TRST ATTRIBUTES | 133888 | 0 OUTPUTMC | 2 | 13 | 2 | 4 | 16 INPUTS | 8 | FCS | LAN_ACCESS | AUTOCONFIG_Z3_ACCESS | LDS | RW | D_OUT<4> | DS1 | DS0 INPUTMC | 3 | 8 | 8 | 7 | 13 | 3 | 10 INPUTP | 5 | 147 | 157 | 158 | 148 | 170 EXPORTS | 1 | 4 | 16 EQ | 8 | ROM_B_0_OBUF$BUF2/ROM_B_0_OBUF$BUF2_TRST = !FCS & LAN_ACCESS # !FCS & AUTOCONFIG_Z3_ACCESS; ROM_B_0_OBUF$BUF2/ROM_B_0_OBUF$BUF2_TRST.EXP = !LDS & !FCS & RW & !LAN_ACCESS & AUTOCONFIG_Z3_ACCESS & D_OUT<4> # !DS1 & !FCS & RW & !LAN_ACCESS & AUTOCONFIG_Z3_ACCESS & D_OUT<4> # !DS0 & !FCS & RW & !LAN_ACCESS & AUTOCONFIG_Z3_ACCESS & D_OUT<4> MACROCELL | 2 | 10 | ROM_B_0_OBUF$BUF8/ROM_B_0_OBUF$BUF8_TRST ATTRIBUTES | 133888 | 0 OUTPUTMC | 1 | 2 | 13 INPUTS | 3 | CP_IRQ | LAN_INT_ENABLE | LAN_IRQ_OUT INPUTMC | 2 | 6 | 15 | 5 | 12 INPUTP | 1 | 59 EQ | 2 | ROM_B_0_OBUF$BUF8/ROM_B_0_OBUF$BUF8_TRST = !CP_IRQ # LAN_INT_ENABLE & !LAN_IRQ_OUT; MACROCELL | 2 | 9 | ROM_B_0_OBUF$BUF9/ROM_B_0_OBUF$BUF9_TRST__$INT ATTRIBUTES | 133888 | 0 OUTPUTMC | 1 | 14 | 11 INPUTS | 4 | FCS | AUTOCONFIG_Z3_ACCESS | CONFIG_READY | LAN_READY INPUTMC | 3 | 7 | 13 | 8 | 6 | 14 | 15 INPUTP | 1 | 147 EQ | 2 | ROM_B_0_OBUF$BUF9/ROM_B_0_OBUF$BUF9_TRST__$INT = FCS # !AUTOCONFIG_Z3_ACCESS & !CONFIG_READY & !LAN_READY; MACROCELL | 0 | 2 | EXP22_ ATTRIBUTES | 2048 | 0 OUTPUTMC | 1 | 0 | 1 INPUTS | 8 | UDS | LAN_SM_FSM_FFd3 | LAN_SM_FSM_FFd4 | LDS | DS1 | DS0 | LAN_SM_FSM_FFd2 | LAN_SM_FSM_FFd1 INPUTMC | 4 | 0 | 10 | 14 | 3 | 0 | 1 | 12 | 4 INPUTP | 4 | 155 | 157 | 148 | 170 EXPORTS | 1 | 0 | 1 EQ | 5 | EXP22_.EXP = !UDS & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # !LDS & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # DS1 & DS0 & LAN_SM_FSM_FFd2 # !LAN_SM_FSM_FFd3 & LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1 MACROCELL | 0 | 17 | EXP23_ ATTRIBUTES | 2048 | 0 OUTPUTMC | 1 | 0 | 0 INPUTS | 11 | D<11>.PIN | UDS | DQ_SWAP | LAN_SM_FSM_FFd3 | LAN_SM_FSM_FFd4 | LDS | A<19>.PIN | LAN_SM_FSM_FFd2 | LAN_SM_FSM_FFd1 | D<3>.PIN | A<11>.PIN INPUTMC | 5 | 8 | 1 | 0 | 10 | 14 | 3 | 0 | 1 | 12 | 4 INPUTP | 6 | 77 | 155 | 157 | 169 | 28 | 114 EXPORTS | 1 | 0 | 0 EQ | 10 | EXP23_.EXP = D<11>.PIN & !UDS & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # D<11>.PIN & !LDS & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # A<19>.PIN & !DQ_SWAP & !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1 # !UDS & D<3>.PIN & DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # DQ_SWAP & !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1 & A<11>.PIN MACROCELL | 2 | 2 | EXP24_ ATTRIBUTES | 2048 | 0 OUTPUTMC | 1 | 2 | 1 INPUTS | 2 | AS | IDE_W_S INPUTMC | 1 | 8 | 11 INPUTP | 1 | 152 EXPORTS | 1 | 2 | 1 EQ | 1 | EXP24_.EXP = !AS & !IDE_W_S MACROCELL | 2 | 17 | EXP25_ ATTRIBUTES | 2048 | 0 OUTPUTMC | 1 | 2 | 0 INPUTS | 7 | D<14>.PIN | LAN_BASEADR<14> | A<18>.PIN | LAN_BASEADR<2> | LAN_BASEADR<7> | A<23>.PIN | Z3_ADR<6>.EXP INPUTMC | 4 | 1 | 6 | 6 | 7 | 6 | 14 | 2 | 16 INPUTP | 3 | 81 | 171 | 161 EXPORTS | 1 | 2 | 0 IMPORTS | 1 | 2 | 16 EQ | 7 | EXP25_.EXP = D<14>.PIN & !LAN_BASEADR<14> # !D<14>.PIN & LAN_BASEADR<14> # A<18>.PIN & !LAN_BASEADR<2> # !A<18>.PIN & LAN_BASEADR<2> # LAN_BASEADR<7> & !A<23>.PIN ;Imported pterms FB3_17 # !A<19>.PIN & LAN_BASEADR<3> MACROCELL | 4 | 0 | EXP26_ ATTRIBUTES | 2048 | 0 OUTPUTMC | 1 | 4 | 1 INPUTS | 6 | A<19>.PIN | CP_BASEADR<3> | A<18>.PIN | CP_BASEADR<2> | A<17>.PIN | CP_BASEADR<1> INPUTMC | 3 | 13 | 0 | 13 | 7 | 13 | 8 INPUTP | 3 | 169 | 171 | 172 EXPORTS | 1 | 4 | 1 EQ | 5 | EXP26_.EXP = A<19>.PIN & !CP_BASEADR<3> # A<18>.PIN & !CP_BASEADR<2> # !A<18>.PIN & CP_BASEADR<2> # A<17>.PIN & !CP_BASEADR<1> # !A<17>.PIN & CP_BASEADR<1> MACROCELL | 4 | 2 | EXP27_ ATTRIBUTES | 2048 | 0 OUTPUTMC | 1 | 4 | 1 INPUTS | 7 | A<20>.PIN | CP_BASEADR<4> | A<19>.PIN | CP_BASEADR<3> | CP_BASEADR<5> | A<21>.PIN | $OpTx$FX_DC$107.EXP INPUTMC | 4 | 9 | 17 | 13 | 0 | 9 | 15 | 4 | 3 INPUTP | 3 | 167 | 169 | 163 EXPORTS | 1 | 4 | 1 IMPORTS | 1 | 4 | 3 EQ | 10 | EXP27_.EXP = A<20>.PIN & !CP_BASEADR<4> # !A<20>.PIN & CP_BASEADR<4> # !A<19>.PIN & CP_BASEADR<3> # CP_BASEADR<5> & !A<21>.PIN # !CP_BASEADR<5> & A<21>.PIN ;Imported pterms FB5_4 # CP_BASEADR<6> & !A<22>.PIN # !CP_BASEADR<6> & A<22>.PIN # CP_BASEADR<7> & !A<23>.PIN # !CP_BASEADR<7> & A<23>.PIN MACROCELL | 4 | 10 | EXP28_ ATTRIBUTES | 2048 | 0 OUTPUTMC | 1 | 4 | 11 INPUTS | 6 | Z3_DATA<25> | LAN_ACCESS | UDS | LDS | DS1 | DS0 INPUTMC | 2 | 15 | 6 | 8 | 8 INPUTP | 4 | 155 | 157 | 148 | 170 EXPORTS | 1 | 4 | 11 EQ | 2 | EXP28_.EXP = Z3_DATA<25> & LAN_ACCESS # UDS & LDS & DS1 & DS0 MACROCELL | 4 | 12 | EXP29_ ATTRIBUTES | 2048 | 0 OUTPUTMC | 1 | 4 | 13 INPUTS | 8 | Z3_DATA<26> | LAN_ACCESS | AUTOCONFIG_Z3_ACCESS | D_OUT<2> | UDS | LDS | DS1 | DS0 INPUTMC | 4 | 15 | 4 | 8 | 8 | 7 | 13 | 3 | 6 INPUTP | 4 | 155 | 157 | 148 | 170 EXPORTS | 1 | 4 | 13 EQ | 4 | EXP29_.EXP = Z3_DATA<26> & LAN_ACCESS # !LAN_ACCESS & !AUTOCONFIG_Z3_ACCESS # !LAN_ACCESS & D_OUT<2> # UDS & LDS & DS1 & DS0 MACROCELL | 4 | 15 | EXP30_ ATTRIBUTES | 2048 | 0 OUTPUTMC | 1 | 4 | 16 INPUTS | 10 | UDS | FCS | Z3_DATA<28> | RW | LAN_ACCESS | LDS | DS1 | DS0 | AUTOCONFIG_Z3_ACCESS | D_OUT<4> INPUTMC | 4 | 10 | 3 | 8 | 8 | 7 | 13 | 3 | 10 INPUTP | 6 | 155 | 147 | 158 | 157 | 148 | 170 EXPORTS | 1 | 4 | 16 EQ | 6 | EXP30_.EXP = !UDS & !FCS & Z3_DATA<28> & RW & LAN_ACCESS # !LDS & !FCS & Z3_DATA<28> & RW & LAN_ACCESS # !DS1 & !FCS & Z3_DATA<28> & RW & LAN_ACCESS # !DS0 & !FCS & Z3_DATA<28> & RW & LAN_ACCESS # !UDS & !FCS & RW & !LAN_ACCESS & AUTOCONFIG_Z3_ACCESS & D_OUT<4> MACROCELL | 6 | 1 | EXP31_ ATTRIBUTES | 2048 | 0 OUTPUTMC | 1 | 6 | 2 INPUTS | 11 | UDS | FCS | Z3_DATA<29> | RW | LAN_ACCESS | LDS | DS1 | DS0 | AUTOCONFIG_Z3_ACCESS | D_OUT<5> | LAN_SM_RST.EXP INPUTMC | 5 | 10 | 1 | 8 | 8 | 7 | 13 | 3 | 9 | 6 | 0 INPUTP | 6 | 155 | 147 | 158 | 157 | 148 | 170 EXPORTS | 1 | 6 | 2 IMPORTS | 1 | 6 | 0 EQ | 9 | EXP31_.EXP = !UDS & !FCS & Z3_DATA<29> & RW & LAN_ACCESS # !LDS & !FCS & Z3_DATA<29> & RW & LAN_ACCESS # !DS1 & !FCS & Z3_DATA<29> & RW & LAN_ACCESS # !DS0 & !FCS & Z3_DATA<29> & RW & LAN_ACCESS # !UDS & !FCS & RW & !LAN_ACCESS & AUTOCONFIG_Z3_ACCESS & D_OUT<5> ;Imported pterms FB7_1 # !LDS & !FCS & RW & !LAN_ACCESS & AUTOCONFIG_Z3_ACCESS & D_OUT<5> MACROCELL | 6 | 5 | EXP32_ ATTRIBUTES | 2048 | 0 OUTPUTMC | 1 | 6 | 4 INPUTS | 11 | UDS | FCS | Z3_DATA<30> | RW | LAN_ACCESS | LDS | DS1 | DS0 | AUTOCONFIG_Z3_ACCESS | D_OUT<6> | SHUT_UP.EXP INPUTMC | 5 | 10 | 0 | 8 | 8 | 7 | 13 | 3 | 8 | 6 | 6 INPUTP | 6 | 155 | 147 | 158 | 157 | 148 | 170 EXPORTS | 1 | 6 | 4 IMPORTS | 1 | 6 | 6 EQ | 13 | EXP32_.EXP = !UDS & !FCS & Z3_DATA<30> & RW & LAN_ACCESS # !LDS & !FCS & Z3_DATA<30> & RW & LAN_ACCESS # !DS1 & !FCS & Z3_DATA<30> & RW & LAN_ACCESS # !DS0 & !FCS & Z3_DATA<30> & RW & LAN_ACCESS # !UDS & !FCS & RW & !LAN_ACCESS & AUTOCONFIG_Z3_ACCESS & D_OUT<6> ;Imported pterms FB7_7 # !LDS & !FCS & RW & !LAN_ACCESS & AUTOCONFIG_Z3_ACCESS & D_OUT<6> # !DS1 & !FCS & RW & !LAN_ACCESS & AUTOCONFIG_Z3_ACCESS & D_OUT<6> # !DS0 & !FCS & RW & !LAN_ACCESS & AUTOCONFIG_Z3_ACCESS & D_OUT<6> MACROCELL | 6 | 12 | EXP33_ ATTRIBUTES | 2048 | 0 OUTPUTMC | 1 | 6 | 11 INPUTS | 11 | LDS | FCS | Z3_DATA<31> | RW | LAN_ACCESS | DS1 | UDS | AUTOCONFIG_Z3_ACCESS | D_OUT<7> | DS0 | LAN_BASEADR<6>.EXP INPUTMC | 5 | 12 | 2 | 8 | 8 | 7 | 13 | 3 | 0 | 6 | 13 INPUTP | 6 | 157 | 147 | 158 | 148 | 155 | 170 EXPORTS | 1 | 6 | 11 IMPORTS | 1 | 6 | 13 EQ | 11 | EXP33_.EXP = !LDS & !FCS & Z3_DATA<31> & RW & LAN_ACCESS # !DS1 & !FCS & Z3_DATA<31> & RW & LAN_ACCESS # !UDS & !FCS & RW & !LAN_ACCESS & AUTOCONFIG_Z3_ACCESS & D_OUT<7> # !DS1 & !FCS & RW & !LAN_ACCESS & AUTOCONFIG_Z3_ACCESS & D_OUT<7> # !DS0 & !FCS & RW & !LAN_ACCESS & AUTOCONFIG_Z3_ACCESS & D_OUT<7> ;Imported pterms FB7_14 # !LDS & !FCS & RW & !LAN_ACCESS & AUTOCONFIG_Z3_ACCESS & D_OUT<7> MACROCELL | 7 | 0 | EXP34_ ATTRIBUTES | 2048 | 0 OUTPUTMC | 1 | 7 | 17 INPUTS | 7 | A<20>.PIN | IDE_BASEADR<4> | A<19>.PIN | IDE_BASEADR<3> | IDE_BASEADR<5> | A<21>.PIN | DQ_12_IOBUFE.EXP INPUTMC | 4 | 9 | 12 | 3 | 14 | 9 | 8 | 7 | 1 INPUTP | 3 | 167 | 169 | 163 EXPORTS | 1 | 7 | 17 IMPORTS | 1 | 7 | 1 EQ | 9 | EXP34_.EXP = A<20>.PIN & !IDE_BASEADR<4> # !A<20>.PIN & IDE_BASEADR<4> # !A<19>.PIN & IDE_BASEADR<3> # IDE_BASEADR<5> & !A<21>.PIN # !IDE_BASEADR<5> & A<21>.PIN ;Imported pterms FB8_2 # IDE_BASEADR<6> & !A<22>.PIN # !IDE_BASEADR<6> & A<22>.PIN # IDE_BASEADR<7> & !A<23>.PIN MACROCELL | 7 | 16 | EXP35_ ATTRIBUTES | 2048 | 0 OUTPUTMC | 1 | 7 | 17 INPUTS | 7 | A<19>.PIN | IDE_BASEADR<3> | A<18>.PIN | IDE_BASEADR<2> | A<17>.PIN | IDE_BASEADR<1> | AUTO_CONFIG_Z2_DONE<0>.EXP INPUTMC | 4 | 3 | 14 | 3 | 15 | 3 | 16 | 7 | 15 INPUTP | 3 | 169 | 171 | 172 EXPORTS | 1 | 7 | 17 IMPORTS | 1 | 7 | 15 EQ | 7 | EXP35_.EXP = A<19>.PIN & !IDE_BASEADR<3> # A<18>.PIN & !IDE_BASEADR<2> # !A<18>.PIN & IDE_BASEADR<2> # A<17>.PIN & !IDE_BASEADR<1> # !A<17>.PIN & IDE_BASEADR<1> ;Imported pterms FB8_16 # !IDE_BASEADR<7> & A<23>.PIN MACROCELL | 8 | 0 | EXP36_ ATTRIBUTES | 2048 | 0 OUTPUTMC | 1 | 8 | 1 INPUTS | 7 | A<13>.PIN | A<14>.PIN | D<9>.PIN | LAN_BASEADR<9> | D<11>.PIN | LAN_BASEADR<11> | EXP40_.EXP INPUTMC | 3 | 6 | 17 | 1 | 12 | 8 | 17 INPUTP | 4 | 123 | 125 | 73 | 77 EXPORTS | 1 | 8 | 1 IMPORTS | 1 | 8 | 17 EQ | 11 | EXP36_.EXP = !A<13>.PIN # !A<14>.PIN # D<9>.PIN & !LAN_BASEADR<9> # !D<9>.PIN & LAN_BASEADR<9> # D<11>.PIN & !LAN_BASEADR<11> ;Imported pterms FB9_18 # D<8>.PIN & !LAN_BASEADR<8> # !D<8>.PIN & LAN_BASEADR<8> # D<13>.PIN & !LAN_BASEADR<13> # D<12>.PIN & !LAN_BASEADR<12> # !D<12>.PIN & LAN_BASEADR<12> MACROCELL | 8 | 2 | EXP37_ ATTRIBUTES | 2048 | 0 OUTPUTMC | 1 | 8 | 1 INPUTS | 7 | D<11>.PIN | LAN_BASEADR<11> | D<10>.PIN | LAN_BASEADR<10> | D<15>.PIN | LAN_BASEADR<15> | Z3_ADR<12>.EXP INPUTMC | 4 | 1 | 12 | 1 | 15 | 1 | 3 | 8 | 3 INPUTP | 3 | 77 | 74 | 89 EXPORTS | 1 | 8 | 1 IMPORTS | 1 | 8 | 3 EQ | 9 | EXP37_.EXP = !D<11>.PIN & LAN_BASEADR<11> # D<10>.PIN & !LAN_BASEADR<10> # !D<10>.PIN & LAN_BASEADR<10> # D<15>.PIN & !LAN_BASEADR<15> # !D<15>.PIN & LAN_BASEADR<15> ;Imported pterms FB9_4 # !D<13>.PIN & LAN_BASEADR<13> # LAN_BASEADR<6> & !A<22>.PIN # !LAN_BASEADR<6> & A<22>.PIN MACROCELL | 8 | 7 | EXP38_ ATTRIBUTES | 2048 | 0 OUTPUTMC | 1 | 8 | 8 INPUTS | 7 | D<9>.PIN | LAN_BASEADR<9> | D<11>.PIN | LAN_BASEADR<11> | D<15>.PIN | LAN_BASEADR<15> | CONFIG_READY.EXP INPUTMC | 4 | 6 | 17 | 1 | 12 | 1 | 3 | 8 | 6 INPUTP | 3 | 73 | 77 | 89 EXPORTS | 1 | 8 | 8 IMPORTS | 1 | 8 | 6 EQ | 10 | EXP38_.EXP = D<9>.PIN & !LAN_BASEADR<9> # !D<9>.PIN & LAN_BASEADR<9> # D<11>.PIN & !LAN_BASEADR<11> # !D<11>.PIN & LAN_BASEADR<11> # D<15>.PIN & !LAN_BASEADR<15> ;Imported pterms FB9_7 # D<8>.PIN & !LAN_BASEADR<8> # !D<8>.PIN & LAN_BASEADR<8> # D<13>.PIN & !LAN_BASEADR<13> # !D<13>.PIN & LAN_BASEADR<13> MACROCELL | 8 | 9 | EXP39_ ATTRIBUTES | 2048 | 0 OUTPUTMC | 1 | 8 | 8 INPUTS | 7 | D<12>.PIN | LAN_BASEADR<12> | D<10>.PIN | LAN_BASEADR<10> | D<15>.PIN | LAN_BASEADR<15> | Z3_DATA<0>.EXP INPUTMC | 4 | 1 | 10 | 1 | 15 | 1 | 3 | 8 | 10 INPUTP | 3 | 78 | 74 | 89 EXPORTS | 1 | 8 | 8 IMPORTS | 1 | 8 | 10 EQ | 8 | EXP39_.EXP = D<12>.PIN & !LAN_BASEADR<12> # !D<12>.PIN & LAN_BASEADR<12> # D<10>.PIN & !LAN_BASEADR<10> # !D<10>.PIN & LAN_BASEADR<10> # !D<15>.PIN & LAN_BASEADR<15> ;Imported pterms FB9_11 # LAN_BASEADR<6> & !A<22>.PIN # !LAN_BASEADR<6> & A<22>.PIN MACROCELL | 8 | 17 | EXP40_ ATTRIBUTES | 2048 | 0 OUTPUTMC | 1 | 8 | 0 INPUTS | 6 | D<8>.PIN | LAN_BASEADR<8> | D<13>.PIN | LAN_BASEADR<13> | D<12>.PIN | LAN_BASEADR<12> INPUTMC | 3 | 6 | 16 | 1 | 8 | 1 | 10 INPUTP | 3 | 32 | 80 | 78 EXPORTS | 1 | 8 | 0 EQ | 5 | EXP40_.EXP = D<8>.PIN & !LAN_BASEADR<8> # !D<8>.PIN & LAN_BASEADR<8> # D<13>.PIN & !LAN_BASEADR<13> # D<12>.PIN & !LAN_BASEADR<12> # !D<12>.PIN & LAN_BASEADR<12> MACROCELL | 10 | 14 | EXP41_ ATTRIBUTES | 2048 | 0 OUTPUTMC | 1 | 10 | 15 INPUTS | 12 | LAN_SM_FSM_FFd3 | LAN_SM_FSM_FFd2 | DQ_DATA<8> | A<16>.PIN | DQ_SWAP | LAN_SM_FSM_FFd4 | LAN_SM_FSM_FFd1 | UDS | D<0>.PIN | LDS | A<8>.PIN | ROM_B_0_OBUF.EXP INPUTMC | 7 | 0 | 10 | 0 | 1 | 10 | 15 | 8 | 1 | 14 | 3 | 12 | 4 | 10 | 13 INPUTP | 5 | 175 | 155 | 4 | 157 | 106 EXPORTS | 1 | 10 | 15 IMPORTS | 1 | 10 | 13 EQ | 18 | EXP41_.EXP = LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd2 & DQ_DATA<8> # A<16>.PIN & !DQ_SWAP & !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1 # !UDS & D<0>.PIN & DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # !LDS & D<0>.PIN & DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # DQ_SWAP & !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1 & A<8>.PIN ;Imported pterms FB11_14 # D<8>.PIN & !UDS & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # D<8>.PIN & !LDS & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # A<16>.PIN & UDS & LDS & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # UDS & LDS & DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 & A<8>.PIN MACROCELL | 11 | 3 | EXP42_ ATTRIBUTES | 2048 | 0 OUTPUTMC | 1 | 11 | 2 INPUTS | 11 | AS | LDS | A<5> | A<1> | A<6> | A<3> | A<2> | AUTOCONFIG_Z2_ACCESS | AUTO_CONFIG_Z2_DONE<0> | UDS | A<4> INPUTMC | 2 | 4 | 6 | 7 | 15 INPUTP | 9 | 152 | 157 | 91 | 107 | 98 | 99 | 101 | 155 | 97 EXPORTS | 1 | 11 | 2 EQ | 10 | EXP42_.EXP = !AS & !LDS & !A<5> & A<1> & !A<6> & !A<3> & A<2> & AUTOCONFIG_Z2_ACCESS # !AS & !AUTO_CONFIG_Z2_DONE<0> & !UDS & !A<5> & !A<4> & !A<6> & !A<3> & A<2> & AUTOCONFIG_Z2_ACCESS # !AS & !AUTO_CONFIG_Z2_DONE<0> & !LDS & !A<5> & !A<4> & !A<6> & !A<3> & A<2> & AUTOCONFIG_Z2_ACCESS # !AS & !UDS & !A<5> & A<4> & !A<1> & !A<6> & A<3> & A<2> & AUTOCONFIG_Z2_ACCESS # !AS & !LDS & !A<5> & A<4> & !A<1> & !A<6> & A<3> & A<2> & AUTOCONFIG_Z2_ACCESS MACROCELL | 11 | 6 | EXP43_ ATTRIBUTES | 2048 | 0 OUTPUTMC | 1 | 11 | 5 INPUTS | 12 | AS | AUTO_CONFIG_Z2_DONE<0> | LDS | A<5> | A<1> | A<6> | A<3> | AUTOCONFIG_Z2_ACCESS | A<4> | A<2> | UDS | DQ_13_IOBUFE.EXP INPUTMC | 3 | 7 | 15 | 4 | 6 | 11 | 7 INPUTP | 9 | 152 | 157 | 91 | 107 | 98 | 99 | 97 | 101 | 155 EXPORTS | 1 | 11 | 5 IMPORTS | 1 | 11 | 7 EQ | 13 | EXP43_.EXP = !AS & !AUTO_CONFIG_Z2_DONE<0> & !LDS & !A<5> & A<1> & !A<6> & !A<3> & AUTOCONFIG_Z2_ACCESS # !AS & !LDS & !A<5> & A<4> & A<1> & !A<6> & A<2> & AUTOCONFIG_Z2_ACCESS # !AS & !UDS & A<5> & !A<4> & !A<1> & !A<6> & !A<3> & A<2> & AUTOCONFIG_Z2_ACCESS # !AS & !UDS & !A<5> & A<4> & !A<1> & !A<6> & A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS # !AS & !LDS & A<5> & !A<4> & !A<1> & !A<6> & !A<3> & A<2> & AUTOCONFIG_Z2_ACCESS ;Imported pterms FB12_8 # !AS & !LDS & !A<5> & A<4> & !A<1> & !A<6> & A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS MACROCELL | 11 | 14 | EXP44_ ATTRIBUTES | 2048 | 0 OUTPUTMC | 1 | 11 | 15 INPUTS | 12 | AS | UDS | A<5> | A<4> | A<6> | A<3> | A<2> | AUTOCONFIG_Z2_ACCESS | LDS | A<1> | AUTO_CONFIG_Z2_DONE<0> | Z3_ADR<5>.EXP INPUTMC | 3 | 4 | 6 | 7 | 15 | 11 | 13 INPUTP | 9 | 152 | 155 | 91 | 97 | 98 | 99 | 101 | 157 | 107 EXPORTS | 1 | 11 | 15 IMPORTS | 1 | 11 | 13 EQ | 13 | EXP44_.EXP = !AS & !UDS & !A<5> & A<4> & !A<6> & A<3> & A<2> & AUTOCONFIG_Z2_ACCESS # !AS & !LDS & !A<5> & A<4> & !A<1> & !A<6> & A<3> & AUTOCONFIG_Z2_ACCESS # !AS & !LDS & !A<5> & A<4> & !A<6> & A<3> & A<2> & AUTOCONFIG_Z2_ACCESS # !AS & AUTO_CONFIG_Z2_DONE<0> & !UDS & !A<5> & !A<4> & A<1> & !A<6> & !A<3> & AUTOCONFIG_Z2_ACCESS # !AS & !AUTO_CONFIG_Z2_DONE<0> & !UDS & !A<5> & !A<4> & !A<1> & !A<6> & !A<3> & AUTOCONFIG_Z2_ACCESS ;Imported pterms FB12_14 # !AS & AUTO_CONFIG_Z2_DONE<0> & !LDS & !A<5> & A<4> & !A<1> & !A<6> & A<2> & AUTOCONFIG_Z2_ACCESS MACROCELL | 11 | 16 | EXP45_ ATTRIBUTES | 2048 | 0 OUTPUTMC | 1 | 11 | 15 INPUTS | 12 | AS | AUTO_CONFIG_Z2_DONE<0> | UDS | A<5> | A<4> | A<1> | A<6> | A<2> | AUTOCONFIG_Z2_ACCESS | LDS | A<3> | Z3_ADR_0.EXP INPUTMC | 3 | 7 | 15 | 4 | 6 | 11 | 17 INPUTP | 9 | 152 | 155 | 91 | 97 | 107 | 98 | 101 | 157 | 99 EXPORTS | 1 | 11 | 15 IMPORTS | 1 | 11 | 17 EQ | 15 | EXP45_.EXP = !AS & AUTO_CONFIG_Z2_DONE<0> & !UDS & !A<5> & A<4> & !A<1> & !A<6> & A<2> & AUTOCONFIG_Z2_ACCESS # !AS & AUTO_CONFIG_Z2_DONE<0> & !LDS & !A<5> & !A<4> & A<1> & !A<6> & !A<3> & AUTOCONFIG_Z2_ACCESS # !AS & !AUTO_CONFIG_Z2_DONE<0> & !UDS & !A<5> & A<1> & !A<6> & !A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS # !AS & !AUTO_CONFIG_Z2_DONE<0> & !LDS & !A<5> & !A<4> & !A<1> & !A<6> & !A<3> & AUTOCONFIG_Z2_ACCESS # !AS & !UDS & A<5> & !A<4> & !A<1> & !A<6> & !A<3> & A<2> & AUTOCONFIG_Z2_ACCESS ;Imported pterms FB12_18 # !AS & !AUTO_CONFIG_Z2_DONE<0> & !LDS & !A<5> & A<1> & !A<6> & !A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS # !AS & !LDS & A<5> & !A<4> & !A<1> & !A<6> & !A<3> & A<2> & AUTOCONFIG_Z2_ACCESS MACROCELL | 12 | 0 | EXP46_ ATTRIBUTES | 2048 | 0 OUTPUTMC | 1 | 12 | 17 INPUTS | 12 | LAN_SM_FSM_FFd3 | LAN_SM_FSM_FFd2 | DQ_DATA<13> | D<13>.PIN | UDS | DQ_SWAP | LAN_SM_FSM_FFd4 | LDS | A<21>.PIN | LAN_SM_FSM_FFd1 | A<13>.PIN | CP_RD_OBUF.EXP INPUTMC | 7 | 0 | 10 | 0 | 1 | 12 | 17 | 8 | 1 | 14 | 3 | 12 | 4 | 12 | 1 INPUTP | 5 | 80 | 155 | 157 | 163 | 123 EXPORTS | 1 | 12 | 17 IMPORTS | 1 | 12 | 1 EQ | 18 | EXP46_.EXP = LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd2 & DQ_DATA<13> # D<13>.PIN & !UDS & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # D<13>.PIN & !LDS & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # A<21>.PIN & !DQ_SWAP & !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1 # DQ_SWAP & !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1 & A<13>.PIN ;Imported pterms FB13_2 # !UDS & D<5>.PIN & DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # !LDS & D<5>.PIN & DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # UDS & LDS & A<21>.PIN & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # UDS & LDS & DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 & A<13>.PIN MACROCELL | 12 | 3 | EXP47_ ATTRIBUTES | 2048 | 0 OUTPUTMC | 1 | 12 | 4 INPUTS | 8 | RW | LAN_SM_FSM_FFd3 | LAN_SM_FSM_FFd4 | LAN_SM_FSM_FFd1 | LAN_SM_FSM_FFd2 | DS1 | DS0 | Z3_DATA<31>.EXP INPUTMC | 5 | 0 | 10 | 14 | 3 | 12 | 4 | 0 | 1 | 12 | 2 INPUTP | 3 | 158 | 148 | 170 EXPORTS | 1 | 12 | 4 IMPORTS | 1 | 12 | 2 EQ | 11 | EXP47_.EXP = !RW & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # LAN_SM_FSM_FFd3 & LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd1 # !LAN_SM_FSM_FFd3 & LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1 # DS1 & DS0 & !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd1 # !DS0 & !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1 ;Imported pterms FB13_3 # !DS1 & !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1 MACROCELL | 12 | 5 | EXP48_ ATTRIBUTES | 2048 | 0 OUTPUTMC | 1 | 12 | 6 INPUTS | 12 | D<14>.PIN | UDS | DQ_SWAP | LAN_SM_FSM_FFd3 | LAN_SM_FSM_FFd4 | LDS | D<6>.PIN | A<22>.PIN | LAN_SM_FSM_FFd2 | LAN_SM_FSM_FFd1 | A<14>.PIN | LAN_SM_FSM_FFd1.EXP INPUTMC | 6 | 8 | 1 | 0 | 10 | 14 | 3 | 0 | 1 | 12 | 4 | 12 | 4 INPUTP | 6 | 81 | 155 | 157 | 26 | 162 | 125 EXPORTS | 1 | 12 | 6 IMPORTS | 1 | 12 | 4 EQ | 17 | EXP48_.EXP = D<14>.PIN & !UDS & DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # D<14>.PIN & !LDS & DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # !UDS & D<6>.PIN & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # A<22>.PIN & DQ_SWAP & !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1 # !DQ_SWAP & !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1 & A<14>.PIN ;Imported pterms FB13_5 # !LDS & D<6>.PIN & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # UDS & LDS & A<22>.PIN & DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # UDS & LDS & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 & A<14>.PIN MACROCELL | 12 | 9 | EXP49_ ATTRIBUTES | 2048 | 0 OUTPUTMC | 1 | 12 | 10 INPUTS | 9 | D<13>.PIN | UDS | DQ_SWAP | LAN_SM_FSM_FFd3 | LAN_SM_FSM_FFd4 | LDS | D<5>.PIN | A<13>.PIN | Z3_DATA<23>.EXP INPUTMC | 4 | 8 | 1 | 0 | 10 | 14 | 3 | 12 | 8 INPUTP | 5 | 80 | 155 | 157 | 37 | 123 EXPORTS | 1 | 12 | 10 IMPORTS | 1 | 12 | 8 EQ | 13 | EXP49_.EXP = D<13>.PIN & !UDS & DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # D<13>.PIN & !LDS & DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # !UDS & D<5>.PIN & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # !LDS & D<5>.PIN & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # UDS & LDS & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 & A<13>.PIN ;Imported pterms FB13_9 # UDS & LDS & A<21>.PIN & DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 MACROCELL | 12 | 10 | EXP50_ ATTRIBUTES | 2048 | 0 OUTPUTMC | 1 | 12 | 11 INPUTS | 9 | LAN_SM_FSM_FFd4 | DQ_DATA<5> | LAN_SM_FSM_FFd3 | LAN_SM_FSM_FFd2 | A<21>.PIN | DQ_SWAP | LAN_SM_FSM_FFd1 | A<13>.PIN | EXP49_.EXP INPUTMC | 7 | 14 | 3 | 12 | 11 | 0 | 10 | 0 | 1 | 8 | 1 | 12 | 4 | 12 | 9 INPUTP | 2 | 163 | 123 EXPORTS | 1 | 12 | 11 IMPORTS | 1 | 12 | 9 EQ | 21 | EXP50_.EXP = LAN_SM_FSM_FFd4 & DQ_DATA<5> # LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd2 & DQ_DATA<5> # !LAN_SM_FSM_FFd3 & LAN_SM_FSM_FFd2 & DQ_DATA<5> # A<21>.PIN & DQ_SWAP & !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1 # !DQ_SWAP & !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1 & A<13>.PIN ;Imported pterms FB13_10 # D<13>.PIN & !UDS & DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # D<13>.PIN & !LDS & DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # !UDS & D<5>.PIN & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # !LDS & D<5>.PIN & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # UDS & LDS & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 & A<13>.PIN ;Imported pterms FB13_9 # UDS & LDS & A<21>.PIN & DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 MACROCELL | 12 | 15 | EXP51_ ATTRIBUTES | 2048 | 0 OUTPUTMC | 1 | 12 | 14 INPUTS | 9 | LAN_SM_FSM_FFd4 | DQ_DATA<14> | LAN_SM_FSM_FFd3 | LAN_SM_FSM_FFd2 | A<22>.PIN | DQ_SWAP | LAN_SM_FSM_FFd1 | A<14>.PIN | EXP52_.EXP INPUTMC | 7 | 14 | 3 | 12 | 14 | 0 | 10 | 0 | 1 | 8 | 1 | 12 | 4 | 12 | 16 INPUTP | 2 | 162 | 125 EXPORTS | 1 | 12 | 14 IMPORTS | 1 | 12 | 16 EQ | 21 | EXP51_.EXP = LAN_SM_FSM_FFd4 & DQ_DATA<14> # LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd2 & DQ_DATA<14> # !LAN_SM_FSM_FFd3 & LAN_SM_FSM_FFd2 & DQ_DATA<14> # A<22>.PIN & !DQ_SWAP & !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1 # DQ_SWAP & !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1 & A<14>.PIN ;Imported pterms FB13_17 # D<14>.PIN & !UDS & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # D<14>.PIN & !LDS & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # !UDS & D<6>.PIN & DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # !LDS & D<6>.PIN & DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # UDS & LDS & DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 & A<14>.PIN ;Imported pterms FB13_18 # UDS & LDS & A<22>.PIN & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 MACROCELL | 12 | 16 | EXP52_ ATTRIBUTES | 2048 | 0 OUTPUTMC | 1 | 12 | 15 INPUTS | 9 | D<14>.PIN | UDS | DQ_SWAP | LAN_SM_FSM_FFd3 | LAN_SM_FSM_FFd4 | LDS | D<6>.PIN | A<14>.PIN | DQ_DATA<13>.EXP INPUTMC | 4 | 8 | 1 | 0 | 10 | 14 | 3 | 12 | 17 INPUTP | 5 | 81 | 155 | 157 | 26 | 125 EXPORTS | 1 | 12 | 15 IMPORTS | 1 | 12 | 17 EQ | 13 | EXP52_.EXP = D<14>.PIN & !UDS & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # D<14>.PIN & !LDS & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # !UDS & D<6>.PIN & DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # !LDS & D<6>.PIN & DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # UDS & LDS & DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 & A<14>.PIN ;Imported pterms FB13_18 # UDS & LDS & A<22>.PIN & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 MACROCELL | 13 | 6 | EXP53_ ATTRIBUTES | 2048 | 0 OUTPUTMC | 1 | 13 | 7 INPUTS | 14 | D<10>.PIN | AS | AUTO_CONFIG_Z2_DONE<0> | UDS | CP_BASEADR<2> | A<5> | A<4> | A<1> | RW | A<6> | A<3> | A<2> | AUTOCONFIG_Z2_ACCESS | LDS INPUTMC | 3 | 7 | 15 | 13 | 7 | 4 | 6 INPUTP | 11 | 74 | 152 | 155 | 91 | 97 | 107 | 158 | 98 | 99 | 101 | 157 EXPORTS | 1 | 13 | 7 EQ | 9 | EXP53_.EXP = D<10>.PIN & !AS & !AUTO_CONFIG_Z2_DONE<0> & !UDS & !CP_BASEADR<2> & !A<5> & !A<4> & !A<1> & !RW & A<6> & A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS # D<10>.PIN & !AS & !AUTO_CONFIG_Z2_DONE<0> & !LDS & !CP_BASEADR<2> & !A<5> & !A<4> & !A<1> & !RW & A<6> & A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS # !D<10>.PIN & !AS & !AUTO_CONFIG_Z2_DONE<0> & !LDS & CP_BASEADR<2> & !A<5> & !A<4> & !A<1> & !RW & A<6> & A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS MACROCELL | 13 | 12 | EXP54_ ATTRIBUTES | 2048 | 0 OUTPUTMC | 1 | 13 | 11 INPUTS | 12 | AS | LDS | A<5> | A<4> | A<6> | A<3> | A<2> | AUTOCONFIG_Z2_ACCESS | AUTO_CONFIG_Z2_DONE<0> | UDS | A<1> | SLAVE_OBUF.EXP INPUTMC | 3 | 4 | 6 | 7 | 15 | 13 | 13 INPUTP | 9 | 152 | 157 | 91 | 97 | 98 | 99 | 101 | 155 | 107 EXPORTS | 1 | 13 | 11 IMPORTS | 1 | 13 | 13 EQ | 17 | EXP54_.EXP = !AS & !LDS & !A<5> & A<4> & !A<6> & A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS # !AS & !AUTO_CONFIG_Z2_DONE<0> & !UDS & !A<5> & !A<4> & !A<1> & !A<6> & !A<3> & AUTOCONFIG_Z2_ACCESS # !AS & !AUTO_CONFIG_Z2_DONE<0> & !UDS & !A<5> & !A<1> & !A<6> & !A<3> & A<2> & AUTOCONFIG_Z2_ACCESS # !AS & !AUTO_CONFIG_Z2_DONE<0> & !LDS & !A<5> & !A<4> & !A<1> & !A<6> & !A<3> & AUTOCONFIG_Z2_ACCESS # !AS & !AUTO_CONFIG_Z2_DONE<0> & !LDS & !A<5> & !A<1> & !A<6> & !A<3> & A<2> & AUTOCONFIG_Z2_ACCESS ;Imported pterms FB14_14 # !AS & AUTO_CONFIG_Z2_DONE<0> & !AUTO_CONFIG_Z2_DONE<1> & !UDS & A<5> & !A<4> & A<1> & !A<6> & A<2> & AUTOCONFIG_Z2_ACCESS # !AS & AUTO_CONFIG_Z2_DONE<0> & !AUTO_CONFIG_Z2_DONE<1> & !LDS & A<5> & !A<4> & A<1> & !A<6> & A<2> & AUTOCONFIG_Z2_ACCESS MACROCELL | 13 | 17 | EXP55_ ATTRIBUTES | 2048 | 0 OUTPUTMC | 1 | 13 | 0 INPUTS | 13 | D<11>.PIN | AS | AUTO_CONFIG_Z2_DONE<0> | LDS | CP_BASEADR<3> | A<5> | A<4> | A<1> | RW | A<6> | A<3> | A<2> | AUTOCONFIG_Z2_ACCESS INPUTMC | 3 | 7 | 15 | 13 | 0 | 4 | 6 INPUTP | 10 | 77 | 152 | 157 | 91 | 97 | 107 | 158 | 98 | 99 | 101 EXPORTS | 1 | 13 | 0 EQ | 3 | EXP55_.EXP = D<11>.PIN & !AS & !AUTO_CONFIG_Z2_DONE<0> & !LDS & !CP_BASEADR<3> & !A<5> & !A<4> & !A<1> & !RW & A<6> & A<3> & !A<2> & AUTOCONFIG_Z2_ACCESS MACROCELL | 14 | 1 | EXP56_ ATTRIBUTES | 2048 | 0 OUTPUTMC | 1 | 14 | 0 INPUTS | 9 | D<9>.PIN | UDS | DQ_SWAP | LAN_SM_FSM_FFd3 | LAN_SM_FSM_FFd4 | LDS | D<1>.PIN | A<17>.PIN | A<9>.PIN INPUTMC | 3 | 8 | 1 | 0 | 10 | 14 | 3 INPUTP | 6 | 73 | 155 | 157 | 30 | 172 | 108 EXPORTS | 1 | 14 | 0 EQ | 10 | EXP56_.EXP = D<9>.PIN & !UDS & DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # D<9>.PIN & !LDS & DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # !LDS & D<1>.PIN & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # A<17>.PIN & UDS & LDS & DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # UDS & LDS & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 & A<9>.PIN MACROCELL | 14 | 5 | EXP57_ ATTRIBUTES | 2048 | 0 OUTPUTMC | 1 | 14 | 4 INPUTS | 9 | D<9>.PIN | UDS | DQ_SWAP | LAN_SM_FSM_FFd3 | LAN_SM_FSM_FFd4 | LDS | D<1>.PIN | A<17>.PIN | A<9>.PIN INPUTMC | 3 | 8 | 1 | 0 | 10 | 14 | 3 INPUTP | 6 | 73 | 155 | 157 | 30 | 172 | 108 EXPORTS | 1 | 14 | 4 EQ | 10 | EXP57_.EXP = D<9>.PIN & !UDS & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # D<9>.PIN & !LDS & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # !LDS & D<1>.PIN & DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # A<17>.PIN & UDS & LDS & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # UDS & LDS & DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 & A<9>.PIN MACROCELL | 14 | 7 | EXP58_ ATTRIBUTES | 2048 | 0 OUTPUTMC | 1 | 14 | 8 INPUTS | 11 | D<15>.PIN | UDS | DQ_SWAP | LAN_SM_FSM_FFd3 | LAN_SM_FSM_FFd4 | LDS | D<7>.PIN | A<23>.PIN | LAN_SM_FSM_FFd2 | LAN_SM_FSM_FFd1 | LAN_WRH_S.EXP INPUTMC | 6 | 8 | 1 | 0 | 10 | 14 | 3 | 0 | 1 | 12 | 4 | 14 | 6 INPUTP | 5 | 89 | 155 | 157 | 29 | 161 EXPORTS | 1 | 14 | 8 IMPORTS | 1 | 14 | 6 EQ | 15 | EXP58_.EXP = D<15>.PIN & !UDS & DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # D<15>.PIN & !LDS & DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # !UDS & D<7>.PIN & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # !LDS & D<7>.PIN & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # A<23>.PIN & DQ_SWAP & !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1 ;Imported pterms FB15_7 # UDS & LDS & A<23>.PIN & DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # UDS & LDS & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 & A<15>.PIN MACROCELL | 14 | 8 | EXP59_ ATTRIBUTES | 2048 | 0 OUTPUTMC | 1 | 14 | 9 INPUTS | 8 | LAN_SM_FSM_FFd4 | DQ_DATA<7> | LAN_SM_FSM_FFd1 | LAN_SM_FSM_FFd3 | LAN_SM_FSM_FFd2 | DQ_SWAP | A<15>.PIN | EXP58_.EXP INPUTMC | 7 | 14 | 3 | 14 | 9 | 12 | 4 | 0 | 10 | 0 | 1 | 8 | 1 | 14 | 7 INPUTP | 1 | 139 EXPORTS | 1 | 14 | 9 IMPORTS | 1 | 14 | 7 EQ | 22 | EXP59_.EXP = LAN_SM_FSM_FFd4 & DQ_DATA<7> # LAN_SM_FSM_FFd1 & DQ_DATA<7> # LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd2 & DQ_DATA<7> # !LAN_SM_FSM_FFd3 & LAN_SM_FSM_FFd2 & DQ_DATA<7> # !DQ_SWAP & !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1 & A<15>.PIN ;Imported pterms FB15_8 # D<15>.PIN & !UDS & DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # D<15>.PIN & !LDS & DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # !UDS & D<7>.PIN & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # !LDS & D<7>.PIN & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # A<23>.PIN & DQ_SWAP & !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1 ;Imported pterms FB15_7 # UDS & LDS & A<23>.PIN & DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # UDS & LDS & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 & A<15>.PIN MACROCELL | 15 | 0 | EXP60_ ATTRIBUTES | 2048 | 0 OUTPUTMC | 1 | 15 | 17 INPUTS | 9 | D<10>.PIN | LDS | DQ_SWAP | LAN_SM_FSM_FFd3 | LAN_SM_FSM_FFd4 | UDS | D<2>.PIN | A<18>.PIN | A<10>.PIN INPUTMC | 3 | 8 | 1 | 0 | 10 | 14 | 3 INPUTP | 6 | 74 | 157 | 155 | 71 | 171 | 112 EXPORTS | 1 | 15 | 17 EQ | 10 | EXP60_.EXP = D<10>.PIN & !LDS & DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # !UDS & D<2>.PIN & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # !LDS & D<2>.PIN & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # A<18>.PIN & UDS & LDS & DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # UDS & LDS & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 & A<10>.PIN MACROCELL | 15 | 14 | EXP61_ ATTRIBUTES | 2048 | 0 OUTPUTMC | 1 | 15 | 15 INPUTS | 12 | D<10>.PIN | UDS | DQ_SWAP | LAN_SM_FSM_FFd3 | LAN_SM_FSM_FFd4 | LDS | A<18>.PIN | LAN_SM_FSM_FFd2 | LAN_SM_FSM_FFd1 | D<2>.PIN | A<10>.PIN | Z3_DATA<16>.EXP INPUTMC | 6 | 8 | 1 | 0 | 10 | 14 | 3 | 0 | 1 | 12 | 4 | 15 | 13 INPUTP | 6 | 74 | 155 | 157 | 171 | 71 | 112 EXPORTS | 1 | 15 | 15 IMPORTS | 1 | 15 | 13 EQ | 13 | EXP61_.EXP = D<10>.PIN & !UDS & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # D<10>.PIN & !LDS & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # A<18>.PIN & !DQ_SWAP & !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1 # !UDS & D<2>.PIN & DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # DQ_SWAP & !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1 & A<10>.PIN ;Imported pterms FB16_14 # UDS & LDS & DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 & A<10>.PIN MACROCELL | 15 | 17 | EXP62_ ATTRIBUTES | 2048 | 0 OUTPUTMC | 1 | 15 | 16 INPUTS | 11 | LAN_SM_FSM_FFd3 | LAN_SM_FSM_FFd2 | DQ_DATA<2> | D<10>.PIN | UDS | DQ_SWAP | LAN_SM_FSM_FFd4 | A<18>.PIN | LAN_SM_FSM_FFd1 | A<10>.PIN | EXP60_.EXP INPUTMC | 7 | 0 | 10 | 0 | 1 | 15 | 16 | 8 | 1 | 14 | 3 | 12 | 4 | 15 | 0 INPUTP | 4 | 74 | 155 | 171 | 112 EXPORTS | 1 | 15 | 16 IMPORTS | 1 | 15 | 0 EQ | 19 | EXP62_.EXP = LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd2 & DQ_DATA<2> # !LAN_SM_FSM_FFd3 & LAN_SM_FSM_FFd2 & DQ_DATA<2> # D<10>.PIN & !UDS & DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # A<18>.PIN & DQ_SWAP & !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1 # !DQ_SWAP & !LAN_SM_FSM_FFd4 & LAN_SM_FSM_FFd2 & !LAN_SM_FSM_FFd1 & A<10>.PIN ;Imported pterms FB16_1 # D<10>.PIN & !LDS & DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # !UDS & D<2>.PIN & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # !LDS & D<2>.PIN & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # A<18>.PIN & UDS & LDS & DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 # UDS & LDS & !DQ_SWAP & !LAN_SM_FSM_FFd3 & !LAN_SM_FSM_FFd4 & A<10>.PIN PIN | Z3 | 64 | 0 | N/A | 151 | 3 | 8 | 1 | 8 | 8 | 7 | 13 PIN | CFIN | 64 | 0 | N/A | 190 | 2 | 4 | 6 | 7 | 13 PIN | CLK_EXT | 4096 | 0 | N/A | 57 | 98 | 8 | 10 | 15 | 5 | 15 | 2 | 15 | 1 | 14 | 16 | 14 | 14 | 14 | 13 | 8 | 13 | 8 | 16 | 10 | 2 | 10 | 4 | 10 | 9 | 10 | 10 | 12 | 7 | 15 | 10 | 15 | 7 | 8 | 15 | 6 | 3 | 1 | 17 | 1 | 15 | 1 | 12 | 1 | 10 | 1 | 8 | 1 | 6 | 1 | 3 | 1 | 0 | 6 | 7 | 6 | 8 | 6 | 9 | 6 | 10 | 6 | 13 | 6 | 14 | 6 | 16 | 6 | 17 | 6 | 15 | 5 | 12 | 15 | 13 | 15 | 12 | 15 | 11 | 10 | 12 | 10 | 8 | 10 | 7 | 10 | 6 | 12 | 8 | 15 | 8 | 15 | 6 | 15 | 4 | 10 | 5 | 10 | 3 | 10 | 1 | 10 | 0 | 12 | 2 | 0 | 10 | 14 | 3 | 0 | 1 | 12 | 4 | 5 | 8 | 5 | 10 | 5 | 11 | 5 | 15 | 5 | 14 | 10 | 17 | 15 | 15 | 0 | 0 | 0 | 15 | 12 | 17 | 12 | 14 | 12 | 12 | 14 | 0 | 15 | 16 | 0 | 12 | 14 | 10 | 12 | 11 | 12 | 6 | 14 | 9 | 10 | 15 | 14 | 4 | 5 | 6 | 6 | 6 | 8 | 6 | 3 | 3 | 3 | 12 | 3 | 6 | 3 | 2 | 3 | 10 | 3 | 9 | 3 | 8 | 3 | 0 | 5 | 17 | 5 | 16 | 5 | 3 | 14 | 12 | 14 | 15 | 14 | 6 | 14 | 17 | 0 | 8 | 5 | 0 | 6 | 0 PIN | FCS | 64 | 0 | N/A | 147 | 91 | 8 | 10 | 15 | 5 | 15 | 2 | 15 | 1 | 14 | 16 | 14 | 14 | 14 | 13 | 8 | 13 | 8 | 16 | 10 | 2 | 10 | 4 | 10 | 9 | 10 | 10 | 12 | 7 | 15 | 10 | 15 | 7 | 8 | 15 | 6 | 3 | 1 | 17 | 1 | 15 | 1 | 12 | 1 | 10 | 1 | 8 | 1 | 6 | 1 | 3 | 1 | 0 | 6 | 7 | 6 | 8 | 6 | 9 | 6 | 10 | 6 | 13 | 6 | 14 | 6 | 16 | 6 | 17 | 6 | 15 | 3 | 1 | 4 | 13 | 4 | 14 | 4 | 16 | 6 | 2 | 6 | 4 | 6 | 11 | 1 | 14 | 4 | 9 | 1 | 11 | 0 | 5 | 0 | 4 | 1 | 9 | 1 | 13 | 1 | 16 | 4 | 11 | 8 | 1 | 9 | 0 | 11 | 0 | 11 | 17 | 2 | 16 | 8 | 8 | 7 | 13 | 11 | 10 | 11 | 12 | 11 | 13 | 7 | 12 | 6 | 6 | 4 | 5 | 8 | 4 | 8 | 3 | 2 | 15 | 2 | 14 | 2 | 12 | 8 | 5 | 3 | 3 | 3 | 12 | 3 | 6 | 3 | 2 | 3 | 10 | 3 | 9 | 3 | 8 | 3 | 0 | 6 | 0 | 7 | 4 | 6 | 12 | 7 | 9 | 13 | 13 | 4 | 7 | 4 | 8 | 4 | 17 | 2 | 9 | 4 | 15 | 6 | 1 | 6 | 5 | 12 | 14 PIN | RW | 64 | 0 | N/A | 158 | 99 | 8 | 10 | 15 | 5 | 15 | 2 | 15 | 1 | 14 | 16 | 14 | 14 | 14 | 13 | 8 | 13 | 8 | 16 | 10 | 2 | 10 | 4 | 10 | 9 | 10 | 10 | 12 | 7 | 15 | 10 | 15 | 7 | 13 | 4 | 13 | 3 | 6 | 3 | 13 | 9 | 13 | 8 | 13 | 7 | 13 | 0 | 9 | 17 | 9 | 15 | 9 | 14 | 13 | 5 | 3 | 17 | 3 | 16 | 3 | 15 | 3 | 14 | 9 | 12 | 9 | 8 | 9 | 6 | 9 | 3 | 1 | 17 | 1 | 15 | 1 | 12 | 1 | 10 | 1 | 8 | 1 | 6 | 1 | 3 | 1 | 0 | 6 | 7 | 6 | 8 | 6 | 9 | 6 | 10 | 6 | 13 | 6 | 14 | 6 | 16 | 6 | 17 | 6 | 15 | 3 | 1 | 4 | 13 | 4 | 14 | 4 | 16 | 6 | 2 | 6 | 4 | 6 | 11 | 1 | 14 | 4 | 9 | 1 | 11 | 0 | 5 | 0 | 4 | 1 | 9 | 1 | 13 | 1 | 16 | 4 | 11 | 0 | 9 | 12 | 3 | 8 | 14 | 13 | 1 | 13 | 15 | 8 | 12 | 8 | 11 | 8 | 5 | 6 | 6 | 14 | 12 | 11 | 8 | 14 | 2 | 4 | 7 | 4 | 8 | 3 | 0 | 3 | 13 | 4 | 15 | 4 | 17 | 6 | 0 | 6 | 1 | 6 | 5 | 6 | 12 | 9 | 0 | 9 | 2 | 9 | 5 | 9 | 7 | 9 | 11 | 9 | 13 | 9 | 16 | 13 | 6 | 13 | 17 PIN | AS | 64 | 0 | N/A | 152 | 63 | 7 | 15 | 7 | 14 | 13 | 4 | 13 | 3 | 13 | 9 | 13 | 8 | 13 | 7 | 13 | 0 | 9 | 17 | 9 | 15 | 9 | 14 | 13 | 5 | 3 | 17 | 3 | 16 | 3 | 15 | 3 | 14 | 9 | 12 | 9 | 8 | 9 | 6 | 9 | 3 | 4 | 6 | 7 | 17 | 8 | 14 | 13 | 1 | 13 | 15 | 13 | 11 | 11 | 15 | 11 | 2 | 11 | 5 | 8 | 12 | 8 | 11 | 8 | 5 | 4 | 4 | 12 | 1 | 10 | 15 | 0 | 16 | 4 | 8 | 13 | 13 | 4 | 1 | 2 | 2 | 3 | 0 | 3 | 13 | 4 | 7 | 9 | 0 | 9 | 2 | 9 | 5 | 9 | 7 | 9 | 11 | 9 | 13 | 9 | 16 | 11 | 1 | 11 | 3 | 11 | 4 | 11 | 6 | 11 | 7 | 11 | 13 | 11 | 14 | 11 | 16 | 11 | 17 | 13 | 6 | 13 | 10 | 13 | 12 | 13 | 17 PIN | RESET | 64 | 0 | N/A | 263 | 126 | 7 | 15 | 7 | 14 | 13 | 4 | 13 | 3 | 8 | 15 | 6 | 3 | 13 | 9 | 13 | 8 | 13 | 7 | 13 | 0 | 9 | 17 | 9 | 15 | 9 | 14 | 13 | 5 | 3 | 17 | 3 | 16 | 3 | 15 | 3 | 14 | 9 | 12 | 9 | 8 | 9 | 6 | 9 | 3 | 1 | 17 | 1 | 15 | 1 | 12 | 1 | 10 | 1 | 8 | 1 | 6 | 1 | 3 | 1 | 0 | 6 | 7 | 6 | 8 | 6 | 9 | 6 | 10 | 6 | 13 | 6 | 14 | 6 | 16 | 6 | 17 | 6 | 15 | 5 | 12 | 9 | 16 | 11 | 9 | 9 | 1 | 9 | 9 | 9 | 13 | 11 | 11 | 9 | 2 | 7 | 1 | 11 | 7 | 7 | 2 | 11 | 4 | 9 | 5 | 9 | 4 | 9 | 7 | 9 | 11 | 9 | 10 | 8 | 1 | 9 | 0 | 11 | 0 | 11 | 17 | 5 | 8 | 5 | 10 | 2 | 16 | 5 | 11 | 8 | 8 | 4 | 6 | 7 | 13 | 11 | 10 | 11 | 12 | 11 | 13 | 7 | 17 | 7 | 12 | 5 | 15 | 5 | 14 | 8 | 14 | 5 | 6 | 13 | 1 | 13 | 15 | 13 | 11 | 11 | 15 | 11 | 2 | 11 | 5 | 8 | 12 | 8 | 11 | 8 | 5 | 6 | 6 | 4 | 5 | 8 | 4 | 8 | 3 | 2 | 15 | 2 | 14 | 2 | 12 | 8 | 6 | 3 | 3 | 3 | 12 | 3 | 6 | 3 | 2 | 3 | 10 | 3 | 9 | 3 | 8 | 3 | 0 | 5 | 17 | 5 | 16 | 5 | 3 | 6 | 0 | 5 | 0 | 3 | 5 | 5 | 5 | 5 | 7 | 5 | 2 | 5 | 4 | 3 | 4 | 3 | 11 | 3 | 7 | 1 | 1 | 3 | 13 | 1 | 4 | 1 | 2 | 5 | 9 | 5 | 13 | 7 | 7 | 7 | 4 | 4 | 7 | 7 | 9 | 4 | 1 | 12 | 14 PIN | UDS | 64 | 0 | N/A | 155 | 124 | 13 | 4 | 13 | 3 | 6 | 3 | 13 | 9 | 13 | 8 | 13 | 7 | 13 | 0 | 9 | 17 | 9 | 15 | 9 | 14 | 13 | 5 | 3 | 17 | 3 | 16 | 3 | 15 | 3 | 14 | 9 | 12 | 9 | 8 | 9 | 6 | 9 | 3 | 1 | 17 | 1 | 15 | 1 | 12 | 1 | 10 | 1 | 8 | 1 | 6 | 1 | 3 | 1 | 0 | 6 | 7 | 6 | 8 | 6 | 9 | 6 | 10 | 6 | 13 | 6 | 14 | 6 | 16 | 6 | 17 | 6 | 15 | 3 | 1 | 4 | 12 | 4 | 13 | 4 | 16 | 6 | 2 | 6 | 4 | 6 | 11 | 1 | 14 | 4 | 9 | 1 | 11 | 0 | 5 | 0 | 4 | 1 | 9 | 1 | 13 | 0 | 17 | 4 | 10 | 0 | 9 | 4 | 6 | 10 | 16 | 15 | 14 | 4 | 7 | 0 | 14 | 12 | 16 | 12 | 13 | 12 | 11 | 13 | 13 | 15 | 13 | 0 | 11 | 14 | 9 | 12 | 9 | 12 | 5 | 14 | 7 | 10 | 14 | 14 | 3 | 13 | 1 | 13 | 15 | 13 | 11 | 11 | 15 | 11 | 2 | 11 | 5 | 6 | 6 | 3 | 3 | 3 | 12 | 3 | 6 | 3 | 2 | 3 | 10 | 3 | 9 | 3 | 8 | 3 | 0 | 14 | 16 | 0 | 7 | 6 | 0 | 11 | 8 | 14 | 2 | 3 | 13 | 0 | 1 | 0 | 2 | 0 | 13 | 0 | 16 | 4 | 4 | 4 | 15 | 6 | 1 | 6 | 5 | 6 | 12 | 10 | 0 | 10 | 13 | 11 | 1 | 11 | 3 | 11 | 4 | 11 | 6 | 11 | 14 | 11 | 16 | 12 | 0 | 12 | 1 | 12 | 4 | 12 | 8 | 12 | 17 | 13 | 6 | 13 | 10 | 13 | 12 | 14 | 1 | 14 | 5 | 14 | 6 | 14 | 11 | 14 | 17 | 15 | 0 | 15 | 16 | 15 | 17 PIN | LDS | 64 | 0 | N/A | 157 | 107 | 13 | 4 | 13 | 3 | 13 | 9 | 13 | 8 | 13 | 6 | 13 | 0 | 9 | 17 | 9 | 15 | 9 | 14 | 13 | 5 | 3 | 17 | 3 | 16 | 3 | 15 | 3 | 14 | 9 | 12 | 9 | 8 | 9 | 6 | 9 | 3 | 6 | 15 | 3 | 1 | 4 | 12 | 4 | 13 | 4 | 16 | 6 | 2 | 6 | 4 | 6 | 11 | 1 | 14 | 4 | 9 | 1 | 11 | 0 | 5 | 0 | 4 | 1 | 9 | 1 | 13 | 0 | 17 | 4 | 10 | 0 | 9 | 4 | 6 | 10 | 16 | 15 | 14 | 4 | 7 | 0 | 14 | 12 | 16 | 12 | 13 | 12 | 8 | 13 | 17 | 15 | 13 | 0 | 11 | 14 | 9 | 12 | 9 | 12 | 5 | 14 | 7 | 10 | 14 | 14 | 1 | 13 | 1 | 13 | 15 | 13 | 10 | 11 | 15 | 11 | 1 | 11 | 5 | 14 | 6 | 0 | 7 | 6 | 0 | 11 | 8 | 14 | 2 | 3 | 13 | 0 | 1 | 0 | 2 | 0 | 13 | 0 | 16 | 1 | 17 | 3 | 0 | 4 | 4 | 4 | 15 | 4 | 17 | 6 | 1 | 6 | 5 | 6 | 6 | 6 | 12 | 6 | 13 | 9 | 0 | 9 | 2 | 9 | 5 | 9 | 7 | 9 | 11 | 9 | 13 | 9 | 16 | 10 | 0 | 10 | 13 | 11 | 3 | 11 | 4 | 11 | 6 | 11 | 7 | 11 | 13 | 11 | 14 | 11 | 16 | 11 | 17 | 12 | 0 | 12 | 1 | 12 | 4 | 12 | 17 | 13 | 7 | 13 | 12 | 13 | 13 | 14 | 5 | 14 | 11 | 15 | 0 | 15 | 16 PIN | DS1 | 64 | 0 | N/A | 148 | 35 | 3 | 1 | 4 | 12 | 4 | 13 | 4 | 16 | 6 | 2 | 6 | 4 | 6 | 11 | 1 | 14 | 4 | 9 | 1 | 11 | 0 | 5 | 0 | 4 | 1 | 9 | 1 | 13 | 0 | 2 | 4 | 10 | 0 | 10 | 14 | 2 | 4 | 7 | 12 | 3 | 14 | 14 | 14 | 17 | 0 | 8 | 6 | 0 | 1 | 17 | 4 | 6 | 4 | 4 | 4 | 15 | 4 | 17 | 6 | 1 | 6 | 3 | 6 | 5 | 6 | 6 | 6 | 12 | 12 | 2 PIN | DS0 | 64 | 0 | N/A | 170 | 35 | 3 | 1 | 4 | 12 | 4 | 13 | 4 | 16 | 6 | 2 | 6 | 4 | 6 | 11 | 1 | 14 | 4 | 9 | 1 | 11 | 0 | 5 | 0 | 4 | 1 | 9 | 1 | 13 | 0 | 2 | 4 | 10 | 0 | 10 | 14 | 2 | 4 | 7 | 12 | 3 | 14 | 14 | 14 | 6 | 0 | 8 | 6 | 0 | 1 | 17 | 4 | 6 | 4 | 4 | 4 | 15 | 4 | 17 | 6 | 1 | 6 | 3 | 6 | 5 | 6 | 6 | 6 | 10 | 6 | 12 PIN | A<4> | 64 | 0 | N/A | 97 | 47 | 13 | 4 | 13 | 3 | 13 | 9 | 13 | 8 | 13 | 7 | 13 | 0 | 9 | 17 | 9 | 15 | 9 | 14 | 13 | 5 | 3 | 17 | 3 | 16 | 3 | 15 | 3 | 14 | 9 | 12 | 9 | 8 | 9 | 6 | 9 | 3 | 9 | 0 | 13 | 1 | 13 | 15 | 13 | 11 | 11 | 15 | 11 | 2 | 11 | 5 | 3 | 0 | 3 | 13 | 9 | 2 | 9 | 5 | 9 | 7 | 9 | 11 | 9 | 13 | 9 | 16 | 11 | 1 | 11 | 3 | 11 | 4 | 11 | 6 | 11 | 7 | 11 | 13 | 11 | 14 | 11 | 16 | 11 | 17 | 13 | 6 | 13 | 10 | 13 | 12 | 13 | 13 | 13 | 17 PIN | A<5> | 64 | 0 | N/A | 91 | 48 | 13 | 4 | 13 | 3 | 13 | 9 | 13 | 8 | 13 | 7 | 13 | 0 | 9 | 17 | 9 | 15 | 9 | 14 | 13 | 5 | 3 | 17 | 3 | 16 | 3 | 15 | 3 | 14 | 9 | 12 | 9 | 8 | 9 | 6 | 9 | 3 | 11 | 10 | 13 | 1 | 13 | 15 | 13 | 11 | 11 | 15 | 11 | 2 | 11 | 5 | 3 | 0 | 3 | 13 | 9 | 0 | 9 | 2 | 9 | 5 | 9 | 7 | 9 | 11 | 9 | 13 | 9 | 16 | 11 | 1 | 11 | 3 | 11 | 4 | 11 | 6 | 11 | 7 | 11 | 13 | 11 | 14 | 11 | 16 | 11 | 17 | 13 | 6 | 13 | 10 | 13 | 12 | 13 | 13 | 13 | 17 PIN | A<3> | 64 | 0 | N/A | 99 | 46 | 13 | 4 | 13 | 3 | 13 | 9 | 13 | 8 | 13 | 7 | 13 | 0 | 9 | 17 | 9 | 15 | 9 | 14 | 13 | 5 | 3 | 17 | 3 | 16 | 3 | 15 | 3 | 14 | 9 | 12 | 9 | 8 | 9 | 6 | 9 | 3 | 11 | 0 | 13 | 1 | 13 | 15 | 13 | 11 | 11 | 15 | 11 | 2 | 11 | 5 | 3 | 0 | 3 | 13 | 9 | 0 | 9 | 2 | 9 | 5 | 9 | 7 | 9 | 11 | 9 | 13 | 9 | 16 | 11 | 1 | 11 | 3 | 11 | 4 | 11 | 6 | 11 | 7 | 11 | 14 | 11 | 16 | 11 | 17 | 13 | 6 | 13 | 10 | 13 | 12 | 13 | 17 PIN | A<1> | 64 | 0 | N/A | 107 | 47 | 13 | 4 | 13 | 3 | 13 | 9 | 13 | 8 | 13 | 7 | 13 | 0 | 9 | 17 | 9 | 15 | 9 | 14 | 13 | 5 | 3 | 17 | 3 | 16 | 3 | 15 | 3 | 14 | 9 | 12 | 9 | 8 | 9 | 6 | 9 | 3 | 13 | 1 | 13 | 15 | 13 | 11 | 11 | 15 | 11 | 2 | 11 | 5 | 3 | 0 | 3 | 13 | 9 | 0 | 9 | 2 | 9 | 5 | 9 | 7 | 9 | 11 | 9 | 13 | 9 | 16 | 11 | 1 | 11 | 3 | 11 | 4 | 11 | 6 | 11 | 7 | 11 | 13 | 11 | 14 | 11 | 16 | 11 | 17 | 13 | 6 | 13 | 10 | 13 | 12 | 13 | 13 | 13 | 17 PIN | A<6> | 64 | 0 | N/A | 98 | 48 | 13 | 4 | 13 | 3 | 13 | 9 | 13 | 8 | 13 | 7 | 13 | 0 | 9 | 17 | 9 | 15 | 9 | 14 | 13 | 5 | 3 | 17 | 3 | 16 | 3 | 15 | 3 | 14 | 9 | 12 | 9 | 8 | 9 | 6 | 9 | 3 | 11 | 12 | 13 | 1 | 13 | 15 | 13 | 11 | 11 | 15 | 11 | 2 | 11 | 5 | 3 | 0 | 3 | 13 | 9 | 0 | 9 | 2 | 9 | 5 | 9 | 7 | 9 | 11 | 9 | 13 | 9 | 16 | 11 | 1 | 11 | 3 | 11 | 4 | 11 | 6 | 11 | 7 | 11 | 13 | 11 | 14 | 11 | 16 | 11 | 17 | 13 | 6 | 13 | 10 | 13 | 12 | 13 | 13 | 13 | 17 PIN | A<2> | 64 | 0 | N/A | 101 | 46 | 13 | 9 | 13 | 8 | 13 | 7 | 13 | 0 | 9 | 17 | 9 | 15 | 9 | 14 | 13 | 5 | 3 | 17 | 3 | 16 | 3 | 15 | 3 | 14 | 9 | 12 | 9 | 8 | 9 | 6 | 9 | 3 | 11 | 17 | 13 | 1 | 13 | 15 | 13 | 11 | 11 | 15 | 11 | 2 | 11 | 5 | 3 | 0 | 3 | 13 | 9 | 0 | 9 | 2 | 9 | 5 | 9 | 7 | 9 | 11 | 9 | 13 | 9 | 16 | 11 | 1 | 11 | 3 | 11 | 4 | 11 | 6 | 11 | 7 | 11 | 13 | 11 | 14 | 11 | 16 | 13 | 4 | 13 | 6 | 13 | 10 | 13 | 12 | 13 | 13 | 13 | 17 PIN | LAN_INT | 64 | 0 | N/A | 201 | 2 | 5 | 12 | 5 | 3 PIN | A<7> | 64 | 0 | N/A | 100 | 1 | 11 | 13 PIN | AUTOBOOT_OFF | 64 | 0 | N/A | 142 | 1 | 4 | 4 PIN | BERR | 64 | 0 | N/A | 176 | 1 | 6 | 0 PIN | C1 | 64 | 0 | N/A | 188 | 1 | 2 | 8 PIN | C3 | 64 | 0 | N/A | 187 | 1 | 2 | 8 PIN | CP_IRQ | 64 | 0 | N/A | 59 | 1 | 2 | 10 PIN | ROM_OE | 536871040 | 0 | N/A | 65 PIN | A_LAN<0> | 536871040 | 0 | N/A | 7 PIN | A_LAN<10> | 536871040 | 0 | N/A | 255 PIN | A_LAN<11> | 536871040 | 0 | N/A | 256 PIN | A_LAN<12> | 536871040 | 0 | N/A | 253 PIN | A_LAN<13> | 536871040 | 0 | N/A | 254 PIN | A_LAN<1> | 536871040 | 0 | N/A | 6 PIN | A_LAN<2> | 536871040 | 0 | N/A | 12 PIN | A_LAN<3> | 536871040 | 0 | N/A | 8 PIN | A_LAN<4> | 536871040 | 0 | N/A | 20 PIN | A_LAN<5> | 536871040 | 0 | N/A | 13 PIN | A_LAN<6> | 536871040 | 0 | N/A | 22 PIN | A_LAN<7> | 536871040 | 0 | N/A | 21 PIN | A_LAN<8> | 536871040 | 0 | N/A | 258 PIN | A_LAN<9> | 536871040 | 0 | N/A | 262 PIN | CP_RD | 536871040 | 0 | N/A | 132 PIN | CP_WE | 536871040 | 0 | N/A | 131 PIN | IDE_R | 536871040 | 0 | N/A | 46 PIN | IDE_W | 536871040 | 0 | N/A | 47 PIN | LAN_CS | 536871040 | 0 | N/A | 240 PIN | LAN_WRH | 536871040 | 0 | N/A | 237 PIN | LAN_WRL | 536871040 | 0 | N/A | 145 PIN | LAN_RD | 536871040 | 0 | N/A | 242 PIN | SLAVE | 536871040 | 0 | N/A | 193 PIN | OVR | 536871040 | 0 | N/A | 185 PIN | INT_OUT | 536871040 | 0 | N/A | 60 PIN | DTACK | 536871040 | 0 | N/A | 160 PIN | CFOUT | 536871040 | 0 | N/A | 191 PIN | CP_CS | 536871040 | 0 | N/A | 63 PIN | IDE_A<0> | 536871040 | 0 | N/A | 43 PIN | IDE_A<1> | 536871040 | 0 | N/A | 45 PIN | IDE_A<2> | 536871040 | 0 | N/A | 44 PIN | IDE_CS<0> | 536871040 | 0 | N/A | 39 PIN | IDE_CS<1> | 536871040 | 0 | N/A | 41 PIN | OWN | 536871040 | 0 | N/A | 195 PIN | MTACK | 536871040 | 0 | N/A | 174 PIN | LAN_CFG<4> | 536871040 | 0 | N/A | 199 PIN | LAN_CFG<3> | 536871040 | 0 | N/A | 24 PIN | LAN_CFG<2> | 536871040 | 0 | N/A | 251 PIN | LAN_CFG<1> | 536871040 | 0 | N/A | 23 PIN | ROM_B<1> | 536871040 | 0 | N/A | 129 PIN | ROM_B<0> | 536871040 | 0 | N/A | 127 PIN | A<8> | 536870976 | 0 | N/A | 106 | 5 | 2 | 16 | 10 | 16 | 10 | 14 | 10 | 0 | 10 | 13 PIN | A<18> | 536870976 | 0 | N/A | 171 | 9 | 4 | 6 | 7 | 13 | 7 | 16 | 15 | 14 | 15 | 0 | 4 | 0 | 2 | 17 | 15 | 16 | 15 | 17 PIN | A<19> | 536870976 | 0 | N/A | 169 | 12 | 4 | 6 | 7 | 13 | 7 | 16 | 0 | 17 | 0 | 11 | 4 | 0 | 0 | 1 | 0 | 13 | 2 | 1 | 2 | 16 | 4 | 2 | 7 | 0 PIN | A<20> | 536870976 | 0 | N/A | 167 | 9 | 4 | 6 | 7 | 13 | 7 | 0 | 0 | 14 | 14 | 9 | 2 | 1 | 0 | 16 | 4 | 2 | 14 | 11 PIN | A<21> | 536870976 | 0 | N/A | 163 | 9 | 4 | 6 | 7 | 13 | 7 | 0 | 12 | 8 | 12 | 10 | 2 | 0 | 4 | 2 | 12 | 0 | 12 | 1 PIN | A<22> | 536870976 | 0 | N/A | 162 | 10 | 4 | 3 | 8 | 3 | 4 | 6 | 7 | 13 | 7 | 1 | 12 | 4 | 12 | 5 | 8 | 10 | 12 | 15 | 12 | 17 PIN | A<23> | 536870976 | 0 | N/A | 161 | 12 | 6 | 15 | 4 | 6 | 7 | 13 | 7 | 15 | 12 | 11 | 14 | 7 | 2 | 17 | 2 | 0 | 4 | 3 | 7 | 1 | 12 | 13 | 14 | 6 PIN | A<9> | 536870976 | 0 | N/A | 108 | 6 | 0 | 11 | 14 | 3 | 2 | 15 | 14 | 1 | 14 | 5 | 14 | 17 PIN | A<10> | 536870976 | 0 | N/A | 112 | 6 | 15 | 14 | 15 | 13 | 2 | 14 | 0 | 14 | 15 | 0 | 15 | 17 PIN | A<11> | 536870976 | 0 | N/A | 114 | 5 | 0 | 13 | 0 | 11 | 2 | 12 | 0 | 1 | 0 | 17 PIN | A<12> | 536870976 | 0 | N/A | 115 | 6 | 0 | 14 | 14 | 9 | 4 | 5 | 0 | 7 | 0 | 16 | 14 | 11 PIN | A<13> | 536870976 | 0 | N/A | 123 | 7 | 8 | 0 | 12 | 9 | 12 | 10 | 8 | 4 | 0 | 9 | 12 | 0 | 12 | 1 PIN | A<14> | 536870976 | 0 | N/A | 125 | 6 | 8 | 0 | 12 | 4 | 12 | 5 | 8 | 4 | 12 | 15 | 12 | 16 PIN | A<15> | 536870976 | 0 | N/A | 139 | 5 | 7 | 12 | 12 | 11 | 14 | 8 | 12 | 13 | 14 | 6 PIN | A<16> | 536870976 | 0 | N/A | 175 | 9 | 4 | 6 | 7 | 13 | 7 | 17 | 10 | 16 | 10 | 14 | 4 | 1 | 2 | 1 | 10 | 0 | 10 | 13 PIN | A<17> | 536870976 | 0 | N/A | 172 | 9 | 4 | 6 | 7 | 13 | 7 | 16 | 2 | 0 | 14 | 3 | 4 | 0 | 14 | 1 | 14 | 5 | 14 | 17 PIN | DQ<10> | 536870976 | 0 | N/A | 234 | 4 | 15 | 5 | 8 | 16 | 15 | 11 | 15 | 4 PIN | DQ<11> | 536870976 | 0 | N/A | 207 | 4 | 15 | 2 | 10 | 2 | 10 | 12 | 10 | 5 PIN | DQ<1> | 536870976 | 0 | N/A | 216 | 4 | 8 | 13 | 15 | 7 | 15 | 12 | 15 | 6 PIN | DQ<4> | 536870976 | 0 | N/A | 225 | 4 | 15 | 1 | 10 | 4 | 10 | 8 | 10 | 3 PIN | DQ<8> | 536870976 | 0 | N/A | 231 | 4 | 15 | 8 | 15 | 10 | 15 | 13 | 8 | 11 PIN | DQ<9> | 536870976 | 0 | N/A | 209 | 4 | 8 | 13 | 15 | 7 | 15 | 12 | 15 | 6 PIN | D<0> | 536870976 | 0 | N/A | 4 | 3 | 1 | 17 | 10 | 16 | 10 | 14 PIN | D<10> | 536870976 | 0 | N/A | 74 | 11 | 13 | 7 | 3 | 15 | 1 | 15 | 3 | 14 | 8 | 2 | 7 | 13 | 15 | 14 | 15 | 0 | 8 | 9 | 13 | 6 | 15 | 17 PIN | D<11> | 536870976 | 0 | N/A | 77 | 11 | 13 | 0 | 3 | 14 | 1 | 12 | 8 | 0 | 8 | 7 | 7 | 13 | 0 | 11 | 0 | 17 | 3 | 13 | 8 | 2 | 13 | 17 PIN | D<12> | 536870976 | 0 | N/A | 78 | 10 | 9 | 17 | 9 | 12 | 1 | 10 | 14 | 9 | 0 | 14 | 7 | 13 | 8 | 9 | 8 | 17 | 9 | 0 | 9 | 11 PIN | D<13> | 536870976 | 0 | N/A | 80 | 11 | 9 | 15 | 9 | 8 | 1 | 8 | 12 | 9 | 8 | 6 | 7 | 13 | 12 | 0 | 8 | 3 | 8 | 17 | 9 | 7 | 9 | 16 PIN | D<14> | 536870976 | 0 | N/A | 81 | 9 | 9 | 14 | 9 | 6 | 1 | 6 | 7 | 13 | 9 | 13 | 12 | 5 | 2 | 17 | 9 | 5 | 12 | 16 PIN | D<15> | 536870976 | 0 | N/A | 89 | 13 | 13 | 5 | 9 | 3 | 1 | 3 | 6 | 15 | 14 | 7 | 8 | 7 | 7 | 13 | 12 | 11 | 8 | 2 | 8 | 9 | 9 | 2 | 12 | 13 | 13 | 4 PIN | D<1> | 536870976 | 0 | N/A | 30 | 5 | 1 | 0 | 14 | 3 | 14 | 1 | 14 | 5 | 14 | 17 PIN | D<2> | 536870976 | 0 | N/A | 71 | 4 | 6 | 7 | 15 | 14 | 15 | 0 | 15 | 16 PIN | D<3> | 536870976 | 0 | N/A | 28 | 4 | 6 | 8 | 0 | 1 | 0 | 13 | 0 | 17 PIN | D<4> | 536870976 | 0 | N/A | 38 | 3 | 6 | 9 | 0 | 16 | 14 | 11 PIN | D<5> | 536870976 | 0 | N/A | 37 | 3 | 6 | 10 | 12 | 1 | 12 | 9 PIN | D<6> | 536870976 | 0 | N/A | 26 | 4 | 6 | 13 | 12 | 4 | 12 | 5 | 12 | 16 PIN | D<7> | 536870976 | 0 | N/A | 29 | 3 | 6 | 14 | 14 | 7 | 12 | 13 PIN | D<8> | 536870976 | 0 | N/A | 32 | 11 | 13 | 9 | 3 | 17 | 6 | 16 | 3 | 0 | 8 | 6 | 7 | 13 | 10 | 16 | 10 | 13 | 8 | 17 | 10 | 0 | 13 | 8 PIN | D<9> | 536870976 | 0 | N/A | 73 | 10 | 13 | 8 | 3 | 16 | 6 | 17 | 8 | 0 | 8 | 7 | 7 | 13 | 13 | 7 | 14 | 1 | 3 | 17 | 14 | 5 PIN | DQ<0> | 536870976 | 0 | N/A | 217 | 4 | 15 | 8 | 15 | 10 | 15 | 13 | 8 | 11 PIN | DQ<12> | 536870976 | 0 | N/A | 235 | 4 | 15 | 1 | 10 | 4 | 10 | 8 | 10 | 3 PIN | DQ<13> | 536870976 | 0 | N/A | 204 | 4 | 14 | 16 | 10 | 9 | 10 | 7 | 10 | 1 PIN | DQ<14> | 536870976 | 0 | N/A | 236 | 4 | 14 | 14 | 10 | 10 | 10 | 6 | 10 | 1 PIN | DQ<15> | 536870976 | 0 | N/A | 202 | 4 | 14 | 13 | 12 | 7 | 12 | 8 | 12 | 2 PIN | DQ<2> | 536870976 | 0 | N/A | 220 | 4 | 15 | 5 | 8 | 16 | 15 | 11 | 15 | 4 PIN | DQ<3> | 536870976 | 0 | N/A | 219 | 4 | 15 | 2 | 10 | 5 | 10 | 12 | 10 | 3 PIN | DQ<5> | 536870976 | 0 | N/A | 221 | 4 | 14 | 15 | 10 | 9 | 10 | 7 | 10 | 2 PIN | DQ<6> | 536870976 | 0 | N/A | 227 | 4 | 14 | 13 | 10 | 10 | 10 | 6 | 10 | 1 PIN | DQ<7> | 536870976 | 0 | N/A | 226 | 4 | 14 | 12 | 12 | 7 | 12 | 8 | 12 | 2