/* enc28j60l.h author: Henryk Richter purpose: header for low-level register and SPI access to ENC28J60 networking device */ #ifndef _INC_ENC28J60L_H #define _INC_ENC28J60L_H #include "compiler.h" /* Purpose: interrupt service routine ( after EnableInterrupt() ) This function will signal the task passed at EnableInterrupt time with the given sigbit when at least one frame is pending. input: - output: - */ ASM SAVEDS void enc28j60l_IntServer_List( void ); /* Purpose: enable HW interrupt input: board - mmapped board base address SigTask - task to signal upon interrupt (or NULL) SigBit - Signal bit to send upon interrupt (or -1) IntMask - ENC HW interrupts to enable (set 0, for now) = RX PACKET only output: <0 - error >=0 - OK notes: */ ASM SAVEDS int enc28j60l_EnableInterrupt( ASMR(a0) void *board ASMREG(a0), ASMR(a1) void* SigTask ASMREG(a1), ASMR(d0) int SigBit ASMREG(d0), ASMR(d1) unsigned int IntMask ASMREG(d1) ); /* Purpose: disable HW interrupt input: board - mmapped board base address output: <0 - error >=0 - OK notes: */ ASM SAVEDS int enc28j60l_DisableInterrupt( ASMR(a0) void *board ASMREG(a0) ); /* Purpose: prepare SPI for use input: - output: success/failure >0 - all fine, ready to work <=0 - init problem (codes undefined yet) */ ASM SAVEDS int enc28j60l_Init( void ); /* Purpose: shutdown SPI input: - output: - */ ASM SAVEDS void enc28j60l_Shutdown( void ); /* Purpose: delay at least the given amount of microseconds input: delay time in microseconds output: - */ ASM SAVEDS void enc28j60l_UMinDelay( ASMR(d0) unsigned long udelay ASMREG(d0) ); /* Purpose: set SPI clock divider input: clock divider 1...n output: - */ ASM SAVEDS void enc28j60l_SetSPISpeed( ASMR(d0) unsigned long divider ASMREG(d0) ); /* purpose: read one byte from a custom register input: op = ENC28J60_READ_CTRL_REG address = register address, including bits denoting the bank data = data byte */ ASM SAVEDS unsigned char enc28j60l_ReadOp( ASMR(d3) unsigned char op ASMREG(d3), ASMR(d0) unsigned char address ASMREG(d0) ); /* purpose: write one byte to a custom register input: op = ENC28J60_WRITE_CTRL_REG, ENC28J60_BIT_FIELD_SET, ENC28J60_BIT_FIELD_CLR address = register address, including bits denoting the bank data = data byte */ ASM void enc28j60l_WriteOp( ASMR(d3) unsigned char op ASMREG(d3), ASMR(d0) unsigned char address ASMREG(d0), ASMR(d1) unsigned char data ASMREG(d1)); /* purpose: select register bank based on given address input: address = register address, including bits denoting the bank */ ASM SAVEDS void enc28j60l_SetBank( ASMR(d0) unsigned char address ASMREG(d0) ); /* purpose: read one short from a custom register input: address = register address, including bits denoting the bank data = data word (unsigned short) */ ASM SAVEDS unsigned short enc28j60l_ReadReg( ASMR(d0) unsigned char address ASMREG(d0) ); /* purpose: write one short to a custom register input: address = register address, including bits denoting the bank data = data word (unsigned short) */ ASM void enc28j60l_WriteReg( ASMR(d0) unsigned char address ASMREG(d0), ASMR(d1) unsigned short data ASMREG(d1)); /* purpose: read one byte from a custom register input: address = register address, including bits denoting the bank */ ASM SAVEDS unsigned char enc28j60l_ReadRegByte( ASMR(d0) unsigned char address ASMREG(d0)); /* purpose: write one byte to a custom register input: address = register address, including bits denoting the bank data = data word (unsigned short) */ ASM void enc28j60l_WriteRegByte( ASMR(d0) unsigned char address ASMREG(d0), ASMR(d1) unsigned char data ASMREG(d1)); /* purpose: Read buffer from device to computer input: buffer = buffer to read into size = length of buffer */ ASM void enc28j60l_ReadBuffer( ASMR(a1) unsigned char *buffer ASMREG(a1), ASMR(d0) unsigned int size ASMREG(d0)); /* purpose: Write buffer from computer to device input: buffer = buffer to write size = length of buffer destptr = destination pointer in device */ ASM void enc28j60l_WriteBuffer( ASMR(a1) unsigned char *buffer ASMREG(a1), ASMR(d0) unsigned int size ASMREG(d0), ASMR(d1) unsigned short destptr ASMREG(d1)); /* Definitions based on the enc28j60.c file from the AVRlib library by Pascal Stang. ENC28J60 Control Registers Control register definitions are a combination of address, bank number, and Ethernet/MAC/PHY indicator bits. - Register address (bits 0-4) - Bank number (bits 5-6) - MAC/PHY indicator (bit 7) */ #define ADDR_MASK 0x1F #define BANK_MASK 0x60 #define SPRD_MASK 0x80 /* All-bank registers */ #define EIE 0x1B #define EIR 0x1C #define ESTAT 0x1D #define ECON2 0x1E #define ECON1 0x1F /* Bank 0 registers */ #define ERDPT (0x00|0x00) #define EWRPT (0x02|0x00) #define ETXST (0x04|0x00) #define ETXND (0x06|0x00) #define ERXST (0x08|0x00) #define ERXND (0x0A|0x00) #define ERXRDPT (0x0C|0x00) #define ERXWRPT (0x0E|0x00) #define EDMAST (0x10|0x00) #define EDMAND (0x12|0x00) /* #define EDMADST (0x14|0x00) */ #define EDMACS (0x16|0x00) /* Bank 1 registers */ #define EHT0 (0x00|0x20) #define EHT1 (0x01|0x20) #define EHT2 (0x02|0x20) #define EHT3 (0x03|0x20) #define EHT4 (0x04|0x20) #define EHT5 (0x05|0x20) #define EHT6 (0x06|0x20) #define EHT7 (0x07|0x20) #define EPMM0 (0x08|0x20) #define EPMM1 (0x09|0x20) #define EPMM2 (0x0A|0x20) #define EPMM3 (0x0B|0x20) #define EPMM4 (0x0C|0x20) #define EPMM5 (0x0D|0x20) #define EPMM6 (0x0E|0x20) #define EPMM7 (0x0F|0x20) #define EPMCS (0x10|0x20) /* #define EPMO (0x14|0x20) */ #define EWOLIE (0x16|0x20) #define EWOLIR (0x17|0x20) #define ERXFCON (0x18|0x20) #define EPKTCNT (0x19|0x20) /* Bank 2 registers */ #define MACON1 (0x00|0x40|0x80) #define MACON2 (0x01|0x40|0x80) #define MACON3 (0x02|0x40|0x80) #define MACON4 (0x03|0x40|0x80) #define MABBIPG (0x04|0x40|0x80) #define MAIPG (0x06|0x40|0x80) #define MACLCON1 (0x08|0x40|0x80) #define MACLCON2 (0x09|0x40|0x80) #define MAMXFL (0x0A|0x40|0x80) #define MAPHSUP (0x0D|0x40|0x80) #define MICON (0x11|0x40|0x80) #define MICMD (0x12|0x40|0x80) #define MIREGADR (0x14|0x40|0x80) #define MIWR (0x16|0x40|0x80) #define MIRD (0x18|0x40|0x80) /* Bank 3 registers */ #define MAADR1 (0x00|0x60|0x80) #define MAADR0 (0x01|0x60|0x80) #define MAADR3 (0x02|0x60|0x80) #define MAADR2 (0x03|0x60|0x80) #define MAADR5 (0x04|0x60|0x80) #define MAADR4 (0x05|0x60|0x80) #define EBSTSD (0x06|0x60) #define EBSTCON (0x07|0x60) #define EBSTCS (0x08|0x60) #define MISTAT (0x0A|0x60|0x80) #define EREVID (0x12|0x60) #define ECOCON (0x15|0x60) #define EFLOCON (0x17|0x60) #define EPAUS (0x18|0x60) /* ENC28J60 ERXFCON Register Bit Definitions */ #define ERXFCON_UCEN 0x80 #define ERXFCON_ANDOR 0x40 #define ERXFCON_CRCEN 0x20 #define ERXFCON_PMEN 0x10 #define ERXFCON_MPEN 0x08 #define ERXFCON_HTEN 0x04 #define ERXFCON_MCEN 0x02 #define ERXFCON_BCEN 0x01 /* ENC28J60 EIE Register Bit Definitions */ #define EIE_INTIE 0x80 #define EIE_PKTIE 0x40 #define EIE_DMAIE 0x20 #define EIE_LINKIE 0x10 #define EIE_TXIE 0x08 #define EIE_WOLIE 0x04 #define EIE_TXERIE 0x02 #define EIE_RXERIE 0x01 /* ENC28J60 EIR Register Bit Definitions */ #define EIR_PKTIF 0x40 #define EIR_DMAIF 0x20 #define EIR_LINKIF 0x10 #define EIR_TXIF 0x08 #define EIR_WOLIF 0x04 #define EIR_TXERIF 0x02 #define EIR_RXERIF 0x01 /* ENC28J60 ESTAT Register Bit Definitions */ #define ESTAT_INT 0x80 #define ESTAT_LATECOL 0x10 #define ESTAT_RXBUSY 0x04 #define ESTAT_TXABRT 0x02 #define ESTAT_CLKRDY 0x01 /* ENC28J60 ECON2 Register Bit Definitions */ #define ECON2_AUTOINC 0x80 #define ECON2_PKTDEC 0x40 #define ECON2_PWRSV 0x20 #define ECON2_VRPS 0x08 /* ENC28J60 ECON1 Register Bit Definitions */ #define ECON1_TXRST 0x80 #define ECON1_RXRST 0x40 #define ECON1_DMAST 0x20 #define ECON1_CSUMEN 0x10 #define ECON1_TXRTS 0x08 #define ECON1_RXEN 0x04 #define ECON1_BSEL1 0x02 #define ECON1_BSEL0 0x01 /* ENC28J60 MACON1 Register Bit Definitions */ #define MACON1_LOOPBK 0x10 #define MACON1_TXPAUS 0x08 #define MACON1_RXPAUS 0x04 #define MACON1_PASSALL 0x02 #define MACON1_MARXEN 0x01 /* ENC28J60 MACON2 Register Bit Definitions */ #define MACON2_MARST 0x80 #define MACON2_RNDRST 0x40 #define MACON2_MARXRST 0x08 #define MACON2_RFUNRST 0x04 #define MACON2_MATXRST 0x02 #define MACON2_TFUNRST 0x01 /* ENC28J60 MACON3 Register Bit Definitions */ #define MACON3_PADCFG2 0x80 #define MACON3_PADCFG1 0x40 #define MACON3_PADCFG0 0x20 #define MACON3_TXCRCEN 0x10 #define MACON3_PHDRLEN 0x08 #define MACON3_HFRMLEN 0x04 #define MACON3_FRMLNEN 0x02 #define MACON3_FULDPX 0x01 /* ENC28J60 MICMD Register Bit Definitions */ #define MICMD_MIISCAN 0x02 #define MICMD_MIIRD 0x01 /* ENC28J60 MISTAT Register Bit Definitions */ #define MISTAT_NVALID 0x04 #define MISTAT_SCAN 0x02 #define MISTAT_BUSY 0x01 /* ENC28J60 EBSTCON Register Bit Definitions */ #define EBSTCON_PSV2 0x80 #define EBSTCON_PSV1 0x40 #define EBSTCON_PSV0 0x20 #define EBSTCON_PSEL 0x10 #define EBSTCON_TMSEL1 0x08 #define EBSTCON_TMSEL0 0x04 #define EBSTCON_TME 0x02 #define EBSTCON_BISTST 0x01 /* PHY registers */ #define PHCON1 0x00 #define PHSTAT1 0x01 #define PHHID1 0x02 #define PHHID2 0x03 #define PHCON2 0x10 #define PHSTAT2 0x11 #define PHIE 0x12 #define PHIR 0x13 #define PHLCON 0x14 /* ENC28J60 PHY PHCON1 Register Bit Definitions */ #define PHCON1_PRST 0x8000 #define PHCON1_PLOOPBK 0x4000 #define PHCON1_PPWRSV 0x0800 #define PHCON1_PDPXMD 0x0100 /* ENC28J60 PHY PHSTAT1 Register Bit Definitions */ #define PHSTAT1_PFDPX 0x1000 #define PHSTAT1_PHDPX 0x0800 #define PHSTAT1_LLSTAT 0x0004 #define PHSTAT1_JBSTAT 0x0002 /* ENC28J60 PHY PHCON2 Register Bit Definitions */ #define PHCON2_FRCLINK 0x4000 #define PHCON2_TXDIS 0x2000 #define PHCON2_JABBER 0x0400 #define PHCON2_HDLDIS 0x0100 /* PHIE Register */ #define PHIE_PGEIE (1<<1) #define PHIE_LNKIE (1<<4) /* ENC28J60 Packet Control Byte Bit Definitions */ #define PKTCTRL_PHUGEEN 0x08 #define PKTCTRL_PPADEN 0x04 #define PKTCTRL_PCRCEN 0x02 #define PKTCTRL_POVERRIDE 0x01 /* SPI operation codes */ #define ENC28J60_READ_CTRL_REG 0x00 #define ENC28J60_READ_BUF_MEM 0x3A #define ENC28J60_WRITE_CTRL_REG 0x40 #define ENC28J60_WRITE_BUF_MEM 0x7A #define ENC28J60_BIT_FIELD_SET 0x80 #define ENC28J60_BIT_FIELD_CLR 0xA0 #define ENC28J60_SOFT_RESET 0xFF #endif /* _INC_ENC28J60L_H */