Release 14.7 - xst P.20131013 (nt64) Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. --> Parameter TMPDIR set to xst/projnav.tmp Total REAL time to Xst completion: 0.00 secs Total CPU time to Xst completion: 0.09 secs --> Parameter xsthdpdir set to xst Total REAL time to Xst completion: 0.00 secs Total CPU time to Xst completion: 0.09 secs --> Reading design: LAN_IDE_CP.prj TABLE OF CONTENTS 1) Synthesis Options Summary 2) HDL Compilation 3) Design Hierarchy Analysis 4) HDL Analysis 5) HDL Synthesis 5.1) HDL Synthesis Report 6) Advanced HDL Synthesis 6.1) Advanced HDL Synthesis Report 7) Low Level Synthesis 8) Partition Report 9) Final Report ========================================================================= * Synthesis Options Summary * ========================================================================= ---- Source Parameters Input File Name : "LAN_IDE_CP.prj" Input Format : mixed Ignore Synthesis Constraint File : NO ---- Target Parameters Output File Name : "LAN_IDE_CP" Output Format : NGC Target Device : XC9500XL CPLDs ---- Source Options Top Module Name : LAN_IDE_CP Automatic FSM Extraction : YES FSM Encoding Algorithm : Gray Safe Implementation : No Mux Extraction : Yes Resource Sharing : YES ---- Target Options Add IO Buffers : YES MACRO Preserve : YES XOR Preserve : YES Equivalent register Removal : YES ---- General Options Optimization Goal : Speed Optimization Effort : 2 Keep Hierarchy : Yes Netlist Hierarchy : As_Optimized RTL Output : Yes Hierarchy Separator : / Bus Delimiter : <> Case Specifier : Maintain Verilog 2001 : YES ---- Other Options Clock Enable : YES wysiwyg : NO ========================================================================= Setting FSM Encoding Algorithm to : Gray ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE_V2/LAN_IDE_CP-Z2v2.vhd" in Library work. Entity compiled. Entity (Architecture ) compiled. ========================================================================= * Design Hierarchy Analysis * ========================================================================= Analyzing hierarchy for entity in library (architecture ). ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity in library (Architecture ). WARNING:Xst:819 - "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE_V2/LAN_IDE_CP-Z2v2.vhd" line 158: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are: Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Performing bidirectional port resolution... INFO:Xst:2561 - Always blocking tristate driving signal in unit is removed. Synthesizing Unit . Related source file is "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE_V2/LAN_IDE_CP-Z2v2.vhd". WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. Found finite state machine for signal . ----------------------------------------------------------------------- | States | 8 | | Transitions | 8 | | Inputs | 0 | | Outputs | 9 | | Clock | CLK_EXT (rising_edge) | | Reset | RESET (negative) | | Reset type | synchronous | | Reset State | nop | | Power Up State | nop | | Encoding | gray | | Implementation | automatic | ----------------------------------------------------------------------- Found 16-bit tristate buffer for signal . Found 16-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 1-bit xor2 for signal created at line 151. Found 1-bit register for signal . Found 2-bit register for signal . Found 2-bit register for signal . Found 2-bit subtractor for signal created at line 464. Found 1-bit register for signal . Found 2-bit comparator greater for signal created at line 227. Found 1-bit register for signal . Found 8-bit comparator equal for signal created at line 237. Found 8-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 16-bit register for signal . Found 16-bit register for signal . Found 4-bit register for signal . Found 3-bit comparator greater for signal created at line 391. Found 1-bit register for signal . Found 8-bit comparator equal for signal created at line 241. Found 8-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 8-bit comparator equal for signal created at line 230. Found 2-bit comparator less for signal created at line 231. Found 8-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 3-bit register for signal . Summary: inferred 1 Finite State Machine(s). inferred 22 D-type flip-flop(s). inferred 1 Adder/Subtractor(s). inferred 6 Comparator(s). inferred 1 Xor(s). inferred 38 Tristate(s). Unit synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # Adders/Subtractors : 1 2-bit subtractor : 1 # Registers : 32 1-bit register : 24 16-bit register : 2 2-bit register : 2 4-bit register : 1 8-bit register : 3 # Comparators : 6 2-bit comparator greater : 1 2-bit comparator less : 1 3-bit comparator greater : 1 8-bit comparator equal : 3 # Tristates : 8 1-bit tristate buffer : 6 16-bit tristate buffer : 2 # Xors : 1 1-bit xor2 : 1 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= Optimizing FSM on signal with gray encoding. ------------------------ State | Encoding ------------------------ nop | 000 wait0 | 001 clr | 011 clr_commit | 010 wait1 | 110 set | 111 set_commit | 101 done | 100 ------------------------ ========================================================================= Advanced HDL Synthesis Report Macro Statistics # FSMs : 1 # Adders/Subtractors : 1 2-bit subtractor : 1 # Registers : 22 Flip-Flops : 22 # Comparators : 3 8-bit comparator equal : 3 ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... implementation constraint: INIT=r : LAN_RST_SM_FSM_FFd3 implementation constraint: INIT=r : LAN_RST_SM_FSM_FFd2 implementation constraint: INIT=r : LAN_RST_SM_FSM_FFd1 ========================================================================= * Partition Report * ========================================================================= Partition Implementation Status ------------------------------- No Partitions were found in this design. ------------------------------- ========================================================================= * Final Report * ========================================================================= Final Results RTL Top Level Output File Name : LAN_IDE_CP.ngr Top Level Output File Name : LAN_IDE_CP Output Format : NGC Optimization Goal : Speed Keep Hierarchy : Yes Target Technology : XC9500XL CPLDs Macro Preserve : YES XOR Preserve : YES Clock Enable : YES wysiwyg : NO Design Statistics # IOs : 113 Cell Usage : # BELS : 745 # AND2 : 193 # AND3 : 54 # AND4 : 7 # AND8 : 3 # GND : 1 # INV : 284 # OR2 : 155 # OR3 : 20 # OR4 : 2 # XOR2 : 26 # FlipFlops/Latches : 91 # FD : 6 # FDC : 8 # FDCE : 33 # FDP : 7 # FDPE : 37 # IO Buffers : 106 # IBUF : 35 # IOBUFE : 32 # OBUF : 33 # OBUFE : 6 ========================================================================= Total REAL time to Xst completion: 2.00 secs Total CPU time to Xst completion: 2.72 secs --> Total memory usage is 4514348 kilobytes Number of errors : 0 ( 0 filtered) Number of warnings : 13 ( 0 filtered) Number of infos : 1 ( 0 filtered)