cpldfit: version P.20131013 Xilinx Inc. Fitter Report Design Name: LAN_IDE_CP Date: 1- 2-2019, 10:08PM Device Used: XC95288XL-10-TQ144 Fitting Status: Successful ************************* Mapped Resource Summary ************************** Macrocells Product Terms Function Block Registers Pins Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot 252/288 ( 87%) 810 /1440 ( 56%) 516/864 ( 60%) 145/288 ( 50%) 112/117 ( 96%) ** Function Block Resources ** Function Mcells FB Inps Pterms IO Block Used/Tot Used/Tot Used/Tot Used/Tot FB1 18/18* 39/54 43/90 8/ 8* FB2 18/18* 29/54 38/90 10/10* FB3 2/18 5/54 2/90 3/ 5 FB4 17/18 29/54 65/90 6/ 6* FB5 18/18* 38/54 51/90 7/ 8 FB6 17/18 25/54 22/90 8/ 8* FB7 11/18 40/54 58/90 4/ 4* FB8 17/18 40/54 67/90 5/ 5* FB9 15/18 39/54 66/90 9/ 9* FB10 14/18 40/54 39/90 10/10* FB11 18/18* 34/54 71/90 7/ 7* FB12 18/18* 19/54 41/90 6/ 6* FB13 16/18 39/54 54/90 5/ 6 FB14 17/18 40/54 49/90 7/ 8 FB15 18/18* 39/54 67/90 9/ 9* FB16 18/18* 21/54 77/90 8/ 8* ----- ----- ----- ----- 252/288 516/864 810/1440 112/117 * - Resource is exhausted ** Global Control Resources ** Signal 'CLK_EXT' mapped onto global clock net GCK1. Global output enable net(s) unused. Global set/reset net(s) unused. ** Pin Resources ** Signal Type Required Mapped | Pin Type Used Total ------------------------------------|------------------------------------ Input : 21 21 | I/O : 105 109 Output : 42 42 | GCK/IO : 2 3 Bidirectional : 48 48 | GTS/IO : 4 4 GCK : 1 1 | GSR/IO : 1 1 GTS : 0 0 | GSR : 0 0 | ---- ---- Total 112 112 ** Power Data ** There are 252 macrocells in high performance mode (MCHP). There are 0 macrocells in low power mode (MCLP). End of Mapped Resource Summary ************************** Errors and Warnings *************************** WARNING:Cpld - Unable to retrieve the path to the iSE Project Repository. Will use the default filename of 'LAN_IDE_CP.ise'. INFO:Cpld - Inferring BUFG constraint for signal 'CLK_EXT' based upon the LOC constraint 'P30'. It is recommended that you declare this BUFG explicitedly in your design. Note that for certain device families the output of a BUFG constraint can not drive a gated clock, and the BUFG constraint will be ignored. WARNING:Cpld:1007 - Removing unused input(s) 'AUTOBOOT_OFF'. The input(s) are unused after optimization. Please verify functionality via simulation. WARNING:Cpld:1007 - Removing unused input(s) 'CP_IRQ'. The input(s) are unused after optimization. Please verify functionality via simulation. WARNING:Cpld:1007 - Removing unused input(s) 'IDE_WAIT'. The input(s) are unused after optimization. Please verify functionality via simulation. WARNING:Cpld:1007 - Removing unused input(s) 'MTCR'. The input(s) are unused after optimization. Please verify functionality via simulation. ************************* Summary of Mapped Logic ************************ ** 90 Outputs ** Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init Name Pts Inps No. Type Use Mode Rate State D<5> 2 3 FB1_5 20 I/O I/O STD FAST D<4> 2 3 FB1_6 21 I/O I/O STD FAST IDE_CS<0> 1 1 FB1_8 22 I/O O STD FAST IDE_CS<1> 1 1 FB1_10 23 I/O O STD FAST IDE_A<0> 1 1 FB1_12 24 I/O O STD FAST IDE_A<2> 1 1 FB1_14 25 I/O O STD FAST IDE_A<1> 1 1 FB1_15 26 I/O O STD FAST IDE_R 1 4 FB1_17 27 I/O O STD FAST A_LAN<4> 1 2 FB2_2 9 I/O O STD FAST A_LAN<7> 1 2 FB2_3 10 I/O O STD FAST A_LAN<6> 2 3 FB2_5 11 I/O O STD FAST LAN_CFG<1> 0 0 FB2_6 12 I/O O STD FAST LAN_CFG<3> 0 0 FB2_8 13 I/O O STD FAST D<6> 2 3 FB2_10 14 I/O I/O STD FAST D<3> 2 3 FB2_12 15 I/O I/O STD FAST D<7> 2 3 FB2_14 16 I/O I/O STD FAST D<1> 2 3 FB2_15 17 I/O I/O STD FAST D<8> 3 5 FB2_17 19 I/O I/O STD FAST IDE_W 1 3 FB3_2 28 I/O O STD FAST INT_OUT 1 2 FB3_14 32 GCK/I/O O STD FAST D<0> 2 3 FB4_2 2 GTS/I/O I/O STD FAST A_LAN<1> 1 2 FB4_5 3 GTS/I/O O STD FAST A_LAN<0> 1 2 FB4_6 4 I/O O STD FAST A_LAN<3> 2 3 FB4_8 5 GTS/I/O O STD FAST A_LAN<2> 1 2 FB4_12 6 GTS/I/O O STD FAST A_LAN<5> 1 2 FB4_14 7 I/O O STD FAST CP_CS 0 0 FB5_2 34 I/O O STD FAST ROM_OE 1 4 FB5_5 35 I/O O STD FAST D<2> 2 3 FB5_10 39 I/O I/O STD FAST D<9> 3 5 FB5_12 40 I/O I/O STD FAST D<10> 3 5 FB5_14 41 I/O I/O STD FAST D<11> 3 5 FB5_15 43 I/O I/O STD FAST D<12> 4 7 FB5_17 44 I/O I/O STD FAST LAN_CFG<2> 0 0 FB6_2 135 I/O O STD FAST A_LAN<12> 1 2 FB6_3 136 I/O O STD FAST A_LAN<13> 1 2 FB6_5 137 I/O O STD FAST A_LAN<10> 1 2 FB6_6 138 I/O O STD FAST A_LAN<11> 1 2 FB6_8 139 I/O O STD FAST A_LAN<8> 1 2 FB6_10 140 I/O O STD FAST A_LAN<9> 1 2 FB6_14 142 I/O O STD FAST Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init Name Pts Inps No. Type Use Mode Rate State D<13> 4 7 FB7_3 45 I/O I/O STD FAST D<14> 4 7 FB7_5 46 I/O I/O STD FAST D<15> 4 7 FB7_12 48 I/O I/O STD FAST DQ<12> 2 3 FB8_2 130 I/O I/O STD FAST DQ<14> 2 3 FB8_3 131 I/O I/O STD FAST LAN_WRH 2 3 FB8_5 132 I/O O STD FAST LAN_CS 2 3 FB8_8 133 I/O O STD FAST LAN_RD 1 2 FB8_10 134 I/O O STD FAST A<8> 5 11 FB9_11 56 I/O I/O STD FAST RESET A<9> 5 11 FB9_14 58 I/O I/O STD FAST RESET A<10> 5 11 FB9_17 59 I/O I/O STD FAST RESET DQ<1> 3 4 FB10_2 117 I/O I/O STD FAST DQ<0> 2 3 FB10_3 118 I/O I/O STD FAST DQ<3> 2 3 FB10_5 119 I/O I/O STD FAST DQ<2> 2 3 FB10_6 120 I/O I/O STD FAST DQ<5> 2 3 FB10_8 121 I/O I/O STD FAST DQ<4> 3 4 FB10_10 124 I/O I/O STD FAST DQ<7> 2 3 FB10_11 125 I/O I/O STD FAST DQ<6> 2 3 FB10_12 126 I/O I/O STD FAST DQ<8> 3 4 FB10_14 128 I/O I/O STD FAST DQ<10> 3 4 FB10_17 129 I/O I/O STD FAST A<11> 5 11 FB11_3 60 I/O I/O STD FAST RESET A<12> 5 11 FB11_5 61 I/O I/O STD FAST RESET A<13> 5 11 FB11_10 64 I/O I/O STD FAST RESET A<14> 5 11 FB11_11 66 I/O I/O STD FAST RESET ROM_B<0> 0 0 FB11_12 68 I/O O STD FAST ROM_B<1> 0 0 FB11_14 69 I/O O STD FAST CP_WE 0 0 FB11_17 70 I/O O STD FAST LAN_CFG<4> 0 0 FB12_2 110 I/O O STD FAST DQ<15> 2 3 FB12_5 112 I/O I/O STD FAST DQ<13> 2 3 FB12_8 113 I/O I/O STD FAST DQ<11> 3 4 FB12_10 115 I/O I/O STD FAST DQ<9> 3 4 FB12_12 116 I/O I/O STD FAST CP_RD 0 0 FB13_2 71 I/O O STD FAST A<15> 5 11 FB13_8 74 I/O I/O STD FAST RESET LAN_WRL 2 3 FB13_14 76 I/O O STD FAST OVR 1 1 FB14_3 100 I/O O STD FAST CFOUT 1 3 FB14_11 105 I/O O STD FAST SLAVE 2 5 FB14_14 106 I/O O STD FAST OWN 0 0 FB14_15 107 I/O O STD FAST Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init Name Pts Inps No. Type Use Mode Rate State DTACK 1 1 FB15_12 85 I/O O STD FAST A<23> 5 11 FB15_14 86 I/O I/O STD FAST RESET A<22> 5 11 FB15_15 87 I/O I/O STD FAST RESET A<21> 5 11 FB15_17 88 I/O I/O STD FAST RESET A<20> 5 11 FB16_2 91 I/O I/O STD FAST RESET A<19> 5 11 FB16_3 92 I/O I/O STD FAST RESET A<18> 5 11 FB16_6 94 I/O I/O STD FAST RESET A<17> 5 11 FB16_8 95 I/O I/O STD FAST RESET MTACK 0 0 FB16_10 96 I/O O STD FAST A<16> 5 11 FB16_11 97 I/O I/O STD FAST RESET ** 162 Buried Nodes ** Signal Total Total Loc Pwr Reg Init Name Pts Inps Mode State $OpTx$FX_DC$16 1 3 FB1_1 STD DQ_5_IOBUFE/DQ_5_IOBUFE_TRST 2 4 FB1_2 STD Z3_ADR<9> 3 3 FB1_3 STD RESET Z3_ADR<10> 3 3 FB1_4 STD RESET IDE_ACCESS 3 3 FB1_7 STD RESET LAN_ACCESS 4 13 FB1_9 STD RESET IDE_ENABLE 4 5 FB1_11 STD RESET D_9_IOBUFE/D_9_IOBUFE_TRST 4 8 FB1_13 STD DQ_SWAP 4 15 FB1_16 STD RESET LAN_INT_ENABLE 5 8 FB1_18 STD RESET SHUT_UP 2 12 FB2_1 STD RESET LAN_BASEADR<9> 3 13 FB2_4 STD RESET LAN_BASEADR<14> 3 13 FB2_7 STD RESET LAN_BASEADR<13> 3 13 FB2_9 STD RESET LAN_BASEADR<12> 3 13 FB2_11 STD RESET LAN_BASEADR<11> 3 13 FB2_13 STD RESET LAN_BASEADR<10> 3 13 FB2_16 STD RESET LAN_BASEADR<0> 3 13 FB2_18 STD RESET D_Z2_OUT<0> 12 14 FB4_1 STD SET $OpTx$FX_DC$34 1 9 FB4_3 STD D_Z2_OUT<3> 3 3 FB4_4 STD SET D_Z2_OUT<2> 3 3 FB4_7 STD SET AUTO_CONFIG_Z2_DONE_CYCLE<0> 3 11 FB4_9 STD RESET CP_BASEADR<6> 4 5 FB4_10 STD RESET AUTO_CONFIG_Z2_DONE_CYCLE<1> 4 13 FB4_11 STD RESET BUF_D_Z2_OUT<2> 6 8 FB4_13 STD BUF_D_Z2_OUT<3> 9 10 FB4_15 STD D_Z2_OUT<1> 11 11 FB4_16 STD SET $OpTx$FX_DC$35 1 10 FB4_18 STD LAN_BASEADR<8> 3 13 FB5_1 STD RESET LAN_BASEADR<7> 3 13 FB5_3 STD RESET LAN_BASEADR<6> 3 13 FB5_4 STD RESET LAN_BASEADR<5> 3 13 FB5_6 STD RESET LAN_BASEADR<4> 3 13 FB5_7 STD RESET LAN_BASEADR<3> 3 13 FB5_8 STD RESET LAN_BASEADR<2> 3 13 FB5_9 STD RESET LAN_BASEADR<1> 3 13 FB5_11 STD RESET LAN_BASEADR<15> 3 13 FB5_13 STD RESET D_OUT<6> 4 11 FB5_16 STD SET D_OUT<5> 4 11 FB5_18 STD SET Signal Total Total Loc Pwr Reg Init Name Pts Inps Mode State $OpTx$FX_DC$57 1 2 FB6_4 STD $OpTx$FX_DC$37 1 2 FB6_7 STD $OpTx$FX_DC$12 1 2 FB6_9 STD $OpTx$FX_DC$10 1 2 FB6_11 STD SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF 2 2 FB6_12 STD LAN_READY 2 2 FB6_13 STD RESET $OpTx$FX_DC$63 2 2 FB6_15 STD $OpTx$FX_DC$62 2 2 FB6_16 STD $OpTx$FX_DC$61 2 2 FB6_17 STD $OpTx$FX_DC$60 2 2 FB6_18 STD CP_ACCESS 19 19 FB7_1 STD RESET SHUT_UP_Z2<0> 3 4 FB7_10 STD SET CP_BASEADR<5> 4 5 FB7_11 STD RESET CP_BASEADR<4> 4 5 FB7_13 STD RESET CP_BASEADR<3> 4 5 FB7_14 STD RESET CP_BASEADR<2> 4 5 FB7_15 STD RESET CP_BASEADR<1> 4 5 FB7_16 STD RESET CP_BASEADR<0> 4 5 FB7_17 STD RESET $OpTx$FX_DC$59 2 2 FB8_1 STD SHUT_UP_Z2<1> 3 4 FB8_4 STD SET IDE_BASEADR<7> 4 5 FB8_6 STD RESET IDE_BASEADR<6> 4 5 FB8_7 STD RESET IDE_BASEADR<5> 4 5 FB8_9 STD RESET IDE_BASEADR<4> 4 5 FB8_11 STD RESET IDE_BASEADR<3> 4 5 FB8_12 STD RESET IDE_BASEADR<2> 4 5 FB8_13 STD RESET IDE_BASEADR<1> 4 5 FB8_14 STD RESET IDE_BASEADR<0> 4 5 FB8_15 STD RESET CP_BASEADR<7> 4 5 FB8_16 STD RESET BUF_IDE_ACCESS 17 17 FB8_18 STD DQ_DATA<13> 6 12 FB9_1 STD RESET DQ_DATA<14> 6 12 FB9_2 STD RESET DQ_DATA<15> 6 12 FB9_3 STD RESET DQ_DATA<5> 6 12 FB9_4 STD RESET DQ_DATA<6> 6 12 FB9_5 STD RESET DQ_DATA<7> 6 12 FB9_6 STD RESET $OpTx$INV$5 4 4 FB9_7 STD Z3_ADR<11> 3 3 FB9_8 STD RESET Z3_ADR<12> 3 3 FB9_9 STD RESET Z3_ADR<13> 3 3 FB9_10 STD RESET Signal Total Total Loc Pwr Reg Init Name Pts Inps Mode State $OpTx$FX_DC$44 1 2 FB9_12 STD LAN_A_INIT<3> 1 1 FB9_13 STD SET AUTOCONFIG_Z3_ACCESS 3 21 FB10_13 STD RESET AUTO_CONFIG_Z2_DONE<1> 4 5 FB10_15 STD RESET AUTO_CONFIG_Z2_DONE<0> 4 5 FB10_16 STD RESET AUTOCONFIG_Z2_ACCESS 4 13 FB10_18 STD RESET Z3_DATA<30> 4 7 FB11_1 STD RESET Z3_DATA<29> 4 7 FB11_2 STD RESET Z3_DATA<22> 4 7 FB11_4 STD RESET Z3_DATA<21> 4 7 FB11_6 STD RESET LAN_SM_FSM_FFd4 4 7 FB11_7 STD RESET LAN_SM_FSM_FFd2 4 7 FB11_8 STD RESET LAN_RD_S 4 6 FB11_9 STD RESET LAN_SM_FSM_FFd1 5 8 FB11_13 STD RESET DQ_DATA<8> 6 12 FB11_15 STD RESET DQ_DATA<10> 6 12 FB11_16 STD RESET DQ_DATA<0> 6 12 FB11_18 STD RESET LAN_SM_RST 1 4 FB12_1 STD RESET LAN_IRQ_D0 2 2 FB12_3 STD RESET LAN_D_INIT<8> 2 2 FB12_4 STD RESET LAN_D_INIT<1> 2 2 FB12_6 STD RESET LAN_A_INIT<6> 2 2 FB12_7 STD SET CONFIG_READY 2 2 FB12_9 STD RESET BUF_LAN_D_INIT<1> 2 3 FB12_11 STD LAN_WR_RST 3 4 FB12_13 STD RESET LAN_RST_SM_FSM_FFd3 3 4 FB12_14 STD RESET LAN_RST_SM_FSM_FFd2 3 4 FB12_15 STD RESET LAN_RST_SM_FSM_FFd1 3 4 FB12_16 STD RESET LAN_IRQ_OUT 3 4 FB12_17 STD RESET LAN_CS_RST 3 4 FB12_18 STD RESET D_OUT<7> 2 9 FB13_4 STD SET D_OUT<3> 2 8 FB13_5 STD SET D_OUT<0> 2 10 FB13_6 STD SET Z3_ADR<8> 3 3 FB13_7 STD RESET Z3_ADR<7> 3 3 FB13_9 STD RESET D_OUT<2> 3 10 FB13_10 STD SET AUTO_CONFIG_DONE_CYCLE 3 12 FB13_11 STD RESET AUTO_CONFIG_DONE 3 3 FB13_12 STD RESET D_OUT<4> 4 11 FB13_13 STD SET D_OUT<1> 4 10 FB13_15 STD SET Signal Total Total Loc Pwr Reg Init Name Pts Inps Mode State DQ_DATA<9> 6 12 FB13_16 STD RESET DQ_DATA<2> 6 12 FB13_17 STD RESET DQ_DATA<1> 6 12 FB13_18 STD RESET $OpTx$INV$4 16 16 FB14_1 STD BUF_CONFIG_READY 1 3 FB14_2 STD $OpTx$FX_DC$49 1 2 FB14_4 STD ROM_B_0_OBUF$BUF9/ROM_B_0_OBUF$BUF9_TRST 2 4 FB14_5 STD ROM_B_0_OBUF$BUF2/ROM_B_0_OBUF$BUF2_TRST 2 3 FB14_6 STD $OpTx$FX_DC$50 2 3 FB14_7 STD Z3_ADR_1 3 3 FB14_8 STD RESET Z3_ADR_0 3 3 FB14_9 STD RESET Z3_ADR<6> 3 3 FB14_10 STD RESET Z3_ADR<5> 3 3 FB14_12 STD RESET Z3_ADR<4> 3 3 FB14_13 STD RESET Z3_ADR<3> 3 3 FB14_16 STD RESET Z3_ADR<2> 3 3 FB14_17 STD RESET DQ_DATA<11> 6 12 FB15_1 STD RESET DQ_DATA<12> 6 12 FB15_2 STD RESET DQ_DATA<3> 6 12 FB15_3 STD RESET DQ_DATA<4> 6 12 FB15_4 STD RESET BUF_LAN_READY 4 5 FB15_5 STD Z3_DATA<23> 4 7 FB15_6 STD RESET Z3_DATA<31> 4 7 FB15_7 STD RESET LAN_WRH_S 3 7 FB15_8 STD RESET LAN_WRL_S 3 7 FB15_9 STD RESET $OpTx$FX_DC$30 2 4 FB15_10 STD $OpTx$FX_DC$36 2 5 FB15_11 STD $OpTx$FX_SC$31 2 5 FB15_13 STD $OpTx$FX_SC$66 2 6 FB15_16 STD Z3_DATA<9>/Z3_DATA<9>_TRST 1 3 FB15_18 STD Z3_DATA<28> 4 7 FB16_1 STD RESET Z3_DATA<27> 4 7 FB16_4 STD RESET Z3_DATA<26> 4 7 FB16_5 STD RESET Z3_DATA<25> 4 7 FB16_7 STD RESET Z3_DATA<24> 4 7 FB16_9 STD RESET Z3_DATA<20> 4 7 FB16_12 STD RESET Z3_DATA<19> 4 7 FB16_13 STD RESET Z3_DATA<17> 4 7 FB16_14 STD RESET Z3_DATA<16> 4 7 FB16_15 STD RESET Z3_A_LOW 6 7 FB16_16 STD RESET Signal Total Total Loc Pwr Reg Init Name Pts Inps Mode State LAN_SM_FSM_FFd3 6 8 FB16_17 STD RESET Z3_DATA<18> 4 7 FB16_18 STD RESET ** 22 Inputs ** Signal Loc Pin Pin Pin Name No. Type Use CLK_EXT FB3_10 30 GCK/I/O GCK RESET FB6_15 143 GSR/I/O I A<5> FB7_15 49 I/O I A<4> FB9_2 50 I/O I A<6> FB9_3 51 I/O I A<3> FB9_5 52 I/O I A<7> FB9_6 53 I/O I A<2> FB9_8 54 I/O I A<1> FB9_12 57 I/O I LAN_INT FB12_3 111 I/O I FCS FB13_15 77 I/O I DS1 FB13_17 78 I/O I C3 FB14_6 102 I/O I C1 FB14_8 103 I/O I CFIN FB14_10 104 I/O I Z3 FB15_2 79 I/O I AS FB15_3 80 I/O I UDS FB15_8 81 I/O I LDS FB15_10 82 I/O I RW FB15_11 83 I/O I DS0 FB16_5 93 I/O I BERR FB16_12 98 I/O I Legend: Pin No. - ~ - User Assigned ************************** Function Block Details ************************ Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X - Signal used as input to the macrocell logic. Pin No. - ~ - User Assigned *********************************** FB1 *********************************** Number of function block inputs used/remaining: 39/15 Number of signals used by logic mapping into function block: 39 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use $OpTx$FX_DC$16 1 0 0 4 FB1_1 (b) (b) DQ_5_IOBUFE/DQ_5_IOBUFE_TRST 2 0 0 3 FB1_2 (b) (b) Z3_ADR<9> 3 0 0 2 FB1_3 (b) (b) Z3_ADR<10> 3 0 0 2 FB1_4 (b) (b) D<5> 2 0 0 3 FB1_5 20 I/O I/O D<4> 2 0 0 3 FB1_6 21 I/O I/O IDE_ACCESS 3 0 0 2 FB1_7 (b) (b) IDE_CS<0> 1 0 0 4 FB1_8 22 I/O O LAN_ACCESS 4 0 0 1 FB1_9 (b) (b) IDE_CS<1> 1 0 0 4 FB1_10 23 I/O O IDE_ENABLE 4 0 0 1 FB1_11 (b) (b) IDE_A<0> 1 0 0 4 FB1_12 24 I/O O D_9_IOBUFE/D_9_IOBUFE_TRST 4 0 0 1 FB1_13 (b) (b) IDE_A<2> 1 0 0 4 FB1_14 25 I/O O IDE_A<1> 1 0 0 4 FB1_15 26 I/O O DQ_SWAP 4 0 0 1 FB1_16 (b) (b) IDE_R 1 0 0 4 FB1_17 27 I/O O LAN_INT_ENABLE 5 0 0 0 FB1_18 (b) (b) Signals Used by Logic in Function Block 1: $OpTx$FX_DC$10 14: BUF_CONFIG_READY 27: A<12>.PIN 2: $OpTx$FX_DC$12 15: BUF_IDE_ACCESS 28: A<13>.PIN 3: $OpTx$FX_DC$50 16: D_9_IOBUFE/D_9_IOBUFE_TRST 29: D<15>.PIN 4: $OpTx$FX_DC$59 17: FCS 30: D<12>.PIN 5: $OpTx$FX_DC$60 18: IDE_ACCESS 31: A<14>.PIN 6: $OpTx$FX_DC$61 19: A<9>.PIN 32: RESET 7: $OpTx$FX_DC$62 20: A<10>.PIN 33: RW 8: $OpTx$FX_DC$63 21: A<11>.PIN 34: SHUT_UP 9: $OpTx$INV$4 22: IDE_ENABLE 35: UDS 10: $OpTx$INV$5 23: LAN_BASEADR<12> 36: Z3_DATA<20> 11: AS 24: LAN_INT_ENABLE 37: Z3_DATA<21> 12: AUTOCONFIG_Z2_ACCESS 25: LDS 38: Z3_DATA<9>/Z3_DATA<9>_TRST 13: AUTOCONFIG_Z3_ACCESS 26: A<23>.PIN 39: Z3 Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs $OpTx$FX_DC$16 X.........XX............................ 3 DQ_5_IOBUFE/DQ_5_IOBUFE_TRST ..X.............X..............X.....X.. 4 Z3_ADR<9> ................X...X..........X........ 3 Z3_ADR<10> ................X.........X....X........ 3 D<5> ...............X....................XX.. 3 D<4> ...............X...................X.X.. 3 IDE_ACCESS ..........X...X................X........ 3 IDE_CS<0> ..........................X............. 1 LAN_ACCESS ...XXXXXXX......X.....X......X.X.X....X. 13 IDE_CS<1> ...........................X............ 1 IDE_ENABLE ..........X...X......X.........XX....... 5 IDE_A<0> ..................X..................... 1 D_9_IOBUFE/D_9_IOBUFE_TRST XX........XXX...X...............X....X.. 8 IDE_A<2> ....................X................... 1 IDE_A<1> ...................X.................... 1 DQ_SWAP ...XXXXXXX......X.....X....X.XXX.X....X. 15 IDE_R ..........X......X...X..........X....... 4 LAN_INT_ENABLE .............X.........XXX..X..XX.X..... 8 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB2 *********************************** Number of function block inputs used/remaining: 29/25 Number of signals used by logic mapping into function block: 29 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use SHUT_UP 2 0 0 3 FB2_1 (b) (b) A_LAN<4> 1 0 0 4 FB2_2 9 I/O O A_LAN<7> 1 0 0 4 FB2_3 10 I/O O LAN_BASEADR<9> 3 0 0 2 FB2_4 (b) (b) A_LAN<6> 2 0 0 3 FB2_5 11 I/O O LAN_CFG<1> 0 0 0 5 FB2_6 12 I/O O LAN_BASEADR<14> 3 0 0 2 FB2_7 (b) (b) LAN_CFG<3> 0 0 0 5 FB2_8 13 I/O O LAN_BASEADR<13> 3 0 0 2 FB2_9 (b) (b) D<6> 2 0 0 3 FB2_10 14 I/O I/O LAN_BASEADR<12> 3 0 0 2 FB2_11 (b) (b) D<3> 2 0 0 3 FB2_12 15 I/O I/O LAN_BASEADR<11> 3 0 0 2 FB2_13 (b) (b) D<7> 2 0 0 3 FB2_14 16 I/O I/O D<1> 2 0 0 3 FB2_15 17 I/O I/O LAN_BASEADR<10> 3 0 0 2 FB2_16 (b) (b) D<8> 3 0 0 2 FB2_17 19 I/O I/O LAN_BASEADR<0> 3 0 0 2 FB2_18 (b) (b) Signals Used by Logic in Function Block 1: $OpTx$FX_DC$36 11: D<10>.PIN 21: Z3_ADR<6> 2: AUTOCONFIG_Z3_ACCESS 12: D<9>.PIN 22: Z3_ADR_0 3: D_9_IOBUFE/D_9_IOBUFE_TRST 13: D<0>.PIN 23: Z3_ADR_1 4: D_OUT<0> 14: RESET 24: Z3_DATA<17> 5: FCS 15: RW 25: Z3_DATA<19> 6: LAN_A_INIT<6> 16: UDS 26: Z3_DATA<22> 7: D<14>.PIN 17: Z3_ADR<2> 27: Z3_DATA<23> 8: D<13>.PIN 18: Z3_ADR<3> 28: Z3_DATA<24> 9: D<12>.PIN 19: Z3_ADR<4> 29: Z3_DATA<9>/Z3_DATA<9>_TRST 10: D<11>.PIN 20: Z3_ADR<5> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs SHUT_UP .X..X........XXXXXXXXXX................. 12 A_LAN<4> .............X...X...................... 2 A_LAN<7> .............X......X................... 2 LAN_BASEADR<9> .X..X......X.XXXXXXXXXX................. 13 A_LAN<6> .....X.......X.....X.................... 3 LAN_CFG<1> ........................................ 0 LAN_BASEADR<14> .X..X.X......XXXXXXXXXX................. 13 LAN_CFG<3> ........................................ 0 LAN_BASEADR<13> .X..X..X.....XXXXXXXXXX................. 13 D<6> ..X......................X..X........... 3 LAN_BASEADR<12> .X..X...X....XXXXXXXXXX................. 13 D<3> ..X.....................X...X........... 3 LAN_BASEADR<11> .X..X....X...XXXXXXXXXX................. 13 D<7> ..X.......................X.X........... 3 D<1> ..X....................X....X........... 3 LAN_BASEADR<10> .X..X.....X..XXXXXXXXXX................. 13 D<8> X.XX.......................XX........... 5 LAN_BASEADR<0> .X..X.......XXXXXXXXXXX................. 13 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB3 *********************************** Number of function block inputs used/remaining: 5/49 Number of signals used by logic mapping into function block: 5 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB3_1 (b) IDE_W 1 0 0 4 FB3_2 28 I/O O (unused) 0 0 0 5 FB3_3 (b) (unused) 0 0 0 5 FB3_4 (b) (unused) 0 0 0 5 FB3_5 (b) (unused) 0 0 0 5 FB3_6 (b) (unused) 0 0 0 5 FB3_7 (b) (unused) 0 0 0 5 FB3_8 (b) (unused) 0 0 0 5 FB3_9 (b) (unused) 0 0 0 5 FB3_10 30 GCK/I/O GCK (unused) 0 0 0 5 FB3_11 (b) (unused) 0 0 0 5 FB3_12 31 I/O (unused) 0 0 0 5 FB3_13 (b) INT_OUT 1 0 0 4 FB3_14 32 GCK/I/O O (unused) 0 0 0 5 FB3_15 33 I/O (unused) 0 0 0 5 FB3_16 (b) (unused) 0 0 0 5 FB3_17 (b) (unused) 0 0 0 5 FB3_18 (b) Signals Used by Logic in Function Block 1: AS 3: LAN_INT_ENABLE 5: RW 2: IDE_ACCESS 4: LAN_IRQ_OUT Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs IDE_W XX..X................................... 3 INT_OUT ..XX.................................... 2 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB4 *********************************** Number of function block inputs used/remaining: 29/25 Number of signals used by logic mapping into function block: 29 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use D_Z2_OUT<0> 12 7<- 0 0 FB4_1 (b) (b) D<0> 2 0 /\3 0 FB4_2 2 GTS/I/O I/O $OpTx$FX_DC$34 1 0 0 4 FB4_3 (b) (b) D_Z2_OUT<3> 3 0 0 2 FB4_4 (b) (b) A_LAN<1> 1 0 0 4 FB4_5 3 GTS/I/O O A_LAN<0> 1 0 0 4 FB4_6 4 I/O O D_Z2_OUT<2> 3 0 0 2 FB4_7 (b) (b) A_LAN<3> 2 0 0 3 FB4_8 5 GTS/I/O O AUTO_CONFIG_Z2_DONE_CYCLE<0> 3 0 0 2 FB4_9 (b) (b) CP_BASEADR<6> 4 0 0 1 FB4_10 (b) (b) AUTO_CONFIG_Z2_DONE_CYCLE<1> 4 0 0 1 FB4_11 (b) (b) A_LAN<2> 1 0 \/2 2 FB4_12 6 GTS/I/O O BUF_D_Z2_OUT<2> 6 2<- \/1 0 FB4_13 (b) (b) A_LAN<5> 1 1<- \/5 0 FB4_14 7 I/O O BUF_D_Z2_OUT<3> 9 5<- \/1 0 FB4_15 (b) (b) D_Z2_OUT<1> 11 6<- 0 0 FB4_16 (b) (b) (unused) 0 0 /\5 0 FB4_17 (b) (b) $OpTx$FX_DC$35 1 0 \/4 0 FB4_18 (b) (b) Signals Used by Logic in Function Block 1: $OpTx$FX_DC$16 11: A<4> 21: RW 2: $OpTx$FX_DC$34 12: A<5> 22: SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF 3: $OpTx$FX_DC$49 13: A<6> 23: Z3_ADR<2> 4: AUTO_CONFIG_Z2_DONE<0> 14: BUF_D_Z2_OUT<2> 24: Z3_ADR<4> 5: AUTO_CONFIG_Z2_DONE<1> 15: BUF_D_Z2_OUT<3> 25: Z3_ADR_0 6: AUTO_CONFIG_Z2_DONE_CYCLE<0> 16: CP_BASEADR<6> 26: Z3_ADR_1 7: AUTO_CONFIG_Z2_DONE_CYCLE<1> 17: D_9_IOBUFE/D_9_IOBUFE_TRST 27: Z3_A_LOW 8: A<1> 18: LAN_A_INIT<3> 28: Z3_DATA<16> 9: A<2> 19: D<14>.PIN 29: Z3_DATA<9>/Z3_DATA<9>_TRST 10: A<3> 20: RESET Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs D_Z2_OUT<0> X.XXX..XXXXXXXX....X.X.................. 14 D<0> ................X..........XX........... 3 $OpTx$FX_DC$34 X..X...XX.XXXX......X................... 9 D_Z2_OUT<3> ..............X....X.X.................. 3 A_LAN<1> ...................X....X............... 2 A_LAN<0> ...................X......X............. 2 D_Z2_OUT<2> .............X.....X.X.................. 3 A_LAN<3> .................X.X..X................. 3 AUTO_CONFIG_Z2_DONE_CYCLE<0> X..X.X.X.XXXX......XXX.................. 11 CP_BASEADR<6> .X.............X..XX.X.................. 5 AUTO_CONFIG_Z2_DONE_CYCLE<1> X..XX.XXXXXXX......XXX.................. 13 A_LAN<2> ...................X.....X.............. 2 BUF_D_Z2_OUT<2> X..X...XXXXXX........................... 8 A_LAN<5> ...................X...X................ 2 BUF_D_Z2_OUT<3> X.XX...XXXXXXX.......................... 10 D_Z2_OUT<1> X..X....XXXXXXX....X.X.................. 11 $OpTx$FX_DC$35 X..XX..XX.XXXX......X................... 10 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB5 *********************************** Number of function block inputs used/remaining: 38/16 Number of signals used by logic mapping into function block: 38 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use LAN_BASEADR<8> 3 0 0 2 FB5_1 (b) (b) CP_CS 0 0 0 5 FB5_2 34 I/O O LAN_BASEADR<7> 3 0 0 2 FB5_3 (b) (b) LAN_BASEADR<6> 3 0 0 2 FB5_4 (b) (b) ROM_OE 1 0 0 4 FB5_5 35 I/O O LAN_BASEADR<5> 3 0 0 2 FB5_6 (b) (b) LAN_BASEADR<4> 3 0 0 2 FB5_7 (b) (b) LAN_BASEADR<3> 3 0 0 2 FB5_8 38 GCK/I/O (b) LAN_BASEADR<2> 3 0 0 2 FB5_9 (b) (b) D<2> 2 0 0 3 FB5_10 39 I/O I/O LAN_BASEADR<1> 3 0 0 2 FB5_11 (b) (b) D<9> 3 0 0 2 FB5_12 40 I/O I/O LAN_BASEADR<15> 3 0 0 2 FB5_13 (b) (b) D<10> 3 0 0 2 FB5_14 41 I/O I/O D<11> 3 0 0 2 FB5_15 43 I/O I/O D_OUT<6> 4 0 0 1 FB5_16 (b) (b) D<12> 4 0 0 1 FB5_17 44 I/O I/O D_OUT<5> 4 0 0 1 FB5_18 (b) (b) Signals Used by Logic in Function Block 1: $OpTx$FX_DC$36 14: D<15>.PIN 27: Z3_ADR<3> 2: $OpTx$FX_SC$66 15: D<8>.PIN 28: Z3_ADR<4> 3: AS 16: D<7>.PIN 29: Z3_ADR<5> 4: AUTOCONFIG_Z3_ACCESS 17: D<6>.PIN 30: Z3_ADR<6> 5: D_9_IOBUFE/D_9_IOBUFE_TRST 18: D<5>.PIN 31: Z3_ADR_0 6: D_OUT<1> 19: D<4>.PIN 32: Z3_ADR_1 7: D_OUT<2> 20: D<3>.PIN 33: Z3_DATA<18> 8: D_OUT<3> 21: D<2>.PIN 34: Z3_DATA<25> 9: D_OUT<4> 22: D<1>.PIN 35: Z3_DATA<26> 10: D_Z2_OUT<0> 23: RESET 36: Z3_DATA<27> 11: FCS 24: RW 37: Z3_DATA<28> 12: IDE_ACCESS 25: UDS 38: Z3_DATA<9>/Z3_DATA<9>_TRST 13: IDE_ENABLE 26: Z3_ADR<2> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs LAN_BASEADR<8> ...X......X...X.......XXXXXXXXXX........ 13 CP_CS ........................................ 0 LAN_BASEADR<7> ...X......X....X......XXXXXXXXXX........ 13 LAN_BASEADR<6> ...X......X.....X.....XXXXXXXXXX........ 13 ROM_OE ..X........XX..........X................ 4 LAN_BASEADR<5> ...X......X......X....XXXXXXXXXX........ 13 LAN_BASEADR<4> ...X......X.......X...XXXXXXXXXX........ 13 LAN_BASEADR<3> ...X......X........X..XXXXXXXXXX........ 13 LAN_BASEADR<2> ...X......X.........X.XXXXXXXXXX........ 13 D<2> ....X...........................X....X.. 3 LAN_BASEADR<1> ...X......X..........XXXXXXXXXXX........ 13 D<9> X...XX...........................X...X.. 5 LAN_BASEADR<15> ...X......X..X........XXXXXXXXXX........ 13 D<10> X...X.X...........................X..X.. 5 D<11> X...X..X...........................X.X.. 5 D_OUT<6> ...X......X...........X.XXXXXXXX........ 11 D<12> XX..X...XX..........................XX.. 7 D_OUT<5> ...X......X...........X.XXXXXXXX........ 11 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB6 *********************************** Number of function block inputs used/remaining: 25/29 Number of signals used by logic mapping into function block: 25 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB6_1 (b) LAN_CFG<2> 0 0 0 5 FB6_2 135 I/O O A_LAN<12> 1 0 0 4 FB6_3 136 I/O O $OpTx$FX_DC$57 1 0 0 4 FB6_4 (b) (b) A_LAN<13> 1 0 0 4 FB6_5 137 I/O O A_LAN<10> 1 0 0 4 FB6_6 138 I/O O $OpTx$FX_DC$37 1 0 0 4 FB6_7 (b) (b) A_LAN<11> 1 0 0 4 FB6_8 139 I/O O $OpTx$FX_DC$12 1 0 0 4 FB6_9 (b) (b) A_LAN<8> 1 0 0 4 FB6_10 140 I/O O $OpTx$FX_DC$10 1 0 0 4 FB6_11 (b) (b) SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF 2 0 0 3 FB6_12 (b) (b) LAN_READY 2 0 0 3 FB6_13 (b) (b) A_LAN<9> 1 0 0 4 FB6_14 142 I/O O $OpTx$FX_DC$63 2 0 0 3 FB6_15 143 GSR/I/O I $OpTx$FX_DC$62 2 0 0 3 FB6_16 (b) (b) $OpTx$FX_DC$61 2 0 0 3 FB6_17 (b) (b) $OpTx$FX_DC$60 2 0 0 3 FB6_18 (b) (b) Signals Used by Logic in Function Block 1: $OpTx$FX_DC$12 10: LAN_BASEADR<9> 18: RESET 2: BUF_LAN_READY 11: LAN_SM_FSM_FFd2 19: UDS 3: C1 12: LAN_SM_RST 20: Z3_ADR<10> 4: C3 13: LDS 21: Z3_ADR<11> 5: DS0 14: D<15>.PIN 22: Z3_ADR<12> 6: DS1 15: D<10>.PIN 23: Z3_ADR<7> 7: LAN_BASEADR<10> 16: D<9>.PIN 24: Z3_ADR<8> 8: LAN_BASEADR<15> 17: D<8>.PIN 25: Z3_ADR<9> 9: LAN_BASEADR<8> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs LAN_CFG<2> ........................................ 0 A_LAN<12> .................X..X................... 2 $OpTx$FX_DC$57 .X........X............................. 2 A_LAN<13> .................X...X.................. 2 A_LAN<10> .................X......X............... 2 $OpTx$FX_DC$37 X...........X........................... 2 A_LAN<11> .................X.X.................... 2 $OpTx$FX_DC$12 ....XX.................................. 2 A_LAN<8> .................X....X................. 2 $OpTx$FX_DC$10 ............X.....X..................... 2 SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF ..XX.................................... 2 LAN_READY .X.........X............................ 2 A_LAN<9> .................X.....X................ 2 $OpTx$FX_DC$63 .......X.....X.......................... 2 $OpTx$FX_DC$62 ........X.......X....................... 2 $OpTx$FX_DC$61 .........X.....X........................ 2 $OpTx$FX_DC$60 ......X.......X......................... 2 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB7 *********************************** Number of function block inputs used/remaining: 40/14 Number of signals used by logic mapping into function block: 40 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use CP_ACCESS 19 14<- 0 0 FB7_1 (b) (b) (unused) 0 0 /\5 0 FB7_2 (b) (b) D<13> 4 2<- /\3 0 FB7_3 45 I/O I/O (unused) 0 0 /\2 3 FB7_4 (b) (b) D<14> 4 0 0 1 FB7_5 46 I/O I/O (unused) 0 0 0 5 FB7_6 (b) (unused) 0 0 0 5 FB7_7 (b) (unused) 0 0 0 5 FB7_8 (b) (unused) 0 0 0 5 FB7_9 (b) SHUT_UP_Z2<0> 3 0 0 2 FB7_10 (b) (b) CP_BASEADR<5> 4 0 0 1 FB7_11 (b) (b) D<15> 4 0 0 1 FB7_12 48 I/O I/O CP_BASEADR<4> 4 0 0 1 FB7_13 (b) (b) CP_BASEADR<3> 4 0 0 1 FB7_14 (b) (b) CP_BASEADR<2> 4 0 0 1 FB7_15 49 I/O I CP_BASEADR<1> 4 0 0 1 FB7_16 (b) (b) CP_BASEADR<0> 4 0 \/1 0 FB7_17 (b) (b) (unused) 0 0 \/5 0 FB7_18 (b) (b) Signals Used by Logic in Function Block 1: $OpTx$FX_DC$34 15: D_OUT<6> 28: D<9>.PIN 2: $OpTx$FX_DC$36 16: D_OUT<7> 29: D<8>.PIN 3: $OpTx$FX_SC$66 17: D_Z2_OUT<1> 30: A<20>.PIN 4: AS 18: D_Z2_OUT<2> 31: A<21>.PIN 5: CP_BASEADR<0> 19: D_Z2_OUT<3> 32: A<16>.PIN 6: CP_BASEADR<1> 20: A<17>.PIN 33: A<22>.PIN 7: CP_BASEADR<2> 21: A<23>.PIN 34: RESET 8: CP_BASEADR<3> 22: A<18>.PIN 35: SHUT_UP_Z2<0> 9: CP_BASEADR<4> 23: A<19>.PIN 36: SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF 10: CP_BASEADR<5> 24: D<13>.PIN 37: Z3_DATA<29> 11: CP_BASEADR<6> 25: D<12>.PIN 38: Z3_DATA<30> 12: CP_BASEADR<7> 26: D<11>.PIN 39: Z3_DATA<31> 13: D_9_IOBUFE/D_9_IOBUFE_TRST 27: D<10>.PIN 40: Z3_DATA<9>/Z3_DATA<9>_TRST 14: D_OUT<5> Signal 1 2 3 4 5 FB Name 0----+----0----+----0----+----0----+----0----+----0 Inputs CP_ACCESS ...XXXXXXXXX.......XXXX......XXXXXX............... 19 D<13> .XX.........XX..X...................X..X.......... 7 D<14> .XX.........X.X..X...................X.X.......... 7 SHUT_UP_Z2<0> X................................XXX.............. 4 CP_BASEADR<5> X........X.............X.........X.X.............. 5 D<15> .XX.........X..X..X...................XX.......... 7 CP_BASEADR<4> X.......X...............X........X.X.............. 5 CP_BASEADR<3> X......X.................X.......X.X.............. 5 CP_BASEADR<2> X.....X...................X......X.X.............. 5 CP_BASEADR<1> X....X.....................X.....X.X.............. 5 CP_BASEADR<0> X...X.......................X....X.X.............. 5 0----+----1----+----2----+----3----+----4----+----5 0 0 0 0 0 *********************************** FB8 *********************************** Number of function block inputs used/remaining: 40/14 Number of signals used by logic mapping into function block: 40 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use $OpTx$FX_DC$59 2 1<- /\4 0 FB8_1 (b) (b) DQ<12> 2 0 /\1 2 FB8_2 130 I/O I/O DQ<14> 2 0 0 3 FB8_3 131 I/O I/O SHUT_UP_Z2<1> 3 0 0 2 FB8_4 (b) (b) LAN_WRH 2 0 0 3 FB8_5 132 I/O O IDE_BASEADR<7> 4 0 0 1 FB8_6 (b) (b) IDE_BASEADR<6> 4 0 0 1 FB8_7 (b) (b) LAN_CS 2 0 0 3 FB8_8 133 I/O O IDE_BASEADR<5> 4 0 0 1 FB8_9 (b) (b) LAN_RD 1 0 0 4 FB8_10 134 I/O O IDE_BASEADR<4> 4 0 0 1 FB8_11 (b) (b) IDE_BASEADR<3> 4 0 0 1 FB8_12 (b) (b) IDE_BASEADR<2> 4 0 0 1 FB8_13 (b) (b) IDE_BASEADR<1> 4 0 \/1 0 FB8_14 (b) (b) IDE_BASEADR<0> 4 1<- \/2 0 FB8_15 (b) (b) CP_BASEADR<7> 4 2<- \/3 0 FB8_16 (b) (b) (unused) 0 0 \/5 0 FB8_17 (b) (b) BUF_IDE_ACCESS 17 12<- 0 0 FB8_18 (b) (b) Signals Used by Logic in Function Block 1: $OpTx$FX_DC$34 15: IDE_BASEADR<7> 28: D<13>.PIN 2: $OpTx$FX_DC$35 16: LAN_ACCESS 29: D<12>.PIN 3: $OpTx$FX_DC$44 17: LAN_BASEADR<11> 30: D<11>.PIN 4: CP_BASEADR<7> 18: LAN_CS_RST 31: D<10>.PIN 5: DQ_5_IOBUFE/DQ_5_IOBUFE_TRST 19: LAN_RD_S 32: D<9>.PIN 6: DQ_DATA<12> 20: LAN_WRH_S 33: D<8>.PIN 7: DQ_DATA<14> 21: LAN_WR_RST 34: A<20>.PIN 8: IDE_BASEADR<0> 22: A<17>.PIN 35: A<21>.PIN 9: IDE_BASEADR<1> 23: A<23>.PIN 36: A<16>.PIN 10: IDE_BASEADR<2> 24: A<18>.PIN 37: A<22>.PIN 11: IDE_BASEADR<3> 25: A<19>.PIN 38: RESET 12: IDE_BASEADR<4> 26: D<15>.PIN 39: SHUT_UP_Z2<1> 13: IDE_BASEADR<5> 27: D<14>.PIN 40: SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF 14: IDE_BASEADR<6> Signal 1 2 3 4 5 FB Name 0----+----0----+----0----+----0----+----0----+----0 Inputs $OpTx$FX_DC$59 ................X............X.................... 2 DQ<12> ....XX...............................X............ 3 DQ<14> ....X.X..............................X............ 3 SHUT_UP_Z2<1> .X...................................XXX.......... 4 LAN_WRH ..X................XX............................. 3 IDE_BASEADR<7> .X............X..........X...........X.X.......... 5 IDE_BASEADR<6> .X...........X............X..........X.X.......... 5 LAN_CS ...............X.X...................X............ 3 IDE_BASEADR<5> .X..........X..............X.........X.X.......... 5 LAN_RD ..X...............X............................... 2 IDE_BASEADR<4> .X.........X................X........X.X.......... 5 IDE_BASEADR<3> .X........X..................X.......X.X.......... 5 IDE_BASEADR<2> .X.......X....................X......X.X.......... 5 IDE_BASEADR<1> .X......X......................X.....X.X.......... 5 IDE_BASEADR<0> .X.....X........................X....X.X.......... 5 CP_BASEADR<7> X..X.....................X...........X.X.......... 5 BUF_IDE_ACCESS .......XXXXXXXX......XXXX........XXXX.X........... 17 0----+----1----+----2----+----3----+----4----+----5 0 0 0 0 0 *********************************** FB9 *********************************** Number of function block inputs used/remaining: 39/15 Number of signals used by logic mapping into function block: 39 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use DQ_DATA<13> 6 3<- \/2 0 FB9_1 (b) (b) DQ_DATA<14> 6 2<- \/1 0 FB9_2 50 I/O I DQ_DATA<15> 6 1<- 0 0 FB9_3 51 I/O I DQ_DATA<5> 6 1<- 0 0 FB9_4 (b) (b) DQ_DATA<6> 6 2<- /\1 0 FB9_5 52 I/O I DQ_DATA<7> 6 3<- /\2 0 FB9_6 53 I/O I $OpTx$INV$5 4 2<- /\3 0 FB9_7 (b) (b) Z3_ADR<11> 3 0 /\2 0 FB9_8 54 I/O I Z3_ADR<12> 3 0 0 2 FB9_9 (b) (b) Z3_ADR<13> 3 0 0 2 FB9_10 (b) (b) A<8> 5 0 0 0 FB9_11 56 I/O I/O $OpTx$FX_DC$44 1 0 0 4 FB9_12 57 I/O I LAN_A_INIT<3> 1 0 0 4 FB9_13 (b) (b) A<9> 5 0 0 0 FB9_14 58 I/O I/O (unused) 0 0 0 5 FB9_15 (b) (unused) 0 0 0 5 FB9_16 (b) A<10> 5 0 0 0 FB9_17 59 I/O I/O (unused) 0 0 \/3 2 FB9_18 (b) (b) Signals Used by Logic in Function Block 1: $OpTx$FX_DC$10 14: LAN_BASEADR<6> 27: DQ<0>.PIN 2: $OpTx$FX_DC$30 15: LAN_SM_FSM_FFd1 28: D<15>.PIN 3: $OpTx$FX_DC$50 16: LAN_SM_FSM_FFd2 29: D<14>.PIN 4: $OpTx$FX_SC$31 17: LAN_SM_FSM_FFd3 30: D<13>.PIN 5: DQ_DATA<13> 18: LAN_SM_FSM_FFd4 31: A<14>.PIN 6: DQ_DATA<14> 19: LAN_SM_RST 32: D<7>.PIN 7: DQ_DATA<15> 20: A<23>.PIN 33: D<6>.PIN 8: DQ_DATA<5> 21: DQ<10>.PIN 34: D<5>.PIN 9: DQ_DATA<6> 22: DQ<9>.PIN 35: A<15>.PIN 10: DQ_DATA<7> 23: DQ<8>.PIN 36: A<21>.PIN 11: DQ_SWAP 24: DQ<2>.PIN 37: A<22>.PIN 12: FCS 25: A<13>.PIN 38: RESET 13: LAN_BASEADR<13> 26: DQ<1>.PIN 39: RW Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs DQ_DATA<13> XX.XX.....X.....XXX.....X....X...X.X.... 12 DQ_DATA<14> XX.X.X....X.....XXX.........X.X.X...X... 12 DQ_DATA<15> XX.X..X...X.....XXXX.......X...X..X..... 12 DQ_DATA<5> XX.X...X..X.....XXX.....X....X...X.X.... 12 DQ_DATA<6> XX.X....X.X.....XXX.........X.X.X...X... 12 DQ_DATA<7> XX.X.....XX.....XXXX.......X...X..X..... 12 $OpTx$INV$5 ............XX...............X......X... 4 Z3_ADR<11> ...........X............X............X.. 3 Z3_ADR<12> ...........X..................X......X.. 3 Z3_ADR<13> ...........X......................X..X.. 3 A<8> ..X.......XX..XXXXX...X...X...........X. 11 $OpTx$FX_DC$44 ...........X.........................X.. 2 LAN_A_INIT<3> .....................................X.. 1 A<9> ..X.......XX..XXXXX..X...X............X. 11 A<10> ..X.......XX..XXXXX.X..X..............X. 11 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB10 *********************************** Number of function block inputs used/remaining: 40/14 Number of signals used by logic mapping into function block: 40 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB10_1 (b) DQ<1> 3 0 0 2 FB10_2 117 I/O I/O DQ<0> 2 0 0 3 FB10_3 118 I/O I/O (unused) 0 0 0 5 FB10_4 (b) DQ<3> 2 0 0 3 FB10_5 119 I/O I/O DQ<2> 2 0 0 3 FB10_6 120 I/O I/O (unused) 0 0 0 5 FB10_7 (b) DQ<5> 2 0 0 3 FB10_8 121 I/O I/O (unused) 0 0 0 5 FB10_9 (b) DQ<4> 3 0 0 2 FB10_10 124 I/O I/O DQ<7> 2 0 0 3 FB10_11 125 I/O I/O DQ<6> 2 0 0 3 FB10_12 126 I/O I/O AUTOCONFIG_Z3_ACCESS 3 0 0 2 FB10_13 (b) (b) DQ<8> 3 0 0 2 FB10_14 128 I/O I/O AUTO_CONFIG_Z2_DONE<1> 4 0 0 1 FB10_15 (b) (b) AUTO_CONFIG_Z2_DONE<0> 4 0 0 1 FB10_16 (b) (b) DQ<10> 3 0 0 2 FB10_17 129 I/O I/O AUTOCONFIG_Z2_ACCESS 4 0 0 1 FB10_18 (b) (b) Signals Used by Logic in Function Block 1: AS 15: DQ_DATA<5> 28: D<13>.PIN 2: AUTO_CONFIG_DONE 16: DQ_DATA<6> 29: D<12>.PIN 3: AUTO_CONFIG_Z2_DONE<0> 17: DQ_DATA<7> 30: D<11>.PIN 4: AUTO_CONFIG_Z2_DONE<1> 18: DQ_DATA<8> 31: D<10>.PIN 5: AUTO_CONFIG_Z2_DONE_CYCLE<0> 19: FCS 32: D<9>.PIN 6: AUTO_CONFIG_Z2_DONE_CYCLE<1> 20: LAN_D_INIT<1> 33: D<8>.PIN 7: CFIN 21: LAN_D_INIT<8> 34: A<20>.PIN 8: DQ_5_IOBUFE/DQ_5_IOBUFE_TRST 22: A<17>.PIN 35: A<21>.PIN 9: DQ_DATA<0> 23: A<23>.PIN 36: A<16>.PIN 10: DQ_DATA<10> 24: A<18>.PIN 37: A<22>.PIN 11: DQ_DATA<1> 25: A<19>.PIN 38: RESET 12: DQ_DATA<2> 26: D<15>.PIN 39: SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF 13: DQ_DATA<3> 27: D<14>.PIN 40: Z3 14: DQ_DATA<4> Signal 1 2 3 4 5 FB Name 0----+----0----+----0----+----0----+----0----+----0 Inputs DQ<1> .......X..X........X.................X............ 4 DQ<0> .......XX............................X............ 3 DQ<3> .......X....X........................X............ 3 DQ<2> .......X...X.........................X............ 3 DQ<5> .......X......X......................X............ 3 DQ<4> .......X.....X.....X.................X............ 4 DQ<7> .......X........X....................X............ 3 DQ<6> .......X.......X.....................X............ 3 AUTOCONFIG_Z3_ACCESS .X....X...........X..XXXXXXXXXXXXXXXXX.X.......... 21 DQ<8> .......X.........X..X................X............ 4 AUTO_CONFIG_Z2_DONE<1> X..X.X...............................XX........... 5 AUTO_CONFIG_Z2_DONE<0> X.X.X................................XX........... 5 DQ<10> .......X.X..........X................X............ 4 AUTOCONFIG_Z2_ACCESS X.XX..X..............XXXX........XXXXX............ 13 0----+----1----+----2----+----3----+----4----+----5 0 0 0 0 0 *********************************** FB11 *********************************** Number of function block inputs used/remaining: 34/20 Number of signals used by logic mapping into function block: 34 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use Z3_DATA<30> 4 0 /\1 0 FB11_1 (b) (b) Z3_DATA<29> 4 0 0 1 FB11_2 (b) (b) A<11> 5 0 0 0 FB11_3 60 I/O I/O Z3_DATA<22> 4 0 0 1 FB11_4 (b) (b) A<12> 5 0 0 0 FB11_5 61 I/O I/O Z3_DATA<21> 4 0 0 1 FB11_6 (b) (b) LAN_SM_FSM_FFd4 4 0 0 1 FB11_7 (b) (b) LAN_SM_FSM_FFd2 4 0 0 1 FB11_8 (b) (b) LAN_RD_S 4 0 0 1 FB11_9 (b) (b) A<13> 5 0 0 0 FB11_10 64 I/O I/O A<14> 5 0 0 0 FB11_11 66 I/O I/O ROM_B<0> 0 0 0 5 FB11_12 68 I/O O LAN_SM_FSM_FFd1 5 0 0 0 FB11_13 (b) (b) ROM_B<1> 0 0 \/1 4 FB11_14 69 I/O O DQ_DATA<8> 6 1<- 0 0 FB11_15 (b) (b) DQ_DATA<10> 6 1<- 0 0 FB11_16 (b) (b) CP_WE 0 0 /\1 4 FB11_17 70 I/O O DQ_DATA<0> 6 1<- 0 0 FB11_18 (b) (b) Signals Used by Logic in Function Block 1: $OpTx$FX_DC$10 13: A<10>.PIN 24: DQ<11>.PIN 2: $OpTx$FX_DC$12 14: LAN_SM_FSM_FFd1 25: DQ<6>.PIN 3: $OpTx$FX_DC$30 15: LAN_SM_FSM_FFd2 26: DQ<5>.PIN 4: $OpTx$FX_DC$50 16: LAN_SM_FSM_FFd3 27: DQ<4>.PIN 5: $OpTx$FX_DC$57 17: LAN_SM_FSM_FFd4 28: DQ<3>.PIN 6: $OpTx$FX_SC$31 18: LAN_SM_RST 29: D<10>.PIN 7: BUF_LAN_READY 19: A<18>.PIN 30: D<8>.PIN 8: DQ_DATA<0> 20: A<8>.PIN 31: D<2>.PIN 9: DQ_DATA<10> 21: DQ<14>.PIN 32: D<0>.PIN 10: DQ_DATA<8> 22: DQ<13>.PIN 33: A<16>.PIN 11: DQ_SWAP 23: DQ<12>.PIN 34: RW 12: FCS Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs Z3_DATA<30> ..........X..XX.XX..X...X............... 7 Z3_DATA<29> ..........X..XX.XX...X...X.............. 7 A<11> ...X......XX.XXXXX.....X...X.....X...... 11 Z3_DATA<22> ..........X..XX.XX..X...X............... 7 A<12> ...X......XX.XXXXX....X...X......X...... 11 Z3_DATA<21> ..........X..XX.XX...X...X.............. 7 LAN_SM_FSM_FFd4 ....X.X......XXXXX...................... 7 LAN_SM_FSM_FFd2 XX...........XXXXX...................... 7 LAN_RD_S .............XXXXX...............X...... 6 A<13> ...X......XX.XXXXX...X...X.......X...... 11 A<14> ...X......XX.XXXXX..X...X........X...... 11 ROM_B<0> ........................................ 0 LAN_SM_FSM_FFd1 ....X.X......XXXXX...............X...... 8 ROM_B<1> ........................................ 0 DQ_DATA<8> X.X..X...XX....XXX.X.........X.XX....... 12 DQ_DATA<10> X.X..X..X.X.X..XXXX.........X.X......... 12 CP_WE ........................................ 0 DQ_DATA<0> X.X..X.X..X....XXX.X.........X.XX....... 12 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB12 *********************************** Number of function block inputs used/remaining: 19/35 Number of signals used by logic mapping into function block: 19 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use LAN_SM_RST 1 0 0 4 FB12_1 (b) (b) LAN_CFG<4> 0 0 0 5 FB12_2 110 I/O O LAN_IRQ_D0 2 0 0 3 FB12_3 111 I/O I LAN_D_INIT<8> 2 0 0 3 FB12_4 (b) (b) DQ<15> 2 0 0 3 FB12_5 112 I/O I/O LAN_D_INIT<1> 2 0 0 3 FB12_6 (b) (b) LAN_A_INIT<6> 2 0 0 3 FB12_7 (b) (b) DQ<13> 2 0 0 3 FB12_8 113 I/O I/O CONFIG_READY 2 0 0 3 FB12_9 (b) (b) DQ<11> 3 0 0 2 FB12_10 115 I/O I/O BUF_LAN_D_INIT<1> 2 0 0 3 FB12_11 (b) (b) DQ<9> 3 0 0 2 FB12_12 116 I/O I/O LAN_WR_RST 3 0 0 2 FB12_13 (b) (b) LAN_RST_SM_FSM_FFd3 3 0 0 2 FB12_14 (b) (b) LAN_RST_SM_FSM_FFd2 3 0 0 2 FB12_15 (b) (b) LAN_RST_SM_FSM_FFd1 3 0 0 2 FB12_16 (b) (b) LAN_IRQ_OUT 3 0 0 2 FB12_17 (b) (b) LAN_CS_RST 3 0 0 2 FB12_18 (b) (b) Signals Used by Logic in Function Block 1: $OpTx$FX_DC$44 8: DQ_DATA<13> 14: LAN_IRQ_D0 2: $OpTx$FX_DC$50 9: DQ_DATA<15> 15: LAN_IRQ_OUT 3: BERR 10: DQ_DATA<9> 16: LAN_RST_SM_FSM_FFd1 4: BUF_CONFIG_READY 11: LAN_D_INIT<1> 17: LAN_RST_SM_FSM_FFd2 5: BUF_LAN_D_INIT<1> 12: LAN_D_INIT<8> 18: LAN_RST_SM_FSM_FFd3 6: DQ_5_IOBUFE/DQ_5_IOBUFE_TRST 13: LAN_INT 19: RESET 7: DQ_DATA<11> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs LAN_SM_RST XXXX.................................... 4 LAN_CFG<4> ........................................ 0 LAN_IRQ_D0 ............X.....X..................... 2 LAN_D_INIT<8> ....X.............X..................... 2 DQ<15> .....X..X.........X..................... 3 LAN_D_INIT<1> ....X.............X..................... 2 LAN_A_INIT<6> ....X.............X..................... 2 DQ<13> .....X.X..........X..................... 3 CONFIG_READY ...X..............X..................... 2 DQ<11> .....XX....X......X..................... 4 BUF_LAN_D_INIT<1> ...............XXX...................... 3 DQ<9> .....X...XX.......X..................... 4 LAN_WR_RST ...............XXXX..................... 4 LAN_RST_SM_FSM_FFd3 ...............XXXX..................... 4 LAN_RST_SM_FSM_FFd2 ...............XXXX..................... 4 LAN_RST_SM_FSM_FFd1 ...............XXXX..................... 4 LAN_IRQ_OUT ............XXX...X..................... 4 LAN_CS_RST ...............XXXX..................... 4 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB13 *********************************** Number of function block inputs used/remaining: 39/15 Number of signals used by logic mapping into function block: 39 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 /\2 3 FB13_1 (b) (b) CP_RD 0 0 0 5 FB13_2 71 I/O O (unused) 0 0 0 5 FB13_3 (b) D_OUT<7> 2 0 0 3 FB13_4 (b) (b) D_OUT<3> 2 0 0 3 FB13_5 (b) (b) D_OUT<0> 2 0 0 3 FB13_6 (b) (b) Z3_ADR<8> 3 0 0 2 FB13_7 (b) (b) A<15> 5 0 0 0 FB13_8 74 I/O I/O Z3_ADR<7> 3 0 0 2 FB13_9 (b) (b) D_OUT<2> 3 0 0 2 FB13_10 (b) (b) AUTO_CONFIG_DONE_CYCLE 3 0 0 2 FB13_11 75 I/O (b) AUTO_CONFIG_DONE 3 0 0 2 FB13_12 (b) (b) D_OUT<4> 4 0 0 1 FB13_13 (b) (b) LAN_WRL 2 0 0 3 FB13_14 76 I/O O D_OUT<1> 4 0 \/1 0 FB13_15 77 I/O I DQ_DATA<9> 6 1<- 0 0 FB13_16 (b) (b) DQ_DATA<2> 6 1<- 0 0 FB13_17 78 I/O I DQ_DATA<1> 6 2<- /\1 0 FB13_18 (b) (b) Signals Used by Logic in Function Block 1: $OpTx$FX_DC$10 14: A<10>.PIN 27: D<9>.PIN 2: $OpTx$FX_DC$30 15: LAN_SM_FSM_FFd1 28: D<2>.PIN 3: $OpTx$FX_DC$44 16: LAN_SM_FSM_FFd2 29: D<1>.PIN 4: $OpTx$FX_DC$50 17: LAN_SM_FSM_FFd3 30: RESET 5: $OpTx$FX_SC$31 18: LAN_SM_FSM_FFd4 31: RW 6: AUTOCONFIG_Z3_ACCESS 19: LAN_SM_RST 32: UDS 7: AUTO_CONFIG_DONE_CYCLE 20: LAN_WRL_S 33: Z3_ADR<2> 8: DQ_DATA<1> 21: LAN_WR_RST 34: Z3_ADR<3> 9: DQ_DATA<2> 22: A<17>.PIN 35: Z3_ADR<4> 10: DQ_DATA<9> 23: A<18>.PIN 36: Z3_ADR<5> 11: DQ_SWAP 24: DQ<15>.PIN 37: Z3_ADR<6> 12: FCS 25: DQ<7>.PIN 38: Z3_ADR_0 13: A<9>.PIN 26: D<10>.PIN 39: Z3_ADR_1 Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs CP_RD ........................................ 0 D_OUT<7> .....X.....X.................X.X.XXXX.X. 9 D_OUT<3> .....X.....X.................X.X.XXX..X. 8 D_OUT<0> .....X.....X.................X.XXXXX.XX. 10 Z3_ADR<8> ...........X.X...............X.......... 3 A<15> ...X......XX..XXXXX....XX.....X......... 11 Z3_ADR<7> ...........XX................X.......... 3 D_OUT<2> .....X.....X.................X.XXXXX.XX. 10 AUTO_CONFIG_DONE_CYCLE .....XX....X.................XXXXXXXXX.. 12 AUTO_CONFIG_DONE ......X....X.................X.......... 3 D_OUT<4> .....X.....X.................X.XXXXXXXX. 11 LAN_WRL ..X................XX................... 3 D_OUT<1> .....X.....X.................X.XXXXX.XX. 10 DQ_DATA<9> XX..X....XX.X...XXX..X....X.X........... 12 DQ_DATA<2> XX..X...X.X..X..XXX...X..X.X............ 12 DQ_DATA<1> XX..X..X..X.X...XXX..X....X.X........... 12 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB14 *********************************** Number of function block inputs used/remaining: 40/14 Number of signals used by logic mapping into function block: 40 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use $OpTx$INV$4 16 11<- 0 0 FB14_1 (b) (b) BUF_CONFIG_READY 1 0 /\4 0 FB14_2 (b) (b) OVR 1 0 0 4 FB14_3 100 I/O O $OpTx$FX_DC$49 1 0 0 4 FB14_4 (b) (b) ROM_B_0_OBUF$BUF9/ROM_B_0_OBUF$BUF9_TRST 2 0 0 3 FB14_5 101 I/O (b) ROM_B_0_OBUF$BUF2/ROM_B_0_OBUF$BUF2_TRST 2 0 0 3 FB14_6 102 I/O I $OpTx$FX_DC$50 2 0 0 3 FB14_7 (b) (b) Z3_ADR_1 3 0 0 2 FB14_8 103 I/O I Z3_ADR_0 3 0 0 2 FB14_9 (b) (b) Z3_ADR<6> 3 0 0 2 FB14_10 104 I/O I CFOUT 1 0 0 4 FB14_11 105 I/O O Z3_ADR<5> 3 0 0 2 FB14_12 (b) (b) Z3_ADR<4> 3 0 0 2 FB14_13 (b) (b) SLAVE 2 0 0 3 FB14_14 106 I/O O OWN 0 0 0 5 FB14_15 107 I/O O Z3_ADR<3> 3 0 0 2 FB14_16 (b) (b) Z3_ADR<2> 3 0 \/2 0 FB14_17 (b) (b) (unused) 0 0 \/5 0 FB14_18 (b) (b) Signals Used by Logic in Function Block 1: $OpTx$FX_DC$10 15: CONFIG_READY 28: LAN_READY 2: $OpTx$FX_DC$12 16: CP_ACCESS 29: A<17>.PIN 3: AS 17: FCS 30: A<23>.PIN 4: AUTOCONFIG_Z2_ACCESS 18: IDE_ACCESS 31: A<18>.PIN 5: AUTOCONFIG_Z3_ACCESS 19: LAN_ACCESS 32: A<19>.PIN 6: AUTO_CONFIG_DONE 20: LAN_BASEADR<0> 33: A<8>.PIN 7: AUTO_CONFIG_Z2_DONE<0> 21: LAN_BASEADR<14> 34: D<14>.PIN 8: AUTO_CONFIG_Z2_DONE<1> 22: LAN_BASEADR<1> 35: A<20>.PIN 9: A<2> 23: LAN_BASEADR<2> 36: A<21>.PIN 10: A<3> 24: LAN_BASEADR<3> 37: A<16>.PIN 11: A<4> 25: LAN_BASEADR<4> 38: RESET 12: A<5> 26: LAN_BASEADR<5> 39: ROM_B_0_OBUF$BUF2/ROM_B_0_OBUF$BUF2_TRST 13: A<6> 27: LAN_BASEADR<7> 40: Z3_ADR<13> 14: A<7> Signal 1 2 3 4 5 FB Name 0----+----0----+----0----+----0----+----0----+----0 Inputs $OpTx$INV$4 ...................XXXXXXXX.XXXX.XXXX............. 16 BUF_CONFIG_READY ................X.X....................X.......... 3 OVR ......................................X........... 1 $OpTx$FX_DC$49 ........X.X....................................... 2 ROM_B_0_OBUF$BUF9/ROM_B_0_OBUF$BUF9_TRST ....X.........X.X..........X...................... 4 ROM_B_0_OBUF$BUF2/ROM_B_0_OBUF$BUF2_TRST ....X...........X.X............................... 3 $OpTx$FX_DC$50 XX................X............................... 3 Z3_ADR_1 .........X......X....................X............ 3 Z3_ADR_0 ........X.......X....................X............ 3 Z3_ADR<6> ................X...............X....X............ 3 CFOUT .....XXX.......................................... 3 Z3_ADR<5> .............X..X....................X............ 3 Z3_ADR<4> ............X...X....................X............ 3 SLAVE ..XX...........X.X....................X........... 5 OWN .................................................. 0 Z3_ADR<3> ...........X....X....................X............ 3 Z3_ADR<2> ..........X.....X....................X............ 3 0----+----1----+----2----+----3----+----4----+----5 0 0 0 0 0 *********************************** FB15 *********************************** Number of function block inputs used/remaining: 39/15 Number of signals used by logic mapping into function block: 39 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use DQ_DATA<11> 6 2<- \/1 0 FB15_1 (b) (b) DQ_DATA<12> 6 1<- 0 0 FB15_2 79 I/O I DQ_DATA<3> 6 1<- 0 0 FB15_3 80 I/O I DQ_DATA<4> 6 2<- /\1 0 FB15_4 (b) (b) BUF_LAN_READY 4 1<- /\2 0 FB15_5 (b) (b) Z3_DATA<23> 4 0 /\1 0 FB15_6 (b) (b) Z3_DATA<31> 4 0 0 1 FB15_7 (b) (b) LAN_WRH_S 3 0 0 2 FB15_8 81 I/O I LAN_WRL_S 3 0 0 2 FB15_9 (b) (b) $OpTx$FX_DC$30 2 0 0 3 FB15_10 82 I/O I $OpTx$FX_DC$36 2 0 0 3 FB15_11 83 I/O I DTACK 1 0 0 4 FB15_12 85 I/O O $OpTx$FX_SC$31 2 0 0 3 FB15_13 (b) (b) A<23> 5 0 0 0 FB15_14 86 I/O I/O A<22> 5 0 0 0 FB15_15 87 I/O I/O $OpTx$FX_SC$66 2 0 0 3 FB15_16 (b) (b) A<21> 5 0 0 0 FB15_17 88 I/O I/O Z3_DATA<9>/Z3_DATA<9>_TRST 1 0 \/2 2 FB15_18 (b) (b) Signals Used by Logic in Function Block 1: $OpTx$FX_DC$10 14: DS1 27: A<12>.PIN 2: $OpTx$FX_DC$12 15: FCS 28: DQ<7>.PIN 3: $OpTx$FX_DC$30 16: A<11>.PIN 29: DQ<6>.PIN 4: $OpTx$FX_DC$37 17: LAN_SM_FSM_FFd1 30: DQ<5>.PIN 5: $OpTx$FX_DC$50 18: LAN_SM_FSM_FFd2 31: D<12>.PIN 6: $OpTx$FX_SC$31 19: LAN_SM_FSM_FFd3 32: D<11>.PIN 7: AUTOCONFIG_Z3_ACCESS 20: LAN_SM_FSM_FFd4 33: D<4>.PIN 8: DQ_DATA<11> 21: LAN_SM_RST 34: D<3>.PIN 9: DQ_DATA<12> 22: LDS 35: A<20>.PIN 10: DQ_DATA<3> 23: A<19>.PIN 36: ROM_B_0_OBUF$BUF9/ROM_B_0_OBUF$BUF9_TRST 11: DQ_DATA<4> 24: DQ<15>.PIN 37: RW 12: DQ_SWAP 25: DQ<14>.PIN 38: UDS 13: DS0 26: DQ<13>.PIN 39: Z3_DATA<9>/Z3_DATA<9>_TRST Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs DQ_DATA<11> X.X..X.X...X...X..XXX.X........X.X...... 12 DQ_DATA<12> X.X..X..X..X......XXX.....X...X.X.X..... 12 DQ_DATA<3> X.X..X...X.X...X..XXX.X........X.X...... 12 DQ_DATA<4> X.X..X....XX......XXX.....X...X.X.X..... 12 BUF_LAN_READY .X..............XXXX.................... 5 Z3_DATA<23> ...........X....XX.XX..X...X............ 7 Z3_DATA<31> ...........X....XX.XX..X...X............ 7 LAN_WRH_S ............X...XXXXXX.................. 7 LAN_WRL_S .............X..XXXXX................X.. 7 $OpTx$FX_DC$30 ................XXXX.................... 4 $OpTx$FX_DC$36 ...X..X.......X.....................XX.. 5 DTACK ...................................X.... 1 $OpTx$FX_SC$31 X...............XXXX.................... 5 A<23> ....X......X..X.XXXXX..X...X........X... 11 A<22> ....X......X..X.XXXXX...X...X.......X... 11 $OpTx$FX_SC$66 ...X..X.......X.....................XXX. 6 A<21> ....X......X..X.XXXXX....X...X......X... 11 Z3_DATA<9>/Z3_DATA<9>_TRST ....X.........X.....................X... 3 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB16 *********************************** Number of function block inputs used/remaining: 21/33 Number of signals used by logic mapping into function block: 21 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use Z3_DATA<28> 4 0 0 1 FB16_1 (b) (b) A<20> 5 0 0 0 FB16_2 91 I/O I/O A<19> 5 0 0 0 FB16_3 92 I/O I/O Z3_DATA<27> 4 0 0 1 FB16_4 (b) (b) Z3_DATA<26> 4 0 0 1 FB16_5 93 I/O I A<18> 5 0 0 0 FB16_6 94 I/O I/O Z3_DATA<25> 4 0 0 1 FB16_7 (b) (b) A<17> 5 0 0 0 FB16_8 95 I/O I/O Z3_DATA<24> 4 0 0 1 FB16_9 (b) (b) MTACK 0 0 0 5 FB16_10 96 I/O O A<16> 5 0 0 0 FB16_11 97 I/O I/O Z3_DATA<20> 4 0 0 1 FB16_12 98 I/O I Z3_DATA<19> 4 0 0 1 FB16_13 (b) (b) Z3_DATA<17> 4 0 0 1 FB16_14 (b) (b) Z3_DATA<16> 4 0 \/1 0 FB16_15 (b) (b) Z3_A_LOW 6 1<- 0 0 FB16_16 (b) (b) LAN_SM_FSM_FFd3 6 1<- 0 0 FB16_17 (b) (b) Z3_DATA<18> 4 0 /\1 0 FB16_18 (b) (b) Signals Used by Logic in Function Block 1: $OpTx$FX_DC$10 8: LAN_SM_FSM_FFd3 15: DQ<8>.PIN 2: $OpTx$FX_DC$12 9: LAN_SM_FSM_FFd4 16: DQ<4>.PIN 3: $OpTx$FX_DC$50 10: LAN_SM_RST 17: DQ<3>.PIN 4: DQ_SWAP 11: DQ<12>.PIN 18: DQ<2>.PIN 5: FCS 12: DQ<11>.PIN 19: DQ<1>.PIN 6: LAN_SM_FSM_FFd1 13: DQ<10>.PIN 20: DQ<0>.PIN 7: LAN_SM_FSM_FFd2 14: DQ<9>.PIN 21: RW Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs Z3_DATA<28> ...X.XX.XXX....X........................ 7 A<20> ..XXXXXXXXX....X....X................... 11 A<19> ..XXXXXXXX.X....X...X................... 11 Z3_DATA<27> ...X.XX.XX.X....X....................... 7 Z3_DATA<26> ...X.XX.XX..X....X...................... 7 A<18> ..XXXXXXXX..X....X..X................... 11 Z3_DATA<25> ...X.XX.XX...X....X..................... 7 A<17> ..XXXXXXXX...X....X.X................... 11 Z3_DATA<24> ...X.XX.XX....X....X.................... 7 MTACK ........................................ 0 A<16> ..XXXXXXXX....X....XX................... 11 Z3_DATA<20> ...X.XX.XXX....X........................ 7 Z3_DATA<19> ...X.XX.XX.X....X....................... 7 Z3_DATA<17> ...X.XX.XX...X....X..................... 7 Z3_DATA<16> ...X.XX.XX....X....X.................... 7 Z3_A_LOW XX...XXXXX.............................. 7 LAN_SM_FSM_FFd3 XX...XXXXX..........X................... 8 Z3_DATA<18> ...X.XX.XX..X....X...................... 7 0----+----1----+----2----+----3----+----4 0 0 0 0 ******************************* Equations ******************************** ********** Mapped Logic ********** $OpTx$FX_DC$10 <= (UDS AND LDS); $OpTx$FX_DC$12 <= (DS1 AND DS0); $OpTx$FX_DC$16 <= (NOT AS AND AUTOCONFIG_Z2_ACCESS AND NOT $OpTx$FX_DC$10); $OpTx$FX_DC$30 <= ((LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1) OR (NOT LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1)); $OpTx$FX_DC$34 <= (NOT AUTO_CONFIG_Z2_DONE(0) AND NOT RW AND NOT A(5) AND NOT A(4) AND NOT A(1) AND NOT A(2) AND A(6) AND $OpTx$FX_DC$16 AND NOT BUF_D_Z2_OUT(2)); $OpTx$FX_DC$35 <= (AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE(1) AND NOT RW AND NOT A(5) AND NOT A(4) AND NOT A(1) AND NOT A(2) AND A(6) AND $OpTx$FX_DC$16 AND NOT BUF_D_Z2_OUT(2)); $OpTx$FX_DC$36 <= ((NOT UDS AND RW AND NOT FCS AND AUTOCONFIG_Z3_ACCESS) OR (RW AND NOT FCS AND AUTOCONFIG_Z3_ACCESS AND NOT $OpTx$FX_DC$37)); $OpTx$FX_DC$37 <= (LDS AND $OpTx$FX_DC$12); $OpTx$FX_DC$44 <= (RESET AND NOT FCS); $OpTx$FX_DC$49 <= (NOT A(4) AND A(2)); $OpTx$FX_DC$50 <= ((NOT LAN_ACCESS) OR ($OpTx$FX_DC$10 AND $OpTx$FX_DC$12)); $OpTx$FX_DC$57 <= (LAN_SM_FSM_FFd2 AND NOT BUF_LAN_READY); $OpTx$FX_DC$59 <= D(11).PIN XOR $OpTx$FX_DC$59 <= LAN_BASEADR(11); $OpTx$FX_DC$60 <= D(10).PIN XOR $OpTx$FX_DC$60 <= LAN_BASEADR(10); $OpTx$FX_DC$61 <= D(9).PIN XOR $OpTx$FX_DC$61 <= LAN_BASEADR(9); $OpTx$FX_DC$62 <= D(8).PIN XOR $OpTx$FX_DC$62 <= LAN_BASEADR(8); $OpTx$FX_DC$63 <= D(15).PIN XOR $OpTx$FX_DC$63 <= LAN_BASEADR(15); $OpTx$FX_SC$31 <= ((NOT LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd4 AND $OpTx$FX_DC$10) OR (NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1)); $OpTx$FX_SC$66 <= ((NOT UDS AND RW AND NOT FCS AND AUTOCONFIG_Z3_ACCESS AND NOT Z3_DATA(9)/Z3_DATA(9)_TRST) OR (RW AND NOT FCS AND AUTOCONFIG_Z3_ACCESS AND NOT Z3_DATA(9)/Z3_DATA(9)_TRST AND NOT $OpTx$FX_DC$37)); $OpTx$INV$4 <= ((LAN_BASEADR(5) AND NOT A(21).PIN) OR (NOT LAN_BASEADR(5) AND A(21).PIN) OR (LAN_BASEADR(7) AND NOT A(23).PIN) OR (NOT LAN_BASEADR(7) AND A(23).PIN) OR (Z3_ADR(2).EXP) OR (A(20).PIN AND NOT LAN_BASEADR(4)) OR (NOT A(20).PIN AND LAN_BASEADR(4)) OR (A(19).PIN AND NOT LAN_BASEADR(3)) OR (NOT A(19).PIN AND LAN_BASEADR(3)) OR (NOT A(18).PIN AND LAN_BASEADR(2)) OR (A(18).PIN AND NOT LAN_BASEADR(2)) OR (A(17).PIN AND NOT LAN_BASEADR(1)) OR (NOT A(17).PIN AND LAN_BASEADR(1)) OR (A(16).PIN AND NOT LAN_BASEADR(0)) OR (NOT A(16).PIN AND LAN_BASEADR(0))); $OpTx$INV$5 <= ((D(13).PIN AND NOT LAN_BASEADR(13)) OR (NOT D(13).PIN AND LAN_BASEADR(13)) OR (LAN_BASEADR(6) AND NOT A(22).PIN) OR (NOT LAN_BASEADR(6) AND A(22).PIN)); FDCPE_A8: FDCPE port map (A_I(8),A(8),CLK_EXT,'0',LAN_SM_RST,A_CE(8)); A(8) <= ((DQ_SWAP AND DQ(8).PIN) OR (NOT DQ_SWAP AND DQ(0).PIN)); A_CE(8) <= (LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1); A(8) <= A_I(8) when A_OE(8) = '1' else 'Z'; A_OE(8) <= (RW AND NOT FCS AND NOT $OpTx$FX_DC$50); FDCPE_A9: FDCPE port map (A_I(9),A(9),CLK_EXT,'0',LAN_SM_RST,A_CE(9)); A(9) <= ((DQ_SWAP AND DQ(9).PIN) OR (NOT DQ_SWAP AND DQ(1).PIN)); A_CE(9) <= (LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1); A(9) <= A_I(9) when A_OE(9) = '1' else 'Z'; A_OE(9) <= (RW AND NOT FCS AND NOT $OpTx$FX_DC$50); FDCPE_A10: FDCPE port map (A_I(10),A(10),CLK_EXT,'0',LAN_SM_RST,A_CE(10)); A(10) <= ((DQ_SWAP AND DQ(10).PIN) OR (NOT DQ_SWAP AND DQ(2).PIN)); A_CE(10) <= (LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1); A(10) <= A_I(10) when A_OE(10) = '1' else 'Z'; A_OE(10) <= (RW AND NOT FCS AND NOT $OpTx$FX_DC$50); FDCPE_A11: FDCPE port map (A_I(11),A(11),CLK_EXT,'0',LAN_SM_RST,A_CE(11)); A(11) <= ((DQ_SWAP AND DQ(11).PIN) OR (NOT DQ_SWAP AND DQ(3).PIN)); A_CE(11) <= (LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1); A(11) <= A_I(11) when A_OE(11) = '1' else 'Z'; A_OE(11) <= (RW AND NOT FCS AND NOT $OpTx$FX_DC$50); FDCPE_A12: FDCPE port map (A_I(12),A(12),CLK_EXT,'0',LAN_SM_RST,A_CE(12)); A(12) <= ((DQ_SWAP AND DQ(12).PIN) OR (NOT DQ_SWAP AND DQ(4).PIN)); A_CE(12) <= (LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1); A(12) <= A_I(12) when A_OE(12) = '1' else 'Z'; A_OE(12) <= (RW AND NOT FCS AND NOT $OpTx$FX_DC$50); FDCPE_A13: FDCPE port map (A_I(13),A(13),CLK_EXT,'0',LAN_SM_RST,A_CE(13)); A(13) <= ((DQ_SWAP AND DQ(13).PIN) OR (NOT DQ_SWAP AND DQ(5).PIN)); A_CE(13) <= (LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1); A(13) <= A_I(13) when A_OE(13) = '1' else 'Z'; A_OE(13) <= (RW AND NOT FCS AND NOT $OpTx$FX_DC$50); FDCPE_A14: FDCPE port map (A_I(14),A(14),CLK_EXT,'0',LAN_SM_RST,A_CE(14)); A(14) <= ((DQ_SWAP AND DQ(14).PIN) OR (NOT DQ_SWAP AND DQ(6).PIN)); A_CE(14) <= (LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1); A(14) <= A_I(14) when A_OE(14) = '1' else 'Z'; A_OE(14) <= (RW AND NOT FCS AND NOT $OpTx$FX_DC$50); FDCPE_A15: FDCPE port map (A_I(15),A(15),CLK_EXT,'0',LAN_SM_RST,A_CE(15)); A(15) <= ((DQ_SWAP AND DQ(15).PIN) OR (NOT DQ_SWAP AND DQ(7).PIN)); A_CE(15) <= (LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1); A(15) <= A_I(15) when A_OE(15) = '1' else 'Z'; A_OE(15) <= (RW AND NOT FCS AND NOT $OpTx$FX_DC$50); FDCPE_A16: FDCPE port map (A_I(16),A(16),CLK_EXT,'0',LAN_SM_RST,A_CE(16)); A(16) <= ((DQ_SWAP AND DQ(0).PIN) OR (NOT DQ_SWAP AND DQ(8).PIN)); A_CE(16) <= (LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1); A(16) <= A_I(16) when A_OE(16) = '1' else 'Z'; A_OE(16) <= (RW AND NOT FCS AND NOT $OpTx$FX_DC$50); FDCPE_A17: FDCPE port map (A_I(17),A(17),CLK_EXT,'0',LAN_SM_RST,A_CE(17)); A(17) <= ((DQ_SWAP AND DQ(1).PIN) OR (NOT DQ_SWAP AND DQ(9).PIN)); A_CE(17) <= (LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1); A(17) <= A_I(17) when A_OE(17) = '1' else 'Z'; A_OE(17) <= (RW AND NOT FCS AND NOT $OpTx$FX_DC$50); FDCPE_A18: FDCPE port map (A_I(18),A(18),CLK_EXT,'0',LAN_SM_RST,A_CE(18)); A(18) <= ((DQ_SWAP AND DQ(2).PIN) OR (NOT DQ_SWAP AND DQ(10).PIN)); A_CE(18) <= (LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1); A(18) <= A_I(18) when A_OE(18) = '1' else 'Z'; A_OE(18) <= (RW AND NOT FCS AND NOT $OpTx$FX_DC$50); FDCPE_A19: FDCPE port map (A_I(19),A(19),CLK_EXT,'0',LAN_SM_RST,A_CE(19)); A(19) <= ((DQ_SWAP AND DQ(3).PIN) OR (NOT DQ_SWAP AND DQ(11).PIN)); A_CE(19) <= (LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1); A(19) <= A_I(19) when A_OE(19) = '1' else 'Z'; A_OE(19) <= (RW AND NOT FCS AND NOT $OpTx$FX_DC$50); FDCPE_A20: FDCPE port map (A_I(20),A(20),CLK_EXT,'0',LAN_SM_RST,A_CE(20)); A(20) <= ((DQ_SWAP AND DQ(4).PIN) OR (NOT DQ_SWAP AND DQ(12).PIN)); A_CE(20) <= (LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1); A(20) <= A_I(20) when A_OE(20) = '1' else 'Z'; A_OE(20) <= (RW AND NOT FCS AND NOT $OpTx$FX_DC$50); FDCPE_A21: FDCPE port map (A_I(21),A(21),CLK_EXT,'0',LAN_SM_RST,A_CE(21)); A(21) <= ((DQ_SWAP AND DQ(5).PIN) OR (NOT DQ_SWAP AND DQ(13).PIN)); A_CE(21) <= (LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1); A(21) <= A_I(21) when A_OE(21) = '1' else 'Z'; A_OE(21) <= (RW AND NOT FCS AND NOT $OpTx$FX_DC$50); FDCPE_A22: FDCPE port map (A_I(22),A(22),CLK_EXT,'0',LAN_SM_RST,A_CE(22)); A(22) <= ((DQ_SWAP AND DQ(6).PIN) OR (NOT DQ_SWAP AND DQ(14).PIN)); A_CE(22) <= (LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1); A(22) <= A_I(22) when A_OE(22) = '1' else 'Z'; A_OE(22) <= (RW AND NOT FCS AND NOT $OpTx$FX_DC$50); FDCPE_A23: FDCPE port map (A_I(23),A(23),CLK_EXT,'0',LAN_SM_RST,A_CE(23)); A(23) <= ((DQ_SWAP AND DQ(7).PIN) OR (NOT DQ_SWAP AND DQ(15).PIN)); A_CE(23) <= (LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1); A(23) <= A_I(23) when A_OE(23) = '1' else 'Z'; A_OE(23) <= (RW AND NOT FCS AND NOT $OpTx$FX_DC$50); FDCPE_AUTOCONFIG_Z2_ACCESS: FDCPE port map (AUTOCONFIG_Z2_ACCESS,AUTOCONFIG_Z2_ACCESS_D,NOT AS,NOT RESET,'0'); AUTOCONFIG_Z2_ACCESS_D <= ((NOT CFIN AND NOT A(20).PIN AND A(19).PIN AND NOT A(18).PIN AND NOT A(17).PIN AND NOT A(16).PIN AND NOT AUTO_CONFIG_Z2_DONE(0) AND A(23).PIN AND A(22).PIN AND A(21).PIN) OR (NOT CFIN AND NOT A(20).PIN AND A(19).PIN AND NOT A(18).PIN AND NOT A(17).PIN AND NOT A(16).PIN AND NOT AUTO_CONFIG_Z2_DONE(1) AND A(23).PIN AND A(22).PIN AND A(21).PIN)); FDCPE_AUTOCONFIG_Z3_ACCESS: FDCPE port map (AUTOCONFIG_Z3_ACCESS,AUTOCONFIG_Z3_ACCESS_D,NOT FCS,NOT RESET,'0'); AUTOCONFIG_Z3_ACCESS_D <= (Z3 AND D(9).PIN AND D(8).PIN AND D(14).PIN AND D(13).PIN AND D(12).PIN AND D(11).PIN AND D(10).PIN AND D(15).PIN AND NOT CFIN AND NOT A(20).PIN AND NOT A(19).PIN AND NOT A(18).PIN AND NOT A(17).PIN AND NOT A(16).PIN AND NOT AUTO_CONFIG_DONE AND NOT A(23).PIN AND NOT A(22).PIN AND NOT A(21).PIN); FDCPE_AUTO_CONFIG_DONE: FDCPE port map (AUTO_CONFIG_DONE,AUTO_CONFIG_DONE_CYCLE,CLK_EXT,NOT RESET,'0',FCS); FTCPE_AUTO_CONFIG_DONE_CYCLE: FTCPE port map (AUTO_CONFIG_DONE_CYCLE,AUTO_CONFIG_DONE_CYCLE_T,CLK_EXT,NOT RESET,'0',AUTO_CONFIG_DONE_CYCLE_CE); AUTO_CONFIG_DONE_CYCLE_T <= (NOT RW AND NOT AUTO_CONFIG_DONE_CYCLE AND NOT Z3_ADR(2) AND Z3_ADR_0 AND NOT Z3_ADR(6) AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5)); AUTO_CONFIG_DONE_CYCLE_CE <= (NOT UDS AND NOT FCS AND AUTOCONFIG_Z3_ACCESS); FDCPE_AUTO_CONFIG_Z2_DONE0: FDCPE port map (AUTO_CONFIG_Z2_DONE(0),AUTO_CONFIG_Z2_DONE_D(0),SHUT_UP_Z2(1)/SHUT_UP_Z2(1)_CLKF,NOT RESET,'0',AS); AUTO_CONFIG_Z2_DONE_D(0) <= (NOT AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE_CYCLE(0)); FDCPE_AUTO_CONFIG_Z2_DONE1: FDCPE port map (AUTO_CONFIG_Z2_DONE(1),AUTO_CONFIG_Z2_DONE_D(1),SHUT_UP_Z2(1)/SHUT_UP_Z2(1)_CLKF,NOT RESET,'0',AS); AUTO_CONFIG_Z2_DONE_D(1) <= (NOT AUTO_CONFIG_Z2_DONE(1) AND NOT AUTO_CONFIG_Z2_DONE_CYCLE(1)); FTCPE_AUTO_CONFIG_Z2_DONE_CYCLE0: FTCPE port map (AUTO_CONFIG_Z2_DONE_CYCLE(0),AUTO_CONFIG_Z2_DONE_CYCLE_T(0),SHUT_UP_Z2(1)/SHUT_UP_Z2(1)_CLKF,NOT RESET,'0'); AUTO_CONFIG_Z2_DONE_CYCLE_T(0) <= (NOT AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE_CYCLE(0) AND NOT RW AND NOT A(5) AND NOT A(4) AND NOT A(1) AND A(6) AND A(3) AND $OpTx$FX_DC$16); FTCPE_AUTO_CONFIG_Z2_DONE_CYCLE1: FTCPE port map (AUTO_CONFIG_Z2_DONE_CYCLE(1),AUTO_CONFIG_Z2_DONE_CYCLE_T(1),SHUT_UP_Z2(1)/SHUT_UP_Z2(1)_CLKF,NOT RESET,'0'); AUTO_CONFIG_Z2_DONE_CYCLE_T(1) <= ((AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE(1) AND NOT AUTO_CONFIG_Z2_DONE_CYCLE(1) AND NOT RW AND NOT A(5) AND NOT A(4) AND NOT A(1) AND A(6) AND A(3) AND $OpTx$FX_DC$16) OR (AUTO_CONFIG_Z2_DONE(0) AND NOT AUTO_CONFIG_Z2_DONE_CYCLE(1) AND NOT RW AND NOT A(5) AND NOT A(4) AND NOT A(1) AND A(2) AND A(6) AND A(3) AND $OpTx$FX_DC$16)); A_LAN(0) <= NOT ((RESET AND NOT Z3_A_LOW)); A_LAN(1) <= NOT ((RESET AND NOT Z3_ADR_0)); A_LAN(2) <= NOT ((RESET AND NOT Z3_ADR_1)); A_LAN(3) <= ((RESET AND Z3_ADR(2)) OR (NOT RESET AND LAN_A_INIT(3))); A_LAN(4) <= NOT ((RESET AND NOT Z3_ADR(3))); A_LAN(5) <= NOT ((RESET AND NOT Z3_ADR(4))); A_LAN(6) <= ((RESET AND Z3_ADR(5)) OR (NOT RESET AND LAN_A_INIT(6))); A_LAN(7) <= NOT ((RESET AND NOT Z3_ADR(6))); A_LAN(8) <= NOT ((RESET AND NOT Z3_ADR(7))); A_LAN(9) <= NOT ((RESET AND NOT Z3_ADR(8))); A_LAN(10) <= NOT ((RESET AND NOT Z3_ADR(9))); A_LAN(11) <= NOT ((RESET AND NOT Z3_ADR(10))); A_LAN(12) <= NOT ((RESET AND NOT Z3_ADR(11))); A_LAN(13) <= NOT ((RESET AND NOT Z3_ADR(12))); BUF_CONFIG_READY <= (NOT FCS AND LAN_ACCESS AND Z3_ADR(13)); BUF_D_Z2_OUT(2) <= ((NOT A(5) AND A(1) AND A(2) AND NOT A(6) AND NOT A(3) AND $OpTx$FX_DC$16) OR (NOT A(4) AND A(1) AND A(2) AND NOT A(6) AND NOT A(3) AND $OpTx$FX_DC$16) OR (NOT A(5) AND NOT A(4) AND A(1) AND NOT A(2) AND NOT A(3) AND $OpTx$FX_DC$16) OR (NOT A(5) AND NOT A(4) AND NOT A(2) AND A(6) AND NOT A(3) AND $OpTx$FX_DC$16) OR (NOT AUTO_CONFIG_Z2_DONE(0) AND NOT A(5) AND NOT A(4) AND A(2) AND NOT A(6) AND NOT A(3) AND $OpTx$FX_DC$16) OR (NOT A(5) AND A(4) AND NOT A(1) AND A(2) AND NOT A(6) AND A(3) AND $OpTx$FX_DC$16)); BUF_D_Z2_OUT(3) <= ((NOT $OpTx$FX_DC$16) OR (NOT A(4) AND A(3)) OR (A(3) AND BUF_D_Z2_OUT(2)) OR (AUTO_CONFIG_Z2_DONE(0) AND BUF_D_Z2_OUT(2) AND $OpTx$FX_DC$49) OR (A(1) AND NOT A(2) AND A(3)) OR (NOT A(5) AND NOT A(1) AND NOT A(6) AND NOT A(3)) OR (A(5) AND BUF_D_Z2_OUT(2)) OR (A(5) AND NOT $OpTx$FX_DC$49) OR (A(6) AND NOT BUF_D_Z2_OUT(2))); BUF_IDE_ACCESS <= ((SHUT_UP_Z2(1)) OR (NOT A(20).PIN AND IDE_BASEADR(4)) OR (IDE_BASEADR(5) AND NOT A(21).PIN) OR (NOT IDE_BASEADR(5) AND A(21).PIN) OR (NOT IDE_BASEADR(7) AND A(23).PIN) OR (CP_BASEADR(7).EXP) OR (A(20).PIN AND NOT IDE_BASEADR(4)) OR (A(19).PIN AND NOT IDE_BASEADR(3)) OR (NOT A(19).PIN AND IDE_BASEADR(3)) OR (A(18).PIN AND NOT IDE_BASEADR(2)) OR (NOT A(18).PIN AND IDE_BASEADR(2)) OR (A(17).PIN AND NOT IDE_BASEADR(1)) OR (NOT A(17).PIN AND IDE_BASEADR(1)) OR (A(16).PIN AND NOT IDE_BASEADR(0)) OR (NOT A(16).PIN AND IDE_BASEADR(0))); BUF_LAN_D_INIT(1) <= ((LAN_RST_SM_FSM_FFd3 AND NOT LAN_RST_SM_FSM_FFd1) OR (NOT LAN_RST_SM_FSM_FFd3 AND LAN_RST_SM_FSM_FFd2)); BUF_LAN_READY <= ((NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd1) OR (LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd2) OR (LAN_SM_FSM_FFd3 AND LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd1) OR (NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND $OpTx$FX_DC$12)); CFOUT <= NOT ((AUTO_CONFIG_Z2_DONE(0) AND AUTO_CONFIG_Z2_DONE(1) AND AUTO_CONFIG_DONE)); FDCPE_CONFIG_READY: FDCPE port map (CONFIG_READY,BUF_CONFIG_READY,CLK_EXT,NOT RESET,'0'); FDCPE_CP_ACCESS: FDCPE port map (CP_ACCESS,CP_ACCESS_D,NOT AS,NOT RESET,'0'); CP_ACCESS_D <= ((SHUT_UP_Z2(0)) OR (D_13_IOBUFE.EXP) OR (A(20).PIN AND NOT CP_BASEADR(4)) OR (NOT A(20).PIN AND CP_BASEADR(4)) OR (NOT A(19).PIN AND CP_BASEADR(3)) OR (CP_BASEADR(5) AND NOT A(21).PIN) OR (NOT CP_BASEADR(5) AND A(21).PIN) OR (CP_BASEADR(0).EXP) OR (A(19).PIN AND NOT CP_BASEADR(3)) OR (A(18).PIN AND NOT CP_BASEADR(2)) OR (NOT A(18).PIN AND CP_BASEADR(2)) OR (A(17).PIN AND NOT CP_BASEADR(1)) OR (NOT A(17).PIN AND CP_BASEADR(1)) OR (A(16).PIN AND NOT CP_BASEADR(0)) OR (NOT A(16).PIN AND CP_BASEADR(0))); FDCPE_CP_BASEADR0: FDCPE port map (CP_BASEADR(0),CP_BASEADR_D(0),SHUT_UP_Z2(1)/SHUT_UP_Z2(1)_CLKF,'0',NOT RESET); CP_BASEADR_D(0) <= ((D(8).PIN AND $OpTx$FX_DC$34) OR (CP_BASEADR(0) AND NOT $OpTx$FX_DC$34)); FDCPE_CP_BASEADR1: FDCPE port map (CP_BASEADR(1),CP_BASEADR_D(1),SHUT_UP_Z2(1)/SHUT_UP_Z2(1)_CLKF,'0',NOT RESET); CP_BASEADR_D(1) <= ((D(9).PIN AND $OpTx$FX_DC$34) OR (CP_BASEADR(1) AND NOT $OpTx$FX_DC$34)); FDCPE_CP_BASEADR2: FDCPE port map (CP_BASEADR(2),CP_BASEADR_D(2),SHUT_UP_Z2(1)/SHUT_UP_Z2(1)_CLKF,'0',NOT RESET); CP_BASEADR_D(2) <= ((D(10).PIN AND $OpTx$FX_DC$34) OR (CP_BASEADR(2) AND NOT $OpTx$FX_DC$34)); FDCPE_CP_BASEADR3: FDCPE port map (CP_BASEADR(3),CP_BASEADR_D(3),SHUT_UP_Z2(1)/SHUT_UP_Z2(1)_CLKF,'0',NOT RESET); CP_BASEADR_D(3) <= ((D(11).PIN AND $OpTx$FX_DC$34) OR (CP_BASEADR(3) AND NOT $OpTx$FX_DC$34)); FDCPE_CP_BASEADR4: FDCPE port map (CP_BASEADR(4),CP_BASEADR_D(4),SHUT_UP_Z2(1)/SHUT_UP_Z2(1)_CLKF,'0',NOT RESET); CP_BASEADR_D(4) <= ((D(12).PIN AND $OpTx$FX_DC$34) OR (CP_BASEADR(4) AND NOT $OpTx$FX_DC$34)); FDCPE_CP_BASEADR5: FDCPE port map (CP_BASEADR(5),CP_BASEADR_D(5),SHUT_UP_Z2(1)/SHUT_UP_Z2(1)_CLKF,'0',NOT RESET); CP_BASEADR_D(5) <= ((D(13).PIN AND $OpTx$FX_DC$34) OR (CP_BASEADR(5) AND NOT $OpTx$FX_DC$34)); FDCPE_CP_BASEADR6: FDCPE port map (CP_BASEADR(6),CP_BASEADR_D(6),SHUT_UP_Z2(1)/SHUT_UP_Z2(1)_CLKF,'0',NOT RESET); CP_BASEADR_D(6) <= ((D(14).PIN AND $OpTx$FX_DC$34) OR (CP_BASEADR(6) AND NOT $OpTx$FX_DC$34)); FDCPE_CP_BASEADR7: FDCPE port map (CP_BASEADR(7),CP_BASEADR_D(7),SHUT_UP_Z2(1)/SHUT_UP_Z2(1)_CLKF,'0',NOT RESET); CP_BASEADR_D(7) <= ((D(15).PIN AND $OpTx$FX_DC$34) OR (CP_BASEADR(7) AND NOT $OpTx$FX_DC$34)); CP_CS <= '1'; CP_RD <= '1'; CP_WE <= '1'; D_I(0) <= NOT ((NOT Z3_DATA(16) AND Z3_DATA(9)/Z3_DATA(9)_TRST)); D(0) <= D_I(0) when D_OE(0) = '1' else 'Z'; D_OE(0) <= D_9_IOBUFE/D_9_IOBUFE_TRST; D_I(1) <= NOT ((NOT Z3_DATA(17) AND Z3_DATA(9)/Z3_DATA(9)_TRST)); D(1) <= D_I(1) when D_OE(1) = '1' else 'Z'; D_OE(1) <= D_9_IOBUFE/D_9_IOBUFE_TRST; D_I(2) <= NOT ((NOT Z3_DATA(18) AND Z3_DATA(9)/Z3_DATA(9)_TRST)); D(2) <= D_I(2) when D_OE(2) = '1' else 'Z'; D_OE(2) <= D_9_IOBUFE/D_9_IOBUFE_TRST; D_I(3) <= NOT ((NOT Z3_DATA(19) AND Z3_DATA(9)/Z3_DATA(9)_TRST)); D(3) <= D_I(3) when D_OE(3) = '1' else 'Z'; D_OE(3) <= D_9_IOBUFE/D_9_IOBUFE_TRST; D_I(4) <= NOT ((NOT Z3_DATA(20) AND Z3_DATA(9)/Z3_DATA(9)_TRST)); D(4) <= D_I(4) when D_OE(4) = '1' else 'Z'; D_OE(4) <= D_9_IOBUFE/D_9_IOBUFE_TRST; D_I(5) <= NOT ((NOT Z3_DATA(21) AND Z3_DATA(9)/Z3_DATA(9)_TRST)); D(5) <= D_I(5) when D_OE(5) = '1' else 'Z'; D_OE(5) <= D_9_IOBUFE/D_9_IOBUFE_TRST; D_I(6) <= NOT ((NOT Z3_DATA(22) AND Z3_DATA(9)/Z3_DATA(9)_TRST)); D(6) <= D_I(6) when D_OE(6) = '1' else 'Z'; D_OE(6) <= D_9_IOBUFE/D_9_IOBUFE_TRST; D_I(7) <= NOT ((NOT Z3_DATA(23) AND Z3_DATA(9)/Z3_DATA(9)_TRST)); D(7) <= D_I(7) when D_OE(7) = '1' else 'Z'; D_OE(7) <= D_9_IOBUFE/D_9_IOBUFE_TRST; D_I(8) <= NOT (((NOT Z3_DATA(24) AND Z3_DATA(9)/Z3_DATA(9)_TRST) OR (NOT D_OUT(0) AND NOT Z3_DATA(9)/Z3_DATA(9)_TRST AND $OpTx$FX_DC$36))); D(8) <= D_I(8) when D_OE(8) = '1' else 'Z'; D_OE(8) <= D_9_IOBUFE/D_9_IOBUFE_TRST; D_I(9) <= NOT (((NOT Z3_DATA(25) AND Z3_DATA(9)/Z3_DATA(9)_TRST) OR (NOT D_OUT(1) AND NOT Z3_DATA(9)/Z3_DATA(9)_TRST AND $OpTx$FX_DC$36))); D(9) <= D_I(9) when D_OE(9) = '1' else 'Z'; D_OE(9) <= D_9_IOBUFE/D_9_IOBUFE_TRST; D_I(10) <= NOT (((NOT Z3_DATA(26) AND Z3_DATA(9)/Z3_DATA(9)_TRST) OR (NOT D_OUT(2) AND NOT Z3_DATA(9)/Z3_DATA(9)_TRST AND $OpTx$FX_DC$36))); D(10) <= D_I(10) when D_OE(10) = '1' else 'Z'; D_OE(10) <= D_9_IOBUFE/D_9_IOBUFE_TRST; D_I(11) <= NOT (((NOT Z3_DATA(27) AND Z3_DATA(9)/Z3_DATA(9)_TRST) OR (NOT D_OUT(3) AND NOT Z3_DATA(9)/Z3_DATA(9)_TRST AND $OpTx$FX_DC$36))); D(11) <= D_I(11) when D_OE(11) = '1' else 'Z'; D_OE(11) <= D_9_IOBUFE/D_9_IOBUFE_TRST; D_I(12) <= ((Z3_DATA(28) AND Z3_DATA(9)/Z3_DATA(9)_TRST) OR (D_OUT(4) AND $OpTx$FX_SC$66) OR (D_Z2_OUT(0) AND NOT Z3_DATA(9)/Z3_DATA(9)_TRST AND NOT $OpTx$FX_DC$36)); D(12) <= D_I(12) when D_OE(12) = '1' else 'Z'; D_OE(12) <= D_9_IOBUFE/D_9_IOBUFE_TRST; D_I(13) <= ((Z3_DATA(29) AND Z3_DATA(9)/Z3_DATA(9)_TRST) OR (D_Z2_OUT(1) AND NOT Z3_DATA(9)/Z3_DATA(9)_TRST AND NOT $OpTx$FX_DC$36) OR (D_OUT(5) AND $OpTx$FX_SC$66)); D(13) <= D_I(13) when D_OE(13) = '1' else 'Z'; D_OE(13) <= D_9_IOBUFE/D_9_IOBUFE_TRST; D_I(14) <= ((Z3_DATA(30) AND Z3_DATA(9)/Z3_DATA(9)_TRST) OR (D_OUT(6) AND $OpTx$FX_SC$66) OR (D_Z2_OUT(2) AND NOT Z3_DATA(9)/Z3_DATA(9)_TRST AND NOT $OpTx$FX_DC$36)); D(14) <= D_I(14) when D_OE(14) = '1' else 'Z'; D_OE(14) <= D_9_IOBUFE/D_9_IOBUFE_TRST; D_I(15) <= ((Z3_DATA(31) AND Z3_DATA(9)/Z3_DATA(9)_TRST) OR (D_OUT(7) AND $OpTx$FX_SC$66) OR (D_Z2_OUT(3) AND NOT Z3_DATA(9)/Z3_DATA(9)_TRST AND NOT $OpTx$FX_DC$36)); D(15) <= D_I(15) when D_OE(15) = '1' else 'Z'; D_OE(15) <= D_9_IOBUFE/D_9_IOBUFE_TRST; DQ_I(0) <= (RESET AND DQ_DATA(0)); DQ(0) <= DQ_I(0) when DQ_OE(0) = '1' else 'Z'; DQ_OE(0) <= DQ_5_IOBUFE/DQ_5_IOBUFE_TRST; DQ_I(1) <= ((RESET AND DQ_DATA(1)) OR (NOT RESET AND LAN_D_INIT(1))); DQ(1) <= DQ_I(1) when DQ_OE(1) = '1' else 'Z'; DQ_OE(1) <= DQ_5_IOBUFE/DQ_5_IOBUFE_TRST; DQ_I(2) <= (RESET AND DQ_DATA(2)); DQ(2) <= DQ_I(2) when DQ_OE(2) = '1' else 'Z'; DQ_OE(2) <= DQ_5_IOBUFE/DQ_5_IOBUFE_TRST; DQ_I(3) <= (RESET AND DQ_DATA(3)); DQ(3) <= DQ_I(3) when DQ_OE(3) = '1' else 'Z'; DQ_OE(3) <= DQ_5_IOBUFE/DQ_5_IOBUFE_TRST; DQ_I(4) <= ((RESET AND DQ_DATA(4)) OR (NOT RESET AND LAN_D_INIT(1))); DQ(4) <= DQ_I(4) when DQ_OE(4) = '1' else 'Z'; DQ_OE(4) <= DQ_5_IOBUFE/DQ_5_IOBUFE_TRST; DQ_I(5) <= (RESET AND DQ_DATA(5)); DQ(5) <= DQ_I(5) when DQ_OE(5) = '1' else 'Z'; DQ_OE(5) <= DQ_5_IOBUFE/DQ_5_IOBUFE_TRST; DQ_I(6) <= (RESET AND DQ_DATA(6)); DQ(6) <= DQ_I(6) when DQ_OE(6) = '1' else 'Z'; DQ_OE(6) <= DQ_5_IOBUFE/DQ_5_IOBUFE_TRST; DQ_I(7) <= (RESET AND DQ_DATA(7)); DQ(7) <= DQ_I(7) when DQ_OE(7) = '1' else 'Z'; DQ_OE(7) <= DQ_5_IOBUFE/DQ_5_IOBUFE_TRST; DQ_I(8) <= ((RESET AND DQ_DATA(8)) OR (NOT RESET AND LAN_D_INIT(8))); DQ(8) <= DQ_I(8) when DQ_OE(8) = '1' else 'Z'; DQ_OE(8) <= DQ_5_IOBUFE/DQ_5_IOBUFE_TRST; DQ_I(9) <= ((RESET AND DQ_DATA(9)) OR (NOT RESET AND LAN_D_INIT(1))); DQ(9) <= DQ_I(9) when DQ_OE(9) = '1' else 'Z'; DQ_OE(9) <= DQ_5_IOBUFE/DQ_5_IOBUFE_TRST; DQ_I(10) <= ((RESET AND DQ_DATA(10)) OR (NOT RESET AND LAN_D_INIT(8))); DQ(10) <= DQ_I(10) when DQ_OE(10) = '1' else 'Z'; DQ_OE(10) <= DQ_5_IOBUFE/DQ_5_IOBUFE_TRST; DQ_I(11) <= ((RESET AND DQ_DATA(11)) OR (NOT RESET AND LAN_D_INIT(8))); DQ(11) <= DQ_I(11) when DQ_OE(11) = '1' else 'Z'; DQ_OE(11) <= DQ_5_IOBUFE/DQ_5_IOBUFE_TRST; DQ_I(12) <= (RESET AND DQ_DATA(12)); DQ(12) <= DQ_I(12) when DQ_OE(12) = '1' else 'Z'; DQ_OE(12) <= DQ_5_IOBUFE/DQ_5_IOBUFE_TRST; DQ_I(13) <= (RESET AND DQ_DATA(13)); DQ(13) <= DQ_I(13) when DQ_OE(13) = '1' else 'Z'; DQ_OE(13) <= DQ_5_IOBUFE/DQ_5_IOBUFE_TRST; DQ_I(14) <= (RESET AND DQ_DATA(14)); DQ(14) <= DQ_I(14) when DQ_OE(14) = '1' else 'Z'; DQ_OE(14) <= DQ_5_IOBUFE/DQ_5_IOBUFE_TRST; DQ_I(15) <= (RESET AND DQ_DATA(15)); DQ(15) <= DQ_I(15) when DQ_OE(15) = '1' else 'Z'; DQ_OE(15) <= DQ_5_IOBUFE/DQ_5_IOBUFE_TRST; DQ_5_IOBUFE/DQ_5_IOBUFE_TRST <= ((NOT RESET) OR (NOT FCS AND NOT $OpTx$FX_DC$50 AND NOT Z3_DATA(9)/Z3_DATA(9)_TRST)); FDCPE_DQ_DATA0: FDCPE port map (DQ_DATA(0),DQ_DATA_D(0),CLK_EXT,'0',LAN_SM_RST); DQ_DATA_D(0) <= ((D(8).PIN AND DQ_SWAP AND NOT LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd4 AND NOT $OpTx$FX_DC$10) OR (DQ_DATA(0) AND NOT $OpTx$FX_DC$30) OR (A(16).PIN AND DQ_SWAP AND $OpTx$FX_SC$31) OR (NOT DQ_SWAP AND A(8).PIN AND $OpTx$FX_SC$31) OR (D(0).PIN AND NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd4 AND NOT $OpTx$FX_DC$10)); FDCPE_DQ_DATA1: FDCPE port map (DQ_DATA(1),DQ_DATA_D(1),CLK_EXT,'0',LAN_SM_RST); DQ_DATA_D(1) <= ((D(9).PIN AND DQ_SWAP AND NOT LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd4 AND NOT $OpTx$FX_DC$10) OR (D(1).PIN AND NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd4 AND NOT $OpTx$FX_DC$10) OR (DQ_DATA(1) AND NOT $OpTx$FX_DC$30) OR (A(17).PIN AND DQ_SWAP AND $OpTx$FX_SC$31) OR (NOT DQ_SWAP AND A(9).PIN AND $OpTx$FX_SC$31)); FDCPE_DQ_DATA2: FDCPE port map (DQ_DATA(2),DQ_DATA_D(2),CLK_EXT,'0',LAN_SM_RST); DQ_DATA_D(2) <= ((D(10).PIN AND DQ_SWAP AND NOT LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd4 AND NOT $OpTx$FX_DC$10) OR (DQ_DATA(2) AND NOT $OpTx$FX_DC$30) OR (A(18).PIN AND DQ_SWAP AND $OpTx$FX_SC$31) OR (NOT DQ_SWAP AND A(10).PIN AND $OpTx$FX_SC$31) OR (D(2).PIN AND NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd4 AND NOT $OpTx$FX_DC$10)); FDCPE_DQ_DATA3: FDCPE port map (DQ_DATA(3),DQ_DATA_D(3),CLK_EXT,'0',LAN_SM_RST); DQ_DATA_D(3) <= ((D(11).PIN AND DQ_SWAP AND NOT LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd4 AND NOT $OpTx$FX_DC$10) OR (DQ_DATA(3) AND NOT $OpTx$FX_DC$30) OR (A(19).PIN AND DQ_SWAP AND $OpTx$FX_SC$31) OR (NOT DQ_SWAP AND A(11).PIN AND $OpTx$FX_SC$31) OR (D(3).PIN AND NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd4 AND NOT $OpTx$FX_DC$10)); FDCPE_DQ_DATA4: FDCPE port map (DQ_DATA(4),DQ_DATA_D(4),CLK_EXT,'0',LAN_SM_RST); DQ_DATA_D(4) <= ((D(12).PIN AND DQ_SWAP AND NOT LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd4 AND NOT $OpTx$FX_DC$10) OR (D(4).PIN AND NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd4 AND NOT $OpTx$FX_DC$10) OR (DQ_DATA(4) AND NOT $OpTx$FX_DC$30) OR (A(20).PIN AND DQ_SWAP AND $OpTx$FX_SC$31) OR (NOT DQ_SWAP AND A(12).PIN AND $OpTx$FX_SC$31)); FDCPE_DQ_DATA5: FDCPE port map (DQ_DATA(5),DQ_DATA_D(5),CLK_EXT,'0',LAN_SM_RST); DQ_DATA_D(5) <= ((D(13).PIN AND DQ_SWAP AND NOT LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd4 AND NOT $OpTx$FX_DC$10) OR (DQ_DATA(5) AND NOT $OpTx$FX_DC$30) OR (A(21).PIN AND DQ_SWAP AND $OpTx$FX_SC$31) OR (NOT DQ_SWAP AND A(13).PIN AND $OpTx$FX_SC$31) OR (D(5).PIN AND NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd4 AND NOT $OpTx$FX_DC$10)); FDCPE_DQ_DATA6: FDCPE port map (DQ_DATA(6),DQ_DATA_D(6),CLK_EXT,'0',LAN_SM_RST); DQ_DATA_D(6) <= ((D(14).PIN AND DQ_SWAP AND NOT LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd4 AND NOT $OpTx$FX_DC$10) OR (D(6).PIN AND NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd4 AND NOT $OpTx$FX_DC$10) OR (DQ_DATA(6) AND NOT $OpTx$FX_DC$30) OR (A(22).PIN AND DQ_SWAP AND $OpTx$FX_SC$31) OR (NOT DQ_SWAP AND A(14).PIN AND $OpTx$FX_SC$31)); FDCPE_DQ_DATA7: FDCPE port map (DQ_DATA(7),DQ_DATA_D(7),CLK_EXT,'0',LAN_SM_RST); DQ_DATA_D(7) <= ((NOT DQ_SWAP AND A(15).PIN AND $OpTx$FX_SC$31) OR (D(15).PIN AND DQ_SWAP AND NOT LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd4 AND NOT $OpTx$FX_DC$10) OR (D(7).PIN AND NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd4 AND NOT $OpTx$FX_DC$10) OR (DQ_DATA(7) AND NOT $OpTx$FX_DC$30) OR (A(23).PIN AND DQ_SWAP AND $OpTx$FX_SC$31)); FDCPE_DQ_DATA8: FDCPE port map (DQ_DATA(8),DQ_DATA_D(8),CLK_EXT,'0',LAN_SM_RST); DQ_DATA_D(8) <= ((D(0).PIN AND DQ_SWAP AND NOT LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd4 AND NOT $OpTx$FX_DC$10) OR (DQ_DATA(8) AND NOT $OpTx$FX_DC$30) OR (A(16).PIN AND NOT DQ_SWAP AND $OpTx$FX_SC$31) OR (DQ_SWAP AND A(8).PIN AND $OpTx$FX_SC$31) OR (D(8).PIN AND NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd4 AND NOT $OpTx$FX_DC$10)); FDCPE_DQ_DATA9: FDCPE port map (DQ_DATA(9),DQ_DATA_D(9),CLK_EXT,'0',LAN_SM_RST); DQ_DATA_D(9) <= ((D(1).PIN AND DQ_SWAP AND NOT LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd4 AND NOT $OpTx$FX_DC$10) OR (DQ_DATA(9) AND NOT $OpTx$FX_DC$30) OR (A(17).PIN AND NOT DQ_SWAP AND $OpTx$FX_SC$31) OR (DQ_SWAP AND A(9).PIN AND $OpTx$FX_SC$31) OR (D(9).PIN AND NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd4 AND NOT $OpTx$FX_DC$10)); FDCPE_DQ_DATA10: FDCPE port map (DQ_DATA(10),DQ_DATA_D(10),CLK_EXT,'0',LAN_SM_RST); DQ_DATA_D(10) <= ((D(2).PIN AND DQ_SWAP AND NOT LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd4 AND NOT $OpTx$FX_DC$10) OR (DQ_DATA(10) AND NOT $OpTx$FX_DC$30) OR (A(18).PIN AND NOT DQ_SWAP AND $OpTx$FX_SC$31) OR (DQ_SWAP AND A(10).PIN AND $OpTx$FX_SC$31) OR (D(10).PIN AND NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd4 AND NOT $OpTx$FX_DC$10)); FDCPE_DQ_DATA11: FDCPE port map (DQ_DATA(11),DQ_DATA_D(11),CLK_EXT,'0',LAN_SM_RST); DQ_DATA_D(11) <= ((D(11).PIN AND NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd4 AND NOT $OpTx$FX_DC$10) OR (D(3).PIN AND DQ_SWAP AND NOT LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd4 AND NOT $OpTx$FX_DC$10) OR (DQ_DATA(11) AND NOT $OpTx$FX_DC$30) OR (A(19).PIN AND NOT DQ_SWAP AND $OpTx$FX_SC$31) OR (DQ_SWAP AND A(11).PIN AND $OpTx$FX_SC$31)); FDCPE_DQ_DATA12: FDCPE port map (DQ_DATA(12),DQ_DATA_D(12),CLK_EXT,'0',LAN_SM_RST); DQ_DATA_D(12) <= ((D(4).PIN AND DQ_SWAP AND NOT LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd4 AND NOT $OpTx$FX_DC$10) OR (DQ_DATA(12) AND NOT $OpTx$FX_DC$30) OR (A(20).PIN AND NOT DQ_SWAP AND $OpTx$FX_SC$31) OR (DQ_SWAP AND A(12).PIN AND $OpTx$FX_SC$31) OR (D(12).PIN AND NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd4 AND NOT $OpTx$FX_DC$10)); FDCPE_DQ_DATA13: FDCPE port map (DQ_DATA(13),DQ_DATA_D(13),CLK_EXT,'0',LAN_SM_RST); DQ_DATA_D(13) <= ((A(21).PIN AND NOT DQ_SWAP AND $OpTx$FX_SC$31) OR (D(13).PIN AND NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd4 AND NOT $OpTx$FX_DC$10) OR (D(5).PIN AND DQ_SWAP AND NOT LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd4 AND NOT $OpTx$FX_DC$10) OR (DQ_DATA(13) AND NOT $OpTx$FX_DC$30) OR (DQ_SWAP AND A(13).PIN AND $OpTx$FX_SC$31)); FDCPE_DQ_DATA14: FDCPE port map (DQ_DATA(14),DQ_DATA_D(14),CLK_EXT,'0',LAN_SM_RST); DQ_DATA_D(14) <= ((D(14).PIN AND NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd4 AND NOT $OpTx$FX_DC$10) OR (D(6).PIN AND DQ_SWAP AND NOT LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd4 AND NOT $OpTx$FX_DC$10) OR (DQ_DATA(14) AND NOT $OpTx$FX_DC$30) OR (A(22).PIN AND NOT DQ_SWAP AND $OpTx$FX_SC$31) OR (DQ_SWAP AND A(14).PIN AND $OpTx$FX_SC$31)); FDCPE_DQ_DATA15: FDCPE port map (DQ_DATA(15),DQ_DATA_D(15),CLK_EXT,'0',LAN_SM_RST); DQ_DATA_D(15) <= ((D(7).PIN AND DQ_SWAP AND NOT LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd4 AND NOT $OpTx$FX_DC$10) OR (DQ_DATA(15) AND NOT $OpTx$FX_DC$30) OR (A(23).PIN AND NOT DQ_SWAP AND $OpTx$FX_SC$31) OR (DQ_SWAP AND A(15).PIN AND $OpTx$FX_SC$31) OR (D(15).PIN AND NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd4 AND NOT $OpTx$FX_DC$10)); FDCPE_DQ_SWAP: FDCPE port map (DQ_SWAP,DQ_SWAP_D,NOT FCS,'0',NOT RESET); DQ_SWAP_D <= ((Z3 AND D(12).PIN AND LAN_BASEADR(12) AND NOT SHUT_UP AND A(13).PIN AND A(14).PIN AND NOT $OpTx$FX_DC$62 AND NOT $OpTx$FX_DC$61 AND NOT $OpTx$FX_DC$60 AND NOT $OpTx$FX_DC$59 AND NOT $OpTx$FX_DC$63 AND NOT $OpTx$INV$5 AND NOT $OpTx$INV$4) OR (Z3 AND NOT D(12).PIN AND NOT LAN_BASEADR(12) AND NOT SHUT_UP AND A(13).PIN AND A(14).PIN AND NOT $OpTx$FX_DC$62 AND NOT $OpTx$FX_DC$61 AND NOT $OpTx$FX_DC$60 AND NOT $OpTx$FX_DC$59 AND NOT $OpTx$FX_DC$63 AND NOT $OpTx$INV$5 AND NOT $OpTx$INV$4)); DTACK_I <= '0'; DTACK <= DTACK_I when DTACK_OE = '1' else 'Z'; DTACK_OE <= NOT ROM_B_0_OBUF$BUF9/ROM_B_0_OBUF$BUF9_TRST; D_9_IOBUFE/D_9_IOBUFE_TRST <= ((Z3_DATA(9)/Z3_DATA(9)_TRST) OR (NOT AS AND RW AND AUTOCONFIG_Z2_ACCESS) OR (RW AND NOT FCS AND AUTOCONFIG_Z3_ACCESS AND NOT $OpTx$FX_DC$10) OR (RW AND NOT FCS AND AUTOCONFIG_Z3_ACCESS AND NOT $OpTx$FX_DC$12)); FDCPE_D_OUT0: FDCPE port map (D_OUT(0),D_OUT_D(0),CLK_EXT,'0',NOT RESET); D_OUT_D(0) <= (NOT UDS AND NOT FCS AND NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND AUTOCONFIG_Z3_ACCESS AND NOT Z3_ADR(3) AND NOT Z3_ADR(4) AND NOT Z3_ADR(5)); FDCPE_D_OUT1: FDCPE port map (D_OUT(1),D_OUT_D(1),CLK_EXT,'0',NOT RESET); D_OUT_D(1) <= ((NOT UDS AND NOT FCS AND NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND AUTOCONFIG_Z3_ACCESS AND NOT Z3_ADR(3) AND NOT Z3_ADR(4) AND NOT Z3_ADR(5)) OR (NOT UDS AND NOT FCS AND NOT Z3_ADR(2) AND NOT Z3_ADR_0 AND AUTOCONFIG_Z3_ACCESS AND NOT Z3_ADR(3) AND NOT Z3_ADR(4) AND NOT Z3_ADR(5)) OR (NOT UDS AND NOT FCS AND NOT Z3_ADR_1 AND NOT Z3_ADR_0 AND AUTOCONFIG_Z3_ACCESS AND NOT Z3_ADR(3) AND NOT Z3_ADR(4) AND NOT Z3_ADR(5))); FDCPE_D_OUT2: FDCPE port map (D_OUT(2),D_OUT_D(2),CLK_EXT,'0',NOT RESET); D_OUT_D(2) <= ((NOT UDS AND NOT FCS AND Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND AUTOCONFIG_Z3_ACCESS AND NOT Z3_ADR(3) AND NOT Z3_ADR(4) AND NOT Z3_ADR(5)) OR (NOT UDS AND NOT FCS AND NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND NOT Z3_ADR_0 AND AUTOCONFIG_Z3_ACCESS AND NOT Z3_ADR(3) AND NOT Z3_ADR(4) AND NOT Z3_ADR(5))); FDCPE_D_OUT3: FDCPE port map (D_OUT(3),D_OUT_D(3),CLK_EXT,'0',NOT RESET); D_OUT_D(3) <= (NOT UDS AND NOT FCS AND NOT Z3_ADR_1 AND AUTOCONFIG_Z3_ACCESS AND NOT Z3_ADR(3) AND NOT Z3_ADR(4) AND NOT Z3_ADR(5)); FDCPE_D_OUT4: FDCPE port map (D_OUT(4),D_OUT_D(4),CLK_EXT,'0',NOT RESET); D_OUT_D(4) <= ((NOT UDS AND NOT FCS AND NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND AUTOCONFIG_Z3_ACCESS AND NOT Z3_ADR(3) AND NOT Z3_ADR(4) AND NOT Z3_ADR(5)) OR (NOT UDS AND NOT FCS AND NOT Z3_ADR(2) AND NOT Z3_ADR_0 AND NOT Z3_ADR(6) AND AUTOCONFIG_Z3_ACCESS AND NOT Z3_ADR(3) AND NOT Z3_ADR(4) AND NOT Z3_ADR(5)) OR (NOT UDS AND NOT FCS AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND AUTOCONFIG_Z3_ACCESS AND NOT Z3_ADR(3) AND NOT Z3_ADR(4) AND NOT Z3_ADR(5))); FDCPE_D_OUT5: FDCPE port map (D_OUT(5),D_OUT_D(5),CLK_EXT,'0',NOT RESET); D_OUT_D(5) <= ((NOT UDS AND NOT FCS AND NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND AUTOCONFIG_Z3_ACCESS AND NOT Z3_ADR(3) AND NOT Z3_ADR(4) AND NOT Z3_ADR(5)) OR (NOT UDS AND NOT FCS AND NOT Z3_ADR(2) AND NOT Z3_ADR_0 AND Z3_ADR(6) AND AUTOCONFIG_Z3_ACCESS AND NOT Z3_ADR(3) AND NOT Z3_ADR(4) AND NOT Z3_ADR(5)) OR (NOT UDS AND NOT FCS AND NOT Z3_ADR_1 AND NOT Z3_ADR_0 AND Z3_ADR(6) AND AUTOCONFIG_Z3_ACCESS AND NOT Z3_ADR(3) AND NOT Z3_ADR(4) AND NOT Z3_ADR(5))); FDCPE_D_OUT6: FDCPE port map (D_OUT(6),D_OUT_D(6),CLK_EXT,'0',NOT RESET); D_OUT_D(6) <= ((NOT UDS AND NOT FCS AND NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND NOT Z3_ADR_0 AND AUTOCONFIG_Z3_ACCESS AND NOT Z3_ADR(3) AND NOT Z3_ADR(4) AND NOT Z3_ADR(5)) OR (NOT UDS AND NOT FCS AND NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND NOT Z3_ADR(6) AND AUTOCONFIG_Z3_ACCESS AND NOT Z3_ADR(3) AND NOT Z3_ADR(4) AND NOT Z3_ADR(5)) OR (NOT UDS AND NOT FCS AND Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND Z3_ADR(6) AND AUTOCONFIG_Z3_ACCESS AND NOT Z3_ADR(3) AND NOT Z3_ADR(4) AND NOT Z3_ADR(5))); FDCPE_D_OUT7: FDCPE port map (D_OUT(7),D_OUT_D(7),CLK_EXT,'0',NOT RESET); D_OUT_D(7) <= (NOT UDS AND NOT FCS AND NOT Z3_ADR_1 AND Z3_ADR(6) AND AUTOCONFIG_Z3_ACCESS AND NOT Z3_ADR(3) AND NOT Z3_ADR(4) AND NOT Z3_ADR(5)); FDCPE_D_Z2_OUT0: FDCPE port map (D_Z2_OUT(0),D_Z2_OUT_D(0),SHUT_UP_Z2(1)/SHUT_UP_Z2(1)_CLKF,'0',NOT RESET); D_Z2_OUT_D(0) <= ((NOT $OpTx$FX_DC$16) OR (AUTO_CONFIG_Z2_DONE(1) AND A(5) AND A(3)) OR (AUTO_CONFIG_Z2_DONE(0) AND NOT A(5) AND NOT A(3) AND BUF_D_Z2_OUT(3)) OR (A(1) AND NOT A(6) AND BUF_D_Z2_OUT(2) AND NOT BUF_D_Z2_OUT(3)) OR (NOT AUTO_CONFIG_Z2_DONE(0) AND A(5) AND A(3)) OR (NOT A(5) AND NOT A(4) AND A(3)) OR (A(4) AND NOT A(2) AND NOT A(3)) OR (NOT A(1) AND A(3) AND BUF_D_Z2_OUT(3)) OR (A(5) AND NOT $OpTx$FX_DC$49) OR (A(6) AND BUF_D_Z2_OUT(3))); FDCPE_D_Z2_OUT1: FDCPE port map (D_Z2_OUT(1),D_Z2_OUT_D(1),SHUT_UP_Z2(1)/SHUT_UP_Z2(1)_CLKF,'0',NOT RESET); D_Z2_OUT_D(1) <= ((NOT $OpTx$FX_DC$16) OR (NOT A(4) AND A(3)) OR (A(4) AND NOT A(2) AND BUF_D_Z2_OUT(3)) OR (A(2) AND BUF_D_Z2_OUT(2) AND NOT BUF_D_Z2_OUT(3)) OR (AUTO_CONFIG_Z2_DONE(0) AND A(4) AND NOT A(3) AND NOT BUF_D_Z2_OUT(3)) OR (NOT AUTO_CONFIG_Z2_DONE(0) AND A(4) AND A(2) AND NOT A(3)) OR (NOT A(4) AND A(2) AND NOT BUF_D_Z2_OUT(2) AND BUF_D_Z2_OUT(3)) OR (A(5) AND BUF_D_Z2_OUT(3)) OR (A(6) AND BUF_D_Z2_OUT(3))); FDCPE_D_Z2_OUT2: FDCPE port map (D_Z2_OUT(2),BUF_D_Z2_OUT(2),SHUT_UP_Z2(1)/SHUT_UP_Z2(1)_CLKF,'0',NOT RESET); FDCPE_D_Z2_OUT3: FDCPE port map (D_Z2_OUT(3),BUF_D_Z2_OUT(3),SHUT_UP_Z2(1)/SHUT_UP_Z2(1)_CLKF,'0',NOT RESET); IDE_A(0) <= A(9).PIN; IDE_A(1) <= A(10).PIN; IDE_A(2) <= A(11).PIN; FDCPE_IDE_ACCESS: FDCPE port map (IDE_ACCESS,BUF_IDE_ACCESS,NOT AS,NOT RESET,'0'); FDCPE_IDE_BASEADR0: FDCPE port map (IDE_BASEADR(0),IDE_BASEADR_D(0),SHUT_UP_Z2(1)/SHUT_UP_Z2(1)_CLKF,'0',NOT RESET); IDE_BASEADR_D(0) <= ((IDE_BASEADR(0) AND NOT $OpTx$FX_DC$35) OR (D(8).PIN AND $OpTx$FX_DC$35)); FDCPE_IDE_BASEADR1: FDCPE port map (IDE_BASEADR(1),IDE_BASEADR_D(1),SHUT_UP_Z2(1)/SHUT_UP_Z2(1)_CLKF,'0',NOT RESET); IDE_BASEADR_D(1) <= ((D(9).PIN AND $OpTx$FX_DC$35) OR (IDE_BASEADR(1) AND NOT $OpTx$FX_DC$35)); FDCPE_IDE_BASEADR2: FDCPE port map (IDE_BASEADR(2),IDE_BASEADR_D(2),SHUT_UP_Z2(1)/SHUT_UP_Z2(1)_CLKF,'0',NOT RESET); IDE_BASEADR_D(2) <= ((D(10).PIN AND $OpTx$FX_DC$35) OR (IDE_BASEADR(2) AND NOT $OpTx$FX_DC$35)); FDCPE_IDE_BASEADR3: FDCPE port map (IDE_BASEADR(3),IDE_BASEADR_D(3),SHUT_UP_Z2(1)/SHUT_UP_Z2(1)_CLKF,'0',NOT RESET); IDE_BASEADR_D(3) <= ((D(11).PIN AND $OpTx$FX_DC$35) OR (IDE_BASEADR(3) AND NOT $OpTx$FX_DC$35)); FDCPE_IDE_BASEADR4: FDCPE port map (IDE_BASEADR(4),IDE_BASEADR_D(4),SHUT_UP_Z2(1)/SHUT_UP_Z2(1)_CLKF,'0',NOT RESET); IDE_BASEADR_D(4) <= ((D(12).PIN AND $OpTx$FX_DC$35) OR (IDE_BASEADR(4) AND NOT $OpTx$FX_DC$35)); FDCPE_IDE_BASEADR5: FDCPE port map (IDE_BASEADR(5),IDE_BASEADR_D(5),SHUT_UP_Z2(1)/SHUT_UP_Z2(1)_CLKF,'0',NOT RESET); IDE_BASEADR_D(5) <= ((D(13).PIN AND $OpTx$FX_DC$35) OR (IDE_BASEADR(5) AND NOT $OpTx$FX_DC$35)); FDCPE_IDE_BASEADR6: FDCPE port map (IDE_BASEADR(6),IDE_BASEADR_D(6),SHUT_UP_Z2(1)/SHUT_UP_Z2(1)_CLKF,'0',NOT RESET); IDE_BASEADR_D(6) <= ((D(14).PIN AND $OpTx$FX_DC$35) OR (IDE_BASEADR(6) AND NOT $OpTx$FX_DC$35)); FDCPE_IDE_BASEADR7: FDCPE port map (IDE_BASEADR(7),IDE_BASEADR_D(7),SHUT_UP_Z2(1)/SHUT_UP_Z2(1)_CLKF,'0',NOT RESET); IDE_BASEADR_D(7) <= ((D(15).PIN AND $OpTx$FX_DC$35) OR (IDE_BASEADR(7) AND NOT $OpTx$FX_DC$35)); IDE_CS(0) <= NOT A(12).PIN; IDE_CS(1) <= NOT A(13).PIN; FDCPE_IDE_ENABLE: FDCPE port map (IDE_ENABLE,IDE_ENABLE_D,NOT AS,NOT RESET,'0'); IDE_ENABLE_D <= ((NOT RW AND NOT BUF_IDE_ACCESS) OR (IDE_ENABLE AND BUF_IDE_ACCESS)); IDE_R <= NOT ((NOT AS AND RW AND IDE_ENABLE AND IDE_ACCESS)); IDE_W <= NOT ((NOT AS AND NOT RW AND IDE_ACCESS)); INT_OUT_I <= '0'; INT_OUT <= INT_OUT_I when INT_OUT_OE = '1' else 'Z'; INT_OUT_OE <= (LAN_INT_ENABLE AND NOT LAN_IRQ_OUT); FDCPE_LAN_ACCESS: FDCPE port map (LAN_ACCESS,LAN_ACCESS_D,NOT FCS,NOT RESET,'0'); LAN_ACCESS_D <= ((Z3 AND D(12).PIN AND LAN_BASEADR(12) AND NOT SHUT_UP AND NOT $OpTx$FX_DC$62 AND NOT $OpTx$FX_DC$61 AND NOT $OpTx$FX_DC$60 AND NOT $OpTx$FX_DC$59 AND NOT $OpTx$FX_DC$63 AND NOT $OpTx$INV$5 AND NOT $OpTx$INV$4) OR (Z3 AND NOT D(12).PIN AND NOT LAN_BASEADR(12) AND NOT SHUT_UP AND NOT $OpTx$FX_DC$62 AND NOT $OpTx$FX_DC$61 AND NOT $OpTx$FX_DC$60 AND NOT $OpTx$FX_DC$59 AND NOT $OpTx$FX_DC$63 AND NOT $OpTx$INV$5 AND NOT $OpTx$INV$4)); FDCPE_LAN_A_INIT3: FDCPE port map (LAN_A_INIT(3),'0',CLK_EXT,'0',RESET); FDCPE_LAN_A_INIT6: FDCPE port map (LAN_A_INIT(6),BUF_LAN_D_INIT(1),CLK_EXT,'0',RESET); FDCPE_LAN_BASEADR0: FDCPE port map (LAN_BASEADR(0),D(0).PIN,CLK_EXT,'0',NOT RESET,LAN_BASEADR_CE(0)); LAN_BASEADR_CE(0) <= (NOT UDS AND NOT RW AND NOT FCS AND NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND AUTOCONFIG_Z3_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5)); FDCPE_LAN_BASEADR1: FDCPE port map (LAN_BASEADR(1),D(1).PIN,CLK_EXT,'0',NOT RESET,LAN_BASEADR_CE(1)); LAN_BASEADR_CE(1) <= (NOT UDS AND NOT RW AND NOT FCS AND NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND AUTOCONFIG_Z3_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5)); FDCPE_LAN_BASEADR2: FDCPE port map (LAN_BASEADR(2),D(2).PIN,CLK_EXT,'0',NOT RESET,LAN_BASEADR_CE(2)); LAN_BASEADR_CE(2) <= (NOT UDS AND NOT RW AND NOT FCS AND NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND AUTOCONFIG_Z3_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5)); FDCPE_LAN_BASEADR3: FDCPE port map (LAN_BASEADR(3),D(3).PIN,CLK_EXT,'0',NOT RESET,LAN_BASEADR_CE(3)); LAN_BASEADR_CE(3) <= (NOT UDS AND NOT RW AND NOT FCS AND NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND AUTOCONFIG_Z3_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5)); FDCPE_LAN_BASEADR4: FDCPE port map (LAN_BASEADR(4),D(4).PIN,CLK_EXT,'0',NOT RESET,LAN_BASEADR_CE(4)); LAN_BASEADR_CE(4) <= (NOT UDS AND NOT RW AND NOT FCS AND NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND AUTOCONFIG_Z3_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5)); FDCPE_LAN_BASEADR5: FDCPE port map (LAN_BASEADR(5),D(5).PIN,CLK_EXT,'0',NOT RESET,LAN_BASEADR_CE(5)); LAN_BASEADR_CE(5) <= (NOT UDS AND NOT RW AND NOT FCS AND NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND AUTOCONFIG_Z3_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5)); FDCPE_LAN_BASEADR6: FDCPE port map (LAN_BASEADR(6),D(6).PIN,CLK_EXT,'0',NOT RESET,LAN_BASEADR_CE(6)); LAN_BASEADR_CE(6) <= (NOT UDS AND NOT RW AND NOT FCS AND NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND AUTOCONFIG_Z3_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5)); FDCPE_LAN_BASEADR7: FDCPE port map (LAN_BASEADR(7),D(7).PIN,CLK_EXT,'0',NOT RESET,LAN_BASEADR_CE(7)); LAN_BASEADR_CE(7) <= (NOT UDS AND NOT RW AND NOT FCS AND NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND AUTOCONFIG_Z3_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5)); FDCPE_LAN_BASEADR8: FDCPE port map (LAN_BASEADR(8),D(8).PIN,CLK_EXT,'0',NOT RESET,LAN_BASEADR_CE(8)); LAN_BASEADR_CE(8) <= (NOT UDS AND NOT RW AND NOT FCS AND NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND AUTOCONFIG_Z3_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5)); FDCPE_LAN_BASEADR9: FDCPE port map (LAN_BASEADR(9),D(9).PIN,CLK_EXT,'0',NOT RESET,LAN_BASEADR_CE(9)); LAN_BASEADR_CE(9) <= (NOT UDS AND NOT RW AND NOT FCS AND NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND AUTOCONFIG_Z3_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5)); FDCPE_LAN_BASEADR10: FDCPE port map (LAN_BASEADR(10),D(10).PIN,CLK_EXT,'0',NOT RESET,LAN_BASEADR_CE(10)); LAN_BASEADR_CE(10) <= (NOT UDS AND NOT RW AND NOT FCS AND NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND AUTOCONFIG_Z3_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5)); FDCPE_LAN_BASEADR11: FDCPE port map (LAN_BASEADR(11),D(11).PIN,CLK_EXT,'0',NOT RESET,LAN_BASEADR_CE(11)); LAN_BASEADR_CE(11) <= (NOT UDS AND NOT RW AND NOT FCS AND NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND AUTOCONFIG_Z3_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5)); FDCPE_LAN_BASEADR12: FDCPE port map (LAN_BASEADR(12),D(12).PIN,CLK_EXT,'0',NOT RESET,LAN_BASEADR_CE(12)); LAN_BASEADR_CE(12) <= (NOT UDS AND NOT RW AND NOT FCS AND NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND AUTOCONFIG_Z3_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5)); FDCPE_LAN_BASEADR13: FDCPE port map (LAN_BASEADR(13),D(13).PIN,CLK_EXT,'0',NOT RESET,LAN_BASEADR_CE(13)); LAN_BASEADR_CE(13) <= (NOT UDS AND NOT RW AND NOT FCS AND NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND AUTOCONFIG_Z3_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5)); FDCPE_LAN_BASEADR14: FDCPE port map (LAN_BASEADR(14),D(14).PIN,CLK_EXT,'0',NOT RESET,LAN_BASEADR_CE(14)); LAN_BASEADR_CE(14) <= (NOT UDS AND NOT RW AND NOT FCS AND NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND AUTOCONFIG_Z3_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5)); FDCPE_LAN_BASEADR15: FDCPE port map (LAN_BASEADR(15),D(15).PIN,CLK_EXT,'0',NOT RESET,LAN_BASEADR_CE(15)); LAN_BASEADR_CE(15) <= (NOT UDS AND NOT RW AND NOT FCS AND NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND AUTOCONFIG_Z3_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5)); LAN_CFG_I(1) <= '0'; LAN_CFG(1) <= LAN_CFG_I(1) when LAN_CFG_OE(1) = '1' else 'Z'; LAN_CFG_OE(1) <= '0'; LAN_CFG_I(2) <= '0'; LAN_CFG(2) <= LAN_CFG_I(2) when LAN_CFG_OE(2) = '1' else 'Z'; LAN_CFG_OE(2) <= '0'; LAN_CFG_I(3) <= '0'; LAN_CFG(3) <= LAN_CFG_I(3) when LAN_CFG_OE(3) = '1' else 'Z'; LAN_CFG_OE(3) <= '0'; LAN_CFG_I(4) <= '0'; LAN_CFG(4) <= LAN_CFG_I(4) when LAN_CFG_OE(4) = '1' else 'Z'; LAN_CFG_OE(4) <= '0'; LAN_CS <= ((RESET AND LAN_ACCESS) OR (NOT RESET AND LAN_CS_RST)); FDCPE_LAN_CS_RST: FDCPE port map (LAN_CS_RST,LAN_CS_RST_D,CLK_EXT,RESET,'0'); LAN_CS_RST_D <= ((NOT LAN_RST_SM_FSM_FFd3 AND LAN_RST_SM_FSM_FFd2 AND LAN_RST_SM_FSM_FFd1) OR (NOT LAN_RST_SM_FSM_FFd3 AND NOT LAN_RST_SM_FSM_FFd2 AND NOT LAN_RST_SM_FSM_FFd1)); FDCPE_LAN_D_INIT1: FDCPE port map (LAN_D_INIT(1),BUF_LAN_D_INIT(1),CLK_EXT,RESET,'0'); FDCPE_LAN_D_INIT8: FDCPE port map (LAN_D_INIT(8),BUF_LAN_D_INIT(1),CLK_EXT,RESET,'0'); FTCPE_LAN_INT_ENABLE: FTCPE port map (LAN_INT_ENABLE,LAN_INT_ENABLE_T,CLK_EXT,NOT RESET,'0'); LAN_INT_ENABLE_T <= ((D(15).PIN AND NOT UDS AND NOT RW AND NOT LAN_INT_ENABLE AND BUF_CONFIG_READY) OR (NOT D(15).PIN AND NOT UDS AND NOT RW AND LAN_INT_ENABLE AND BUF_CONFIG_READY) OR (UDS AND NOT LDS AND NOT RW AND LAN_INT_ENABLE AND NOT A(23).PIN AND BUF_CONFIG_READY) OR (UDS AND NOT LDS AND NOT RW AND NOT LAN_INT_ENABLE AND A(23).PIN AND BUF_CONFIG_READY)); FDCPE_LAN_IRQ_D0: FDCPE port map (LAN_IRQ_D0,LAN_INT,CLK_EXT,'0',NOT RESET); FDCPE_LAN_IRQ_OUT: FDCPE port map (LAN_IRQ_OUT,LAN_IRQ_OUT_D,CLK_EXT,'0',NOT RESET); LAN_IRQ_OUT_D <= ((LAN_INT) OR (LAN_IRQ_OUT AND NOT LAN_IRQ_D0)); LAN_RD <= (LAN_RD_S AND $OpTx$FX_DC$44); FDCPE_LAN_RD_S: FDCPE port map (LAN_RD_S,LAN_RD_S_D,CLK_EXT,LAN_SM_RST,'0'); LAN_RD_S_D <= ((RW AND NOT LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd4) OR (NOT LAN_SM_FSM_FFd3 AND LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1) OR (LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1)); FDCPE_LAN_READY: FDCPE port map (LAN_READY,BUF_LAN_READY,CLK_EXT,LAN_SM_RST,'0'); FDCPE_LAN_RST_SM_FSM_FFd1: FDCPE port map (LAN_RST_SM_FSM_FFd1,LAN_RST_SM_FSM_FFd1_D,CLK_EXT,RESET,'0'); LAN_RST_SM_FSM_FFd1_D <= ((NOT LAN_RST_SM_FSM_FFd3) OR (NOT LAN_RST_SM_FSM_FFd2 AND LAN_RST_SM_FSM_FFd1)); FDCPE_LAN_RST_SM_FSM_FFd2: FDCPE port map (LAN_RST_SM_FSM_FFd2,LAN_RST_SM_FSM_FFd2_D,CLK_EXT,RESET,'0'); LAN_RST_SM_FSM_FFd2_D <= ((NOT LAN_RST_SM_FSM_FFd3 AND NOT LAN_RST_SM_FSM_FFd2) OR (LAN_RST_SM_FSM_FFd3 AND LAN_RST_SM_FSM_FFd2 AND LAN_RST_SM_FSM_FFd1)); FTCPE_LAN_RST_SM_FSM_FFd3: FTCPE port map (LAN_RST_SM_FSM_FFd3,LAN_RST_SM_FSM_FFd3_T,CLK_EXT,RESET,'0'); LAN_RST_SM_FSM_FFd3_T <= ((LAN_RST_SM_FSM_FFd3 AND LAN_RST_SM_FSM_FFd2 AND NOT LAN_RST_SM_FSM_FFd1) OR (NOT LAN_RST_SM_FSM_FFd3 AND NOT LAN_RST_SM_FSM_FFd2 AND LAN_RST_SM_FSM_FFd1)); FDCPE_LAN_SM_FSM_FFd1: FDCPE port map (LAN_SM_FSM_FFd1,LAN_SM_FSM_FFd1_D,CLK_EXT,LAN_SM_RST,'0'); LAN_SM_FSM_FFd1_D <= ((LAN_SM_FSM_FFd1 AND NOT $OpTx$FX_DC$57) OR (NOT RW AND NOT LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd4) OR (NOT LAN_SM_FSM_FFd3 AND LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1) OR (LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd1 AND NOT BUF_LAN_READY)); FTCPE_LAN_SM_FSM_FFd2: FTCPE port map (LAN_SM_FSM_FFd2,LAN_SM_FSM_FFd2_T,CLK_EXT,LAN_SM_RST,'0'); LAN_SM_FSM_FFd2_T <= ((LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND NOT $OpTx$FX_DC$12) OR (NOT LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND NOT $OpTx$FX_DC$10) OR (NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd1 AND $OpTx$FX_DC$10 AND NOT $OpTx$FX_DC$12)); FDCPE_LAN_SM_FSM_FFd3: FDCPE port map (LAN_SM_FSM_FFd3,LAN_SM_FSM_FFd3_D,CLK_EXT,LAN_SM_RST,'0'); LAN_SM_FSM_FFd3_D <= ((NOT LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1 AND NOT $OpTx$FX_DC$10) OR (LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND NOT $OpTx$FX_DC$12) OR (NOT RW AND NOT LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1) OR (NOT RW AND NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd1 AND NOT $OpTx$FX_DC$12) OR (NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd1 AND NOT $OpTx$FX_DC$10 AND NOT $OpTx$FX_DC$12)); FDCPE_LAN_SM_FSM_FFd4: FDCPE port map (LAN_SM_FSM_FFd4,LAN_SM_FSM_FFd4_D,CLK_EXT,LAN_SM_RST,'0'); LAN_SM_FSM_FFd4_D <= ((NOT LAN_SM_FSM_FFd3 AND NOT $OpTx$FX_DC$57) OR (NOT LAN_SM_FSM_FFd4 AND NOT BUF_LAN_READY) OR (LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd1)); FDCPE_LAN_SM_RST: FDCPE port map (LAN_SM_RST,LAN_SM_RST_D,NOT CLK_EXT,'0','0'); LAN_SM_RST_D <= (BERR AND NOT $OpTx$FX_DC$50 AND NOT BUF_CONFIG_READY AND $OpTx$FX_DC$44); LAN_WRH <= ((LAN_WR_RST AND NOT $OpTx$FX_DC$44) OR (LAN_WRH_S AND $OpTx$FX_DC$44)); FDCPE_LAN_WRH_S: FDCPE port map (LAN_WRH_S,LAN_WRH_S_D,CLK_EXT,LAN_SM_RST,'0'); LAN_WRH_S_D <= ((NOT LDS AND LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd1) OR (NOT DS0 AND NOT LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd1)); LAN_WRL <= ((LAN_WR_RST AND NOT $OpTx$FX_DC$44) OR (LAN_WRL_S AND $OpTx$FX_DC$44)); FDCPE_LAN_WRL_S: FDCPE port map (LAN_WRL_S,LAN_WRL_S_D,CLK_EXT,LAN_SM_RST,'0'); LAN_WRL_S_D <= ((NOT UDS AND LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd1) OR (NOT DS1 AND NOT LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd1)); FDCPE_LAN_WR_RST: FDCPE port map (LAN_WR_RST,LAN_WR_RST_D,CLK_EXT,RESET,'0'); LAN_WR_RST_D <= ((LAN_RST_SM_FSM_FFd3 AND LAN_RST_SM_FSM_FFd2 AND NOT LAN_RST_SM_FSM_FFd1) OR (LAN_RST_SM_FSM_FFd3 AND NOT LAN_RST_SM_FSM_FFd2 AND LAN_RST_SM_FSM_FFd1)); MTACK_I <= '0'; MTACK <= MTACK_I when MTACK_OE = '1' else 'Z'; MTACK_OE <= '0'; OVR_I <= '0'; OVR <= OVR_I when OVR_OE = '1' else 'Z'; OVR_OE <= ROM_B_0_OBUF$BUF2/ROM_B_0_OBUF$BUF2_TRST; OWN_I <= '0'; OWN <= OWN_I when OWN_OE = '1' else 'Z'; OWN_OE <= '0'; ROM_B(0) <= '0'; ROM_B(1) <= '0'; ROM_B_0_OBUF$BUF2/ROM_B_0_OBUF$BUF2_TRST <= ((NOT FCS AND LAN_ACCESS) OR (NOT FCS AND AUTOCONFIG_Z3_ACCESS)); ROM_B_0_OBUF$BUF9/ROM_B_0_OBUF$BUF9_TRST <= ((FCS) OR (NOT AUTOCONFIG_Z3_ACCESS AND NOT CONFIG_READY AND NOT LAN_READY)); ROM_OE <= NOT ((NOT AS AND RW AND NOT IDE_ENABLE AND IDE_ACCESS)); FDCPE_SHUT_UP: FDCPE port map (SHUT_UP,'0',CLK_EXT,'0',NOT RESET,SHUT_UP_CE); SHUT_UP_CE <= (NOT UDS AND NOT RW AND NOT FCS AND NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND AUTOCONFIG_Z3_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5)); FDCPE_SHUT_UP_Z20: FDCPE port map (SHUT_UP_Z2(0),SHUT_UP_Z2_D(0),SHUT_UP_Z2(1)/SHUT_UP_Z2(1)_CLKF,'0',NOT RESET); SHUT_UP_Z2_D(0) <= (SHUT_UP_Z2(0) AND NOT $OpTx$FX_DC$34); SHUT_UP_Z2(1)/SHUT_UP_Z2(1)_CLKF <= C3 XOR SHUT_UP_Z2(1)/SHUT_UP_Z2(1)_CLKF <= C1; FDCPE_SHUT_UP_Z21: FDCPE port map (SHUT_UP_Z2(1),SHUT_UP_Z2_D(1),SHUT_UP_Z2(1)/SHUT_UP_Z2(1)_CLKF,'0',NOT RESET); SHUT_UP_Z2_D(1) <= (SHUT_UP_Z2(1) AND NOT $OpTx$FX_DC$35); SLAVE <= ((AS AND NOT ROM_B_0_OBUF$BUF2/ROM_B_0_OBUF$BUF2_TRST) OR (NOT AUTOCONFIG_Z2_ACCESS AND NOT IDE_ACCESS AND NOT CP_ACCESS AND NOT ROM_B_0_OBUF$BUF2/ROM_B_0_OBUF$BUF2_TRST)); FDCPE_Z3_ADR2: FDCPE port map (Z3_ADR(2),A(4),NOT FCS,'0',NOT RESET); FDCPE_Z3_ADR3: FDCPE port map (Z3_ADR(3),A(5),NOT FCS,'0',NOT RESET); FDCPE_Z3_ADR4: FDCPE port map (Z3_ADR(4),A(6),NOT FCS,'0',NOT RESET); FDCPE_Z3_ADR5: FDCPE port map (Z3_ADR(5),A(7),NOT FCS,'0',NOT RESET); FDCPE_Z3_ADR6: FDCPE port map (Z3_ADR(6),A(8).PIN,NOT FCS,'0',NOT RESET); FDCPE_Z3_ADR7: FDCPE port map (Z3_ADR(7),A(9).PIN,NOT FCS,'0',NOT RESET); FDCPE_Z3_ADR8: FDCPE port map (Z3_ADR(8),A(10).PIN,NOT FCS,'0',NOT RESET); FDCPE_Z3_ADR9: FDCPE port map (Z3_ADR(9),A(11).PIN,NOT FCS,'0',NOT RESET); FDCPE_Z3_ADR10: FDCPE port map (Z3_ADR(10),A(12).PIN,NOT FCS,'0',NOT RESET); FDCPE_Z3_ADR11: FDCPE port map (Z3_ADR(11),A(13).PIN,NOT FCS,'0',NOT RESET); FDCPE_Z3_ADR12: FDCPE port map (Z3_ADR(12),A(14).PIN,NOT FCS,'0',NOT RESET); FDCPE_Z3_ADR13: FDCPE port map (Z3_ADR(13),A(15).PIN,NOT FCS,'0',NOT RESET); FDCPE_Z3_ADR_0: FDCPE port map (Z3_ADR_0,A(2),NOT FCS,'0',NOT RESET); FDCPE_Z3_ADR_1: FDCPE port map (Z3_ADR_1,A(3),NOT FCS,'0',NOT RESET); FDCPE_Z3_A_LOW: FDCPE port map (Z3_A_LOW,Z3_A_LOW_D,CLK_EXT,LAN_SM_RST,'0'); Z3_A_LOW_D <= ((NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND NOT $OpTx$FX_DC$12) OR (LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2) OR (LAN_SM_FSM_FFd3 AND LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd1) OR (NOT LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd4 AND $OpTx$FX_DC$10) OR (NOT LAN_SM_FSM_FFd3 AND NOT LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd1)); Z3_DATA(9)/Z3_DATA(9)_TRST <= (RW AND NOT FCS AND NOT $OpTx$FX_DC$50); FDCPE_Z3_DATA16: FDCPE port map (Z3_DATA(16),Z3_DATA_D(16),CLK_EXT,'0',LAN_SM_RST,Z3_DATA_CE(16)); Z3_DATA_D(16) <= ((DQ_SWAP AND DQ(8).PIN) OR (NOT DQ_SWAP AND DQ(0).PIN)); Z3_DATA_CE(16) <= (NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd1); FDCPE_Z3_DATA17: FDCPE port map (Z3_DATA(17),Z3_DATA_D(17),CLK_EXT,'0',LAN_SM_RST,Z3_DATA_CE(17)); Z3_DATA_D(17) <= ((DQ_SWAP AND DQ(9).PIN) OR (NOT DQ_SWAP AND DQ(1).PIN)); Z3_DATA_CE(17) <= (NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd1); FDCPE_Z3_DATA18: FDCPE port map (Z3_DATA(18),Z3_DATA_D(18),CLK_EXT,'0',LAN_SM_RST,Z3_DATA_CE(18)); Z3_DATA_D(18) <= ((DQ_SWAP AND DQ(10).PIN) OR (NOT DQ_SWAP AND DQ(2).PIN)); Z3_DATA_CE(18) <= (NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd1); FDCPE_Z3_DATA19: FDCPE port map (Z3_DATA(19),Z3_DATA_D(19),CLK_EXT,'0',LAN_SM_RST,Z3_DATA_CE(19)); Z3_DATA_D(19) <= ((DQ_SWAP AND DQ(11).PIN) OR (NOT DQ_SWAP AND DQ(3).PIN)); Z3_DATA_CE(19) <= (NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd1); FDCPE_Z3_DATA20: FDCPE port map (Z3_DATA(20),Z3_DATA_D(20),CLK_EXT,'0',LAN_SM_RST,Z3_DATA_CE(20)); Z3_DATA_D(20) <= ((DQ_SWAP AND DQ(12).PIN) OR (NOT DQ_SWAP AND DQ(4).PIN)); Z3_DATA_CE(20) <= (NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd1); FDCPE_Z3_DATA21: FDCPE port map (Z3_DATA(21),Z3_DATA_D(21),CLK_EXT,'0',LAN_SM_RST,Z3_DATA_CE(21)); Z3_DATA_D(21) <= ((DQ_SWAP AND DQ(13).PIN) OR (NOT DQ_SWAP AND DQ(5).PIN)); Z3_DATA_CE(21) <= (NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd1); FDCPE_Z3_DATA22: FDCPE port map (Z3_DATA(22),Z3_DATA_D(22),CLK_EXT,'0',LAN_SM_RST,Z3_DATA_CE(22)); Z3_DATA_D(22) <= ((DQ_SWAP AND DQ(14).PIN) OR (NOT DQ_SWAP AND DQ(6).PIN)); Z3_DATA_CE(22) <= (NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd1); FDCPE_Z3_DATA23: FDCPE port map (Z3_DATA(23),Z3_DATA_D(23),CLK_EXT,'0',LAN_SM_RST,Z3_DATA_CE(23)); Z3_DATA_D(23) <= ((DQ_SWAP AND DQ(15).PIN) OR (NOT DQ_SWAP AND DQ(7).PIN)); Z3_DATA_CE(23) <= (NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd1); FDCPE_Z3_DATA24: FDCPE port map (Z3_DATA(24),Z3_DATA_D(24),CLK_EXT,'0',LAN_SM_RST,Z3_DATA_CE(24)); Z3_DATA_D(24) <= ((DQ_SWAP AND DQ(0).PIN) OR (NOT DQ_SWAP AND DQ(8).PIN)); Z3_DATA_CE(24) <= (NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd1); FDCPE_Z3_DATA25: FDCPE port map (Z3_DATA(25),Z3_DATA_D(25),CLK_EXT,'0',LAN_SM_RST,Z3_DATA_CE(25)); Z3_DATA_D(25) <= ((DQ_SWAP AND DQ(1).PIN) OR (NOT DQ_SWAP AND DQ(9).PIN)); Z3_DATA_CE(25) <= (NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd1); FDCPE_Z3_DATA26: FDCPE port map (Z3_DATA(26),Z3_DATA_D(26),CLK_EXT,'0',LAN_SM_RST,Z3_DATA_CE(26)); Z3_DATA_D(26) <= ((DQ_SWAP AND DQ(2).PIN) OR (NOT DQ_SWAP AND DQ(10).PIN)); Z3_DATA_CE(26) <= (NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd1); FDCPE_Z3_DATA27: FDCPE port map (Z3_DATA(27),Z3_DATA_D(27),CLK_EXT,'0',LAN_SM_RST,Z3_DATA_CE(27)); Z3_DATA_D(27) <= ((DQ_SWAP AND DQ(3).PIN) OR (NOT DQ_SWAP AND DQ(11).PIN)); Z3_DATA_CE(27) <= (NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd1); FDCPE_Z3_DATA28: FDCPE port map (Z3_DATA(28),Z3_DATA_D(28),CLK_EXT,'0',LAN_SM_RST,Z3_DATA_CE(28)); Z3_DATA_D(28) <= ((DQ_SWAP AND DQ(4).PIN) OR (NOT DQ_SWAP AND DQ(12).PIN)); Z3_DATA_CE(28) <= (NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd1); FDCPE_Z3_DATA29: FDCPE port map (Z3_DATA(29),Z3_DATA_D(29),CLK_EXT,'0',LAN_SM_RST,Z3_DATA_CE(29)); Z3_DATA_D(29) <= ((DQ_SWAP AND DQ(5).PIN) OR (NOT DQ_SWAP AND DQ(13).PIN)); Z3_DATA_CE(29) <= (NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd1); FDCPE_Z3_DATA30: FDCPE port map (Z3_DATA(30),Z3_DATA_D(30),CLK_EXT,'0',LAN_SM_RST,Z3_DATA_CE(30)); Z3_DATA_D(30) <= ((DQ_SWAP AND DQ(6).PIN) OR (NOT DQ_SWAP AND DQ(14).PIN)); Z3_DATA_CE(30) <= (NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd1); FDCPE_Z3_DATA31: FDCPE port map (Z3_DATA(31),Z3_DATA_D(31),CLK_EXT,'0',LAN_SM_RST,Z3_DATA_CE(31)); Z3_DATA_D(31) <= ((DQ_SWAP AND DQ(7).PIN) OR (NOT DQ_SWAP AND DQ(15).PIN)); Z3_DATA_CE(31) <= (NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd1); Register Legend: FDCPE (Q,D,C,CLR,PRE,CE); FTCPE (Q,D,C,CLR,PRE,CE); LDCP (Q,D,G,CLR,PRE); ****************************** Device Pin Out ***************************** Device : XC95288XL-10-TQ144 Pin Signal Pin Signal No. Name No. Name 1 VCC 73 VCC 2 D<0> 74 A<15> 3 A_LAN<1> 75 TIE 4 A_LAN<0> 76 LAN_WRL 5 A_LAN<3> 77 FCS 6 A_LAN<2> 78 DS1 7 A_LAN<5> 79 Z3 8 VCC 80 AS 9 A_LAN<4> 81 UDS 10 A_LAN<7> 82 LDS 11 A_LAN<6> 83 RW 12 LAN_CFG<1> 84 VCC 13 LAN_CFG<3> 85 DTACK 14 D<6> 86 A<23> 15 D<3> 87 A<22> 16 D<7> 88 A<21> 17 D<1> 89 GND 18 GND 90 GND 19 D<8> 91 A<20> 20 D<5> 92 A<19> 21 D<4> 93 DS0 22 IDE_CS<0> 94 A<18> 23 IDE_CS<1> 95 A<17> 24 IDE_A<0> 96 MTACK 25 IDE_A<2> 97 A<16> 26 IDE_A<1> 98 BERR 27 IDE_R 99 GND 28 IDE_W 100 OVR 29 GND 101 TIE 30 CLK_EXT 102 C3 31 TIE 103 C1 32 INT_OUT 104 CFIN 33 TIE 105 CFOUT 34 CP_CS 106 SLAVE 35 ROM_OE 107 OWN 36 GND 108 GND 37 VCC 109 VCC 38 TIE 110 LAN_CFG<4> 39 D<2> 111 LAN_INT 40 D<9> 112 DQ<15> 41 D<10> 113 DQ<13> 42 VCC 114 GND 43 D<11> 115 DQ<11> 44 D<12> 116 DQ<9> 45 D<13> 117 DQ<1> 46 D<14> 118 DQ<0> 47 GND 119 DQ<3> 48 D<15> 120 DQ<2> 49 A<5> 121 DQ<5> 50 A<4> 122 TDO 51 A<6> 123 GND 52 A<3> 124 DQ<4> 53 A<7> 125 DQ<7> 54 A<2> 126 DQ<6> 55 VCC 127 VCC 56 A<8> 128 DQ<8> 57 A<1> 129 DQ<10> 58 A<9> 130 DQ<12> 59 A<10> 131 DQ<14> 60 A<11> 132 LAN_WRH 61 A<12> 133 LAN_CS 62 GND 134 LAN_RD 63 TDI 135 LAN_CFG<2> 64 A<13> 136 A_LAN<12> 65 TMS 137 A_LAN<13> 66 A<14> 138 A_LAN<10> 67 TCK 139 A_LAN<11> 68 ROM_B<0> 140 A_LAN<8> 69 ROM_B<1> 141 VCC 70 CP_WE 142 A_LAN<9> 71 CP_RD 143 RESET 72 GND 144 GND Legend : NC = Not Connected, unbonded pin PGND = Unused I/O configured as additional Ground pin TIE = Unused I/O floating -- must tie to VCC, GND or other signal KPR = Unused I/O with weak keeper (leave unconnected) VCC = Dedicated Power Pin GND = Dedicated Ground Pin TDI = Test Data In, JTAG pin TDO = Test Data Out, JTAG pin TCK = Test Clock, JTAG pin TMS = Test Mode Select, JTAG pin PROHIBITED = User reserved pin **************************** Compiler Options **************************** Following is a list of all global compiler options used by the fitter run. Device(s) Specified : xc95288xl-10-TQ144 Optimization Method : DENSITY Multi-Level Logic Optimization : ON Ignore Timing Specifications : OFF Default Register Power Up Value : LOW Keep User Location Constraints : ON What-You-See-Is-What-You-Get : OFF Exhaustive Fitting : OFF Keep Unused Inputs : OFF Slew Rate : FAST Power Mode : STD Ground on Unused IOs : OFF Set I/O Pin Termination : FLOAT Global Clock Optimization : ON Global Set/Reset Optimization : ON Global Ouput Enable Optimization : ON Input Limit : 54 Pterm Limit : 35