Pin Freeze File: version P.20131013 95288XL144 XC95288XL-10-TQ144 AS S:PIN80 A<1> S:PIN57 A<2> S:PIN54 A<3> S:PIN52 A<4> S:PIN50 A<5> S:PIN49 A<6> S:PIN51 A<7> S:PIN53 BERR S:PIN98 C1 S:PIN103 C3 S:PIN102 CFIN S:PIN104 CLK_EXT S:PIN30 DS0 S:PIN93 DS1 S:PIN78 FCS S:PIN77 LAN_INT S:PIN111 LDS S:PIN82 RESET S:PIN143 RW S:PIN83 UDS S:PIN81 Z3 S:PIN79 A_LAN<0> S:PIN4 A_LAN<10> S:PIN138 A_LAN<11> S:PIN139 A_LAN<12> S:PIN136 A_LAN<13> S:PIN137 A_LAN<1> S:PIN3 A_LAN<2> S:PIN6 A_LAN<3> S:PIN5 A_LAN<4> S:PIN9 A_LAN<5> S:PIN7 A_LAN<6> S:PIN11 A_LAN<7> S:PIN10 A_LAN<8> S:PIN140 A_LAN<9> S:PIN142 CFOUT S:PIN105 CP_WE S:PIN70 CP_RD S:PIN71 CP_CS S:PIN34 DQ<0> S:PIN118 DQ<10> S:PIN129 DQ<11> S:PIN115 DQ<12> S:PIN130 DQ<13> S:PIN113 DQ<14> S:PIN131 DQ<15> S:PIN112 DQ<1> S:PIN117 DQ<2> S:PIN120 DQ<3> S:PIN119 DQ<4> S:PIN124 DQ<5> S:PIN121 DQ<6> S:PIN126 DQ<7> S:PIN125 DQ<8> S:PIN128 DQ<9> S:PIN116 D<0> S:PIN2 D<10> S:PIN41 D<11> S:PIN43 D<12> S:PIN44 D<13> S:PIN45 D<14> S:PIN46 D<15> S:PIN48 D<1> S:PIN17 D<2> S:PIN39 D<3> S:PIN15 D<4> S:PIN21 D<5> S:PIN20 D<6> S:PIN14 D<7> S:PIN16 D<8> S:PIN19 D<9> S:PIN40 IDE_A<0> S:PIN24 IDE_A<1> S:PIN26 IDE_A<2> S:PIN25 IDE_CS<0> S:PIN22 IDE_CS<1> S:PIN23 IDE_R S:PIN27 IDE_W S:PIN28 LAN_CS S:PIN133 LAN_RD S:PIN134 LAN_WRH S:PIN132 LAN_WRL S:PIN76 ROM_B<1> S:PIN69 ROM_B<0> S:PIN68 OWN S:PIN107 OVR S:PIN100 MTACK S:PIN96 LAN_CFG<4> S:PIN110 LAN_CFG<3> S:PIN13 LAN_CFG<2> S:PIN135 LAN_CFG<1> S:PIN12 INT_OUT S:PIN32 DTACK S:PIN85 ROM_OE S:PIN35 SLAVE S:PIN106 A<8> S:PIN56 A<9> S:PIN58 A<10> S:PIN59 A<11> S:PIN60 A<12> S:PIN61 A<13> S:PIN64 A<14> S:PIN66 A<15> S:PIN74 A<16> S:PIN97 A<17> S:PIN95 A<18> S:PIN94 A<19> S:PIN92 A<20> S:PIN91 A<21> S:PIN88 A<22> S:PIN87 A<23> S:PIN86 ;The remaining section of the .gyd file is for documentation purposes only. ;It shows where your internal equations were placed in the last successful fit. PARTITION FB1_1 $OpTx$FX_DC$16 DQ_5_IOBUFE/DQ_5_IOBUFE_TRST Z3_ADR<9> Z3_ADR<10> D_5_IOBUFE D_4_IOBUFE IDE_ACCESS IDE_CS_0_OBUF LAN_ACCESS IDE_CS_1_OBUF IDE_ENABLE IDE_A_0_OBUF$BUF0 D_9_IOBUFE/D_9_IOBUFE_TRST IDE_A_2_OBUF$BUF0 IDE_A_1_OBUF$BUF0 DQ_SWAP IDE_R_OBUF LAN_INT_ENABLE PARTITION FB2_1 SHUT_UP A_LAN_4_OBUF A_LAN_7_OBUF LAN_BASEADR<9> A_LAN_6_OBUF ROM_B_0_OBUF$BUF7 LAN_BASEADR<14> ROM_B_0_OBUF$BUF5 LAN_BASEADR<13> D_6_IOBUFE LAN_BASEADR<12> D_3_IOBUFE LAN_BASEADR<11> D_7_IOBUFE D_1_IOBUFE LAN_BASEADR<10> D_8_IOBUFE LAN_BASEADR<0> PARTITION FB3_2 IDE_W_OBUF PARTITION FB3_14 ROM_B_0_OBUF$BUF8 PARTITION FB4_1 D_Z2_OUT<0> D_0_IOBUFE $OpTx$FX_DC$34 D_Z2_OUT<3> A_LAN_1_OBUF A_LAN_0_OBUF D_Z2_OUT<2> A_LAN_3_OBUF AUTO_CONFIG_Z2_DONE_CYCLE<0> CP_BASEADR<6> AUTO_CONFIG_Z2_DONE_CYCLE<1> A_LAN_2_OBUF BUF_D_Z2_OUT<2> A_LAN_5_OBUF BUF_D_Z2_OUT<3> D_Z2_OUT<1> EXP22_ $OpTx$FX_DC$35 PARTITION FB5_1 LAN_BASEADR<8> CP_WE_OBUF$BUF1 LAN_BASEADR<7> LAN_BASEADR<6> ROM_OE_OBUF LAN_BASEADR<5> LAN_BASEADR<4> LAN_BASEADR<3> LAN_BASEADR<2> D_2_IOBUFE LAN_BASEADR<1> D_9_IOBUFE LAN_BASEADR<15> D_10_IOBUFE D_11_IOBUFE D_OUT<6> D_12_IOBUFE D_OUT<5> PARTITION FB6_2 ROM_B_0_OBUF$BUF6 A_LAN_12_OBUF $OpTx$FX_DC$57 A_LAN_13_OBUF A_LAN_10_OBUF $OpTx$FX_DC$37 A_LAN_11_OBUF $OpTx$FX_DC$12 A_LAN_8_OBUF $OpTx$FX_DC$10 SHUT_UP_Z2<1>/SHUT_UP_Z2<1>_CLKF LAN_READY A_LAN_9_OBUF $OpTx$FX_DC$63 $OpTx$FX_DC$62 $OpTx$FX_DC$61 $OpTx$FX_DC$60 PARTITION FB7_1 CP_ACCESS EXP23_ D_13_IOBUFE EXP24_ D_14_IOBUFE PARTITION FB7_10 SHUT_UP_Z2<0> CP_BASEADR<5> D_15_IOBUFE CP_BASEADR<4> CP_BASEADR<3> CP_BASEADR<2> CP_BASEADR<1> CP_BASEADR<0> EXP25_ PARTITION FB8_1 $OpTx$FX_DC$59 DQ_12_IOBUFE DQ_14_IOBUFE SHUT_UP_Z2<1> LAN_WRH_OBUF IDE_BASEADR<7> IDE_BASEADR<6> LAN_CS_OBUF IDE_BASEADR<5> LAN_RD_OBUF IDE_BASEADR<4> IDE_BASEADR<3> IDE_BASEADR<2> IDE_BASEADR<1> IDE_BASEADR<0> CP_BASEADR<7> EXP26_ BUF_IDE_ACCESS PARTITION FB9_1 DQ_DATA<13> DQ_DATA<14> DQ_DATA<15> DQ_DATA<5> DQ_DATA<6> DQ_DATA<7> $OpTx$INV$5 Z3_ADR<11> Z3_ADR<12> Z3_ADR<13> Z3_DATA<0> $OpTx$FX_DC$44 LAN_A_INIT<3> Z3_DATA<1> PARTITION FB9_17 Z3_DATA<2> EXP27_ PARTITION FB10_2 DQ_1_IOBUFE DQ_0_IOBUFE PARTITION FB10_5 DQ_3_IOBUFE DQ_2_IOBUFE PARTITION FB10_8 DQ_5_IOBUFE PARTITION FB10_10 DQ_4_IOBUFE DQ_7_IOBUFE DQ_6_IOBUFE AUTOCONFIG_Z3_ACCESS DQ_8_IOBUFE AUTO_CONFIG_Z2_DONE<1> AUTO_CONFIG_Z2_DONE<0> DQ_10_IOBUFE AUTOCONFIG_Z2_ACCESS PARTITION FB11_1 Z3_DATA<30> Z3_DATA<29> Z3_DATA<3> Z3_DATA<22> Z3_DATA<4> Z3_DATA<21> LAN_SM_FSM_FFd4 LAN_SM_FSM_FFd2 LAN_RD_S Z3_DATA<5> Z3_DATA<6> ROM_B_0_OBUF$BUF0 LAN_SM_FSM_FFd1 ROM_B_0_OBUF DQ_DATA<8> DQ_DATA<10> CP_WE_OBUF DQ_DATA<0> PARTITION FB12_1 LAN_SM_RST ROM_B_0_OBUF$BUF4 LAN_IRQ_D0 LAN_D_INIT<8> DQ_15_IOBUFE LAN_D_INIT<1> LAN_A_INIT<6> DQ_13_IOBUFE CONFIG_READY DQ_11_IOBUFE BUF_LAN_D_INIT<1> DQ_9_IOBUFE LAN_WR_RST LAN_RST_SM_FSM_FFd3 LAN_RST_SM_FSM_FFd2 LAN_RST_SM_FSM_FFd1 LAN_IRQ_OUT LAN_CS_RST PARTITION FB13_1 EXP28_ CP_WE_OBUF$BUF0 PARTITION FB13_4 D_OUT<7> D_OUT<3> D_OUT<0> Z3_ADR<8> Z3_DATA<7> Z3_ADR<7> D_OUT<2> AUTO_CONFIG_DONE_CYCLE AUTO_CONFIG_DONE D_OUT<4> LAN_WRL_OBUF D_OUT<1> DQ_DATA<9> DQ_DATA<2> DQ_DATA<1> PARTITION FB14_1 $OpTx$INV$4 BUF_CONFIG_READY ROM_B_0_OBUF$BUF2 $OpTx$FX_DC$49 ROM_B_0_OBUF$BUF9/ROM_B_0_OBUF$BUF9_TRST ROM_B_0_OBUF$BUF2/ROM_B_0_OBUF$BUF2_TRST $OpTx$FX_DC$50 Z3_ADR_1 Z3_ADR_0 Z3_ADR<6> CFOUT_OBUF Z3_ADR<5> Z3_ADR<4> SLAVE_OBUF ROM_B_0_OBUF$BUF1 Z3_ADR<3> Z3_ADR<2> EXP29_ PARTITION FB15_1 DQ_DATA<11> DQ_DATA<12> DQ_DATA<3> DQ_DATA<4> BUF_LAN_READY Z3_DATA<23> Z3_DATA<31> LAN_WRH_S LAN_WRL_S $OpTx$FX_DC$30 $OpTx$FX_DC$36 ROM_B_0_OBUF$BUF9 $OpTx$FX_SC$31 Z3_DATA<15> Z3_DATA<14> $OpTx$FX_SC$66 Z3_DATA<13> Z3_DATA<9>/Z3_DATA<9>_TRST PARTITION FB16_1 Z3_DATA<28> Z3_DATA<12> Z3_DATA<11> Z3_DATA<27> Z3_DATA<26> Z3_DATA<10> Z3_DATA<25> Z3_DATA<9> Z3_DATA<24> ROM_B_0_OBUF$BUF3 Z3_DATA<8> Z3_DATA<20> Z3_DATA<19> Z3_DATA<17> Z3_DATA<16> Z3_A_LOW LAN_SM_FSM_FFd3 Z3_DATA<18>