Release 14.7 - xst P.20131013 (nt64) Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. --> Parameter TMPDIR set to xst/projnav.tmp Total REAL time to Xst completion: 0.00 secs Total CPU time to Xst completion: 0.20 secs --> Parameter xsthdpdir set to xst Total REAL time to Xst completion: 0.00 secs Total CPU time to Xst completion: 0.20 secs --> Reading design: LAN_IDE_CP.prj TABLE OF CONTENTS 1) Synthesis Options Summary 2) HDL Compilation 3) Design Hierarchy Analysis 4) HDL Analysis 5) HDL Synthesis 5.1) HDL Synthesis Report 6) Advanced HDL Synthesis 6.1) Advanced HDL Synthesis Report 7) Low Level Synthesis 8) Partition Report 9) Final Report ========================================================================= * Synthesis Options Summary * ========================================================================= ---- Source Parameters Input File Name : "LAN_IDE_CP.prj" Input Format : mixed Ignore Synthesis Constraint File : NO ---- Target Parameters Output File Name : "LAN_IDE_CP" Output Format : NGC Target Device : XC9500XL CPLDs ---- Source Options Top Module Name : LAN_IDE_CP Automatic FSM Extraction : YES FSM Encoding Algorithm : Auto Safe Implementation : Yes Mux Extraction : No Resource Sharing : YES ---- Target Options Add IO Buffers : YES MACRO Preserve : YES XOR Preserve : YES Equivalent register Removal : YES ---- General Options Optimization Goal : Area Optimization Effort : 1 Keep Hierarchy : Yes Netlist Hierarchy : Rebuilt RTL Output : Yes Hierarchy Separator : / Bus Delimiter : <> Case Specifier : Maintain Verilog 2001 : YES ---- Other Options Clock Enable : YES wysiwyg : NO ========================================================================= ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.vhd" in Library work. Entity compiled. Entity (Architecture ) compiled. ========================================================================= * Design Hierarchy Analysis * ========================================================================= Analyzing hierarchy for entity in library (architecture ). ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity in library (Architecture ). Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Performing bidirectional port resolution... INFO:Xst:2561 - Always blocking tristate driving signal in unit is removed. Synthesizing Unit . Related source file is "C:/Users/Matze/Amiga/Hardwarehacks/Zorro-LAN-IDE/Logic/LAN_IDE/LAN_IDE_CP.vhd". WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. WARNING:Xst - You have specified state as a recovery-only state for the safe implementation of FSM . Due to a limitation in this version of the software, the logic required to implement this recovery-only state might not be properly generated. Please refer to the Xilinx Answers Database for more details. Found finite state machine for signal . ----------------------------------------------------------------------- | States | 8 | | Transitions | 8 | | Inputs | 0 | | Outputs | 8 | | Clock | CLK_EXT (rising_edge) | | Reset | RESET (positive) | | Reset type | synchronous | | Reset State | nop | | Power Up State | nop | | Recovery State | nop | | Encoding | automatic | | Implementation | automatic | ----------------------------------------------------------------------- Found 16-bit tristate buffer for signal . Found 16-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 4-bit tristate buffer for signal . Found 1-bit xor2 for signal created at line 146. Found 2-bit register for signal . Found 2-bit register for signal . Found 2-bit adder for signal created at line 413. Found 1-bit register for signal . Found 1-bit register for signal . Found 8-bit comparator equal for signal created at line 216. Found 8-bit comparator equal for signal created at line 222. Found 2-bit comparator less for signal created at line 215. Found 8-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 4-bit register for signal . Found 3-bit comparator less for signal created at line 335. Found 1-bit register for signal . Found 1-bit register for signal . Found 8-bit comparator equal for signal created at line 225. Found 8-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 2-bit comparator less for signal created at line 218. Found 8-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 3-bit register for signal . Summary: inferred 1 Finite State Machine(s). inferred 18 D-type flip-flop(s). inferred 1 Adder/Subtractor(s). inferred 6 Comparator(s). inferred 1 Xor(s). inferred 41 Tristate(s). Unit synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # Adders/Subtractors : 1 2-bit adder : 1 # Registers : 31 1-bit register : 25 2-bit register : 2 4-bit register : 1 8-bit register : 3 # Comparators : 6 2-bit comparator less : 2 3-bit comparator less : 1 8-bit comparator equal : 3 # Tristates : 11 1-bit tristate buffer : 9 16-bit tristate buffer : 2 # Xors : 1 1-bit xor2 : 1 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= Analyzing FSM for best encoding. Optimizing FSM on signal with gray encoding. ------------------------ State | Encoding ------------------------ nop | 000 wait0 | 001 clr | 011 clr_commit | 010 wait1 | 110 set | 111 set_commit | 101 done | 100 ------------------------ ========================================================================= Advanced HDL Synthesis Report Macro Statistics # FSMs : 1 # Adders/Subtractors : 1 2-bit adder : 1 # Registers : 18 Flip-Flops : 18 # Comparators : 3 8-bit comparator equal : 3 ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... implementation constraint: INIT=r : LAN_RST_SM_FSM_FFd1 implementation constraint: INIT=r : LAN_RST_SM_FSM_FFd2 implementation constraint: INIT=r : LAN_RST_SM_FSM_FFd3 ========================================================================= * Partition Report * ========================================================================= Partition Implementation Status ------------------------------- No Partitions were found in this design. ------------------------------- ========================================================================= * Final Report * ========================================================================= Final Results RTL Top Level Output File Name : LAN_IDE_CP.ngr Top Level Output File Name : LAN_IDE_CP Output Format : NGC Optimization Goal : Area Keep Hierarchy : Yes Target Technology : XC9500XL CPLDs Macro Preserve : YES XOR Preserve : YES Clock Enable : YES wysiwyg : NO Design Statistics # IOs : 116 Cell Usage : # BELS : 645 # AND2 : 220 # AND3 : 13 # AND4 : 3 # GND : 1 # INV : 207 # OR2 : 157 # OR3 : 17 # OR4 : 1 # XOR2 : 26 # FlipFlops/Latches : 60 # FD : 11 # FDC : 6 # FDCE : 6 # FDP : 4 # FDPE : 33 # IO Buffers : 111 # IBUF : 37 # IOBUFE : 32 # OBUF : 33 # OBUFE : 9 ========================================================================= Total REAL time to Xst completion: 9.00 secs Total CPU time to Xst completion: 8.59 secs --> Total memory usage is 4534760 kilobytes Number of errors : 0 ( 0 filtered) Number of warnings : 8 ( 0 filtered) Number of infos : 1 ( 0 filtered)