(pcb "kicad/ZORRO-PICO2W-CP-unrouted-gnd-plane.dsn" (parser (string_quote ") (space_in_quoted_tokens on) (host_cad "KiCad's Pcbnew") (host_version "9.0.9-9.0.9~ubuntu24.04.1") ) (resolution um 10) (unit um) (structure (layer F.Cu (type signal) (property (index 0) ) ) (layer In1.Cu (type power) (property (index 1) ) ) (layer In2.Cu (type signal) (property (index 2) ) ) (layer B.Cu (type signal) (property (index 3) ) ) (boundary (path pcb 0 213271 -144681 83730.9 -144681 83730.9 -65326.1 213271 -65326.1 213271 -144681) ) (plane GND (polygon In1.Cu 0 213652 -144808 83223.1 -144808 83223.1 -54384.1 213652 -54384.1 213652 -144808)) (plane +3V3 (polygon In2.Cu 0 186982 -113058 111163 -113058 111163 -84229.1 152438 -84229.1 152438 -76609.1 186982 -76609.1 186982 -113058)) (plane +5V (polygon In2.Cu 0 213652 -145443 83223.1 -145443 83223.1 -55019.1 213652 -55019.1 213652 -145443)) (keepout "" (polygon F.Cu 0 157000 -97500 171000 -97500 171000 -106500 157000 -106500 157000 -97500)) (keepout "" (polygon B.Cu 0 157000 -97500 171000 -97500 171000 -106500 157000 -106500 157000 -97500)) (keepout "" (polygon In1.Cu 0 157000 -97500 171000 -97500 171000 -106500 157000 -106500 157000 -97500)) (keepout "" (polygon In2.Cu 0 157000 -97500 171000 -97500 171000 -106500 157000 -106500 157000 -97500)) (via "Via[0-3]_600:300_um") (rule (width 200) (clearance 200) (clearance 50 (type smd_smd)) ) ) (placement (component "ZORRO-LAN-IDE-CP-V2F:ML10L" (place SV2 86525.200000 -85626.100000 front 90.000000) ) (component "ZORRO-LAN-IDE-CP-V2F:SJ" (place SJ1 98733.800000 -121811.700000 front 180.000000) ) (component "ZORRO-LAN-IDE-CP-V2F:C0603K" (place C17 98590.200000 -77371.100000 front -90.000000 (PN 100n)) (place C14 89065.200000 -76736.100000 front -90.000000 (PN 100n)) (place C16 85740.000000 -110515.800000 front -90.000000 (PN 100n)) (place C22 192316.200000 -83864.000000 front -90.000000 (PN 100n)) (place C29 126185.200000 -118977.100000 front 180.000000 (PN 100n)) (place C15 119989.700000 -78196.600000 front -90.000000 (PN 100n)) (place C11 110122.500000 -102867.900000 back 270.000000 (PN 100n)) (place C9 139252.100000 -103153.400000 back 270.000000 (PN 100n)) ) (component "ZORRO-LAN-IDE-CP-V2F:TSSOP20" (place IC3 93510.200000 -78641.100000 front 0.000000 (PN 74HCT245PW)) (place IC5 124625.200000 -78641.100000 front 0.000000 (PN 74HCT245PW)) (place IC4 103670.200000 -79276.100000 front 0.000000 (PN 74HCT245PW)) ) (component "ZORRO-LAN-IDE-CP-V2F:JP1" (place IDE_ACT0 144945.200000 -69116.100000 front 90.000000) ) (component "ZORRO-LAN-IDE-CP-V2F:R0603" (place R2 118580.000000 -81562.100000 front 180.000000 (PN 4.7k)) ) (component "ZORRO-LAN-IDE-CP-V2F:R0603::1" (place R1 95251.400000 -125350.800000 front 90.000000 (PN 4.7k)) (place R5 88906.900000 -125263.500000 front 90.000000 (PN 4.7k)) (place R7 149390.200000 -70386.100000 front 90.000000 (PN 330)) (place R9 186732.900000 -128206.400000 front 90.000000 (PN 4.7k)) ) (component RPi_Pico_SMD_TH (place PICO1 183500.000000 -102000.000000 front 90.000000 (PN "Raspberry Pi Pico 2 W")) ) (component "ZORRO-LAN-IDE-CP-V2F:PLCC-SR32" (place IC8 95902.900000 -103288.800000 front 180.000000 (PN AM29F010S)) ) (component "ZORRO-LAN-IDE-CP-V2F:R0603::2" (place R3 118560.900000 -75434.300000 front 0.000000 (PN 4.7k)) ) (component "SOT-23" (place U3 153000.000000 -113500.000000 front 0.000000 (PN SN74LVC1G04)) (place Q3 158000.000000 -116500.000000 front 0.000000 (PN "2N7002 !INT6 OPEN DRAIN")) ) (component "ZORRO-LAN-IDE-CP-V2F:JP1::1" (place IDE_OFF 86575.300000 -125267.300000 front 0.000000) (place AUTOBOOT_ON 92453.600000 -125370.800000 front 0.000000) ) (component "ZORRO-LAN-IDE-CP-V2F:C0805K" (place C2 114497.000000 -83057.500000 front 0.000000 (PN 10u)) ) (component "ZORRO-LAN-IDE-CP-V2F:LKONT_50_R" (place CN1 145961.200000 -139601.100000 front 0.000000 (PN ZORROII_EDGE_ROUND_CONTACTS)) ) (component "ZORRO-LAN-IDE-CP-V2F:C1206K" (place C20 193284.500000 -80101.600000 front 0.000000 (PN 10u)) (place C31 208111.800000 -127599.600000 front 0.000000 (PN 47u)) ) (component "ZORRO-LAN-IDE-CP-V2F:R0805" (place R11 167000.000000 -117000.000000 front 180.000000 (PN 1K)) ) (component "ZORRO-LAN-IDE-CP-V2F:R0603::3" (place R8 101425.900000 -125462.500000 front -90.000000 (PN 4.7k)) ) (component "ZORRO-LAN-IDE-CP-V2F:TQFP144" (place IC2 126158.200000 -102771.100000 front -135.000000 (PN "XC95288XL-TQ144")) ) (component "ZORRO-LAN-IDE-CP-V2F:ML40" (place IDE0 112560.200000 -69751.100000 front 0.000000) ) (component "ZORRO-LAN-IDE-CP-V2F:DPACK" (place IC7 185299.400000 -82451.100000 front 90.000000 (PN LD117ADT33TR)) ) (component "ZORRO-LAN-IDE-CP-V2F:JP1::2" (place JP1 98458.100000 -125603.700000 front 180.000000) ) (component "ZORRO-LAN-IDE-CP-V2F:CAY16" (place RN1 85250.900000 -98300.400000 front 90.000000) ) (component "ZORRO-LAN-IDE-CP-V2F:C1210K" (place C21 179806.700000 -77133.000000 front 90.000000 (PN 10u)) ) (component "ZORRO-LAN-IDE-CP-V2F:R2512" (place F1 112560.200000 -79911.100000 front 180.000000 (PN 500mA)) ) (component "TSSOP-24_4.4x7.8mm_P0.65mm" (place U2 150000.000000 -104500.000000 front 0.000000 (PN "SN74LVC8T245 CONTROL BUFFER")) ) (component "ZORRO-LAN-IDE-CP-V2F:C0805K::1" (place C23 113830.200000 -76101.100000 front 180.000000 (PN 10u)) ) (component "ZORRO-LAN-IDE-CP-V2F:C0603K::1" (place C10 119319.100000 -91612.500000 back 225.100000 (PN 100n)) ) (component "TSSOP-24_4.4x7.8mm_P0.65mm::1" (place U1 150000.000000 -94000.000000 back 180.000000 (PN "SN74LVC8T245 DATA BUFFER")) ) (component "ZORRO-LAN-IDE-CP-V2F:C0603K::2" (place C30 134626.400000 -92722.200000 back 317.600000 (PN 100n)) ) (component "ZORRO-LAN-IDE-CP-V2F:C0603K::3" (place C32 127895.400000 -89991.700000 back 180.000000 (PN 100n)) ) (component "ZORRO-LAN-IDE-CP-V2F:C0603K::4" (place C12 115729.500000 -106138.500000 back 137.900000 (PN 100n)) ) ) (library (image "ZORRO-LAN-IDE-CP-V2F:ML10L" (outline (path signal 152.4 10160 10922 10160 2032)) (outline (path signal 152.4 4826 10922 4826 9906)) (outline (path signal 152.4 2159 10922 10160 10922)) (outline (path signal 152.4 2159 10922 2159 4445)) (outline (path signal 152.4 -2159 10922 2159 10922)) (outline (path signal 152.4 -2159 10922 -10160 10922)) (outline (path signal 152.4 -2159 10922 -2159 4445)) (outline (path signal 254 -3810 10160 -5080 7620)) (outline (path signal 254 -6350 10160 -3810 10160)) (outline (path signal 508 0 10033 0 10287)) (outline (path signal 152.4 2794 9906 2794 10922)) (outline (path signal 152.4 2794 9906 4826 9906)) (outline (path signal 152.4 6731 8255 9525 8255)) (outline (path signal 152.4 6731 8255 6731 4445)) (outline (path signal 254 -5080 7620 -6350 10160)) (outline (path signal 152.4 4572 5969 4572 4445)) (outline (path signal 152.4 3048 5969 3048 4445)) (outline (path signal 152.4 9525 4445 9525 8255)) (outline (path signal 152.4 6731 4445 9525 4445)) (outline (path signal 152.4 4572 4445 4572 3683)) (outline (path signal 152.4 3048 4445 4572 4445)) (outline (path signal 152.4 3048 4445 3048 3683)) (outline (path signal 152.4 2159 4445 -2159 4445)) (outline (path signal 152.4 2159 4445 2159 3683)) (outline (path signal 152.4 -2159 4445 -2159 3429)) (outline (path signal 152.4 5969 3683 5969 10922)) (outline (path signal 152.4 5969 3683 5969 2032)) (outline (path signal 152.4 4572 3683 5969 3683)) (outline (path signal 152.4 2159 3683 3048 3683)) (outline (path signal 152.4 2159 3683 2159 3429)) (outline (path signal 152.4 2159 3429 -2159 3429)) (outline (path signal 152.4 2159 3429 2159 2159)) (outline (path signal 152.4 10160 2032 9017 2032)) (outline (path signal 152.4 9017 2032 8001 2032)) (outline (path signal 152.4 8001 2032 5969 2032)) (outline (path signal 152.4 8001 2032 8001 1397)) (outline (path signal 152.4 5969 2032 5715 2032)) (outline (path signal 152.4 3175 2032 4445 2032)) (outline (path signal 152.4 635 2032 1905 2032)) (outline (path signal 152.4 -1905 2032 -635 2032)) (outline (path signal 152.4 -4445 2032 -3175 2032)) (outline (path signal 152.4 -8001 2032 -5715 2032)) (outline (path signal 152.4 -9017 2032 -8001 2032)) (outline (path signal 152.4 -9017 2032 -9017 1397)) (outline (path signal 152.4 -10160 2032 -10160 10922)) (outline (path signal 152.4 -10160 2032 -9017 2032)) (outline (path signal 152.4 9017 1397 9017 2032)) (outline (path signal 152.4 9017 1397 8001 1397)) (outline (path signal 152.4 -8001 1397 -8001 2032)) (outline (path signal 152.4 -8001 1397 -9017 1397)) (outline (polygon signal 0 3124.2 5969 3109.65 5924.21 3071.55 5896.53 3024.45 5896.53 2986.35 5924.21 2971.8 5969 2990.12 6143.27 3044.27 6309.93 3131.88 6461.68 3249.14 6591.9 3390.9 6694.9 3550.98 6766.18 3722.38 6802.61 3897.62 6802.61 4069.02 6766.18 4229.1 6694.9 4370.86 6591.9 4488.12 6461.68 4575.73 6309.93 4629.88 6143.27 4648.2 5969 4633.65 5924.21 4595.55 5896.53 4548.45 5896.53 4510.35 5924.21 4495.8 5969 4495.8 6046.27 4461.41 6196.94 4394.36 6336.18 4298 6457 4177.18 6553.36 4037.94 6620.41 3887.27 6654.8 3732.73 6654.8 3582.06 6620.41 3442.82 6553.36 3322 6457 3225.64 6336.18 3158.59 6196.94 3124.2 6046.27 3124.2 5969)) (outline (path signal 152.4 2159 2159 2159 2032)) (outline (path signal 152.4 5715 2032 4445 2032)) (outline (path signal 152.4 2159 2032 3175 2032)) (outline (path signal 152.4 1905 2032 2159 2032)) (outline (path signal 152.4 -635 2032 635 2032)) (outline (path signal 152.4 -3175 2032 -1905 2032)) (outline (path signal 152.4 -5715 2032 -4445 2032)) (pin RoundRect[A]Pad_1214.400000x1214.400000_304.755000_um_0.292893_F 1 -5080 -1270) (pin RoundRect[A]Pad_1214.400000x1214.400000_304.755000_um_0.292893_F 2 -5080 1270) (pin RoundRect[A]Pad_1214.400000x1214.400000_304.755000_um_0.292893_F 3 -2540 -1270) (pin RoundRect[A]Pad_1214.400000x1214.400000_304.755000_um_0.292893_F 4 -2540 1270) (pin RoundRect[A]Pad_1214.400000x1214.400000_304.755000_um_0.292893_F 5 0 -1270) (pin RoundRect[A]Pad_1214.400000x1214.400000_304.755000_um_0.292893_F 6 0 1270) (pin RoundRect[A]Pad_1214.400000x1214.400000_304.755000_um_0.292893_F 7 2540 -1270) (pin RoundRect[A]Pad_1214.400000x1214.400000_304.755000_um_0.292893_F 8 2540 1270) (pin RoundRect[A]Pad_1214.400000x1214.400000_304.755000_um_0.292893_F 9 5080 -1270) (pin RoundRect[A]Pad_1214.400000x1214.400000_304.755000_um_0.292893_F 10 5080 1270) ) (image "ZORRO-LAN-IDE-CP-V2F:SJ" (outline (path signal 152.4 1651 -762 1651 762)) (outline (path signal 152.4 1397 -1016 -1397 -1016)) (outline (path signal 152.4 -1397 1016 1397 1016)) (outline (path signal 152.4 -1651 -762 -1651 762)) (outline (polygon signal 0 1574.8 -762 1589.35 -717.211 1627.45 -689.529 1674.55 -689.53 1712.65 -717.211 1727.2 -762 1715.95 -847.462 1682.96 -927.1 1630.49 -995.487 1562.1 -1047.96 1482.46 -1080.95 1397 -1092.2 1352.21 -1077.65 1324.53 -1039.55 1324.53 -992.453 1352.21 -954.353 1397 -939.8 1432.37 -939.8 1497.71 -912.731 1547.73 -862.715 1574.8 -797.366 1574.8 -762)) (outline (polygon signal 0 1397 939.8 1352.21 954.353 1324.53 992.453 1324.53 1039.55 1352.21 1077.65 1397 1092.2 1482.46 1080.95 1562.1 1047.96 1630.49 995.487 1682.96 927.1 1715.95 847.462 1727.2 762 1712.65 717.211 1674.55 689.53 1627.45 689.529 1589.35 717.211 1574.8 762 1574.8 797.366 1547.73 862.715 1497.71 912.731 1432.37 939.8 1397 939.8)) (outline (polygon signal 0 -1397 -939.8 -1352.21 -954.353 -1324.53 -992.453 -1324.53 -1039.55 -1352.21 -1077.65 -1397 -1092.2 -1482.46 -1080.95 -1562.1 -1047.96 -1630.49 -995.487 -1682.96 -927.1 -1715.95 -847.462 -1727.2 -762 -1712.65 -717.211 -1674.55 -689.53 -1627.45 -689.529 -1589.35 -717.211 -1574.8 -762 -1574.8 -797.366 -1547.73 -862.715 -1497.71 -912.731 -1432.37 -939.8 -1397 -939.8)) (outline (polygon signal 0 -1574.8 762 -1589.35 717.211 -1627.45 689.529 -1674.55 689.53 -1712.65 717.211 -1727.2 762 -1715.95 847.462 -1682.96 927.1 -1630.49 995.487 -1562.1 1047.96 -1482.46 1080.95 -1397 1092.2 -1352.21 1077.65 -1324.53 1039.55 -1324.53 992.453 -1352.21 954.353 -1397 939.8 -1432.37 939.8 -1497.71 912.731 -1547.73 862.715 -1574.8 797.366 -1574.8 762)) (outline (path signal 152.4 1016 0 1524 0)) (outline (path signal 152.4 -1016 0 -1524 0)) (outline (polygon signal 0 254 -508 112.699 -492.079 -21.516 -445.115 -141.916 -369.463 -242.463 -268.916 -318.115 -148.516 -365.079 -14.301 -381 127 -365.079 268.301 -318.115 402.516 -242.463 522.916 -141.916 623.463 -21.516 699.115 112.699 746.079 254 762 412.429 745.348 563.933 696.122 701.892 616.471 820.276 509.878 913.911 381 978.705 235.471 1011.83 79.651 1011.83 -79.651 978.705 -235.471 913.911 -381 820.276 -509.878 701.892 -616.471 563.933 -696.122 412.429 -745.348 254 -762 112.699 -746.079 -21.516 -699.115 -141.916 -623.463 -242.463 -522.916 -318.115 -402.516 -365.079 -268.301 -381 -127 -365.079 14.301 -318.115 148.516 -242.463 268.916 -141.916 369.463 -21.516 445.115 112.699 492.079 254 508)) (outline (polygon signal 0 -254 508 -112.699 492.079 21.516 445.115 141.916 369.463 242.463 268.916 318.115 148.516 365.079 14.301 381 -127 365.079 -268.301 318.115 -402.516 242.463 -522.916 141.916 -623.463 21.516 -699.115 -112.699 -746.079 -254 -762 -412.429 -745.348 -563.933 -696.122 -701.892 -616.471 -820.276 -509.878 -913.911 -381 -978.705 -235.471 -1011.83 -79.651 -1011.83 79.651 -978.705 235.471 -913.911 381 -820.276 509.878 -701.892 616.471 -563.933 696.122 -412.429 745.348 -254 762 -112.699 746.079 21.516 699.115 141.916 623.463 242.463 522.916 318.115 402.516 365.079 268.301 381 127 365.079 -14.301 318.115 -148.516 242.463 -268.916 141.916 -369.463 21.516 -445.115 -112.699 -492.079 -254 -508)) (pin Rect[T]Pad_1168.400000x1600.200000_um 1 -762 0) (pin Rect[T]Pad_1168.400000x1600.200000_um 2 762 0) ) (image "ZORRO-LAN-IDE-CP-V2F:C0603K" (outline (path signal 101.6 725 -350 -725 -350)) (outline (path signal 101.6 -725 350 725 350)) (pin Rect[T]Pad_1050.000000x1080.000000_um 1 -875 0) (pin Rect[T]Pad_1050.000000x1080.000000_um 2 875 0) ) (image "ZORRO-LAN-IDE-CP-V2F:TSSOP20" (outline (path signal 203.2 -3300 2250 -3300 -2250)) (outline (path signal 203.2 -3300 -2250 3300 -2250)) (outline (path signal 203.2 3300 2250 -3300 2250)) (outline (path signal 203.2 3300 -2250 3300 2250)) (outline (path signal 325 -2437.5 -1600 -2453.59 -1670.51 -2498.68 -1727.05 -2563.84 -1758.43 -2636.16 -1758.43 -2701.32 -1727.05 -2746.41 -1670.51 -2762.5 -1600 -2746.41 -1529.49 -2701.32 -1472.95 -2636.16 -1441.57 -2563.84 -1441.57 -2498.68 -1472.95 -2453.59 -1529.49 -2437.5 -1600)) (pin Rect[T]Pad_300.000000x1000.000000_um 1 -2925 -3000) (pin Rect[T]Pad_300.000000x1000.000000_um 2 -2275 -3000) (pin Rect[T]Pad_300.000000x1000.000000_um 3 -1625 -3000) (pin Rect[T]Pad_300.000000x1000.000000_um 4 -975 -3000) (pin Rect[T]Pad_300.000000x1000.000000_um 5 -325 -3000) (pin Rect[T]Pad_300.000000x1000.000000_um 6 325 -3000) (pin Rect[T]Pad_300.000000x1000.000000_um 7 975 -3000) (pin Rect[T]Pad_300.000000x1000.000000_um 8 1625 -3000) (pin Rect[T]Pad_300.000000x1000.000000_um 9 2275 -3000) (pin Rect[T]Pad_300.000000x1000.000000_um 10 2925 -3000) (pin Rect[T]Pad_300.000000x1000.000000_um 11 2925 3000) (pin Rect[T]Pad_300.000000x1000.000000_um 12 2275 3000) (pin Rect[T]Pad_300.000000x1000.000000_um 13 1625 3000) (pin Rect[T]Pad_300.000000x1000.000000_um 14 975 3000) (pin Rect[T]Pad_300.000000x1000.000000_um 15 325 3000) (pin Rect[T]Pad_300.000000x1000.000000_um 16 -325 3000) (pin Rect[T]Pad_300.000000x1000.000000_um 17 -975 3000) (pin Rect[T]Pad_300.000000x1000.000000_um 18 -1625 3000) (pin Rect[T]Pad_300.000000x1000.000000_um 19 -2275 3000) (pin Rect[T]Pad_300.000000x1000.000000_um 20 -2925 3000) ) (image "ZORRO-LAN-IDE-CP-V2F:JP1" (outline (path signal 152.4 1016 2540 -1016 2540)) (outline (path signal 152.4 1270 2286 1016 2540)) (outline (path signal 152.4 1270 2286 1270 254)) (outline (path signal 152.4 -1270 2286 -1016 2540)) (outline (path signal 152.4 -1270 2286 -1270 254)) (outline (path signal 152.4 1016 0 1270 254)) (outline (path signal 152.4 1016 0 1270 -254)) (outline (path signal 152.4 -1016 0 -1270 254)) (outline (path signal 152.4 -1016 0 -1270 -254)) (outline (path signal 152.4 1270 -254 1270 -2286)) (outline (path signal 152.4 -1270 -254 -1270 -2286)) (outline (path signal 152.4 1016 -2540 1270 -2286)) (outline (path signal 152.4 -1016 -2540 -1270 -2286)) (outline (path signal 152.4 -1016 -2540 1016 -2540)) (pin Oval[A]Pad_2428.800000x1214.400000_um 1 0 -1270) (pin Oval[A]Pad_2428.800000x1214.400000_um 2 0 1270) ) (image "ZORRO-LAN-IDE-CP-V2F:R0603" (outline (path signal 50.8 1473 -983 -1473 -983)) (outline (path signal 50.8 1473 983 1473 -983)) (outline (path signal 50.8 -1473 -983 -1473 983)) (outline (path signal 50.8 -1473 983 1473 983)) (outline (path signal 152.4 432 356 -432 356)) (outline (path signal 152.4 -432 -356 432 -356)) (pin Rect[T]Pad_1000.000000x1100.000000_um 1 -850 0) (pin Rect[T]Pad_1000.000000x1100.000000_um 2 850 0) ) (image "ZORRO-LAN-IDE-CP-V2F:R0603::1" (outline (path signal 50.8 1473 983 1473 -983)) (outline (path signal 50.8 -1473 983 1473 983)) (outline (path signal 50.8 1473 -983 -1473 -983)) (outline (path signal 50.8 -1473 -983 -1473 983)) (outline (path signal 152.4 432 356 -432 356)) (outline (path signal 152.4 -432 -356 432 -356)) (pin Rect[T]Pad_1000.000000x1100.000000_um 1 -850 0) (pin Rect[T]Pad_1000.000000x1100.000000_um 2 850 0) ) (image RPi_Pico_SMD_TH (outline (path signal 120 10500 25500 10500 25200)) (outline (path signal 120 -10500 25500 10500 25500)) (outline (path signal 120 -10500 25500 -10500 25200)) (outline (path signal 120 10500 23100 10500 22700)) (outline (path signal 120 -10500 23100 -10500 22700)) (outline (path signal 120 -7493 22833 -7493 25500)) (outline (path signal 120 -10500 22833 -7493 22833)) (outline (path signal 120 10500 20500 10500 20100)) (outline (path signal 120 -10500 20500 -10500 20100)) (outline (path signal 120 10500 18000 10500 17600)) (outline (path signal 120 -10500 18000 -10500 17600)) (outline (path signal 120 10500 15400 10500 15000)) (outline (path signal 120 -10500 15400 -10500 15000)) (outline (path signal 120 10500 12900 10500 12500)) (outline (path signal 120 -10500 12900 -10500 12500)) (outline (path signal 120 10500 10400 10500 10000)) (outline (path signal 120 -10500 10400 -10500 10000)) (outline (path signal 120 10500 7800 10500 7400)) (outline (path signal 120 -10500 7800 -10500 7400)) (outline (path signal 120 10500 5300 10500 4900)) (outline (path signal 120 -10500 5300 -10500 4900)) (outline (path signal 120 10500 2700 10500 2300)) (outline (path signal 120 -10500 2700 -10500 2300)) (outline (path signal 120 10500 200 10500 -200)) (outline (path signal 120 -10500 200 -10500 -200)) (outline (path signal 120 10500 -2300 10500 -2700)) (outline (path signal 120 -10500 -2300 -10500 -2700)) (outline (path signal 120 10500 -4900 10500 -5300)) (outline (path signal 120 -10500 -4900 -10500 -5300)) (outline (path signal 120 10500 -7400 10500 -7800)) (outline (path signal 120 -10500 -7400 -10500 -7800)) (outline (path signal 120 10500 -10000 10500 -10400)) (outline (path signal 120 -10500 -10000 -10500 -10400)) (outline (path signal 120 10500 -12500 10500 -12900)) (outline (path signal 120 -10500 -12500 -10500 -12900)) (outline (path signal 120 10500 -15100 10500 -15500)) (outline (path signal 120 -10500 -15100 -10500 -15500)) (outline (path signal 120 10500 -17600 10500 -18000)) (outline (path signal 120 -10500 -17600 -10500 -18000)) (outline (path signal 120 10500 -20100 10500 -20500)) (outline (path signal 120 -10500 -20100 -10500 -20500)) (outline (path signal 120 10500 -22700 10500 -23100)) (outline (path signal 120 -10500 -22700 -10500 -23100)) (outline (path signal 120 10500 -25500 3700 -25500)) (outline (path signal 120 1100 -25500 1500 -25500)) (outline (path signal 120 -1500 -25500 -1100 -25500)) (outline (path signal 120 -3700 -25500 -10500 -25500)) (outline (path signal 120 11000 26000 11000 -26000)) (outline (path signal 120 -11000 26000 11000 26000)) (outline (path signal 120 11000 -26000 -11000 -26000)) (outline (path signal 120 -11000 -26000 -11000 26000)) (outline (path signal 120 10500 25500 10500 -25500)) (outline (path signal 120 -10500 25500 10500 25500)) (outline (path signal 120 -10500 24200 -9200 25500)) (outline (path signal 120 10500 -25500 -10500 -25500)) (outline (path signal 120 -10500 -25500 -10500 25500)) (pin Oval[A]Pad_1800.000000x1800.000000_um @1 -2725 24000) (pin Oval[A]Pad_1500.000000x1500.000000_um @2 -2425 20970) (pin Oval[A]Pad_1500.000000x1500.000000_um @3 2425 20970) (pin Oval[A]Pad_1800.000000x1800.000000_um @4 2725 24000) (pin Oval[A]Pad_1700.000000x1700.000000_um 1 -8890 24130) (pin "Rect[T][-900.000000,0.000000]Pad_3500.000000x1700.000000_um" 1@1 -8890 24130) (pin Oval[A]Pad_1700.000000x1700.000000_um 2 -8890 21590) (pin "Rect[T][-900.000000,0.000000]Pad_3500.000000x1700.000000_um" 2@1 -8890 21590) (pin Rect[A]Pad_1700.000000x1700.000000_um 3 -8890 19050) (pin "Rect[T][-900.000000,0.000000]Pad_3500.000000x1700.000000_um" 3@1 -8890 19050) (pin Oval[A]Pad_1700.000000x1700.000000_um 4 -8890 16510) (pin "Rect[T][-900.000000,0.000000]Pad_3500.000000x1700.000000_um" 4@1 -8890 16510) (pin Oval[A]Pad_1700.000000x1700.000000_um 5 -8890 13970) (pin "Rect[T][-900.000000,0.000000]Pad_3500.000000x1700.000000_um" 5@1 -8890 13970) (pin Oval[A]Pad_1700.000000x1700.000000_um 6 -8890 11430) (pin "Rect[T][-900.000000,0.000000]Pad_3500.000000x1700.000000_um" 6@1 -8890 11430) (pin Oval[A]Pad_1700.000000x1700.000000_um 7 -8890 8890) (pin "Rect[T][-900.000000,0.000000]Pad_3500.000000x1700.000000_um" 7@1 -8890 8890) (pin Rect[A]Pad_1700.000000x1700.000000_um 8 -8890 6350) (pin "Rect[T][-900.000000,0.000000]Pad_3500.000000x1700.000000_um" 8@1 -8890 6350) (pin Oval[A]Pad_1700.000000x1700.000000_um 9 -8890 3810) (pin "Rect[T][-900.000000,0.000000]Pad_3500.000000x1700.000000_um" 9@1 -8890 3810) (pin Oval[A]Pad_1700.000000x1700.000000_um 10 -8890 1270) (pin "Rect[T][-900.000000,0.000000]Pad_3500.000000x1700.000000_um" 10@1 -8890 1270) (pin Oval[A]Pad_1700.000000x1700.000000_um 11 -8890 -1270) (pin "Rect[T][-900.000000,0.000000]Pad_3500.000000x1700.000000_um" 11@1 -8890 -1270) (pin Oval[A]Pad_1700.000000x1700.000000_um 12 -8890 -3810) (pin "Rect[T][-900.000000,0.000000]Pad_3500.000000x1700.000000_um" 12@1 -8890 -3810) (pin Rect[A]Pad_1700.000000x1700.000000_um 13 -8890 -6350) (pin "Rect[T][-900.000000,0.000000]Pad_3500.000000x1700.000000_um" 13@1 -8890 -6350) (pin Oval[A]Pad_1700.000000x1700.000000_um 14 -8890 -8890) (pin "Rect[T][-900.000000,0.000000]Pad_3500.000000x1700.000000_um" 14@1 -8890 -8890) (pin Oval[A]Pad_1700.000000x1700.000000_um 15 -8890 -11430) (pin "Rect[T][-900.000000,0.000000]Pad_3500.000000x1700.000000_um" 15@1 -8890 -11430) (pin Oval[A]Pad_1700.000000x1700.000000_um 16 -8890 -13970) (pin "Rect[T][-900.000000,0.000000]Pad_3500.000000x1700.000000_um" 16@1 -8890 -13970) (pin Oval[A]Pad_1700.000000x1700.000000_um 17 -8890 -16510) (pin "Rect[T][-900.000000,0.000000]Pad_3500.000000x1700.000000_um" 17@1 -8890 -16510) (pin Rect[A]Pad_1700.000000x1700.000000_um 18 -8890 -19050) (pin "Rect[T][-900.000000,0.000000]Pad_3500.000000x1700.000000_um" 18@1 -8890 -19050) (pin Oval[A]Pad_1700.000000x1700.000000_um 19 -8890 -21590) (pin "Rect[T][-900.000000,0.000000]Pad_3500.000000x1700.000000_um" 19@1 -8890 -21590) (pin Oval[A]Pad_1700.000000x1700.000000_um 20 -8890 -24130) (pin "Rect[T][-900.000000,0.000000]Pad_3500.000000x1700.000000_um" 20@1 -8890 -24130) (pin Oval[A]Pad_1700.000000x1700.000000_um 21 8890 -24130) (pin Rect[T][900.000000,0.000000]Pad_3500.000000x1700.000000_um 21@1 8890 -24130) (pin Oval[A]Pad_1700.000000x1700.000000_um 22 8890 -21590) (pin Rect[T][900.000000,0.000000]Pad_3500.000000x1700.000000_um 22@1 8890 -21590) (pin Rect[A]Pad_1700.000000x1700.000000_um 23 8890 -19050) (pin Rect[T][900.000000,0.000000]Pad_3500.000000x1700.000000_um 23@1 8890 -19050) (pin Oval[A]Pad_1700.000000x1700.000000_um 24 8890 -16510) (pin Rect[T][900.000000,0.000000]Pad_3500.000000x1700.000000_um 24@1 8890 -16510) (pin Oval[A]Pad_1700.000000x1700.000000_um 25 8890 -13970) (pin Rect[T][900.000000,0.000000]Pad_3500.000000x1700.000000_um 25@1 8890 -13970) (pin Oval[A]Pad_1700.000000x1700.000000_um 26 8890 -11430) (pin Rect[T][900.000000,0.000000]Pad_3500.000000x1700.000000_um 26@1 8890 -11430) (pin Oval[A]Pad_1700.000000x1700.000000_um 27 8890 -8890) (pin Rect[T][900.000000,0.000000]Pad_3500.000000x1700.000000_um 27@1 8890 -8890) (pin Rect[A]Pad_1700.000000x1700.000000_um 28 8890 -6350) (pin Rect[T][900.000000,0.000000]Pad_3500.000000x1700.000000_um 28@1 8890 -6350) (pin Oval[A]Pad_1700.000000x1700.000000_um 29 8890 -3810) (pin Rect[T][900.000000,0.000000]Pad_3500.000000x1700.000000_um 29@1 8890 -3810) (pin Oval[A]Pad_1700.000000x1700.000000_um 30 8890 -1270) (pin Rect[T][900.000000,0.000000]Pad_3500.000000x1700.000000_um 30@1 8890 -1270) (pin Oval[A]Pad_1700.000000x1700.000000_um 31 8890 1270) (pin Rect[T][900.000000,0.000000]Pad_3500.000000x1700.000000_um 31@1 8890 1270) (pin Oval[A]Pad_1700.000000x1700.000000_um 32 8890 3810) (pin Rect[T][900.000000,0.000000]Pad_3500.000000x1700.000000_um 32@1 8890 3810) (pin Rect[A]Pad_1700.000000x1700.000000_um 33 8890 6350) (pin Rect[T][900.000000,0.000000]Pad_3500.000000x1700.000000_um 33@1 8890 6350) (pin Oval[A]Pad_1700.000000x1700.000000_um 34 8890 8890) (pin Rect[T][900.000000,0.000000]Pad_3500.000000x1700.000000_um 34@1 8890 8890) (pin Oval[A]Pad_1700.000000x1700.000000_um 35 8890 11430) (pin Rect[T][900.000000,0.000000]Pad_3500.000000x1700.000000_um 35@1 8890 11430) (pin Oval[A]Pad_1700.000000x1700.000000_um 36 8890 13970) (pin Rect[T][900.000000,0.000000]Pad_3500.000000x1700.000000_um 36@1 8890 13970) (pin Oval[A]Pad_1700.000000x1700.000000_um 37 8890 16510) (pin Rect[T][900.000000,0.000000]Pad_3500.000000x1700.000000_um 37@1 8890 16510) (pin Rect[A]Pad_1700.000000x1700.000000_um 38 8890 19050) (pin Rect[T][900.000000,0.000000]Pad_3500.000000x1700.000000_um 38@1 8890 19050) (pin Oval[A]Pad_1700.000000x1700.000000_um 39 8890 21590) (pin Rect[T][900.000000,0.000000]Pad_3500.000000x1700.000000_um 39@1 8890 21590) (pin Oval[A]Pad_1700.000000x1700.000000_um 40 8890 24130) (pin Rect[T][900.000000,0.000000]Pad_3500.000000x1700.000000_um 40@1 8890 24130) (pin Oval[A]Pad_1700.000000x1700.000000_um 41 -2540 -23900) (pin "Rect[T][-900.000000,0.000000]Pad_3500.000000x1700.000000_um" (rotate 90) 41@1 -2540 -23900) (pin Rect[A]Pad_1700.000000x1700.000000_um 42 0 -23900) (pin "Rect[T][-900.000000,0.000000]Pad_3500.000000x1700.000000_um" (rotate 90) 42@1 0 -23900) (pin Oval[A]Pad_1700.000000x1700.000000_um 43 2540 -23900) (pin "Rect[T][-900.000000,0.000000]Pad_3500.000000x1700.000000_um" (rotate 90) 43@1 2540 -23900) ) (image "ZORRO-LAN-IDE-CP-V2F:PLCC-SR32" (outline (path signal 152.4 9144 -9779 9144 9779)) (outline (path signal 152.4 8509 -10414 -8509 -10414)) (outline (path signal 152.4 8509 10414 -7620 10414)) (outline (path signal 152.4 7874 -5461 7366 -5461)) (outline (path signal 152.4 7874 -4699 7874 -5461)) (outline (path signal 152.4 7874 -4191 6858 -4191)) (outline (path signal 152.4 7874 -3429 7874 -4191)) (outline (path signal 152.4 7874 -2921 7366 -2921)) (outline (path signal 152.4 7874 -2159 7874 -2921)) (outline (path signal 152.4 7874 -1651 6858 -1651)) (outline (path signal 152.4 7874 -889 7874 -1651)) (outline (path signal 152.4 7874 -381 7366 -381)) (outline (path signal 152.4 7874 381 7874 -381)) (outline (path signal 152.4 7874 889 6858 889)) (outline (path signal 152.4 7874 1651 7874 889)) (outline (path signal 152.4 7874 2159 7366 2159)) (outline (path signal 152.4 7874 2921 7874 2159)) (outline (path signal 152.4 7874 3429 6858 3429)) (outline (path signal 152.4 7874 4191 7874 3429)) (outline (path signal 152.4 7874 4699 7366 4699)) (outline (path signal 152.4 7874 5461 7874 4699)) (outline (path signal 152.4 7874 8128 6858 9144)) (outline (path signal 152.4 7874 8128 5715 5969)) (outline (path signal 152.4 7366 -4699 7874 -4699)) (outline (path signal 152.4 7366 -2159 7874 -2159)) (outline (path signal 152.4 7366 381 7874 381)) (outline (path signal 152.4 7366 2921 7874 2921)) (outline (path signal 152.4 7366 5461 7874 5461)) (outline (path signal 152.4 6858 -3429 7874 -3429)) (outline (path signal 152.4 6858 -889 7874 -889)) (outline (path signal 152.4 6858 1651 7874 1651)) (outline (path signal 152.4 6858 4191 7874 4191)) (outline (path signal 152.4 6858 9144 4699 6985)) (outline (path signal 152.4 5715 -5715 5715 -6985)) (outline (path signal 152.4 5715 5969 5715 5715)) (outline (path signal 152.4 4699 6985 4445 6985)) (outline (path signal 152.4 4445 -6985 5715 -6985)) (outline (path signal 152.4 4191 -9144 4191 -8636)) (outline (path signal 152.4 4191 8636 4191 9144)) (outline (path signal 152.4 4191 9144 3429 9144)) (outline (path signal 152.4 3429 -9144 4191 -9144)) (outline (path signal 152.4 3429 -8636 3429 -9144)) (outline (path signal 152.4 3429 9144 3429 8636)) (outline (path signal 152.4 2921 -9144 2921 -8255)) (outline (path signal 152.4 2921 8255 2921 9144)) (outline (path signal 152.4 2921 9144 2159 9144)) (outline (path signal 152.4 2159 -9144 2921 -9144)) (outline (path signal 152.4 2159 -8255 2159 -9144)) (outline (path signal 152.4 2159 9144 2159 8255)) (outline (path signal 152.4 1651 -9144 1651 -8636)) (outline (path signal 152.4 1651 8636 1651 9144)) (outline (path signal 152.4 1651 9144 889 9144)) (outline (path signal 152.4 1270 3556 0 4826)) (outline (path signal 152.4 889 -9144 1651 -9144)) (outline (path signal 152.4 889 -8636 889 -9144)) (outline (path signal 152.4 889 9144 889 8636)) (outline (path signal 152.4 381 -9144 381 -8255)) (outline (path signal 152.4 381 8255 381 9144)) (outline (path signal 152.4 381 9144 -381 9144)) (outline (path signal 152.4 0 4826 -1270 3556)) (outline (path signal 152.4 -381 -9144 381 -9144)) (outline (path signal 152.4 -381 -8255 -381 -9144)) (outline (path signal 152.4 -381 9144 -381 8255)) (outline (path signal 152.4 -889 -9144 -889 -8636)) (outline (path signal 152.4 -889 8636 -889 9144)) (outline (path signal 152.4 -889 9144 -1651 9144)) (outline (path signal 152.4 -1270 3556 1270 3556)) (outline (path signal 152.4 -1651 -9144 -889 -9144)) (outline (path signal 152.4 -1651 -8636 -1651 -9144)) (outline (path signal 152.4 -1651 9144 -1651 8636)) (outline (path signal 152.4 -2159 -9144 -2159 -8255)) (outline (path signal 152.4 -2159 8255 -2159 9144)) (outline (path signal 152.4 -2159 9144 -2921 9144)) (outline (path signal 152.4 -2921 -9144 -2159 -9144)) (outline (path signal 152.4 -2921 -8255 -2921 -9144)) (outline (path signal 152.4 -2921 9144 -2921 8255)) (outline (path signal 152.4 -3429 -9144 -3429 -8636)) (outline (path signal 152.4 -3429 8636 -3429 9144)) (outline (path signal 152.4 -3429 9144 -4191 9144)) (outline (path signal 152.4 -4191 -9144 -3429 -9144)) (outline (path signal 152.4 -4191 -8636 -4191 -9144)) (outline (path signal 152.4 -4191 9144 -4191 8636)) (outline (path signal 152.4 -4699 -6985 -4445 -6985)) (outline (path signal 152.4 -5715 -5969 -5715 -5715)) (outline (path signal 152.4 -5715 5715 -4445 6985)) (outline (path signal 152.4 -6858 -9144 -4699 -6985)) (outline (path signal 152.4 -6858 -9144 -7874 -8128)) (outline (path signal 152.4 -6985 -4191 -7874 -4191)) (outline (path signal 152.4 -6985 -1651 -7874 -1651)) (outline (path signal 152.4 -6985 889 -7874 889)) (outline (path signal 152.4 -6985 3429 -7874 3429)) (outline (path signal 152.4 -7366 -5461 -7874 -5461)) (outline (path signal 152.4 -7366 -2921 -7874 -2921)) (outline (path signal 152.4 -7366 -381 -7874 -381)) (outline (path signal 152.4 -7366 2159 -7874 2159)) (outline (path signal 152.4 -7366 4699 -7874 4699)) (outline (path signal 152.4 -7620 10414 -9144 8890)) (outline (path signal 152.4 -7874 -8128 -5715 -5969)) (outline (path signal 152.4 -7874 -5461 -7874 -4699)) (outline (path signal 152.4 -7874 -4699 -7366 -4699)) (outline (path signal 152.4 -7874 -4191 -7874 -3429)) (outline (path signal 152.4 -7874 -3429 -6985 -3429)) (outline (path signal 152.4 -7874 -2921 -7874 -2159)) (outline (path signal 152.4 -7874 -2159 -7366 -2159)) (outline (path signal 152.4 -7874 -1651 -7874 -889)) (outline (path signal 152.4 -7874 -889 -6985 -889)) (outline (path signal 152.4 -7874 -381 -7874 381)) (outline (path signal 152.4 -7874 381 -7366 381)) (outline (path signal 152.4 -7874 889 -7874 1651)) (outline (path signal 152.4 -7874 1651 -6985 1651)) (outline (path signal 152.4 -7874 2159 -7874 2921)) (outline (path signal 152.4 -7874 2921 -7366 2921)) (outline (path signal 152.4 -7874 3429 -7874 4191)) (outline (path signal 152.4 -7874 4191 -6985 4191)) (outline (path signal 152.4 -7874 4699 -7874 5461)) (outline (path signal 152.4 -7874 5461 -7366 5461)) (outline (path signal 152.4 -9144 8890 -9144 -9779)) (outline (polygon signal 0 9067.8 -9779 9082.35 -9734.21 9120.45 -9706.53 9167.55 -9706.53 9205.65 -9734.21 9220.2 -9779 9206.53 -9917.75 9166.06 -10051.2 9100.34 -10174.1 9011.9 -10281.9 8904.12 -10370.3 8781.17 -10436.1 8647.75 -10476.5 8509 -10490.2 8464.21 -10475.6 8436.53 -10437.5 8436.53 -10390.5 8464.21 -10352.4 8509 -10337.8 8571.96 -10337.8 8694.73 -10309.8 8808.18 -10255.1 8906.63 -10176.6 8985.14 -10078.2 9039.78 -9964.73 9067.8 -9841.96 9067.8 -9779)) (outline (polygon signal 0 8509 10337.8 8464.21 10352.4 8436.53 10390.5 8436.53 10437.5 8464.21 10475.6 8509 10490.2 8647.75 10476.5 8781.17 10436.1 8904.12 10370.3 9011.9 10281.9 9100.34 10174.1 9166.06 10051.2 9206.53 9917.75 9220.2 9779 9205.65 9734.21 9167.55 9706.53 9120.45 9706.53 9082.35 9734.21 9067.8 9779 9067.8 9841.96 9039.78 9964.73 8985.14 10078.2 8906.63 10176.6 8808.18 10255.1 8694.73 10309.8 8571.96 10337.8 8509 10337.8)) (outline (polygon signal 0 3384.12 1695.88 3426.08 1717.26 3472.59 1709.89 3505.89 1676.59 3513.26 1630.08 3491.88 1588.12 3324.11 1445.78 3135.39 1332.66 2930.76 1251.8 2715.7 1205.36 2495.94 1194.56 2277.36 1219.71 2065.8 1280.13 1866.9 1374.2 1685.99 1499.42 1527.88 1652.43 1396.82 1829.15 1296.29 2024.87 1228.99 2234.34 1196.7 2451.98 1200.3 2671.98 1239.69 2888.44 1313.82 3095.6 1420.7 3287.92 1557.47 3460.26 1720.5 3608.02 1905.42 3727.25 2107.29 3814.76 2320.71 3868.22 2540 3886.2 2584.79 3871.65 2612.47 3833.55 2612.47 3786.45 2584.79 3748.35 2540 3733.8 2433.17 3733.85 2222.9 3695.92 2022.7 3621.25 1838.95 3512.22 1677.47 3372.3 1543.4 3205.93 1441 3018.4 1373.52 2815.67 1343.12 2604.18 1350.74 2390.65 1396.16 2181.87 1477.92 1984.47 1593.44 1804.72 1739.03 1648.34 1910.08 1520.29 2101.14 1424.65 2306.15 1364.45 2518.59 1341.61 2731.72 1356.85 2938.75 1409.69 3133.1 1498.45 3308.61 1620.3 3384.12 1695.88)) (outline (polygon signal 0 3384.02 -3384.01 3425.98 -3362.64 3472.5 -3370.01 3505.8 -3403.31 3513.16 -3449.82 3491.78 -3491.78 3324.01 -3634.11 3135.3 -3747.2 2930.68 -3828.05 2715.64 -3874.48 2495.89 -3885.27 2277.33 -3860.11 2065.79 -3799.69 1866.91 -3705.62 1686.01 -3580.41 1527.92 -3427.4 1396.87 -3250.69 1296.36 -3054.99 1229.06 -2845.53 1196.79 -2627.9 1200.39 -2407.93 1239.78 -2191.47 1313.9 -1984.33 1420.77 -1792.03 1557.55 -1619.7 1720.56 -1471.96 1905.46 -1352.74 2107.32 -1265.23 2320.73 -1211.78 2540 -1193.8 2584.79 -1208.35 2612.47 -1246.45 2612.47 -1293.55 2584.79 -1331.65 2540 -1346.2 2433.18 -1346.14 2222.92 -1384.08 2022.74 -1458.74 1839 -1567.76 1677.54 -1707.66 1543.48 -1874.02 1441.08 -2061.53 1373.61 -2264.24 1343.2 -2475.72 1350.82 -2689.23 1396.23 -2898 1477.98 -3095.39 1593.48 -3275.12 1739.06 -3431.49 1910.09 -3559.53 2101.14 -3655.18 2306.13 -3715.38 2518.55 -3738.22 2731.66 -3722.99 2938.67 -3670.16 3133.02 -3581.42 3308.52 -3459.58 3384.02 -3384.01)) (outline (polygon signal 0 -3384.12 -1695.88 -3426.08 -1717.26 -3472.59 -1709.89 -3505.89 -1676.59 -3513.26 -1630.08 -3491.88 -1588.12 -3324.11 -1445.78 -3135.39 -1332.66 -2930.76 -1251.8 -2715.7 -1205.36 -2495.94 -1194.56 -2277.36 -1219.71 -2065.8 -1280.13 -1866.9 -1374.2 -1685.99 -1499.42 -1527.88 -1652.43 -1396.82 -1829.15 -1296.29 -2024.87 -1228.99 -2234.34 -1196.7 -2451.98 -1200.3 -2671.98 -1239.69 -2888.44 -1313.82 -3095.6 -1420.7 -3287.92 -1557.47 -3460.26 -1720.5 -3608.02 -1905.42 -3727.25 -2107.29 -3814.76 -2320.71 -3868.22 -2540 -3886.2 -2584.79 -3871.65 -2612.47 -3833.55 -2612.47 -3786.45 -2584.79 -3748.35 -2540 -3733.8 -2433.17 -3733.85 -2222.9 -3695.92 -2022.7 -3621.25 -1838.95 -3512.22 -1677.47 -3372.3 -1543.4 -3205.93 -1441 -3018.4 -1373.52 -2815.67 -1343.12 -2604.18 -1350.74 -2390.65 -1396.16 -2181.87 -1477.92 -1984.47 -1593.44 -1804.72 -1739.03 -1648.34 -1910.08 -1520.29 -2101.14 -1424.65 -2306.15 -1364.45 -2518.59 -1341.61 -2731.72 -1356.85 -2938.75 -1409.69 -3133.1 -1498.45 -3308.61 -1620.3 -3384.12 -1695.88)) (outline (polygon signal 0 -3384.12 3384.12 -3426.08 3362.74 -3472.6 3370.11 -3505.9 3403.41 -3513.26 3449.92 -3491.88 3491.88 -3324.1 3634.22 -3135.37 3747.33 -2930.74 3828.19 -2715.67 3874.63 -2495.91 3885.42 -2277.32 3860.26 -2065.75 3799.84 -1866.86 3705.76 -1685.94 3580.54 -1527.84 3427.52 -1396.77 3250.79 -1296.24 3055.07 -1228.94 2845.59 -1196.66 2627.94 -1200.26 2407.95 -1239.66 2191.47 -1313.78 1984.31 -1420.67 1791.99 -1557.45 1619.64 -1720.48 1471.89 -1905.4 1352.66 -2107.28 1265.14 -2320.71 1211.68 -2540 1193.7 -2584.79 1208.25 -2612.47 1246.35 -2612.47 1293.45 -2584.79 1331.55 -2540 1346.1 -2433.16 1346.05 -2222.89 1383.98 -2022.69 1458.65 -1838.93 1567.68 -1677.44 1707.61 -1543.37 1873.98 -1440.97 2061.51 -1373.49 2264.25 -1343.07 2475.74 -1350.7 2689.28 -1396.11 2898.07 -1477.88 3095.48 -1593.39 3275.23 -1738.99 3431.62 -1910.04 3559.67 -2101.1 3655.32 -2306.12 3715.53 -2518.56 3738.37 -2731.69 3723.14 -2938.73 3670.3 -3133.09 3581.55 -3308.61 3459.7 -3384.12 3384.12)) (outline (polygon signal 0 -8509 -10337.8 -8464.21 -10352.4 -8436.53 -10390.5 -8436.53 -10437.5 -8464.21 -10475.6 -8509 -10490.2 -8647.75 -10476.5 -8781.17 -10436.1 -8904.12 -10370.3 -9011.9 -10281.9 -9100.34 -10174.1 -9166.06 -10051.2 -9206.53 -9917.75 -9220.2 -9779 -9205.65 -9734.21 -9167.55 -9706.53 -9120.45 -9706.53 -9082.35 -9734.21 -9067.8 -9779 -9067.8 -9841.96 -9039.78 -9964.73 -8985.14 -10078.2 -8906.63 -10176.6 -8808.18 -10255.1 -8694.73 -10309.8 -8571.96 -10337.8 -8509 -10337.8)) (outline (path signal 152.4 7366 -4699 5715 -4699)) (outline (path signal 152.4 7366 -2159 5715 -2159)) (outline (path signal 152.4 7366 381 5715 381)) (outline (path signal 152.4 7366 2921 5715 2921)) (outline (path signal 152.4 7366 5461 5715 5461)) (outline (path signal 152.4 6858 -3429 5715 -3429)) (outline (path signal 152.4 6858 -889 5715 -889)) (outline (path signal 152.4 6858 1651 5715 1651)) (outline (path signal 152.4 6858 4191 5715 4191)) (outline (path signal 152.4 5715 -5715 5715 -5461)) (outline (path signal 152.4 5715 -5461 7366 -5461)) (outline (path signal 152.4 5715 -4191 6858 -4191)) (outline (path signal 152.4 5715 -4191 5715 -4699)) (outline (path signal 152.4 5715 -2921 7366 -2921)) (outline (path signal 152.4 5715 -2921 5715 -3429)) (outline (path signal 152.4 5715 -1651 6858 -1651)) (outline (path signal 152.4 5715 -1651 5715 -2159)) (outline (path signal 152.4 5715 -381 7366 -381)) (outline (path signal 152.4 5715 -381 5715 -889)) (outline (path signal 152.4 5715 889 6858 889)) (outline (path signal 152.4 5715 889 5715 381)) (outline (path signal 152.4 5715 2159 7366 2159)) (outline (path signal 152.4 5715 2159 5715 1651)) (outline (path signal 152.4 5715 3429 6858 3429)) (outline (path signal 152.4 5715 3429 5715 2921)) (outline (path signal 152.4 5715 4699 7366 4699)) (outline (path signal 152.4 5715 4699 5715 4191)) (outline (path signal 152.4 5715 5461 5715 5715)) (outline (path signal 152.4 4445 -6985 4191 -6985)) (outline (path signal 152.4 4191 -6985 4191 -8636)) (outline (path signal 152.4 4191 6985 4445 6985)) (outline (path signal 152.4 4191 8636 4191 6985)) (outline (path signal 152.4 3429 -8636 3429 -6985)) (outline (path signal 152.4 3429 6985 3429 8636)) (outline (path signal 152.4 3429 6985 2921 6985)) (outline (path signal 152.4 2921 -6985 3429 -6985)) (outline (path signal 152.4 2921 -6985 2921 -8255)) (outline (path signal 152.4 2921 8255 2921 6985)) (outline (path signal 152.4 2159 -8255 2159 -6985)) (outline (path signal 152.4 2159 6985 2159 8255)) (outline (path signal 152.4 2159 6985 1651 6985)) (outline (path signal 152.4 1651 -6985 2159 -6985)) (outline (path signal 152.4 1651 -6985 1651 -8636)) (outline (path signal 152.4 1651 8636 1651 6985)) (outline (path signal 152.4 889 -8636 889 -6985)) (outline (path signal 152.4 889 6985 889 8636)) (outline (path signal 152.4 889 6985 381 6985)) (outline (path signal 152.4 381 -6985 889 -6985)) (outline (path signal 152.4 381 -6985 381 -8255)) (outline (path signal 152.4 381 8255 381 6985)) (outline (path signal 152.4 -381 -8255 -381 -6985)) (outline (path signal 152.4 -381 6985 -381 8255)) (outline (path signal 152.4 -381 6985 -889 6985)) (outline (path signal 152.4 -889 -6985 -381 -6985)) (outline (path signal 152.4 -889 -6985 -889 -8636)) (outline (path signal 152.4 -889 8636 -889 6985)) (outline (path signal 152.4 -1651 -8636 -1651 -6985)) (outline (path signal 152.4 -1651 6985 -1651 8636)) (outline (path signal 152.4 -1651 6985 -2159 6985)) (outline (path signal 152.4 -2159 -6985 -1651 -6985)) (outline (path signal 152.4 -2159 -6985 -2159 -8255)) (outline (path signal 152.4 -2159 8255 -2159 6985)) (outline (path signal 152.4 -2921 -8255 -2921 -6985)) (outline (path signal 152.4 -2921 6985 -2921 8255)) (outline (path signal 152.4 -2921 6985 -3429 6985)) (outline (path signal 152.4 -3429 -6985 -2921 -6985)) (outline (path signal 152.4 -3429 -6985 -3429 -8636)) (outline (path signal 152.4 -3429 8636 -3429 6985)) (outline (path signal 152.4 -4191 -8636 -4191 -6985)) (outline (path signal 152.4 -4191 -6985 -4445 -6985)) (outline (path signal 152.4 -4191 6985 -4191 8636)) (outline (path signal 152.4 -4191 6985 -4445 6985)) (outline (path signal 152.4 -5715 -5715 -5715 -5461)) (outline (path signal 152.4 -5715 -4699 -5715 -4191)) (outline (path signal 152.4 -5715 -4699 -7366 -4699)) (outline (path signal 152.4 -5715 -3429 -5715 -2921)) (outline (path signal 152.4 -5715 -3429 -6985 -3429)) (outline (path signal 152.4 -5715 -2159 -5715 -1651)) (outline (path signal 152.4 -5715 -2159 -7366 -2159)) (outline (path signal 152.4 -5715 -889 -5715 -381)) (outline (path signal 152.4 -5715 -889 -6985 -889)) (outline (path signal 152.4 -5715 381 -5715 889)) (outline (path signal 152.4 -5715 381 -7366 381)) (outline (path signal 152.4 -5715 1651 -5715 2159)) (outline (path signal 152.4 -5715 1651 -6985 1651)) (outline (path signal 152.4 -5715 2921 -5715 3429)) (outline (path signal 152.4 -5715 2921 -7366 2921)) (outline (path signal 152.4 -5715 4191 -5715 4699)) (outline (path signal 152.4 -5715 4191 -6985 4191)) (outline (path signal 152.4 -5715 5461 -5715 5715)) (outline (path signal 152.4 -5715 5461 -7366 5461)) (outline (path signal 152.4 -6985 -4191 -5715 -4191)) (outline (path signal 152.4 -6985 -1651 -5715 -1651)) (outline (path signal 152.4 -6985 889 -5715 889)) (outline (path signal 152.4 -6985 3429 -5715 3429)) (outline (path signal 152.4 -7366 -5461 -5715 -5461)) (outline (path signal 152.4 -7366 -2921 -5715 -2921)) (outline (path signal 152.4 -7366 -381 -5715 -381)) (outline (path signal 152.4 -7366 2159 -5715 2159)) (outline (path signal 152.4 -7366 4699 -5715 4699)) (outline (polygon signal 0 3733.8 -2540 3748.36 -2495.21 3786.46 -2467.53 3833.55 -2467.53 3871.65 -2495.21 3886.2 -2540 3874.68 -2715.71 3840.32 -2888.42 3783.71 -3055.16 3705.82 -3213.09 3607.99 -3359.5 3491.88 -3491.88 3449.92 -3513.26 3403.4 -3505.89 3370.1 -3472.59 3362.74 -3426.08 3384.12 -3384.12 3450.56 -3317.68 3561.01 -3165.67 3646.32 -2998.25 3704.39 -2819.54 3733.8 -2633.95 3733.8 -2540)) (outline (polygon signal 0 3733.8 2540 3748.36 2584.79 3786.46 2612.47 3833.55 2612.47 3871.65 2584.79 3886.2 2540 3874.68 2364.29 3840.32 2191.58 3783.71 2024.84 3705.82 1866.91 3607.99 1720.5 3491.88 1588.12 3449.92 1566.74 3403.4 1574.11 3370.1 1607.41 3362.74 1653.92 3384.12 1695.88 3450.56 1762.32 3561.01 1914.33 3646.32 2081.75 3704.39 2260.46 3733.8 2446.05 3733.8 2540)) (outline (polygon signal 0 2540 -1346.2 2495.21 -1331.65 2467.53 -1293.55 2467.53 -1246.45 2495.21 -1208.35 2540 -1193.8 2750.59 -1210.37 2956 -1259.69 3151.16 -1340.53 3331.28 -1450.9 3491.91 -1588.09 3629.1 -1748.72 3739.47 -1928.84 3820.31 -2124 3869.63 -2329.41 3886.2 -2540 3871.65 -2584.79 3833.55 -2612.47 3786.45 -2612.47 3748.35 -2584.79 3733.8 -2540 3733.8 -2446.05 3704.4 -2260.45 3646.34 -2081.74 3561.03 -1914.31 3450.58 -1762.29 3317.71 -1629.42 3165.69 -1518.97 2998.26 -1433.66 2819.55 -1375.6 2633.95 -1346.2 2540 -1346.2)) (outline (polygon signal 0 2540 3733.8 2495.21 3748.35 2467.53 3786.45 2467.53 3833.55 2495.21 3871.65 2540 3886.2 2750.59 3869.63 2956 3820.31 3151.16 3739.47 3331.28 3629.1 3491.91 3491.91 3629.1 3331.28 3739.47 3151.16 3820.31 2956 3869.63 2750.59 3886.2 2540 3871.65 2495.21 3833.55 2467.53 3786.45 2467.53 3748.35 2495.21 3733.8 2540 3733.8 2633.95 3704.4 2819.55 3646.34 2998.26 3561.03 3165.69 3450.58 3317.71 3317.71 3450.58 3165.69 3561.03 2998.26 3646.34 2819.55 3704.4 2633.95 3733.8 2540 3733.8)) (outline (polygon signal 0 -2540 -3733.8 -2495.21 -3748.35 -2467.53 -3786.45 -2467.53 -3833.55 -2495.21 -3871.65 -2540 -3886.2 -2750.59 -3869.63 -2956 -3820.31 -3151.16 -3739.47 -3331.28 -3629.1 -3491.91 -3491.91 -3629.1 -3331.28 -3739.47 -3151.16 -3820.31 -2956 -3869.63 -2750.59 -3886.2 -2540 -3871.65 -2495.21 -3833.55 -2467.53 -3786.45 -2467.53 -3748.35 -2495.21 -3733.8 -2540 -3733.8 -2633.95 -3704.4 -2819.55 -3646.34 -2998.26 -3561.03 -3165.69 -3450.58 -3317.71 -3317.71 -3450.58 -3165.69 -3561.03 -2998.26 -3646.34 -2819.55 -3704.4 -2633.95 -3733.8 -2540 -3733.8)) (outline (polygon signal 0 -2540 1346.2 -2495.21 1331.65 -2467.53 1293.55 -2467.53 1246.45 -2495.21 1208.35 -2540 1193.8 -2750.59 1210.37 -2956 1259.69 -3151.16 1340.53 -3331.28 1450.9 -3491.91 1588.09 -3629.1 1748.72 -3739.47 1928.84 -3820.31 2124 -3869.63 2329.41 -3886.2 2540 -3871.65 2584.79 -3833.55 2612.47 -3786.45 2612.47 -3748.35 2584.79 -3733.8 2540 -3733.8 2446.05 -3704.4 2260.45 -3646.34 2081.74 -3561.03 1914.31 -3450.58 1762.29 -3317.71 1629.42 -3165.69 1518.97 -2998.26 1433.66 -2819.55 1375.6 -2633.95 1346.2 -2540 1346.2)) (outline (polygon signal 0 -3733.8 -2540 -3748.36 -2584.79 -3786.46 -2612.47 -3833.55 -2612.47 -3871.65 -2584.79 -3886.2 -2540 -3874.68 -2364.29 -3840.32 -2191.58 -3783.71 -2024.84 -3705.82 -1866.91 -3607.99 -1720.5 -3491.88 -1588.12 -3449.92 -1566.74 -3403.4 -1574.11 -3370.1 -1607.41 -3362.74 -1653.92 -3384.12 -1695.88 -3450.56 -1762.32 -3561.01 -1914.33 -3646.32 -2081.75 -3704.39 -2260.46 -3733.8 -2446.05 -3733.8 -2540)) (outline (polygon signal 0 -3733.8 2540 -3748.36 2495.21 -3786.46 2467.53 -3833.55 2467.53 -3871.65 2495.21 -3886.2 2540 -3874.68 2715.71 -3840.32 2888.42 -3783.71 3055.16 -3705.82 3213.09 -3607.99 3359.5 -3491.88 3491.88 -3449.92 3513.26 -3403.4 3505.89 -3370.1 3472.59 -3362.74 3426.08 -3384.12 3384.12 -3450.55 3317.68 -3561.01 3165.67 -3646.32 2998.25 -3704.39 2819.54 -3733.8 2633.95 -3733.8 2540)) (pin Round[A]Pad_1600.200000_um 1 1270 5080) (pin RoundRect[A]Pad_1600.200000x1600.200000_401.572000_um_0.292893_F 2 -1270 7620) (pin RoundRect[A]Pad_1600.200000x1600.200000_401.572000_um_0.292893_F 3 -1270 5080) (pin RoundRect[A]Pad_1600.200000x1600.200000_401.572000_um_0.292893_F 4 -3810 7620) (pin RoundRect[A]Pad_1600.200000x1600.200000_401.572000_um_0.292893_F 5 -6350 5080) (pin RoundRect[A]Pad_1600.200000x1600.200000_401.572000_um_0.292893_F 6 -3810 5080) (pin RoundRect[A]Pad_1600.200000x1600.200000_401.572000_um_0.292893_F 7 -6350 2540) (pin RoundRect[A]Pad_1600.200000x1600.200000_401.572000_um_0.292893_F 8 -3810 2540) (pin RoundRect[A]Pad_1600.200000x1600.200000_401.572000_um_0.292893_F 9 -6350 0) (pin RoundRect[A]Pad_1600.200000x1600.200000_401.572000_um_0.292893_F 10 -3810 0) (pin RoundRect[A]Pad_1600.200000x1600.200000_401.572000_um_0.292893_F 11 -6350 -2540) (pin RoundRect[A]Pad_1600.200000x1600.200000_401.572000_um_0.292893_F 12 -3810 -2540) (pin RoundRect[A]Pad_1600.200000x1600.200000_401.572000_um_0.292893_F 13 -6350 -5080) (pin RoundRect[A]Pad_1600.200000x1600.200000_401.572000_um_0.292893_F 14 -3810 -7620) (pin RoundRect[A]Pad_1600.200000x1600.200000_401.572000_um_0.292893_F 15 -3810 -5080) (pin RoundRect[A]Pad_1600.200000x1600.200000_401.572000_um_0.292893_F 16 -1270 -7620) (pin RoundRect[A]Pad_1600.200000x1600.200000_401.572000_um_0.292893_F 17 -1270 -5080) (pin RoundRect[A]Pad_1600.200000x1600.200000_401.572000_um_0.292893_F 18 1270 -7620) (pin RoundRect[A]Pad_1600.200000x1600.200000_401.572000_um_0.292893_F 19 1270 -5080) (pin RoundRect[A]Pad_1600.200000x1600.200000_401.572000_um_0.292893_F 20 3810 -7620) (pin RoundRect[A]Pad_1600.200000x1600.200000_401.572000_um_0.292893_F 21 6350 -5080) (pin RoundRect[A]Pad_1600.200000x1600.200000_401.572000_um_0.292893_F 22 3810 -5080) (pin RoundRect[A]Pad_1600.200000x1600.200000_401.572000_um_0.292893_F 23 6350 -2540) (pin RoundRect[A]Pad_1600.200000x1600.200000_401.572000_um_0.292893_F 24 3810 -2540) (pin RoundRect[A]Pad_1600.200000x1600.200000_401.572000_um_0.292893_F 25 6350 0) (pin RoundRect[A]Pad_1600.200000x1600.200000_401.572000_um_0.292893_F 26 3810 0) (pin RoundRect[A]Pad_1600.200000x1600.200000_401.572000_um_0.292893_F 27 6350 2540) (pin RoundRect[A]Pad_1600.200000x1600.200000_401.572000_um_0.292893_F 28 3810 2540) (pin RoundRect[A]Pad_1600.200000x1600.200000_401.572000_um_0.292893_F 29 6350 5080) (pin RoundRect[A]Pad_1600.200000x1600.200000_401.572000_um_0.292893_F 30 3810 7620) (pin RoundRect[A]Pad_1600.200000x1600.200000_401.572000_um_0.292893_F 31 3810 5080) (pin RoundRect[A]Pad_1600.200000x1600.200000_401.572000_um_0.292893_F 32 1270 7620) ) (image "ZORRO-LAN-IDE-CP-V2F:R0603::2" (outline (path signal 50.8 -1473 983 1473 983)) (outline (path signal 50.8 -1473 -983 -1473 983)) (outline (path signal 50.8 1473 983 1473 -983)) (outline (path signal 50.8 1473 -983 -1473 -983)) (outline (path signal 152.4 -432 -356 432 -356)) (outline (path signal 152.4 432 356 -432 356)) (pin Rect[T]Pad_1000.000000x1100.000000_um 1 -850 0) (pin Rect[T]Pad_1000.000000x1100.000000_um 2 850 0) ) (image "SOT-23" (outline (path signal 120 -760 1560 760 1560)) (outline (path signal 120 -760 1510 -760 1560)) (outline (path signal 120 -760 -390 -760 390)) (outline (path signal 120 -760 -1560 -760 -1510)) (outline (path signal 120 760 1560 760 560)) (outline (path signal 120 760 -560 760 -1560)) (outline (path signal 120 760 -1560 -760 -1560)) (outline (path signal 50 -1930 1500 -900 1500)) (outline (path signal 50 -1930 390 -1930 1500)) (outline (path signal 50 -1930 -390 -900 -390)) (outline (path signal 50 -1930 -1500 -1930 -390)) (outline (path signal 50 -900 1700 900 1700)) (outline (path signal 50 -900 1500 -900 1700)) (outline (path signal 50 -900 390 -1930 390)) (outline (path signal 50 -900 -390 -900 390)) (outline (path signal 50 -900 -1500 -1930 -1500)) (outline (path signal 50 -900 -1700 -900 -1500)) (outline (path signal 50 900 1700 900 550)) (outline (path signal 50 900 550 1930 550)) (outline (path signal 50 900 -550 900 -1700)) (outline (path signal 50 900 -1700 -900 -1700)) (outline (path signal 50 1930 550 1930 -550)) (outline (path signal 50 1930 -550 900 -550)) (pin RoundRect[T]Pad_1475.000000x600.000000_150.571000_um_0.000000_0 1 -937.5 950) (pin RoundRect[T]Pad_1475.000000x600.000000_150.571000_um_0.000000_0 2 -937.5 -950) (pin RoundRect[T]Pad_1475.000000x600.000000_150.571000_um_0.000000_0 3 937.5 0) ) (image "ZORRO-LAN-IDE-CP-V2F:JP1::1" (outline (path signal 152.4 -1270 2286 -1270 254)) (outline (path signal 152.4 -1270 2286 -1016 2540)) (outline (path signal 152.4 -1270 -254 -1270 -2286)) (outline (path signal 152.4 -1016 0 -1270 254)) (outline (path signal 152.4 -1016 0 -1270 -254)) (outline (path signal 152.4 -1016 -2540 -1270 -2286)) (outline (path signal 152.4 -1016 -2540 1016 -2540)) (outline (path signal 152.4 1016 2540 -1016 2540)) (outline (path signal 152.4 1016 0 1270 254)) (outline (path signal 152.4 1016 0 1270 -254)) (outline (path signal 152.4 1016 -2540 1270 -2286)) (outline (path signal 152.4 1270 2286 1016 2540)) (outline (path signal 152.4 1270 2286 1270 254)) (outline (path signal 152.4 1270 -254 1270 -2286)) (pin Oval[A]Pad_2428.800000x1214.400000_um 1 0 -1270) (pin Oval[A]Pad_2428.800000x1214.400000_um 2 0 1270) ) (image "ZORRO-LAN-IDE-CP-V2F:C0805K" (outline (path signal 101.6 -925 600 925 600)) (outline (path signal 101.6 925 -600 -925 -600)) (pin Rect[T]Pad_1300.000000x1600.000000_um 1 -1000 0) (pin Rect[T]Pad_1300.000000x1600.000000_um 2 1000 0) ) (image "ZORRO-LAN-IDE-CP-V2F:LKONT_50_R" (outline (path signal 50 -62230 4603.8 -62230 -5080)) (outline (path signal 50 -62230 -5080 67310.1 -5080)) (outline (path signal 50 67310.1 -5080 67310.1 4762.5)) (pin RoundRect[B]Pad_7620.000000x1270.000000_637.416000_um_0.000000_0 (rotate 90) 1 64770 0) (pin RoundRect[T]Pad_7620.000000x1270.000000_637.416000_um_0.000000_0 (rotate 90) 2 64770 0) (pin RoundRect[B]Pad_7620.000000x1270.000000_637.416000_um_0.000000_0 (rotate 90) 3 62230 0) (pin RoundRect[T]Pad_7620.000000x1270.000000_637.416000_um_0.000000_0 (rotate 90) 4 62230 0) (pin RoundRect[B]Pad_7620.000000x1270.000000_637.416000_um_0.000000_0 (rotate 90) 5 59690 0) (pin RoundRect[T]Pad_7620.000000x1270.000000_637.416000_um_0.000000_0 (rotate 90) 6 59690 0) (pin RoundRect[B]Pad_7620.000000x1270.000000_637.416000_um_0.000000_0 (rotate 90) 7 57150 0) (pin RoundRect[T]Pad_7620.000000x1270.000000_637.416000_um_0.000000_0 (rotate 90) 8 57150 0) (pin RoundRect[B]Pad_7620.000000x1270.000000_637.416000_um_0.000000_0 (rotate 90) 9 54610 0) (pin RoundRect[T]Pad_7620.000000x1270.000000_637.416000_um_0.000000_0 (rotate 90) 10 54610 0) (pin RoundRect[B]Pad_7620.000000x1270.000000_637.416000_um_0.000000_0 (rotate 90) 11 52070 0) (pin RoundRect[T]Pad_7620.000000x1270.000000_637.416000_um_0.000000_0 (rotate 90) 12 52070 0) (pin RoundRect[B]Pad_7620.000000x1270.000000_637.416000_um_0.000000_0 (rotate 90) 13 49530 0) (pin RoundRect[T]Pad_7620.000000x1270.000000_637.416000_um_0.000000_0 (rotate 90) 14 49530 0) (pin RoundRect[B]Pad_7620.000000x1270.000000_637.416000_um_0.000000_0 (rotate 90) 15 46990 0) (pin RoundRect[T]Pad_7620.000000x1270.000000_637.416000_um_0.000000_0 (rotate 90) 16 46990 0) (pin RoundRect[B]Pad_7620.000000x1270.000000_637.416000_um_0.000000_0 (rotate 90) 17 44450 0) (pin RoundRect[T]Pad_7620.000000x1270.000000_637.416000_um_0.000000_0 (rotate 90) 18 44450 0) (pin RoundRect[B]Pad_7620.000000x1270.000000_637.416000_um_0.000000_0 (rotate 90) 19 41910 0) (pin RoundRect[T]Pad_7620.000000x1270.000000_637.416000_um_0.000000_0 (rotate 90) 20 41910 0) (pin RoundRect[B]Pad_7620.000000x1270.000000_637.416000_um_0.000000_0 (rotate 90) 21 39370 0) (pin RoundRect[T]Pad_7620.000000x1270.000000_637.416000_um_0.000000_0 (rotate 90) 22 39370 0) (pin RoundRect[B]Pad_7620.000000x1270.000000_637.416000_um_0.000000_0 (rotate 90) 23 36830 0) (pin RoundRect[T]Pad_7620.000000x1270.000000_637.416000_um_0.000000_0 (rotate 90) 24 36830 0) (pin RoundRect[B]Pad_7620.000000x1270.000000_637.416000_um_0.000000_0 (rotate 90) 25 34290 0) (pin RoundRect[T]Pad_7620.000000x1270.000000_637.416000_um_0.000000_0 (rotate 90) 26 34290 0) (pin RoundRect[B]Pad_7620.000000x1270.000000_637.416000_um_0.000000_0 (rotate 90) 27 31750 0) (pin RoundRect[T]Pad_7620.000000x1270.000000_637.416000_um_0.000000_0 (rotate 90) 28 31750 0) (pin RoundRect[B]Pad_7620.000000x1270.000000_637.416000_um_0.000000_0 (rotate 90) 29 29210 0) (pin RoundRect[T]Pad_7620.000000x1270.000000_637.416000_um_0.000000_0 (rotate 90) 30 29210 0) (pin RoundRect[B]Pad_7620.000000x1270.000000_637.416000_um_0.000000_0 (rotate 90) 31 26670 0) (pin RoundRect[T]Pad_7620.000000x1270.000000_637.416000_um_0.000000_0 (rotate 90) 32 26670 0) (pin RoundRect[B]Pad_7620.000000x1270.000000_637.416000_um_0.000000_0 (rotate 90) 33 24130 0) (pin RoundRect[T]Pad_7620.000000x1270.000000_637.416000_um_0.000000_0 (rotate 90) 34 24130 0) (pin RoundRect[B]Pad_7620.000000x1270.000000_637.416000_um_0.000000_0 (rotate 90) 35 21590 0) (pin RoundRect[T]Pad_7620.000000x1270.000000_637.416000_um_0.000000_0 (rotate 90) 36 21590 0) (pin RoundRect[B]Pad_7620.000000x1270.000000_637.416000_um_0.000000_0 (rotate 90) 37 19050 0) (pin RoundRect[T]Pad_7620.000000x1270.000000_637.416000_um_0.000000_0 (rotate 90) 38 19050 0) (pin RoundRect[B]Pad_7620.000000x1270.000000_637.416000_um_0.000000_0 (rotate 90) 39 16510 0) (pin RoundRect[T]Pad_7620.000000x1270.000000_637.416000_um_0.000000_0 (rotate 90) 40 16510 0) (pin RoundRect[B]Pad_7620.000000x1270.000000_637.416000_um_0.000000_0 (rotate 90) 41 13970 0) (pin RoundRect[T]Pad_7620.000000x1270.000000_637.416000_um_0.000000_0 (rotate 90) 42 13970 0) (pin RoundRect[B]Pad_7620.000000x1270.000000_637.416000_um_0.000000_0 (rotate 90) 43 11430 0) (pin RoundRect[T]Pad_7620.000000x1270.000000_637.416000_um_0.000000_0 (rotate 90) 44 11430 0) (pin RoundRect[B]Pad_7620.000000x1270.000000_637.416000_um_0.000000_0 (rotate 90) 45 8890 0) (pin RoundRect[T]Pad_7620.000000x1270.000000_637.416000_um_0.000000_0 (rotate 90) 46 8890 0) (pin RoundRect[B]Pad_7620.000000x1270.000000_637.416000_um_0.000000_0 (rotate 90) 47 6350 0) (pin RoundRect[T]Pad_7620.000000x1270.000000_637.416000_um_0.000000_0 (rotate 90) 48 6350 0) (pin RoundRect[B]Pad_7620.000000x1270.000000_637.416000_um_0.000000_0 (rotate 90) 49 3810 0) (pin RoundRect[T]Pad_7620.000000x1270.000000_637.416000_um_0.000000_0 (rotate 90) 50 3810 0) (pin RoundRect[B]Pad_7620.000000x1270.000000_637.416000_um_0.000000_0 (rotate 90) 51 1270 0) (pin RoundRect[T]Pad_7620.000000x1270.000000_637.416000_um_0.000000_0 (rotate 90) 52 1270 0) (pin RoundRect[B]Pad_7620.000000x1270.000000_637.416000_um_0.000000_0 (rotate 90) 53 -1270 0) (pin RoundRect[T]Pad_7620.000000x1270.000000_637.416000_um_0.000000_0 (rotate 90) 54 -1270 0) (pin RoundRect[B]Pad_7620.000000x1270.000000_637.416000_um_0.000000_0 (rotate 90) 55 -3810 0) (pin RoundRect[T]Pad_7620.000000x1270.000000_637.416000_um_0.000000_0 (rotate 90) 56 -3810 0) (pin RoundRect[B]Pad_7620.000000x1270.000000_637.416000_um_0.000000_0 (rotate 90) 57 -6350 0) (pin RoundRect[T]Pad_7620.000000x1270.000000_637.416000_um_0.000000_0 (rotate 90) 58 -6350 0) (pin RoundRect[B]Pad_7620.000000x1270.000000_637.416000_um_0.000000_0 (rotate 90) 59 -8890 0) (pin RoundRect[T]Pad_7620.000000x1270.000000_637.416000_um_0.000000_0 (rotate 90) 60 -8890 0) (pin RoundRect[B]Pad_7620.000000x1270.000000_637.416000_um_0.000000_0 (rotate 90) 61 -11430 0) (pin RoundRect[T]Pad_7620.000000x1270.000000_637.416000_um_0.000000_0 (rotate 90) 62 -11430 0) (pin RoundRect[B]Pad_7620.000000x1270.000000_637.416000_um_0.000000_0 (rotate 90) 63 -13970 0) (pin RoundRect[T]Pad_7620.000000x1270.000000_637.416000_um_0.000000_0 (rotate 90) 64 -13970 0) (pin RoundRect[B]Pad_7620.000000x1270.000000_637.416000_um_0.000000_0 (rotate 90) 65 -16510 0) (pin RoundRect[T]Pad_7620.000000x1270.000000_637.416000_um_0.000000_0 (rotate 90) 66 -16510 0) (pin RoundRect[B]Pad_7620.000000x1270.000000_637.416000_um_0.000000_0 (rotate 90) 67 -19050 0) (pin RoundRect[T]Pad_7620.000000x1270.000000_637.416000_um_0.000000_0 (rotate 90) 68 -19050 0) (pin RoundRect[B]Pad_7620.000000x1270.000000_637.416000_um_0.000000_0 (rotate 90) 69 -21590 0) (pin RoundRect[T]Pad_7620.000000x1270.000000_637.416000_um_0.000000_0 (rotate 90) 70 -21590 0) (pin RoundRect[B]Pad_7620.000000x1270.000000_637.416000_um_0.000000_0 (rotate 90) 71 -24130 0) (pin RoundRect[T]Pad_7620.000000x1270.000000_637.416000_um_0.000000_0 (rotate 90) 72 -24130 0) (pin RoundRect[B]Pad_7620.000000x1270.000000_637.416000_um_0.000000_0 (rotate 90) 73 -26670 0) (pin RoundRect[T]Pad_7620.000000x1270.000000_637.416000_um_0.000000_0 (rotate 90) 74 -26670 0) (pin RoundRect[B]Pad_7620.000000x1270.000000_637.416000_um_0.000000_0 (rotate 90) 75 -29210 0) (pin RoundRect[T]Pad_7620.000000x1270.000000_637.416000_um_0.000000_0 (rotate 90) 76 -29210 0) (pin RoundRect[B]Pad_7620.000000x1270.000000_637.416000_um_0.000000_0 (rotate 90) 77 -31750 0) (pin RoundRect[T]Pad_7620.000000x1270.000000_637.416000_um_0.000000_0 (rotate 90) 78 -31750 0) (pin RoundRect[B]Pad_7620.000000x1270.000000_637.416000_um_0.000000_0 (rotate 90) 79 -34290 0) (pin RoundRect[T]Pad_7620.000000x1270.000000_637.416000_um_0.000000_0 (rotate 90) 80 -34290 0) (pin RoundRect[B]Pad_7620.000000x1270.000000_637.416000_um_0.000000_0 (rotate 90) 81 -36830 0) (pin RoundRect[T]Pad_7620.000000x1270.000000_637.416000_um_0.000000_0 (rotate 90) 82 -36830 0) (pin RoundRect[B]Pad_7620.000000x1270.000000_637.416000_um_0.000000_0 (rotate 90) 83 -39370 0) (pin RoundRect[T]Pad_7620.000000x1270.000000_637.416000_um_0.000000_0 (rotate 90) 84 -39370 0) (pin RoundRect[B]Pad_7620.000000x1270.000000_637.416000_um_0.000000_0 (rotate 90) 85 -41910 0) (pin RoundRect[T]Pad_7620.000000x1270.000000_637.416000_um_0.000000_0 (rotate 90) 86 -41910 0) (pin RoundRect[B]Pad_7620.000000x1270.000000_637.416000_um_0.000000_0 (rotate 90) 87 -44450 0) (pin RoundRect[T]Pad_7620.000000x1270.000000_637.416000_um_0.000000_0 (rotate 90) 88 -44450 0) (pin RoundRect[B]Pad_7620.000000x1270.000000_637.416000_um_0.000000_0 (rotate 90) 89 -46990 0) (pin RoundRect[T]Pad_7620.000000x1270.000000_637.416000_um_0.000000_0 (rotate 90) 90 -46990 0) (pin RoundRect[B]Pad_7620.000000x1270.000000_637.416000_um_0.000000_0 (rotate 90) 91 -49530 0) (pin RoundRect[T]Pad_7620.000000x1270.000000_637.416000_um_0.000000_0 (rotate 90) 92 -49530 0) (pin RoundRect[B]Pad_7620.000000x1270.000000_637.416000_um_0.000000_0 (rotate 90) 93 -52070 0) (pin RoundRect[T]Pad_7620.000000x1270.000000_637.416000_um_0.000000_0 (rotate 90) 94 -52070 0) (pin RoundRect[B]Pad_7620.000000x1270.000000_637.416000_um_0.000000_0 (rotate 90) 95 -54610 0) (pin RoundRect[T]Pad_7620.000000x1270.000000_637.416000_um_0.000000_0 (rotate 90) 96 -54610 0) (pin RoundRect[B]Pad_7620.000000x1270.000000_637.416000_um_0.000000_0 (rotate 90) 97 -57150 0) (pin RoundRect[T]Pad_7620.000000x1270.000000_637.416000_um_0.000000_0 (rotate 90) 98 -57150 0) (pin RoundRect[B]Pad_7620.000000x1270.000000_637.416000_um_0.000000_0 (rotate 90) 99 -59690 0) (pin RoundRect[T]Pad_7620.000000x1270.000000_637.416000_um_0.000000_0 (rotate 90) 100 -59690 0) ) (image "ZORRO-LAN-IDE-CP-V2F:C1206K" (outline (path signal 101.6 -1525 750 1525 750)) (outline (path signal 101.6 1525 -750 -1525 -750)) (pin Rect[T]Pad_1500.000000x2000.000000_um 1 -1500 0) (pin Rect[T]Pad_1500.000000x2000.000000_um 2 1500 0) ) (image "ZORRO-LAN-IDE-CP-V2F:R0805" (outline (path signal 50.8 1973 -983 -1973 -983)) (outline (path signal 50.8 1973 983 1973 -983)) (outline (path signal 50.8 -1973 -983 -1973 983)) (outline (path signal 50.8 -1973 983 1973 983)) (outline (path signal 152.4 -410 -635 410 -635)) (outline (path signal 152.4 -410 635 410 635)) (pin Rect[T]Pad_1300.000000x1500.000000_um 1 -950 0) (pin Rect[T]Pad_1300.000000x1500.000000_um 2 950 0) ) (image "ZORRO-LAN-IDE-CP-V2F:R0603::3" (outline (path signal 50.8 -1473 -983 -1473 983)) (outline (path signal 50.8 1473 -983 -1473 -983)) (outline (path signal 50.8 -1473 983 1473 983)) (outline (path signal 50.8 1473 983 1473 -983)) (outline (path signal 152.4 -432 -356 432 -356)) (outline (path signal 152.4 432 356 -432 356)) (pin Rect[T]Pad_1000.000000x1100.000000_um 1 -850 0) (pin Rect[T]Pad_1000.000000x1100.000000_um 2 850 0) ) (image "ZORRO-LAN-IDE-CP-V2F:TQFP144" (outline (path signal 152.4 9873 -9873 -9123 -9873)) (outline (path signal 152.4 -9123 -9873 -9873 -9123)) (outline (path signal 152.4 9873 9873 9873 -9873)) (outline (path signal 152.4 -9873 -9123 -9873 9873)) (outline (path signal 152.4 -9873 9873 9873 9873)) (outline (path signal 152.4 -8707.11 -7292.89 -8555.57 -7168.53 -8382.68 -7076.12 -8195.09 -7019.21 -8000 -7000 -7804.91 -7019.21 -7617.32 -7076.12 -7444.43 -7168.53 -7292.89 -7292.89 -7168.53 -7444.43 -7076.12 -7617.32 -7019.21 -7804.91 -7000 -8000 -7019.21 -8195.09 -7076.12 -8382.68 -7168.53 -8555.57 -7292.89 -8707.11 -7444.43 -8831.47 -7617.32 -8923.88 -7804.91 -8980.78 -8000 -9000 -8195.09 -8980.78 -8382.68 -8923.88 -8555.57 -8831.47 -8707.11 -8707.11 -8831.47 -8555.57 -8923.88 -8382.68 -8980.78 -8195.09 -9000 -8000 -8980.78 -7804.91 -8923.88 -7617.32 -8831.47 -7444.43 -8707.11 -7292.89)) (pin Rect[T]Pad_270.000000x1500.000000_um 1 -8750 -10750) (pin Rect[T]Pad_270.000000x1500.000000_um 2 -8250 -10750) (pin Rect[T]Pad_270.000000x1500.000000_um 3 -7750 -10750) (pin Rect[T]Pad_270.000000x1500.000000_um 4 -7250 -10750) (pin Rect[T]Pad_270.000000x1500.000000_um 5 -6750 -10750) (pin Rect[T]Pad_270.000000x1500.000000_um 6 -6250 -10750) (pin Rect[T]Pad_270.000000x1500.000000_um 7 -5750 -10750) (pin Rect[T]Pad_270.000000x1500.000000_um 8 -5250 -10750) (pin Rect[T]Pad_270.000000x1500.000000_um 9 -4750 -10750) (pin Rect[T]Pad_270.000000x1500.000000_um 10 -4250 -10750) (pin Rect[T]Pad_270.000000x1500.000000_um 11 -3750 -10750) (pin Rect[T]Pad_270.000000x1500.000000_um 12 -3250 -10750) (pin Rect[T]Pad_270.000000x1500.000000_um 13 -2750 -10750) (pin Rect[T]Pad_270.000000x1500.000000_um 14 -2250 -10750) (pin Rect[T]Pad_270.000000x1500.000000_um 15 -1750 -10750) (pin Rect[T]Pad_270.000000x1500.000000_um 16 -1250 -10750) (pin Rect[T]Pad_270.000000x1500.000000_um 17 -750 -10750) (pin Rect[T]Pad_270.000000x1500.000000_um 18 -250 -10750) (pin Rect[T]Pad_270.000000x1500.000000_um 19 250 -10750) (pin Rect[T]Pad_270.000000x1500.000000_um 20 750 -10750) (pin Rect[T]Pad_270.000000x1500.000000_um 21 1250 -10750) (pin Rect[T]Pad_270.000000x1500.000000_um 22 1750 -10750) (pin Rect[T]Pad_270.000000x1500.000000_um 23 2250 -10750) (pin Rect[T]Pad_270.000000x1500.000000_um 24 2750 -10750) (pin Rect[T]Pad_270.000000x1500.000000_um 25 3250 -10750) (pin Rect[T]Pad_270.000000x1500.000000_um 26 3750 -10750) (pin Rect[T]Pad_270.000000x1500.000000_um 27 4250 -10750) (pin Rect[T]Pad_270.000000x1500.000000_um 28 4750 -10750) (pin Rect[T]Pad_270.000000x1500.000000_um 29 5250 -10750) (pin Rect[T]Pad_270.000000x1500.000000_um 30 5750 -10750) (pin Rect[T]Pad_270.000000x1500.000000_um 31 6250 -10750) (pin Rect[T]Pad_270.000000x1500.000000_um 32 6750 -10750) (pin Rect[T]Pad_270.000000x1500.000000_um 33 7250 -10750) (pin Rect[T]Pad_270.000000x1500.000000_um 34 7750 -10750) (pin Rect[T]Pad_270.000000x1500.000000_um 35 8250 -10750) (pin Rect[T]Pad_270.000000x1500.000000_um 36 8750 -10750) (pin Rect[T]Pad_1500.000000x270.000000_um 37 10750 -8750) (pin Rect[T]Pad_1500.000000x270.000000_um 38 10750 -8250) (pin Rect[T]Pad_1500.000000x270.000000_um 39 10750 -7750) (pin Rect[T]Pad_1500.000000x270.000000_um 40 10750 -7250) (pin Rect[T]Pad_1500.000000x270.000000_um 41 10750 -6750) (pin Rect[T]Pad_1500.000000x270.000000_um 42 10750 -6250) (pin Rect[T]Pad_1500.000000x270.000000_um 43 10750 -5750) (pin Rect[T]Pad_1500.000000x270.000000_um 44 10750 -5250) (pin Rect[T]Pad_1500.000000x270.000000_um 45 10750 -4750) (pin Rect[T]Pad_1500.000000x270.000000_um 46 10750 -4250) (pin Rect[T]Pad_1500.000000x270.000000_um 47 10750 -3750) (pin Rect[T]Pad_1500.000000x270.000000_um 48 10750 -3250) (pin Rect[T]Pad_1500.000000x270.000000_um 49 10750 -2750) (pin Rect[T]Pad_1500.000000x270.000000_um 50 10750 -2250) (pin Rect[T]Pad_1500.000000x270.000000_um 51 10750 -1750) (pin Rect[T]Pad_1500.000000x270.000000_um 52 10750 -1250) (pin Rect[T]Pad_1500.000000x270.000000_um 53 10750 -750) (pin Rect[T]Pad_1500.000000x270.000000_um 54 10750 -250) (pin Rect[T]Pad_1500.000000x270.000000_um 55 10750 250) (pin Rect[T]Pad_1500.000000x270.000000_um 56 10750 750) (pin Rect[T]Pad_1500.000000x270.000000_um 57 10750 1250) (pin Rect[T]Pad_1500.000000x270.000000_um 58 10750 1750) (pin Rect[T]Pad_1500.000000x270.000000_um 59 10750 2250) (pin Rect[T]Pad_1500.000000x270.000000_um 60 10750 2750) (pin Rect[T]Pad_1500.000000x270.000000_um 61 10750 3250) (pin Rect[T]Pad_1500.000000x270.000000_um 62 10750 3750) (pin Rect[T]Pad_1500.000000x270.000000_um 63 10750 4250) (pin Rect[T]Pad_1500.000000x270.000000_um 64 10750 4750) (pin Rect[T]Pad_1500.000000x270.000000_um 65 10750 5250) (pin Rect[T]Pad_1500.000000x270.000000_um 66 10750 5750) (pin Rect[T]Pad_1500.000000x270.000000_um 67 10750 6250) (pin Rect[T]Pad_1500.000000x270.000000_um 68 10750 6750) (pin Rect[T]Pad_1500.000000x270.000000_um 69 10750 7250) (pin Rect[T]Pad_1500.000000x270.000000_um 70 10750 7750) (pin Rect[T]Pad_1500.000000x270.000000_um 71 10750 8250) (pin Rect[T]Pad_1500.000000x270.000000_um 72 10750 8750) (pin Rect[T]Pad_270.000000x1500.000000_um 73 8750 10750) (pin Rect[T]Pad_270.000000x1500.000000_um 74 8250 10750) (pin Rect[T]Pad_270.000000x1500.000000_um 75 7750 10750) (pin Rect[T]Pad_270.000000x1500.000000_um 76 7250 10750) (pin Rect[T]Pad_270.000000x1500.000000_um 77 6750 10750) (pin Rect[T]Pad_270.000000x1500.000000_um 78 6250 10750) (pin Rect[T]Pad_270.000000x1500.000000_um 79 5750 10750) (pin Rect[T]Pad_270.000000x1500.000000_um 80 5250 10750) (pin Rect[T]Pad_270.000000x1500.000000_um 81 4750 10750) (pin Rect[T]Pad_270.000000x1500.000000_um 82 4250 10750) (pin Rect[T]Pad_270.000000x1500.000000_um 83 3750 10750) (pin Rect[T]Pad_270.000000x1500.000000_um 84 3250 10750) (pin Rect[T]Pad_270.000000x1500.000000_um 85 2750 10750) (pin Rect[T]Pad_270.000000x1500.000000_um 86 2250 10750) (pin Rect[T]Pad_270.000000x1500.000000_um 87 1750 10750) (pin Rect[T]Pad_270.000000x1500.000000_um 88 1250 10750) (pin Rect[T]Pad_270.000000x1500.000000_um 89 750 10750) (pin Rect[T]Pad_270.000000x1500.000000_um 90 250 10750) (pin Rect[T]Pad_270.000000x1500.000000_um 91 -250 10750) (pin Rect[T]Pad_270.000000x1500.000000_um 92 -750 10750) (pin Rect[T]Pad_270.000000x1500.000000_um 93 -1250 10750) (pin Rect[T]Pad_270.000000x1500.000000_um 94 -1750 10750) (pin Rect[T]Pad_270.000000x1500.000000_um 95 -2250 10750) (pin Rect[T]Pad_270.000000x1500.000000_um 96 -2750 10750) (pin Rect[T]Pad_270.000000x1500.000000_um 97 -3250 10750) (pin Rect[T]Pad_270.000000x1500.000000_um 98 -3750 10750) (pin Rect[T]Pad_270.000000x1500.000000_um 99 -4250 10750) (pin Rect[T]Pad_270.000000x1500.000000_um 100 -4750 10750) (pin Rect[T]Pad_270.000000x1500.000000_um 101 -5250 10750) (pin Rect[T]Pad_270.000000x1500.000000_um 102 -5750 10750) (pin Rect[T]Pad_270.000000x1500.000000_um 103 -6250 10750) (pin Rect[T]Pad_270.000000x1500.000000_um 104 -6750 10750) (pin Rect[T]Pad_270.000000x1500.000000_um 105 -7250 10750) (pin Rect[T]Pad_270.000000x1500.000000_um 106 -7750 10750) (pin Rect[T]Pad_270.000000x1500.000000_um 107 -8250 10750) (pin Rect[T]Pad_270.000000x1500.000000_um 108 -8750 10750) (pin Rect[T]Pad_1500.000000x270.000000_um 109 -10750 8750) (pin Rect[T]Pad_1500.000000x270.000000_um 110 -10750 8250) (pin Rect[T]Pad_1500.000000x270.000000_um 111 -10750 7750) (pin Rect[T]Pad_1500.000000x270.000000_um 112 -10750 7250) (pin Rect[T]Pad_1500.000000x270.000000_um 113 -10750 6750) (pin Rect[T]Pad_1500.000000x270.000000_um 114 -10750 6250) (pin Rect[T]Pad_1500.000000x270.000000_um 115 -10750 5750) (pin Rect[T]Pad_1500.000000x270.000000_um 116 -10750 5250) (pin Rect[T]Pad_1500.000000x270.000000_um 117 -10750 4750) (pin Rect[T]Pad_1500.000000x270.000000_um 118 -10750 4250) (pin Rect[T]Pad_1500.000000x270.000000_um 119 -10750 3750) (pin Rect[T]Pad_1500.000000x270.000000_um 120 -10750 3250) (pin Rect[T]Pad_1500.000000x270.000000_um 121 -10750 2750) (pin Rect[T]Pad_1500.000000x270.000000_um 122 -10750 2250) (pin Rect[T]Pad_1500.000000x270.000000_um 123 -10750 1750) (pin Rect[T]Pad_1500.000000x270.000000_um 124 -10750 1250) (pin Rect[T]Pad_1500.000000x270.000000_um 125 -10750 750) (pin Rect[T]Pad_1500.000000x270.000000_um 126 -10750 250) (pin Rect[T]Pad_1500.000000x270.000000_um 127 -10750 -250) (pin Rect[T]Pad_1500.000000x270.000000_um 128 -10750 -750) (pin Rect[T]Pad_1500.000000x270.000000_um 129 -10750 -1250) (pin Rect[T]Pad_1500.000000x270.000000_um 130 -10750 -1750) (pin Rect[T]Pad_1500.000000x270.000000_um 131 -10750 -2250) (pin Rect[T]Pad_1500.000000x270.000000_um 132 -10750 -2750) (pin Rect[T]Pad_1500.000000x270.000000_um 133 -10750 -3250) (pin Rect[T]Pad_1500.000000x270.000000_um 134 -10750 -3750) (pin Rect[T]Pad_1500.000000x270.000000_um 135 -10750 -4250) (pin Rect[T]Pad_1500.000000x270.000000_um 136 -10750 -4750) (pin Rect[T]Pad_1500.000000x270.000000_um 137 -10750 -5250) (pin Rect[T]Pad_1500.000000x270.000000_um 138 -10750 -5750) (pin Rect[T]Pad_1500.000000x270.000000_um 139 -10750 -6250) (pin Rect[T]Pad_1500.000000x270.000000_um 140 -10750 -6750) (pin Rect[T]Pad_1500.000000x270.000000_um 141 -10750 -7250) (pin Rect[T]Pad_1500.000000x270.000000_um 142 -10750 -7750) (pin Rect[T]Pad_1500.000000x270.000000_um 143 -10750 -8250) (pin Rect[T]Pad_1500.000000x270.000000_um 144 -10750 -8750) ) (image "ZORRO-LAN-IDE-CP-V2F:ML40" (outline (path signal 152.4 -29210 4445 -29210 -4445)) (outline (path signal 152.4 -29210 4445 -27940 4445)) (outline (path signal 152.4 -29210 -4445 -24892 -4445)) (outline (path signal 50.8 -28194 3429 -28194 -3429)) (outline (path signal 50.8 -28194 -3429 -21082 -3429)) (outline (path signal 152.4 -27940 4699 -27940 4445)) (outline (path signal 152.4 -27940 3175 -27940 -3175)) (outline (path signal 152.4 -27940 3175 27940 3175)) (outline (path signal 152.4 -26670 4699 -27940 4699)) (outline (path signal 152.4 -26670 4699 -26670 4445)) (outline (path signal 152.4 -26670 4445 -635 4445)) (outline (path signal 152.4 -24892 -4318 -24892 -4445)) (outline (path signal 152.4 -24892 -4318 -23368 -4318)) (outline (path signal 152.4 -23368 -4445 -23368 -4318)) (outline (path signal 152.4 -23368 -4445 -21971 -4445)) (outline (path signal 152.4 -21971 -4445 -21590 -3937)) (outline (path signal 152.4 -21082 -3175 -27940 -3175)) (outline (path signal 152.4 -21082 -3175 -21082 -3429)) (outline (path signal 152.4 -21082 -3429 -21082 -3937)) (outline (path signal 152.4 -21082 -3937 -21590 -3937)) (outline (path signal 152.4 -19558 -3175 -21082 -3175)) (outline (path signal 152.4 -19558 -3175 -19558 -3429)) (outline (path signal 152.4 -19558 -3429 -19558 -3937)) (outline (path signal 50.8 -19558 -3429 -2032 -3429)) (outline (path signal 152.4 -19558 -3937 -21082 -3937)) (outline (path signal 152.4 -19050 -3937 -19558 -3937)) (outline (path signal 152.4 -19050 -3937 -18669 -4445)) (outline (path signal 152.4 -18669 -4445 -2032 -4445)) (outline (path signal 152.4 -2032 -3175 -19558 -3175)) (outline (path signal 152.4 -2032 -3175 -2032 -2413)) (outline (path signal 152.4 -2032 -3175 -2032 -3429)) (outline (path signal 152.4 -2032 -3429 -2032 -4445)) (outline (path signal 152.4 -635 4699 -635 4445)) (outline (path signal 152.4 635 4699 -635 4699)) (outline (path signal 152.4 635 4699 635 4445)) (outline (path signal 152.4 635 4445 26670 4445)) (outline (path signal 152.4 2032 -2413 -2032 -2413)) (outline (path signal 152.4 2032 -2413 2032 -3175)) (outline (path signal 152.4 2032 -3175 2032 -3429)) (outline (path signal 152.4 2032 -3429 2032 -4445)) (outline (path signal 152.4 2032 -4445 -2032 -4445)) (outline (path signal 152.4 21209 -4445 2032 -4445)) (outline (path signal 152.4 21209 -4445 21590 -3937)) (outline (path signal 152.4 22098 -3175 2032 -3175)) (outline (path signal 152.4 22098 -3175 22098 -3429)) (outline (path signal 50.8 22098 -3429 2032 -3429)) (outline (path signal 152.4 22098 -3429 22098 -3937)) (outline (path signal 152.4 22098 -3937 21590 -3937)) (outline (path signal 152.4 23622 -3175 22098 -3175)) (outline (path signal 152.4 23622 -3175 23622 -3429)) (outline (path signal 152.4 23622 -3429 23622 -3937)) (outline (path signal 50.8 23622 -3429 28194 -3429)) (outline (path signal 152.4 23622 -3937 22098 -3937)) (outline (path signal 152.4 24130 -3937 23622 -3937)) (outline (path signal 152.4 24130 -3937 24511 -4445)) (outline (path signal 152.4 26670 4445 26670 4699)) (outline (path signal 152.4 27940 4699 26670 4699)) (outline (path signal 152.4 27940 4445 27940 4699)) (outline (path signal 152.4 27940 4445 29210 4445)) (outline (path signal 152.4 27940 -3175 23622 -3175)) (outline (path signal 152.4 27940 -3175 27940 3175)) (outline (path signal 50.8 28194 3429 -28194 3429)) (outline (path signal 50.8 28194 -3429 28194 3429)) (outline (path signal 152.4 29210 -4445 24511 -4445)) (outline (path signal 152.4 29210 -4445 29210 4445)) (pin RoundRect[A]Pad_1214.400000x1214.400000_304.755000_um_0.292893_F 1 -24130 -1270) (pin RoundRect[A]Pad_1214.400000x1214.400000_304.755000_um_0.292893_F 2 -24130 1270) (pin RoundRect[A]Pad_1214.400000x1214.400000_304.755000_um_0.292893_F 3 -21590 -1270) (pin RoundRect[A]Pad_1214.400000x1214.400000_304.755000_um_0.292893_F 4 -21590 1270) (pin RoundRect[A]Pad_1214.400000x1214.400000_304.755000_um_0.292893_F 5 -19050 -1270) (pin RoundRect[A]Pad_1214.400000x1214.400000_304.755000_um_0.292893_F 6 -19050 1270) (pin RoundRect[A]Pad_1214.400000x1214.400000_304.755000_um_0.292893_F 7 -16510 -1270) (pin RoundRect[A]Pad_1214.400000x1214.400000_304.755000_um_0.292893_F 8 -16510 1270) (pin RoundRect[A]Pad_1214.400000x1214.400000_304.755000_um_0.292893_F 9 -13970 -1270) (pin RoundRect[A]Pad_1214.400000x1214.400000_304.755000_um_0.292893_F 10 -13970 1270) (pin RoundRect[A]Pad_1214.400000x1214.400000_304.755000_um_0.292893_F 11 -11430 -1270) (pin RoundRect[A]Pad_1214.400000x1214.400000_304.755000_um_0.292893_F 12 -11430 1270) (pin RoundRect[A]Pad_1214.400000x1214.400000_304.755000_um_0.292893_F 13 -8890 -1270) (pin RoundRect[A]Pad_1214.400000x1214.400000_304.755000_um_0.292893_F 14 -8890 1270) (pin RoundRect[A]Pad_1214.400000x1214.400000_304.755000_um_0.292893_F 15 -6350 -1270) (pin RoundRect[A]Pad_1214.400000x1214.400000_304.755000_um_0.292893_F 16 -6350 1270) (pin RoundRect[A]Pad_1214.400000x1214.400000_304.755000_um_0.292893_F 17 -3810 -1270) (pin RoundRect[A]Pad_1214.400000x1214.400000_304.755000_um_0.292893_F 18 -3810 1270) (pin RoundRect[A]Pad_1214.400000x1214.400000_304.755000_um_0.292893_F 19 -1270 -1270) (pin RoundRect[A]Pad_1214.400000x1214.400000_304.755000_um_0.292893_F 20 -1270 1270) (pin RoundRect[A]Pad_1214.400000x1214.400000_304.755000_um_0.292893_F 21 1270 -1270) (pin RoundRect[A]Pad_1214.400000x1214.400000_304.755000_um_0.292893_F 22 1270 1270) (pin RoundRect[A]Pad_1214.400000x1214.400000_304.755000_um_0.292893_F 23 3810 -1270) (pin RoundRect[A]Pad_1214.400000x1214.400000_304.755000_um_0.292893_F 24 3810 1270) (pin RoundRect[A]Pad_1214.400000x1214.400000_304.755000_um_0.292893_F 25 6350 -1270) (pin RoundRect[A]Pad_1214.400000x1214.400000_304.755000_um_0.292893_F 26 6350 1270) (pin RoundRect[A]Pad_1214.400000x1214.400000_304.755000_um_0.292893_F 27 8890 -1270) (pin RoundRect[A]Pad_1214.400000x1214.400000_304.755000_um_0.292893_F 28 8890 1270) (pin RoundRect[A]Pad_1214.400000x1214.400000_304.755000_um_0.292893_F 29 11430 -1270) (pin RoundRect[A]Pad_1214.400000x1214.400000_304.755000_um_0.292893_F 30 11430 1270) (pin RoundRect[A]Pad_1214.400000x1214.400000_304.755000_um_0.292893_F 31 13970 -1270) (pin RoundRect[A]Pad_1214.400000x1214.400000_304.755000_um_0.292893_F 32 13970 1270) (pin RoundRect[A]Pad_1214.400000x1214.400000_304.755000_um_0.292893_F 33 16510 -1270) (pin RoundRect[A]Pad_1214.400000x1214.400000_304.755000_um_0.292893_F 34 16510 1270) (pin RoundRect[A]Pad_1214.400000x1214.400000_304.755000_um_0.292893_F 35 19050 -1270) (pin RoundRect[A]Pad_1214.400000x1214.400000_304.755000_um_0.292893_F 36 19050 1270) (pin RoundRect[A]Pad_1214.400000x1214.400000_304.755000_um_0.292893_F 37 21590 -1270) (pin RoundRect[A]Pad_1214.400000x1214.400000_304.755000_um_0.292893_F 38 21590 1270) (pin RoundRect[A]Pad_1214.400000x1214.400000_304.755000_um_0.292893_F 39 24130 -1270) (pin RoundRect[A]Pad_1214.400000x1214.400000_304.755000_um_0.292893_F 40 24130 1270) ) (image "ZORRO-LAN-IDE-CP-V2F:DPACK" (outline (path signal 203.2 3276.6 3835.4 3277 -2159)) (outline (path signal 203.2 3277 -2159 -3277 -2159)) (outline (path signal 203.2 -3277 -2159 -3276.6 3835.4)) (outline (path signal 203.2 2108.2 5105.4 2565.4 4648.2)) (outline (path signal 203.2 -2108.2 5105.4 2108.2 5105.4)) (outline (path signal 203.2 2565.4 4648.2 2565.4 3937)) (outline (path signal 203.2 -2565.4 4648.2 -2108.2 5105.4)) (outline (path signal 203.2 2565.4 3937 -2565.4 3937)) (outline (path signal 203.2 -2565.4 3937 -2565.4 4648.2)) (outline (path signal 203.2 -3277 3835 3277.4 3834.6)) (pin Rect[T]Pad_1600.000000x3000.000000_um 1 -2280 -4800) (pin Rect[T]Pad_1600.000000x3000.000000_um 3 2280 -4800) (pin Rect[T]Pad_5800.000000x6200.000000_um 4 0 2380) ) (image "ZORRO-LAN-IDE-CP-V2F:JP1::2" (outline (path signal 152.4 1270 -254 1270 -2286)) (outline (path signal 152.4 1270 2286 1270 254)) (outline (path signal 152.4 1270 2286 1016 2540)) (outline (path signal 152.4 1016 -2540 1270 -2286)) (outline (path signal 152.4 1016 0 1270 -254)) (outline (path signal 152.4 1016 0 1270 254)) (outline (path signal 152.4 1016 2540 -1016 2540)) (outline (path signal 152.4 -1016 -2540 1016 -2540)) (outline (path signal 152.4 -1016 -2540 -1270 -2286)) (outline (path signal 152.4 -1016 0 -1270 -254)) (outline (path signal 152.4 -1016 0 -1270 254)) (outline (path signal 152.4 -1270 -254 -1270 -2286)) (outline (path signal 152.4 -1270 2286 -1016 2540)) (outline (path signal 152.4 -1270 2286 -1270 254)) (pin Oval[A]Pad_2428.800000x1214.400000_um 1 0 -1270) (pin Oval[A]Pad_2428.800000x1214.400000_um 2 0 1270) ) (image "ZORRO-LAN-IDE-CP-V2F:CAY16" (outline (path signal 101.6 1550 750 1550 -750)) (outline (path signal 101.6 1000 750 1550 750)) (outline (path signal 101.6 200 750 600 750)) (outline (path signal 101.6 -600 750 -200 750)) (outline (path signal 101.6 -1550 750 -1000 750)) (outline (path signal 101.6 1550 -750 1000 -750)) (outline (path signal 101.6 600 -750 200 -750)) (outline (path signal 101.6 -200 -750 -600 -750)) (outline (path signal 101.6 -1000 -750 -1550 -750)) (outline (path signal 101.6 -1550 -750 -1550 750)) (outline (polygon signal 0 949.2 750 958.902 779.859 984.302 798.314 1015.7 798.314 1041.1 779.859 1050.8 750 1035.67 664.221 992.124 588.789 925.4 532.801 843.551 503.01 756.449 503.01 674.6 532.801 607.876 588.789 564.325 664.221 549.2 750 558.902 779.859 584.302 798.314 615.698 798.314 641.098 779.859 650.8 750 650.8 715.946 680.351 654.583 733.6 612.118 800 596.963 866.4 612.118 919.649 654.583 949.2 715.946 949.2 750)) (outline (polygon signal 0 149.2 750 158.902 779.859 184.302 798.314 215.698 798.314 241.098 779.859 250.8 750 235.675 664.221 192.124 588.789 125.4 532.801 43.551 503.01 -43.551 503.01 -125.4 532.801 -192.124 588.789 -235.675 664.221 -250.8 750 -241.098 779.859 -215.698 798.314 -184.302 798.314 -158.902 779.859 -149.2 750 -149.2 715.946 -119.649 654.583 -66.4 612.118 0 596.963 66.4 612.118 119.649 654.583 149.2 715.946 149.2 750)) (outline (polygon signal 0 -650.8 750 -641.098 779.859 -615.698 798.314 -584.302 798.314 -558.902 779.859 -549.2 750 -564.325 664.221 -607.876 588.789 -674.6 532.801 -756.449 503.01 -843.551 503.01 -925.4 532.801 -992.124 588.789 -1035.67 664.221 -1050.8 750 -1041.1 779.859 -1015.7 798.314 -984.302 798.314 -958.902 779.859 -949.2 750 -949.2 715.946 -919.649 654.583 -866.4 612.118 -800 596.963 -733.6 612.118 -680.351 654.583 -650.8 715.946 -650.8 750)) (outline (polygon signal 0 650.8 -750 641.098 -779.859 615.698 -798.314 584.302 -798.314 558.902 -779.859 549.2 -750 564.325 -664.221 607.876 -588.789 674.6 -532.801 756.449 -503.01 843.551 -503.01 925.4 -532.801 992.124 -588.789 1035.67 -664.221 1050.8 -750 1041.1 -779.859 1015.7 -798.314 984.302 -798.314 958.902 -779.859 949.2 -750 949.2 -715.946 919.649 -654.583 866.4 -612.118 800 -596.963 733.6 -612.118 680.351 -654.583 650.8 -715.946 650.8 -750)) (outline (polygon signal 0 -149.2 -750 -158.902 -779.859 -184.302 -798.314 -215.698 -798.314 -241.098 -779.859 -250.8 -750 -235.675 -664.221 -192.124 -588.789 -125.4 -532.801 -43.551 -503.01 43.551 -503.01 125.4 -532.801 192.124 -588.789 235.675 -664.221 250.8 -750 241.098 -779.859 215.698 -798.314 184.302 -798.314 158.902 -779.859 149.2 -750 149.2 -715.946 119.649 -654.583 66.4 -612.118 0 -596.963 -66.4 -612.118 -119.649 -654.583 -149.2 -715.946 -149.2 -750)) (outline (polygon signal 0 -949.2 -750 -958.902 -779.859 -984.302 -798.314 -1015.7 -798.314 -1041.1 -779.859 -1050.8 -750 -1035.67 -664.221 -992.124 -588.789 -925.4 -532.801 -843.551 -503.01 -756.449 -503.01 -674.6 -532.801 -607.876 -588.789 -564.325 -664.221 -549.2 -750 -558.902 -779.859 -584.302 -798.314 -615.698 -798.314 -641.098 -779.859 -650.8 -750 -650.8 -715.946 -680.351 -654.583 -733.6 -612.118 -800 -596.963 -866.4 -612.118 -919.649 -654.583 -949.2 -715.946 -949.2 -750)) (pin Rect[T]Pad_500.000000x650.000000_um 1 -1200 -675) (pin Rect[T]Pad_500.000000x650.000000_um 2 -400 -675) (pin Rect[T]Pad_500.000000x650.000000_um 3 400 -675) (pin Rect[T]Pad_500.000000x650.000000_um 4 1200 -675) (pin Rect[T]Pad_500.000000x650.000000_um 5 1200 675) (pin Rect[T]Pad_500.000000x650.000000_um 6 400 675) (pin Rect[T]Pad_500.000000x650.000000_um 7 -400 675) (pin Rect[T]Pad_500.000000x650.000000_um 8 -1200 675) ) (image "ZORRO-LAN-IDE-CP-V2F:C1210K" (outline (path signal 101.6 -1525 1175 1525 1175)) (outline (path signal 101.6 1525 -1175 -1525 -1175)) (pin Rect[T]Pad_1500.000000x2900.000000_um 1 -1500 0) (pin Rect[T]Pad_1500.000000x2900.000000_um 2 1500 0) ) (image "ZORRO-LAN-IDE-CP-V2F:R2512" (outline (path signal 50.8 3973 -1983 -3973 -1983)) (outline (path signal 50.8 3973 1983 3973 -1983)) (outline (path signal 50.8 -3973 -1983 -3973 1983)) (outline (path signal 50.8 -3973 1983 3973 1983)) (outline (path signal 152.4 -2362 -1473 2387 -1473)) (outline (path signal 152.4 -2362 1473 2387 1473)) (pin Rect[T]Pad_1800.000000x3200.000000_um 1 -2800 0) (pin Rect[T]Pad_1800.000000x3200.000000_um 2 2800 0) ) (image "TSSOP-24_4.4x7.8mm_P0.65mm" (outline (path signal 120 -2310 4035 2310 4035)) (outline (path signal 120 2310 -4035 -2310 -4035)) (outline (path signal 50 -3850 4030 -2450 4030)) (outline (path signal 50 -3850 -4030 -3850 4030)) (outline (path signal 50 -2450 4150 2450 4150)) (outline (path signal 50 -2450 4030 -2450 4150)) (outline (path signal 50 -2450 -4030 -3850 -4030)) (outline (path signal 50 -2450 -4150 -2450 -4030)) (outline (path signal 50 2450 4150 2450 4030)) (outline (path signal 50 2450 4030 3850 4030)) (outline (path signal 50 2450 -4030 2450 -4150)) (outline (path signal 50 2450 -4150 -2450 -4150)) (outline (path signal 50 3850 4030 3850 -4030)) (outline (path signal 50 3850 -4030 2450 -4030)) (pin RoundRect[T]Pad_1475.000000x400.000000_100.381000_um_0.000000_0 1 -2862.5 3575) (pin RoundRect[T]Pad_1475.000000x400.000000_100.381000_um_0.000000_0 2 -2862.5 2925) (pin RoundRect[T]Pad_1475.000000x400.000000_100.381000_um_0.000000_0 3 -2862.5 2275) (pin RoundRect[T]Pad_1475.000000x400.000000_100.381000_um_0.000000_0 4 -2862.5 1625) (pin RoundRect[T]Pad_1475.000000x400.000000_100.381000_um_0.000000_0 5 -2862.5 975) (pin RoundRect[T]Pad_1475.000000x400.000000_100.381000_um_0.000000_0 6 -2862.5 325) (pin RoundRect[T]Pad_1475.000000x400.000000_100.381000_um_0.000000_0 7 -2862.5 -325) (pin RoundRect[T]Pad_1475.000000x400.000000_100.381000_um_0.000000_0 8 -2862.5 -975) (pin RoundRect[T]Pad_1475.000000x400.000000_100.381000_um_0.000000_0 9 -2862.5 -1625) (pin RoundRect[T]Pad_1475.000000x400.000000_100.381000_um_0.000000_0 10 -2862.5 -2275) (pin RoundRect[T]Pad_1475.000000x400.000000_100.381000_um_0.000000_0 11 -2862.5 -2925) (pin RoundRect[T]Pad_1475.000000x400.000000_100.381000_um_0.000000_0 12 -2862.5 -3575) (pin RoundRect[T]Pad_1475.000000x400.000000_100.381000_um_0.000000_0 13 2862.5 -3575) (pin RoundRect[T]Pad_1475.000000x400.000000_100.381000_um_0.000000_0 14 2862.5 -2925) (pin RoundRect[T]Pad_1475.000000x400.000000_100.381000_um_0.000000_0 15 2862.5 -2275) (pin RoundRect[T]Pad_1475.000000x400.000000_100.381000_um_0.000000_0 16 2862.5 -1625) (pin RoundRect[T]Pad_1475.000000x400.000000_100.381000_um_0.000000_0 17 2862.5 -975) (pin RoundRect[T]Pad_1475.000000x400.000000_100.381000_um_0.000000_0 18 2862.5 -325) (pin RoundRect[T]Pad_1475.000000x400.000000_100.381000_um_0.000000_0 19 2862.5 325) (pin RoundRect[T]Pad_1475.000000x400.000000_100.381000_um_0.000000_0 20 2862.5 975) (pin RoundRect[T]Pad_1475.000000x400.000000_100.381000_um_0.000000_0 21 2862.5 1625) (pin RoundRect[T]Pad_1475.000000x400.000000_100.381000_um_0.000000_0 22 2862.5 2275) (pin RoundRect[T]Pad_1475.000000x400.000000_100.381000_um_0.000000_0 23 2862.5 2925) (pin RoundRect[T]Pad_1475.000000x400.000000_100.381000_um_0.000000_0 24 2862.5 3575) ) (image "ZORRO-LAN-IDE-CP-V2F:C0805K::1" (outline (path signal 101.6 925 -600 -925 -600)) (outline (path signal 101.6 -925 600 925 600)) (pin Rect[T]Pad_1300.000000x1600.000000_um 1 -1000 0) (pin Rect[T]Pad_1300.000000x1600.000000_um 2 1000 0) ) (image "ZORRO-LAN-IDE-CP-V2F:C0603K::1" (outline (path signal 101.6 -725 350 725 350)) (outline (path signal 101.6 725 -350 -725 -350)) (pin Rect[T]Pad_1050.000000x1080.000000_um 1 -875 -0.001) (pin Rect[T]Pad_1050.000000x1080.000000_um 2 875 0.001) ) (image "TSSOP-24_4.4x7.8mm_P0.65mm::1" (outline (path signal 120 -2310 4035 2310 4035)) (outline (path signal 120 2310 -4035 -2310 -4035)) (outline (path signal 50 -3850 -4030 -3850 4030)) (outline (path signal 50 -3850 4030 -2450 4030)) (outline (path signal 50 -2450 -4150 -2450 -4030)) (outline (path signal 50 -2450 -4030 -3850 -4030)) (outline (path signal 50 -2450 4030 -2450 4150)) (outline (path signal 50 -2450 4150 2450 4150)) (outline (path signal 50 2450 -4150 -2450 -4150)) (outline (path signal 50 2450 -4030 2450 -4150)) (outline (path signal 50 2450 4030 3850 4030)) (outline (path signal 50 2450 4150 2450 4030)) (outline (path signal 50 3850 -4030 2450 -4030)) (outline (path signal 50 3850 4030 3850 -4030)) (pin RoundRect[T]Pad_1475.000000x400.000000_100.381000_um_0.000000_0 1 -2862.5 3575) (pin RoundRect[T]Pad_1475.000000x400.000000_100.381000_um_0.000000_0 2 -2862.5 2925) (pin RoundRect[T]Pad_1475.000000x400.000000_100.381000_um_0.000000_0 3 -2862.5 2275) (pin RoundRect[T]Pad_1475.000000x400.000000_100.381000_um_0.000000_0 4 -2862.5 1625) (pin RoundRect[T]Pad_1475.000000x400.000000_100.381000_um_0.000000_0 5 -2862.5 975) (pin RoundRect[T]Pad_1475.000000x400.000000_100.381000_um_0.000000_0 6 -2862.5 325) (pin RoundRect[T]Pad_1475.000000x400.000000_100.381000_um_0.000000_0 7 -2862.5 -325) (pin RoundRect[T]Pad_1475.000000x400.000000_100.381000_um_0.000000_0 8 -2862.5 -975) (pin RoundRect[T]Pad_1475.000000x400.000000_100.381000_um_0.000000_0 9 -2862.5 -1625) (pin RoundRect[T]Pad_1475.000000x400.000000_100.381000_um_0.000000_0 10 -2862.5 -2275) (pin RoundRect[T]Pad_1475.000000x400.000000_100.381000_um_0.000000_0 11 -2862.5 -2925) (pin RoundRect[T]Pad_1475.000000x400.000000_100.381000_um_0.000000_0 12 -2862.5 -3575) (pin RoundRect[T]Pad_1475.000000x400.000000_100.381000_um_0.000000_0 13 2862.5 -3575) (pin RoundRect[T]Pad_1475.000000x400.000000_100.381000_um_0.000000_0 14 2862.5 -2925) (pin RoundRect[T]Pad_1475.000000x400.000000_100.381000_um_0.000000_0 15 2862.5 -2275) (pin RoundRect[T]Pad_1475.000000x400.000000_100.381000_um_0.000000_0 16 2862.5 -1625) (pin RoundRect[T]Pad_1475.000000x400.000000_100.381000_um_0.000000_0 17 2862.5 -975) (pin RoundRect[T]Pad_1475.000000x400.000000_100.381000_um_0.000000_0 18 2862.5 -325) (pin RoundRect[T]Pad_1475.000000x400.000000_100.381000_um_0.000000_0 19 2862.5 325) (pin RoundRect[T]Pad_1475.000000x400.000000_100.381000_um_0.000000_0 20 2862.5 975) (pin RoundRect[T]Pad_1475.000000x400.000000_100.381000_um_0.000000_0 21 2862.5 1625) (pin RoundRect[T]Pad_1475.000000x400.000000_100.381000_um_0.000000_0 22 2862.5 2275) (pin RoundRect[T]Pad_1475.000000x400.000000_100.381000_um_0.000000_0 23 2862.5 2925) (pin RoundRect[T]Pad_1475.000000x400.000000_100.381000_um_0.000000_0 24 2862.5 3575) ) (image "ZORRO-LAN-IDE-CP-V2F:C0603K::2" (outline (path signal 101.6 725 -350 -725 -350)) (outline (path signal 101.6 -725 350 725 350)) (pin Rect[T]Pad_1050.000000x1080.000000_um 1 -875 -0.001) (pin Rect[T]Pad_1050.000000x1080.000000_um 2 875 0.001) ) (image "ZORRO-LAN-IDE-CP-V2F:C0603K::3" (outline (path signal 101.6 -725 350 725 350)) (outline (path signal 101.6 725 -350 -725 -350)) (pin Rect[T]Pad_1050.000000x1080.000000_um 1 -875 0) (pin Rect[T]Pad_1050.000000x1080.000000_um 2 875 0) ) (image "ZORRO-LAN-IDE-CP-V2F:C0603K::4" (outline (path signal 101.6 -725 350 725 350)) (outline (path signal 101.6 725 -350 -725 -350)) (pin Rect[T]Pad_1050.000000x1080.000000_um (rotate 2.13163e-14) 1 -875 0) (pin Rect[T]Pad_1050.000000x1080.000000_um (rotate 2.13163e-14) 2 875 0) ) (padstack Round[A]Pad_1600.200000_um (shape (circle F.Cu 1600.2)) (shape (circle In1.Cu 1600.2)) (shape (circle In2.Cu 1600.2)) (shape (circle B.Cu 1600.2)) (attach off) ) (padstack Oval[A]Pad_2428.800000x1214.400000_um (shape (path F.Cu 1214.4 -607.2 0 607.2 0)) (shape (path In1.Cu 1214.4 -607.2 0 607.2 0)) (shape (path In2.Cu 1214.4 -607.2 0 607.2 0)) (shape (path B.Cu 1214.4 -607.2 0 607.2 0)) (attach off) ) (padstack Oval[A]Pad_1500.000000x1500.000000_um (shape (path F.Cu 1500 0 0 0 0)) (shape (path In1.Cu 1500 0 0 0 0)) (shape (path In2.Cu 1500 0 0 0 0)) (shape (path B.Cu 1500 0 0 0 0)) (attach off) ) (padstack Oval[A]Pad_1700.000000x1700.000000_um (shape (path F.Cu 1700 0 0 0 0)) (shape (path In1.Cu 1700 0 0 0 0)) (shape (path In2.Cu 1700 0 0 0 0)) (shape (path B.Cu 1700 0 0 0 0)) (attach off) ) (padstack Oval[A]Pad_1800.000000x1800.000000_um (shape (path F.Cu 1800 0 0 0 0)) (shape (path In1.Cu 1800 0 0 0 0)) (shape (path In2.Cu 1800 0 0 0 0)) (shape (path B.Cu 1800 0 0 0 0)) (attach off) ) (padstack RoundRect[B]Pad_7620.000000x1270.000000_637.416000_um_0.000000_0 (shape (polygon B.Cu 0 -3812.42 0 -3804.57 99.714 -3759.99 253.148 -3678.66 390.677 -3565.68 503.657 -3428.15 584.991 -3274.71 629.568 -3175 637.416 3175 637.416 3274.71 629.568 3428.15 584.991 3565.68 503.657 3678.66 390.677 3759.99 253.148 3804.57 99.714 3812.42 0 3804.57 -99.714 3759.99 -253.148 3678.66 -390.677 3565.68 -503.657 3428.15 -584.991 3274.71 -629.568 3175 -637.416 -3175 -637.416 -3274.71 -629.568 -3428.15 -584.991 -3565.68 -503.657 -3678.66 -390.677 -3759.99 -253.148 -3804.57 -99.714 -3812.42 0 -3812.42 0)) (attach off) ) (padstack RoundRect[T]Pad_7620.000000x1270.000000_637.416000_um_0.000000_0 (shape (polygon F.Cu 0 -3812.42 0 -3804.57 99.714 -3759.99 253.148 -3678.66 390.677 -3565.68 503.657 -3428.15 584.991 -3274.71 629.568 -3175 637.416 3175 637.416 3274.71 629.568 3428.15 584.991 3565.68 503.657 3678.66 390.677 3759.99 253.148 3804.57 99.714 3812.42 0 3804.57 -99.714 3759.99 -253.148 3678.66 -390.677 3565.68 -503.657 3428.15 -584.991 3274.71 -629.568 3175 -637.416 -3175 -637.416 -3274.71 -629.568 -3428.15 -584.991 -3565.68 -503.657 -3678.66 -390.677 -3759.99 -253.148 -3804.57 -99.714 -3812.42 0 -3812.42 0)) (attach off) ) (padstack RoundRect[A]Pad_1214.400000x1214.400000_304.755000_um_0.292893_F (shape (polygon F.Cu 0 -608.355 251.989 -251.989 608.355 251.989 608.355 608.355 251.989 608.355 -251.989 251.989 -608.355 -251.989 -608.355 -608.355 -251.989 -608.355 251.989)) (shape (polygon In1.Cu 0 -608.355 251.989 -251.989 608.355 251.989 608.355 608.355 251.989 608.355 -251.989 251.989 -608.355 -251.989 -608.355 -608.355 -251.989 -608.355 251.989)) (shape (polygon In2.Cu 0 -608.355 251.989 -251.989 608.355 251.989 608.355 608.355 251.989 608.355 -251.989 251.989 -608.355 -251.989 -608.355 -608.355 -251.989 -608.355 251.989)) (shape (polygon B.Cu 0 -608.355 251.989 -251.989 608.355 251.989 608.355 608.355 251.989 608.355 -251.989 251.989 -608.355 -251.989 -608.355 -608.355 -251.989 -608.355 251.989)) (attach off) ) (padstack RoundRect[T]Pad_1475.000000x400.000000_100.381000_um_0.000000_0 (shape (polygon F.Cu 0 -737.881 100 -730.24 138.414 -708.48 170.98 -675.914 192.74 -637.499 200.38 637.5 200.381 675.914 192.74 708.48 170.98 730.24 138.414 737.88 99.999 737.881 -100 730.24 -138.414 708.48 -170.98 675.914 -192.74 637.499 -200.38 -637.5 -200.381 -675.914 -192.74 -708.48 -170.98 -730.24 -138.414 -737.88 -99.999 -737.881 100)) (attach off) ) (padstack RoundRect[T]Pad_1475.000000x600.000000_150.571000_um_0.000000_0 (shape (polygon F.Cu 0 -738.071 150 -726.609 207.621 -693.97 256.47 -645.121 289.109 -587.499 300.57 587.5 300.571 645.121 289.109 693.97 256.47 726.609 207.621 738.07 149.999 738.071 -150 726.609 -207.621 693.97 -256.47 645.121 -289.109 587.499 -300.57 -587.5 -300.571 -645.121 -289.109 -693.97 -256.47 -726.609 -207.621 -738.07 -149.999 -738.071 150)) (attach off) ) (padstack RoundRect[A]Pad_1600.200000x1600.200000_401.572000_um_0.292893_F (shape (polygon F.Cu 0 -801.622 332.043 -332.043 801.622 332.043 801.622 801.622 332.043 801.622 -332.043 332.043 -801.622 -332.043 -801.622 -801.622 -332.043 -801.622 332.043)) (shape (polygon In1.Cu 0 -801.622 332.043 -332.043 801.622 332.043 801.622 801.622 332.043 801.622 -332.043 332.043 -801.622 -332.043 -801.622 -801.622 -332.043 -801.622 332.043)) (shape (polygon In2.Cu 0 -801.622 332.043 -332.043 801.622 332.043 801.622 801.622 332.043 801.622 -332.043 332.043 -801.622 -332.043 -801.622 -801.622 -332.043 -801.622 332.043)) (shape (polygon B.Cu 0 -801.622 332.043 -332.043 801.622 332.043 801.622 801.622 332.043 801.622 -332.043 332.043 -801.622 -332.043 -801.622 -801.622 -332.043 -801.622 332.043)) (attach off) ) (padstack Rect[T]Pad_270.000000x1500.000000_um (shape (rect F.Cu -135 -750 135 750)) (attach off) ) (padstack Rect[T]Pad_300.000000x1000.000000_um (shape (rect F.Cu -150 -500 150 500)) (attach off) ) (padstack Rect[T]Pad_500.000000x650.000000_um (shape (rect F.Cu -250 -325 250 325)) (attach off) ) (padstack "Rect[T][-900.000000,0.000000]Pad_3500.000000x1700.000000_um" (shape (rect F.Cu -2650 -850 850 850)) (attach off) ) (padstack Rect[T]Pad_5800.000000x6200.000000_um (shape (rect F.Cu -2900 -3100 2900 3100)) (attach off) ) (padstack Rect[T]Pad_1000.000000x1100.000000_um (shape (rect F.Cu -500 -550 500 550)) (attach off) ) (padstack Rect[T]Pad_1050.000000x1080.000000_um (shape (rect F.Cu -525 -540 525 540)) (attach off) ) (padstack Rect[T]Pad_1168.400000x1600.200000_um (shape (rect F.Cu -584.2 -800.1 584.2 800.1)) (attach off) ) (padstack Rect[T]Pad_1300.000000x1500.000000_um (shape (rect F.Cu -650 -750 650 750)) (attach off) ) (padstack Rect[T]Pad_1300.000000x1600.000000_um (shape (rect F.Cu -650 -800 650 800)) (attach off) ) (padstack Rect[T]Pad_1500.000000x2000.000000_um (shape (rect F.Cu -750 -1000 750 1000)) (attach off) ) (padstack Rect[T]Pad_1500.000000x270.000000_um (shape (rect F.Cu -750 -135 750 135)) (attach off) ) (padstack Rect[T]Pad_1500.000000x2900.000000_um (shape (rect F.Cu -750 -1450 750 1450)) (attach off) ) (padstack Rect[T]Pad_1600.000000x3000.000000_um (shape (rect F.Cu -800 -1500 800 1500)) (attach off) ) (padstack Rect[T][900.000000,0.000000]Pad_3500.000000x1700.000000_um (shape (rect F.Cu -850 -850 2650 850)) (attach off) ) (padstack Rect[A]Pad_1700.000000x1700.000000_um (shape (rect F.Cu -850 -850 850 850)) (shape (rect In1.Cu -850 -850 850 850)) (shape (rect In2.Cu -850 -850 850 850)) (shape (rect B.Cu -850 -850 850 850)) (attach off) ) (padstack Rect[T]Pad_1800.000000x3200.000000_um (shape (rect F.Cu -900 -1600 900 1600)) (attach off) ) (padstack "Via[0-3]_600:300_um" (shape (circle F.Cu 600)) (shape (circle In1.Cu 600)) (shape (circle In2.Cu 600)) (shape (circle B.Cu 600)) (attach off) ) ) (network (net GND (pins SV2-2 SV2-10 C17-2 IC3-10 IC3-19 PICO1-3 PICO1-3@1 PICO1-8 PICO1-8@1 PICO1-13 PICO1-13@1 PICO1-18 PICO1-18@1 PICO1-23 PICO1-23@1 PICO1-28 PICO1-28@1 PICO1-38 PICO1-38@1 C14-2 IC8-16 U3-2 IDE_OFF-1 C2-2 IC5-10 IC5-19 CN1-1 CN1-2 CN1-3 CN1-4 CN1-13 CN1-25 CN1-37 CN1-49 CN1-61 CN1-73 CN1-85 CN1-87 CN1-88 CN1-89 CN1-90 CN1-99 CN1-100 C16-2 AUTOBOOT_ON-1 C22-2 C29-2 Q3-2 C20-2 R8-2 IC2-18 IC2-29 IC2-36 IC2-47 IC2-62 IC2-72 IC2-89 IC2-90 IC2-99 IC2-108 IC2-114 IC2-123 IC2-144 IDE0-2 IDE0-19 IDE0-22 IDE0-24 IDE0-26 IDE0-28 IDE0-30 IDE0-40 IC7-1 C15-2 C31-2 C21-2 U2-11 U2-12 U2-13 U2-22 C23-2 IC4-10 IC4-19 C10-1 U1-11 U1-12 U1-13 C30-1 C11-2 C32-2 C12-2 C9-1) ) (net "~{BERR}" (pins CN1-46 IC2-98) ) (net "~{DTACK}" (pins CN1-66 IC2-85) ) (net D0 (pins CN1-75 IC2-2) ) (net D1 (pins CN1-77 IC2-17) ) (net D2 (pins CN1-79 IC2-39) ) (net D3 (pins CN1-81 IC2-15) ) (net D4 (pins CN1-83 IC2-21) ) (net D5 (pins CN1-86 IC2-20) ) (net D6 (pins CN1-84 IC2-14) ) (net D7 (pins CN1-82 IC2-16) ) (net D8 (pins CN1-80 IC2-19) ) (net D9 (pins CN1-78 IC2-40) ) (net D10 (pins CN1-76 IC2-41) ) (net D11 (pins CN1-71 IC2-43) ) (net D12 (pins CN1-69 IC2-44) ) (net D13 (pins CN1-67 IC2-45) ) (net D14 (pins CN1-65 IC2-46) ) (net D15 (pins CN1-63 IC2-48) ) (net R/W (pins CN1-68 IC2-83) ) (net "~{UDS}" (pins CN1-72 IC2-81) ) (net "~{LDS}" (pins CN1-70 IC2-82) ) (net A1 (pins IC8-12 CN1-29 IC2-57) ) (net A2 (pins IC8-11 CN1-27 IC2-54) ) (net A3 (pins IC8-10 CN1-26 IC2-52) ) (net A4 (pins IC8-9 CN1-24 IC2-50) ) (net A5 (pins IC8-8 CN1-21 IC2-49) ) (net A6 (pins IC8-7 CN1-23 IC2-51) ) (net A7 (pins IC8-6 CN1-28 IC2-53) ) (net A9 (pins IC8-27 CN1-32 IC2-58) ) (net A8 (pins IC8-5 CN1-30 IC2-56) ) (net A10 (pins IC8-26 CN1-34 IC2-59) ) (net A11 (pins IC8-23 CN1-36 IC2-60) ) (net A12 (pins IC8-25 CN1-38 IC2-61) ) (net A13 (pins IC8-4 CN1-39 IC2-64) ) (net A14 (pins IC8-28 CN1-41 IC2-66) ) (net A15 (pins IC8-29 CN1-43 IC2-74) ) (net A16 (pins CN1-45 IC2-97) ) (net A17 (pins CN1-47 IC2-95) ) (net A18 (pins CN1-52 IC2-94) ) (net A19 (pins CN1-54 IC2-92) ) (net A20 (pins CN1-56 IC2-91) ) (net A21 (pins CN1-58 IC2-88) ) (net A22 (pins CN1-57 IC2-87) ) (net A23 (pins CN1-59 IC2-86) ) (net +3V3 (pins PICO1-36 PICO1-36@1 C22-1 C29-1 IC2-1 IC2-8 IC2-37 IC2-42 IC2-55 IC2-73 IC2-84 IC2-109 IC2-127 IC2-141 IC7-4 C21-1 U2-1 U2-2 U2-23 U2-24 C10-2 U1-1 U1-23 U1-24 C30-2 C11-1 C32-1 C12-1 C9-2) ) (net IDE_RST (pins IC5-18 IDE0-1 U2-10) ) (net "~{IDE_R}" (pins IC5-16 IDE0-25) ) (net IDE_A2 (pins IC5-14 IDE0-36) ) (net IDE_A1 (pins IC5-15 IDE0-33) ) (net IDE_A0 (pins IC5-13 IDE0-35) ) (net IDE_CS1 (pins IC5-12 IDE0-38) ) (net IDE_CS0 (pins IC5-11 IDE0-37) ) (net "~{IDE_W}" (pins IC5-17 IDE0-23) ) (net "~{IDE_ACT}" (pins IDE_ACT0-2 IDE0-39) ) (net IDED7 (pins IC3-18 IDE0-3) ) (net IDED6 (pins IC3-16 IDE0-5) ) (net IDED5 (pins IC3-14 IDE0-7) ) (net IDED4 (pins IC3-12 IDE0-9) ) (net IDED3 (pins IDE0-11 IC4-18) ) (net IDED2 (pins IDE0-13 IC4-16) ) (net IDED1 (pins IDE0-15 IC4-14) ) (net IDED0 (pins IDE0-17 IC4-12) ) (net IDED8 (pins IC3-17 IDE0-4) ) (net IDED9 (pins IC3-15 IDE0-6) ) (net IDED10 (pins IC3-13 IDE0-8) ) (net IDED11 (pins IC3-11 IDE0-10) ) (net IDED12 (pins IDE0-12 IC4-17) ) (net IDED13 (pins IDE0-14 IC4-15) ) (net IDED14 (pins IDE0-16 IC4-13) ) (net IDED15 (pins IDE0-18 IC4-11) ) (net IDE_IRQ (pins R2-2 IDE0-31) ) (net IDE_WAIT (pins R3-2 IC2-33 IDE0-27) ) (net KEY_PIN_POWER (pins IDE0-20 F1-1 C23-1) ) (net "~{RESET}" (pins IC5-2 CN1-53 IC2-143) ) (net C_IDE_R (pins IC3-1 IC5-4 IC2-27 IC4-1) ) (net C_IDE_A1 (pins IC5-5 IC2-26) ) (net C_IDE_A0 (pins IC5-7 IC2-24) ) (net C_IDE_CS1 (pins IC5-8 IC2-23) ) (net C_IDE_A2 (pins IC5-6 IC2-25) ) (net C_IDE_CS0 (pins IC5-9 IC2-22) ) (net +5V (pins SV2-4 C17-1 IC3-20 R2-1 R1-1 R5-1 PICO1-39 PICO1-39@1 C14-1 IC8-1 IC8-30 IC8-31 IC8-32 R3-1 C2-1 IC5-1 IC5-20 CN1-5 CN1-6 C16-1 C20-1 R11-1 IC7-3 R7-1 JP1-2 C15-1 RN1-5 RN1-6 RN1-7 RN1-8 C31-1 R9-1 F1-2 IC4-20) ) (net C_IDE_W (pins IC5-3 IC2-28) ) (net ROM_B0 (pins SJ1-2 IC8-3 R8-1 JP1-1) ) (net ROM_B1 (pins IC8-2 IC2-69) ) (net ROM_OE (pins IC8-24 IC2-35) ) (net TCK (pins SV2-1 IC2-67 RN1-1) ) (net TDI (pins SV2-9 IC2-63 RN1-3) ) (net TDO (pins SV2-3 IC2-122) ) (net TMS (pins SV2-5 IC2-65 RN1-2) ) (net DQ7 (pins IC8-21 IC2-125 IC4-9 U1-10) ) (net DQ6 (pins IC8-20 IC2-126 IC4-7 U1-9) ) (net DQ5 (pins IC8-19 IC2-121 IC4-5 U1-8) ) (net DQ4 (pins IC8-18 IC2-124 IC4-3 U1-7) ) (net DQ3 (pins IC3-9 IC8-17 IC2-119 U1-6) ) (net DQ2 (pins IC3-7 IC8-15 IC2-120 U1-5) ) (net DQ1 (pins IC3-5 IC8-14 IC2-117 U1-4) ) (net DQ0 (pins IC3-3 IC8-13 IC2-118 U1-3) ) (net DQ15 (pins IC3-2 IC2-112) ) (net DQ14 (pins IC3-4 IC2-131) ) (net DQ13 (pins IC3-6 IC2-113) ) (net DQ12 (pins IC3-8 IC2-130) ) (net DQ11 (pins IC2-115 IC4-2) ) (net DQ10 (pins IC2-129 IC4-4) ) (net DQ9 (pins IC2-116 IC4-6) ) (net DQ8 (pins IC2-128 IC4-8) ) (net LAN_A3 (pins IC2-5 U2-3) ) (net LAN_A2 (pins IC2-6) ) (net LAN_A1 (pins IC2-3) ) (net LAN_A0 (pins IC2-4) ) (net LAN_A10 (pins IC2-138) ) (net LAN_A11 (pins IC2-139) ) (net LAN_A9 (pins IC2-142) ) (net LAN_A8 (pins IC2-140) ) (net LAN_A7 (pins IC2-10) ) (net LAN_A6 (pins IC2-11 U2-6) ) (net LAN_A5 (pins IC2-7 U2-5) ) (net LAN_A4 (pins IC2-9 U2-4) ) (net CLK_EXT (pins IC2-30) ) (net IDE_OFF (pins R5-2 IDE_OFF-2 IC2-75) ) (net N$42 (pins IDE_ACT0-1 R7-2) ) (net "~{AS}" (pins CN1-74 IC2-80) ) (net C1 (pins CN1-14 IC2-103) ) (net "~{OWN}" (pins CN1-7 IC2-107) ) (net "~{SLAVE}" (pins CN1-9 IC2-106) ) (net "~{CFOUT}" (pins CN1-11 IC2-105) ) (net "~{CFIN}" (pins CN1-12 IC2-104) ) (net "~{OVR}" (pins CN1-17 IC2-100) ) (net C3 (pins CN1-16 IC2-102) ) (net "~{DS0}" (pins CN1-51 IC2-93) ) (net "~{MTACK}" (pins CN1-48 IC2-96) ) (net "~{MTCR}" (pins CN1-18 IC2-101) ) (net "~{FCS}" (pins CN1-97 IC2-77) ) (net "~{DS1}" (pins CN1-98 IC2-78) ) (net Z3 (pins CN1-91 IC2-79) ) (net FC0 (pins CN1-31) ) (net FC1 (pins CN1-33) ) (net FC2 (pins CN1-35) ) (net N$40 (pins SJ1-1 IC2-68) ) (net INT2 (pins CN1-19 IC2-32 R9-2) ) (net INT6 (pins CN1-22 IC2-135) ) (net LAN_A12 (pins IC2-136) ) (net LAN_A13 (pins IC2-137) ) (net LAN_WRH (pins IC2-132) ) (net LAN_INT (pins IC2-111) ) (net LAN_CS (pins IC2-133) ) (net LAN_CFG4 (pins IC2-110) ) (net LAN_EN (pins IC2-76) ) (net LAN_RD (pins IC2-134) ) (net LAN_CFG1 (pins IC2-12) ) (net LAN_CFG3 (pins IC2-13) ) (net CP_IRQ (pins Q3-3 R11-2 IC2-31) ) (net CP_CS (pins IC2-34 U2-7 U1-22) ) (net CP_WE (pins U3-1 IC2-70 U2-8) ) (net CP_RD (pins IC2-71 U2-9) ) (net ROM_CE (pins R1-2 IC8-22 AUTOBOOT_ON-2) ) (net DOE (pins CN1-93 IC2-38) ) (net PICO_D0 (pins PICO1-1 PICO1-1@1 U1-21) ) (net PICO_D1 (pins PICO1-2 PICO1-2@1 U1-20) ) (net PICO_D2 (pins PICO1-4 PICO1-4@1 U1-19) ) (net PICO_D3 (pins PICO1-5 PICO1-5@1 U1-18) ) (net PICO_D4 (pins PICO1-6 PICO1-6@1 U1-17) ) (net PICO_D5 (pins PICO1-7 PICO1-7@1 U1-16) ) (net PICO_D6 (pins PICO1-9 PICO1-9@1 U1-15) ) (net PICO_D7 (pins PICO1-10 PICO1-10@1 U1-14) ) (net PICO_A2 (pins PICO1-11 PICO1-11@1 U2-21) ) (net PICO_A3 (pins PICO1-12 PICO1-12@1 U2-20) ) (net PICO_A4 (pins PICO1-14 PICO1-14@1 U2-19) ) (net PICO_A5 (pins PICO1-15 PICO1-15@1 U2-18) ) (net PICO_CS (pins PICO1-16 PICO1-16@1 U2-17) ) (net PICO_WE (pins PICO1-17 PICO1-17@1 U2-16) ) (net PICO_RD (pins PICO1-19 PICO1-19@1 U2-15) ) (net PICO_RESET (pins PICO1-20 PICO1-20@1 U2-14) ) (net PICO_IRQ (pins PICO1-24 PICO1-24@1 Q3-1) ) (net CP_DIR (pins U3-3 U1-2) ) (class kicad_default +3V3 +5V A1 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A2 A20 A21 A22 A23 A3 A4 A5 A6 A7 A8 A9 C1 C3 CLK_EXT CP_CS CP_DIR CP_IRQ CP_RD CP_WE C_IDE_A0 C_IDE_A1 C_IDE_A2 C_IDE_CS0 C_IDE_CS1 C_IDE_R C_IDE_W D0 D1 D10 D11 D12 D13 D14 D15 D2 D3 D4 D5 D6 D7 D8 D9 DOE DQ0 DQ1 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 FC0 FC1 FC2 GND IDED0 IDED1 IDED10 IDED11 IDED12 IDED13 IDED14 IDED15 IDED2 IDED3 IDED4 IDED5 IDED6 IDED7 IDED8 IDED9 IDE_A0 IDE_A1 IDE_A2 IDE_CS0 IDE_CS1 IDE_IRQ IDE_OFF IDE_RST IDE_WAIT INT2 INT6 KEY_PIN_POWER LAN_A0 LAN_A1 LAN_A10 LAN_A11 LAN_A12 LAN_A13 LAN_A2 LAN_A3 LAN_A4 LAN_A5 LAN_A6 LAN_A7 LAN_A8 LAN_A9 LAN_CFG1 LAN_CFG3 LAN_CFG4 LAN_CS LAN_EN LAN_INT LAN_RD LAN_WRH N$40 N$42 PICO_A2 PICO_A3 PICO_A4 PICO_A5 PICO_CS PICO_D0 PICO_D1 PICO_D2 PICO_D3 PICO_D4 PICO_D5 PICO_D6 PICO_D7 PICO_IRQ PICO_RD PICO_RESET PICO_WE R/W ROM_B0 ROM_B1 ROM_CE ROM_OE TCK TDI TDO TMS Z3 "~{AS}" "~{BERR}" "~{CFIN}" "~{CFOUT}" "~{DS0}" "~{DS1}" "~{DTACK}" "~{FCS}" "~{IDE_ACT}" "~{IDE_R}" "~{IDE_W}" "~{LDS}" "~{MTACK}" "~{MTCR}" "~{OVR}" "~{OWN}" "~{RESET}" "~{SLAVE}" "~{UDS}" (circuit (use_via "Via[0-3]_600:300_um") ) (rule (width 200) (clearance 200) ) ) ) (wiring ) )