cpldfit: version P.20131013 Xilinx Inc. Fitter Report Design Name: LAN_IDE_CP Date: 1- 2-2019, 11:11AM Device Used: XC95288XL-10-TQ144 Fitting Status: Successful ************************* Mapped Resource Summary ************************** Macrocells Product Terms Function Block Registers Pins Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot 208/288 ( 72%) 604 /1440 ( 42%) 410/864 ( 47%) 115/288 ( 40%) 109/117 ( 93%) ** Function Block Resources ** Function Mcells FB Inps Pterms IO Block Used/Tot Used/Tot Used/Tot Used/Tot FB1 8/18 4/54 4/90 8/ 8* FB2 18/18* 29/54 39/90 10/10* FB3 2/18 2/54 1/90 3/ 5 FB4 18/18* 25/54 37/90 6/ 6* FB5 18/18* 29/54 48/90 7/ 8 FB6 10/18 31/54 28/90 8/ 8* FB7 13/18 31/54 43/90 4/ 4* FB8 16/18 32/54 39/90 5/ 5* FB9 8/18 31/54 42/90 8/ 9 FB10 18/18* 31/54 48/90 10/10* FB11 18/18* 28/54 70/90 7/ 7* FB12 9/18 31/54 18/90 6/ 6* FB13 9/18 31/54 36/90 6/ 6* FB14 12/18 23/54 21/90 5/ 8 FB15 13/18 31/54 53/90 8/ 9 FB16 18/18* 21/54 77/90 8/ 8* ----- ----- ----- ----- 208/288 410/864 604/1440 109/117 * - Resource is exhausted ** Global Control Resources ** Signal 'CLK_EXT' mapped onto global clock net GCK1. Global output enable net(s) unused. Global set/reset net(s) unused. ** Pin Resources ** Signal Type Required Mapped | Pin Type Used Total ------------------------------------|------------------------------------ Input : 18 18 | I/O : 102 109 Output : 42 42 | GCK/IO : 2 3 Bidirectional : 48 48 | GTS/IO : 4 4 GCK : 1 1 | GSR/IO : 1 1 GTS : 0 0 | GSR : 0 0 | ---- ---- Total 109 109 ** Power Data ** There are 208 macrocells in high performance mode (MCHP). There are 0 macrocells in low power mode (MCLP). End of Mapped Resource Summary ************************** Errors and Warnings *************************** WARNING:Cpld - Unable to retrieve the path to the iSE Project Repository. Will use the default filename of 'LAN_IDE_CP.ise'. INFO:Cpld - Inferring BUFG constraint for signal 'CLK_EXT' based upon the LOC constraint 'P30'. It is recommended that you declare this BUFG explicitedly in your design. Note that for certain device families the output of a BUFG constraint can not drive a gated clock, and the BUFG constraint will be ignored. WARNING:Cpld:1007 - Removing unused input(s) 'A<1>'. The input(s) are unused after optimization. Please verify functionality via simulation. WARNING:Cpld:1007 - Removing unused input(s) 'AS'. The input(s) are unused after optimization. Please verify functionality via simulation. WARNING:Cpld:1007 - Removing unused input(s) 'C1'. The input(s) are unused after optimization. Please verify functionality via simulation. WARNING:Cpld:1007 - Removing unused input(s) 'C3'. The input(s) are unused after optimization. Please verify functionality via simulation. WARNING:Cpld:1007 - Removing unused input(s) 'CP_IRQ'. The input(s) are unused after optimization. Please verify functionality via simulation. WARNING:Cpld:1007 - Removing unused input(s) 'IDE_WAIT'. The input(s) are unused after optimization. Please verify functionality via simulation. WARNING:Cpld:1007 - Removing unused input(s) 'MTCR'. The input(s) are unused after optimization. Please verify functionality via simulation. ************************* Summary of Mapped Logic ************************ ** 90 Outputs ** Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init Name Pts Inps No. Type Use Mode Rate State D<5> 2 3 FB1_5 20 I/O I/O STD FAST D<4> 2 3 FB1_6 21 I/O I/O STD FAST IDE_CS<0> 0 0 FB1_8 22 I/O O STD FAST IDE_CS<1> 0 0 FB1_10 23 I/O O STD FAST IDE_A<0> 0 0 FB1_12 24 I/O O STD FAST IDE_A<2> 0 0 FB1_14 25 I/O O STD FAST IDE_A<1> 0 0 FB1_15 26 I/O O STD FAST IDE_R 0 0 FB1_17 27 I/O O STD FAST A_LAN<4> 1 2 FB2_2 9 I/O O STD FAST A_LAN<7> 1 2 FB2_3 10 I/O O STD FAST A_LAN<6> 2 3 FB2_5 11 I/O O STD FAST LAN_CFG<1> 0 0 FB2_6 12 I/O O STD FAST LAN_CFG<3> 0 0 FB2_8 13 I/O O STD FAST D<6> 2 3 FB2_10 14 I/O I/O STD FAST D<3> 2 3 FB2_12 15 I/O I/O STD FAST D<7> 2 3 FB2_14 16 I/O I/O STD FAST D<1> 2 3 FB2_15 17 I/O I/O STD FAST D<8> 3 4 FB2_17 19 I/O I/O STD FAST IDE_W 0 0 FB3_2 28 I/O O STD FAST INT_OUT 1 2 FB3_14 32 GCK/I/O O STD FAST D<0> 2 3 FB4_2 2 GTS/I/O I/O STD FAST A_LAN<1> 1 2 FB4_5 3 GTS/I/O O STD FAST A_LAN<0> 1 2 FB4_6 4 I/O O STD FAST A_LAN<3> 2 3 FB4_8 5 GTS/I/O O STD FAST A_LAN<2> 1 2 FB4_12 6 GTS/I/O O STD FAST A_LAN<5> 1 2 FB4_14 7 I/O O STD FAST CP_CS 0 0 FB5_2 34 I/O O STD FAST ROM_OE 0 0 FB5_5 35 I/O O STD FAST D<2> 2 3 FB5_10 39 I/O I/O STD FAST D<9> 3 4 FB5_12 40 I/O I/O STD FAST D<10> 3 4 FB5_14 41 I/O I/O STD FAST D<11> 3 4 FB5_15 43 I/O I/O STD FAST D<12> 3 4 FB5_17 44 I/O I/O STD FAST LAN_CFG<2> 0 0 FB6_2 135 I/O O STD FAST A_LAN<12> 1 2 FB6_3 136 I/O O STD FAST A_LAN<13> 1 2 FB6_5 137 I/O O STD FAST A_LAN<10> 1 2 FB6_6 138 I/O O STD FAST A_LAN<11> 1 2 FB6_8 139 I/O O STD FAST A_LAN<8> 1 2 FB6_10 140 I/O O STD FAST A_LAN<9> 1 2 FB6_14 142 I/O O STD FAST Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init Name Pts Inps No. Type Use Mode Rate State D<13> 3 4 FB7_3 45 I/O I/O STD FAST D<14> 3 4 FB7_5 46 I/O I/O STD FAST D<15> 3 4 FB7_12 48 I/O I/O STD FAST DQ<12> 2 3 FB8_2 130 I/O I/O STD FAST DQ<14> 2 3 FB8_3 131 I/O I/O STD FAST LAN_WRH 2 3 FB8_5 132 I/O O STD FAST LAN_CS 2 3 FB8_8 133 I/O O STD FAST LAN_RD 1 2 FB8_10 134 I/O O STD FAST A<8> 5 10 FB9_11 56 I/O I/O STD FAST RESET A<9> 5 10 FB9_14 58 I/O I/O STD FAST RESET A<10> 5 10 FB9_17 59 I/O I/O STD FAST RESET DQ<1> 3 4 FB10_2 117 I/O I/O STD FAST DQ<0> 2 3 FB10_3 118 I/O I/O STD FAST DQ<3> 2 3 FB10_5 119 I/O I/O STD FAST DQ<2> 2 3 FB10_6 120 I/O I/O STD FAST DQ<5> 2 3 FB10_8 121 I/O I/O STD FAST DQ<4> 3 4 FB10_10 124 I/O I/O STD FAST DQ<7> 2 3 FB10_11 125 I/O I/O STD FAST DQ<6> 2 3 FB10_12 126 I/O I/O STD FAST DQ<8> 3 4 FB10_14 128 I/O I/O STD FAST DQ<10> 3 4 FB10_17 129 I/O I/O STD FAST A<11> 5 10 FB11_3 60 I/O I/O STD FAST RESET A<12> 5 10 FB11_5 61 I/O I/O STD FAST RESET A<13> 5 10 FB11_10 64 I/O I/O STD FAST RESET A<14> 5 10 FB11_11 66 I/O I/O STD FAST RESET ROM_B<0> 0 0 FB11_12 68 I/O O STD FAST ROM_B<1> 0 0 FB11_14 69 I/O O STD FAST CP_WE 0 0 FB11_17 70 I/O O STD FAST LAN_CFG<4> 0 0 FB12_2 110 I/O O STD FAST DQ<15> 2 3 FB12_5 112 I/O I/O STD FAST DQ<13> 2 3 FB12_8 113 I/O I/O STD FAST DQ<11> 3 4 FB12_10 115 I/O I/O STD FAST DQ<9> 3 4 FB12_12 116 I/O I/O STD FAST CP_RD 0 0 FB13_2 71 I/O O STD FAST A<15> 5 10 FB13_8 74 I/O I/O STD FAST RESET LAN_WRL 2 3 FB13_14 76 I/O O STD FAST OVR 1 1 FB14_3 100 I/O O STD FAST CFOUT 3 4 FB14_11 105 I/O O STD FAST SET SLAVE 2 3 FB14_14 106 I/O O STD FAST OWN 0 0 FB14_15 107 I/O O STD FAST Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init Name Pts Inps No. Type Use Mode Rate State DTACK 1 1 FB15_12 85 I/O O STD FAST A<23> 5 10 FB15_14 86 I/O I/O STD FAST RESET A<22> 5 10 FB15_15 87 I/O I/O STD FAST RESET A<21> 5 10 FB15_17 88 I/O I/O STD FAST RESET A<20> 5 10 FB16_2 91 I/O I/O STD FAST RESET A<19> 5 10 FB16_3 92 I/O I/O STD FAST RESET A<18> 5 10 FB16_6 94 I/O I/O STD FAST RESET A<17> 5 10 FB16_8 95 I/O I/O STD FAST RESET MTACK 0 0 FB16_10 96 I/O O STD FAST A<16> 5 10 FB16_11 97 I/O I/O STD FAST RESET ** 118 Buried Nodes ** Signal Total Total Loc Pwr Reg Init Name Pts Inps Mode State LAN_BASEADR<7> 3 13 FB2_1 STD RESET LAN_BASEADR<5> 3 13 FB2_4 STD RESET LAN_BASEADR<4> 3 13 FB2_7 STD RESET LAN_BASEADR<3> 3 13 FB2_9 STD RESET LAN_BASEADR<2> 3 13 FB2_11 STD RESET LAN_BASEADR<1> 3 13 FB2_13 STD RESET LAN_BASEADR<15> 3 13 FB2_16 STD RESET LAN_BASEADR<10> 3 13 FB2_18 STD RESET LAN_SM_RST 1 3 FB4_1 STD RESET LAN_WR_RST 2 3 FB4_3 STD RESET LAN_RST_SM_FSM_FFd1 2 4 FB4_4 STD RESET LAN_IRQ_D0 2 2 FB4_7 STD RESET LAN_CS_RST 2 3 FB4_9 STD RESET LAN_A_INIT<6> 2 2 FB4_10 STD SET DQ_9_IOBUFE/DQ_9_IOBUFE_TRST 2 3 FB4_11 STD CONFIG_READY 2 2 FB4_13 STD RESET LAN_RST_SM_FSM_FFd3 3 3 FB4_15 STD RESET LAN_RST_SM_FSM_FFd2 3 4 FB4_16 STD RESET LAN_IRQ_OUT 3 4 FB4_17 STD RESET LAN_INT_ENABLE 5 8 FB4_18 STD RESET D_OUT<7> 2 9 FB5_1 STD SET D_OUT<3> 2 8 FB5_3 STD SET D_OUT<0> 2 10 FB5_4 STD SET LAN_BASEADR<9> 3 13 FB5_6 STD RESET LAN_BASEADR<8> 3 13 FB5_7 STD RESET D_OUT<2> 3 10 FB5_8 STD SET AUTO_CONFIG_DONE_CYCLE 3 12 FB5_9 STD RESET D_OUT<6> 4 11 FB5_11 STD SET D_OUT<4> 4 11 FB5_13 STD SET D_OUT<1> 4 10 FB5_16 STD SET D_9_IOBUFE/D_9_IOBUFE_TRST 4 8 FB5_18 STD $OpTx$INV$1 16 16 FB6_1 STD N0$BUF7/N0$BUF7_TRST 2 4 FB6_16 STD $OpTx$INV$2 4 4 FB6_17 STD LAN_A_INIT<3> 1 1 FB7_8 STD SET Z3_ADR_1 3 3 FB7_9 STD RESET Z3_ADR_0 3 3 FB7_10 STD RESET Z3_ADR<9> 3 3 FB7_11 STD RESET Z3_ADR<8> 3 3 FB7_13 STD RESET Z3_ADR<7> 3 3 FB7_14 STD RESET Signal Total Total Loc Pwr Reg Init Name Pts Inps Mode State Z3_ADR<6> 3 3 FB7_15 STD RESET Z3_ADR<5> 3 3 FB7_16 STD RESET DQ_DATA<9> 6 13 FB7_17 STD RESET DQ_DATA<1> 6 13 FB7_18 STD RESET BUF_CONFIG_READY 1 3 FB8_6 STD $OpTx$FX_DC$24 1 2 FB8_7 STD $OpTx$FX_DC$32 2 4 FB8_9 STD Z3_ADR<3> 3 3 FB8_11 STD RESET Z3_ADR<2> 3 3 FB8_12 STD RESET Z3_ADR<13> 3 3 FB8_13 STD RESET Z3_ADR<12> 3 3 FB8_14 STD RESET Z3_ADR<11> 3 3 FB8_15 STD RESET Z3_ADR<10> 3 3 FB8_16 STD RESET LAN_ACCESS 4 13 FB8_17 STD RESET DQ_SWAP 4 15 FB8_18 STD RESET DQ_DATA<4> 6 13 FB9_1 STD RESET LAN_WRH_S 3 7 FB9_12 STD RESET DQ_DATA<5> 6 13 FB9_13 STD RESET DQ_DATA<13> 6 13 FB9_16 STD RESET DQ_DATA<12> 6 13 FB9_18 STD RESET SHUT_UP 2 12 FB10_1 STD RESET LAN_BASEADR<6> 3 13 FB10_4 STD RESET LAN_BASEADR<14> 3 13 FB10_7 STD RESET LAN_BASEADR<13> 3 13 FB10_9 STD RESET LAN_BASEADR<12> 3 13 FB10_13 STD RESET LAN_BASEADR<11> 3 13 FB10_15 STD RESET LAN_BASEADR<0> 3 13 FB10_16 STD RESET D_OUT<5> 4 11 FB10_18 STD SET Z3_DATA<31> 4 8 FB11_1 STD RESET Z3_DATA<30> 4 8 FB11_2 STD RESET Z3_DATA<29> 4 8 FB11_4 STD RESET Z3_DATA<23> 4 8 FB11_6 STD RESET Z3_DATA<22> 4 8 FB11_7 STD RESET Z3_DATA<21> 4 8 FB11_8 STD RESET LAN_SM_FSM_FFd2 4 7 FB11_9 STD RESET LAN_RD_S 4 6 FB11_13 STD RESET LAN_SM_FSM_FFd4 6 7 FB11_15 STD RESET DQ_DATA<8> 6 13 FB11_16 STD RESET DQ_DATA<0> 6 13 FB11_18 STD RESET Z3_ADR_1/Z3_ADR_1_SETF 1 2 FB12_15 STD Signal Total Total Loc Pwr Reg Init Name Pts Inps Mode State LAN_D_INIT<8> 2 2 FB12_16 STD RESET LAN_D_INIT<1> 2 2 FB12_17 STD RESET AUTOCONFIG_ACCESS 3 21 FB12_18 STD RESET LAN_READY 2 2 FB13_1 STD RESET LAN_WRL_S 3 7 FB13_13 STD RESET DQ_DATA<7> 6 13 FB13_15 STD RESET DQ_DATA<6> 6 13 FB13_16 STD RESET DQ_DATA<15> 6 13 FB13_17 STD RESET DQ_DATA<14> 6 13 FB13_18 STD RESET $OpTx$FX_DC$8 1 2 FB14_8 STD $OpTx$FX_DC$10 1 2 FB14_9 STD $OpTx$FX_DC$39 2 2 FB14_10 STD $OpTx$FX_DC$38 2 2 FB14_12 STD $OpTx$FX_DC$37 2 2 FB14_13 STD $OpTx$FX_DC$36 2 2 FB14_16 STD $OpTx$FX_DC$35 2 2 FB14_17 STD Z3_ADR<4> 3 3 FB14_18 STD RESET DQ_DATA<10> 6 13 FB15_1 STD RESET DQ_DATA<11> 6 13 FB15_2 STD RESET DQ_DATA<2> 6 13 FB15_3 STD RESET DQ_DATA<3> 6 13 FB15_4 STD RESET BUF_LAN_READY 5 5 FB15_5 STD LAN_SM_FSM_FFd1 3 5 FB15_6 STD RESET $OpTx$FX_DC$16 2 4 FB15_7 STD $OpTx$FX_SC$18 2 5 FB15_8 STD Z3_DATA<1>/Z3_DATA<1>_TRST 1 2 FB15_9 STD Z3_DATA<28> 4 8 FB16_1 STD RESET Z3_DATA<27> 4 8 FB16_4 STD RESET Z3_DATA<26> 4 8 FB16_5 STD RESET Z3_DATA<25> 4 8 FB16_7 STD RESET Z3_DATA<24> 4 8 FB16_9 STD RESET Z3_DATA<20> 4 8 FB16_12 STD RESET Z3_DATA<19> 4 8 FB16_13 STD RESET Z3_DATA<17> 4 8 FB16_14 STD RESET Z3_DATA<16> 4 8 FB16_15 STD RESET Z3_A_LOW 6 8 FB16_16 STD RESET LAN_SM_FSM_FFd3 6 8 FB16_17 STD RESET Z3_DATA<18> 4 8 FB16_18 STD RESET ** 19 Inputs ** Signal Loc Pin Pin Pin Name No. Type Use CLK_EXT FB3_10 30 GCK/I/O GCK RESET FB6_15 143 GSR/I/O I A<5> FB7_15 49 I/O I A<4> FB9_2 50 I/O I A<6> FB9_3 51 I/O I A<3> FB9_5 52 I/O I A<7> FB9_6 53 I/O I A<2> FB9_8 54 I/O I LAN_INT FB12_3 111 I/O I AUTOBOOT_OFF FB13_11 75 I/O I FCS FB13_15 77 I/O I DS1 FB13_17 78 I/O I CFIN FB14_10 104 I/O I Z3 FB15_2 79 I/O I UDS FB15_8 81 I/O I LDS FB15_10 82 I/O I RW FB15_11 83 I/O I DS0 FB16_5 93 I/O I BERR FB16_12 98 I/O I Legend: Pin No. - ~ - User Assigned ************************** Function Block Details ************************ Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X - Signal used as input to the macrocell logic. Pin No. - ~ - User Assigned *********************************** FB1 *********************************** Number of function block inputs used/remaining: 4/50 Number of signals used by logic mapping into function block: 4 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB1_1 (b) (unused) 0 0 0 5 FB1_2 (b) (unused) 0 0 0 5 FB1_3 (b) (unused) 0 0 0 5 FB1_4 (b) D<5> 2 0 0 3 FB1_5 20 I/O I/O D<4> 2 0 0 3 FB1_6 21 I/O I/O (unused) 0 0 0 5 FB1_7 (b) IDE_CS<0> 0 0 0 5 FB1_8 22 I/O O (unused) 0 0 0 5 FB1_9 (b) IDE_CS<1> 0 0 0 5 FB1_10 23 I/O O (unused) 0 0 0 5 FB1_11 (b) IDE_A<0> 0 0 0 5 FB1_12 24 I/O O (unused) 0 0 0 5 FB1_13 (b) IDE_A<2> 0 0 0 5 FB1_14 25 I/O O IDE_A<1> 0 0 0 5 FB1_15 26 I/O O (unused) 0 0 0 5 FB1_16 (b) IDE_R 0 0 0 5 FB1_17 27 I/O O (unused) 0 0 0 5 FB1_18 (b) Signals Used by Logic in Function Block 1: D_9_IOBUFE/D_9_IOBUFE_TRST 3: Z3_DATA<20> 4: Z3_DATA<21> 2: Z3_DATA<1>/Z3_DATA<1>_TRST Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs D<5> XX.X.................................... 3 D<4> XXX..................................... 3 IDE_CS<0> ........................................ 0 IDE_CS<1> ........................................ 0 IDE_A<0> ........................................ 0 IDE_A<2> ........................................ 0 IDE_A<1> ........................................ 0 IDE_R ........................................ 0 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB2 *********************************** Number of function block inputs used/remaining: 29/25 Number of signals used by logic mapping into function block: 29 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use LAN_BASEADR<7> 3 0 0 2 FB2_1 (b) (b) A_LAN<4> 1 0 0 4 FB2_2 9 I/O O A_LAN<7> 1 0 0 4 FB2_3 10 I/O O LAN_BASEADR<5> 3 0 0 2 FB2_4 (b) (b) A_LAN<6> 2 0 0 3 FB2_5 11 I/O O LAN_CFG<1> 0 0 0 5 FB2_6 12 I/O O LAN_BASEADR<4> 3 0 0 2 FB2_7 (b) (b) LAN_CFG<3> 0 0 0 5 FB2_8 13 I/O O LAN_BASEADR<3> 3 0 0 2 FB2_9 (b) (b) D<6> 2 0 0 3 FB2_10 14 I/O I/O LAN_BASEADR<2> 3 0 0 2 FB2_11 (b) (b) D<3> 2 0 0 3 FB2_12 15 I/O I/O LAN_BASEADR<1> 3 0 0 2 FB2_13 (b) (b) D<7> 2 0 0 3 FB2_14 16 I/O I/O D<1> 2 0 0 3 FB2_15 17 I/O I/O LAN_BASEADR<15> 3 0 0 2 FB2_16 (b) (b) D<8> 3 0 0 2 FB2_17 19 I/O I/O LAN_BASEADR<10> 3 0 0 2 FB2_18 (b) (b) Signals Used by Logic in Function Block 1: AUTOCONFIG_ACCESS 11: D<3>.PIN 21: Z3_ADR<6> 2: D_9_IOBUFE/D_9_IOBUFE_TRST 12: D<2>.PIN 22: Z3_ADR_0 3: D_OUT<0> 13: D<1>.PIN 23: Z3_ADR_1 4: FCS 14: RESET 24: Z3_DATA<17> 5: LAN_A_INIT<6> 15: RW 25: Z3_DATA<19> 6: D<15>.PIN 16: UDS 26: Z3_DATA<1>/Z3_DATA<1>_TRST 7: D<10>.PIN 17: Z3_ADR<2> 27: Z3_DATA<22> 8: D<7>.PIN 18: Z3_ADR<3> 28: Z3_DATA<23> 9: D<5>.PIN 19: Z3_ADR<4> 29: Z3_DATA<24> 10: D<4>.PIN 20: Z3_ADR<5> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs LAN_BASEADR<7> X..X...X.....XXXXXXXXXX................. 13 A_LAN<4> .............X...X...................... 2 A_LAN<7> .............X......X................... 2 LAN_BASEADR<5> X..X....X....XXXXXXXXXX................. 13 A_LAN<6> ....X........X.....X.................... 3 LAN_CFG<1> ........................................ 0 LAN_BASEADR<4> X..X.....X...XXXXXXXXXX................. 13 LAN_CFG<3> ........................................ 0 LAN_BASEADR<3> X..X......X..XXXXXXXXXX................. 13 D<6> .X.......................XX............. 3 LAN_BASEADR<2> X..X.......X.XXXXXXXXXX................. 13 D<3> .X......................XX.............. 3 LAN_BASEADR<1> X..X........XXXXXXXXXXX................. 13 D<7> .X.......................X.X............ 3 D<1> .X.....................X.X.............. 3 LAN_BASEADR<15> X..X.X.......XXXXXXXXXX................. 13 D<8> .XX......................X..X........... 4 LAN_BASEADR<10> X..X..X......XXXXXXXXXX................. 13 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB3 *********************************** Number of function block inputs used/remaining: 2/52 Number of signals used by logic mapping into function block: 2 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB3_1 (b) IDE_W 0 0 0 5 FB3_2 28 I/O O (unused) 0 0 0 5 FB3_3 (b) (unused) 0 0 0 5 FB3_4 (b) (unused) 0 0 0 5 FB3_5 (b) (unused) 0 0 0 5 FB3_6 (b) (unused) 0 0 0 5 FB3_7 (b) (unused) 0 0 0 5 FB3_8 (b) (unused) 0 0 0 5 FB3_9 (b) (unused) 0 0 0 5 FB3_10 30 GCK/I/O GCK (unused) 0 0 0 5 FB3_11 (b) (unused) 0 0 0 5 FB3_12 31 I/O (unused) 0 0 0 5 FB3_13 (b) INT_OUT 1 0 0 4 FB3_14 32 GCK/I/O O (unused) 0 0 0 5 FB3_15 33 I/O (unused) 0 0 0 5 FB3_16 (b) (unused) 0 0 0 5 FB3_17 (b) (unused) 0 0 0 5 FB3_18 (b) Signals Used by Logic in Function Block 1: LAN_INT_ENABLE 2: LAN_IRQ_OUT Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs IDE_W ........................................ 0 INT_OUT XX...................................... 2 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB4 *********************************** Number of function block inputs used/remaining: 25/29 Number of signals used by logic mapping into function block: 25 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use LAN_SM_RST 1 0 0 4 FB4_1 (b) (b) D<0> 2 0 0 3 FB4_2 2 GTS/I/O I/O LAN_WR_RST 2 0 0 3 FB4_3 (b) (b) LAN_RST_SM_FSM_FFd1 2 0 0 3 FB4_4 (b) (b) A_LAN<1> 1 0 0 4 FB4_5 3 GTS/I/O O A_LAN<0> 1 0 0 4 FB4_6 4 I/O O LAN_IRQ_D0 2 0 0 3 FB4_7 (b) (b) A_LAN<3> 2 0 0 3 FB4_8 5 GTS/I/O O LAN_CS_RST 2 0 0 3 FB4_9 (b) (b) LAN_A_INIT<6> 2 0 0 3 FB4_10 (b) (b) DQ_9_IOBUFE/DQ_9_IOBUFE_TRST 2 0 0 3 FB4_11 (b) (b) A_LAN<2> 1 0 0 4 FB4_12 6 GTS/I/O O CONFIG_READY 2 0 0 3 FB4_13 (b) (b) A_LAN<5> 1 0 0 4 FB4_14 7 I/O O LAN_RST_SM_FSM_FFd3 3 0 0 2 FB4_15 (b) (b) LAN_RST_SM_FSM_FFd2 3 0 0 2 FB4_16 (b) (b) LAN_IRQ_OUT 3 0 0 2 FB4_17 (b) (b) LAN_INT_ENABLE 5 0 0 0 FB4_18 (b) (b) Signals Used by Logic in Function Block 1: $OpTx$FX_DC$32 10: LAN_RST_SM_FSM_FFd2 18: Z3_ADR<2> 2: BUF_CONFIG_READY 11: LAN_RST_SM_FSM_FFd3 19: Z3_ADR<4> 3: D_9_IOBUFE/D_9_IOBUFE_TRST 12: LDS 20: Z3_ADR_0 4: LAN_A_INIT<3> 13: A<23>.PIN 21: Z3_ADR_1 5: LAN_INT_ENABLE 14: D<15>.PIN 22: Z3_ADR_1/Z3_ADR_1_SETF 6: LAN_INT 15: RESET 23: Z3_A_LOW 7: LAN_IRQ_D0 16: RW 24: Z3_DATA<16> 8: LAN_IRQ_OUT 17: UDS 25: Z3_DATA<1>/Z3_DATA<1>_TRST 9: LAN_RST_SM_FSM_FFd1 Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs LAN_SM_RST XX...................X.................. 3 D<0> ..X....................XX............... 3 LAN_WR_RST .........XX...X......................... 3 LAN_RST_SM_FSM_FFd1 ........XXX...X......................... 4 A_LAN<1> ..............X....X.................... 2 A_LAN<0> ..............X.......X................. 2 LAN_IRQ_D0 .....X........X......................... 2 A_LAN<3> ...X..........X..X...................... 3 LAN_CS_RST .........XX...X......................... 3 LAN_A_INIT<6> ........X.....X......................... 2 DQ_9_IOBUFE/DQ_9_IOBUFE_TRST X.............X.........X............... 3 A_LAN<2> ..............X.....X................... 2 CONFIG_READY .X............X......................... 2 A_LAN<5> ..............X...X..................... 2 LAN_RST_SM_FSM_FFd3 ........XX....X......................... 3 LAN_RST_SM_FSM_FFd2 ........XXX...X......................... 4 LAN_IRQ_OUT .....XXX......X......................... 4 LAN_INT_ENABLE .X..X......XXXXXX....................... 8 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB5 *********************************** Number of function block inputs used/remaining: 29/25 Number of signals used by logic mapping into function block: 29 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use D_OUT<7> 2 0 0 3 FB5_1 (b) (b) CP_CS 0 0 0 5 FB5_2 34 I/O O D_OUT<3> 2 0 0 3 FB5_3 (b) (b) D_OUT<0> 2 0 0 3 FB5_4 (b) (b) ROM_OE 0 0 0 5 FB5_5 35 I/O O LAN_BASEADR<9> 3 0 0 2 FB5_6 (b) (b) LAN_BASEADR<8> 3 0 0 2 FB5_7 (b) (b) D_OUT<2> 3 0 0 2 FB5_8 38 GCK/I/O (b) AUTO_CONFIG_DONE_CYCLE 3 0 0 2 FB5_9 (b) (b) D<2> 2 0 0 3 FB5_10 39 I/O I/O D_OUT<6> 4 0 0 1 FB5_11 (b) (b) D<9> 3 0 0 2 FB5_12 40 I/O I/O D_OUT<4> 4 0 0 1 FB5_13 (b) (b) D<10> 3 0 0 2 FB5_14 41 I/O I/O D<11> 3 0 0 2 FB5_15 43 I/O I/O D_OUT<1> 4 0 0 1 FB5_16 (b) (b) D<12> 3 0 0 2 FB5_17 44 I/O I/O D_9_IOBUFE/D_9_IOBUFE_TRST 4 0 0 1 FB5_18 (b) (b) Signals Used by Logic in Function Block 1: $OpTx$FX_DC$10 11: D<9>.PIN 21: Z3_ADR<6> 2: AUTOCONFIG_ACCESS 12: D<8>.PIN 22: Z3_ADR_0 3: AUTO_CONFIG_DONE_CYCLE 13: RESET 23: Z3_ADR_1 4: D_9_IOBUFE/D_9_IOBUFE_TRST 14: RW 24: Z3_DATA<18> 5: D_OUT<1> 15: SLAVE 25: Z3_DATA<1>/Z3_DATA<1>_TRST 6: D_OUT<2> 16: UDS 26: Z3_DATA<25> 7: D_OUT<3> 17: Z3_ADR<2> 27: Z3_DATA<26> 8: D_OUT<4> 18: Z3_ADR<3> 28: Z3_DATA<27> 9: FCS 19: Z3_ADR<4> 29: Z3_DATA<28> 10: LDS 20: Z3_ADR<5> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs D_OUT<7> .X......X...X..X.XXXX.X................. 9 CP_CS ........................................ 0 D_OUT<3> .X......X...X..X.XXX..X................. 8 D_OUT<0> .X......X...X..XXXXX.XX................. 10 ROM_OE ........................................ 0 LAN_BASEADR<9> .X......X.X.XX.XXXXXXXX................. 13 LAN_BASEADR<8> .X......X..XXX.XXXXXXXX................. 13 D_OUT<2> .X......X...X..XXXXX.XX................. 10 AUTO_CONFIG_DONE_CYCLE .XX.....X...XX.XXXXXXX.................. 12 D<2> ...X...................XX............... 3 D_OUT<6> .X......X...X..XXXXXXXX................. 11 D<9> ...XX...................XX.............. 4 D_OUT<4> .X......X...X..XXXXXXXX................. 11 D<10> ...X.X..................X.X............. 4 D<11> ...X..X.................X..X............ 4 D_OUT<1> .X......X...X..XXXXX.XX................. 10 D<12> ...X...X................X...X........... 4 D_9_IOBUFE/D_9_IOBUFE_TRST XX......XX...XXX........X............... 8 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB6 *********************************** Number of function block inputs used/remaining: 31/23 Number of signals used by logic mapping into function block: 31 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use $OpTx$INV$1 16 11<- 0 0 FB6_1 (b) (b) LAN_CFG<2> 0 0 /\4 1 FB6_2 135 I/O O A_LAN<12> 1 0 0 4 FB6_3 136 I/O O (unused) 0 0 0 5 FB6_4 (b) A_LAN<13> 1 0 0 4 FB6_5 137 I/O O A_LAN<10> 1 0 0 4 FB6_6 138 I/O O (unused) 0 0 0 5 FB6_7 (b) A_LAN<11> 1 0 0 4 FB6_8 139 I/O O (unused) 0 0 0 5 FB6_9 (b) A_LAN<8> 1 0 0 4 FB6_10 140 I/O O (unused) 0 0 0 5 FB6_11 (b) (unused) 0 0 0 5 FB6_12 (b) (unused) 0 0 0 5 FB6_13 (b) A_LAN<9> 1 0 0 4 FB6_14 142 I/O O (unused) 0 0 0 5 FB6_15 143 GSR/I/O I N0$BUF7/N0$BUF7_TRST 2 0 \/1 2 FB6_16 (b) (b) $OpTx$INV$2 4 1<- \/2 0 FB6_17 (b) (b) (unused) 0 0 \/5 0 FB6_18 (b) (b) Signals Used by Logic in Function Block 1: AUTOCONFIG_ACCESS 12: LAN_BASEADR<6> 22: A<21>.PIN 2: CONFIG_READY 13: LAN_BASEADR<7> 23: A<16>.PIN 3: FCS 14: LAN_READY 24: A<22>.PIN 4: LAN_BASEADR<0> 15: A<17>.PIN 25: RESET 5: LAN_BASEADR<13> 16: A<23>.PIN 26: Z3_ADR<10> 6: LAN_BASEADR<14> 17: A<18>.PIN 27: Z3_ADR<11> 7: LAN_BASEADR<1> 18: A<19>.PIN 28: Z3_ADR<12> 8: LAN_BASEADR<2> 19: D<14>.PIN 29: Z3_ADR<7> 9: LAN_BASEADR<3> 20: D<13>.PIN 30: Z3_ADR<8> 10: LAN_BASEADR<4> 21: A<20>.PIN 31: Z3_ADR<9> 11: LAN_BASEADR<5> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs $OpTx$INV$1 ...X.XXXXXX.X.XXXXX.XXX................. 16 LAN_CFG<2> ........................................ 0 A_LAN<12> ........................X.X............. 2 A_LAN<13> ........................X..X............ 2 A_LAN<10> ........................X.....X......... 2 A_LAN<11> ........................XX.............. 2 A_LAN<8> ........................X...X........... 2 A_LAN<9> ........................X....X.......... 2 N0$BUF7/N0$BUF7_TRST XXX..........X.......................... 4 $OpTx$INV$2 ....X......X.......X...X................ 4 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB7 *********************************** Number of function block inputs used/remaining: 31/23 Number of signals used by logic mapping into function block: 31 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 /\1 4 FB7_1 (b) (b) (unused) 0 0 0 5 FB7_2 (b) D<13> 3 0 0 2 FB7_3 45 I/O I/O (unused) 0 0 0 5 FB7_4 (b) D<14> 3 0 0 2 FB7_5 46 I/O I/O (unused) 0 0 0 5 FB7_6 (b) (unused) 0 0 0 5 FB7_7 (b) LAN_A_INIT<3> 1 0 0 4 FB7_8 (b) (b) Z3_ADR_1 3 0 0 2 FB7_9 (b) (b) Z3_ADR_0 3 0 0 2 FB7_10 (b) (b) Z3_ADR<9> 3 0 0 2 FB7_11 (b) (b) D<15> 3 0 0 2 FB7_12 48 I/O I/O Z3_ADR<8> 3 0 0 2 FB7_13 (b) (b) Z3_ADR<7> 3 0 0 2 FB7_14 (b) (b) Z3_ADR<6> 3 0 0 2 FB7_15 49 I/O I Z3_ADR<5> 3 0 \/1 1 FB7_16 (b) (b) DQ_DATA<9> 6 1<- 0 0 FB7_17 (b) (b) DQ_DATA<1> 6 1<- 0 0 FB7_18 (b) (b) Signals Used by Logic in Function Block 1: $OpTx$FX_DC$16 12: D_OUT<6> 22: A<8>.PIN 2: $OpTx$FX_DC$8 13: D_OUT<7> 23: A<9>.PIN 3: $OpTx$FX_SC$18 14: FCS 24: D<9>.PIN 4: A<2> 15: LAN_SM_FSM_FFd2 25: D<1>.PIN 5: A<3> 16: LAN_SM_FSM_FFd3 26: RESET 6: A<7> 17: LAN_SM_FSM_FFd4 27: Z3_ADR_1/Z3_ADR_1_SETF 7: DQ_DATA<1> 18: LAN_SM_RST 28: Z3_DATA<1>/Z3_DATA<1>_TRST 8: DQ_DATA<9> 19: A<10>.PIN 29: Z3_DATA<29> 9: DQ_SWAP 20: A<11>.PIN 30: Z3_DATA<30> 10: D_9_IOBUFE/D_9_IOBUFE_TRST 21: A<17>.PIN 31: Z3_DATA<31> 11: D_OUT<5> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs D<13> .........XX................XX........... 4 D<14> .........X.X...............X.X.......... 4 LAN_A_INIT<3> .........................X.............. 1 Z3_ADR_1 ....X........X............X............. 3 Z3_ADR_0 ...X.........X............X............. 3 Z3_ADR<9> .............X.....X......X............. 3 D<15> .........X..X..............X..X......... 4 Z3_ADR<8> .............X....X.......X............. 3 Z3_ADR<7> .............X........X...X............. 3 Z3_ADR<6> .............X.......X....X............. 3 Z3_ADR<5> .....X.......X............X............. 3 DQ_DATA<9> XXX....XX.....XXXX..X.XXX............... 13 DQ_DATA<1> XXX...X.X.....XXXX..X.XXX............... 13 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB8 *********************************** Number of function block inputs used/remaining: 32/22 Number of signals used by logic mapping into function block: 32 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB8_1 (b) DQ<12> 2 0 0 3 FB8_2 130 I/O I/O DQ<14> 2 0 0 3 FB8_3 131 I/O I/O (unused) 0 0 0 5 FB8_4 (b) LAN_WRH 2 0 0 3 FB8_5 132 I/O O BUF_CONFIG_READY 1 0 0 4 FB8_6 (b) (b) $OpTx$FX_DC$24 1 0 0 4 FB8_7 (b) (b) LAN_CS 2 0 0 3 FB8_8 133 I/O O $OpTx$FX_DC$32 2 0 0 3 FB8_9 (b) (b) LAN_RD 1 0 0 4 FB8_10 134 I/O O Z3_ADR<3> 3 0 0 2 FB8_11 (b) (b) Z3_ADR<2> 3 0 0 2 FB8_12 (b) (b) Z3_ADR<13> 3 0 0 2 FB8_13 (b) (b) Z3_ADR<12> 3 0 0 2 FB8_14 (b) (b) Z3_ADR<11> 3 0 0 2 FB8_15 (b) (b) Z3_ADR<10> 3 0 0 2 FB8_16 (b) (b) LAN_ACCESS 4 0 0 1 FB8_17 (b) (b) DQ_SWAP 4 0 0 1 FB8_18 (b) (b) Signals Used by Logic in Function Block 1: $OpTx$FX_DC$10 12: A<5> 23: A<12>.PIN 2: $OpTx$FX_DC$24 13: DQ_9_IOBUFE/DQ_9_IOBUFE_TRST 24: A<13>.PIN 3: $OpTx$FX_DC$35 14: DQ_DATA<12> 25: D<12>.PIN 4: $OpTx$FX_DC$36 15: DQ_DATA<14> 26: A<14>.PIN 5: $OpTx$FX_DC$37 16: FCS 27: A<15>.PIN 6: $OpTx$FX_DC$38 17: LAN_ACCESS 28: RESET 7: $OpTx$FX_DC$39 18: LAN_BASEADR<12> 29: SHUT_UP 8: $OpTx$FX_DC$8 19: LAN_CS_RST 30: Z3_ADR<13> 9: $OpTx$INV$1 20: LAN_RD_S 31: Z3_ADR_1/Z3_ADR_1_SETF 10: $OpTx$INV$2 21: LAN_WRH_S 32: Z3 11: A<4> 22: LAN_WR_RST Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs DQ<12> ............XX.............X............ 3 DQ<14> ............X.X............X............ 3 LAN_WRH .X..................XX.................. 3 BUF_CONFIG_READY ...............XX............X.......... 3 $OpTx$FX_DC$24 ...............X...........X............ 2 LAN_CS ................X.X........X............ 3 $OpTx$FX_DC$32 X......X.......XX....................... 4 LAN_RD .X.................X.................... 2 Z3_ADR<3> ...........X...X..............X......... 3 Z3_ADR<2> ..........X....X..............X......... 3 Z3_ADR<13> ...............X..........X...X......... 3 Z3_ADR<12> ...............X.........X....X......... 3 Z3_ADR<11> ...............X.......X......X......... 3 Z3_ADR<10> ...............X......X.......X......... 3 LAN_ACCESS ..XXXXX.XX.....X.X......X...X.XX........ 13 DQ_SWAP ..XXXXX.XX.....X.X.....XXX..X.XX........ 15 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB9 *********************************** Number of function block inputs used/remaining: 31/23 Number of signals used by logic mapping into function block: 31 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use DQ_DATA<4> 6 2<- /\1 0 FB9_1 (b) (b) (unused) 0 0 /\2 3 FB9_2 50 I/O I (unused) 0 0 0 5 FB9_3 51 I/O I (unused) 0 0 0 5 FB9_4 (b) (unused) 0 0 0 5 FB9_5 52 I/O I (unused) 0 0 0 5 FB9_6 53 I/O I (unused) 0 0 0 5 FB9_7 (b) (unused) 0 0 0 5 FB9_8 54 I/O I (unused) 0 0 0 5 FB9_9 (b) (unused) 0 0 0 5 FB9_10 (b) A<8> 5 0 0 0 FB9_11 56 I/O I/O LAN_WRH_S 3 0 \/1 1 FB9_12 57 I/O (b) DQ_DATA<5> 6 1<- 0 0 FB9_13 (b) (b) A<9> 5 0 0 0 FB9_14 58 I/O I/O (unused) 0 0 \/1 4 FB9_15 (b) (b) DQ_DATA<13> 6 1<- 0 0 FB9_16 (b) (b) A<10> 5 0 0 0 FB9_17 59 I/O I/O DQ_DATA<12> 6 1<- 0 0 FB9_18 (b) (b) Signals Used by Logic in Function Block 1: $OpTx$FX_DC$16 12: LAN_SM_FSM_FFd2 22: A<13>.PIN 2: $OpTx$FX_DC$32 13: LAN_SM_FSM_FFd3 23: DQ<1>.PIN 3: $OpTx$FX_DC$8 14: LAN_SM_FSM_FFd4 24: DQ<0>.PIN 4: $OpTx$FX_SC$18 15: LAN_SM_RST 25: D<13>.PIN 5: DQ_DATA<12> 16: LDS 26: D<12>.PIN 6: DQ_DATA<13> 17: A<12>.PIN 27: D<5>.PIN 7: DQ_DATA<4> 18: DQ<10>.PIN 28: D<4>.PIN 8: DQ_DATA<5> 19: DQ<9>.PIN 29: A<20>.PIN 9: DQ_SWAP 20: DQ<8>.PIN 30: A<21>.PIN 10: DS0 21: DQ<2>.PIN 31: RW 11: LAN_SM_FSM_FFd1 Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs DQ_DATA<4> X.XX..X.X..XXXX.X........X.XX........... 13 A<8> .X......X.XXXXX....X...X......X......... 10 LAN_WRH_S .........XXXXXXX........................ 7 DQ_DATA<5> X.XX...XX..XXXX......X..X.X..X.......... 13 A<9> .X......X.XXXXX...X...X.......X......... 10 DQ_DATA<13> X.XX.X..X..XXXX......X..X.X..X.......... 13 A<10> .X......X.XXXXX..X..X.........X......... 10 DQ_DATA<12> X.XXX...X..XXXX.X........X.XX........... 13 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB10 *********************************** Number of function block inputs used/remaining: 31/23 Number of signals used by logic mapping into function block: 31 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use SHUT_UP 2 0 0 3 FB10_1 (b) (b) DQ<1> 3 0 0 2 FB10_2 117 I/O I/O DQ<0> 2 0 0 3 FB10_3 118 I/O I/O LAN_BASEADR<6> 3 0 0 2 FB10_4 (b) (b) DQ<3> 2 0 0 3 FB10_5 119 I/O I/O DQ<2> 2 0 0 3 FB10_6 120 I/O I/O LAN_BASEADR<14> 3 0 0 2 FB10_7 (b) (b) DQ<5> 2 0 0 3 FB10_8 121 I/O I/O LAN_BASEADR<13> 3 0 0 2 FB10_9 (b) (b) DQ<4> 3 0 0 2 FB10_10 124 I/O I/O DQ<7> 2 0 0 3 FB10_11 125 I/O I/O DQ<6> 2 0 0 3 FB10_12 126 I/O I/O LAN_BASEADR<12> 3 0 0 2 FB10_13 (b) (b) DQ<8> 3 0 0 2 FB10_14 128 I/O I/O LAN_BASEADR<11> 3 0 0 2 FB10_15 (b) (b) LAN_BASEADR<0> 3 0 0 2 FB10_16 (b) (b) DQ<10> 3 0 0 2 FB10_17 129 I/O I/O D_OUT<5> 4 0 0 1 FB10_18 (b) (b) Signals Used by Logic in Function Block 1: AUTOCONFIG_ACCESS 12: DQ_DATA<8> 22: RESET 2: DQ_9_IOBUFE/DQ_9_IOBUFE_TRST 13: FCS 23: RW 3: DQ_DATA<0> 14: LAN_D_INIT<1> 24: UDS 4: DQ_DATA<10> 15: LAN_D_INIT<8> 25: Z3_ADR<2> 5: DQ_DATA<1> 16: D<14>.PIN 26: Z3_ADR<3> 6: DQ_DATA<2> 17: D<13>.PIN 27: Z3_ADR<4> 7: DQ_DATA<3> 18: D<12>.PIN 28: Z3_ADR<5> 8: DQ_DATA<4> 19: D<11>.PIN 29: Z3_ADR<6> 9: DQ_DATA<5> 20: D<6>.PIN 30: Z3_ADR_0 10: DQ_DATA<6> 21: D<0>.PIN 31: Z3_ADR_1 11: DQ_DATA<7> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs SHUT_UP X...........X........XXXXXXXXXX......... 12 DQ<1> .X..X........X.......X.................. 4 DQ<0> .XX..................X.................. 3 LAN_BASEADR<6> X...........X......X.XXXXXXXXXX......... 13 DQ<3> .X....X..............X.................. 3 DQ<2> .X...X...............X.................. 3 LAN_BASEADR<14> X...........X..X.....XXXXXXXXXX......... 13 DQ<5> .X......X............X.................. 3 LAN_BASEADR<13> X...........X...X....XXXXXXXXXX......... 13 DQ<4> .X.....X.....X.......X.................. 4 DQ<7> .X........X..........X.................. 3 DQ<6> .X.......X...........X.................. 3 LAN_BASEADR<12> X...........X....X...XXXXXXXXXX......... 13 DQ<8> .X.........X..X......X.................. 4 LAN_BASEADR<11> X...........X.....X..XXXXXXXXXX......... 13 LAN_BASEADR<0> X...........X.......XXXXXXXXXXX......... 13 DQ<10> .X.X..........X......X.................. 4 D_OUT<5> X...........X........X.XXXXXXXX......... 11 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB11 *********************************** Number of function block inputs used/remaining: 28/26 Number of signals used by logic mapping into function block: 28 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use Z3_DATA<31> 4 0 /\1 0 FB11_1 (b) (b) Z3_DATA<30> 4 0 0 1 FB11_2 (b) (b) A<11> 5 0 0 0 FB11_3 60 I/O I/O Z3_DATA<29> 4 0 0 1 FB11_4 (b) (b) A<12> 5 0 0 0 FB11_5 61 I/O I/O Z3_DATA<23> 4 0 0 1 FB11_6 (b) (b) Z3_DATA<22> 4 0 0 1 FB11_7 (b) (b) Z3_DATA<21> 4 0 0 1 FB11_8 (b) (b) LAN_SM_FSM_FFd2 4 0 0 1 FB11_9 (b) (b) A<13> 5 0 0 0 FB11_10 64 I/O I/O A<14> 5 0 0 0 FB11_11 66 I/O I/O ROM_B<0> 0 0 0 5 FB11_12 68 I/O O LAN_RD_S 4 0 0 1 FB11_13 (b) (b) ROM_B<1> 0 0 \/1 4 FB11_14 69 I/O O LAN_SM_FSM_FFd4 6 1<- 0 0 FB11_15 (b) (b) DQ_DATA<8> 6 1<- 0 0 FB11_16 (b) (b) CP_WE 0 0 /\1 4 FB11_17 70 I/O O DQ_DATA<0> 6 1<- 0 0 FB11_18 (b) (b) Signals Used by Logic in Function Block 1: $OpTx$FX_DC$10 11: LAN_SM_FSM_FFd3 20: DQ<7>.PIN 2: $OpTx$FX_DC$16 12: LAN_SM_FSM_FFd4 21: DQ<6>.PIN 3: $OpTx$FX_DC$32 13: LAN_SM_RST 22: DQ<5>.PIN 4: $OpTx$FX_DC$8 14: A<8>.PIN 23: DQ<4>.PIN 5: $OpTx$FX_SC$18 15: DQ<15>.PIN 24: DQ<3>.PIN 6: DQ_DATA<0> 16: DQ<14>.PIN 25: D<8>.PIN 7: DQ_DATA<8> 17: DQ<13>.PIN 26: D<0>.PIN 8: DQ_SWAP 18: DQ<12>.PIN 27: A<16>.PIN 9: LAN_SM_FSM_FFd1 19: DQ<11>.PIN 28: RW 10: LAN_SM_FSM_FFd2 Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs Z3_DATA<31> .......XXXXXX.X....X.................... 8 Z3_DATA<30> .......XXXXXX..X....X................... 8 A<11> ..X....XXXXXX.....X....X...X............ 10 Z3_DATA<29> .......XXXXXX...X....X.................. 8 A<12> ..X....XXXXXX....X....X....X............ 10 Z3_DATA<23> .......XXXXXX.X....X.................... 8 Z3_DATA<22> .......XXXXXX..X....X................... 8 Z3_DATA<21> .......XXXXXX...X....X.................. 8 LAN_SM_FSM_FFd2 ...X....XXXXX..............X............ 7 A<13> ..X....XXXXXX...X....X.....X............ 10 A<14> ..X....XXXXXX..X....X......X............ 10 ROM_B<0> ........................................ 0 LAN_RD_S ........XXXXX..............X............ 6 ROM_B<1> ........................................ 0 LAN_SM_FSM_FFd4 X.......XXXXX..............X............ 7 DQ_DATA<8> .X.XX.XX.XXXXX..........XXX............. 13 CP_WE ........................................ 0 DQ_DATA<0> .X.XXX.X.XXXXX..........XXX............. 13 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB12 *********************************** Number of function block inputs used/remaining: 31/23 Number of signals used by logic mapping into function block: 31 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB12_1 (b) LAN_CFG<4> 0 0 0 5 FB12_2 110 I/O O (unused) 0 0 0 5 FB12_3 111 I/O I (unused) 0 0 0 5 FB12_4 (b) DQ<15> 2 0 0 3 FB12_5 112 I/O I/O (unused) 0 0 0 5 FB12_6 (b) (unused) 0 0 0 5 FB12_7 (b) DQ<13> 2 0 0 3 FB12_8 113 I/O I/O (unused) 0 0 0 5 FB12_9 (b) DQ<11> 3 0 0 2 FB12_10 115 I/O I/O (unused) 0 0 0 5 FB12_11 (b) DQ<9> 3 0 0 2 FB12_12 116 I/O I/O (unused) 0 0 0 5 FB12_13 (b) (unused) 0 0 0 5 FB12_14 (b) Z3_ADR_1/Z3_ADR_1_SETF 1 0 0 4 FB12_15 (b) (b) LAN_D_INIT<8> 2 0 0 3 FB12_16 (b) (b) LAN_D_INIT<1> 2 0 0 3 FB12_17 (b) (b) AUTOCONFIG_ACCESS 3 0 0 2 FB12_18 (b) (b) Signals Used by Logic in Function Block 1: BERR 12: LAN_RST_SM_FSM_FFd1 22: D<10>.PIN 2: CFIN 13: A<17>.PIN 23: D<9>.PIN 3: CFOUT 14: A<23>.PIN 24: D<8>.PIN 4: DQ_9_IOBUFE/DQ_9_IOBUFE_TRST 15: A<18>.PIN 25: A<20>.PIN 5: DQ_DATA<11> 16: A<19>.PIN 26: A<21>.PIN 6: DQ_DATA<13> 17: D<15>.PIN 27: A<16>.PIN 7: DQ_DATA<15> 18: D<14>.PIN 28: A<22>.PIN 8: DQ_DATA<9> 19: D<13>.PIN 29: RESET 9: FCS 20: D<12>.PIN 30: Z3_ADR_1/Z3_ADR_1_SETF 10: LAN_D_INIT<1> 21: D<11>.PIN 31: Z3 11: LAN_D_INIT<8> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs LAN_CFG<4> ........................................ 0 DQ<15> ...X..X.....................X........... 3 DQ<13> ...X.X......................X........... 3 DQ<11> ...XX.....X.................X........... 4 DQ<9> ...X...X.X..................X........... 4 Z3_ADR_1/Z3_ADR_1_SETF X...........................X........... 2 LAN_D_INIT<8> ...........X................X........... 2 LAN_D_INIT<1> ...........X................X........... 2 AUTOCONFIG_ACCESS .XX.....X...XXXXXXXXXXXXXXXX.XX......... 21 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB13 *********************************** Number of function block inputs used/remaining: 31/23 Number of signals used by logic mapping into function block: 31 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use LAN_READY 2 0 /\2 1 FB13_1 (b) (b) CP_RD 0 0 0 5 FB13_2 71 I/O O (unused) 0 0 0 5 FB13_3 (b) (unused) 0 0 0 5 FB13_4 (b) (unused) 0 0 0 5 FB13_5 (b) (unused) 0 0 0 5 FB13_6 (b) (unused) 0 0 0 5 FB13_7 (b) A<15> 5 0 0 0 FB13_8 74 I/O I/O (unused) 0 0 0 5 FB13_9 (b) (unused) 0 0 0 5 FB13_10 (b) (unused) 0 0 0 5 FB13_11 75 I/O I (unused) 0 0 0 5 FB13_12 (b) LAN_WRL_S 3 0 0 2 FB13_13 (b) (b) LAN_WRL 2 0 \/2 1 FB13_14 76 I/O O DQ_DATA<7> 6 2<- \/1 0 FB13_15 77 I/O I DQ_DATA<6> 6 1<- 0 0 FB13_16 (b) (b) DQ_DATA<15> 6 1<- 0 0 FB13_17 78 I/O I DQ_DATA<14> 6 2<- /\1 0 FB13_18 (b) (b) Signals Used by Logic in Function Block 1: $OpTx$FX_DC$16 12: DS1 22: DQ<7>.PIN 2: $OpTx$FX_DC$24 13: LAN_SM_FSM_FFd1 23: D<15>.PIN 3: $OpTx$FX_DC$32 14: LAN_SM_FSM_FFd2 24: D<14>.PIN 4: $OpTx$FX_DC$8 15: LAN_SM_FSM_FFd3 25: A<14>.PIN 5: $OpTx$FX_SC$18 16: LAN_SM_FSM_FFd4 26: D<7>.PIN 6: BUF_LAN_READY 17: LAN_SM_RST 27: D<6>.PIN 7: DQ_DATA<14> 18: LAN_WRL_S 28: A<15>.PIN 8: DQ_DATA<15> 19: LAN_WR_RST 29: A<22>.PIN 9: DQ_DATA<6> 20: A<23>.PIN 30: RW 10: DQ_DATA<7> 21: DQ<15>.PIN 31: UDS 11: DQ_SWAP Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs LAN_READY .....X..........X....................... 2 CP_RD ........................................ 0 A<15> ..X.......X.XXXXX...XX.......X.......... 10 LAN_WRL_S ...........XXXXXX.............X......... 7 LAN_WRL .X...............XX..................... 3 DQ_DATA<7> X..XX....XX..XXXX..X..X..X.X............ 13 DQ_DATA<6> X..XX...X.X..XXXX......XX.X.X........... 13 DQ_DATA<15> X..XX..X..X..XXXX..X..X..X.X............ 13 DQ_DATA<14> X..XX.X...X..XXXX......XX.X.X........... 13 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB14 *********************************** Number of function block inputs used/remaining: 23/31 Number of signals used by logic mapping into function block: 23 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB14_1 (b) (unused) 0 0 0 5 FB14_2 (b) OVR 1 0 0 4 FB14_3 100 I/O O (unused) 0 0 0 5 FB14_4 (b) (unused) 0 0 0 5 FB14_5 101 I/O (unused) 0 0 0 5 FB14_6 102 I/O (unused) 0 0 0 5 FB14_7 (b) $OpTx$FX_DC$8 1 0 0 4 FB14_8 103 I/O (b) $OpTx$FX_DC$10 1 0 0 4 FB14_9 (b) (b) $OpTx$FX_DC$39 2 0 0 3 FB14_10 104 I/O I CFOUT 3 0 0 2 FB14_11 105 I/O O $OpTx$FX_DC$38 2 0 0 3 FB14_12 (b) (b) $OpTx$FX_DC$37 2 0 0 3 FB14_13 (b) (b) SLAVE 2 0 0 3 FB14_14 106 I/O O OWN 0 0 0 5 FB14_15 107 I/O O $OpTx$FX_DC$36 2 0 0 3 FB14_16 (b) (b) $OpTx$FX_DC$35 2 0 0 3 FB14_17 (b) (b) Z3_ADR<4> 3 0 0 2 FB14_18 (b) (b) Signals Used by Logic in Function Block 1: AUTOBOOT_OFF 9: LAN_BASEADR<10> 17: D<10>.PIN 2: AUTOCONFIG_ACCESS 10: LAN_BASEADR<11> 18: D<9>.PIN 3: AUTO_CONFIG_DONE_CYCLE 11: LAN_BASEADR<15> 19: D<8>.PIN 4: A<6> 12: LAN_BASEADR<8> 20: RESET 5: DS0 13: LAN_BASEADR<9> 21: SLAVE 6: DS1 14: LDS 22: UDS 7: FCS 15: D<15>.PIN 23: Z3_ADR_1/Z3_ADR_1_SETF 8: LAN_ACCESS 16: D<11>.PIN Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs OVR ....................X................... 1 $OpTx$FX_DC$8 .............X.......X.................. 2 $OpTx$FX_DC$10 ....XX.................................. 2 $OpTx$FX_DC$39 ..........X...X......................... 2 CFOUT X.X...X............X.................... 4 $OpTx$FX_DC$38 ...........X......X..................... 2 $OpTx$FX_DC$37 ............X....X...................... 2 SLAVE .X....XX................................ 3 OWN ........................................ 0 $OpTx$FX_DC$36 ........X.......X....................... 2 $OpTx$FX_DC$35 .........X.....X........................ 2 Z3_ADR<4> ...X..X...............X................. 3 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB15 *********************************** Number of function block inputs used/remaining: 31/23 Number of signals used by logic mapping into function block: 31 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use DQ_DATA<10> 6 3<- \/2 0 FB15_1 (b) (b) DQ_DATA<11> 6 2<- \/1 0 FB15_2 79 I/O I DQ_DATA<2> 6 1<- 0 0 FB15_3 80 I/O (b) DQ_DATA<3> 6 1<- 0 0 FB15_4 (b) (b) BUF_LAN_READY 5 1<- /\1 0 FB15_5 (b) (b) LAN_SM_FSM_FFd1 3 0 /\1 1 FB15_6 (b) (b) $OpTx$FX_DC$16 2 0 0 3 FB15_7 (b) (b) $OpTx$FX_SC$18 2 0 0 3 FB15_8 81 I/O I Z3_DATA<1>/Z3_DATA<1>_TRST 1 0 0 4 FB15_9 (b) (b) (unused) 0 0 0 5 FB15_10 82 I/O I (unused) 0 0 0 5 FB15_11 83 I/O I DTACK 1 0 0 4 FB15_12 85 I/O O (unused) 0 0 0 5 FB15_13 (b) A<23> 5 0 0 0 FB15_14 86 I/O I/O A<22> 5 0 0 0 FB15_15 87 I/O I/O (unused) 0 0 0 5 FB15_16 (b) A<21> 5 0 0 0 FB15_17 88 I/O I/O (unused) 0 0 \/3 2 FB15_18 (b) (b) Signals Used by Logic in Function Block 1: $OpTx$FX_DC$10 12: LAN_SM_FSM_FFd2 22: DQ<14>.PIN 2: $OpTx$FX_DC$16 13: LAN_SM_FSM_FFd3 23: DQ<13>.PIN 3: $OpTx$FX_DC$32 14: LAN_SM_FSM_FFd4 24: DQ<7>.PIN 4: $OpTx$FX_DC$8 15: LAN_SM_RST 25: DQ<6>.PIN 5: $OpTx$FX_SC$18 16: N0$BUF7/N0$BUF7_TRST 26: DQ<5>.PIN 6: DQ_DATA<10> 17: A<10>.PIN 27: D<11>.PIN 7: DQ_DATA<11> 18: A<11>.PIN 28: D<10>.PIN 8: DQ_DATA<2> 19: A<18>.PIN 29: D<3>.PIN 9: DQ_DATA<3> 20: A<19>.PIN 30: D<2>.PIN 10: DQ_SWAP 21: DQ<15>.PIN 31: RW 11: LAN_SM_FSM_FFd1 Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs DQ_DATA<10> .X.XXX...X.XXXX.X.X........X.X.......... 13 DQ_DATA<11> .X.XX.X..X.XXXX..X.X......X.X........... 13 DQ_DATA<2> .X.XX..X.X.XXXX.X.X........X.X.......... 13 DQ_DATA<3> .X.XX...XX.XXXX..X.X......X.X........... 13 BUF_LAN_READY X.........XXXX.......................... 5 LAN_SM_FSM_FFd1 X.........X.XXX......................... 5 $OpTx$FX_DC$16 ..........XXXX.......................... 4 $OpTx$FX_SC$18 ...X......XXXX.......................... 5 Z3_DATA<1>/Z3_DATA<1>_TRST ..X...........................X......... 2 DTACK ...............X........................ 1 A<23> ..X......XXXXXX.....X..X......X......... 10 A<22> ..X......XXXXXX......X..X.....X......... 10 A<21> ..X......XXXXXX.......X..X....X......... 10 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB16 *********************************** Number of function block inputs used/remaining: 21/33 Number of signals used by logic mapping into function block: 21 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use Z3_DATA<28> 4 0 0 1 FB16_1 (b) (b) A<20> 5 0 0 0 FB16_2 91 I/O I/O A<19> 5 0 0 0 FB16_3 92 I/O I/O Z3_DATA<27> 4 0 0 1 FB16_4 (b) (b) Z3_DATA<26> 4 0 0 1 FB16_5 93 I/O I A<18> 5 0 0 0 FB16_6 94 I/O I/O Z3_DATA<25> 4 0 0 1 FB16_7 (b) (b) A<17> 5 0 0 0 FB16_8 95 I/O I/O Z3_DATA<24> 4 0 0 1 FB16_9 (b) (b) MTACK 0 0 0 5 FB16_10 96 I/O O A<16> 5 0 0 0 FB16_11 97 I/O I/O Z3_DATA<20> 4 0 0 1 FB16_12 98 I/O I Z3_DATA<19> 4 0 0 1 FB16_13 (b) (b) Z3_DATA<17> 4 0 0 1 FB16_14 (b) (b) Z3_DATA<16> 4 0 \/1 0 FB16_15 (b) (b) Z3_A_LOW 6 1<- 0 0 FB16_16 (b) (b) LAN_SM_FSM_FFd3 6 1<- 0 0 FB16_17 (b) (b) Z3_DATA<18> 4 0 /\1 0 FB16_18 (b) (b) Signals Used by Logic in Function Block 1: $OpTx$FX_DC$10 8: LAN_SM_FSM_FFd3 15: DQ<8>.PIN 2: $OpTx$FX_DC$32 9: LAN_SM_FSM_FFd4 16: DQ<4>.PIN 3: $OpTx$FX_DC$8 10: LAN_SM_RST 17: DQ<3>.PIN 4: BUF_LAN_READY 11: DQ<12>.PIN 18: DQ<2>.PIN 5: DQ_SWAP 12: DQ<11>.PIN 19: DQ<1>.PIN 6: LAN_SM_FSM_FFd1 13: DQ<10>.PIN 20: DQ<0>.PIN 7: LAN_SM_FSM_FFd2 14: DQ<9>.PIN 21: RW Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs Z3_DATA<28> ....XXXXXXX....X........................ 8 A<20> .X..XXXXXXX....X....X................... 10 A<19> .X..XXXXXX.X....X...X................... 10 Z3_DATA<27> ....XXXXXX.X....X....................... 8 Z3_DATA<26> ....XXXXXX..X....X...................... 8 A<18> .X..XXXXXX..X....X..X................... 10 Z3_DATA<25> ....XXXXXX...X....X..................... 8 A<17> .X..XXXXXX...X....X.X................... 10 Z3_DATA<24> ....XXXXXX....X....X.................... 8 MTACK ........................................ 0 A<16> .X..XXXXXX....X....XX................... 10 Z3_DATA<20> ....XXXXXXX....X........................ 8 Z3_DATA<19> ....XXXXXX.X....X....................... 8 Z3_DATA<17> ....XXXXXX...X....X..................... 8 Z3_DATA<16> ....XXXXXX....X....X.................... 8 Z3_A_LOW X.XX.XXXXX.............................. 8 LAN_SM_FSM_FFd3 X.X..XXXXX..........X................... 8 Z3_DATA<18> ....XXXXXX..X....X...................... 8 0----+----1----+----2----+----3----+----4 0 0 0 0 ******************************* Equations ******************************** ********** Mapped Logic ********** $OpTx$FX_DC$10 <= (DS1 AND DS0); $OpTx$FX_DC$16 <= ((LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd1 AND NOT LAN_SM_FSM_FFd3) OR (NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1 AND NOT LAN_SM_FSM_FFd3)); $OpTx$FX_DC$24 <= (NOT FCS AND RESET); $OpTx$FX_DC$32 <= ((NOT FCS AND LAN_ACCESS AND NOT $OpTx$FX_DC$8) OR (NOT FCS AND LAN_ACCESS AND NOT $OpTx$FX_DC$10)); $OpTx$FX_DC$35 <= D(11).PIN XOR $OpTx$FX_DC$35 <= LAN_BASEADR(11); $OpTx$FX_DC$36 <= D(10).PIN XOR $OpTx$FX_DC$36 <= LAN_BASEADR(10); $OpTx$FX_DC$37 <= D(9).PIN XOR $OpTx$FX_DC$37 <= LAN_BASEADR(9); $OpTx$FX_DC$38 <= D(8).PIN XOR $OpTx$FX_DC$38 <= LAN_BASEADR(8); $OpTx$FX_DC$39 <= D(15).PIN XOR $OpTx$FX_DC$39 <= LAN_BASEADR(15); $OpTx$FX_DC$8 <= (UDS AND LDS); $OpTx$FX_SC$18 <= ((LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd1 AND NOT LAN_SM_FSM_FFd3) OR (NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3 AND $OpTx$FX_DC$8)); $OpTx$INV$1 <= ((D(14).PIN AND NOT LAN_BASEADR(14)) OR (NOT D(14).PIN AND LAN_BASEADR(14)) OR (LAN_BASEADR(7) AND NOT A(23).PIN) OR (NOT LAN_BASEADR(7) AND A(23).PIN) OR ($OpTx$INV$2.EXP) OR (A(20).PIN AND NOT LAN_BASEADR(4)) OR (NOT A(20).PIN AND LAN_BASEADR(4)) OR (NOT A(19).PIN AND LAN_BASEADR(3)) OR (LAN_BASEADR(5) AND NOT A(21).PIN) OR (NOT LAN_BASEADR(5) AND A(21).PIN) OR (A(19).PIN AND NOT LAN_BASEADR(3)) OR (A(18).PIN AND NOT LAN_BASEADR(2)) OR (NOT A(18).PIN AND LAN_BASEADR(2)) OR (A(17).PIN AND NOT LAN_BASEADR(1)) OR (NOT A(17).PIN AND LAN_BASEADR(1))); $OpTx$INV$2 <= ((NOT D(13).PIN AND LAN_BASEADR(13)) OR (D(13).PIN AND NOT LAN_BASEADR(13)) OR (LAN_BASEADR(6) AND NOT A(22).PIN) OR (NOT LAN_BASEADR(6) AND A(22).PIN)); FDCPE_A8: FDCPE port map (A_I(8),A(8),CLK_EXT,'0',LAN_SM_RST,A_CE(8)); A(8) <= ((DQ_SWAP AND DQ(8).PIN) OR (NOT DQ_SWAP AND DQ(0).PIN)); A_CE(8) <= (NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1 AND NOT LAN_SM_FSM_FFd3); A(8) <= A_I(8) when A_OE(8) = '1' else 'Z'; A_OE(8) <= (RW AND $OpTx$FX_DC$32); FDCPE_A9: FDCPE port map (A_I(9),A(9),CLK_EXT,'0',LAN_SM_RST,A_CE(9)); A(9) <= ((DQ_SWAP AND DQ(9).PIN) OR (NOT DQ_SWAP AND DQ(1).PIN)); A_CE(9) <= (NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1 AND NOT LAN_SM_FSM_FFd3); A(9) <= A_I(9) when A_OE(9) = '1' else 'Z'; A_OE(9) <= (RW AND $OpTx$FX_DC$32); FDCPE_A10: FDCPE port map (A_I(10),A(10),CLK_EXT,'0',LAN_SM_RST,A_CE(10)); A(10) <= ((DQ_SWAP AND DQ(10).PIN) OR (NOT DQ_SWAP AND DQ(2).PIN)); A_CE(10) <= (NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1 AND NOT LAN_SM_FSM_FFd3); A(10) <= A_I(10) when A_OE(10) = '1' else 'Z'; A_OE(10) <= (RW AND $OpTx$FX_DC$32); FDCPE_A11: FDCPE port map (A_I(11),A(11),CLK_EXT,'0',LAN_SM_RST,A_CE(11)); A(11) <= ((DQ_SWAP AND DQ(11).PIN) OR (NOT DQ_SWAP AND DQ(3).PIN)); A_CE(11) <= (NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1 AND NOT LAN_SM_FSM_FFd3); A(11) <= A_I(11) when A_OE(11) = '1' else 'Z'; A_OE(11) <= (RW AND $OpTx$FX_DC$32); FDCPE_A12: FDCPE port map (A_I(12),A(12),CLK_EXT,'0',LAN_SM_RST,A_CE(12)); A(12) <= ((DQ_SWAP AND DQ(12).PIN) OR (NOT DQ_SWAP AND DQ(4).PIN)); A_CE(12) <= (NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1 AND NOT LAN_SM_FSM_FFd3); A(12) <= A_I(12) when A_OE(12) = '1' else 'Z'; A_OE(12) <= (RW AND $OpTx$FX_DC$32); FDCPE_A13: FDCPE port map (A_I(13),A(13),CLK_EXT,'0',LAN_SM_RST,A_CE(13)); A(13) <= ((DQ_SWAP AND DQ(13).PIN) OR (NOT DQ_SWAP AND DQ(5).PIN)); A_CE(13) <= (NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1 AND NOT LAN_SM_FSM_FFd3); A(13) <= A_I(13) when A_OE(13) = '1' else 'Z'; A_OE(13) <= (RW AND $OpTx$FX_DC$32); FDCPE_A14: FDCPE port map (A_I(14),A(14),CLK_EXT,'0',LAN_SM_RST,A_CE(14)); A(14) <= ((DQ_SWAP AND DQ(14).PIN) OR (NOT DQ_SWAP AND DQ(6).PIN)); A_CE(14) <= (NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1 AND NOT LAN_SM_FSM_FFd3); A(14) <= A_I(14) when A_OE(14) = '1' else 'Z'; A_OE(14) <= (RW AND $OpTx$FX_DC$32); FDCPE_A15: FDCPE port map (A_I(15),A(15),CLK_EXT,'0',LAN_SM_RST,A_CE(15)); A(15) <= ((DQ_SWAP AND DQ(15).PIN) OR (NOT DQ_SWAP AND DQ(7).PIN)); A_CE(15) <= (NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1 AND NOT LAN_SM_FSM_FFd3); A(15) <= A_I(15) when A_OE(15) = '1' else 'Z'; A_OE(15) <= (RW AND $OpTx$FX_DC$32); FDCPE_A16: FDCPE port map (A_I(16),A(16),CLK_EXT,'0',LAN_SM_RST,A_CE(16)); A(16) <= ((DQ_SWAP AND DQ(0).PIN) OR (NOT DQ_SWAP AND DQ(8).PIN)); A_CE(16) <= (NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1 AND NOT LAN_SM_FSM_FFd3); A(16) <= A_I(16) when A_OE(16) = '1' else 'Z'; A_OE(16) <= (RW AND $OpTx$FX_DC$32); FDCPE_A17: FDCPE port map (A_I(17),A(17),CLK_EXT,'0',LAN_SM_RST,A_CE(17)); A(17) <= ((DQ_SWAP AND DQ(1).PIN) OR (NOT DQ_SWAP AND DQ(9).PIN)); A_CE(17) <= (NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1 AND NOT LAN_SM_FSM_FFd3); A(17) <= A_I(17) when A_OE(17) = '1' else 'Z'; A_OE(17) <= (RW AND $OpTx$FX_DC$32); FDCPE_A18: FDCPE port map (A_I(18),A(18),CLK_EXT,'0',LAN_SM_RST,A_CE(18)); A(18) <= ((DQ_SWAP AND DQ(2).PIN) OR (NOT DQ_SWAP AND DQ(10).PIN)); A_CE(18) <= (NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1 AND NOT LAN_SM_FSM_FFd3); A(18) <= A_I(18) when A_OE(18) = '1' else 'Z'; A_OE(18) <= (RW AND $OpTx$FX_DC$32); FDCPE_A19: FDCPE port map (A_I(19),A(19),CLK_EXT,'0',LAN_SM_RST,A_CE(19)); A(19) <= ((DQ_SWAP AND DQ(3).PIN) OR (NOT DQ_SWAP AND DQ(11).PIN)); A_CE(19) <= (NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1 AND NOT LAN_SM_FSM_FFd3); A(19) <= A_I(19) when A_OE(19) = '1' else 'Z'; A_OE(19) <= (RW AND $OpTx$FX_DC$32); FDCPE_A20: FDCPE port map (A_I(20),A(20),CLK_EXT,'0',LAN_SM_RST,A_CE(20)); A(20) <= ((DQ_SWAP AND DQ(4).PIN) OR (NOT DQ_SWAP AND DQ(12).PIN)); A_CE(20) <= (NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1 AND NOT LAN_SM_FSM_FFd3); A(20) <= A_I(20) when A_OE(20) = '1' else 'Z'; A_OE(20) <= (RW AND $OpTx$FX_DC$32); FDCPE_A21: FDCPE port map (A_I(21),A(21),CLK_EXT,'0',LAN_SM_RST,A_CE(21)); A(21) <= ((DQ_SWAP AND DQ(5).PIN) OR (NOT DQ_SWAP AND DQ(13).PIN)); A_CE(21) <= (NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1 AND NOT LAN_SM_FSM_FFd3); A(21) <= A_I(21) when A_OE(21) = '1' else 'Z'; A_OE(21) <= (RW AND $OpTx$FX_DC$32); FDCPE_A22: FDCPE port map (A_I(22),A(22),CLK_EXT,'0',LAN_SM_RST,A_CE(22)); A(22) <= ((DQ_SWAP AND DQ(6).PIN) OR (NOT DQ_SWAP AND DQ(14).PIN)); A_CE(22) <= (NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1 AND NOT LAN_SM_FSM_FFd3); A(22) <= A_I(22) when A_OE(22) = '1' else 'Z'; A_OE(22) <= (RW AND $OpTx$FX_DC$32); FDCPE_A23: FDCPE port map (A_I(23),A(23),CLK_EXT,'0',LAN_SM_RST,A_CE(23)); A(23) <= ((DQ_SWAP AND DQ(7).PIN) OR (NOT DQ_SWAP AND DQ(15).PIN)); A_CE(23) <= (NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1 AND NOT LAN_SM_FSM_FFd3); A(23) <= A_I(23) when A_OE(23) = '1' else 'Z'; A_OE(23) <= (RW AND $OpTx$FX_DC$32); FDCPE_AUTOCONFIG_ACCESS: FDCPE port map (AUTOCONFIG_ACCESS,AUTOCONFIG_ACCESS_D,NOT FCS,NOT Z3_ADR_1/Z3_ADR_1_SETF,'0'); AUTOCONFIG_ACCESS_D <= (Z3 AND D(9).PIN AND D(8).PIN AND D(14).PIN AND D(13).PIN AND D(12).PIN AND D(11).PIN AND D(10).PIN AND D(15).PIN AND NOT CFIN AND NOT A(20).PIN AND NOT A(19).PIN AND NOT A(18).PIN AND NOT A(17).PIN AND NOT A(16).PIN AND NOT A(23).PIN AND NOT A(22).PIN AND NOT A(21).PIN AND CFOUT); FTCPE_AUTO_CONFIG_DONE_CYCLE: FTCPE port map (AUTO_CONFIG_DONE_CYCLE,AUTO_CONFIG_DONE_CYCLE_T,CLK_EXT,NOT RESET,'0',AUTO_CONFIG_DONE_CYCLE_CE); AUTO_CONFIG_DONE_CYCLE_T <= (NOT RW AND NOT AUTO_CONFIG_DONE_CYCLE AND NOT Z3_ADR(2) AND Z3_ADR_0 AND NOT Z3_ADR(6) AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5)); AUTO_CONFIG_DONE_CYCLE_CE <= (NOT FCS AND NOT UDS AND AUTOCONFIG_ACCESS); A_LAN(0) <= NOT ((RESET AND NOT Z3_A_LOW)); A_LAN(1) <= NOT ((RESET AND NOT Z3_ADR_0)); A_LAN(2) <= NOT ((RESET AND NOT Z3_ADR_1)); A_LAN(3) <= ((RESET AND Z3_ADR(2)) OR (NOT RESET AND LAN_A_INIT(3))); A_LAN(4) <= NOT ((RESET AND NOT Z3_ADR(3))); A_LAN(5) <= NOT ((RESET AND NOT Z3_ADR(4))); A_LAN(6) <= ((RESET AND Z3_ADR(5)) OR (NOT RESET AND LAN_A_INIT(6))); A_LAN(7) <= NOT ((RESET AND NOT Z3_ADR(6))); A_LAN(8) <= NOT ((RESET AND NOT Z3_ADR(7))); A_LAN(9) <= NOT ((RESET AND NOT Z3_ADR(8))); A_LAN(10) <= NOT ((RESET AND NOT Z3_ADR(9))); A_LAN(11) <= NOT ((RESET AND NOT Z3_ADR(10))); A_LAN(12) <= NOT ((RESET AND NOT Z3_ADR(11))); A_LAN(13) <= NOT ((RESET AND NOT Z3_ADR(12))); BUF_CONFIG_READY <= (NOT FCS AND LAN_ACCESS AND Z3_ADR(13)); BUF_LAN_READY <= ((NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1 AND NOT LAN_SM_FSM_FFd3) OR (LAN_SM_FSM_FFd1 AND LAN_SM_FSM_FFd3) OR (LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd3) OR (LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd1 AND $OpTx$FX_DC$10) OR (LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd3 AND $OpTx$FX_DC$10)); FDCPE_CFOUT: FDCPE port map (CFOUT,CFOUT_D,CLK_EXT,'0',NOT RESET,FCS); CFOUT_D <= (NOT AUTO_CONFIG_DONE_CYCLE AND AUTOBOOT_OFF); FDCPE_CONFIG_READY: FDCPE port map (CONFIG_READY,BUF_CONFIG_READY,CLK_EXT,NOT RESET,'0'); CP_CS <= '1'; CP_RD <= '1'; CP_WE <= '1'; D_I(0) <= NOT ((NOT Z3_DATA(16) AND Z3_DATA(1)/Z3_DATA(1)_TRST)); D(0) <= D_I(0) when D_OE(0) = '1' else 'Z'; D_OE(0) <= D_9_IOBUFE/D_9_IOBUFE_TRST; D_I(1) <= NOT ((NOT Z3_DATA(17) AND Z3_DATA(1)/Z3_DATA(1)_TRST)); D(1) <= D_I(1) when D_OE(1) = '1' else 'Z'; D_OE(1) <= D_9_IOBUFE/D_9_IOBUFE_TRST; D_I(2) <= NOT ((NOT Z3_DATA(18) AND Z3_DATA(1)/Z3_DATA(1)_TRST)); D(2) <= D_I(2) when D_OE(2) = '1' else 'Z'; D_OE(2) <= D_9_IOBUFE/D_9_IOBUFE_TRST; D_I(3) <= NOT ((NOT Z3_DATA(19) AND Z3_DATA(1)/Z3_DATA(1)_TRST)); D(3) <= D_I(3) when D_OE(3) = '1' else 'Z'; D_OE(3) <= D_9_IOBUFE/D_9_IOBUFE_TRST; D_I(4) <= NOT ((NOT Z3_DATA(20) AND Z3_DATA(1)/Z3_DATA(1)_TRST)); D(4) <= D_I(4) when D_OE(4) = '1' else 'Z'; D_OE(4) <= D_9_IOBUFE/D_9_IOBUFE_TRST; D_I(5) <= NOT ((NOT Z3_DATA(21) AND Z3_DATA(1)/Z3_DATA(1)_TRST)); D(5) <= D_I(5) when D_OE(5) = '1' else 'Z'; D_OE(5) <= D_9_IOBUFE/D_9_IOBUFE_TRST; D_I(6) <= NOT ((NOT Z3_DATA(22) AND Z3_DATA(1)/Z3_DATA(1)_TRST)); D(6) <= D_I(6) when D_OE(6) = '1' else 'Z'; D_OE(6) <= D_9_IOBUFE/D_9_IOBUFE_TRST; D_I(7) <= NOT ((NOT Z3_DATA(23) AND Z3_DATA(1)/Z3_DATA(1)_TRST)); D(7) <= D_I(7) when D_OE(7) = '1' else 'Z'; D_OE(7) <= D_9_IOBUFE/D_9_IOBUFE_TRST; D_I(8) <= ((Z3_DATA(24) AND Z3_DATA(1)/Z3_DATA(1)_TRST) OR (D_OUT(0) AND NOT Z3_DATA(1)/Z3_DATA(1)_TRST)); D(8) <= D_I(8) when D_OE(8) = '1' else 'Z'; D_OE(8) <= D_9_IOBUFE/D_9_IOBUFE_TRST; D_I(9) <= ((Z3_DATA(25) AND Z3_DATA(1)/Z3_DATA(1)_TRST) OR (D_OUT(1) AND NOT Z3_DATA(1)/Z3_DATA(1)_TRST)); D(9) <= D_I(9) when D_OE(9) = '1' else 'Z'; D_OE(9) <= D_9_IOBUFE/D_9_IOBUFE_TRST; D_I(10) <= ((Z3_DATA(26) AND Z3_DATA(1)/Z3_DATA(1)_TRST) OR (D_OUT(2) AND NOT Z3_DATA(1)/Z3_DATA(1)_TRST)); D(10) <= D_I(10) when D_OE(10) = '1' else 'Z'; D_OE(10) <= D_9_IOBUFE/D_9_IOBUFE_TRST; D_I(11) <= ((Z3_DATA(27) AND Z3_DATA(1)/Z3_DATA(1)_TRST) OR (D_OUT(3) AND NOT Z3_DATA(1)/Z3_DATA(1)_TRST)); D(11) <= D_I(11) when D_OE(11) = '1' else 'Z'; D_OE(11) <= D_9_IOBUFE/D_9_IOBUFE_TRST; D_I(12) <= ((Z3_DATA(28) AND Z3_DATA(1)/Z3_DATA(1)_TRST) OR (D_OUT(4) AND NOT Z3_DATA(1)/Z3_DATA(1)_TRST)); D(12) <= D_I(12) when D_OE(12) = '1' else 'Z'; D_OE(12) <= D_9_IOBUFE/D_9_IOBUFE_TRST; D_I(13) <= ((Z3_DATA(29) AND Z3_DATA(1)/Z3_DATA(1)_TRST) OR (D_OUT(5) AND NOT Z3_DATA(1)/Z3_DATA(1)_TRST)); D(13) <= D_I(13) when D_OE(13) = '1' else 'Z'; D_OE(13) <= D_9_IOBUFE/D_9_IOBUFE_TRST; D_I(14) <= ((Z3_DATA(30) AND Z3_DATA(1)/Z3_DATA(1)_TRST) OR (D_OUT(6) AND NOT Z3_DATA(1)/Z3_DATA(1)_TRST)); D(14) <= D_I(14) when D_OE(14) = '1' else 'Z'; D_OE(14) <= D_9_IOBUFE/D_9_IOBUFE_TRST; D_I(15) <= ((Z3_DATA(31) AND Z3_DATA(1)/Z3_DATA(1)_TRST) OR (D_OUT(7) AND NOT Z3_DATA(1)/Z3_DATA(1)_TRST)); D(15) <= D_I(15) when D_OE(15) = '1' else 'Z'; D_OE(15) <= D_9_IOBUFE/D_9_IOBUFE_TRST; DQ_I(0) <= (RESET AND DQ_DATA(0)); DQ(0) <= DQ_I(0) when DQ_OE(0) = '1' else 'Z'; DQ_OE(0) <= DQ_9_IOBUFE/DQ_9_IOBUFE_TRST; DQ_I(1) <= ((RESET AND DQ_DATA(1)) OR (NOT RESET AND LAN_D_INIT(1))); DQ(1) <= DQ_I(1) when DQ_OE(1) = '1' else 'Z'; DQ_OE(1) <= DQ_9_IOBUFE/DQ_9_IOBUFE_TRST; DQ_I(2) <= (RESET AND DQ_DATA(2)); DQ(2) <= DQ_I(2) when DQ_OE(2) = '1' else 'Z'; DQ_OE(2) <= DQ_9_IOBUFE/DQ_9_IOBUFE_TRST; DQ_I(3) <= (RESET AND DQ_DATA(3)); DQ(3) <= DQ_I(3) when DQ_OE(3) = '1' else 'Z'; DQ_OE(3) <= DQ_9_IOBUFE/DQ_9_IOBUFE_TRST; DQ_I(4) <= ((RESET AND DQ_DATA(4)) OR (NOT RESET AND LAN_D_INIT(1))); DQ(4) <= DQ_I(4) when DQ_OE(4) = '1' else 'Z'; DQ_OE(4) <= DQ_9_IOBUFE/DQ_9_IOBUFE_TRST; DQ_I(5) <= (RESET AND DQ_DATA(5)); DQ(5) <= DQ_I(5) when DQ_OE(5) = '1' else 'Z'; DQ_OE(5) <= DQ_9_IOBUFE/DQ_9_IOBUFE_TRST; DQ_I(6) <= (RESET AND DQ_DATA(6)); DQ(6) <= DQ_I(6) when DQ_OE(6) = '1' else 'Z'; DQ_OE(6) <= DQ_9_IOBUFE/DQ_9_IOBUFE_TRST; DQ_I(7) <= (RESET AND DQ_DATA(7)); DQ(7) <= DQ_I(7) when DQ_OE(7) = '1' else 'Z'; DQ_OE(7) <= DQ_9_IOBUFE/DQ_9_IOBUFE_TRST; DQ_I(8) <= ((RESET AND DQ_DATA(8)) OR (NOT RESET AND LAN_D_INIT(8))); DQ(8) <= DQ_I(8) when DQ_OE(8) = '1' else 'Z'; DQ_OE(8) <= DQ_9_IOBUFE/DQ_9_IOBUFE_TRST; DQ_I(9) <= ((RESET AND DQ_DATA(9)) OR (NOT RESET AND LAN_D_INIT(1))); DQ(9) <= DQ_I(9) when DQ_OE(9) = '1' else 'Z'; DQ_OE(9) <= DQ_9_IOBUFE/DQ_9_IOBUFE_TRST; DQ_I(10) <= ((RESET AND DQ_DATA(10)) OR (NOT RESET AND LAN_D_INIT(8))); DQ(10) <= DQ_I(10) when DQ_OE(10) = '1' else 'Z'; DQ_OE(10) <= DQ_9_IOBUFE/DQ_9_IOBUFE_TRST; DQ_I(11) <= ((RESET AND DQ_DATA(11)) OR (NOT RESET AND LAN_D_INIT(8))); DQ(11) <= DQ_I(11) when DQ_OE(11) = '1' else 'Z'; DQ_OE(11) <= DQ_9_IOBUFE/DQ_9_IOBUFE_TRST; DQ_I(12) <= (RESET AND DQ_DATA(12)); DQ(12) <= DQ_I(12) when DQ_OE(12) = '1' else 'Z'; DQ_OE(12) <= DQ_9_IOBUFE/DQ_9_IOBUFE_TRST; DQ_I(13) <= (RESET AND DQ_DATA(13)); DQ(13) <= DQ_I(13) when DQ_OE(13) = '1' else 'Z'; DQ_OE(13) <= DQ_9_IOBUFE/DQ_9_IOBUFE_TRST; DQ_I(14) <= (RESET AND DQ_DATA(14)); DQ(14) <= DQ_I(14) when DQ_OE(14) = '1' else 'Z'; DQ_OE(14) <= DQ_9_IOBUFE/DQ_9_IOBUFE_TRST; DQ_I(15) <= (RESET AND DQ_DATA(15)); DQ(15) <= DQ_I(15) when DQ_OE(15) = '1' else 'Z'; DQ_OE(15) <= DQ_9_IOBUFE/DQ_9_IOBUFE_TRST; DQ_9_IOBUFE/DQ_9_IOBUFE_TRST <= ((NOT RESET) OR ($OpTx$FX_DC$32 AND NOT Z3_DATA(1)/Z3_DATA(1)_TRST)); FDCPE_DQ_DATA0: FDCPE port map (DQ_DATA(0),DQ_DATA_D(0),CLK_EXT,'0',LAN_SM_RST); DQ_DATA_D(0) <= ((D(0).PIN AND NOT LAN_SM_FSM_FFd4 AND NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3 AND NOT $OpTx$FX_DC$8) OR (DQ_DATA(0) AND NOT $OpTx$FX_DC$16) OR (A(16).PIN AND DQ_SWAP AND $OpTx$FX_SC$18) OR (NOT DQ_SWAP AND A(8).PIN AND $OpTx$FX_SC$18) OR (D(8).PIN AND NOT LAN_SM_FSM_FFd4 AND DQ_SWAP AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3 AND NOT $OpTx$FX_DC$8)); FDCPE_DQ_DATA1: FDCPE port map (DQ_DATA(1),DQ_DATA_D(1),CLK_EXT,'0',LAN_SM_RST); DQ_DATA_D(1) <= ((D(1).PIN AND NOT LAN_SM_FSM_FFd4 AND NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3 AND NOT $OpTx$FX_DC$8) OR (DQ_DATA(1) AND NOT $OpTx$FX_DC$16) OR (A(17).PIN AND DQ_SWAP AND $OpTx$FX_SC$18) OR (NOT DQ_SWAP AND A(9).PIN AND $OpTx$FX_SC$18) OR (D(9).PIN AND NOT LAN_SM_FSM_FFd4 AND DQ_SWAP AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3 AND NOT $OpTx$FX_DC$8)); FDCPE_DQ_DATA2: FDCPE port map (DQ_DATA(2),DQ_DATA_D(2),CLK_EXT,'0',LAN_SM_RST); DQ_DATA_D(2) <= ((D(2).PIN AND NOT LAN_SM_FSM_FFd4 AND NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3 AND NOT $OpTx$FX_DC$8) OR (DQ_DATA(2) AND NOT $OpTx$FX_DC$16) OR (A(18).PIN AND DQ_SWAP AND $OpTx$FX_SC$18) OR (NOT DQ_SWAP AND A(10).PIN AND $OpTx$FX_SC$18) OR (D(10).PIN AND NOT LAN_SM_FSM_FFd4 AND DQ_SWAP AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3 AND NOT $OpTx$FX_DC$8)); FDCPE_DQ_DATA3: FDCPE port map (DQ_DATA(3),DQ_DATA_D(3),CLK_EXT,'0',LAN_SM_RST); DQ_DATA_D(3) <= ((D(3).PIN AND NOT LAN_SM_FSM_FFd4 AND NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3 AND NOT $OpTx$FX_DC$8) OR (DQ_DATA(3) AND NOT $OpTx$FX_DC$16) OR (A(19).PIN AND DQ_SWAP AND $OpTx$FX_SC$18) OR (NOT DQ_SWAP AND A(11).PIN AND $OpTx$FX_SC$18) OR (D(11).PIN AND NOT LAN_SM_FSM_FFd4 AND DQ_SWAP AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3 AND NOT $OpTx$FX_DC$8)); FDCPE_DQ_DATA4: FDCPE port map (DQ_DATA(4),DQ_DATA_D(4),CLK_EXT,'0',LAN_SM_RST); DQ_DATA_D(4) <= ((D(12).PIN AND NOT LAN_SM_FSM_FFd4 AND DQ_SWAP AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3 AND NOT $OpTx$FX_DC$8) OR (D(4).PIN AND NOT LAN_SM_FSM_FFd4 AND NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3 AND NOT $OpTx$FX_DC$8) OR (DQ_DATA(4) AND NOT $OpTx$FX_DC$16) OR (A(20).PIN AND DQ_SWAP AND $OpTx$FX_SC$18) OR (NOT DQ_SWAP AND A(12).PIN AND $OpTx$FX_SC$18)); FDCPE_DQ_DATA5: FDCPE port map (DQ_DATA(5),DQ_DATA_D(5),CLK_EXT,'0',LAN_SM_RST); DQ_DATA_D(5) <= ((D(5).PIN AND NOT LAN_SM_FSM_FFd4 AND NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3 AND NOT $OpTx$FX_DC$8) OR (DQ_DATA(5) AND NOT $OpTx$FX_DC$16) OR (DQ_SWAP AND A(21).PIN AND $OpTx$FX_SC$18) OR (NOT DQ_SWAP AND A(13).PIN AND $OpTx$FX_SC$18) OR (D(13).PIN AND NOT LAN_SM_FSM_FFd4 AND DQ_SWAP AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3 AND NOT $OpTx$FX_DC$8)); FDCPE_DQ_DATA6: FDCPE port map (DQ_DATA(6),DQ_DATA_D(6),CLK_EXT,'0',LAN_SM_RST); DQ_DATA_D(6) <= ((D(6).PIN AND NOT LAN_SM_FSM_FFd4 AND NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3 AND NOT $OpTx$FX_DC$8) OR (DQ_DATA(6) AND NOT $OpTx$FX_DC$16) OR (DQ_SWAP AND A(22).PIN AND $OpTx$FX_SC$18) OR (NOT DQ_SWAP AND A(14).PIN AND $OpTx$FX_SC$18) OR (D(14).PIN AND NOT LAN_SM_FSM_FFd4 AND DQ_SWAP AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3 AND NOT $OpTx$FX_DC$8)); FDCPE_DQ_DATA7: FDCPE port map (DQ_DATA(7),DQ_DATA_D(7),CLK_EXT,'0',LAN_SM_RST); DQ_DATA_D(7) <= ((D(15).PIN AND NOT LAN_SM_FSM_FFd4 AND DQ_SWAP AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3 AND NOT $OpTx$FX_DC$8) OR (D(7).PIN AND NOT LAN_SM_FSM_FFd4 AND NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3 AND NOT $OpTx$FX_DC$8) OR (DQ_DATA(7) AND NOT $OpTx$FX_DC$16) OR (DQ_SWAP AND A(23).PIN AND $OpTx$FX_SC$18) OR (NOT DQ_SWAP AND A(15).PIN AND $OpTx$FX_SC$18)); FDCPE_DQ_DATA8: FDCPE port map (DQ_DATA(8),DQ_DATA_D(8),CLK_EXT,'0',LAN_SM_RST); DQ_DATA_D(8) <= ((D(8).PIN AND NOT LAN_SM_FSM_FFd4 AND NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3 AND NOT $OpTx$FX_DC$8) OR (DQ_DATA(8) AND NOT $OpTx$FX_DC$16) OR (A(16).PIN AND NOT DQ_SWAP AND $OpTx$FX_SC$18) OR (DQ_SWAP AND A(8).PIN AND $OpTx$FX_SC$18) OR (D(0).PIN AND NOT LAN_SM_FSM_FFd4 AND DQ_SWAP AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3 AND NOT $OpTx$FX_DC$8)); FDCPE_DQ_DATA9: FDCPE port map (DQ_DATA(9),DQ_DATA_D(9),CLK_EXT,'0',LAN_SM_RST); DQ_DATA_D(9) <= ((D(9).PIN AND NOT LAN_SM_FSM_FFd4 AND NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3 AND NOT $OpTx$FX_DC$8) OR (DQ_DATA(9) AND NOT $OpTx$FX_DC$16) OR (A(17).PIN AND NOT DQ_SWAP AND $OpTx$FX_SC$18) OR (DQ_SWAP AND A(9).PIN AND $OpTx$FX_SC$18) OR (D(1).PIN AND NOT LAN_SM_FSM_FFd4 AND DQ_SWAP AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3 AND NOT $OpTx$FX_DC$8)); FDCPE_DQ_DATA10: FDCPE port map (DQ_DATA(10),DQ_DATA_D(10),CLK_EXT,'0',LAN_SM_RST); DQ_DATA_D(10) <= ((DQ_SWAP AND A(10).PIN AND $OpTx$FX_SC$18) OR (D(10).PIN AND NOT LAN_SM_FSM_FFd4 AND NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3 AND NOT $OpTx$FX_DC$8) OR (D(2).PIN AND NOT LAN_SM_FSM_FFd4 AND DQ_SWAP AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3 AND NOT $OpTx$FX_DC$8) OR (DQ_DATA(10) AND NOT $OpTx$FX_DC$16) OR (A(18).PIN AND NOT DQ_SWAP AND $OpTx$FX_SC$18)); FDCPE_DQ_DATA11: FDCPE port map (DQ_DATA(11),DQ_DATA_D(11),CLK_EXT,'0',LAN_SM_RST); DQ_DATA_D(11) <= ((D(11).PIN AND NOT LAN_SM_FSM_FFd4 AND NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3 AND NOT $OpTx$FX_DC$8) OR (D(3).PIN AND NOT LAN_SM_FSM_FFd4 AND DQ_SWAP AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3 AND NOT $OpTx$FX_DC$8) OR (DQ_DATA(11) AND NOT $OpTx$FX_DC$16) OR (A(19).PIN AND NOT DQ_SWAP AND $OpTx$FX_SC$18) OR (DQ_SWAP AND A(11).PIN AND $OpTx$FX_SC$18)); FDCPE_DQ_DATA12: FDCPE port map (DQ_DATA(12),DQ_DATA_D(12),CLK_EXT,'0',LAN_SM_RST); DQ_DATA_D(12) <= ((D(12).PIN AND NOT LAN_SM_FSM_FFd4 AND NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3 AND NOT $OpTx$FX_DC$8) OR (DQ_DATA(12) AND NOT $OpTx$FX_DC$16) OR (A(20).PIN AND NOT DQ_SWAP AND $OpTx$FX_SC$18) OR (DQ_SWAP AND A(12).PIN AND $OpTx$FX_SC$18) OR (D(4).PIN AND NOT LAN_SM_FSM_FFd4 AND DQ_SWAP AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3 AND NOT $OpTx$FX_DC$8)); FDCPE_DQ_DATA13: FDCPE port map (DQ_DATA(13),DQ_DATA_D(13),CLK_EXT,'0',LAN_SM_RST); DQ_DATA_D(13) <= ((D(13).PIN AND NOT LAN_SM_FSM_FFd4 AND NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3 AND NOT $OpTx$FX_DC$8) OR (DQ_DATA(13) AND NOT $OpTx$FX_DC$16) OR (DQ_SWAP AND A(13).PIN AND $OpTx$FX_SC$18) OR (NOT DQ_SWAP AND A(21).PIN AND $OpTx$FX_SC$18) OR (D(5).PIN AND NOT LAN_SM_FSM_FFd4 AND DQ_SWAP AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3 AND NOT $OpTx$FX_DC$8)); FDCPE_DQ_DATA14: FDCPE port map (DQ_DATA(14),DQ_DATA_D(14),CLK_EXT,'0',LAN_SM_RST); DQ_DATA_D(14) <= ((D(14).PIN AND NOT LAN_SM_FSM_FFd4 AND NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3 AND NOT $OpTx$FX_DC$8) OR (D(6).PIN AND NOT LAN_SM_FSM_FFd4 AND DQ_SWAP AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3 AND NOT $OpTx$FX_DC$8) OR (DQ_DATA(14) AND NOT $OpTx$FX_DC$16) OR (DQ_SWAP AND A(14).PIN AND $OpTx$FX_SC$18) OR (NOT DQ_SWAP AND A(22).PIN AND $OpTx$FX_SC$18)); FDCPE_DQ_DATA15: FDCPE port map (DQ_DATA(15),DQ_DATA_D(15),CLK_EXT,'0',LAN_SM_RST); DQ_DATA_D(15) <= ((D(15).PIN AND NOT LAN_SM_FSM_FFd4 AND NOT DQ_SWAP AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3 AND NOT $OpTx$FX_DC$8) OR (DQ_DATA(15) AND NOT $OpTx$FX_DC$16) OR (DQ_SWAP AND A(15).PIN AND $OpTx$FX_SC$18) OR (NOT DQ_SWAP AND A(23).PIN AND $OpTx$FX_SC$18) OR (D(7).PIN AND NOT LAN_SM_FSM_FFd4 AND DQ_SWAP AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3 AND NOT $OpTx$FX_DC$8)); FDCPE_DQ_SWAP: FDCPE port map (DQ_SWAP,DQ_SWAP_D,NOT FCS,'0',NOT Z3_ADR_1/Z3_ADR_1_SETF); DQ_SWAP_D <= ((Z3 AND D(12).PIN AND LAN_BASEADR(12) AND NOT SHUT_UP AND A(13).PIN AND A(14).PIN AND NOT $OpTx$FX_DC$38 AND NOT $OpTx$FX_DC$37 AND NOT $OpTx$FX_DC$36 AND NOT $OpTx$FX_DC$35 AND NOT $OpTx$FX_DC$39 AND NOT $OpTx$INV$2 AND NOT $OpTx$INV$1) OR (Z3 AND NOT D(12).PIN AND NOT LAN_BASEADR(12) AND NOT SHUT_UP AND A(13).PIN AND A(14).PIN AND NOT $OpTx$FX_DC$38 AND NOT $OpTx$FX_DC$37 AND NOT $OpTx$FX_DC$36 AND NOT $OpTx$FX_DC$35 AND NOT $OpTx$FX_DC$39 AND NOT $OpTx$INV$2 AND NOT $OpTx$INV$1)); DTACK_I <= '0'; DTACK <= DTACK_I when DTACK_OE = '1' else 'Z'; DTACK_OE <= NOT N0$BUF7/N0$BUF7_TRST; D_9_IOBUFE/D_9_IOBUFE_TRST <= ((Z3_DATA(1)/Z3_DATA(1)_TRST) OR (RW AND NOT LDS AND NOT SLAVE) OR (RW AND NOT SLAVE AND NOT $OpTx$FX_DC$10) OR (RW AND NOT FCS AND NOT UDS AND AUTOCONFIG_ACCESS)); FDCPE_D_OUT0: FDCPE port map (D_OUT(0),D_OUT_D(0),CLK_EXT,'0',NOT RESET); D_OUT_D(0) <= (NOT FCS AND NOT UDS AND NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND NOT Z3_ADR(4) AND NOT Z3_ADR(5)); FDCPE_D_OUT1: FDCPE port map (D_OUT(1),D_OUT_D(1),CLK_EXT,'0',NOT RESET); D_OUT_D(1) <= ((NOT FCS AND NOT UDS AND NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND NOT Z3_ADR(4) AND NOT Z3_ADR(5)) OR (NOT FCS AND NOT UDS AND NOT Z3_ADR(2) AND NOT Z3_ADR_0 AND AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND NOT Z3_ADR(4) AND NOT Z3_ADR(5)) OR (NOT FCS AND NOT UDS AND NOT Z3_ADR_1 AND NOT Z3_ADR_0 AND AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND NOT Z3_ADR(4) AND NOT Z3_ADR(5))); FDCPE_D_OUT2: FDCPE port map (D_OUT(2),D_OUT_D(2),CLK_EXT,'0',NOT RESET); D_OUT_D(2) <= ((NOT FCS AND NOT UDS AND Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND NOT Z3_ADR(4) AND NOT Z3_ADR(5)) OR (NOT FCS AND NOT UDS AND NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND NOT Z3_ADR_0 AND AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND NOT Z3_ADR(4) AND NOT Z3_ADR(5))); FDCPE_D_OUT3: FDCPE port map (D_OUT(3),D_OUT_D(3),CLK_EXT,'0',NOT RESET); D_OUT_D(3) <= (NOT FCS AND NOT UDS AND NOT Z3_ADR_1 AND AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND NOT Z3_ADR(4) AND NOT Z3_ADR(5)); FDCPE_D_OUT4: FDCPE port map (D_OUT(4),D_OUT_D(4),CLK_EXT,'0',NOT RESET); D_OUT_D(4) <= ((NOT FCS AND NOT UDS AND NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND NOT Z3_ADR(4) AND NOT Z3_ADR(5)) OR (NOT FCS AND NOT UDS AND NOT Z3_ADR(2) AND NOT Z3_ADR_0 AND NOT Z3_ADR(6) AND AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND NOT Z3_ADR(4) AND NOT Z3_ADR(5)) OR (NOT FCS AND NOT UDS AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND NOT Z3_ADR(4) AND NOT Z3_ADR(5))); FDCPE_D_OUT5: FDCPE port map (D_OUT(5),D_OUT_D(5),CLK_EXT,'0',NOT RESET); D_OUT_D(5) <= ((NOT FCS AND NOT UDS AND NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND NOT Z3_ADR(4) AND NOT Z3_ADR(5)) OR (NOT FCS AND NOT UDS AND NOT Z3_ADR(2) AND NOT Z3_ADR_0 AND Z3_ADR(6) AND AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND NOT Z3_ADR(4) AND NOT Z3_ADR(5)) OR (NOT FCS AND NOT UDS AND NOT Z3_ADR_1 AND NOT Z3_ADR_0 AND Z3_ADR(6) AND AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND NOT Z3_ADR(4) AND NOT Z3_ADR(5))); FDCPE_D_OUT6: FDCPE port map (D_OUT(6),D_OUT_D(6),CLK_EXT,'0',NOT RESET); D_OUT_D(6) <= ((NOT FCS AND NOT UDS AND NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND NOT Z3_ADR_0 AND AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND NOT Z3_ADR(4) AND NOT Z3_ADR(5)) OR (NOT FCS AND NOT UDS AND NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND NOT Z3_ADR(6) AND AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND NOT Z3_ADR(4) AND NOT Z3_ADR(5)) OR (NOT FCS AND NOT UDS AND Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND Z3_ADR(6) AND AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND NOT Z3_ADR(4) AND NOT Z3_ADR(5))); FDCPE_D_OUT7: FDCPE port map (D_OUT(7),D_OUT_D(7),CLK_EXT,'0',NOT RESET); D_OUT_D(7) <= (NOT FCS AND NOT UDS AND NOT Z3_ADR_1 AND Z3_ADR(6) AND AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND NOT Z3_ADR(4) AND NOT Z3_ADR(5)); IDE_A(0) <= '1'; IDE_A(1) <= '1'; IDE_A(2) <= '1'; IDE_CS(0) <= '1'; IDE_CS(1) <= '1'; IDE_R <= '1'; IDE_W <= '1'; INT_OUT_I <= '0'; INT_OUT <= INT_OUT_I when INT_OUT_OE = '1' else 'Z'; INT_OUT_OE <= (LAN_INT_ENABLE AND NOT LAN_IRQ_OUT); FDCPE_LAN_ACCESS: FDCPE port map (LAN_ACCESS,LAN_ACCESS_D,NOT FCS,NOT Z3_ADR_1/Z3_ADR_1_SETF,'0'); LAN_ACCESS_D <= ((Z3 AND D(12).PIN AND LAN_BASEADR(12) AND NOT SHUT_UP AND NOT $OpTx$FX_DC$38 AND NOT $OpTx$FX_DC$37 AND NOT $OpTx$FX_DC$36 AND NOT $OpTx$FX_DC$35 AND NOT $OpTx$FX_DC$39 AND NOT $OpTx$INV$2 AND NOT $OpTx$INV$1) OR (Z3 AND NOT D(12).PIN AND NOT LAN_BASEADR(12) AND NOT SHUT_UP AND NOT $OpTx$FX_DC$38 AND NOT $OpTx$FX_DC$37 AND NOT $OpTx$FX_DC$36 AND NOT $OpTx$FX_DC$35 AND NOT $OpTx$FX_DC$39 AND NOT $OpTx$INV$2 AND NOT $OpTx$INV$1)); FDCPE_LAN_A_INIT3: FDCPE port map (LAN_A_INIT(3),'0',CLK_EXT,'0',RESET); FDCPE_LAN_A_INIT6: FDCPE port map (LAN_A_INIT(6),NOT LAN_RST_SM_FSM_FFd1,CLK_EXT,'0',RESET); FDCPE_LAN_BASEADR0: FDCPE port map (LAN_BASEADR(0),D(0).PIN,CLK_EXT,'0',NOT RESET,LAN_BASEADR_CE(0)); LAN_BASEADR_CE(0) <= (NOT RW AND NOT FCS AND NOT UDS AND NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5)); FDCPE_LAN_BASEADR1: FDCPE port map (LAN_BASEADR(1),D(1).PIN,CLK_EXT,'0',NOT RESET,LAN_BASEADR_CE(1)); LAN_BASEADR_CE(1) <= (NOT RW AND NOT FCS AND NOT UDS AND NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5)); FDCPE_LAN_BASEADR2: FDCPE port map (LAN_BASEADR(2),D(2).PIN,CLK_EXT,'0',NOT RESET,LAN_BASEADR_CE(2)); LAN_BASEADR_CE(2) <= (NOT RW AND NOT FCS AND NOT UDS AND NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5)); FDCPE_LAN_BASEADR3: FDCPE port map (LAN_BASEADR(3),D(3).PIN,CLK_EXT,'0',NOT RESET,LAN_BASEADR_CE(3)); LAN_BASEADR_CE(3) <= (NOT RW AND NOT FCS AND NOT UDS AND NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5)); FDCPE_LAN_BASEADR4: FDCPE port map (LAN_BASEADR(4),D(4).PIN,CLK_EXT,'0',NOT RESET,LAN_BASEADR_CE(4)); LAN_BASEADR_CE(4) <= (NOT RW AND NOT FCS AND NOT UDS AND NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5)); FDCPE_LAN_BASEADR5: FDCPE port map (LAN_BASEADR(5),D(5).PIN,CLK_EXT,'0',NOT RESET,LAN_BASEADR_CE(5)); LAN_BASEADR_CE(5) <= (NOT RW AND NOT FCS AND NOT UDS AND NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5)); FDCPE_LAN_BASEADR6: FDCPE port map (LAN_BASEADR(6),D(6).PIN,CLK_EXT,'0',NOT RESET,LAN_BASEADR_CE(6)); LAN_BASEADR_CE(6) <= (NOT RW AND NOT FCS AND NOT UDS AND NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5)); FDCPE_LAN_BASEADR7: FDCPE port map (LAN_BASEADR(7),D(7).PIN,CLK_EXT,'0',NOT RESET,LAN_BASEADR_CE(7)); LAN_BASEADR_CE(7) <= (NOT RW AND NOT FCS AND NOT UDS AND NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5)); FDCPE_LAN_BASEADR8: FDCPE port map (LAN_BASEADR(8),D(8).PIN,CLK_EXT,'0',NOT RESET,LAN_BASEADR_CE(8)); LAN_BASEADR_CE(8) <= (NOT RW AND NOT FCS AND NOT UDS AND NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5)); FDCPE_LAN_BASEADR9: FDCPE port map (LAN_BASEADR(9),D(9).PIN,CLK_EXT,'0',NOT RESET,LAN_BASEADR_CE(9)); LAN_BASEADR_CE(9) <= (NOT RW AND NOT FCS AND NOT UDS AND NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5)); FDCPE_LAN_BASEADR10: FDCPE port map (LAN_BASEADR(10),D(10).PIN,CLK_EXT,'0',NOT RESET,LAN_BASEADR_CE(10)); LAN_BASEADR_CE(10) <= (NOT RW AND NOT FCS AND NOT UDS AND NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5)); FDCPE_LAN_BASEADR11: FDCPE port map (LAN_BASEADR(11),D(11).PIN,CLK_EXT,'0',NOT RESET,LAN_BASEADR_CE(11)); LAN_BASEADR_CE(11) <= (NOT RW AND NOT FCS AND NOT UDS AND NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5)); FDCPE_LAN_BASEADR12: FDCPE port map (LAN_BASEADR(12),D(12).PIN,CLK_EXT,'0',NOT RESET,LAN_BASEADR_CE(12)); LAN_BASEADR_CE(12) <= (NOT RW AND NOT FCS AND NOT UDS AND NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5)); FDCPE_LAN_BASEADR13: FDCPE port map (LAN_BASEADR(13),D(13).PIN,CLK_EXT,'0',NOT RESET,LAN_BASEADR_CE(13)); LAN_BASEADR_CE(13) <= (NOT RW AND NOT FCS AND NOT UDS AND NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5)); FDCPE_LAN_BASEADR14: FDCPE port map (LAN_BASEADR(14),D(14).PIN,CLK_EXT,'0',NOT RESET,LAN_BASEADR_CE(14)); LAN_BASEADR_CE(14) <= (NOT RW AND NOT FCS AND NOT UDS AND NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5)); FDCPE_LAN_BASEADR15: FDCPE port map (LAN_BASEADR(15),D(15).PIN,CLK_EXT,'0',NOT RESET,LAN_BASEADR_CE(15)); LAN_BASEADR_CE(15) <= (NOT RW AND NOT FCS AND NOT UDS AND NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5)); LAN_CFG_I(1) <= '0'; LAN_CFG(1) <= LAN_CFG_I(1) when LAN_CFG_OE(1) = '1' else 'Z'; LAN_CFG_OE(1) <= '0'; LAN_CFG_I(2) <= '0'; LAN_CFG(2) <= LAN_CFG_I(2) when LAN_CFG_OE(2) = '1' else 'Z'; LAN_CFG_OE(2) <= '0'; LAN_CFG_I(3) <= '0'; LAN_CFG(3) <= LAN_CFG_I(3) when LAN_CFG_OE(3) = '1' else 'Z'; LAN_CFG_OE(3) <= '0'; LAN_CFG_I(4) <= '0'; LAN_CFG(4) <= LAN_CFG_I(4) when LAN_CFG_OE(4) = '1' else 'Z'; LAN_CFG_OE(4) <= '0'; LAN_CS <= ((RESET AND LAN_ACCESS) OR (NOT RESET AND LAN_CS_RST)); FDCPE_LAN_CS_RST: FDCPE port map (LAN_CS_RST,LAN_CS_RST_D,CLK_EXT,RESET,'0'); LAN_CS_RST_D <= (NOT LAN_RST_SM_FSM_FFd2 AND NOT LAN_RST_SM_FSM_FFd3); FDCPE_LAN_D_INIT1: FDCPE port map (LAN_D_INIT(1),LAN_RST_SM_FSM_FFd1,CLK_EXT,RESET,'0'); FDCPE_LAN_D_INIT8: FDCPE port map (LAN_D_INIT(8),NOT LAN_RST_SM_FSM_FFd1,CLK_EXT,RESET,'0'); FTCPE_LAN_INT_ENABLE: FTCPE port map (LAN_INT_ENABLE,LAN_INT_ENABLE_T,CLK_EXT,NOT RESET,'0'); LAN_INT_ENABLE_T <= ((D(15).PIN AND NOT RW AND NOT UDS AND NOT LAN_INT_ENABLE AND BUF_CONFIG_READY) OR (NOT D(15).PIN AND NOT RW AND NOT UDS AND LAN_INT_ENABLE AND BUF_CONFIG_READY) OR (NOT RW AND UDS AND NOT LDS AND LAN_INT_ENABLE AND NOT A(23).PIN AND BUF_CONFIG_READY) OR (NOT RW AND UDS AND NOT LDS AND NOT LAN_INT_ENABLE AND A(23).PIN AND BUF_CONFIG_READY)); FDCPE_LAN_IRQ_D0: FDCPE port map (LAN_IRQ_D0,LAN_INT,CLK_EXT,'0',NOT RESET); FDCPE_LAN_IRQ_OUT: FDCPE port map (LAN_IRQ_OUT,LAN_IRQ_OUT_D,CLK_EXT,'0',NOT RESET); LAN_IRQ_OUT_D <= ((LAN_INT) OR (LAN_IRQ_OUT AND NOT LAN_IRQ_D0)); LAN_RD <= (LAN_RD_S AND $OpTx$FX_DC$24); FDCPE_LAN_RD_S: FDCPE port map (LAN_RD_S,LAN_RD_S_D,CLK_EXT,LAN_SM_RST,'0'); LAN_RD_S_D <= ((LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2) OR (RW AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3) OR (LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd1 AND NOT LAN_SM_FSM_FFd3)); FDCPE_LAN_READY: FDCPE port map (LAN_READY,BUF_LAN_READY,CLK_EXT,LAN_SM_RST,'0'); FTCPE_LAN_RST_SM_FSM_FFd1: FTCPE port map (LAN_RST_SM_FSM_FFd1,LAN_RST_SM_FSM_FFd1_T,CLK_EXT,RESET,'0'); LAN_RST_SM_FSM_FFd1_T <= (NOT LAN_RST_SM_FSM_FFd1 AND LAN_RST_SM_FSM_FFd2 AND NOT LAN_RST_SM_FSM_FFd3); FDCPE_LAN_RST_SM_FSM_FFd2: FDCPE port map (LAN_RST_SM_FSM_FFd2,LAN_RST_SM_FSM_FFd2_D,CLK_EXT,RESET,'0'); LAN_RST_SM_FSM_FFd2_D <= ((NOT LAN_RST_SM_FSM_FFd1 AND LAN_RST_SM_FSM_FFd3) OR (LAN_RST_SM_FSM_FFd2 AND NOT LAN_RST_SM_FSM_FFd3)); FDCPE_LAN_RST_SM_FSM_FFd3: FDCPE port map (LAN_RST_SM_FSM_FFd3,LAN_RST_SM_FSM_FFd3_D,CLK_EXT,RESET,'0'); LAN_RST_SM_FSM_FFd3_D <= LAN_RST_SM_FSM_FFd1 XOR LAN_RST_SM_FSM_FFd3_D <= LAN_RST_SM_FSM_FFd2; FTCPE_LAN_SM_FSM_FFd1: FTCPE port map (LAN_SM_FSM_FFd1,LAN_SM_FSM_FFd1_T,CLK_EXT,LAN_SM_RST,'0'); LAN_SM_FSM_FFd1_T <= ((NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd1 AND LAN_SM_FSM_FFd3) OR (LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd1 AND NOT LAN_SM_FSM_FFd3 AND NOT $OpTx$FX_DC$10)); FDCPE_LAN_SM_FSM_FFd2: FDCPE port map (LAN_SM_FSM_FFd2,LAN_SM_FSM_FFd2_D,CLK_EXT,LAN_SM_RST,'0'); LAN_SM_FSM_FFd2_D <= ((LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1 AND NOT LAN_SM_FSM_FFd3) OR (RW AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1 AND NOT LAN_SM_FSM_FFd3) OR (NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1 AND NOT LAN_SM_FSM_FFd3 AND NOT $OpTx$FX_DC$8)); FDCPE_LAN_SM_FSM_FFd3: FDCPE port map (LAN_SM_FSM_FFd3,LAN_SM_FSM_FFd3_D,CLK_EXT,LAN_SM_RST,'0'); LAN_SM_FSM_FFd3_D <= ((LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd1 AND LAN_SM_FSM_FFd3 AND NOT $OpTx$FX_DC$10) OR (NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3) OR (NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1 AND LAN_SM_FSM_FFd3) OR (RW AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd3 AND NOT $OpTx$FX_DC$8) OR (LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd1 AND NOT LAN_SM_FSM_FFd3 AND $OpTx$FX_DC$10)); FDCPE_LAN_SM_FSM_FFd4: FDCPE port map (LAN_SM_FSM_FFd4,LAN_SM_FSM_FFd4_D,CLK_EXT,LAN_SM_RST,'0'); LAN_SM_FSM_FFd4_D <= ((NOT RW AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd1 AND NOT LAN_SM_FSM_FFd3) OR (NOT LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd3) OR (LAN_SM_FSM_FFd1 AND LAN_SM_FSM_FFd3) OR (LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd1 AND NOT $OpTx$FX_DC$10) OR (NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1 AND NOT LAN_SM_FSM_FFd3)); FDCPE_LAN_SM_RST: FDCPE port map (LAN_SM_RST,LAN_SM_RST_D,NOT CLK_EXT,'0','0'); LAN_SM_RST_D <= ($OpTx$FX_DC$32 AND NOT BUF_CONFIG_READY AND Z3_ADR_1/Z3_ADR_1_SETF); LAN_WRH <= ((LAN_WR_RST AND NOT $OpTx$FX_DC$24) OR (LAN_WRH_S AND $OpTx$FX_DC$24)); FDCPE_LAN_WRH_S: FDCPE port map (LAN_WRH_S,LAN_WRH_S_D,CLK_EXT,LAN_SM_RST,'0'); LAN_WRH_S_D <= ((NOT LDS AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd3) OR (NOT DS0 AND NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1 AND LAN_SM_FSM_FFd3)); LAN_WRL <= ((LAN_WR_RST AND NOT $OpTx$FX_DC$24) OR (LAN_WRL_S AND $OpTx$FX_DC$24)); FDCPE_LAN_WRL_S: FDCPE port map (LAN_WRL_S,LAN_WRL_S_D,CLK_EXT,LAN_SM_RST,'0'); LAN_WRL_S_D <= ((NOT UDS AND NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd3) OR (NOT DS1 AND NOT LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1 AND LAN_SM_FSM_FFd3)); FDCPE_LAN_WR_RST: FDCPE port map (LAN_WR_RST,LAN_WR_RST_D,CLK_EXT,RESET,'0'); LAN_WR_RST_D <= (LAN_RST_SM_FSM_FFd2 AND LAN_RST_SM_FSM_FFd3); MTACK_I <= '0'; MTACK <= MTACK_I when MTACK_OE = '1' else 'Z'; MTACK_OE <= '0'; N0$BUF7/N0$BUF7_TRST <= ((FCS) OR (NOT AUTOCONFIG_ACCESS AND NOT CONFIG_READY AND NOT LAN_READY)); OVR_I <= '0'; OVR <= OVR_I when OVR_OE = '1' else 'Z'; OVR_OE <= NOT SLAVE; OWN_I <= '0'; OWN <= OWN_I when OWN_OE = '1' else 'Z'; OWN_OE <= '0'; ROM_B(0) <= '1'; ROM_B(1) <= '1'; ROM_OE <= '1'; FDCPE_SHUT_UP: FDCPE port map (SHUT_UP,'0',CLK_EXT,'0',NOT RESET,SHUT_UP_CE); SHUT_UP_CE <= (NOT RW AND NOT FCS AND NOT UDS AND NOT Z3_ADR(2) AND NOT Z3_ADR_1 AND Z3_ADR_0 AND NOT Z3_ADR(6) AND AUTOCONFIG_ACCESS AND NOT Z3_ADR(3) AND Z3_ADR(4) AND NOT Z3_ADR(5)); SLAVE <= ((FCS) OR (NOT LAN_ACCESS AND NOT AUTOCONFIG_ACCESS)); FDCPE_Z3_ADR2: FDCPE port map (Z3_ADR(2),A(4),NOT FCS,'0',NOT Z3_ADR_1/Z3_ADR_1_SETF); FDCPE_Z3_ADR3: FDCPE port map (Z3_ADR(3),A(5),NOT FCS,'0',NOT Z3_ADR_1/Z3_ADR_1_SETF); FDCPE_Z3_ADR4: FDCPE port map (Z3_ADR(4),A(6),NOT FCS,'0',NOT Z3_ADR_1/Z3_ADR_1_SETF); FDCPE_Z3_ADR5: FDCPE port map (Z3_ADR(5),A(7),NOT FCS,'0',NOT Z3_ADR_1/Z3_ADR_1_SETF); FDCPE_Z3_ADR6: FDCPE port map (Z3_ADR(6),A(8).PIN,NOT FCS,'0',NOT Z3_ADR_1/Z3_ADR_1_SETF); FDCPE_Z3_ADR7: FDCPE port map (Z3_ADR(7),A(9).PIN,NOT FCS,'0',NOT Z3_ADR_1/Z3_ADR_1_SETF); FDCPE_Z3_ADR8: FDCPE port map (Z3_ADR(8),A(10).PIN,NOT FCS,'0',NOT Z3_ADR_1/Z3_ADR_1_SETF); FDCPE_Z3_ADR9: FDCPE port map (Z3_ADR(9),A(11).PIN,NOT FCS,'0',NOT Z3_ADR_1/Z3_ADR_1_SETF); FDCPE_Z3_ADR10: FDCPE port map (Z3_ADR(10),A(12).PIN,NOT FCS,'0',NOT Z3_ADR_1/Z3_ADR_1_SETF); FDCPE_Z3_ADR11: FDCPE port map (Z3_ADR(11),A(13).PIN,NOT FCS,'0',NOT Z3_ADR_1/Z3_ADR_1_SETF); FDCPE_Z3_ADR12: FDCPE port map (Z3_ADR(12),A(14).PIN,NOT FCS,'0',NOT Z3_ADR_1/Z3_ADR_1_SETF); FDCPE_Z3_ADR13: FDCPE port map (Z3_ADR(13),A(15).PIN,NOT FCS,'0',NOT Z3_ADR_1/Z3_ADR_1_SETF); FDCPE_Z3_ADR_0: FDCPE port map (Z3_ADR_0,A(2),NOT FCS,'0',NOT Z3_ADR_1/Z3_ADR_1_SETF); FDCPE_Z3_ADR_1: FDCPE port map (Z3_ADR_1,A(3),NOT FCS,'0',NOT Z3_ADR_1/Z3_ADR_1_SETF); Z3_ADR_1/Z3_ADR_1_SETF <= (RESET AND BERR); FDCPE_Z3_A_LOW: FDCPE port map (Z3_A_LOW,Z3_A_LOW_D,CLK_EXT,LAN_SM_RST,'0'); Z3_A_LOW_D <= ((LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd1 AND LAN_SM_FSM_FFd3) OR (LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND LAN_SM_FSM_FFd3) OR (LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd1 AND NOT $OpTx$FX_DC$10) OR (LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1 AND NOT BUF_LAN_READY) OR (NOT LAN_SM_FSM_FFd4 AND NOT LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd3 AND $OpTx$FX_DC$8)); Z3_DATA(1)/Z3_DATA(1)_TRST <= (RW AND $OpTx$FX_DC$32); FDCPE_Z3_DATA16: FDCPE port map (Z3_DATA(16),Z3_DATA_D(16),CLK_EXT,'0',LAN_SM_RST,Z3_DATA_CE(16)); Z3_DATA_D(16) <= ((DQ_SWAP AND DQ(8).PIN) OR (NOT DQ_SWAP AND DQ(0).PIN)); Z3_DATA_CE(16) <= (LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1 AND LAN_SM_FSM_FFd3); FDCPE_Z3_DATA17: FDCPE port map (Z3_DATA(17),Z3_DATA_D(17),CLK_EXT,'0',LAN_SM_RST,Z3_DATA_CE(17)); Z3_DATA_D(17) <= ((DQ_SWAP AND DQ(9).PIN) OR (NOT DQ_SWAP AND DQ(1).PIN)); Z3_DATA_CE(17) <= (LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1 AND LAN_SM_FSM_FFd3); FDCPE_Z3_DATA18: FDCPE port map (Z3_DATA(18),Z3_DATA_D(18),CLK_EXT,'0',LAN_SM_RST,Z3_DATA_CE(18)); Z3_DATA_D(18) <= ((DQ_SWAP AND DQ(10).PIN) OR (NOT DQ_SWAP AND DQ(2).PIN)); Z3_DATA_CE(18) <= (LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1 AND LAN_SM_FSM_FFd3); FDCPE_Z3_DATA19: FDCPE port map (Z3_DATA(19),Z3_DATA_D(19),CLK_EXT,'0',LAN_SM_RST,Z3_DATA_CE(19)); Z3_DATA_D(19) <= ((DQ_SWAP AND DQ(11).PIN) OR (NOT DQ_SWAP AND DQ(3).PIN)); Z3_DATA_CE(19) <= (LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1 AND LAN_SM_FSM_FFd3); FDCPE_Z3_DATA20: FDCPE port map (Z3_DATA(20),Z3_DATA_D(20),CLK_EXT,'0',LAN_SM_RST,Z3_DATA_CE(20)); Z3_DATA_D(20) <= ((DQ_SWAP AND DQ(12).PIN) OR (NOT DQ_SWAP AND DQ(4).PIN)); Z3_DATA_CE(20) <= (LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1 AND LAN_SM_FSM_FFd3); FDCPE_Z3_DATA21: FDCPE port map (Z3_DATA(21),Z3_DATA_D(21),CLK_EXT,'0',LAN_SM_RST,Z3_DATA_CE(21)); Z3_DATA_D(21) <= ((DQ_SWAP AND DQ(13).PIN) OR (NOT DQ_SWAP AND DQ(5).PIN)); Z3_DATA_CE(21) <= (LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1 AND LAN_SM_FSM_FFd3); FDCPE_Z3_DATA22: FDCPE port map (Z3_DATA(22),Z3_DATA_D(22),CLK_EXT,'0',LAN_SM_RST,Z3_DATA_CE(22)); Z3_DATA_D(22) <= ((DQ_SWAP AND DQ(14).PIN) OR (NOT DQ_SWAP AND DQ(6).PIN)); Z3_DATA_CE(22) <= (LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1 AND LAN_SM_FSM_FFd3); FDCPE_Z3_DATA23: FDCPE port map (Z3_DATA(23),Z3_DATA_D(23),CLK_EXT,'0',LAN_SM_RST,Z3_DATA_CE(23)); Z3_DATA_D(23) <= ((DQ_SWAP AND DQ(15).PIN) OR (NOT DQ_SWAP AND DQ(7).PIN)); Z3_DATA_CE(23) <= (LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1 AND LAN_SM_FSM_FFd3); FDCPE_Z3_DATA24: FDCPE port map (Z3_DATA(24),Z3_DATA_D(24),CLK_EXT,'0',LAN_SM_RST,Z3_DATA_CE(24)); Z3_DATA_D(24) <= ((DQ_SWAP AND DQ(0).PIN) OR (NOT DQ_SWAP AND DQ(8).PIN)); Z3_DATA_CE(24) <= (LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1 AND LAN_SM_FSM_FFd3); FDCPE_Z3_DATA25: FDCPE port map (Z3_DATA(25),Z3_DATA_D(25),CLK_EXT,'0',LAN_SM_RST,Z3_DATA_CE(25)); Z3_DATA_D(25) <= ((DQ_SWAP AND DQ(1).PIN) OR (NOT DQ_SWAP AND DQ(9).PIN)); Z3_DATA_CE(25) <= (LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1 AND LAN_SM_FSM_FFd3); FDCPE_Z3_DATA26: FDCPE port map (Z3_DATA(26),Z3_DATA_D(26),CLK_EXT,'0',LAN_SM_RST,Z3_DATA_CE(26)); Z3_DATA_D(26) <= ((DQ_SWAP AND DQ(2).PIN) OR (NOT DQ_SWAP AND DQ(10).PIN)); Z3_DATA_CE(26) <= (LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1 AND LAN_SM_FSM_FFd3); FDCPE_Z3_DATA27: FDCPE port map (Z3_DATA(27),Z3_DATA_D(27),CLK_EXT,'0',LAN_SM_RST,Z3_DATA_CE(27)); Z3_DATA_D(27) <= ((DQ_SWAP AND DQ(3).PIN) OR (NOT DQ_SWAP AND DQ(11).PIN)); Z3_DATA_CE(27) <= (LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1 AND LAN_SM_FSM_FFd3); FDCPE_Z3_DATA28: FDCPE port map (Z3_DATA(28),Z3_DATA_D(28),CLK_EXT,'0',LAN_SM_RST,Z3_DATA_CE(28)); Z3_DATA_D(28) <= ((DQ_SWAP AND DQ(4).PIN) OR (NOT DQ_SWAP AND DQ(12).PIN)); Z3_DATA_CE(28) <= (LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1 AND LAN_SM_FSM_FFd3); FDCPE_Z3_DATA29: FDCPE port map (Z3_DATA(29),Z3_DATA_D(29),CLK_EXT,'0',LAN_SM_RST,Z3_DATA_CE(29)); Z3_DATA_D(29) <= ((DQ_SWAP AND DQ(5).PIN) OR (NOT DQ_SWAP AND DQ(13).PIN)); Z3_DATA_CE(29) <= (LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1 AND LAN_SM_FSM_FFd3); FDCPE_Z3_DATA30: FDCPE port map (Z3_DATA(30),Z3_DATA_D(30),CLK_EXT,'0',LAN_SM_RST,Z3_DATA_CE(30)); Z3_DATA_D(30) <= ((DQ_SWAP AND DQ(6).PIN) OR (NOT DQ_SWAP AND DQ(14).PIN)); Z3_DATA_CE(30) <= (LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1 AND LAN_SM_FSM_FFd3); FDCPE_Z3_DATA31: FDCPE port map (Z3_DATA(31),Z3_DATA_D(31),CLK_EXT,'0',LAN_SM_RST,Z3_DATA_CE(31)); Z3_DATA_D(31) <= ((DQ_SWAP AND DQ(7).PIN) OR (NOT DQ_SWAP AND DQ(15).PIN)); Z3_DATA_CE(31) <= (LAN_SM_FSM_FFd4 AND LAN_SM_FSM_FFd2 AND NOT LAN_SM_FSM_FFd1 AND LAN_SM_FSM_FFd3); Register Legend: FDCPE (Q,D,C,CLR,PRE,CE); FTCPE (Q,D,C,CLR,PRE,CE); LDCP (Q,D,G,CLR,PRE); ****************************** Device Pin Out ***************************** Device : XC95288XL-10-TQ144 Pin Signal Pin Signal No. Name No. Name 1 VCC 73 VCC 2 D<0> 74 A<15> 3 A_LAN<1> 75 AUTOBOOT_OFF 4 A_LAN<0> 76 LAN_WRL 5 A_LAN<3> 77 FCS 6 A_LAN<2> 78 DS1 7 A_LAN<5> 79 Z3 8 VCC 80 TIE 9 A_LAN<4> 81 UDS 10 A_LAN<7> 82 LDS 11 A_LAN<6> 83 RW 12 LAN_CFG<1> 84 VCC 13 LAN_CFG<3> 85 DTACK 14 D<6> 86 A<23> 15 D<3> 87 A<22> 16 D<7> 88 A<21> 17 D<1> 89 GND 18 GND 90 GND 19 D<8> 91 A<20> 20 D<5> 92 A<19> 21 D<4> 93 DS0 22 IDE_CS<0> 94 A<18> 23 IDE_CS<1> 95 A<17> 24 IDE_A<0> 96 MTACK 25 IDE_A<2> 97 A<16> 26 IDE_A<1> 98 BERR 27 IDE_R 99 GND 28 IDE_W 100 OVR 29 GND 101 TIE 30 CLK_EXT 102 TIE 31 TIE 103 TIE 32 INT_OUT 104 CFIN 33 TIE 105 CFOUT 34 CP_CS 106 SLAVE 35 ROM_OE 107 OWN 36 GND 108 GND 37 VCC 109 VCC 38 TIE 110 LAN_CFG<4> 39 D<2> 111 LAN_INT 40 D<9> 112 DQ<15> 41 D<10> 113 DQ<13> 42 VCC 114 GND 43 D<11> 115 DQ<11> 44 D<12> 116 DQ<9> 45 D<13> 117 DQ<1> 46 D<14> 118 DQ<0> 47 GND 119 DQ<3> 48 D<15> 120 DQ<2> 49 A<5> 121 DQ<5> 50 A<4> 122 TDO 51 A<6> 123 GND 52 A<3> 124 DQ<4> 53 A<7> 125 DQ<7> 54 A<2> 126 DQ<6> 55 VCC 127 VCC 56 A<8> 128 DQ<8> 57 TIE 129 DQ<10> 58 A<9> 130 DQ<12> 59 A<10> 131 DQ<14> 60 A<11> 132 LAN_WRH 61 A<12> 133 LAN_CS 62 GND 134 LAN_RD 63 TDI 135 LAN_CFG<2> 64 A<13> 136 A_LAN<12> 65 TMS 137 A_LAN<13> 66 A<14> 138 A_LAN<10> 67 TCK 139 A_LAN<11> 68 ROM_B<0> 140 A_LAN<8> 69 ROM_B<1> 141 VCC 70 CP_WE 142 A_LAN<9> 71 CP_RD 143 RESET 72 GND 144 GND Legend : NC = Not Connected, unbonded pin PGND = Unused I/O configured as additional Ground pin TIE = Unused I/O floating -- must tie to VCC, GND or other signal KPR = Unused I/O with weak keeper (leave unconnected) VCC = Dedicated Power Pin GND = Dedicated Ground Pin TDI = Test Data In, JTAG pin TDO = Test Data Out, JTAG pin TCK = Test Clock, JTAG pin TMS = Test Mode Select, JTAG pin PROHIBITED = User reserved pin **************************** Compiler Options **************************** Following is a list of all global compiler options used by the fitter run. Device(s) Specified : xc95288xl-10-TQ144 Optimization Method : DENSITY Multi-Level Logic Optimization : ON Ignore Timing Specifications : OFF Default Register Power Up Value : LOW Keep User Location Constraints : ON What-You-See-Is-What-You-Get : OFF Exhaustive Fitting : OFF Keep Unused Inputs : OFF Slew Rate : FAST Power Mode : STD Ground on Unused IOs : OFF Set I/O Pin Termination : FLOAT Global Clock Optimization : ON Global Set/Reset Optimization : ON Global Ouput Enable Optimization : ON Input Limit : 54 Pterm Limit : 35